1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Define parameter passing and return registers. */
1623 static int const x86_64_int_parameter_registers[6] =
1625 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1628 static int const x86_64_ms_abi_int_parameter_registers[4] =
1630 CX_REG, DX_REG, R8_REG, R9_REG
1633 static int const x86_64_int_return_registers[4] =
1635 AX_REG, DX_REG, DI_REG, SI_REG
1638 /* Define the structure for the machine field in struct function. */
1640 struct stack_local_entry GTY(())
1642 unsigned short mode;
1645 struct stack_local_entry *next;
1648 /* Structure describing stack frame layout.
1649 Stack grows downward:
1655 saved frame pointer if frame_pointer_needed
1656 <- HARD_FRAME_POINTER
1665 [va_arg registers] (
1666 > to_allocate <- FRAME_POINTER
1678 HOST_WIDE_INT frame;
1680 int outgoing_arguments_size;
1683 HOST_WIDE_INT to_allocate;
1684 /* The offsets relative to ARG_POINTER. */
1685 HOST_WIDE_INT frame_pointer_offset;
1686 HOST_WIDE_INT hard_frame_pointer_offset;
1687 HOST_WIDE_INT stack_pointer_offset;
1689 /* When save_regs_using_mov is set, emit prologue using
1690 move instead of push instructions. */
1691 bool save_regs_using_mov;
1694 /* Code model option. */
1695 enum cmodel ix86_cmodel;
1697 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1699 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1701 /* Which unit we are generating floating point math for. */
1702 enum fpmath_unit ix86_fpmath;
1704 /* Which cpu are we scheduling for. */
1705 enum attr_cpu ix86_schedule;
1707 /* Which cpu are we optimizing for. */
1708 enum processor_type ix86_tune;
1710 /* Which instruction set architecture to use. */
1711 enum processor_type ix86_arch;
1713 /* true if sse prefetch instruction is not NOOP. */
1714 int x86_prefetch_sse;
1716 /* ix86_regparm_string as a number */
1717 static int ix86_regparm;
1719 /* -mstackrealign option */
1720 extern int ix86_force_align_arg_pointer;
1721 static const char ix86_force_align_arg_pointer_string[]
1722 = "force_align_arg_pointer";
1724 static rtx (*ix86_gen_leave) (void);
1725 static rtx (*ix86_gen_pop1) (rtx);
1726 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1728 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1729 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1730 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1731 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1733 /* Preferred alignment for stack boundary in bits. */
1734 unsigned int ix86_preferred_stack_boundary;
1736 /* Alignment for incoming stack boundary in bits specified at
1738 static unsigned int ix86_user_incoming_stack_boundary;
1740 /* Default alignment for incoming stack boundary in bits. */
1741 static unsigned int ix86_default_incoming_stack_boundary;
1743 /* Alignment for incoming stack boundary in bits. */
1744 unsigned int ix86_incoming_stack_boundary;
1746 /* Values 1-5: see jump.c */
1747 int ix86_branch_cost;
1749 /* Calling abi specific va_list type nodes. */
1750 static GTY(()) tree sysv_va_list_type_node;
1751 static GTY(()) tree ms_va_list_type_node;
1753 /* Variables which are this size or smaller are put in the data/bss
1754 or ldata/lbss sections. */
1756 int ix86_section_threshold = 65536;
1758 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1759 char internal_label_prefix[16];
1760 int internal_label_prefix_len;
1762 /* Fence to use after loop using movnt. */
1765 /* Register class used for passing given 64bit part of the argument.
1766 These represent classes as documented by the PS ABI, with the exception
1767 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1768 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1770 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1771 whenever possible (upper half does contain padding). */
1772 enum x86_64_reg_class
1775 X86_64_INTEGER_CLASS,
1776 X86_64_INTEGERSI_CLASS,
1783 X86_64_COMPLEX_X87_CLASS,
1787 #define MAX_CLASSES 4
1789 /* Table of constants used by fldpi, fldln2, etc.... */
1790 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1791 static bool ext_80387_constants_init = 0;
1794 static struct machine_function * ix86_init_machine_status (void);
1795 static rtx ix86_function_value (const_tree, const_tree, bool);
1796 static int ix86_function_regparm (const_tree, const_tree);
1797 static void ix86_compute_frame_layout (struct ix86_frame *);
1798 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1800 static void ix86_add_new_builtins (int);
1802 enum ix86_function_specific_strings
1804 IX86_FUNCTION_SPECIFIC_ARCH,
1805 IX86_FUNCTION_SPECIFIC_TUNE,
1806 IX86_FUNCTION_SPECIFIC_FPMATH,
1807 IX86_FUNCTION_SPECIFIC_MAX
1810 static char *ix86_target_string (int, int, const char *, const char *,
1811 const char *, bool);
1812 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1813 static void ix86_function_specific_save (struct cl_target_option *);
1814 static void ix86_function_specific_restore (struct cl_target_option *);
1815 static void ix86_function_specific_print (FILE *, int,
1816 struct cl_target_option *);
1817 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1818 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1819 static bool ix86_can_inline_p (tree, tree);
1820 static void ix86_set_current_function (tree);
1823 /* The svr4 ABI for the i386 says that records and unions are returned
1825 #ifndef DEFAULT_PCC_STRUCT_RETURN
1826 #define DEFAULT_PCC_STRUCT_RETURN 1
1829 /* Whether -mtune= or -march= were specified */
1830 static int ix86_tune_defaulted;
1831 static int ix86_arch_specified;
1833 /* Bit flags that specify the ISA we are compiling for. */
1834 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1836 /* A mask of ix86_isa_flags that includes bit X if X
1837 was set or cleared on the command line. */
1838 static int ix86_isa_flags_explicit;
1840 /* Define a set of ISAs which are available when a given ISA is
1841 enabled. MMX and SSE ISAs are handled separately. */
1843 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1844 #define OPTION_MASK_ISA_3DNOW_SET \
1845 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1847 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1848 #define OPTION_MASK_ISA_SSE2_SET \
1849 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1850 #define OPTION_MASK_ISA_SSE3_SET \
1851 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1852 #define OPTION_MASK_ISA_SSSE3_SET \
1853 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1854 #define OPTION_MASK_ISA_SSE4_1_SET \
1855 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1856 #define OPTION_MASK_ISA_SSE4_2_SET \
1857 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1858 #define OPTION_MASK_ISA_AVX_SET \
1859 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1860 #define OPTION_MASK_ISA_FMA_SET \
1861 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1863 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1865 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1867 #define OPTION_MASK_ISA_SSE4A_SET \
1868 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1869 #define OPTION_MASK_ISA_SSE5_SET \
1870 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1872 /* AES and PCLMUL need SSE2 because they use xmm registers */
1873 #define OPTION_MASK_ISA_AES_SET \
1874 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1875 #define OPTION_MASK_ISA_PCLMUL_SET \
1876 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1878 #define OPTION_MASK_ISA_ABM_SET \
1879 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1880 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1881 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1882 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1884 /* Define a set of ISAs which aren't available when a given ISA is
1885 disabled. MMX and SSE ISAs are handled separately. */
1887 #define OPTION_MASK_ISA_MMX_UNSET \
1888 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1889 #define OPTION_MASK_ISA_3DNOW_UNSET \
1890 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1891 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1893 #define OPTION_MASK_ISA_SSE_UNSET \
1894 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1895 #define OPTION_MASK_ISA_SSE2_UNSET \
1896 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1897 #define OPTION_MASK_ISA_SSE3_UNSET \
1898 (OPTION_MASK_ISA_SSE3 \
1899 | OPTION_MASK_ISA_SSSE3_UNSET \
1900 | OPTION_MASK_ISA_SSE4A_UNSET )
1901 #define OPTION_MASK_ISA_SSSE3_UNSET \
1902 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1903 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1904 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1905 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1906 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1907 #define OPTION_MASK_ISA_AVX_UNSET \
1908 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1909 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1911 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1913 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1915 #define OPTION_MASK_ISA_SSE4A_UNSET \
1916 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1917 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1918 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1919 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1920 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1921 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1922 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1923 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1925 /* Vectorization library interface and handlers. */
1926 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1927 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1928 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1930 /* Processor target table, indexed by processor number */
1933 const struct processor_costs *cost; /* Processor costs */
1934 const int align_loop; /* Default alignments. */
1935 const int align_loop_max_skip;
1936 const int align_jump;
1937 const int align_jump_max_skip;
1938 const int align_func;
1941 static const struct ptt processor_target_table[PROCESSOR_max] =
1943 {&i386_cost, 4, 3, 4, 3, 4},
1944 {&i486_cost, 16, 15, 16, 15, 16},
1945 {&pentium_cost, 16, 7, 16, 7, 16},
1946 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1947 {&geode_cost, 0, 0, 0, 0, 0},
1948 {&k6_cost, 32, 7, 32, 7, 32},
1949 {&athlon_cost, 16, 7, 16, 7, 16},
1950 {&pentium4_cost, 0, 0, 0, 0, 0},
1951 {&k8_cost, 16, 7, 16, 7, 16},
1952 {&nocona_cost, 0, 0, 0, 0, 0},
1953 {&core2_cost, 16, 10, 16, 10, 16},
1954 {&generic32_cost, 16, 7, 16, 7, 16},
1955 {&generic64_cost, 16, 10, 16, 10, 16},
1956 {&amdfam10_cost, 32, 24, 32, 7, 32}
1959 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1984 /* Implement TARGET_HANDLE_OPTION. */
1987 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1994 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1995 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1999 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2007 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2008 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2012 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2023 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2024 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2028 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2036 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2037 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2041 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2049 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2050 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2054 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2062 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2063 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2067 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2075 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2076 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2080 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2088 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2089 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2093 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2101 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2102 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2106 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2114 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2115 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2119 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2130 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2137 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2138 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2142 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2150 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2151 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2155 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2163 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2164 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2168 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2176 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2177 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2181 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2189 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2190 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2194 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2202 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2203 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2207 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2215 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2216 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2220 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2228 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2229 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2233 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2243 /* Return a string the documents the current -m options. The caller is
2244 responsible for freeing the string. */
2247 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2248 const char *fpmath, bool add_nl_p)
2250 struct ix86_target_opts
2252 const char *option; /* option string */
2253 int mask; /* isa mask options */
2256 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2257 preceding options while match those first. */
2258 static struct ix86_target_opts isa_opts[] =
2260 { "-m64", OPTION_MASK_ISA_64BIT },
2261 { "-msse5", OPTION_MASK_ISA_SSE5 },
2262 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2263 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2264 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2265 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2266 { "-msse3", OPTION_MASK_ISA_SSE3 },
2267 { "-msse2", OPTION_MASK_ISA_SSE2 },
2268 { "-msse", OPTION_MASK_ISA_SSE },
2269 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2270 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2271 { "-mmmx", OPTION_MASK_ISA_MMX },
2272 { "-mabm", OPTION_MASK_ISA_ABM },
2273 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2274 { "-maes", OPTION_MASK_ISA_AES },
2275 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2279 static struct ix86_target_opts flag_opts[] =
2281 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2282 { "-m80387", MASK_80387 },
2283 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2284 { "-malign-double", MASK_ALIGN_DOUBLE },
2285 { "-mcld", MASK_CLD },
2286 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2287 { "-mieee-fp", MASK_IEEE_FP },
2288 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2289 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2290 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2291 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2292 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2293 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2294 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2295 { "-mno-red-zone", MASK_NO_RED_ZONE },
2296 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2297 { "-mrecip", MASK_RECIP },
2298 { "-mrtd", MASK_RTD },
2299 { "-msseregparm", MASK_SSEREGPARM },
2300 { "-mstack-arg-probe", MASK_STACK_PROBE },
2301 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2304 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2307 char target_other[40];
2316 memset (opts, '\0', sizeof (opts));
2318 /* Add -march= option. */
2321 opts[num][0] = "-march=";
2322 opts[num++][1] = arch;
2325 /* Add -mtune= option. */
2328 opts[num][0] = "-mtune=";
2329 opts[num++][1] = tune;
2332 /* Pick out the options in isa options. */
2333 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2335 if ((isa & isa_opts[i].mask) != 0)
2337 opts[num++][0] = isa_opts[i].option;
2338 isa &= ~ isa_opts[i].mask;
2342 if (isa && add_nl_p)
2344 opts[num++][0] = isa_other;
2345 sprintf (isa_other, "(other isa: 0x%x)", isa);
2348 /* Add flag options. */
2349 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2351 if ((flags & flag_opts[i].mask) != 0)
2353 opts[num++][0] = flag_opts[i].option;
2354 flags &= ~ flag_opts[i].mask;
2358 if (flags && add_nl_p)
2360 opts[num++][0] = target_other;
2361 sprintf (target_other, "(other flags: 0x%x)", isa);
2364 /* Add -fpmath= option. */
2367 opts[num][0] = "-mfpmath=";
2368 opts[num++][1] = fpmath;
2375 gcc_assert (num < ARRAY_SIZE (opts));
2377 /* Size the string. */
2379 sep_len = (add_nl_p) ? 3 : 1;
2380 for (i = 0; i < num; i++)
2383 for (j = 0; j < 2; j++)
2385 len += strlen (opts[i][j]);
2388 /* Build the string. */
2389 ret = ptr = (char *) xmalloc (len);
2392 for (i = 0; i < num; i++)
2396 for (j = 0; j < 2; j++)
2397 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2404 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2412 for (j = 0; j < 2; j++)
2415 memcpy (ptr, opts[i][j], len2[j]);
2417 line_len += len2[j];
2422 gcc_assert (ret + len >= ptr);
2427 /* Function that is callable from the debugger to print the current
2430 ix86_debug_options (void)
2432 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2433 ix86_arch_string, ix86_tune_string,
2434 ix86_fpmath_string, true);
2438 fprintf (stderr, "%s\n\n", opts);
2442 fprintf (stderr, "<no options>\n\n");
2447 /* Sometimes certain combinations of command options do not make
2448 sense on a particular target machine. You can define a macro
2449 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2450 defined, is executed once just after all the command options have
2453 Don't use this macro to turn on various extra optimizations for
2454 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 override_options (bool main_args_p)
2460 unsigned int ix86_arch_mask, ix86_tune_mask;
2465 /* Comes from final.c -- no real reason to change it. */
2466 #define MAX_CODE_ALIGN 16
2474 PTA_PREFETCH_SSE = 1 << 4,
2476 PTA_3DNOW_A = 1 << 6,
2480 PTA_POPCNT = 1 << 10,
2482 PTA_SSE4A = 1 << 12,
2483 PTA_NO_SAHF = 1 << 13,
2484 PTA_SSE4_1 = 1 << 14,
2485 PTA_SSE4_2 = 1 << 15,
2488 PTA_PCLMUL = 1 << 18,
2495 const char *const name; /* processor name or nickname. */
2496 const enum processor_type processor;
2497 const enum attr_cpu schedule;
2498 const unsigned /*enum pta_flags*/ flags;
2500 const processor_alias_table[] =
2502 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2503 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2504 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2505 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2506 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2507 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2508 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2509 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2510 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2511 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2512 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2513 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2514 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2516 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2518 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2519 PTA_MMX | PTA_SSE | PTA_SSE2},
2520 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2521 PTA_MMX |PTA_SSE | PTA_SSE2},
2522 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2523 PTA_MMX | PTA_SSE | PTA_SSE2},
2524 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2525 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2526 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2527 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 | PTA_CX16 | PTA_NO_SAHF},
2529 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2530 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2531 | PTA_SSSE3 | PTA_CX16},
2532 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2533 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2534 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2535 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2536 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2537 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2538 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2539 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2540 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2541 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2542 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2543 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2544 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2545 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2546 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2547 {"x86-64", PROCESSOR_K8, CPU_K8,
2548 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2549 {"k8", PROCESSOR_K8, CPU_K8,
2550 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2551 | PTA_SSE2 | PTA_NO_SAHF},
2552 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2553 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2554 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2555 {"opteron", PROCESSOR_K8, CPU_K8,
2556 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2557 | PTA_SSE2 | PTA_NO_SAHF},
2558 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2559 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2560 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2561 {"athlon64", PROCESSOR_K8, CPU_K8,
2562 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2563 | PTA_SSE2 | PTA_NO_SAHF},
2564 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2565 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2566 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2567 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2568 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2569 | PTA_SSE2 | PTA_NO_SAHF},
2570 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2571 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2572 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2573 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2574 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2575 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2576 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2577 0 /* flags are only used for -march switch. */ },
2578 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2579 PTA_64BIT /* flags are only used for -march switch. */ },
2582 int const pta_size = ARRAY_SIZE (processor_alias_table);
2584 /* Set up prefix/suffix so the error messages refer to either the command
2585 line argument, or the attribute(target). */
2594 prefix = "option(\"";
2599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2600 SUBTARGET_OVERRIDE_OPTIONS;
2603 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2604 SUBSUBTARGET_OVERRIDE_OPTIONS;
2607 /* -fPIC is the default for x86_64. */
2608 if (TARGET_MACHO && TARGET_64BIT)
2611 /* Set the default values for switches whose default depends on TARGET_64BIT
2612 in case they weren't overwritten by command line options. */
2615 /* Mach-O doesn't support omitting the frame pointer for now. */
2616 if (flag_omit_frame_pointer == 2)
2617 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2618 if (flag_asynchronous_unwind_tables == 2)
2619 flag_asynchronous_unwind_tables = 1;
2620 if (flag_pcc_struct_return == 2)
2621 flag_pcc_struct_return = 0;
2625 if (flag_omit_frame_pointer == 2)
2626 flag_omit_frame_pointer = 0;
2627 if (flag_asynchronous_unwind_tables == 2)
2628 flag_asynchronous_unwind_tables = 0;
2629 if (flag_pcc_struct_return == 2)
2630 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2633 /* Need to check -mtune=generic first. */
2634 if (ix86_tune_string)
2636 if (!strcmp (ix86_tune_string, "generic")
2637 || !strcmp (ix86_tune_string, "i686")
2638 /* As special support for cross compilers we read -mtune=native
2639 as -mtune=generic. With native compilers we won't see the
2640 -mtune=native, as it was changed by the driver. */
2641 || !strcmp (ix86_tune_string, "native"))
2644 ix86_tune_string = "generic64";
2646 ix86_tune_string = "generic32";
2648 /* If this call is for setting the option attribute, allow the
2649 generic32/generic64 that was previously set. */
2650 else if (!main_args_p
2651 && (!strcmp (ix86_tune_string, "generic32")
2652 || !strcmp (ix86_tune_string, "generic64")))
2654 else if (!strncmp (ix86_tune_string, "generic", 7))
2655 error ("bad value (%s) for %stune=%s %s",
2656 ix86_tune_string, prefix, suffix, sw);
2660 if (ix86_arch_string)
2661 ix86_tune_string = ix86_arch_string;
2662 if (!ix86_tune_string)
2664 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2665 ix86_tune_defaulted = 1;
2668 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2669 need to use a sensible tune option. */
2670 if (!strcmp (ix86_tune_string, "generic")
2671 || !strcmp (ix86_tune_string, "x86-64")
2672 || !strcmp (ix86_tune_string, "i686"))
2675 ix86_tune_string = "generic64";
2677 ix86_tune_string = "generic32";
2680 if (ix86_stringop_string)
2682 if (!strcmp (ix86_stringop_string, "rep_byte"))
2683 stringop_alg = rep_prefix_1_byte;
2684 else if (!strcmp (ix86_stringop_string, "libcall"))
2685 stringop_alg = libcall;
2686 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2687 stringop_alg = rep_prefix_4_byte;
2688 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2690 /* rep; movq isn't available in 32-bit code. */
2691 stringop_alg = rep_prefix_8_byte;
2692 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2693 stringop_alg = loop_1_byte;
2694 else if (!strcmp (ix86_stringop_string, "loop"))
2695 stringop_alg = loop;
2696 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2697 stringop_alg = unrolled_loop;
2699 error ("bad value (%s) for %sstringop-strategy=%s %s",
2700 ix86_stringop_string, prefix, suffix, sw);
2702 if (!strcmp (ix86_tune_string, "x86-64"))
2703 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2704 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2705 prefix, suffix, prefix, suffix, prefix, suffix);
2707 if (!ix86_arch_string)
2708 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2710 ix86_arch_specified = 1;
2712 if (!strcmp (ix86_arch_string, "generic"))
2713 error ("generic CPU can be used only for %stune=%s %s",
2714 prefix, suffix, sw);
2715 if (!strncmp (ix86_arch_string, "generic", 7))
2716 error ("bad value (%s) for %sarch=%s %s",
2717 ix86_arch_string, prefix, suffix, sw);
2719 if (ix86_cmodel_string != 0)
2721 if (!strcmp (ix86_cmodel_string, "small"))
2722 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2723 else if (!strcmp (ix86_cmodel_string, "medium"))
2724 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2725 else if (!strcmp (ix86_cmodel_string, "large"))
2726 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2728 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2729 else if (!strcmp (ix86_cmodel_string, "32"))
2730 ix86_cmodel = CM_32;
2731 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2732 ix86_cmodel = CM_KERNEL;
2734 error ("bad value (%s) for %scmodel=%s %s",
2735 ix86_cmodel_string, prefix, suffix, sw);
2739 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2740 use of rip-relative addressing. This eliminates fixups that
2741 would otherwise be needed if this object is to be placed in a
2742 DLL, and is essentially just as efficient as direct addressing. */
2743 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2744 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2745 else if (TARGET_64BIT)
2746 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2748 ix86_cmodel = CM_32;
2750 if (ix86_asm_string != 0)
2753 && !strcmp (ix86_asm_string, "intel"))
2754 ix86_asm_dialect = ASM_INTEL;
2755 else if (!strcmp (ix86_asm_string, "att"))
2756 ix86_asm_dialect = ASM_ATT;
2758 error ("bad value (%s) for %sasm=%s %s",
2759 ix86_asm_string, prefix, suffix, sw);
2761 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2762 error ("code model %qs not supported in the %s bit mode",
2763 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2764 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2765 sorry ("%i-bit mode not compiled in",
2766 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2768 for (i = 0; i < pta_size; i++)
2769 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2771 ix86_schedule = processor_alias_table[i].schedule;
2772 ix86_arch = processor_alias_table[i].processor;
2773 /* Default cpu tuning to the architecture. */
2774 ix86_tune = ix86_arch;
2776 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2777 error ("CPU you selected does not support x86-64 "
2780 if (processor_alias_table[i].flags & PTA_MMX
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2782 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2783 if (processor_alias_table[i].flags & PTA_3DNOW
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2785 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2786 if (processor_alias_table[i].flags & PTA_3DNOW_A
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2788 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2789 if (processor_alias_table[i].flags & PTA_SSE
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2791 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2792 if (processor_alias_table[i].flags & PTA_SSE2
2793 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2794 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2795 if (processor_alias_table[i].flags & PTA_SSE3
2796 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2797 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2798 if (processor_alias_table[i].flags & PTA_SSSE3
2799 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2800 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2801 if (processor_alias_table[i].flags & PTA_SSE4_1
2802 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2803 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2804 if (processor_alias_table[i].flags & PTA_SSE4_2
2805 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2806 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2807 if (processor_alias_table[i].flags & PTA_AVX
2808 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2809 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2810 if (processor_alias_table[i].flags & PTA_FMA
2811 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2812 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2813 if (processor_alias_table[i].flags & PTA_SSE4A
2814 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2815 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2816 if (processor_alias_table[i].flags & PTA_SSE5
2817 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2818 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2819 if (processor_alias_table[i].flags & PTA_ABM
2820 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2821 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2822 if (processor_alias_table[i].flags & PTA_CX16
2823 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2824 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2825 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2826 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2827 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2828 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2829 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2830 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2831 if (processor_alias_table[i].flags & PTA_AES
2832 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2833 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2834 if (processor_alias_table[i].flags & PTA_PCLMUL
2835 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2836 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2837 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2838 x86_prefetch_sse = true;
2844 error ("bad value (%s) for %sarch=%s %s",
2845 ix86_arch_string, prefix, suffix, sw);
2847 ix86_arch_mask = 1u << ix86_arch;
2848 for (i = 0; i < X86_ARCH_LAST; ++i)
2849 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2851 for (i = 0; i < pta_size; i++)
2852 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2854 ix86_schedule = processor_alias_table[i].schedule;
2855 ix86_tune = processor_alias_table[i].processor;
2856 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2858 if (ix86_tune_defaulted)
2860 ix86_tune_string = "x86-64";
2861 for (i = 0; i < pta_size; i++)
2862 if (! strcmp (ix86_tune_string,
2863 processor_alias_table[i].name))
2865 ix86_schedule = processor_alias_table[i].schedule;
2866 ix86_tune = processor_alias_table[i].processor;
2869 error ("CPU you selected does not support x86-64 "
2872 /* Intel CPUs have always interpreted SSE prefetch instructions as
2873 NOPs; so, we can enable SSE prefetch instructions even when
2874 -mtune (rather than -march) points us to a processor that has them.
2875 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2876 higher processors. */
2878 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2879 x86_prefetch_sse = true;
2883 error ("bad value (%s) for %stune=%s %s",
2884 ix86_tune_string, prefix, suffix, sw);
2886 ix86_tune_mask = 1u << ix86_tune;
2887 for (i = 0; i < X86_TUNE_LAST; ++i)
2888 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2891 ix86_cost = &ix86_size_cost;
2893 ix86_cost = processor_target_table[ix86_tune].cost;
2895 /* Arrange to set up i386_stack_locals for all functions. */
2896 init_machine_status = ix86_init_machine_status;
2898 /* Validate -mregparm= value. */
2899 if (ix86_regparm_string)
2902 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2903 i = atoi (ix86_regparm_string);
2904 if (i < 0 || i > REGPARM_MAX)
2905 error ("%sregparm=%d%s is not between 0 and %d",
2906 prefix, i, suffix, REGPARM_MAX);
2911 ix86_regparm = REGPARM_MAX;
2913 /* If the user has provided any of the -malign-* options,
2914 warn and use that value only if -falign-* is not set.
2915 Remove this code in GCC 3.2 or later. */
2916 if (ix86_align_loops_string)
2918 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2919 prefix, suffix, suffix);
2920 if (align_loops == 0)
2922 i = atoi (ix86_align_loops_string);
2923 if (i < 0 || i > MAX_CODE_ALIGN)
2924 error ("%salign-loops=%d%s is not between 0 and %d",
2925 prefix, i, suffix, MAX_CODE_ALIGN);
2927 align_loops = 1 << i;
2931 if (ix86_align_jumps_string)
2933 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2934 prefix, suffix, suffix);
2935 if (align_jumps == 0)
2937 i = atoi (ix86_align_jumps_string);
2938 if (i < 0 || i > MAX_CODE_ALIGN)
2939 error ("%salign-loops=%d%s is not between 0 and %d",
2940 prefix, i, suffix, MAX_CODE_ALIGN);
2942 align_jumps = 1 << i;
2946 if (ix86_align_funcs_string)
2948 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2949 prefix, suffix, suffix);
2950 if (align_functions == 0)
2952 i = atoi (ix86_align_funcs_string);
2953 if (i < 0 || i > MAX_CODE_ALIGN)
2954 error ("%salign-loops=%d%s is not between 0 and %d",
2955 prefix, i, suffix, MAX_CODE_ALIGN);
2957 align_functions = 1 << i;
2961 /* Default align_* from the processor table. */
2962 if (align_loops == 0)
2964 align_loops = processor_target_table[ix86_tune].align_loop;
2965 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2967 if (align_jumps == 0)
2969 align_jumps = processor_target_table[ix86_tune].align_jump;
2970 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2972 if (align_functions == 0)
2974 align_functions = processor_target_table[ix86_tune].align_func;
2977 /* Validate -mbranch-cost= value, or provide default. */
2978 ix86_branch_cost = ix86_cost->branch_cost;
2979 if (ix86_branch_cost_string)
2981 i = atoi (ix86_branch_cost_string);
2983 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2985 ix86_branch_cost = i;
2987 if (ix86_section_threshold_string)
2989 i = atoi (ix86_section_threshold_string);
2991 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2993 ix86_section_threshold = i;
2996 if (ix86_tls_dialect_string)
2998 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2999 ix86_tls_dialect = TLS_DIALECT_GNU;
3000 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3001 ix86_tls_dialect = TLS_DIALECT_GNU2;
3002 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3003 ix86_tls_dialect = TLS_DIALECT_SUN;
3005 error ("bad value (%s) for %stls-dialect=%s %s",
3006 ix86_tls_dialect_string, prefix, suffix, sw);
3009 if (ix87_precision_string)
3011 i = atoi (ix87_precision_string);
3012 if (i != 32 && i != 64 && i != 80)
3013 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3018 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3020 /* Enable by default the SSE and MMX builtins. Do allow the user to
3021 explicitly disable any of these. In particular, disabling SSE and
3022 MMX for kernel code is extremely useful. */
3023 if (!ix86_arch_specified)
3025 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3026 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3029 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3033 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3035 if (!ix86_arch_specified)
3037 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3039 /* i386 ABI does not specify red zone. It still makes sense to use it
3040 when programmer takes care to stack from being destroyed. */
3041 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3042 target_flags |= MASK_NO_RED_ZONE;
3045 /* Keep nonleaf frame pointers. */
3046 if (flag_omit_frame_pointer)
3047 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3048 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3049 flag_omit_frame_pointer = 1;
3051 /* If we're doing fast math, we don't care about comparison order
3052 wrt NaNs. This lets us use a shorter comparison sequence. */
3053 if (flag_finite_math_only)
3054 target_flags &= ~MASK_IEEE_FP;
3056 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3057 since the insns won't need emulation. */
3058 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3059 target_flags &= ~MASK_NO_FANCY_MATH_387;
3061 /* Likewise, if the target doesn't have a 387, or we've specified
3062 software floating point, don't use 387 inline intrinsics. */
3064 target_flags |= MASK_NO_FANCY_MATH_387;
3066 /* Turn on MMX builtins for -msse. */
3069 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3070 x86_prefetch_sse = true;
3073 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3074 if (TARGET_SSE4_2 || TARGET_ABM)
3075 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3077 /* Validate -mpreferred-stack-boundary= value or default it to
3078 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3079 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3080 if (ix86_preferred_stack_boundary_string)
3082 i = atoi (ix86_preferred_stack_boundary_string);
3083 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3084 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3085 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3087 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3090 /* Set the default value for -mstackrealign. */
3091 if (ix86_force_align_arg_pointer == -1)
3092 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3094 /* Validate -mincoming-stack-boundary= value or default it to
3095 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3096 if (ix86_force_align_arg_pointer)
3097 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3099 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3100 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3101 if (ix86_incoming_stack_boundary_string)
3103 i = atoi (ix86_incoming_stack_boundary_string);
3104 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3105 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3106 i, TARGET_64BIT ? 4 : 2);
3109 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3110 ix86_incoming_stack_boundary
3111 = ix86_user_incoming_stack_boundary;
3115 /* Accept -msseregparm only if at least SSE support is enabled. */
3116 if (TARGET_SSEREGPARM
3118 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3120 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3121 if (ix86_fpmath_string != 0)
3123 if (! strcmp (ix86_fpmath_string, "387"))
3124 ix86_fpmath = FPMATH_387;
3125 else if (! strcmp (ix86_fpmath_string, "sse"))
3129 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3130 ix86_fpmath = FPMATH_387;
3133 ix86_fpmath = FPMATH_SSE;
3135 else if (! strcmp (ix86_fpmath_string, "387,sse")
3136 || ! strcmp (ix86_fpmath_string, "387+sse")
3137 || ! strcmp (ix86_fpmath_string, "sse,387")
3138 || ! strcmp (ix86_fpmath_string, "sse+387")
3139 || ! strcmp (ix86_fpmath_string, "both"))
3143 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3144 ix86_fpmath = FPMATH_387;
3146 else if (!TARGET_80387)
3148 warning (0, "387 instruction set disabled, using SSE arithmetics");
3149 ix86_fpmath = FPMATH_SSE;
3152 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3155 error ("bad value (%s) for %sfpmath=%s %s",
3156 ix86_fpmath_string, prefix, suffix, sw);
3159 /* If the i387 is disabled, then do not return values in it. */
3161 target_flags &= ~MASK_FLOAT_RETURNS;
3163 /* Use external vectorized library in vectorizing intrinsics. */
3164 if (ix86_veclibabi_string)
3166 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3167 ix86_veclib_handler = ix86_veclibabi_svml;
3168 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3169 ix86_veclib_handler = ix86_veclibabi_acml;
3171 error ("unknown vectorization library ABI type (%s) for "
3172 "%sveclibabi=%s %s", ix86_veclibabi_string,
3173 prefix, suffix, sw);
3176 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3177 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3179 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3181 /* ??? Unwind info is not correct around the CFG unless either a frame
3182 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3183 unwind info generation to be aware of the CFG and propagating states
3185 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3186 || flag_exceptions || flag_non_call_exceptions)
3187 && flag_omit_frame_pointer
3188 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3190 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3191 warning (0, "unwind tables currently require either a frame pointer "
3192 "or %saccumulate-outgoing-args%s for correctness",
3194 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3197 /* If stack probes are required, the space used for large function
3198 arguments on the stack must also be probed, so enable
3199 -maccumulate-outgoing-args so this happens in the prologue. */
3200 if (TARGET_STACK_PROBE
3201 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3203 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3204 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3205 "for correctness", prefix, suffix);
3206 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3209 /* For sane SSE instruction set generation we need fcomi instruction.
3210 It is safe to enable all CMOVE instructions. */
3214 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3217 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3218 p = strchr (internal_label_prefix, 'X');
3219 internal_label_prefix_len = p - internal_label_prefix;
3223 /* When scheduling description is not available, disable scheduler pass
3224 so it won't slow down the compilation and make x87 code slower. */
3225 if (!TARGET_SCHEDULE)
3226 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3228 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3229 set_param_value ("simultaneous-prefetches",
3230 ix86_cost->simultaneous_prefetches);
3231 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3232 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3233 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3234 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3235 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3236 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3238 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3239 can be optimized to ap = __builtin_next_arg (0). */
3241 targetm.expand_builtin_va_start = NULL;
3245 ix86_gen_leave = gen_leave_rex64;
3246 ix86_gen_pop1 = gen_popdi1;
3247 ix86_gen_add3 = gen_adddi3;
3248 ix86_gen_sub3 = gen_subdi3;
3249 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3250 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3251 ix86_gen_monitor = gen_sse3_monitor64;
3252 ix86_gen_andsp = gen_anddi3;
3256 ix86_gen_leave = gen_leave;
3257 ix86_gen_pop1 = gen_popsi1;
3258 ix86_gen_add3 = gen_addsi3;
3259 ix86_gen_sub3 = gen_subsi3;
3260 ix86_gen_sub3_carry = gen_subsi3_carry;
3261 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3262 ix86_gen_monitor = gen_sse3_monitor;
3263 ix86_gen_andsp = gen_andsi3;
3267 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3269 target_flags |= MASK_CLD & ~target_flags_explicit;
3272 /* Save the initial options in case the user does function specific options */
3274 target_option_default_node = target_option_current_node
3275 = build_target_option_node ();
3278 /* Save the current options */
3281 ix86_function_specific_save (struct cl_target_option *ptr)
3283 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3284 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3285 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3286 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3287 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3289 ptr->arch = ix86_arch;
3290 ptr->schedule = ix86_schedule;
3291 ptr->tune = ix86_tune;
3292 ptr->fpmath = ix86_fpmath;
3293 ptr->branch_cost = ix86_branch_cost;
3294 ptr->tune_defaulted = ix86_tune_defaulted;
3295 ptr->arch_specified = ix86_arch_specified;
3296 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3297 ptr->target_flags_explicit = target_flags_explicit;
3300 /* Restore the current options */
3303 ix86_function_specific_restore (struct cl_target_option *ptr)
3305 enum processor_type old_tune = ix86_tune;
3306 enum processor_type old_arch = ix86_arch;
3307 unsigned int ix86_arch_mask, ix86_tune_mask;
3310 ix86_arch = ptr->arch;
3311 ix86_schedule = ptr->schedule;
3312 ix86_tune = ptr->tune;
3313 ix86_fpmath = ptr->fpmath;
3314 ix86_branch_cost = ptr->branch_cost;
3315 ix86_tune_defaulted = ptr->tune_defaulted;
3316 ix86_arch_specified = ptr->arch_specified;
3317 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3318 target_flags_explicit = ptr->target_flags_explicit;
3320 /* Recreate the arch feature tests if the arch changed */
3321 if (old_arch != ix86_arch)
3323 ix86_arch_mask = 1u << ix86_arch;
3324 for (i = 0; i < X86_ARCH_LAST; ++i)
3325 ix86_arch_features[i]
3326 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3329 /* Recreate the tune optimization tests */
3330 if (old_tune != ix86_tune)
3332 ix86_tune_mask = 1u << ix86_tune;
3333 for (i = 0; i < X86_TUNE_LAST; ++i)
3334 ix86_tune_features[i]
3335 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3339 /* Print the current options */
3342 ix86_function_specific_print (FILE *file, int indent,
3343 struct cl_target_option *ptr)
3346 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3347 NULL, NULL, NULL, false);
3349 fprintf (file, "%*sarch = %d (%s)\n",
3352 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3353 ? cpu_names[ptr->arch]
3356 fprintf (file, "%*stune = %d (%s)\n",
3359 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3360 ? cpu_names[ptr->tune]
3363 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3364 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3365 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3366 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3370 fprintf (file, "%*s%s\n", indent, "", target_string);
3371 free (target_string);
3376 /* Inner function to process the attribute((target(...))), take an argument and
3377 set the current options from the argument. If we have a list, recursively go
3381 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3386 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3387 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3388 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3389 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3404 enum ix86_opt_type type;
3409 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3410 IX86_ATTR_ISA ("abm", OPT_mabm),
3411 IX86_ATTR_ISA ("aes", OPT_maes),
3412 IX86_ATTR_ISA ("avx", OPT_mavx),
3413 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3414 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3415 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3416 IX86_ATTR_ISA ("sse", OPT_msse),
3417 IX86_ATTR_ISA ("sse2", OPT_msse2),
3418 IX86_ATTR_ISA ("sse3", OPT_msse3),
3419 IX86_ATTR_ISA ("sse4", OPT_msse4),
3420 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3421 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3422 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3423 IX86_ATTR_ISA ("sse5", OPT_msse5),
3424 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3426 /* string options */
3427 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3428 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3429 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3432 IX86_ATTR_YES ("cld",
3436 IX86_ATTR_NO ("fancy-math-387",
3437 OPT_mfancy_math_387,
3438 MASK_NO_FANCY_MATH_387),
3440 IX86_ATTR_NO ("fused-madd",
3442 MASK_NO_FUSED_MADD),
3444 IX86_ATTR_YES ("ieee-fp",
3448 IX86_ATTR_YES ("inline-all-stringops",
3449 OPT_minline_all_stringops,
3450 MASK_INLINE_ALL_STRINGOPS),
3452 IX86_ATTR_YES ("inline-stringops-dynamically",
3453 OPT_minline_stringops_dynamically,
3454 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3456 IX86_ATTR_NO ("align-stringops",
3457 OPT_mno_align_stringops,
3458 MASK_NO_ALIGN_STRINGOPS),
3460 IX86_ATTR_YES ("recip",
3466 /* If this is a list, recurse to get the options. */
3467 if (TREE_CODE (args) == TREE_LIST)
3471 for (; args; args = TREE_CHAIN (args))
3472 if (TREE_VALUE (args)
3473 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3479 else if (TREE_CODE (args) != STRING_CST)
3482 /* Handle multiple arguments separated by commas. */
3483 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3485 while (next_optstr && *next_optstr != '\0')
3487 char *p = next_optstr;
3489 char *comma = strchr (next_optstr, ',');
3490 const char *opt_string;
3491 size_t len, opt_len;
3496 enum ix86_opt_type type = ix86_opt_unknown;
3502 len = comma - next_optstr;
3503 next_optstr = comma + 1;
3511 /* Recognize no-xxx. */
3512 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3521 /* Find the option. */
3524 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3526 type = attrs[i].type;
3527 opt_len = attrs[i].len;
3528 if (ch == attrs[i].string[0]
3529 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3530 && memcmp (p, attrs[i].string, opt_len) == 0)
3533 mask = attrs[i].mask;
3534 opt_string = attrs[i].string;
3539 /* Process the option. */
3542 error ("attribute(target(\"%s\")) is unknown", orig_p);
3546 else if (type == ix86_opt_isa)
3547 ix86_handle_option (opt, p, opt_set_p);
3549 else if (type == ix86_opt_yes || type == ix86_opt_no)
3551 if (type == ix86_opt_no)
3552 opt_set_p = !opt_set_p;
3555 target_flags |= mask;
3557 target_flags &= ~mask;
3560 else if (type == ix86_opt_str)
3564 error ("option(\"%s\") was already specified", opt_string);
3568 p_strings[opt] = xstrdup (p + opt_len);
3578 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3581 ix86_valid_target_attribute_tree (tree args)
3583 const char *orig_arch_string = ix86_arch_string;
3584 const char *orig_tune_string = ix86_tune_string;
3585 const char *orig_fpmath_string = ix86_fpmath_string;
3586 int orig_tune_defaulted = ix86_tune_defaulted;
3587 int orig_arch_specified = ix86_arch_specified;
3588 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3591 struct cl_target_option *def
3592 = TREE_TARGET_OPTION (target_option_default_node);
3594 /* Process each of the options on the chain. */
3595 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3598 /* If the changed options are different from the default, rerun override_options,
3599 and then save the options away. The string options are are attribute options,
3600 and will be undone when we copy the save structure. */
3601 if (ix86_isa_flags != def->ix86_isa_flags
3602 || target_flags != def->target_flags
3603 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3604 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3605 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3607 /* If we are using the default tune= or arch=, undo the string assigned,
3608 and use the default. */
3609 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3610 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3611 else if (!orig_arch_specified)
3612 ix86_arch_string = NULL;
3614 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3615 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3616 else if (orig_tune_defaulted)
3617 ix86_tune_string = NULL;
3619 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3620 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3621 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3622 else if (!TARGET_64BIT && TARGET_SSE)
3623 ix86_fpmath_string = "sse,387";
3625 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3626 override_options (false);
3628 /* Add any builtin functions with the new isa if any. */
3629 ix86_add_new_builtins (ix86_isa_flags);
3631 /* Save the current options unless we are validating options for
3633 t = build_target_option_node ();
3635 ix86_arch_string = orig_arch_string;
3636 ix86_tune_string = orig_tune_string;
3637 ix86_fpmath_string = orig_fpmath_string;
3639 /* Free up memory allocated to hold the strings */
3640 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3641 if (option_strings[i])
3642 free (option_strings[i]);
3648 /* Hook to validate attribute((target("string"))). */
3651 ix86_valid_target_attribute_p (tree fndecl,
3652 tree ARG_UNUSED (name),
3654 int ARG_UNUSED (flags))
3656 struct cl_target_option cur_target;
3658 tree old_optimize = build_optimization_node ();
3659 tree new_target, new_optimize;
3660 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3662 /* If the function changed the optimization levels as well as setting target
3663 options, start with the optimizations specified. */
3664 if (func_optimize && func_optimize != old_optimize)
3665 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3667 /* The target attributes may also change some optimization flags, so update
3668 the optimization options if necessary. */
3669 cl_target_option_save (&cur_target);
3670 new_target = ix86_valid_target_attribute_tree (args);
3671 new_optimize = build_optimization_node ();
3678 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3680 if (old_optimize != new_optimize)
3681 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3684 cl_target_option_restore (&cur_target);
3686 if (old_optimize != new_optimize)
3687 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3693 /* Hook to determine if one function can safely inline another. */
3696 ix86_can_inline_p (tree caller, tree callee)
3699 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3700 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3702 /* If callee has no option attributes, then it is ok to inline. */
3706 /* If caller has no option attributes, but callee does then it is not ok to
3708 else if (!caller_tree)
3713 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3714 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3716 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3717 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3719 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3720 != callee_opts->ix86_isa_flags)
3723 /* See if we have the same non-isa options. */
3724 else if (caller_opts->target_flags != callee_opts->target_flags)
3727 /* See if arch, tune, etc. are the same. */
3728 else if (caller_opts->arch != callee_opts->arch)
3731 else if (caller_opts->tune != callee_opts->tune)
3734 else if (caller_opts->fpmath != callee_opts->fpmath)
3737 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3748 /* Remember the last target of ix86_set_current_function. */
3749 static GTY(()) tree ix86_previous_fndecl;
3751 /* Establish appropriate back-end context for processing the function
3752 FNDECL. The argument might be NULL to indicate processing at top
3753 level, outside of any function scope. */
3755 ix86_set_current_function (tree fndecl)
3757 /* Only change the context if the function changes. This hook is called
3758 several times in the course of compiling a function, and we don't want to
3759 slow things down too much or call target_reinit when it isn't safe. */
3760 if (fndecl && fndecl != ix86_previous_fndecl)
3762 tree old_tree = (ix86_previous_fndecl
3763 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3766 tree new_tree = (fndecl
3767 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3770 ix86_previous_fndecl = fndecl;
3771 if (old_tree == new_tree)
3776 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3782 struct cl_target_option *def
3783 = TREE_TARGET_OPTION (target_option_current_node);
3785 cl_target_option_restore (def);
3792 /* Return true if this goes in large data/bss. */
3795 ix86_in_large_data_p (tree exp)
3797 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3800 /* Functions are never large data. */
3801 if (TREE_CODE (exp) == FUNCTION_DECL)
3804 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3806 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3807 if (strcmp (section, ".ldata") == 0
3808 || strcmp (section, ".lbss") == 0)
3814 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3816 /* If this is an incomplete type with size 0, then we can't put it
3817 in data because it might be too big when completed. */
3818 if (!size || size > ix86_section_threshold)
3825 /* Switch to the appropriate section for output of DECL.
3826 DECL is either a `VAR_DECL' node or a constant of some sort.
3827 RELOC indicates whether forming the initial value of DECL requires
3828 link-time relocations. */
3830 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3834 x86_64_elf_select_section (tree decl, int reloc,
3835 unsigned HOST_WIDE_INT align)
3837 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3838 && ix86_in_large_data_p (decl))
3840 const char *sname = NULL;
3841 unsigned int flags = SECTION_WRITE;
3842 switch (categorize_decl_for_section (decl, reloc))
3847 case SECCAT_DATA_REL:
3848 sname = ".ldata.rel";
3850 case SECCAT_DATA_REL_LOCAL:
3851 sname = ".ldata.rel.local";
3853 case SECCAT_DATA_REL_RO:
3854 sname = ".ldata.rel.ro";
3856 case SECCAT_DATA_REL_RO_LOCAL:
3857 sname = ".ldata.rel.ro.local";
3861 flags |= SECTION_BSS;
3864 case SECCAT_RODATA_MERGE_STR:
3865 case SECCAT_RODATA_MERGE_STR_INIT:
3866 case SECCAT_RODATA_MERGE_CONST:
3870 case SECCAT_SRODATA:
3877 /* We don't split these for medium model. Place them into
3878 default sections and hope for best. */
3880 case SECCAT_EMUTLS_VAR:
3881 case SECCAT_EMUTLS_TMPL:
3886 /* We might get called with string constants, but get_named_section
3887 doesn't like them as they are not DECLs. Also, we need to set
3888 flags in that case. */
3890 return get_section (sname, flags, NULL);
3891 return get_named_section (decl, sname, reloc);
3894 return default_elf_select_section (decl, reloc, align);
3897 /* Build up a unique section name, expressed as a
3898 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3899 RELOC indicates whether the initial value of EXP requires
3900 link-time relocations. */
3902 static void ATTRIBUTE_UNUSED
3903 x86_64_elf_unique_section (tree decl, int reloc)
3905 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3906 && ix86_in_large_data_p (decl))
3908 const char *prefix = NULL;
3909 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3910 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3912 switch (categorize_decl_for_section (decl, reloc))
3915 case SECCAT_DATA_REL:
3916 case SECCAT_DATA_REL_LOCAL:
3917 case SECCAT_DATA_REL_RO:
3918 case SECCAT_DATA_REL_RO_LOCAL:
3919 prefix = one_only ? ".ld" : ".ldata";
3922 prefix = one_only ? ".lb" : ".lbss";
3925 case SECCAT_RODATA_MERGE_STR:
3926 case SECCAT_RODATA_MERGE_STR_INIT:
3927 case SECCAT_RODATA_MERGE_CONST:
3928 prefix = one_only ? ".lr" : ".lrodata";
3930 case SECCAT_SRODATA:
3937 /* We don't split these for medium model. Place them into
3938 default sections and hope for best. */
3940 case SECCAT_EMUTLS_VAR:
3941 prefix = targetm.emutls.var_section;
3943 case SECCAT_EMUTLS_TMPL:
3944 prefix = targetm.emutls.tmpl_section;
3949 const char *name, *linkonce;
3952 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3953 name = targetm.strip_name_encoding (name);
3955 /* If we're using one_only, then there needs to be a .gnu.linkonce
3956 prefix to the section name. */
3957 linkonce = one_only ? ".gnu.linkonce" : "";
3959 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3961 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3965 default_unique_section (decl, reloc);
3968 #ifdef COMMON_ASM_OP
3969 /* This says how to output assembler code to declare an
3970 uninitialized external linkage data object.
3972 For medium model x86-64 we need to use .largecomm opcode for
3975 x86_elf_aligned_common (FILE *file,
3976 const char *name, unsigned HOST_WIDE_INT size,
3979 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3980 && size > (unsigned int)ix86_section_threshold)
3981 fprintf (file, ".largecomm\t");
3983 fprintf (file, "%s", COMMON_ASM_OP);
3984 assemble_name (file, name);
3985 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
3986 size, align / BITS_PER_UNIT);
3990 /* Utility function for targets to use in implementing
3991 ASM_OUTPUT_ALIGNED_BSS. */
3994 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
3995 const char *name, unsigned HOST_WIDE_INT size,
3998 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3999 && size > (unsigned int)ix86_section_threshold)
4000 switch_to_section (get_named_section (decl, ".lbss", 0));
4002 switch_to_section (bss_section);
4003 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4004 #ifdef ASM_DECLARE_OBJECT_NAME
4005 last_assemble_variable_decl = decl;
4006 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4008 /* Standard thing is just output label for the object. */
4009 ASM_OUTPUT_LABEL (file, name);
4010 #endif /* ASM_DECLARE_OBJECT_NAME */
4011 ASM_OUTPUT_SKIP (file, size ? size : 1);
4015 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4017 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4018 make the problem with not enough registers even worse. */
4019 #ifdef INSN_SCHEDULING
4021 flag_schedule_insns = 0;
4025 /* The Darwin libraries never set errno, so we might as well
4026 avoid calling them when that's the only reason we would. */
4027 flag_errno_math = 0;
4029 /* The default values of these switches depend on the TARGET_64BIT
4030 that is not known at this moment. Mark these values with 2 and
4031 let user the to override these. In case there is no command line option
4032 specifying them, we will set the defaults in override_options. */
4034 flag_omit_frame_pointer = 2;
4035 flag_pcc_struct_return = 2;
4036 flag_asynchronous_unwind_tables = 2;
4037 flag_vect_cost_model = 1;
4038 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4039 SUBTARGET_OPTIMIZATION_OPTIONS;
4043 /* Decide whether we can make a sibling call to a function. DECL is the
4044 declaration of the function being targeted by the call and EXP is the
4045 CALL_EXPR representing the call. */
4048 ix86_function_ok_for_sibcall (tree decl, tree exp)
4053 /* If we are generating position-independent code, we cannot sibcall
4054 optimize any indirect call, or a direct call to a global function,
4055 as the PLT requires %ebx be live. */
4056 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4063 func = TREE_TYPE (CALL_EXPR_FN (exp));
4064 if (POINTER_TYPE_P (func))
4065 func = TREE_TYPE (func);
4068 /* Check that the return value locations are the same. Like
4069 if we are returning floats on the 80387 register stack, we cannot
4070 make a sibcall from a function that doesn't return a float to a
4071 function that does or, conversely, from a function that does return
4072 a float to a function that doesn't; the necessary stack adjustment
4073 would not be executed. This is also the place we notice
4074 differences in the return value ABI. Note that it is ok for one
4075 of the functions to have void return type as long as the return
4076 value of the other is passed in a register. */
4077 a = ix86_function_value (TREE_TYPE (exp), func, false);
4078 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4080 if (STACK_REG_P (a) || STACK_REG_P (b))
4082 if (!rtx_equal_p (a, b))
4085 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4087 else if (!rtx_equal_p (a, b))
4090 /* If this call is indirect, we'll need to be able to use a call-clobbered
4091 register for the address of the target function. Make sure that all
4092 such registers are not used for passing parameters. */
4093 if (!decl && !TARGET_64BIT)
4097 /* We're looking at the CALL_EXPR, we need the type of the function. */
4098 type = CALL_EXPR_FN (exp); /* pointer expression */
4099 type = TREE_TYPE (type); /* pointer type */
4100 type = TREE_TYPE (type); /* function type */
4102 if (ix86_function_regparm (type, NULL) >= 3)
4104 /* ??? Need to count the actual number of registers to be used,
4105 not the possible number of registers. Fix later. */
4110 /* Dllimport'd functions are also called indirectly. */
4111 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4113 && decl && DECL_DLLIMPORT_P (decl)
4114 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4117 /* If we need to align the outgoing stack, then sibcalling would
4118 unalign the stack, which may break the called function. */
4119 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4122 /* Otherwise okay. That also includes certain types of indirect calls. */
4126 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4127 calling convention attributes;
4128 arguments as in struct attribute_spec.handler. */
4131 ix86_handle_cconv_attribute (tree *node, tree name,
4133 int flags ATTRIBUTE_UNUSED,
4136 if (TREE_CODE (*node) != FUNCTION_TYPE
4137 && TREE_CODE (*node) != METHOD_TYPE
4138 && TREE_CODE (*node) != FIELD_DECL
4139 && TREE_CODE (*node) != TYPE_DECL)
4141 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4142 IDENTIFIER_POINTER (name));
4143 *no_add_attrs = true;
4147 /* Can combine regparm with all attributes but fastcall. */
4148 if (is_attribute_p ("regparm", name))
4152 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4154 error ("fastcall and regparm attributes are not compatible");
4157 cst = TREE_VALUE (args);
4158 if (TREE_CODE (cst) != INTEGER_CST)
4160 warning (OPT_Wattributes,
4161 "%qs attribute requires an integer constant argument",
4162 IDENTIFIER_POINTER (name));
4163 *no_add_attrs = true;
4165 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4167 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4168 IDENTIFIER_POINTER (name), REGPARM_MAX);
4169 *no_add_attrs = true;
4177 /* Do not warn when emulating the MS ABI. */
4178 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4179 warning (OPT_Wattributes, "%qs attribute ignored",
4180 IDENTIFIER_POINTER (name));
4181 *no_add_attrs = true;
4185 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4186 if (is_attribute_p ("fastcall", name))
4188 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4190 error ("fastcall and cdecl attributes are not compatible");
4192 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4194 error ("fastcall and stdcall attributes are not compatible");
4196 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4198 error ("fastcall and regparm attributes are not compatible");
4202 /* Can combine stdcall with fastcall (redundant), regparm and
4204 else if (is_attribute_p ("stdcall", name))
4206 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4208 error ("stdcall and cdecl attributes are not compatible");
4210 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4212 error ("stdcall and fastcall attributes are not compatible");
4216 /* Can combine cdecl with regparm and sseregparm. */
4217 else if (is_attribute_p ("cdecl", name))
4219 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4221 error ("stdcall and cdecl attributes are not compatible");
4223 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4225 error ("fastcall and cdecl attributes are not compatible");
4229 /* Can combine sseregparm with all attributes. */
4234 /* Return 0 if the attributes for two types are incompatible, 1 if they
4235 are compatible, and 2 if they are nearly compatible (which causes a
4236 warning to be generated). */
4239 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4241 /* Check for mismatch of non-default calling convention. */
4242 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4244 if (TREE_CODE (type1) != FUNCTION_TYPE
4245 && TREE_CODE (type1) != METHOD_TYPE)
4248 /* Check for mismatched fastcall/regparm types. */
4249 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4250 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4251 || (ix86_function_regparm (type1, NULL)
4252 != ix86_function_regparm (type2, NULL)))
4255 /* Check for mismatched sseregparm types. */
4256 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4257 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4260 /* Check for mismatched return types (cdecl vs stdcall). */
4261 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4262 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4268 /* Return the regparm value for a function with the indicated TYPE and DECL.
4269 DECL may be NULL when calling function indirectly
4270 or considering a libcall. */
4273 ix86_function_regparm (const_tree type, const_tree decl)
4276 int regparm = ix86_regparm;
4278 static bool error_issued;
4282 if (ix86_function_type_abi (type) == DEFAULT_ABI)
4284 return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
4287 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4291 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4293 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4295 /* We can't use regparm(3) for nested functions because
4296 these pass static chain pointer in %ecx register. */
4297 if (!error_issued && regparm == 3
4298 && decl_function_context (decl)
4299 && !DECL_NO_STATIC_CHAIN (decl))
4301 error ("nested functions are limited to 2 register parameters");
4302 error_issued = true;
4310 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4313 /* Use register calling convention for local functions when possible. */
4314 if (decl && TREE_CODE (decl) == FUNCTION_DECL
4317 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4318 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4321 int local_regparm, globals = 0, regno;
4324 /* Make sure no regparm register is taken by a
4325 fixed register variable. */
4326 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4327 if (fixed_regs[local_regparm])
4330 /* We can't use regparm(3) for nested functions as these use
4331 static chain pointer in third argument. */
4332 if (local_regparm == 3
4333 && decl_function_context (decl)
4334 && !DECL_NO_STATIC_CHAIN (decl))
4337 /* If the function realigns its stackpointer, the prologue will
4338 clobber %ecx. If we've already generated code for the callee,
4339 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4340 scanning the attributes for the self-realigning property. */
4341 f = DECL_STRUCT_FUNCTION (decl);
4342 /* Since current internal arg pointer won't conflict with
4343 parameter passing regs, so no need to change stack
4344 realignment and adjust regparm number.
4346 Each fixed register usage increases register pressure,
4347 so less registers should be used for argument passing.
4348 This functionality can be overriden by an explicit
4350 for (regno = 0; regno <= DI_REG; regno++)
4351 if (fixed_regs[regno])
4355 = globals < local_regparm ? local_regparm - globals : 0;
4357 if (local_regparm > regparm)
4358 regparm = local_regparm;
4365 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4366 DFmode (2) arguments in SSE registers for a function with the
4367 indicated TYPE and DECL. DECL may be NULL when calling function
4368 indirectly or considering a libcall. Otherwise return 0. */
4371 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4373 gcc_assert (!TARGET_64BIT);
4375 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4376 by the sseregparm attribute. */
4377 if (TARGET_SSEREGPARM
4378 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4385 error ("Calling %qD with attribute sseregparm without "
4386 "SSE/SSE2 enabled", decl);
4388 error ("Calling %qT with attribute sseregparm without "
4389 "SSE/SSE2 enabled", type);
4397 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4398 (and DFmode for SSE2) arguments in SSE registers. */
4399 if (decl && TARGET_SSE_MATH && !profile_flag)
4401 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4402 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4404 return TARGET_SSE2 ? 2 : 1;
4410 /* Return true if EAX is live at the start of the function. Used by
4411 ix86_expand_prologue to determine if we need special help before
4412 calling allocate_stack_worker. */
4415 ix86_eax_live_at_start_p (void)
4417 /* Cheat. Don't bother working forward from ix86_function_regparm
4418 to the function type to whether an actual argument is located in
4419 eax. Instead just look at cfg info, which is still close enough
4420 to correct at this point. This gives false positives for broken
4421 functions that might use uninitialized data that happens to be
4422 allocated in eax, but who cares? */
4423 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4426 /* Value is the number of bytes of arguments automatically
4427 popped when returning from a subroutine call.
4428 FUNDECL is the declaration node of the function (as a tree),
4429 FUNTYPE is the data type of the function (as a tree),
4430 or for a library call it is an identifier node for the subroutine name.
4431 SIZE is the number of bytes of arguments passed on the stack.
4433 On the 80386, the RTD insn may be used to pop them if the number
4434 of args is fixed, but if the number is variable then the caller
4435 must pop them all. RTD can't be used for library calls now
4436 because the library is compiled with the Unix compiler.
4437 Use of RTD is a selectable option, since it is incompatible with
4438 standard Unix calling sequences. If the option is not selected,
4439 the caller must always pop the args.
4441 The attribute stdcall is equivalent to RTD on a per module basis. */
4444 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4448 /* None of the 64-bit ABIs pop arguments. */
4452 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4454 /* Cdecl functions override -mrtd, and never pop the stack. */
4455 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4457 /* Stdcall and fastcall functions will pop the stack if not
4459 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4460 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4463 if (rtd && ! stdarg_p (funtype))
4467 /* Lose any fake structure return argument if it is passed on the stack. */
4468 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4469 && !KEEP_AGGREGATE_RETURN_POINTER)
4471 int nregs = ix86_function_regparm (funtype, fundecl);
4473 return GET_MODE_SIZE (Pmode);
4479 /* Argument support functions. */
4481 /* Return true when register may be used to pass function parameters. */
4483 ix86_function_arg_regno_p (int regno)
4486 const int *parm_regs;
4491 return (regno < REGPARM_MAX
4492 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4494 return (regno < REGPARM_MAX
4495 || (TARGET_MMX && MMX_REGNO_P (regno)
4496 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4497 || (TARGET_SSE && SSE_REGNO_P (regno)
4498 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4503 if (SSE_REGNO_P (regno) && TARGET_SSE)
4508 if (TARGET_SSE && SSE_REGNO_P (regno)
4509 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4513 /* TODO: The function should depend on current function ABI but
4514 builtins.c would need updating then. Therefore we use the
4517 /* RAX is used as hidden argument to va_arg functions. */
4518 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4521 if (DEFAULT_ABI == MS_ABI)
4522 parm_regs = x86_64_ms_abi_int_parameter_registers;
4524 parm_regs = x86_64_int_parameter_registers;
4525 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4526 : X86_64_REGPARM_MAX); i++)
4527 if (regno == parm_regs[i])
4532 /* Return if we do not know how to pass TYPE solely in registers. */
4535 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4537 if (must_pass_in_stack_var_size_or_pad (mode, type))
4540 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4541 The layout_type routine is crafty and tries to trick us into passing
4542 currently unsupported vector types on the stack by using TImode. */
4543 return (!TARGET_64BIT && mode == TImode
4544 && type && TREE_CODE (type) != VECTOR_TYPE);
4547 /* It returns the size, in bytes, of the area reserved for arguments passed
4548 in registers for the function represented by fndecl dependent to the used
4551 ix86_reg_parm_stack_space (const_tree fndecl)
4553 int call_abi = SYSV_ABI;
4554 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4555 call_abi = ix86_function_abi (fndecl);
4557 call_abi = ix86_function_type_abi (fndecl);
4558 if (call_abi == MS_ABI)
4563 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4566 ix86_function_type_abi (const_tree fntype)
4568 if (TARGET_64BIT && fntype != NULL)
4571 if (DEFAULT_ABI == SYSV_ABI)
4572 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4574 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4582 ix86_function_abi (const_tree fndecl)
4586 return ix86_function_type_abi (TREE_TYPE (fndecl));
4589 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4592 ix86_cfun_abi (void)
4594 if (! cfun || ! TARGET_64BIT)
4596 return cfun->machine->call_abi;
4600 extern void init_regs (void);
4602 /* Implementation of call abi switching target hook. Specific to FNDECL
4603 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4604 for more details. */
4606 ix86_call_abi_override (const_tree fndecl)
4608 if (fndecl == NULL_TREE)
4609 cfun->machine->call_abi = DEFAULT_ABI;
4611 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4614 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4615 re-initialization of init_regs each time we switch function context since
4616 this is needed only during RTL expansion. */
4618 ix86_maybe_switch_abi (void)
4621 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4625 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4626 for a call to a function whose data type is FNTYPE.
4627 For a library call, FNTYPE is 0. */
4630 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4631 tree fntype, /* tree ptr for function decl */
4632 rtx libname, /* SYMBOL_REF of library name or 0 */
4635 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4636 memset (cum, 0, sizeof (*cum));
4639 cum->call_abi = ix86_function_abi (fndecl);
4641 cum->call_abi = ix86_function_type_abi (fntype);
4642 /* Set up the number of registers to use for passing arguments. */
4644 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4645 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4646 cum->nregs = ix86_regparm;
4649 if (cum->call_abi != DEFAULT_ABI)
4650 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4655 cum->sse_nregs = SSE_REGPARM_MAX;
4658 if (cum->call_abi != DEFAULT_ABI)
4659 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4660 : X64_SSE_REGPARM_MAX;
4664 cum->mmx_nregs = MMX_REGPARM_MAX;
4665 cum->warn_avx = true;
4666 cum->warn_sse = true;
4667 cum->warn_mmx = true;
4669 /* Because type might mismatch in between caller and callee, we need to
4670 use actual type of function for local calls.
4671 FIXME: cgraph_analyze can be told to actually record if function uses
4672 va_start so for local functions maybe_vaarg can be made aggressive
4674 FIXME: once typesytem is fixed, we won't need this code anymore. */
4676 fntype = TREE_TYPE (fndecl);
4677 cum->maybe_vaarg = (fntype
4678 ? (!prototype_p (fntype) || stdarg_p (fntype))
4683 /* If there are variable arguments, then we won't pass anything
4684 in registers in 32-bit mode. */
4685 if (stdarg_p (fntype))
4696 /* Use ecx and edx registers if function has fastcall attribute,
4697 else look for regparm information. */
4700 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4706 cum->nregs = ix86_function_regparm (fntype, fndecl);
4709 /* Set up the number of SSE registers used for passing SFmode
4710 and DFmode arguments. Warn for mismatching ABI. */
4711 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4715 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4716 But in the case of vector types, it is some vector mode.
4718 When we have only some of our vector isa extensions enabled, then there
4719 are some modes for which vector_mode_supported_p is false. For these
4720 modes, the generic vector support in gcc will choose some non-vector mode
4721 in order to implement the type. By computing the natural mode, we'll
4722 select the proper ABI location for the operand and not depend on whatever
4723 the middle-end decides to do with these vector types.
4725 The midde-end can't deal with the vector types > 16 bytes. In this
4726 case, we return the original mode and warn ABI change if CUM isn't
4729 static enum machine_mode
4730 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4732 enum machine_mode mode = TYPE_MODE (type);
4734 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4736 HOST_WIDE_INT size = int_size_in_bytes (type);
4737 if ((size == 8 || size == 16 || size == 32)
4738 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4739 && TYPE_VECTOR_SUBPARTS (type) > 1)
4741 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4743 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4744 mode = MIN_MODE_VECTOR_FLOAT;
4746 mode = MIN_MODE_VECTOR_INT;
4748 /* Get the mode which has this inner mode and number of units. */
4749 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4750 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4751 && GET_MODE_INNER (mode) == innermode)
4753 if (size == 32 && !TARGET_AVX)
4755 static bool warnedavx;
4762 warning (0, "AVX vector argument without AVX "
4763 "enabled changes the ABI");
4765 return TYPE_MODE (type);
4778 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4779 this may not agree with the mode that the type system has chosen for the
4780 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4781 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4784 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4789 if (orig_mode != BLKmode)
4790 tmp = gen_rtx_REG (orig_mode, regno);
4793 tmp = gen_rtx_REG (mode, regno);
4794 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4795 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4801 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4802 of this code is to classify each 8bytes of incoming argument by the register
4803 class and assign registers accordingly. */
4805 /* Return the union class of CLASS1 and CLASS2.
4806 See the x86-64 PS ABI for details. */
4808 static enum x86_64_reg_class
4809 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4811 /* Rule #1: If both classes are equal, this is the resulting class. */
4812 if (class1 == class2)
4815 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4817 if (class1 == X86_64_NO_CLASS)
4819 if (class2 == X86_64_NO_CLASS)
4822 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4823 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4824 return X86_64_MEMORY_CLASS;
4826 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4827 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4828 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4829 return X86_64_INTEGERSI_CLASS;
4830 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4831 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4832 return X86_64_INTEGER_CLASS;
4834 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4836 if (class1 == X86_64_X87_CLASS
4837 || class1 == X86_64_X87UP_CLASS
4838 || class1 == X86_64_COMPLEX_X87_CLASS
4839 || class2 == X86_64_X87_CLASS
4840 || class2 == X86_64_X87UP_CLASS
4841 || class2 == X86_64_COMPLEX_X87_CLASS)
4842 return X86_64_MEMORY_CLASS;
4844 /* Rule #6: Otherwise class SSE is used. */
4845 return X86_64_SSE_CLASS;
4848 /* Classify the argument of type TYPE and mode MODE.
4849 CLASSES will be filled by the register class used to pass each word
4850 of the operand. The number of words is returned. In case the parameter
4851 should be passed in memory, 0 is returned. As a special case for zero
4852 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4854 BIT_OFFSET is used internally for handling records and specifies offset
4855 of the offset in bits modulo 256 to avoid overflow cases.
4857 See the x86-64 PS ABI for details.
4861 classify_argument (enum machine_mode mode, const_tree type,
4862 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4864 HOST_WIDE_INT bytes =
4865 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4866 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4868 /* Variable sized entities are always passed/returned in memory. */
4872 if (mode != VOIDmode
4873 && targetm.calls.must_pass_in_stack (mode, type))
4876 if (type && AGGREGATE_TYPE_P (type))
4880 enum x86_64_reg_class subclasses[MAX_CLASSES];
4882 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4886 for (i = 0; i < words; i++)
4887 classes[i] = X86_64_NO_CLASS;
4889 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4890 signalize memory class, so handle it as special case. */
4893 classes[0] = X86_64_NO_CLASS;
4897 /* Classify each field of record and merge classes. */
4898 switch (TREE_CODE (type))
4901 /* And now merge the fields of structure. */
4902 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4904 if (TREE_CODE (field) == FIELD_DECL)
4908 if (TREE_TYPE (field) == error_mark_node)
4911 /* Bitfields are always classified as integer. Handle them
4912 early, since later code would consider them to be
4913 misaligned integers. */
4914 if (DECL_BIT_FIELD (field))
4916 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4917 i < ((int_bit_position (field) + (bit_offset % 64))
4918 + tree_low_cst (DECL_SIZE (field), 0)
4921 merge_classes (X86_64_INTEGER_CLASS,
4926 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4927 TREE_TYPE (field), subclasses,
4928 (int_bit_position (field)
4929 + bit_offset) % 256);
4932 for (i = 0; i < num; i++)
4935 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4937 merge_classes (subclasses[i], classes[i + pos]);
4945 /* Arrays are handled as small records. */
4948 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4949 TREE_TYPE (type), subclasses, bit_offset);
4953 /* The partial classes are now full classes. */
4954 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4955 subclasses[0] = X86_64_SSE_CLASS;
4956 if (subclasses[0] == X86_64_INTEGERSI_CLASS
4957 && !((bit_offset % 64) == 0 && bytes == 4))
4958 subclasses[0] = X86_64_INTEGER_CLASS;
4960 for (i = 0; i < words; i++)
4961 classes[i] = subclasses[i % num];
4966 case QUAL_UNION_TYPE:
4967 /* Unions are similar to RECORD_TYPE but offset is always 0.
4969 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4971 if (TREE_CODE (field) == FIELD_DECL)
4975 if (TREE_TYPE (field) == error_mark_node)
4978 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4979 TREE_TYPE (field), subclasses,
4983 for (i = 0; i < num; i++)
4984 classes[i] = merge_classes (subclasses[i], classes[i]);
4995 /* When size > 16 bytes, if the first one isn't
4996 X86_64_SSE_CLASS or any other ones aren't
4997 X86_64_SSEUP_CLASS, everything should be passed in
4999 if (classes[0] != X86_64_SSE_CLASS)
5002 for (i = 1; i < words; i++)
5003 if (classes[i] != X86_64_SSEUP_CLASS)
5007 /* Final merger cleanup. */
5008 for (i = 0; i < words; i++)
5010 /* If one class is MEMORY, everything should be passed in
5012 if (classes[i] == X86_64_MEMORY_CLASS)
5015 /* The X86_64_SSEUP_CLASS should be always preceded by
5016 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5017 if (classes[i] == X86_64_SSEUP_CLASS
5018 && classes[i - 1] != X86_64_SSE_CLASS
5019 && classes[i - 1] != X86_64_SSEUP_CLASS)
5021 /* The first one should never be X86_64_SSEUP_CLASS. */
5022 gcc_assert (i != 0);
5023 classes[i] = X86_64_SSE_CLASS;
5026 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5027 everything should be passed in memory. */
5028 if (classes[i] == X86_64_X87UP_CLASS
5029 && (classes[i - 1] != X86_64_X87_CLASS))
5033 /* The first one should never be X86_64_X87UP_CLASS. */
5034 gcc_assert (i != 0);
5035 if (!warned && warn_psabi)
5038 inform (input_location,
5039 "The ABI of passing union with long double"
5040 " has changed in GCC 4.4");
5048 /* Compute alignment needed. We align all types to natural boundaries with
5049 exception of XFmode that is aligned to 64bits. */
5050 if (mode != VOIDmode && mode != BLKmode)
5052 int mode_alignment = GET_MODE_BITSIZE (mode);
5055 mode_alignment = 128;
5056 else if (mode == XCmode)
5057 mode_alignment = 256;
5058 if (COMPLEX_MODE_P (mode))
5059 mode_alignment /= 2;
5060 /* Misaligned fields are always returned in memory. */
5061 if (bit_offset % mode_alignment)
5065 /* for V1xx modes, just use the base mode */
5066 if (VECTOR_MODE_P (mode) && mode != V1DImode
5067 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5068 mode = GET_MODE_INNER (mode);
5070 /* Classification of atomic types. */
5075 classes[0] = X86_64_SSE_CLASS;
5078 classes[0] = X86_64_SSE_CLASS;
5079 classes[1] = X86_64_SSEUP_CLASS;
5089 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5093 classes[0] = X86_64_INTEGERSI_CLASS;
5096 else if (size <= 64)
5098 classes[0] = X86_64_INTEGER_CLASS;
5101 else if (size <= 64+32)
5103 classes[0] = X86_64_INTEGER_CLASS;
5104 classes[1] = X86_64_INTEGERSI_CLASS;
5107 else if (size <= 64+64)
5109 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5117 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5121 /* OImode shouldn't be used directly. */
5126 if (!(bit_offset % 64))
5127 classes[0] = X86_64_SSESF_CLASS;
5129 classes[0] = X86_64_SSE_CLASS;
5132 classes[0] = X86_64_SSEDF_CLASS;
5135 classes[0] = X86_64_X87_CLASS;
5136 classes[1] = X86_64_X87UP_CLASS;
5139 classes[0] = X86_64_SSE_CLASS;
5140 classes[1] = X86_64_SSEUP_CLASS;
5143 classes[0] = X86_64_SSE_CLASS;
5146 classes[0] = X86_64_SSEDF_CLASS;
5147 classes[1] = X86_64_SSEDF_CLASS;
5150 classes[0] = X86_64_COMPLEX_X87_CLASS;
5153 /* This modes is larger than 16 bytes. */
5161 classes[0] = X86_64_SSE_CLASS;
5162 classes[1] = X86_64_SSEUP_CLASS;
5163 classes[2] = X86_64_SSEUP_CLASS;
5164 classes[3] = X86_64_SSEUP_CLASS;
5172 classes[0] = X86_64_SSE_CLASS;
5173 classes[1] = X86_64_SSEUP_CLASS;
5180 classes[0] = X86_64_SSE_CLASS;
5186 gcc_assert (VECTOR_MODE_P (mode));
5191 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5193 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5194 classes[0] = X86_64_INTEGERSI_CLASS;
5196 classes[0] = X86_64_INTEGER_CLASS;
5197 classes[1] = X86_64_INTEGER_CLASS;
5198 return 1 + (bytes > 8);
5202 /* Examine the argument and return set number of register required in each
5203 class. Return 0 iff parameter should be passed in memory. */
5205 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5206 int *int_nregs, int *sse_nregs)
5208 enum x86_64_reg_class regclass[MAX_CLASSES];
5209 int n = classify_argument (mode, type, regclass, 0);
5215 for (n--; n >= 0; n--)
5216 switch (regclass[n])
5218 case X86_64_INTEGER_CLASS:
5219 case X86_64_INTEGERSI_CLASS:
5222 case X86_64_SSE_CLASS:
5223 case X86_64_SSESF_CLASS:
5224 case X86_64_SSEDF_CLASS:
5227 case X86_64_NO_CLASS:
5228 case X86_64_SSEUP_CLASS:
5230 case X86_64_X87_CLASS:
5231 case X86_64_X87UP_CLASS:
5235 case X86_64_COMPLEX_X87_CLASS:
5236 return in_return ? 2 : 0;
5237 case X86_64_MEMORY_CLASS:
5243 /* Construct container for the argument used by GCC interface. See
5244 FUNCTION_ARG for the detailed description. */
5247 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5248 const_tree type, int in_return, int nintregs, int nsseregs,
5249 const int *intreg, int sse_regno)
5251 /* The following variables hold the static issued_error state. */
5252 static bool issued_sse_arg_error;
5253 static bool issued_sse_ret_error;
5254 static bool issued_x87_ret_error;
5256 enum machine_mode tmpmode;
5258 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5259 enum x86_64_reg_class regclass[MAX_CLASSES];
5263 int needed_sseregs, needed_intregs;
5264 rtx exp[MAX_CLASSES];
5267 n = classify_argument (mode, type, regclass, 0);
5270 if (!examine_argument (mode, type, in_return, &needed_intregs,
5273 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5276 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5277 some less clueful developer tries to use floating-point anyway. */
5278 if (needed_sseregs && !TARGET_SSE)
5282 if (!issued_sse_ret_error)
5284 error ("SSE register return with SSE disabled");
5285 issued_sse_ret_error = true;
5288 else if (!issued_sse_arg_error)
5290 error ("SSE register argument with SSE disabled");
5291 issued_sse_arg_error = true;
5296 /* Likewise, error if the ABI requires us to return values in the
5297 x87 registers and the user specified -mno-80387. */
5298 if (!TARGET_80387 && in_return)
5299 for (i = 0; i < n; i++)
5300 if (regclass[i] == X86_64_X87_CLASS
5301 || regclass[i] == X86_64_X87UP_CLASS
5302 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5304 if (!issued_x87_ret_error)
5306 error ("x87 register return with x87 disabled");
5307 issued_x87_ret_error = true;
5312 /* First construct simple cases. Avoid SCmode, since we want to use
5313 single register to pass this type. */
5314 if (n == 1 && mode != SCmode)
5315 switch (regclass[0])
5317 case X86_64_INTEGER_CLASS:
5318 case X86_64_INTEGERSI_CLASS:
5319 return gen_rtx_REG (mode, intreg[0]);
5320 case X86_64_SSE_CLASS:
5321 case X86_64_SSESF_CLASS:
5322 case X86_64_SSEDF_CLASS:
5323 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5324 case X86_64_X87_CLASS:
5325 case X86_64_COMPLEX_X87_CLASS:
5326 return gen_rtx_REG (mode, FIRST_STACK_REG);
5327 case X86_64_NO_CLASS:
5328 /* Zero sized array, struct or class. */
5333 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5334 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5335 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5337 && regclass[0] == X86_64_SSE_CLASS
5338 && regclass[1] == X86_64_SSEUP_CLASS
5339 && regclass[2] == X86_64_SSEUP_CLASS
5340 && regclass[3] == X86_64_SSEUP_CLASS
5342 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5345 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5346 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5347 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5348 && regclass[1] == X86_64_INTEGER_CLASS
5349 && (mode == CDImode || mode == TImode || mode == TFmode)
5350 && intreg[0] + 1 == intreg[1])
5351 return gen_rtx_REG (mode, intreg[0]);
5353 /* Otherwise figure out the entries of the PARALLEL. */
5354 for (i = 0; i < n; i++)
5358 switch (regclass[i])
5360 case X86_64_NO_CLASS:
5362 case X86_64_INTEGER_CLASS:
5363 case X86_64_INTEGERSI_CLASS:
5364 /* Merge TImodes on aligned occasions here too. */
5365 if (i * 8 + 8 > bytes)
5366 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5367 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5371 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5372 if (tmpmode == BLKmode)
5374 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5375 gen_rtx_REG (tmpmode, *intreg),
5379 case X86_64_SSESF_CLASS:
5380 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5381 gen_rtx_REG (SFmode,
5382 SSE_REGNO (sse_regno)),
5386 case X86_64_SSEDF_CLASS:
5387 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5388 gen_rtx_REG (DFmode,
5389 SSE_REGNO (sse_regno)),
5393 case X86_64_SSE_CLASS:
5401 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5411 && regclass[1] == X86_64_SSEUP_CLASS
5412 && regclass[2] == X86_64_SSEUP_CLASS
5413 && regclass[3] == X86_64_SSEUP_CLASS);
5420 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5421 gen_rtx_REG (tmpmode,
5422 SSE_REGNO (sse_regno)),
5431 /* Empty aligned struct, union or class. */
5435 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5436 for (i = 0; i < nexps; i++)
5437 XVECEXP (ret, 0, i) = exp [i];
5441 /* Update the data in CUM to advance over an argument of mode MODE
5442 and data type TYPE. (TYPE is null for libcalls where that information
5443 may not be available.) */
5446 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5447 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5463 cum->words += words;
5464 cum->nregs -= words;
5465 cum->regno += words;
5467 if (cum->nregs <= 0)
5475 /* OImode shouldn't be used directly. */
5479 if (cum->float_in_sse < 2)
5482 if (cum->float_in_sse < 1)
5499 if (!type || !AGGREGATE_TYPE_P (type))
5501 cum->sse_words += words;
5502 cum->sse_nregs -= 1;
5503 cum->sse_regno += 1;
5504 if (cum->sse_nregs <= 0)
5517 if (!type || !AGGREGATE_TYPE_P (type))
5519 cum->mmx_words += words;
5520 cum->mmx_nregs -= 1;
5521 cum->mmx_regno += 1;
5522 if (cum->mmx_nregs <= 0)
5533 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5534 tree type, HOST_WIDE_INT words, int named)
5536 int int_nregs, sse_nregs;
5538 /* Unnamed 256bit vector mode parameters are passed on stack. */
5539 if (!named && VALID_AVX256_REG_MODE (mode))
5542 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5543 cum->words += words;
5544 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5546 cum->nregs -= int_nregs;
5547 cum->sse_nregs -= sse_nregs;
5548 cum->regno += int_nregs;
5549 cum->sse_regno += sse_nregs;
5552 cum->words += words;
5556 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5557 HOST_WIDE_INT words)
5559 /* Otherwise, this should be passed indirect. */
5560 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5562 cum->words += words;
5571 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5572 tree type, int named)
5574 HOST_WIDE_INT bytes, words;
5576 if (mode == BLKmode)
5577 bytes = int_size_in_bytes (type);
5579 bytes = GET_MODE_SIZE (mode);
5580 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5583 mode = type_natural_mode (type, NULL);
5585 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5586 function_arg_advance_ms_64 (cum, bytes, words);
5587 else if (TARGET_64BIT)
5588 function_arg_advance_64 (cum, mode, type, words, named);
5590 function_arg_advance_32 (cum, mode, type, bytes, words);
5593 /* Define where to put the arguments to a function.
5594 Value is zero to push the argument on the stack,
5595 or a hard register in which to store the argument.
5597 MODE is the argument's machine mode.
5598 TYPE is the data type of the argument (as a tree).
5599 This is null for libcalls where that information may
5601 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5602 the preceding args and about the function being called.
5603 NAMED is nonzero if this argument is a named parameter
5604 (otherwise it is an extra parameter matching an ellipsis). */
5607 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5608 enum machine_mode orig_mode, tree type,
5609 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5611 static bool warnedsse, warnedmmx;
5613 /* Avoid the AL settings for the Unix64 ABI. */
5614 if (mode == VOIDmode)
5630 if (words <= cum->nregs)
5632 int regno = cum->regno;
5634 /* Fastcall allocates the first two DWORD (SImode) or
5635 smaller arguments to ECX and EDX if it isn't an
5641 || (type && AGGREGATE_TYPE_P (type)))
5644 /* ECX not EAX is the first allocated register. */
5645 if (regno == AX_REG)
5648 return gen_rtx_REG (mode, regno);
5653 if (cum->float_in_sse < 2)
5656 if (cum->float_in_sse < 1)
5660 /* In 32bit, we pass TImode in xmm registers. */
5667 if (!type || !AGGREGATE_TYPE_P (type))
5669 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5672 warning (0, "SSE vector argument without SSE enabled "
5676 return gen_reg_or_parallel (mode, orig_mode,
5677 cum->sse_regno + FIRST_SSE_REG);
5682 /* OImode shouldn't be used directly. */
5691 if (!type || !AGGREGATE_TYPE_P (type))
5694 return gen_reg_or_parallel (mode, orig_mode,
5695 cum->sse_regno + FIRST_SSE_REG);
5704 if (!type || !AGGREGATE_TYPE_P (type))
5706 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5709 warning (0, "MMX vector argument without MMX enabled "
5713 return gen_reg_or_parallel (mode, orig_mode,
5714 cum->mmx_regno + FIRST_MMX_REG);
5723 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5724 enum machine_mode orig_mode, tree type, int named)
5726 /* Handle a hidden AL argument containing number of registers
5727 for varargs x86-64 functions. */
5728 if (mode == VOIDmode)
5729 return GEN_INT (cum->maybe_vaarg
5730 ? (cum->sse_nregs < 0
5731 ? (cum->call_abi == DEFAULT_ABI
5733 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5734 : X64_SSE_REGPARM_MAX))
5749 /* Unnamed 256bit vector mode parameters are passed on stack. */
5755 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5757 &x86_64_int_parameter_registers [cum->regno],
5762 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5763 enum machine_mode orig_mode, int named,
5764 HOST_WIDE_INT bytes)
5768 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5769 We use value of -2 to specify that current function call is MSABI. */
5770 if (mode == VOIDmode)
5771 return GEN_INT (-2);
5773 /* If we've run out of registers, it goes on the stack. */
5774 if (cum->nregs == 0)
5777 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5779 /* Only floating point modes are passed in anything but integer regs. */
5780 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5783 regno = cum->regno + FIRST_SSE_REG;
5788 /* Unnamed floating parameters are passed in both the
5789 SSE and integer registers. */
5790 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5791 t2 = gen_rtx_REG (mode, regno);
5792 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5793 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5794 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5797 /* Handle aggregated types passed in register. */
5798 if (orig_mode == BLKmode)
5800 if (bytes > 0 && bytes <= 8)
5801 mode = (bytes > 4 ? DImode : SImode);
5802 if (mode == BLKmode)
5806 return gen_reg_or_parallel (mode, orig_mode, regno);
5810 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5811 tree type, int named)
5813 enum machine_mode mode = omode;
5814 HOST_WIDE_INT bytes, words;
5816 if (mode == BLKmode)
5817 bytes = int_size_in_bytes (type);
5819 bytes = GET_MODE_SIZE (mode);
5820 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5822 /* To simplify the code below, represent vector types with a vector mode
5823 even if MMX/SSE are not active. */
5824 if (type && TREE_CODE (type) == VECTOR_TYPE)
5825 mode = type_natural_mode (type, cum);
5827 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5828 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5829 else if (TARGET_64BIT)
5830 return function_arg_64 (cum, mode, omode, type, named);
5832 return function_arg_32 (cum, mode, omode, type, bytes, words);
5835 /* A C expression that indicates when an argument must be passed by
5836 reference. If nonzero for an argument, a copy of that argument is
5837 made in memory and a pointer to the argument is passed instead of
5838 the argument itself. The pointer is passed in whatever way is
5839 appropriate for passing a pointer to that type. */
5842 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5843 enum machine_mode mode ATTRIBUTE_UNUSED,
5844 const_tree type, bool named ATTRIBUTE_UNUSED)
5846 /* See Windows x64 Software Convention. */
5847 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5849 int msize = (int) GET_MODE_SIZE (mode);
5852 /* Arrays are passed by reference. */
5853 if (TREE_CODE (type) == ARRAY_TYPE)
5856 if (AGGREGATE_TYPE_P (type))
5858 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5859 are passed by reference. */
5860 msize = int_size_in_bytes (type);
5864 /* __m128 is passed by reference. */
5866 case 1: case 2: case 4: case 8:
5872 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5878 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5881 contains_aligned_value_p (tree type)
5883 enum machine_mode mode = TYPE_MODE (type);
5884 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5888 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5890 if (TYPE_ALIGN (type) < 128)
5893 if (AGGREGATE_TYPE_P (type))
5895 /* Walk the aggregates recursively. */
5896 switch (TREE_CODE (type))
5900 case QUAL_UNION_TYPE:
5904 /* Walk all the structure fields. */
5905 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5907 if (TREE_CODE (field) == FIELD_DECL
5908 && contains_aligned_value_p (TREE_TYPE (field)))
5915 /* Just for use if some languages passes arrays by value. */
5916 if (contains_aligned_value_p (TREE_TYPE (type)))
5927 /* Gives the alignment boundary, in bits, of an argument with the
5928 specified mode and type. */
5931 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5936 /* Since canonical type is used for call, we convert it to
5937 canonical type if needed. */
5938 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5939 type = TYPE_CANONICAL (type);
5940 align = TYPE_ALIGN (type);
5943 align = GET_MODE_ALIGNMENT (mode);
5944 if (align < PARM_BOUNDARY)
5945 align = PARM_BOUNDARY;
5946 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5947 natural boundaries. */
5948 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5950 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5951 make an exception for SSE modes since these require 128bit
5954 The handling here differs from field_alignment. ICC aligns MMX
5955 arguments to 4 byte boundaries, while structure fields are aligned
5956 to 8 byte boundaries. */
5959 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5960 align = PARM_BOUNDARY;
5964 if (!contains_aligned_value_p (type))
5965 align = PARM_BOUNDARY;
5968 if (align > BIGGEST_ALIGNMENT)
5969 align = BIGGEST_ALIGNMENT;
5973 /* Return true if N is a possible register number of function value. */
5976 ix86_function_value_regno_p (int regno)
5983 case FIRST_FLOAT_REG:
5984 /* TODO: The function should depend on current function ABI but
5985 builtins.c would need updating then. Therefore we use the
5987 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
5989 return TARGET_FLOAT_RETURNS_IN_80387;
5995 if (TARGET_MACHO || TARGET_64BIT)
6003 /* Define how to find the value returned by a function.
6004 VALTYPE is the data type of the value (as a tree).
6005 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6006 otherwise, FUNC is 0. */
6009 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6010 const_tree fntype, const_tree fn)
6014 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6015 we normally prevent this case when mmx is not available. However
6016 some ABIs may require the result to be returned like DImode. */
6017 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6018 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6020 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6021 we prevent this case when sse is not available. However some ABIs
6022 may require the result to be returned like integer TImode. */
6023 else if (mode == TImode
6024 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6025 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6027 /* 32-byte vector modes in %ymm0. */
6028 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6029 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6031 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6032 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6033 regno = FIRST_FLOAT_REG;
6035 /* Most things go in %eax. */
6038 /* Override FP return register with %xmm0 for local functions when
6039 SSE math is enabled or for functions with sseregparm attribute. */
6040 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6042 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6043 if ((sse_level >= 1 && mode == SFmode)
6044 || (sse_level == 2 && mode == DFmode))
6045 regno = FIRST_SSE_REG;
6048 /* OImode shouldn't be used directly. */
6049 gcc_assert (mode != OImode);
6051 return gen_rtx_REG (orig_mode, regno);
6055 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6060 /* Handle libcalls, which don't provide a type node. */
6061 if (valtype == NULL)
6073 return gen_rtx_REG (mode, FIRST_SSE_REG);
6076 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6080 return gen_rtx_REG (mode, AX_REG);
6084 ret = construct_container (mode, orig_mode, valtype, 1,
6085 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6086 x86_64_int_return_registers, 0);
6088 /* For zero sized structures, construct_container returns NULL, but we
6089 need to keep rest of compiler happy by returning meaningful value. */
6091 ret = gen_rtx_REG (orig_mode, AX_REG);
6097 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6099 unsigned int regno = AX_REG;
6103 switch (GET_MODE_SIZE (mode))
6106 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6107 && !COMPLEX_MODE_P (mode))
6108 regno = FIRST_SSE_REG;
6112 if (mode == SFmode || mode == DFmode)
6113 regno = FIRST_SSE_REG;
6119 return gen_rtx_REG (orig_mode, regno);
6123 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6124 enum machine_mode orig_mode, enum machine_mode mode)
6126 const_tree fn, fntype;
6129 if (fntype_or_decl && DECL_P (fntype_or_decl))
6130 fn = fntype_or_decl;
6131 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6133 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6134 return function_value_ms_64 (orig_mode, mode);
6135 else if (TARGET_64BIT)
6136 return function_value_64 (orig_mode, mode, valtype);
6138 return function_value_32 (orig_mode, mode, fntype, fn);
6142 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6143 bool outgoing ATTRIBUTE_UNUSED)
6145 enum machine_mode mode, orig_mode;
6147 orig_mode = TYPE_MODE (valtype);
6148 mode = type_natural_mode (valtype, NULL);
6149 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6153 ix86_libcall_value (enum machine_mode mode)
6155 return ix86_function_value_1 (NULL, NULL, mode, mode);
6158 /* Return true iff type is returned in memory. */
6160 static int ATTRIBUTE_UNUSED
6161 return_in_memory_32 (const_tree type, enum machine_mode mode)
6165 if (mode == BLKmode)
6168 size = int_size_in_bytes (type);
6170 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6173 if (VECTOR_MODE_P (mode) || mode == TImode)
6175 /* User-created vectors small enough to fit in EAX. */
6179 /* MMX/3dNow values are returned in MM0,
6180 except when it doesn't exits. */
6182 return (TARGET_MMX ? 0 : 1);
6184 /* SSE values are returned in XMM0, except when it doesn't exist. */
6186 return (TARGET_SSE ? 0 : 1);
6188 /* AVX values are returned in YMM0, except when it doesn't exist. */
6190 return TARGET_AVX ? 0 : 1;
6199 /* OImode shouldn't be used directly. */
6200 gcc_assert (mode != OImode);
6205 static int ATTRIBUTE_UNUSED
6206 return_in_memory_64 (const_tree type, enum machine_mode mode)
6208 int needed_intregs, needed_sseregs;
6209 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6212 static int ATTRIBUTE_UNUSED
6213 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6215 HOST_WIDE_INT size = int_size_in_bytes (type);
6217 /* __m128 is returned in xmm0. */
6218 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6219 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6222 /* Otherwise, the size must be exactly in [1248]. */
6223 return (size != 1 && size != 2 && size != 4 && size != 8);
6227 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6229 #ifdef SUBTARGET_RETURN_IN_MEMORY
6230 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6232 const enum machine_mode mode = type_natural_mode (type, NULL);
6236 if (ix86_function_type_abi (fntype) == MS_ABI)
6237 return return_in_memory_ms_64 (type, mode);
6239 return return_in_memory_64 (type, mode);
6242 return return_in_memory_32 (type, mode);
6246 /* Return false iff TYPE is returned in memory. This version is used
6247 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6248 but differs notably in that when MMX is available, 8-byte vectors
6249 are returned in memory, rather than in MMX registers. */
6252 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6255 enum machine_mode mode = type_natural_mode (type, NULL);
6258 return return_in_memory_64 (type, mode);
6260 if (mode == BLKmode)
6263 size = int_size_in_bytes (type);
6265 if (VECTOR_MODE_P (mode))
6267 /* Return in memory only if MMX registers *are* available. This
6268 seems backwards, but it is consistent with the existing
6275 else if (mode == TImode)
6277 else if (mode == XFmode)
6283 /* When returning SSE vector types, we have a choice of either
6284 (1) being abi incompatible with a -march switch, or
6285 (2) generating an error.
6286 Given no good solution, I think the safest thing is one warning.
6287 The user won't be able to use -Werror, but....
6289 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6290 called in response to actually generating a caller or callee that
6291 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6292 via aggregate_value_p for general type probing from tree-ssa. */
6295 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6297 static bool warnedsse, warnedmmx;
6299 if (!TARGET_64BIT && type)
6301 /* Look at the return type of the function, not the function type. */
6302 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6304 if (!TARGET_SSE && !warnedsse)
6307 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6310 warning (0, "SSE vector return without SSE enabled "
6315 if (!TARGET_MMX && !warnedmmx)
6317 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6320 warning (0, "MMX vector return without MMX enabled "
6330 /* Create the va_list data type. */
6332 /* Returns the calling convention specific va_list date type.
6333 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6336 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6338 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6340 /* For i386 we use plain pointer to argument area. */
6341 if (!TARGET_64BIT || abi == MS_ABI)
6342 return build_pointer_type (char_type_node);
6344 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6345 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6347 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6348 unsigned_type_node);
6349 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6350 unsigned_type_node);
6351 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6353 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6356 va_list_gpr_counter_field = f_gpr;
6357 va_list_fpr_counter_field = f_fpr;
6359 DECL_FIELD_CONTEXT (f_gpr) = record;
6360 DECL_FIELD_CONTEXT (f_fpr) = record;
6361 DECL_FIELD_CONTEXT (f_ovf) = record;
6362 DECL_FIELD_CONTEXT (f_sav) = record;
6364 TREE_CHAIN (record) = type_decl;
6365 TYPE_NAME (record) = type_decl;
6366 TYPE_FIELDS (record) = f_gpr;
6367 TREE_CHAIN (f_gpr) = f_fpr;
6368 TREE_CHAIN (f_fpr) = f_ovf;
6369 TREE_CHAIN (f_ovf) = f_sav;
6371 layout_type (record);
6373 /* The correct type is an array type of one element. */
6374 return build_array_type (record, build_index_type (size_zero_node));
6377 /* Setup the builtin va_list data type and for 64-bit the additional
6378 calling convention specific va_list data types. */
6381 ix86_build_builtin_va_list (void)
6383 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6385 /* Initialize abi specific va_list builtin types. */
6389 if (DEFAULT_ABI == MS_ABI)
6391 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6392 if (TREE_CODE (t) != RECORD_TYPE)
6393 t = build_variant_type_copy (t);
6394 sysv_va_list_type_node = t;
6399 if (TREE_CODE (t) != RECORD_TYPE)
6400 t = build_variant_type_copy (t);
6401 sysv_va_list_type_node = t;
6403 if (DEFAULT_ABI != MS_ABI)
6405 t = ix86_build_builtin_va_list_abi (MS_ABI);
6406 if (TREE_CODE (t) != RECORD_TYPE)
6407 t = build_variant_type_copy (t);
6408 ms_va_list_type_node = t;
6413 if (TREE_CODE (t) != RECORD_TYPE)
6414 t = build_variant_type_copy (t);
6415 ms_va_list_type_node = t;
6422 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6425 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6434 int regparm = ix86_regparm;
6436 if (cum->call_abi != DEFAULT_ABI)
6437 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6439 /* GPR size of varargs save area. */
6440 if (cfun->va_list_gpr_size)
6441 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6443 ix86_varargs_gpr_size = 0;
6445 /* FPR size of varargs save area. We don't need it if we don't pass
6446 anything in SSE registers. */
6447 if (cum->sse_nregs && cfun->va_list_fpr_size)
6448 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6450 ix86_varargs_fpr_size = 0;
6452 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6455 save_area = frame_pointer_rtx;
6456 set = get_varargs_alias_set ();
6458 for (i = cum->regno;
6460 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6463 mem = gen_rtx_MEM (Pmode,
6464 plus_constant (save_area, i * UNITS_PER_WORD));
6465 MEM_NOTRAP_P (mem) = 1;
6466 set_mem_alias_set (mem, set);
6467 emit_move_insn (mem, gen_rtx_REG (Pmode,
6468 x86_64_int_parameter_registers[i]));
6471 if (ix86_varargs_fpr_size)
6473 /* Now emit code to save SSE registers. The AX parameter contains number
6474 of SSE parameter registers used to call this function. We use
6475 sse_prologue_save insn template that produces computed jump across
6476 SSE saves. We need some preparation work to get this working. */
6478 label = gen_label_rtx ();
6479 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6481 /* Compute address to jump to :
6482 label - eax*4 + nnamed_sse_arguments*4 Or
6483 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6484 tmp_reg = gen_reg_rtx (Pmode);
6485 nsse_reg = gen_reg_rtx (Pmode);
6486 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6487 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6488 gen_rtx_MULT (Pmode, nsse_reg,
6491 /* vmovaps is one byte longer than movaps. */
6493 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6494 gen_rtx_PLUS (Pmode, tmp_reg,
6500 gen_rtx_CONST (DImode,
6501 gen_rtx_PLUS (DImode,
6503 GEN_INT (cum->sse_regno
6504 * (TARGET_AVX ? 5 : 4)))));
6506 emit_move_insn (nsse_reg, label_ref);
6507 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6509 /* Compute address of memory block we save into. We always use pointer
6510 pointing 127 bytes after first byte to store - this is needed to keep
6511 instruction size limited by 4 bytes (5 bytes for AVX) with one
6512 byte displacement. */
6513 tmp_reg = gen_reg_rtx (Pmode);
6514 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6515 plus_constant (save_area,
6516 ix86_varargs_gpr_size + 127)));
6517 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6518 MEM_NOTRAP_P (mem) = 1;
6519 set_mem_alias_set (mem, set);
6520 set_mem_align (mem, BITS_PER_WORD);
6522 /* And finally do the dirty job! */
6523 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6524 GEN_INT (cum->sse_regno), label));
6529 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6531 alias_set_type set = get_varargs_alias_set ();
6534 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6538 mem = gen_rtx_MEM (Pmode,
6539 plus_constant (virtual_incoming_args_rtx,
6540 i * UNITS_PER_WORD));
6541 MEM_NOTRAP_P (mem) = 1;
6542 set_mem_alias_set (mem, set);
6544 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6545 emit_move_insn (mem, reg);
6550 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6551 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6554 CUMULATIVE_ARGS next_cum;
6557 /* This argument doesn't appear to be used anymore. Which is good,
6558 because the old code here didn't suppress rtl generation. */
6559 gcc_assert (!no_rtl);
6564 fntype = TREE_TYPE (current_function_decl);
6566 /* For varargs, we do not want to skip the dummy va_dcl argument.
6567 For stdargs, we do want to skip the last named argument. */
6569 if (stdarg_p (fntype))
6570 function_arg_advance (&next_cum, mode, type, 1);
6572 if (cum->call_abi == MS_ABI)
6573 setup_incoming_varargs_ms_64 (&next_cum);
6575 setup_incoming_varargs_64 (&next_cum);
6578 /* Checks if TYPE is of kind va_list char *. */
6581 is_va_list_char_pointer (tree type)
6585 /* For 32-bit it is always true. */
6588 canonic = ix86_canonical_va_list_type (type);
6589 return (canonic == ms_va_list_type_node
6590 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6593 /* Implement va_start. */
6596 ix86_va_start (tree valist, rtx nextarg)
6598 HOST_WIDE_INT words, n_gpr, n_fpr;
6599 tree f_gpr, f_fpr, f_ovf, f_sav;
6600 tree gpr, fpr, ovf, sav, t;
6603 /* Only 64bit target needs something special. */
6604 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6606 std_expand_builtin_va_start (valist, nextarg);
6610 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6611 f_fpr = TREE_CHAIN (f_gpr);
6612 f_ovf = TREE_CHAIN (f_fpr);
6613 f_sav = TREE_CHAIN (f_ovf);
6615 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6616 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6617 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6618 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6619 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6621 /* Count number of gp and fp argument registers used. */
6622 words = crtl->args.info.words;
6623 n_gpr = crtl->args.info.regno;
6624 n_fpr = crtl->args.info.sse_regno;
6626 if (cfun->va_list_gpr_size)
6628 type = TREE_TYPE (gpr);
6629 t = build2 (MODIFY_EXPR, type,
6630 gpr, build_int_cst (type, n_gpr * 8));
6631 TREE_SIDE_EFFECTS (t) = 1;
6632 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6635 if (TARGET_SSE && cfun->va_list_fpr_size)
6637 type = TREE_TYPE (fpr);
6638 t = build2 (MODIFY_EXPR, type, fpr,
6639 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6640 TREE_SIDE_EFFECTS (t) = 1;
6641 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6644 /* Find the overflow area. */
6645 type = TREE_TYPE (ovf);
6646 t = make_tree (type, crtl->args.internal_arg_pointer);
6648 t = build2 (POINTER_PLUS_EXPR, type, t,
6649 size_int (words * UNITS_PER_WORD));
6650 t = build2 (MODIFY_EXPR, type, ovf, t);
6651 TREE_SIDE_EFFECTS (t) = 1;
6652 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6654 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6656 /* Find the register save area.
6657 Prologue of the function save it right above stack frame. */
6658 type = TREE_TYPE (sav);
6659 t = make_tree (type, frame_pointer_rtx);
6660 if (!ix86_varargs_gpr_size)
6661 t = build2 (POINTER_PLUS_EXPR, type, t,
6662 size_int (-8 * X86_64_REGPARM_MAX));
6663 t = build2 (MODIFY_EXPR, type, sav, t);
6664 TREE_SIDE_EFFECTS (t) = 1;
6665 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6669 /* Implement va_arg. */
6672 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6675 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6676 tree f_gpr, f_fpr, f_ovf, f_sav;
6677 tree gpr, fpr, ovf, sav, t;
6679 tree lab_false, lab_over = NULL_TREE;
6684 enum machine_mode nat_mode;
6687 /* Only 64bit target needs something special. */
6688 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6689 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6691 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6692 f_fpr = TREE_CHAIN (f_gpr);
6693 f_ovf = TREE_CHAIN (f_fpr);
6694 f_sav = TREE_CHAIN (f_ovf);
6696 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6697 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6698 valist = build_va_arg_indirect_ref (valist);
6699 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6700 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6701 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6703 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6705 type = build_pointer_type (type);
6706 size = int_size_in_bytes (type);
6707 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6709 nat_mode = type_natural_mode (type, NULL);
6718 /* Unnamed 256bit vector mode parameters are passed on stack. */
6719 if (ix86_cfun_abi () == SYSV_ABI)
6726 container = construct_container (nat_mode, TYPE_MODE (type),
6727 type, 0, X86_64_REGPARM_MAX,
6728 X86_64_SSE_REGPARM_MAX, intreg,
6733 /* Pull the value out of the saved registers. */
6735 addr = create_tmp_var (ptr_type_node, "addr");
6736 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6740 int needed_intregs, needed_sseregs;
6742 tree int_addr, sse_addr;
6744 lab_false = create_artificial_label ();
6745 lab_over = create_artificial_label ();
6747 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6749 need_temp = (!REG_P (container)
6750 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6751 || TYPE_ALIGN (type) > 128));
6753 /* In case we are passing structure, verify that it is consecutive block
6754 on the register save area. If not we need to do moves. */
6755 if (!need_temp && !REG_P (container))
6757 /* Verify that all registers are strictly consecutive */
6758 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6762 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6764 rtx slot = XVECEXP (container, 0, i);
6765 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6766 || INTVAL (XEXP (slot, 1)) != i * 16)
6774 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6776 rtx slot = XVECEXP (container, 0, i);
6777 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6778 || INTVAL (XEXP (slot, 1)) != i * 8)
6790 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6791 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6792 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6793 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6796 /* First ensure that we fit completely in registers. */
6799 t = build_int_cst (TREE_TYPE (gpr),
6800 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6801 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6802 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6803 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6804 gimplify_and_add (t, pre_p);
6808 t = build_int_cst (TREE_TYPE (fpr),
6809 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6810 + X86_64_REGPARM_MAX * 8);
6811 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6812 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6813 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6814 gimplify_and_add (t, pre_p);
6817 /* Compute index to start of area used for integer regs. */
6820 /* int_addr = gpr + sav; */
6821 t = fold_convert (sizetype, gpr);
6822 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6823 gimplify_assign (int_addr, t, pre_p);
6827 /* sse_addr = fpr + sav; */
6828 t = fold_convert (sizetype, fpr);
6829 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6830 gimplify_assign (sse_addr, t, pre_p);
6835 tree temp = create_tmp_var (type, "va_arg_tmp");
6838 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6839 gimplify_assign (addr, t, pre_p);
6841 for (i = 0; i < XVECLEN (container, 0); i++)
6843 rtx slot = XVECEXP (container, 0, i);
6844 rtx reg = XEXP (slot, 0);
6845 enum machine_mode mode = GET_MODE (reg);
6846 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6847 tree addr_type = build_pointer_type (piece_type);
6848 tree daddr_type = build_pointer_type_for_mode (piece_type,
6852 tree dest_addr, dest;
6854 if (SSE_REGNO_P (REGNO (reg)))
6856 src_addr = sse_addr;
6857 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6861 src_addr = int_addr;
6862 src_offset = REGNO (reg) * 8;
6864 src_addr = fold_convert (addr_type, src_addr);
6865 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6866 size_int (src_offset));
6867 src = build_va_arg_indirect_ref (src_addr);
6869 dest_addr = fold_convert (daddr_type, addr);
6870 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6871 size_int (INTVAL (XEXP (slot, 1))));
6872 dest = build_va_arg_indirect_ref (dest_addr);
6874 gimplify_assign (dest, src, pre_p);
6880 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6881 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6882 gimplify_assign (gpr, t, pre_p);
6887 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6888 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6889 gimplify_assign (fpr, t, pre_p);
6892 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6894 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6897 /* ... otherwise out of the overflow area. */
6899 /* When we align parameter on stack for caller, if the parameter
6900 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6901 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6902 here with caller. */
6903 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6904 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6905 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6907 /* Care for on-stack alignment if needed. */
6908 if (arg_boundary <= 64
6909 || integer_zerop (TYPE_SIZE (type)))
6913 HOST_WIDE_INT align = arg_boundary / 8;
6914 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6915 size_int (align - 1));
6916 t = fold_convert (sizetype, t);
6917 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6919 t = fold_convert (TREE_TYPE (ovf), t);
6921 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6922 gimplify_assign (addr, t, pre_p);
6924 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6925 size_int (rsize * UNITS_PER_WORD));
6926 gimplify_assign (unshare_expr (ovf), t, pre_p);
6929 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6931 ptrtype = build_pointer_type (type);
6932 addr = fold_convert (ptrtype, addr);
6935 addr = build_va_arg_indirect_ref (addr);
6936 return build_va_arg_indirect_ref (addr);
6939 /* Return nonzero if OPNUM's MEM should be matched
6940 in movabs* patterns. */
6943 ix86_check_movabs (rtx insn, int opnum)
6947 set = PATTERN (insn);
6948 if (GET_CODE (set) == PARALLEL)
6949 set = XVECEXP (set, 0, 0);
6950 gcc_assert (GET_CODE (set) == SET);
6951 mem = XEXP (set, opnum);
6952 while (GET_CODE (mem) == SUBREG)
6953 mem = SUBREG_REG (mem);
6954 gcc_assert (MEM_P (mem));
6955 return (volatile_ok || !MEM_VOLATILE_P (mem));
6958 /* Initialize the table of extra 80387 mathematical constants. */
6961 init_ext_80387_constants (void)
6963 static const char * cst[5] =
6965 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6966 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6967 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6968 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6969 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6973 for (i = 0; i < 5; i++)
6975 real_from_string (&ext_80387_constants_table[i], cst[i]);
6976 /* Ensure each constant is rounded to XFmode precision. */
6977 real_convert (&ext_80387_constants_table[i],
6978 XFmode, &ext_80387_constants_table[i]);
6981 ext_80387_constants_init = 1;
6984 /* Return true if the constant is something that can be loaded with
6985 a special instruction. */
6988 standard_80387_constant_p (rtx x)
6990 enum machine_mode mode = GET_MODE (x);
6994 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
6997 if (x == CONST0_RTX (mode))
6999 if (x == CONST1_RTX (mode))
7002 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7004 /* For XFmode constants, try to find a special 80387 instruction when
7005 optimizing for size or on those CPUs that benefit from them. */
7007 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7011 if (! ext_80387_constants_init)
7012 init_ext_80387_constants ();
7014 for (i = 0; i < 5; i++)
7015 if (real_identical (&r, &ext_80387_constants_table[i]))
7019 /* Load of the constant -0.0 or -1.0 will be split as
7020 fldz;fchs or fld1;fchs sequence. */
7021 if (real_isnegzero (&r))
7023 if (real_identical (&r, &dconstm1))
7029 /* Return the opcode of the special instruction to be used to load
7033 standard_80387_constant_opcode (rtx x)
7035 switch (standard_80387_constant_p (x))
7059 /* Return the CONST_DOUBLE representing the 80387 constant that is
7060 loaded by the specified special instruction. The argument IDX
7061 matches the return value from standard_80387_constant_p. */
7064 standard_80387_constant_rtx (int idx)
7068 if (! ext_80387_constants_init)
7069 init_ext_80387_constants ();
7085 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7089 /* Return 1 if mode is a valid mode for sse. */
7091 standard_sse_mode_p (enum machine_mode mode)
7108 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7109 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7110 modes and AVX is enabled. */
7113 standard_sse_constant_p (rtx x)
7115 enum machine_mode mode = GET_MODE (x);
7117 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7119 if (vector_all_ones_operand (x, mode))
7121 if (standard_sse_mode_p (mode))
7122 return TARGET_SSE2 ? 2 : -2;
7123 else if (VALID_AVX256_REG_MODE (mode))
7124 return TARGET_AVX ? 3 : -3;
7130 /* Return the opcode of the special instruction to be used to load
7134 standard_sse_constant_opcode (rtx insn, rtx x)
7136 switch (standard_sse_constant_p (x))
7139 switch (get_attr_mode (insn))
7142 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7144 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7146 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7148 return "vxorps\t%x0, %x0, %x0";
7150 return "vxorpd\t%x0, %x0, %x0";
7152 return "vpxor\t%x0, %x0, %x0";
7158 switch (get_attr_mode (insn))
7163 return "vpcmpeqd\t%0, %0, %0";
7169 return "pcmpeqd\t%0, %0";
7174 /* Returns 1 if OP contains a symbol reference */
7177 symbolic_reference_mentioned_p (rtx op)
7182 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7185 fmt = GET_RTX_FORMAT (GET_CODE (op));
7186 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7192 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7193 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7197 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7204 /* Return 1 if it is appropriate to emit `ret' instructions in the
7205 body of a function. Do this only if the epilogue is simple, needing a
7206 couple of insns. Prior to reloading, we can't tell how many registers
7207 must be saved, so return 0 then. Return 0 if there is no frame
7208 marker to de-allocate. */
7211 ix86_can_use_return_insn_p (void)
7213 struct ix86_frame frame;
7215 if (! reload_completed || frame_pointer_needed)
7218 /* Don't allow more than 32 pop, since that's all we can do
7219 with one instruction. */
7220 if (crtl->args.pops_args
7221 && crtl->args.size >= 32768)
7224 ix86_compute_frame_layout (&frame);
7225 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7228 /* Value should be nonzero if functions must have frame pointers.
7229 Zero means the frame pointer need not be set up (and parms may
7230 be accessed via the stack pointer) in functions that seem suitable. */
7233 ix86_frame_pointer_required (void)
7235 /* If we accessed previous frames, then the generated code expects
7236 to be able to access the saved ebp value in our frame. */
7237 if (cfun->machine->accesses_prev_frame)
7240 /* Several x86 os'es need a frame pointer for other reasons,
7241 usually pertaining to setjmp. */
7242 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7245 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7246 the frame pointer by default. Turn it back on now if we've not
7247 got a leaf function. */
7248 if (TARGET_OMIT_LEAF_FRAME_POINTER
7249 && (!current_function_is_leaf
7250 || ix86_current_function_calls_tls_descriptor))
7259 /* Record that the current function accesses previous call frames. */
7262 ix86_setup_frame_addresses (void)
7264 cfun->machine->accesses_prev_frame = 1;
7267 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7268 # define USE_HIDDEN_LINKONCE 1
7270 # define USE_HIDDEN_LINKONCE 0
7273 static int pic_labels_used;
7275 /* Fills in the label name that should be used for a pc thunk for
7276 the given register. */
7279 get_pc_thunk_name (char name[32], unsigned int regno)
7281 gcc_assert (!TARGET_64BIT);
7283 if (USE_HIDDEN_LINKONCE)
7284 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7286 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7290 /* This function generates code for -fpic that loads %ebx with
7291 the return address of the caller and then returns. */
7294 ix86_file_end (void)
7299 for (regno = 0; regno < 8; ++regno)
7303 if (! ((pic_labels_used >> regno) & 1))
7306 get_pc_thunk_name (name, regno);
7311 switch_to_section (darwin_sections[text_coal_section]);
7312 fputs ("\t.weak_definition\t", asm_out_file);
7313 assemble_name (asm_out_file, name);
7314 fputs ("\n\t.private_extern\t", asm_out_file);
7315 assemble_name (asm_out_file, name);
7316 fputs ("\n", asm_out_file);
7317 ASM_OUTPUT_LABEL (asm_out_file, name);
7321 if (USE_HIDDEN_LINKONCE)
7325 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7327 TREE_PUBLIC (decl) = 1;
7328 TREE_STATIC (decl) = 1;
7329 DECL_ONE_ONLY (decl) = 1;
7331 (*targetm.asm_out.unique_section) (decl, 0);
7332 switch_to_section (get_named_section (decl, NULL, 0));
7334 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7335 fputs ("\t.hidden\t", asm_out_file);
7336 assemble_name (asm_out_file, name);
7337 fputc ('\n', asm_out_file);
7338 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7342 switch_to_section (text_section);
7343 ASM_OUTPUT_LABEL (asm_out_file, name);
7346 xops[0] = gen_rtx_REG (Pmode, regno);
7347 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7348 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7349 output_asm_insn ("ret", xops);
7352 if (NEED_INDICATE_EXEC_STACK)
7353 file_end_indicate_exec_stack ();
7356 /* Emit code for the SET_GOT patterns. */
7359 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7365 if (TARGET_VXWORKS_RTP && flag_pic)
7367 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7368 xops[2] = gen_rtx_MEM (Pmode,
7369 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7370 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7372 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7373 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7374 an unadorned address. */
7375 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7376 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7377 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7381 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7383 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7385 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7388 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7390 output_asm_insn ("call\t%a2", xops);
7393 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7394 is what will be referenced by the Mach-O PIC subsystem. */
7396 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7399 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7400 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7403 output_asm_insn ("pop%z0\t%0", xops);
7408 get_pc_thunk_name (name, REGNO (dest));
7409 pic_labels_used |= 1 << REGNO (dest);
7411 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7412 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7413 output_asm_insn ("call\t%X2", xops);
7414 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7415 is what will be referenced by the Mach-O PIC subsystem. */
7418 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7420 targetm.asm_out.internal_label (asm_out_file, "L",
7421 CODE_LABEL_NUMBER (label));
7428 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7429 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7431 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7436 /* Generate an "push" pattern for input ARG. */
7441 return gen_rtx_SET (VOIDmode,
7443 gen_rtx_PRE_DEC (Pmode,
7444 stack_pointer_rtx)),
7448 /* Return >= 0 if there is an unused call-clobbered register available
7449 for the entire function. */
7452 ix86_select_alt_pic_regnum (void)
7454 if (current_function_is_leaf && !crtl->profile
7455 && !ix86_current_function_calls_tls_descriptor)
7458 /* Can't use the same register for both PIC and DRAP. */
7460 drap = REGNO (crtl->drap_reg);
7463 for (i = 2; i >= 0; --i)
7464 if (i != drap && !df_regs_ever_live_p (i))
7468 return INVALID_REGNUM;
7471 /* Return 1 if we need to save REGNO. */
7473 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7475 if (pic_offset_table_rtx
7476 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7477 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7479 || crtl->calls_eh_return
7480 || crtl->uses_const_pool))
7482 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7487 if (crtl->calls_eh_return && maybe_eh_return)
7492 unsigned test = EH_RETURN_DATA_REGNO (i);
7493 if (test == INVALID_REGNUM)
7501 && regno == REGNO (crtl->drap_reg))
7504 return (df_regs_ever_live_p (regno)
7505 && !call_used_regs[regno]
7506 && !fixed_regs[regno]
7507 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7510 /* Return number of saved general prupose registers. */
7513 ix86_nsaved_regs (void)
7518 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7519 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7524 /* Return number of saved SSE registrers. */
7527 ix86_nsaved_sseregs (void)
7532 if (ix86_cfun_abi () != MS_ABI)
7534 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7535 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7540 /* Given FROM and TO register numbers, say whether this elimination is
7541 allowed. If stack alignment is needed, we can only replace argument
7542 pointer with hard frame pointer, or replace frame pointer with stack
7543 pointer. Otherwise, frame pointer elimination is automatically
7544 handled and all other eliminations are valid. */
7547 ix86_can_eliminate (int from, int to)
7549 if (stack_realign_fp)
7550 return ((from == ARG_POINTER_REGNUM
7551 && to == HARD_FRAME_POINTER_REGNUM)
7552 || (from == FRAME_POINTER_REGNUM
7553 && to == STACK_POINTER_REGNUM));
7555 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7558 /* Return the offset between two registers, one to be eliminated, and the other
7559 its replacement, at the start of a routine. */
7562 ix86_initial_elimination_offset (int from, int to)
7564 struct ix86_frame frame;
7565 ix86_compute_frame_layout (&frame);
7567 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7568 return frame.hard_frame_pointer_offset;
7569 else if (from == FRAME_POINTER_REGNUM
7570 && to == HARD_FRAME_POINTER_REGNUM)
7571 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7574 gcc_assert (to == STACK_POINTER_REGNUM);
7576 if (from == ARG_POINTER_REGNUM)
7577 return frame.stack_pointer_offset;
7579 gcc_assert (from == FRAME_POINTER_REGNUM);
7580 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7584 /* In a dynamically-aligned function, we can't know the offset from
7585 stack pointer to frame pointer, so we must ensure that setjmp
7586 eliminates fp against the hard fp (%ebp) rather than trying to
7587 index from %esp up to the top of the frame across a gap that is
7588 of unknown (at compile-time) size. */
7590 ix86_builtin_setjmp_frame_value (void)
7592 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7595 /* Fill structure ix86_frame about frame of currently computed function. */
7598 ix86_compute_frame_layout (struct ix86_frame *frame)
7600 HOST_WIDE_INT total_size;
7601 unsigned int stack_alignment_needed;
7602 HOST_WIDE_INT offset;
7603 unsigned int preferred_alignment;
7604 HOST_WIDE_INT size = get_frame_size ();
7606 frame->nregs = ix86_nsaved_regs ();
7607 frame->nsseregs = ix86_nsaved_sseregs ();
7610 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7611 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7613 /* MS ABI seem to require stack alignment to be always 16 except for function
7615 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7617 preferred_alignment = 16;
7618 stack_alignment_needed = 16;
7619 crtl->preferred_stack_boundary = 128;
7620 crtl->stack_alignment_needed = 128;
7623 gcc_assert (!size || stack_alignment_needed);
7624 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7625 gcc_assert (preferred_alignment <= stack_alignment_needed);
7627 /* During reload iteration the amount of registers saved can change.
7628 Recompute the value as needed. Do not recompute when amount of registers
7629 didn't change as reload does multiple calls to the function and does not
7630 expect the decision to change within single iteration. */
7631 if (!optimize_function_for_size_p (cfun)
7632 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7634 int count = frame->nregs;
7636 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7637 /* The fast prologue uses move instead of push to save registers. This
7638 is significantly longer, but also executes faster as modern hardware
7639 can execute the moves in parallel, but can't do that for push/pop.
7641 Be careful about choosing what prologue to emit: When function takes
7642 many instructions to execute we may use slow version as well as in
7643 case function is known to be outside hot spot (this is known with
7644 feedback only). Weight the size of function by number of registers
7645 to save as it is cheap to use one or two push instructions but very
7646 slow to use many of them. */
7648 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7649 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7650 || (flag_branch_probabilities
7651 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7652 cfun->machine->use_fast_prologue_epilogue = false;
7654 cfun->machine->use_fast_prologue_epilogue
7655 = !expensive_function_p (count);
7657 if (TARGET_PROLOGUE_USING_MOVE
7658 && cfun->machine->use_fast_prologue_epilogue)
7659 frame->save_regs_using_mov = true;
7661 frame->save_regs_using_mov = false;
7664 /* Skip return address and saved base pointer. */
7665 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7667 frame->hard_frame_pointer_offset = offset;
7669 /* Set offset to aligned because the realigned frame starts from
7671 if (stack_realign_fp)
7672 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7674 /* Register save area */
7675 offset += frame->nregs * UNITS_PER_WORD;
7677 /* Align SSE reg save area. */
7678 if (frame->nsseregs)
7679 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7681 frame->padding0 = 0;
7683 /* SSE register save area. */
7684 offset += frame->padding0 + frame->nsseregs * 16;
7687 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7688 offset += frame->va_arg_size;
7690 /* Align start of frame for local function. */
7691 frame->padding1 = ((offset + stack_alignment_needed - 1)
7692 & -stack_alignment_needed) - offset;
7694 offset += frame->padding1;
7696 /* Frame pointer points here. */
7697 frame->frame_pointer_offset = offset;
7701 /* Add outgoing arguments area. Can be skipped if we eliminated
7702 all the function calls as dead code.
7703 Skipping is however impossible when function calls alloca. Alloca
7704 expander assumes that last crtl->outgoing_args_size
7705 of stack frame are unused. */
7706 if (ACCUMULATE_OUTGOING_ARGS
7707 && (!current_function_is_leaf || cfun->calls_alloca
7708 || ix86_current_function_calls_tls_descriptor))
7710 offset += crtl->outgoing_args_size;
7711 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7714 frame->outgoing_arguments_size = 0;
7716 /* Align stack boundary. Only needed if we're calling another function
7718 if (!current_function_is_leaf || cfun->calls_alloca
7719 || ix86_current_function_calls_tls_descriptor)
7720 frame->padding2 = ((offset + preferred_alignment - 1)
7721 & -preferred_alignment) - offset;
7723 frame->padding2 = 0;
7725 offset += frame->padding2;
7727 /* We've reached end of stack frame. */
7728 frame->stack_pointer_offset = offset;
7730 /* Size prologue needs to allocate. */
7731 frame->to_allocate =
7732 (size + frame->padding1 + frame->padding2
7733 + frame->outgoing_arguments_size + frame->va_arg_size);
7735 if ((!frame->to_allocate && frame->nregs <= 1)
7736 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7737 frame->save_regs_using_mov = false;
7739 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7740 && current_function_is_leaf
7741 && !ix86_current_function_calls_tls_descriptor)
7743 frame->red_zone_size = frame->to_allocate;
7744 if (frame->save_regs_using_mov)
7745 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7746 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7747 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7750 frame->red_zone_size = 0;
7751 frame->to_allocate -= frame->red_zone_size;
7752 frame->stack_pointer_offset -= frame->red_zone_size;
7754 fprintf (stderr, "\n");
7755 fprintf (stderr, "size: %ld\n", (long)size);
7756 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7757 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7758 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7759 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7760 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7761 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7762 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7763 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7764 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7765 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7766 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7767 (long)frame->hard_frame_pointer_offset);
7768 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7769 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7770 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7771 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7775 /* Emit code to save registers in the prologue. */
7778 ix86_emit_save_regs (void)
7783 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7784 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7786 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7787 RTX_FRAME_RELATED_P (insn) = 1;
7791 /* Emit code to save registers using MOV insns. First register
7792 is restored from POINTER + OFFSET. */
7794 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7799 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7800 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7802 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7804 gen_rtx_REG (Pmode, regno));
7805 RTX_FRAME_RELATED_P (insn) = 1;
7806 offset += UNITS_PER_WORD;
7810 /* Emit code to save registers using MOV insns. First register
7811 is restored from POINTER + OFFSET. */
7813 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7819 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7820 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7822 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7823 set_mem_align (mem, 128);
7824 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7825 RTX_FRAME_RELATED_P (insn) = 1;
7830 /* Expand prologue or epilogue stack adjustment.
7831 The pattern exist to put a dependency on all ebp-based memory accesses.
7832 STYLE should be negative if instructions should be marked as frame related,
7833 zero if %r11 register is live and cannot be freely used and positive
7837 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7842 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7843 else if (x86_64_immediate_operand (offset, DImode))
7844 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7848 /* r11 is used by indirect sibcall return as well, set before the
7849 epilogue and used after the epilogue. ATM indirect sibcall
7850 shouldn't be used together with huge frame sizes in one
7851 function because of the frame_size check in sibcall.c. */
7853 r11 = gen_rtx_REG (DImode, R11_REG);
7854 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7856 RTX_FRAME_RELATED_P (insn) = 1;
7857 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7861 RTX_FRAME_RELATED_P (insn) = 1;
7864 /* Find an available register to be used as dynamic realign argument
7865 pointer regsiter. Such a register will be written in prologue and
7866 used in begin of body, so it must not be
7867 1. parameter passing register.
7869 We reuse static-chain register if it is available. Otherwise, we
7870 use DI for i386 and R13 for x86-64. We chose R13 since it has
7873 Return: the regno of chosen register. */
7876 find_drap_reg (void)
7878 tree decl = cfun->decl;
7882 /* Use R13 for nested function or function need static chain.
7883 Since function with tail call may use any caller-saved
7884 registers in epilogue, DRAP must not use caller-saved
7885 register in such case. */
7886 if ((decl_function_context (decl)
7887 && !DECL_NO_STATIC_CHAIN (decl))
7888 || crtl->tail_call_emit)
7895 /* Use DI for nested function or function need static chain.
7896 Since function with tail call may use any caller-saved
7897 registers in epilogue, DRAP must not use caller-saved
7898 register in such case. */
7899 if ((decl_function_context (decl)
7900 && !DECL_NO_STATIC_CHAIN (decl))
7901 || crtl->tail_call_emit)
7904 /* Reuse static chain register if it isn't used for parameter
7906 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7907 && !lookup_attribute ("fastcall",
7908 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7915 /* Update incoming stack boundary and estimated stack alignment. */
7918 ix86_update_stack_boundary (void)
7920 /* Prefer the one specified at command line. */
7921 ix86_incoming_stack_boundary
7922 = (ix86_user_incoming_stack_boundary
7923 ? ix86_user_incoming_stack_boundary
7924 : ix86_default_incoming_stack_boundary);
7926 /* Incoming stack alignment can be changed on individual functions
7927 via force_align_arg_pointer attribute. We use the smallest
7928 incoming stack boundary. */
7929 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7930 && lookup_attribute (ix86_force_align_arg_pointer_string,
7931 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7932 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7934 /* The incoming stack frame has to be aligned at least at
7935 parm_stack_boundary. */
7936 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
7937 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
7939 /* Stack at entrance of main is aligned by runtime. We use the
7940 smallest incoming stack boundary. */
7941 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7942 && DECL_NAME (current_function_decl)
7943 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7944 && DECL_FILE_SCOPE_P (current_function_decl))
7945 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7947 /* x86_64 vararg needs 16byte stack alignment for register save
7951 && crtl->stack_alignment_estimated < 128)
7952 crtl->stack_alignment_estimated = 128;
7955 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7956 needed or an rtx for DRAP otherwise. */
7959 ix86_get_drap_rtx (void)
7961 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7962 crtl->need_drap = true;
7964 if (stack_realign_drap)
7966 /* Assign DRAP to vDRAP and returns vDRAP */
7967 unsigned int regno = find_drap_reg ();
7972 arg_ptr = gen_rtx_REG (Pmode, regno);
7973 crtl->drap_reg = arg_ptr;
7976 drap_vreg = copy_to_reg (arg_ptr);
7980 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
7981 RTX_FRAME_RELATED_P (insn) = 1;
7988 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7991 ix86_internal_arg_pointer (void)
7993 return virtual_incoming_args_rtx;
7996 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7997 This is called from dwarf2out.c to emit call frame instructions
7998 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8000 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8002 rtx unspec = SET_SRC (pattern);
8003 gcc_assert (GET_CODE (unspec) == UNSPEC);
8007 case UNSPEC_REG_SAVE:
8008 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8009 SET_DEST (pattern));
8011 case UNSPEC_DEF_CFA:
8012 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8013 INTVAL (XVECEXP (unspec, 0, 0)));
8020 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8021 to be generated in correct form. */
8023 ix86_finalize_stack_realign_flags (void)
8025 /* Check if stack realign is really needed after reload, and
8026 stores result in cfun */
8027 unsigned int incoming_stack_boundary
8028 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8029 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8030 unsigned int stack_realign = (incoming_stack_boundary
8031 < (current_function_is_leaf
8032 ? crtl->max_used_stack_slot_alignment
8033 : crtl->stack_alignment_needed));
8035 if (crtl->stack_realign_finalized)
8037 /* After stack_realign_needed is finalized, we can't no longer
8039 gcc_assert (crtl->stack_realign_needed == stack_realign);
8043 crtl->stack_realign_needed = stack_realign;
8044 crtl->stack_realign_finalized = true;
8048 /* Expand the prologue into a bunch of separate insns. */
8051 ix86_expand_prologue (void)
8055 struct ix86_frame frame;
8056 HOST_WIDE_INT allocate;
8058 ix86_finalize_stack_realign_flags ();
8060 /* DRAP should not coexist with stack_realign_fp */
8061 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8063 ix86_compute_frame_layout (&frame);
8065 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8066 of DRAP is needed and stack realignment is really needed after reload */
8067 if (crtl->drap_reg && crtl->stack_realign_needed)
8070 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8071 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8072 ? 0 : UNITS_PER_WORD);
8074 gcc_assert (stack_realign_drap);
8076 /* Grab the argument pointer. */
8077 x = plus_constant (stack_pointer_rtx,
8078 (UNITS_PER_WORD + param_ptr_offset));
8081 /* Only need to push parameter pointer reg if it is caller
8083 if (!call_used_regs[REGNO (crtl->drap_reg)])
8085 /* Push arg pointer reg */
8086 insn = emit_insn (gen_push (y));
8087 RTX_FRAME_RELATED_P (insn) = 1;
8090 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8091 RTX_FRAME_RELATED_P (insn) = 1;
8093 /* Align the stack. */
8094 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8096 GEN_INT (-align_bytes)));
8097 RTX_FRAME_RELATED_P (insn) = 1;
8099 /* Replicate the return address on the stack so that return
8100 address can be reached via (argp - 1) slot. This is needed
8101 to implement macro RETURN_ADDR_RTX and intrinsic function
8102 expand_builtin_return_addr etc. */
8104 x = gen_frame_mem (Pmode,
8105 plus_constant (x, -UNITS_PER_WORD));
8106 insn = emit_insn (gen_push (x));
8107 RTX_FRAME_RELATED_P (insn) = 1;
8110 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8111 slower on all targets. Also sdb doesn't like it. */
8113 if (frame_pointer_needed)
8115 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8116 RTX_FRAME_RELATED_P (insn) = 1;
8118 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8119 RTX_FRAME_RELATED_P (insn) = 1;
8122 if (stack_realign_fp)
8124 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8125 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8127 /* Align the stack. */
8128 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8130 GEN_INT (-align_bytes)));
8131 RTX_FRAME_RELATED_P (insn) = 1;
8134 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8136 if (!frame.save_regs_using_mov)
8137 ix86_emit_save_regs ();
8139 allocate += frame.nregs * UNITS_PER_WORD;
8141 /* When using red zone we may start register saving before allocating
8142 the stack frame saving one cycle of the prologue. However I will
8143 avoid doing this if I am going to have to probe the stack since
8144 at least on x86_64 the stack probe can turn into a call that clobbers
8145 a red zone location */
8146 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8147 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8148 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8149 && !crtl->stack_realign_needed)
8150 ? hard_frame_pointer_rtx
8151 : stack_pointer_rtx,
8152 -frame.nregs * UNITS_PER_WORD);
8156 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8157 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8158 GEN_INT (-allocate), -1);
8161 /* Only valid for Win32. */
8162 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8166 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8168 if (cfun->machine->call_abi == MS_ABI)
8171 eax_live = ix86_eax_live_at_start_p ();
8175 emit_insn (gen_push (eax));
8176 allocate -= UNITS_PER_WORD;
8179 emit_move_insn (eax, GEN_INT (allocate));
8182 insn = gen_allocate_stack_worker_64 (eax, eax);
8184 insn = gen_allocate_stack_worker_32 (eax, eax);
8185 insn = emit_insn (insn);
8186 RTX_FRAME_RELATED_P (insn) = 1;
8187 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8188 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8189 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8190 t, REG_NOTES (insn));
8194 if (frame_pointer_needed)
8195 t = plus_constant (hard_frame_pointer_rtx,
8198 - frame.nregs * UNITS_PER_WORD);
8200 t = plus_constant (stack_pointer_rtx, allocate);
8201 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8205 if (frame.save_regs_using_mov
8206 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8207 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8209 if (!frame_pointer_needed
8210 || !frame.to_allocate
8211 || crtl->stack_realign_needed)
8212 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8214 + frame.nsseregs * 16 + frame.padding0);
8216 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8217 -frame.nregs * UNITS_PER_WORD);
8219 if (!frame_pointer_needed
8220 || !frame.to_allocate
8221 || crtl->stack_realign_needed)
8222 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8225 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8226 - frame.nregs * UNITS_PER_WORD
8227 - frame.nsseregs * 16
8230 pic_reg_used = false;
8231 if (pic_offset_table_rtx
8232 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8235 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8237 if (alt_pic_reg_used != INVALID_REGNUM)
8238 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8240 pic_reg_used = true;
8247 if (ix86_cmodel == CM_LARGE_PIC)
8249 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8250 rtx label = gen_label_rtx ();
8252 LABEL_PRESERVE_P (label) = 1;
8253 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8254 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8255 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8256 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8257 pic_offset_table_rtx, tmp_reg));
8260 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8263 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8266 /* In the pic_reg_used case, make sure that the got load isn't deleted
8267 when mcount needs it. Blockage to avoid call movement across mcount
8268 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8270 if (crtl->profile && pic_reg_used)
8271 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8273 if (crtl->drap_reg && !crtl->stack_realign_needed)
8275 /* vDRAP is setup but after reload it turns out stack realign
8276 isn't necessary, here we will emit prologue to setup DRAP
8277 without stack realign adjustment */
8278 int drap_bp_offset = UNITS_PER_WORD * 2;
8279 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8280 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8283 /* Prevent instructions from being scheduled into register save push
8284 sequence when access to the redzone area is done through frame pointer.
8285 The offset betweeh the frame pointer and the stack pointer is calculated
8286 relative to the value of the stack pointer at the end of the function
8287 prologue, and moving instructions that access redzone area via frame
8288 pointer inside push sequence violates this assumption. */
8289 if (frame_pointer_needed && frame.red_zone_size)
8290 emit_insn (gen_memory_blockage ());
8292 /* Emit cld instruction if stringops are used in the function. */
8293 if (TARGET_CLD && ix86_current_function_needs_cld)
8294 emit_insn (gen_cld ());
8297 /* Emit code to restore saved registers using MOV insns. First register
8298 is restored from POINTER + OFFSET. */
8300 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8301 int maybe_eh_return)
8304 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8306 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8307 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8309 /* Ensure that adjust_address won't be forced to produce pointer
8310 out of range allowed by x86-64 instruction set. */
8311 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8315 r11 = gen_rtx_REG (DImode, R11_REG);
8316 emit_move_insn (r11, GEN_INT (offset));
8317 emit_insn (gen_adddi3 (r11, r11, pointer));
8318 base_address = gen_rtx_MEM (Pmode, r11);
8321 emit_move_insn (gen_rtx_REG (Pmode, regno),
8322 adjust_address (base_address, Pmode, offset));
8323 offset += UNITS_PER_WORD;
8327 /* Emit code to restore saved registers using MOV insns. First register
8328 is restored from POINTER + OFFSET. */
8330 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8331 int maybe_eh_return)
8334 rtx base_address = gen_rtx_MEM (TImode, pointer);
8337 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8338 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8340 /* Ensure that adjust_address won't be forced to produce pointer
8341 out of range allowed by x86-64 instruction set. */
8342 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8346 r11 = gen_rtx_REG (DImode, R11_REG);
8347 emit_move_insn (r11, GEN_INT (offset));
8348 emit_insn (gen_adddi3 (r11, r11, pointer));
8349 base_address = gen_rtx_MEM (TImode, r11);
8352 mem = adjust_address (base_address, TImode, offset);
8353 set_mem_align (mem, 128);
8354 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8359 /* Restore function stack, frame, and registers. */
8362 ix86_expand_epilogue (int style)
8366 struct ix86_frame frame;
8367 HOST_WIDE_INT offset;
8369 ix86_finalize_stack_realign_flags ();
8371 /* When stack is realigned, SP must be valid. */
8372 sp_valid = (!frame_pointer_needed
8373 || current_function_sp_is_unchanging
8374 || stack_realign_fp);
8376 ix86_compute_frame_layout (&frame);
8378 /* See the comment about red zone and frame
8379 pointer usage in ix86_expand_prologue. */
8380 if (frame_pointer_needed && frame.red_zone_size)
8381 emit_insn (gen_memory_blockage ());
8383 /* Calculate start of saved registers relative to ebp. Special care
8384 must be taken for the normal return case of a function using
8385 eh_return: the eax and edx registers are marked as saved, but not
8386 restored along this path. */
8387 offset = frame.nregs;
8388 if (crtl->calls_eh_return && style != 2)
8390 offset *= -UNITS_PER_WORD;
8391 offset -= frame.nsseregs * 16 + frame.padding0;
8393 /* If we're only restoring one register and sp is not valid then
8394 using a move instruction to restore the register since it's
8395 less work than reloading sp and popping the register.
8397 The default code result in stack adjustment using add/lea instruction,
8398 while this code results in LEAVE instruction (or discrete equivalent),
8399 so it is profitable in some other cases as well. Especially when there
8400 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8401 and there is exactly one register to pop. This heuristic may need some
8402 tuning in future. */
8403 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8404 || (TARGET_EPILOGUE_USING_MOVE
8405 && cfun->machine->use_fast_prologue_epilogue
8406 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8407 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs) && frame.to_allocate)
8408 || (frame_pointer_needed && TARGET_USE_LEAVE
8409 && cfun->machine->use_fast_prologue_epilogue
8410 && (frame.nregs + frame.nsseregs) == 1)
8411 || crtl->calls_eh_return)
8413 /* Restore registers. We can use ebp or esp to address the memory
8414 locations. If both are available, default to ebp, since offsets
8415 are known to be small. Only exception is esp pointing directly
8416 to the end of block of saved registers, where we may simplify
8419 If we are realigning stack with bp and sp, regs restore can't
8420 be addressed by bp. sp must be used instead. */
8422 if (!frame_pointer_needed
8423 || (sp_valid && !frame.to_allocate)
8424 || stack_realign_fp)
8426 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8427 frame.to_allocate, style == 2);
8428 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8430 + frame.nsseregs * 16
8431 + frame.padding0, style == 2);
8435 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8436 offset, style == 2);
8437 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8439 + frame.nsseregs * 16
8440 + frame.padding0, style == 2);
8443 /* eh_return epilogues need %ecx added to the stack pointer. */
8446 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8448 /* Stack align doesn't work with eh_return. */
8449 gcc_assert (!crtl->stack_realign_needed);
8451 if (frame_pointer_needed)
8453 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8454 tmp = plus_constant (tmp, UNITS_PER_WORD);
8455 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8457 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8458 emit_move_insn (hard_frame_pointer_rtx, tmp);
8460 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8465 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8466 tmp = plus_constant (tmp, (frame.to_allocate
8467 + frame.nregs * UNITS_PER_WORD
8468 + frame.nsseregs * 16
8470 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8473 else if (!frame_pointer_needed)
8474 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8475 GEN_INT (frame.to_allocate
8476 + frame.nregs * UNITS_PER_WORD
8477 + frame.nsseregs * 16
8480 /* If not an i386, mov & pop is faster than "leave". */
8481 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8482 || !cfun->machine->use_fast_prologue_epilogue)
8483 emit_insn ((*ix86_gen_leave) ());
8486 pro_epilogue_adjust_stack (stack_pointer_rtx,
8487 hard_frame_pointer_rtx,
8490 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8495 /* First step is to deallocate the stack frame so that we can
8498 If we realign stack with frame pointer, then stack pointer
8499 won't be able to recover via lea $offset(%bp), %sp, because
8500 there is a padding area between bp and sp for realign.
8501 "add $to_allocate, %sp" must be used instead. */
8504 gcc_assert (frame_pointer_needed);
8505 gcc_assert (!stack_realign_fp);
8506 pro_epilogue_adjust_stack (stack_pointer_rtx,
8507 hard_frame_pointer_rtx,
8508 GEN_INT (offset), style);
8509 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8510 frame.to_allocate, style == 2);
8511 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8512 GEN_INT (frame.nsseregs * 16), style);
8514 else if (frame.to_allocate || frame.nsseregs)
8516 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8519 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8520 GEN_INT (frame.to_allocate
8521 + frame.nsseregs * 16
8522 + frame.padding0), style);
8525 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8526 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8527 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8528 if (frame_pointer_needed)
8530 /* Leave results in shorter dependency chains on CPUs that are
8531 able to grok it fast. */
8532 if (TARGET_USE_LEAVE)
8533 emit_insn ((*ix86_gen_leave) ());
8536 /* For stack realigned really happens, recover stack
8537 pointer to hard frame pointer is a must, if not using
8539 if (stack_realign_fp)
8540 pro_epilogue_adjust_stack (stack_pointer_rtx,
8541 hard_frame_pointer_rtx,
8543 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8548 if (crtl->drap_reg && crtl->stack_realign_needed)
8550 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8551 ? 0 : UNITS_PER_WORD);
8552 gcc_assert (stack_realign_drap);
8553 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8555 GEN_INT (-(UNITS_PER_WORD
8556 + param_ptr_offset))));
8557 if (!call_used_regs[REGNO (crtl->drap_reg)])
8558 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8562 /* Sibcall epilogues don't want a return instruction. */
8566 if (crtl->args.pops_args && crtl->args.size)
8568 rtx popc = GEN_INT (crtl->args.pops_args);
8570 /* i386 can only pop 64K bytes. If asked to pop more, pop
8571 return address, do explicit add, and jump indirectly to the
8574 if (crtl->args.pops_args >= 65536)
8576 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8578 /* There is no "pascal" calling convention in any 64bit ABI. */
8579 gcc_assert (!TARGET_64BIT);
8581 emit_insn (gen_popsi1 (ecx));
8582 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8583 emit_jump_insn (gen_return_indirect_internal (ecx));
8586 emit_jump_insn (gen_return_pop_internal (popc));
8589 emit_jump_insn (gen_return_internal ());
8592 /* Reset from the function's potential modifications. */
8595 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8596 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8598 if (pic_offset_table_rtx)
8599 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8601 /* Mach-O doesn't support labels at the end of objects, so if
8602 it looks like we might want one, insert a NOP. */
8604 rtx insn = get_last_insn ();
8607 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8608 insn = PREV_INSN (insn);
8612 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8613 fputs ("\tnop\n", file);
8619 /* Extract the parts of an RTL expression that is a valid memory address
8620 for an instruction. Return 0 if the structure of the address is
8621 grossly off. Return -1 if the address contains ASHIFT, so it is not
8622 strictly valid, but still used for computing length of lea instruction. */
8625 ix86_decompose_address (rtx addr, struct ix86_address *out)
8627 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8628 rtx base_reg, index_reg;
8629 HOST_WIDE_INT scale = 1;
8630 rtx scale_rtx = NULL_RTX;
8632 enum ix86_address_seg seg = SEG_DEFAULT;
8634 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8636 else if (GET_CODE (addr) == PLUS)
8646 addends[n++] = XEXP (op, 1);
8649 while (GET_CODE (op) == PLUS);
8654 for (i = n; i >= 0; --i)
8657 switch (GET_CODE (op))
8662 index = XEXP (op, 0);
8663 scale_rtx = XEXP (op, 1);
8667 if (XINT (op, 1) == UNSPEC_TP
8668 && TARGET_TLS_DIRECT_SEG_REFS
8669 && seg == SEG_DEFAULT)
8670 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8699 else if (GET_CODE (addr) == MULT)
8701 index = XEXP (addr, 0); /* index*scale */
8702 scale_rtx = XEXP (addr, 1);
8704 else if (GET_CODE (addr) == ASHIFT)
8708 /* We're called for lea too, which implements ashift on occasion. */
8709 index = XEXP (addr, 0);
8710 tmp = XEXP (addr, 1);
8711 if (!CONST_INT_P (tmp))
8713 scale = INTVAL (tmp);
8714 if ((unsigned HOST_WIDE_INT) scale > 3)
8720 disp = addr; /* displacement */
8722 /* Extract the integral value of scale. */
8725 if (!CONST_INT_P (scale_rtx))
8727 scale = INTVAL (scale_rtx);
8730 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8731 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8733 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8734 if (base_reg && index_reg && scale == 1
8735 && (index_reg == arg_pointer_rtx
8736 || index_reg == frame_pointer_rtx
8737 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8740 tmp = base, base = index, index = tmp;
8741 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8744 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8745 if ((base_reg == hard_frame_pointer_rtx
8746 || base_reg == frame_pointer_rtx
8747 || base_reg == arg_pointer_rtx) && !disp)
8750 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8751 Avoid this by transforming to [%esi+0].
8752 Reload calls address legitimization without cfun defined, so we need
8753 to test cfun for being non-NULL. */
8754 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8755 && base_reg && !index_reg && !disp
8757 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8760 /* Special case: encode reg+reg instead of reg*2. */
8761 if (!base && index && scale && scale == 2)
8762 base = index, base_reg = index_reg, scale = 1;
8764 /* Special case: scaling cannot be encoded without base or displacement. */
8765 if (!base && !disp && index && scale != 1)
8777 /* Return cost of the memory address x.
8778 For i386, it is better to use a complex address than let gcc copy
8779 the address into a reg and make a new pseudo. But not if the address
8780 requires to two regs - that would mean more pseudos with longer
8783 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8785 struct ix86_address parts;
8787 int ok = ix86_decompose_address (x, &parts);
8791 if (parts.base && GET_CODE (parts.base) == SUBREG)
8792 parts.base = SUBREG_REG (parts.base);
8793 if (parts.index && GET_CODE (parts.index) == SUBREG)
8794 parts.index = SUBREG_REG (parts.index);
8796 /* Attempt to minimize number of registers in the address. */
8798 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8800 && (!REG_P (parts.index)
8801 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8805 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8807 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8808 && parts.base != parts.index)
8811 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8812 since it's predecode logic can't detect the length of instructions
8813 and it degenerates to vector decoded. Increase cost of such
8814 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8815 to split such addresses or even refuse such addresses at all.
8817 Following addressing modes are affected:
8822 The first and last case may be avoidable by explicitly coding the zero in
8823 memory address, but I don't have AMD-K6 machine handy to check this
8827 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8828 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8829 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8835 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8836 this is used for to form addresses to local data when -fPIC is in
8840 darwin_local_data_pic (rtx disp)
8842 return (GET_CODE (disp) == UNSPEC
8843 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8846 /* Determine if a given RTX is a valid constant. We already know this
8847 satisfies CONSTANT_P. */
8850 legitimate_constant_p (rtx x)
8852 switch (GET_CODE (x))
8857 if (GET_CODE (x) == PLUS)
8859 if (!CONST_INT_P (XEXP (x, 1)))
8864 if (TARGET_MACHO && darwin_local_data_pic (x))
8867 /* Only some unspecs are valid as "constants". */
8868 if (GET_CODE (x) == UNSPEC)
8869 switch (XINT (x, 1))
8874 return TARGET_64BIT;
8877 x = XVECEXP (x, 0, 0);
8878 return (GET_CODE (x) == SYMBOL_REF
8879 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8881 x = XVECEXP (x, 0, 0);
8882 return (GET_CODE (x) == SYMBOL_REF
8883 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8888 /* We must have drilled down to a symbol. */
8889 if (GET_CODE (x) == LABEL_REF)
8891 if (GET_CODE (x) != SYMBOL_REF)
8896 /* TLS symbols are never valid. */
8897 if (SYMBOL_REF_TLS_MODEL (x))
8900 /* DLLIMPORT symbols are never valid. */
8901 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8902 && SYMBOL_REF_DLLIMPORT_P (x))
8907 if (GET_MODE (x) == TImode
8908 && x != CONST0_RTX (TImode)
8914 if (x == CONST0_RTX (GET_MODE (x)))
8922 /* Otherwise we handle everything else in the move patterns. */
8926 /* Determine if it's legal to put X into the constant pool. This
8927 is not possible for the address of thread-local symbols, which
8928 is checked above. */
8931 ix86_cannot_force_const_mem (rtx x)
8933 /* We can always put integral constants and vectors in memory. */
8934 switch (GET_CODE (x))
8944 return !legitimate_constant_p (x);
8947 /* Determine if a given RTX is a valid constant address. */
8950 constant_address_p (rtx x)
8952 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8955 /* Nonzero if the constant value X is a legitimate general operand
8956 when generating PIC code. It is given that flag_pic is on and
8957 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8960 legitimate_pic_operand_p (rtx x)
8964 switch (GET_CODE (x))
8967 inner = XEXP (x, 0);
8968 if (GET_CODE (inner) == PLUS
8969 && CONST_INT_P (XEXP (inner, 1)))
8970 inner = XEXP (inner, 0);
8972 /* Only some unspecs are valid as "constants". */
8973 if (GET_CODE (inner) == UNSPEC)
8974 switch (XINT (inner, 1))
8979 return TARGET_64BIT;
8981 x = XVECEXP (inner, 0, 0);
8982 return (GET_CODE (x) == SYMBOL_REF
8983 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8984 case UNSPEC_MACHOPIC_OFFSET:
8985 return legitimate_pic_address_disp_p (x);
8993 return legitimate_pic_address_disp_p (x);
9000 /* Determine if a given CONST RTX is a valid memory displacement
9004 legitimate_pic_address_disp_p (rtx disp)
9008 /* In 64bit mode we can allow direct addresses of symbols and labels
9009 when they are not dynamic symbols. */
9012 rtx op0 = disp, op1;
9014 switch (GET_CODE (disp))
9020 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9022 op0 = XEXP (XEXP (disp, 0), 0);
9023 op1 = XEXP (XEXP (disp, 0), 1);
9024 if (!CONST_INT_P (op1)
9025 || INTVAL (op1) >= 16*1024*1024
9026 || INTVAL (op1) < -16*1024*1024)
9028 if (GET_CODE (op0) == LABEL_REF)
9030 if (GET_CODE (op0) != SYMBOL_REF)
9035 /* TLS references should always be enclosed in UNSPEC. */
9036 if (SYMBOL_REF_TLS_MODEL (op0))
9038 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9039 && ix86_cmodel != CM_LARGE_PIC)
9047 if (GET_CODE (disp) != CONST)
9049 disp = XEXP (disp, 0);
9053 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9054 of GOT tables. We should not need these anyway. */
9055 if (GET_CODE (disp) != UNSPEC
9056 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9057 && XINT (disp, 1) != UNSPEC_GOTOFF
9058 && XINT (disp, 1) != UNSPEC_PLTOFF))
9061 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9062 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9068 if (GET_CODE (disp) == PLUS)
9070 if (!CONST_INT_P (XEXP (disp, 1)))
9072 disp = XEXP (disp, 0);
9076 if (TARGET_MACHO && darwin_local_data_pic (disp))
9079 if (GET_CODE (disp) != UNSPEC)
9082 switch (XINT (disp, 1))
9087 /* We need to check for both symbols and labels because VxWorks loads
9088 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9090 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9091 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9093 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9094 While ABI specify also 32bit relocation but we don't produce it in
9095 small PIC model at all. */
9096 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9097 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9099 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9101 case UNSPEC_GOTTPOFF:
9102 case UNSPEC_GOTNTPOFF:
9103 case UNSPEC_INDNTPOFF:
9106 disp = XVECEXP (disp, 0, 0);
9107 return (GET_CODE (disp) == SYMBOL_REF
9108 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9110 disp = XVECEXP (disp, 0, 0);
9111 return (GET_CODE (disp) == SYMBOL_REF
9112 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9114 disp = XVECEXP (disp, 0, 0);
9115 return (GET_CODE (disp) == SYMBOL_REF
9116 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9122 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9123 memory address for an instruction. The MODE argument is the machine mode
9124 for the MEM expression that wants to use this address.
9126 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9127 convert common non-canonical forms to canonical form so that they will
9131 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9132 rtx addr, int strict)
9134 struct ix86_address parts;
9135 rtx base, index, disp;
9136 HOST_WIDE_INT scale;
9137 const char *reason = NULL;
9138 rtx reason_rtx = NULL_RTX;
9140 if (ix86_decompose_address (addr, &parts) <= 0)
9142 reason = "decomposition failed";
9147 index = parts.index;
9149 scale = parts.scale;
9151 /* Validate base register.
9153 Don't allow SUBREG's that span more than a word here. It can lead to spill
9154 failures when the base is one word out of a two word structure, which is
9155 represented internally as a DImode int. */
9164 else if (GET_CODE (base) == SUBREG
9165 && REG_P (SUBREG_REG (base))
9166 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9168 reg = SUBREG_REG (base);
9171 reason = "base is not a register";
9175 if (GET_MODE (base) != Pmode)
9177 reason = "base is not in Pmode";
9181 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9182 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9184 reason = "base is not valid";
9189 /* Validate index register.
9191 Don't allow SUBREG's that span more than a word here -- same as above. */
9200 else if (GET_CODE (index) == SUBREG
9201 && REG_P (SUBREG_REG (index))
9202 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9204 reg = SUBREG_REG (index);
9207 reason = "index is not a register";
9211 if (GET_MODE (index) != Pmode)
9213 reason = "index is not in Pmode";
9217 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9218 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9220 reason = "index is not valid";
9225 /* Validate scale factor. */
9228 reason_rtx = GEN_INT (scale);
9231 reason = "scale without index";
9235 if (scale != 2 && scale != 4 && scale != 8)
9237 reason = "scale is not a valid multiplier";
9242 /* Validate displacement. */
9247 if (GET_CODE (disp) == CONST
9248 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9249 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9250 switch (XINT (XEXP (disp, 0), 1))
9252 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9253 used. While ABI specify also 32bit relocations, we don't produce
9254 them at all and use IP relative instead. */
9257 gcc_assert (flag_pic);
9259 goto is_legitimate_pic;
9260 reason = "64bit address unspec";
9263 case UNSPEC_GOTPCREL:
9264 gcc_assert (flag_pic);
9265 goto is_legitimate_pic;
9267 case UNSPEC_GOTTPOFF:
9268 case UNSPEC_GOTNTPOFF:
9269 case UNSPEC_INDNTPOFF:
9275 reason = "invalid address unspec";
9279 else if (SYMBOLIC_CONST (disp)
9283 && MACHOPIC_INDIRECT
9284 && !machopic_operand_p (disp)
9290 if (TARGET_64BIT && (index || base))
9292 /* foo@dtpoff(%rX) is ok. */
9293 if (GET_CODE (disp) != CONST
9294 || GET_CODE (XEXP (disp, 0)) != PLUS
9295 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9296 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9297 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9298 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9300 reason = "non-constant pic memory reference";
9304 else if (! legitimate_pic_address_disp_p (disp))
9306 reason = "displacement is an invalid pic construct";
9310 /* This code used to verify that a symbolic pic displacement
9311 includes the pic_offset_table_rtx register.
9313 While this is good idea, unfortunately these constructs may
9314 be created by "adds using lea" optimization for incorrect
9323 This code is nonsensical, but results in addressing
9324 GOT table with pic_offset_table_rtx base. We can't
9325 just refuse it easily, since it gets matched by
9326 "addsi3" pattern, that later gets split to lea in the
9327 case output register differs from input. While this
9328 can be handled by separate addsi pattern for this case
9329 that never results in lea, this seems to be easier and
9330 correct fix for crash to disable this test. */
9332 else if (GET_CODE (disp) != LABEL_REF
9333 && !CONST_INT_P (disp)
9334 && (GET_CODE (disp) != CONST
9335 || !legitimate_constant_p (disp))
9336 && (GET_CODE (disp) != SYMBOL_REF
9337 || !legitimate_constant_p (disp)))
9339 reason = "displacement is not constant";
9342 else if (TARGET_64BIT
9343 && !x86_64_immediate_operand (disp, VOIDmode))
9345 reason = "displacement is out of range";
9350 /* Everything looks valid. */
9357 /* Return a unique alias set for the GOT. */
9359 static alias_set_type
9360 ix86_GOT_alias_set (void)
9362 static alias_set_type set = -1;
9364 set = new_alias_set ();
9368 /* Return a legitimate reference for ORIG (an address) using the
9369 register REG. If REG is 0, a new pseudo is generated.
9371 There are two types of references that must be handled:
9373 1. Global data references must load the address from the GOT, via
9374 the PIC reg. An insn is emitted to do this load, and the reg is
9377 2. Static data references, constant pool addresses, and code labels
9378 compute the address as an offset from the GOT, whose base is in
9379 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9380 differentiate them from global data objects. The returned
9381 address is the PIC reg + an unspec constant.
9383 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9384 reg also appears in the address. */
9387 legitimize_pic_address (rtx orig, rtx reg)
9394 if (TARGET_MACHO && !TARGET_64BIT)
9397 reg = gen_reg_rtx (Pmode);
9398 /* Use the generic Mach-O PIC machinery. */
9399 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9403 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9405 else if (TARGET_64BIT
9406 && ix86_cmodel != CM_SMALL_PIC
9407 && gotoff_operand (addr, Pmode))
9410 /* This symbol may be referenced via a displacement from the PIC
9411 base address (@GOTOFF). */
9413 if (reload_in_progress)
9414 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9415 if (GET_CODE (addr) == CONST)
9416 addr = XEXP (addr, 0);
9417 if (GET_CODE (addr) == PLUS)
9419 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9421 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9424 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9425 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9427 tmpreg = gen_reg_rtx (Pmode);
9430 emit_move_insn (tmpreg, new_rtx);
9434 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9435 tmpreg, 1, OPTAB_DIRECT);
9438 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9440 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9442 /* This symbol may be referenced via a displacement from the PIC
9443 base address (@GOTOFF). */
9445 if (reload_in_progress)
9446 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9447 if (GET_CODE (addr) == CONST)
9448 addr = XEXP (addr, 0);
9449 if (GET_CODE (addr) == PLUS)
9451 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9453 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9456 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9457 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9458 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9462 emit_move_insn (reg, new_rtx);
9466 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9467 /* We can't use @GOTOFF for text labels on VxWorks;
9468 see gotoff_operand. */
9469 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9471 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9473 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9474 return legitimize_dllimport_symbol (addr, true);
9475 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9476 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9477 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9479 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9480 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9484 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9486 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9487 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9488 new_rtx = gen_const_mem (Pmode, new_rtx);
9489 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9492 reg = gen_reg_rtx (Pmode);
9493 /* Use directly gen_movsi, otherwise the address is loaded
9494 into register for CSE. We don't want to CSE this addresses,
9495 instead we CSE addresses from the GOT table, so skip this. */
9496 emit_insn (gen_movsi (reg, new_rtx));
9501 /* This symbol must be referenced via a load from the
9502 Global Offset Table (@GOT). */
9504 if (reload_in_progress)
9505 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9506 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9507 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9509 new_rtx = force_reg (Pmode, new_rtx);
9510 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9511 new_rtx = gen_const_mem (Pmode, new_rtx);
9512 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9515 reg = gen_reg_rtx (Pmode);
9516 emit_move_insn (reg, new_rtx);
9522 if (CONST_INT_P (addr)
9523 && !x86_64_immediate_operand (addr, VOIDmode))
9527 emit_move_insn (reg, addr);
9531 new_rtx = force_reg (Pmode, addr);
9533 else if (GET_CODE (addr) == CONST)
9535 addr = XEXP (addr, 0);
9537 /* We must match stuff we generate before. Assume the only
9538 unspecs that can get here are ours. Not that we could do
9539 anything with them anyway.... */
9540 if (GET_CODE (addr) == UNSPEC
9541 || (GET_CODE (addr) == PLUS
9542 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9544 gcc_assert (GET_CODE (addr) == PLUS);
9546 if (GET_CODE (addr) == PLUS)
9548 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9550 /* Check first to see if this is a constant offset from a @GOTOFF
9551 symbol reference. */
9552 if (gotoff_operand (op0, Pmode)
9553 && CONST_INT_P (op1))
9557 if (reload_in_progress)
9558 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9559 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9561 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9562 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9563 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9567 emit_move_insn (reg, new_rtx);
9573 if (INTVAL (op1) < -16*1024*1024
9574 || INTVAL (op1) >= 16*1024*1024)
9576 if (!x86_64_immediate_operand (op1, Pmode))
9577 op1 = force_reg (Pmode, op1);
9578 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9584 base = legitimize_pic_address (XEXP (addr, 0), reg);
9585 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9586 base == reg ? NULL_RTX : reg);
9588 if (CONST_INT_P (new_rtx))
9589 new_rtx = plus_constant (base, INTVAL (new_rtx));
9592 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9594 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9595 new_rtx = XEXP (new_rtx, 1);
9597 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9605 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9608 get_thread_pointer (int to_reg)
9612 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9616 reg = gen_reg_rtx (Pmode);
9617 insn = gen_rtx_SET (VOIDmode, reg, tp);
9618 insn = emit_insn (insn);
9623 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9624 false if we expect this to be used for a memory address and true if
9625 we expect to load the address into a register. */
9628 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9630 rtx dest, base, off, pic, tp;
9635 case TLS_MODEL_GLOBAL_DYNAMIC:
9636 dest = gen_reg_rtx (Pmode);
9637 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9639 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9641 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9644 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9645 insns = get_insns ();
9648 RTL_CONST_CALL_P (insns) = 1;
9649 emit_libcall_block (insns, dest, rax, x);
9651 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9652 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9654 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9656 if (TARGET_GNU2_TLS)
9658 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9660 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9664 case TLS_MODEL_LOCAL_DYNAMIC:
9665 base = gen_reg_rtx (Pmode);
9666 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9668 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9670 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9673 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9674 insns = get_insns ();
9677 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9678 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9679 RTL_CONST_CALL_P (insns) = 1;
9680 emit_libcall_block (insns, base, rax, note);
9682 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9683 emit_insn (gen_tls_local_dynamic_base_64 (base));
9685 emit_insn (gen_tls_local_dynamic_base_32 (base));
9687 if (TARGET_GNU2_TLS)
9689 rtx x = ix86_tls_module_base ();
9691 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9692 gen_rtx_MINUS (Pmode, x, tp));
9695 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9696 off = gen_rtx_CONST (Pmode, off);
9698 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9700 if (TARGET_GNU2_TLS)
9702 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9704 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9709 case TLS_MODEL_INITIAL_EXEC:
9713 type = UNSPEC_GOTNTPOFF;
9717 if (reload_in_progress)
9718 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9719 pic = pic_offset_table_rtx;
9720 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9722 else if (!TARGET_ANY_GNU_TLS)
9724 pic = gen_reg_rtx (Pmode);
9725 emit_insn (gen_set_got (pic));
9726 type = UNSPEC_GOTTPOFF;
9731 type = UNSPEC_INDNTPOFF;
9734 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9735 off = gen_rtx_CONST (Pmode, off);
9737 off = gen_rtx_PLUS (Pmode, pic, off);
9738 off = gen_const_mem (Pmode, off);
9739 set_mem_alias_set (off, ix86_GOT_alias_set ());
9741 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9743 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9744 off = force_reg (Pmode, off);
9745 return gen_rtx_PLUS (Pmode, base, off);
9749 base = get_thread_pointer (true);
9750 dest = gen_reg_rtx (Pmode);
9751 emit_insn (gen_subsi3 (dest, base, off));
9755 case TLS_MODEL_LOCAL_EXEC:
9756 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9757 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9758 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9759 off = gen_rtx_CONST (Pmode, off);
9761 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9763 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9764 return gen_rtx_PLUS (Pmode, base, off);
9768 base = get_thread_pointer (true);
9769 dest = gen_reg_rtx (Pmode);
9770 emit_insn (gen_subsi3 (dest, base, off));
9781 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9784 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9785 htab_t dllimport_map;
9788 get_dllimport_decl (tree decl)
9790 struct tree_map *h, in;
9794 size_t namelen, prefixlen;
9800 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9802 in.hash = htab_hash_pointer (decl);
9803 in.base.from = decl;
9804 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9805 h = (struct tree_map *) *loc;
9809 *loc = h = GGC_NEW (struct tree_map);
9811 h->base.from = decl;
9812 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9813 DECL_ARTIFICIAL (to) = 1;
9814 DECL_IGNORED_P (to) = 1;
9815 DECL_EXTERNAL (to) = 1;
9816 TREE_READONLY (to) = 1;
9818 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9819 name = targetm.strip_name_encoding (name);
9820 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9821 ? "*__imp_" : "*__imp__";
9822 namelen = strlen (name);
9823 prefixlen = strlen (prefix);
9824 imp_name = (char *) alloca (namelen + prefixlen + 1);
9825 memcpy (imp_name, prefix, prefixlen);
9826 memcpy (imp_name + prefixlen, name, namelen + 1);
9828 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9829 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9830 SET_SYMBOL_REF_DECL (rtl, to);
9831 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9833 rtl = gen_const_mem (Pmode, rtl);
9834 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9836 SET_DECL_RTL (to, rtl);
9837 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9842 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9843 true if we require the result be a register. */
9846 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9851 gcc_assert (SYMBOL_REF_DECL (symbol));
9852 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9854 x = DECL_RTL (imp_decl);
9856 x = force_reg (Pmode, x);
9860 /* Try machine-dependent ways of modifying an illegitimate address
9861 to be legitimate. If we find one, return the new, valid address.
9862 This macro is used in only one place: `memory_address' in explow.c.
9864 OLDX is the address as it was before break_out_memory_refs was called.
9865 In some cases it is useful to look at this to decide what needs to be done.
9867 MODE and WIN are passed so that this macro can use
9868 GO_IF_LEGITIMATE_ADDRESS.
9870 It is always safe for this macro to do nothing. It exists to recognize
9871 opportunities to optimize the output.
9873 For the 80386, we handle X+REG by loading X into a register R and
9874 using R+REG. R will go in a general reg and indexing will be used.
9875 However, if REG is a broken-out memory address or multiplication,
9876 nothing needs to be done because REG can certainly go in a general reg.
9878 When -fpic is used, special handling is needed for symbolic references.
9879 See comments by legitimize_pic_address in i386.c for details. */
9882 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9887 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9889 return legitimize_tls_address (x, (enum tls_model) log, false);
9890 if (GET_CODE (x) == CONST
9891 && GET_CODE (XEXP (x, 0)) == PLUS
9892 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9893 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9895 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9896 (enum tls_model) log, false);
9897 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9900 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9902 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9903 return legitimize_dllimport_symbol (x, true);
9904 if (GET_CODE (x) == CONST
9905 && GET_CODE (XEXP (x, 0)) == PLUS
9906 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9907 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9909 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9910 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9914 if (flag_pic && SYMBOLIC_CONST (x))
9915 return legitimize_pic_address (x, 0);
9917 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9918 if (GET_CODE (x) == ASHIFT
9919 && CONST_INT_P (XEXP (x, 1))
9920 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9923 log = INTVAL (XEXP (x, 1));
9924 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9925 GEN_INT (1 << log));
9928 if (GET_CODE (x) == PLUS)
9930 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9932 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9933 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9934 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9937 log = INTVAL (XEXP (XEXP (x, 0), 1));
9938 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9939 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9940 GEN_INT (1 << log));
9943 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9944 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9945 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9948 log = INTVAL (XEXP (XEXP (x, 1), 1));
9949 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9950 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9951 GEN_INT (1 << log));
9954 /* Put multiply first if it isn't already. */
9955 if (GET_CODE (XEXP (x, 1)) == MULT)
9957 rtx tmp = XEXP (x, 0);
9958 XEXP (x, 0) = XEXP (x, 1);
9963 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9964 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9965 created by virtual register instantiation, register elimination, and
9966 similar optimizations. */
9967 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9970 x = gen_rtx_PLUS (Pmode,
9971 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9972 XEXP (XEXP (x, 1), 0)),
9973 XEXP (XEXP (x, 1), 1));
9977 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9978 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9979 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9980 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
9981 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
9982 && CONSTANT_P (XEXP (x, 1)))
9985 rtx other = NULL_RTX;
9987 if (CONST_INT_P (XEXP (x, 1)))
9989 constant = XEXP (x, 1);
9990 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
9992 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
9994 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
9995 other = XEXP (x, 1);
10003 x = gen_rtx_PLUS (Pmode,
10004 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10005 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10006 plus_constant (other, INTVAL (constant)));
10010 if (changed && legitimate_address_p (mode, x, FALSE))
10013 if (GET_CODE (XEXP (x, 0)) == MULT)
10016 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10019 if (GET_CODE (XEXP (x, 1)) == MULT)
10022 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10026 && REG_P (XEXP (x, 1))
10027 && REG_P (XEXP (x, 0)))
10030 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10033 x = legitimize_pic_address (x, 0);
10036 if (changed && legitimate_address_p (mode, x, FALSE))
10039 if (REG_P (XEXP (x, 0)))
10041 rtx temp = gen_reg_rtx (Pmode);
10042 rtx val = force_operand (XEXP (x, 1), temp);
10044 emit_move_insn (temp, val);
10046 XEXP (x, 1) = temp;
10050 else if (REG_P (XEXP (x, 1)))
10052 rtx temp = gen_reg_rtx (Pmode);
10053 rtx val = force_operand (XEXP (x, 0), temp);
10055 emit_move_insn (temp, val);
10057 XEXP (x, 0) = temp;
10065 /* Print an integer constant expression in assembler syntax. Addition
10066 and subtraction are the only arithmetic that may appear in these
10067 expressions. FILE is the stdio stream to write to, X is the rtx, and
10068 CODE is the operand print code from the output string. */
10071 output_pic_addr_const (FILE *file, rtx x, int code)
10075 switch (GET_CODE (x))
10078 gcc_assert (flag_pic);
10083 if (! TARGET_MACHO || TARGET_64BIT)
10084 output_addr_const (file, x);
10087 const char *name = XSTR (x, 0);
10089 /* Mark the decl as referenced so that cgraph will
10090 output the function. */
10091 if (SYMBOL_REF_DECL (x))
10092 mark_decl_referenced (SYMBOL_REF_DECL (x));
10095 if (MACHOPIC_INDIRECT
10096 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10097 name = machopic_indirection_name (x, /*stub_p=*/true);
10099 assemble_name (file, name);
10101 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10102 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10103 fputs ("@PLT", file);
10110 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10111 assemble_name (asm_out_file, buf);
10115 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10119 /* This used to output parentheses around the expression,
10120 but that does not work on the 386 (either ATT or BSD assembler). */
10121 output_pic_addr_const (file, XEXP (x, 0), code);
10125 if (GET_MODE (x) == VOIDmode)
10127 /* We can use %d if the number is <32 bits and positive. */
10128 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10129 fprintf (file, "0x%lx%08lx",
10130 (unsigned long) CONST_DOUBLE_HIGH (x),
10131 (unsigned long) CONST_DOUBLE_LOW (x));
10133 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10136 /* We can't handle floating point constants;
10137 PRINT_OPERAND must handle them. */
10138 output_operand_lossage ("floating constant misused");
10142 /* Some assemblers need integer constants to appear first. */
10143 if (CONST_INT_P (XEXP (x, 0)))
10145 output_pic_addr_const (file, XEXP (x, 0), code);
10147 output_pic_addr_const (file, XEXP (x, 1), code);
10151 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10152 output_pic_addr_const (file, XEXP (x, 1), code);
10154 output_pic_addr_const (file, XEXP (x, 0), code);
10160 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10161 output_pic_addr_const (file, XEXP (x, 0), code);
10163 output_pic_addr_const (file, XEXP (x, 1), code);
10165 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10169 gcc_assert (XVECLEN (x, 0) == 1);
10170 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10171 switch (XINT (x, 1))
10174 fputs ("@GOT", file);
10176 case UNSPEC_GOTOFF:
10177 fputs ("@GOTOFF", file);
10179 case UNSPEC_PLTOFF:
10180 fputs ("@PLTOFF", file);
10182 case UNSPEC_GOTPCREL:
10183 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10184 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10186 case UNSPEC_GOTTPOFF:
10187 /* FIXME: This might be @TPOFF in Sun ld too. */
10188 fputs ("@GOTTPOFF", file);
10191 fputs ("@TPOFF", file);
10193 case UNSPEC_NTPOFF:
10195 fputs ("@TPOFF", file);
10197 fputs ("@NTPOFF", file);
10199 case UNSPEC_DTPOFF:
10200 fputs ("@DTPOFF", file);
10202 case UNSPEC_GOTNTPOFF:
10204 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10205 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10207 fputs ("@GOTNTPOFF", file);
10209 case UNSPEC_INDNTPOFF:
10210 fputs ("@INDNTPOFF", file);
10213 case UNSPEC_MACHOPIC_OFFSET:
10215 machopic_output_function_base_name (file);
10219 output_operand_lossage ("invalid UNSPEC as operand");
10225 output_operand_lossage ("invalid expression as operand");
10229 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10230 We need to emit DTP-relative relocations. */
10232 static void ATTRIBUTE_UNUSED
10233 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10235 fputs (ASM_LONG, file);
10236 output_addr_const (file, x);
10237 fputs ("@DTPOFF", file);
10243 fputs (", 0", file);
10246 gcc_unreachable ();
10250 /* Return true if X is a representation of the PIC register. This copes
10251 with calls from ix86_find_base_term, where the register might have
10252 been replaced by a cselib value. */
10255 ix86_pic_register_p (rtx x)
10257 if (GET_CODE (x) == VALUE)
10258 return (pic_offset_table_rtx
10259 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10261 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10264 /* In the name of slightly smaller debug output, and to cater to
10265 general assembler lossage, recognize PIC+GOTOFF and turn it back
10266 into a direct symbol reference.
10268 On Darwin, this is necessary to avoid a crash, because Darwin
10269 has a different PIC label for each routine but the DWARF debugging
10270 information is not associated with any particular routine, so it's
10271 necessary to remove references to the PIC label from RTL stored by
10272 the DWARF output code. */
10275 ix86_delegitimize_address (rtx orig_x)
10278 /* reg_addend is NULL or a multiple of some register. */
10279 rtx reg_addend = NULL_RTX;
10280 /* const_addend is NULL or a const_int. */
10281 rtx const_addend = NULL_RTX;
10282 /* This is the result, or NULL. */
10283 rtx result = NULL_RTX;
10290 if (GET_CODE (x) != CONST
10291 || GET_CODE (XEXP (x, 0)) != UNSPEC
10292 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10293 || !MEM_P (orig_x))
10295 return XVECEXP (XEXP (x, 0), 0, 0);
10298 if (GET_CODE (x) != PLUS
10299 || GET_CODE (XEXP (x, 1)) != CONST)
10302 if (ix86_pic_register_p (XEXP (x, 0)))
10303 /* %ebx + GOT/GOTOFF */
10305 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10307 /* %ebx + %reg * scale + GOT/GOTOFF */
10308 reg_addend = XEXP (x, 0);
10309 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10310 reg_addend = XEXP (reg_addend, 1);
10311 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10312 reg_addend = XEXP (reg_addend, 0);
10315 if (!REG_P (reg_addend)
10316 && GET_CODE (reg_addend) != MULT
10317 && GET_CODE (reg_addend) != ASHIFT)
10323 x = XEXP (XEXP (x, 1), 0);
10324 if (GET_CODE (x) == PLUS
10325 && CONST_INT_P (XEXP (x, 1)))
10327 const_addend = XEXP (x, 1);
10331 if (GET_CODE (x) == UNSPEC
10332 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10333 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10334 result = XVECEXP (x, 0, 0);
10336 if (TARGET_MACHO && darwin_local_data_pic (x)
10337 && !MEM_P (orig_x))
10338 result = XVECEXP (x, 0, 0);
10344 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10346 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10350 /* If X is a machine specific address (i.e. a symbol or label being
10351 referenced as a displacement from the GOT implemented using an
10352 UNSPEC), then return the base term. Otherwise return X. */
10355 ix86_find_base_term (rtx x)
10361 if (GET_CODE (x) != CONST)
10363 term = XEXP (x, 0);
10364 if (GET_CODE (term) == PLUS
10365 && (CONST_INT_P (XEXP (term, 1))
10366 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10367 term = XEXP (term, 0);
10368 if (GET_CODE (term) != UNSPEC
10369 || XINT (term, 1) != UNSPEC_GOTPCREL)
10372 return XVECEXP (term, 0, 0);
10375 return ix86_delegitimize_address (x);
10379 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10380 int fp, FILE *file)
10382 const char *suffix;
10384 if (mode == CCFPmode || mode == CCFPUmode)
10386 enum rtx_code second_code, bypass_code;
10387 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10388 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10389 code = ix86_fp_compare_code_to_integer (code);
10393 code = reverse_condition (code);
10444 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10448 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10449 Those same assemblers have the same but opposite lossage on cmov. */
10450 if (mode == CCmode)
10451 suffix = fp ? "nbe" : "a";
10452 else if (mode == CCCmode)
10455 gcc_unreachable ();
10471 gcc_unreachable ();
10475 gcc_assert (mode == CCmode || mode == CCCmode);
10492 gcc_unreachable ();
10496 /* ??? As above. */
10497 gcc_assert (mode == CCmode || mode == CCCmode);
10498 suffix = fp ? "nb" : "ae";
10501 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10505 /* ??? As above. */
10506 if (mode == CCmode)
10508 else if (mode == CCCmode)
10509 suffix = fp ? "nb" : "ae";
10511 gcc_unreachable ();
10514 suffix = fp ? "u" : "p";
10517 suffix = fp ? "nu" : "np";
10520 gcc_unreachable ();
10522 fputs (suffix, file);
10525 /* Print the name of register X to FILE based on its machine mode and number.
10526 If CODE is 'w', pretend the mode is HImode.
10527 If CODE is 'b', pretend the mode is QImode.
10528 If CODE is 'k', pretend the mode is SImode.
10529 If CODE is 'q', pretend the mode is DImode.
10530 If CODE is 'x', pretend the mode is V4SFmode.
10531 If CODE is 't', pretend the mode is V8SFmode.
10532 If CODE is 'h', pretend the reg is the 'high' byte register.
10533 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10534 If CODE is 'd', duplicate the operand for AVX instruction.
10538 print_reg (rtx x, int code, FILE *file)
10541 bool duplicated = code == 'd' && TARGET_AVX;
10543 gcc_assert (x == pc_rtx
10544 || (REGNO (x) != ARG_POINTER_REGNUM
10545 && REGNO (x) != FRAME_POINTER_REGNUM
10546 && REGNO (x) != FLAGS_REG
10547 && REGNO (x) != FPSR_REG
10548 && REGNO (x) != FPCR_REG));
10550 if (ASSEMBLER_DIALECT == ASM_ATT)
10555 gcc_assert (TARGET_64BIT);
10556 fputs ("rip", file);
10560 if (code == 'w' || MMX_REG_P (x))
10562 else if (code == 'b')
10564 else if (code == 'k')
10566 else if (code == 'q')
10568 else if (code == 'y')
10570 else if (code == 'h')
10572 else if (code == 'x')
10574 else if (code == 't')
10577 code = GET_MODE_SIZE (GET_MODE (x));
10579 /* Irritatingly, AMD extended registers use different naming convention
10580 from the normal registers. */
10581 if (REX_INT_REG_P (x))
10583 gcc_assert (TARGET_64BIT);
10587 error ("extended registers have no high halves");
10590 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10593 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10596 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10599 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10602 error ("unsupported operand size for extended register");
10612 if (STACK_TOP_P (x))
10621 if (! ANY_FP_REG_P (x))
10622 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10627 reg = hi_reg_name[REGNO (x)];
10630 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10632 reg = qi_reg_name[REGNO (x)];
10635 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10637 reg = qi_high_reg_name[REGNO (x)];
10642 gcc_assert (!duplicated);
10644 fputs (hi_reg_name[REGNO (x)] + 1, file);
10649 gcc_unreachable ();
10655 if (ASSEMBLER_DIALECT == ASM_ATT)
10656 fprintf (file, ", %%%s", reg);
10658 fprintf (file, ", %s", reg);
10662 /* Locate some local-dynamic symbol still in use by this function
10663 so that we can print its name in some tls_local_dynamic_base
10667 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10671 if (GET_CODE (x) == SYMBOL_REF
10672 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10674 cfun->machine->some_ld_name = XSTR (x, 0);
10681 static const char *
10682 get_some_local_dynamic_name (void)
10686 if (cfun->machine->some_ld_name)
10687 return cfun->machine->some_ld_name;
10689 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10691 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10692 return cfun->machine->some_ld_name;
10694 gcc_unreachable ();
10697 /* Meaning of CODE:
10698 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10699 C -- print opcode suffix for set/cmov insn.
10700 c -- like C, but print reversed condition
10701 E,e -- likewise, but for compare-and-branch fused insn.
10702 F,f -- likewise, but for floating-point.
10703 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10705 R -- print the prefix for register names.
10706 z -- print the opcode suffix for the size of the current operand.
10707 * -- print a star (in certain assembler syntax)
10708 A -- print an absolute memory reference.
10709 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10710 s -- print a shift double count, followed by the assemblers argument
10712 b -- print the QImode name of the register for the indicated operand.
10713 %b0 would print %al if operands[0] is reg 0.
10714 w -- likewise, print the HImode name of the register.
10715 k -- likewise, print the SImode name of the register.
10716 q -- likewise, print the DImode name of the register.
10717 x -- likewise, print the V4SFmode name of the register.
10718 t -- likewise, print the V8SFmode name of the register.
10719 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10720 y -- print "st(0)" instead of "st" as a register.
10721 d -- print duplicated register operand for AVX instruction.
10722 D -- print condition for SSE cmp instruction.
10723 P -- if PIC, print an @PLT suffix.
10724 X -- don't print any sort of PIC '@' suffix for a symbol.
10725 & -- print some in-use local-dynamic symbol name.
10726 H -- print a memory address offset by 8; used for sse high-parts
10727 Y -- print condition for SSE5 com* instruction.
10728 + -- print a branch hint as 'cs' or 'ds' prefix
10729 ; -- print a semicolon (after prefixes due to bug in older gas).
10733 print_operand (FILE *file, rtx x, int code)
10740 if (ASSEMBLER_DIALECT == ASM_ATT)
10745 assemble_name (file, get_some_local_dynamic_name ());
10749 switch (ASSEMBLER_DIALECT)
10756 /* Intel syntax. For absolute addresses, registers should not
10757 be surrounded by braces. */
10761 PRINT_OPERAND (file, x, 0);
10768 gcc_unreachable ();
10771 PRINT_OPERAND (file, x, 0);
10776 if (ASSEMBLER_DIALECT == ASM_ATT)
10781 if (ASSEMBLER_DIALECT == ASM_ATT)
10786 if (ASSEMBLER_DIALECT == ASM_ATT)
10791 if (ASSEMBLER_DIALECT == ASM_ATT)
10796 if (ASSEMBLER_DIALECT == ASM_ATT)
10801 if (ASSEMBLER_DIALECT == ASM_ATT)
10806 /* 387 opcodes don't get size suffixes if the operands are
10808 if (STACK_REG_P (x))
10811 /* Likewise if using Intel opcodes. */
10812 if (ASSEMBLER_DIALECT == ASM_INTEL)
10815 /* This is the size of op from size of operand. */
10816 switch (GET_MODE_SIZE (GET_MODE (x)))
10825 #ifdef HAVE_GAS_FILDS_FISTS
10835 if (GET_MODE (x) == SFmode)
10850 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10854 #ifdef GAS_MNEMONICS
10869 gcc_unreachable ();
10886 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10888 PRINT_OPERAND (file, x, 0);
10889 fputs (", ", file);
10894 /* Little bit of braindamage here. The SSE compare instructions
10895 does use completely different names for the comparisons that the
10896 fp conditional moves. */
10899 switch (GET_CODE (x))
10902 fputs ("eq", file);
10905 fputs ("eq_us", file);
10908 fputs ("lt", file);
10911 fputs ("nge", file);
10914 fputs ("le", file);
10917 fputs ("ngt", file);
10920 fputs ("unord", file);
10923 fputs ("neq", file);
10926 fputs ("neq_oq", file);
10929 fputs ("ge", file);
10932 fputs ("nlt", file);
10935 fputs ("gt", file);
10938 fputs ("nle", file);
10941 fputs ("ord", file);
10944 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10950 switch (GET_CODE (x))
10954 fputs ("eq", file);
10958 fputs ("lt", file);
10962 fputs ("le", file);
10965 fputs ("unord", file);
10969 fputs ("neq", file);
10973 fputs ("nlt", file);
10977 fputs ("nle", file);
10980 fputs ("ord", file);
10983 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10989 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10990 if (ASSEMBLER_DIALECT == ASM_ATT)
10992 switch (GET_MODE (x))
10994 case HImode: putc ('w', file); break;
10996 case SFmode: putc ('l', file); break;
10998 case DFmode: putc ('q', file); break;
10999 default: gcc_unreachable ();
11006 if (!COMPARISON_P (x))
11008 output_operand_lossage ("operand is neither a constant nor a "
11009 "condition code, invalid operand code "
11013 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11016 if (!COMPARISON_P (x))
11018 output_operand_lossage ("operand is neither a constant nor a "
11019 "condition code, invalid operand code "
11023 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11024 if (ASSEMBLER_DIALECT == ASM_ATT)
11027 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11030 /* Like above, but reverse condition */
11032 /* Check to see if argument to %c is really a constant
11033 and not a condition code which needs to be reversed. */
11034 if (!COMPARISON_P (x))
11036 output_operand_lossage ("operand is neither a constant nor a "
11037 "condition code, invalid operand "
11041 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11044 if (!COMPARISON_P (x))
11046 output_operand_lossage ("operand is neither a constant nor a "
11047 "condition code, invalid operand "
11051 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11052 if (ASSEMBLER_DIALECT == ASM_ATT)
11055 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11059 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11063 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11067 /* It doesn't actually matter what mode we use here, as we're
11068 only going to use this for printing. */
11069 x = adjust_address_nv (x, DImode, 8);
11077 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11080 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11083 int pred_val = INTVAL (XEXP (x, 0));
11085 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11086 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11088 int taken = pred_val > REG_BR_PROB_BASE / 2;
11089 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11091 /* Emit hints only in the case default branch prediction
11092 heuristics would fail. */
11093 if (taken != cputaken)
11095 /* We use 3e (DS) prefix for taken branches and
11096 2e (CS) prefix for not taken branches. */
11098 fputs ("ds ; ", file);
11100 fputs ("cs ; ", file);
11108 switch (GET_CODE (x))
11111 fputs ("neq", file);
11114 fputs ("eq", file);
11118 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11122 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11126 fputs ("le", file);
11130 fputs ("lt", file);
11133 fputs ("unord", file);
11136 fputs ("ord", file);
11139 fputs ("ueq", file);
11142 fputs ("nlt", file);
11145 fputs ("nle", file);
11148 fputs ("ule", file);
11151 fputs ("ult", file);
11154 fputs ("une", file);
11157 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11164 fputs (" ; ", file);
11171 output_operand_lossage ("invalid operand code '%c'", code);
11176 print_reg (x, code, file);
11178 else if (MEM_P (x))
11180 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11181 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11182 && GET_MODE (x) != BLKmode)
11185 switch (GET_MODE_SIZE (GET_MODE (x)))
11187 case 1: size = "BYTE"; break;
11188 case 2: size = "WORD"; break;
11189 case 4: size = "DWORD"; break;
11190 case 8: size = "QWORD"; break;
11191 case 12: size = "XWORD"; break;
11193 if (GET_MODE (x) == XFmode)
11199 gcc_unreachable ();
11202 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11205 else if (code == 'w')
11207 else if (code == 'k')
11210 fputs (size, file);
11211 fputs (" PTR ", file);
11215 /* Avoid (%rip) for call operands. */
11216 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11217 && !CONST_INT_P (x))
11218 output_addr_const (file, x);
11219 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11220 output_operand_lossage ("invalid constraints for operand");
11222 output_address (x);
11225 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11230 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11231 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11233 if (ASSEMBLER_DIALECT == ASM_ATT)
11235 fprintf (file, "0x%08lx", (long unsigned int) l);
11238 /* These float cases don't actually occur as immediate operands. */
11239 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11243 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11244 fprintf (file, "%s", dstr);
11247 else if (GET_CODE (x) == CONST_DOUBLE
11248 && GET_MODE (x) == XFmode)
11252 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11253 fprintf (file, "%s", dstr);
11258 /* We have patterns that allow zero sets of memory, for instance.
11259 In 64-bit mode, we should probably support all 8-byte vectors,
11260 since we can in fact encode that into an immediate. */
11261 if (GET_CODE (x) == CONST_VECTOR)
11263 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11269 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11271 if (ASSEMBLER_DIALECT == ASM_ATT)
11274 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11275 || GET_CODE (x) == LABEL_REF)
11277 if (ASSEMBLER_DIALECT == ASM_ATT)
11280 fputs ("OFFSET FLAT:", file);
11283 if (CONST_INT_P (x))
11284 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11286 output_pic_addr_const (file, x, code);
11288 output_addr_const (file, x);
11292 /* Print a memory operand whose address is ADDR. */
11295 print_operand_address (FILE *file, rtx addr)
11297 struct ix86_address parts;
11298 rtx base, index, disp;
11300 int ok = ix86_decompose_address (addr, &parts);
11305 index = parts.index;
11307 scale = parts.scale;
11315 if (ASSEMBLER_DIALECT == ASM_ATT)
11317 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11320 gcc_unreachable ();
11323 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11324 if (TARGET_64BIT && !base && !index)
11328 if (GET_CODE (disp) == CONST
11329 && GET_CODE (XEXP (disp, 0)) == PLUS
11330 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11331 symbol = XEXP (XEXP (disp, 0), 0);
11333 if (GET_CODE (symbol) == LABEL_REF
11334 || (GET_CODE (symbol) == SYMBOL_REF
11335 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11338 if (!base && !index)
11340 /* Displacement only requires special attention. */
11342 if (CONST_INT_P (disp))
11344 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11345 fputs ("ds:", file);
11346 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11349 output_pic_addr_const (file, disp, 0);
11351 output_addr_const (file, disp);
11355 if (ASSEMBLER_DIALECT == ASM_ATT)
11360 output_pic_addr_const (file, disp, 0);
11361 else if (GET_CODE (disp) == LABEL_REF)
11362 output_asm_label (disp);
11364 output_addr_const (file, disp);
11369 print_reg (base, 0, file);
11373 print_reg (index, 0, file);
11375 fprintf (file, ",%d", scale);
11381 rtx offset = NULL_RTX;
11385 /* Pull out the offset of a symbol; print any symbol itself. */
11386 if (GET_CODE (disp) == CONST
11387 && GET_CODE (XEXP (disp, 0)) == PLUS
11388 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11390 offset = XEXP (XEXP (disp, 0), 1);
11391 disp = gen_rtx_CONST (VOIDmode,
11392 XEXP (XEXP (disp, 0), 0));
11396 output_pic_addr_const (file, disp, 0);
11397 else if (GET_CODE (disp) == LABEL_REF)
11398 output_asm_label (disp);
11399 else if (CONST_INT_P (disp))
11402 output_addr_const (file, disp);
11408 print_reg (base, 0, file);
11411 if (INTVAL (offset) >= 0)
11413 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11417 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11424 print_reg (index, 0, file);
11426 fprintf (file, "*%d", scale);
11434 output_addr_const_extra (FILE *file, rtx x)
11438 if (GET_CODE (x) != UNSPEC)
11441 op = XVECEXP (x, 0, 0);
11442 switch (XINT (x, 1))
11444 case UNSPEC_GOTTPOFF:
11445 output_addr_const (file, op);
11446 /* FIXME: This might be @TPOFF in Sun ld. */
11447 fputs ("@GOTTPOFF", file);
11450 output_addr_const (file, op);
11451 fputs ("@TPOFF", file);
11453 case UNSPEC_NTPOFF:
11454 output_addr_const (file, op);
11456 fputs ("@TPOFF", file);
11458 fputs ("@NTPOFF", file);
11460 case UNSPEC_DTPOFF:
11461 output_addr_const (file, op);
11462 fputs ("@DTPOFF", file);
11464 case UNSPEC_GOTNTPOFF:
11465 output_addr_const (file, op);
11467 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11468 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11470 fputs ("@GOTNTPOFF", file);
11472 case UNSPEC_INDNTPOFF:
11473 output_addr_const (file, op);
11474 fputs ("@INDNTPOFF", file);
11477 case UNSPEC_MACHOPIC_OFFSET:
11478 output_addr_const (file, op);
11480 machopic_output_function_base_name (file);
11491 /* Split one or more DImode RTL references into pairs of SImode
11492 references. The RTL can be REG, offsettable MEM, integer constant, or
11493 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11494 split and "num" is its length. lo_half and hi_half are output arrays
11495 that parallel "operands". */
11498 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11502 rtx op = operands[num];
11504 /* simplify_subreg refuse to split volatile memory addresses,
11505 but we still have to handle it. */
11508 lo_half[num] = adjust_address (op, SImode, 0);
11509 hi_half[num] = adjust_address (op, SImode, 4);
11513 lo_half[num] = simplify_gen_subreg (SImode, op,
11514 GET_MODE (op) == VOIDmode
11515 ? DImode : GET_MODE (op), 0);
11516 hi_half[num] = simplify_gen_subreg (SImode, op,
11517 GET_MODE (op) == VOIDmode
11518 ? DImode : GET_MODE (op), 4);
11522 /* Split one or more TImode RTL references into pairs of DImode
11523 references. The RTL can be REG, offsettable MEM, integer constant, or
11524 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11525 split and "num" is its length. lo_half and hi_half are output arrays
11526 that parallel "operands". */
11529 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11533 rtx op = operands[num];
11535 /* simplify_subreg refuse to split volatile memory addresses, but we
11536 still have to handle it. */
11539 lo_half[num] = adjust_address (op, DImode, 0);
11540 hi_half[num] = adjust_address (op, DImode, 8);
11544 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11545 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11550 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11551 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11552 is the expression of the binary operation. The output may either be
11553 emitted here, or returned to the caller, like all output_* functions.
11555 There is no guarantee that the operands are the same mode, as they
11556 might be within FLOAT or FLOAT_EXTEND expressions. */
11558 #ifndef SYSV386_COMPAT
11559 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11560 wants to fix the assemblers because that causes incompatibility
11561 with gcc. No-one wants to fix gcc because that causes
11562 incompatibility with assemblers... You can use the option of
11563 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11564 #define SYSV386_COMPAT 1
11568 output_387_binary_op (rtx insn, rtx *operands)
11570 static char buf[40];
11573 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11575 #ifdef ENABLE_CHECKING
11576 /* Even if we do not want to check the inputs, this documents input
11577 constraints. Which helps in understanding the following code. */
11578 if (STACK_REG_P (operands[0])
11579 && ((REG_P (operands[1])
11580 && REGNO (operands[0]) == REGNO (operands[1])
11581 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11582 || (REG_P (operands[2])
11583 && REGNO (operands[0]) == REGNO (operands[2])
11584 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11585 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11588 gcc_assert (is_sse);
11591 switch (GET_CODE (operands[3]))
11594 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11595 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11603 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11604 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11612 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11613 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11621 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11622 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11630 gcc_unreachable ();
11637 strcpy (buf, ssep);
11638 if (GET_MODE (operands[0]) == SFmode)
11639 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11641 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11645 strcpy (buf, ssep + 1);
11646 if (GET_MODE (operands[0]) == SFmode)
11647 strcat (buf, "ss\t{%2, %0|%0, %2}");
11649 strcat (buf, "sd\t{%2, %0|%0, %2}");
11655 switch (GET_CODE (operands[3]))
11659 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11661 rtx temp = operands[2];
11662 operands[2] = operands[1];
11663 operands[1] = temp;
11666 /* know operands[0] == operands[1]. */
11668 if (MEM_P (operands[2]))
11674 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11676 if (STACK_TOP_P (operands[0]))
11677 /* How is it that we are storing to a dead operand[2]?
11678 Well, presumably operands[1] is dead too. We can't
11679 store the result to st(0) as st(0) gets popped on this
11680 instruction. Instead store to operands[2] (which I
11681 think has to be st(1)). st(1) will be popped later.
11682 gcc <= 2.8.1 didn't have this check and generated
11683 assembly code that the Unixware assembler rejected. */
11684 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11686 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11690 if (STACK_TOP_P (operands[0]))
11691 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11693 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11698 if (MEM_P (operands[1]))
11704 if (MEM_P (operands[2]))
11710 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11713 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11714 derived assemblers, confusingly reverse the direction of
11715 the operation for fsub{r} and fdiv{r} when the
11716 destination register is not st(0). The Intel assembler
11717 doesn't have this brain damage. Read !SYSV386_COMPAT to
11718 figure out what the hardware really does. */
11719 if (STACK_TOP_P (operands[0]))
11720 p = "{p\t%0, %2|rp\t%2, %0}";
11722 p = "{rp\t%2, %0|p\t%0, %2}";
11724 if (STACK_TOP_P (operands[0]))
11725 /* As above for fmul/fadd, we can't store to st(0). */
11726 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11728 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11733 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11736 if (STACK_TOP_P (operands[0]))
11737 p = "{rp\t%0, %1|p\t%1, %0}";
11739 p = "{p\t%1, %0|rp\t%0, %1}";
11741 if (STACK_TOP_P (operands[0]))
11742 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11744 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11749 if (STACK_TOP_P (operands[0]))
11751 if (STACK_TOP_P (operands[1]))
11752 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11754 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11757 else if (STACK_TOP_P (operands[1]))
11760 p = "{\t%1, %0|r\t%0, %1}";
11762 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11768 p = "{r\t%2, %0|\t%0, %2}";
11770 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11776 gcc_unreachable ();
11783 /* Return needed mode for entity in optimize_mode_switching pass. */
11786 ix86_mode_needed (int entity, rtx insn)
11788 enum attr_i387_cw mode;
11790 /* The mode UNINITIALIZED is used to store control word after a
11791 function call or ASM pattern. The mode ANY specify that function
11792 has no requirements on the control word and make no changes in the
11793 bits we are interested in. */
11796 || (NONJUMP_INSN_P (insn)
11797 && (asm_noperands (PATTERN (insn)) >= 0
11798 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11799 return I387_CW_UNINITIALIZED;
11801 if (recog_memoized (insn) < 0)
11802 return I387_CW_ANY;
11804 mode = get_attr_i387_cw (insn);
11809 if (mode == I387_CW_TRUNC)
11814 if (mode == I387_CW_FLOOR)
11819 if (mode == I387_CW_CEIL)
11824 if (mode == I387_CW_MASK_PM)
11829 gcc_unreachable ();
11832 return I387_CW_ANY;
11835 /* Output code to initialize control word copies used by trunc?f?i and
11836 rounding patterns. CURRENT_MODE is set to current control word,
11837 while NEW_MODE is set to new control word. */
11840 emit_i387_cw_initialization (int mode)
11842 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11845 enum ix86_stack_slot slot;
11847 rtx reg = gen_reg_rtx (HImode);
11849 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11850 emit_move_insn (reg, copy_rtx (stored_mode));
11852 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11853 || optimize_function_for_size_p (cfun))
11857 case I387_CW_TRUNC:
11858 /* round toward zero (truncate) */
11859 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11860 slot = SLOT_CW_TRUNC;
11863 case I387_CW_FLOOR:
11864 /* round down toward -oo */
11865 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11866 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11867 slot = SLOT_CW_FLOOR;
11871 /* round up toward +oo */
11872 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11873 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11874 slot = SLOT_CW_CEIL;
11877 case I387_CW_MASK_PM:
11878 /* mask precision exception for nearbyint() */
11879 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11880 slot = SLOT_CW_MASK_PM;
11884 gcc_unreachable ();
11891 case I387_CW_TRUNC:
11892 /* round toward zero (truncate) */
11893 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11894 slot = SLOT_CW_TRUNC;
11897 case I387_CW_FLOOR:
11898 /* round down toward -oo */
11899 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11900 slot = SLOT_CW_FLOOR;
11904 /* round up toward +oo */
11905 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11906 slot = SLOT_CW_CEIL;
11909 case I387_CW_MASK_PM:
11910 /* mask precision exception for nearbyint() */
11911 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11912 slot = SLOT_CW_MASK_PM;
11916 gcc_unreachable ();
11920 gcc_assert (slot < MAX_386_STACK_LOCALS);
11922 new_mode = assign_386_stack_local (HImode, slot);
11923 emit_move_insn (new_mode, reg);
11926 /* Output code for INSN to convert a float to a signed int. OPERANDS
11927 are the insn operands. The output may be [HSD]Imode and the input
11928 operand may be [SDX]Fmode. */
11931 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11933 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11934 int dimode_p = GET_MODE (operands[0]) == DImode;
11935 int round_mode = get_attr_i387_cw (insn);
11937 /* Jump through a hoop or two for DImode, since the hardware has no
11938 non-popping instruction. We used to do this a different way, but
11939 that was somewhat fragile and broke with post-reload splitters. */
11940 if ((dimode_p || fisttp) && !stack_top_dies)
11941 output_asm_insn ("fld\t%y1", operands);
11943 gcc_assert (STACK_TOP_P (operands[1]));
11944 gcc_assert (MEM_P (operands[0]));
11945 gcc_assert (GET_MODE (operands[1]) != TFmode);
11948 output_asm_insn ("fisttp%z0\t%0", operands);
11951 if (round_mode != I387_CW_ANY)
11952 output_asm_insn ("fldcw\t%3", operands);
11953 if (stack_top_dies || dimode_p)
11954 output_asm_insn ("fistp%z0\t%0", operands);
11956 output_asm_insn ("fist%z0\t%0", operands);
11957 if (round_mode != I387_CW_ANY)
11958 output_asm_insn ("fldcw\t%2", operands);
11964 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11965 have the values zero or one, indicates the ffreep insn's operand
11966 from the OPERANDS array. */
11968 static const char *
11969 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11971 if (TARGET_USE_FFREEP)
11972 #if HAVE_AS_IX86_FFREEP
11973 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11976 static char retval[] = ".word\t0xc_df";
11977 int regno = REGNO (operands[opno]);
11979 gcc_assert (FP_REGNO_P (regno));
11981 retval[9] = '0' + (regno - FIRST_STACK_REG);
11986 return opno ? "fstp\t%y1" : "fstp\t%y0";
11990 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11991 should be used. UNORDERED_P is true when fucom should be used. */
11994 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
11996 int stack_top_dies;
11997 rtx cmp_op0, cmp_op1;
11998 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12002 cmp_op0 = operands[0];
12003 cmp_op1 = operands[1];
12007 cmp_op0 = operands[1];
12008 cmp_op1 = operands[2];
12013 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12014 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12015 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12016 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12018 if (GET_MODE (operands[0]) == SFmode)
12020 return &ucomiss[TARGET_AVX ? 0 : 1];
12022 return &comiss[TARGET_AVX ? 0 : 1];
12025 return &ucomisd[TARGET_AVX ? 0 : 1];
12027 return &comisd[TARGET_AVX ? 0 : 1];
12030 gcc_assert (STACK_TOP_P (cmp_op0));
12032 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12034 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12036 if (stack_top_dies)
12038 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12039 return output_387_ffreep (operands, 1);
12042 return "ftst\n\tfnstsw\t%0";
12045 if (STACK_REG_P (cmp_op1)
12047 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12048 && REGNO (cmp_op1) != FIRST_STACK_REG)
12050 /* If both the top of the 387 stack dies, and the other operand
12051 is also a stack register that dies, then this must be a
12052 `fcompp' float compare */
12056 /* There is no double popping fcomi variant. Fortunately,
12057 eflags is immune from the fstp's cc clobbering. */
12059 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12061 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12062 return output_387_ffreep (operands, 0);
12067 return "fucompp\n\tfnstsw\t%0";
12069 return "fcompp\n\tfnstsw\t%0";
12074 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12076 static const char * const alt[16] =
12078 "fcom%z2\t%y2\n\tfnstsw\t%0",
12079 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12080 "fucom%z2\t%y2\n\tfnstsw\t%0",
12081 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12083 "ficom%z2\t%y2\n\tfnstsw\t%0",
12084 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12088 "fcomi\t{%y1, %0|%0, %y1}",
12089 "fcomip\t{%y1, %0|%0, %y1}",
12090 "fucomi\t{%y1, %0|%0, %y1}",
12091 "fucomip\t{%y1, %0|%0, %y1}",
12102 mask = eflags_p << 3;
12103 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12104 mask |= unordered_p << 1;
12105 mask |= stack_top_dies;
12107 gcc_assert (mask < 16);
12116 ix86_output_addr_vec_elt (FILE *file, int value)
12118 const char *directive = ASM_LONG;
12122 directive = ASM_QUAD;
12124 gcc_assert (!TARGET_64BIT);
12127 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12131 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12133 const char *directive = ASM_LONG;
12136 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12137 directive = ASM_QUAD;
12139 gcc_assert (!TARGET_64BIT);
12141 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12142 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12143 fprintf (file, "%s%s%d-%s%d\n",
12144 directive, LPREFIX, value, LPREFIX, rel);
12145 else if (HAVE_AS_GOTOFF_IN_DATA)
12146 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12148 else if (TARGET_MACHO)
12150 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12151 machopic_output_function_base_name (file);
12152 fprintf(file, "\n");
12156 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12157 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12160 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12164 ix86_expand_clear (rtx dest)
12168 /* We play register width games, which are only valid after reload. */
12169 gcc_assert (reload_completed);
12171 /* Avoid HImode and its attendant prefix byte. */
12172 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12173 dest = gen_rtx_REG (SImode, REGNO (dest));
12174 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12176 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12177 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12179 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12180 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12186 /* X is an unchanging MEM. If it is a constant pool reference, return
12187 the constant pool rtx, else NULL. */
12190 maybe_get_pool_constant (rtx x)
12192 x = ix86_delegitimize_address (XEXP (x, 0));
12194 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12195 return get_pool_constant (x);
12201 ix86_expand_move (enum machine_mode mode, rtx operands[])
12204 enum tls_model model;
12209 if (GET_CODE (op1) == SYMBOL_REF)
12211 model = SYMBOL_REF_TLS_MODEL (op1);
12214 op1 = legitimize_tls_address (op1, model, true);
12215 op1 = force_operand (op1, op0);
12219 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12220 && SYMBOL_REF_DLLIMPORT_P (op1))
12221 op1 = legitimize_dllimport_symbol (op1, false);
12223 else if (GET_CODE (op1) == CONST
12224 && GET_CODE (XEXP (op1, 0)) == PLUS
12225 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12227 rtx addend = XEXP (XEXP (op1, 0), 1);
12228 rtx symbol = XEXP (XEXP (op1, 0), 0);
12231 model = SYMBOL_REF_TLS_MODEL (symbol);
12233 tmp = legitimize_tls_address (symbol, model, true);
12234 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12235 && SYMBOL_REF_DLLIMPORT_P (symbol))
12236 tmp = legitimize_dllimport_symbol (symbol, true);
12240 tmp = force_operand (tmp, NULL);
12241 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12242 op0, 1, OPTAB_DIRECT);
12248 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12250 if (TARGET_MACHO && !TARGET_64BIT)
12255 rtx temp = ((reload_in_progress
12256 || ((op0 && REG_P (op0))
12258 ? op0 : gen_reg_rtx (Pmode));
12259 op1 = machopic_indirect_data_reference (op1, temp);
12260 op1 = machopic_legitimize_pic_address (op1, mode,
12261 temp == op1 ? 0 : temp);
12263 else if (MACHOPIC_INDIRECT)
12264 op1 = machopic_indirect_data_reference (op1, 0);
12272 op1 = force_reg (Pmode, op1);
12273 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12275 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12276 op1 = legitimize_pic_address (op1, reg);
12285 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12286 || !push_operand (op0, mode))
12288 op1 = force_reg (mode, op1);
12290 if (push_operand (op0, mode)
12291 && ! general_no_elim_operand (op1, mode))
12292 op1 = copy_to_mode_reg (mode, op1);
12294 /* Force large constants in 64bit compilation into register
12295 to get them CSEed. */
12296 if (can_create_pseudo_p ()
12297 && (mode == DImode) && TARGET_64BIT
12298 && immediate_operand (op1, mode)
12299 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12300 && !register_operand (op0, mode)
12302 op1 = copy_to_mode_reg (mode, op1);
12304 if (can_create_pseudo_p ()
12305 && FLOAT_MODE_P (mode)
12306 && GET_CODE (op1) == CONST_DOUBLE)
12308 /* If we are loading a floating point constant to a register,
12309 force the value to memory now, since we'll get better code
12310 out the back end. */
12312 op1 = validize_mem (force_const_mem (mode, op1));
12313 if (!register_operand (op0, mode))
12315 rtx temp = gen_reg_rtx (mode);
12316 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12317 emit_move_insn (op0, temp);
12323 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12327 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12329 rtx op0 = operands[0], op1 = operands[1];
12330 unsigned int align = GET_MODE_ALIGNMENT (mode);
12332 /* Force constants other than zero into memory. We do not know how
12333 the instructions used to build constants modify the upper 64 bits
12334 of the register, once we have that information we may be able
12335 to handle some of them more efficiently. */
12336 if (can_create_pseudo_p ()
12337 && register_operand (op0, mode)
12338 && (CONSTANT_P (op1)
12339 || (GET_CODE (op1) == SUBREG
12340 && CONSTANT_P (SUBREG_REG (op1))))
12341 && standard_sse_constant_p (op1) <= 0)
12342 op1 = validize_mem (force_const_mem (mode, op1));
12344 /* We need to check memory alignment for SSE mode since attribute
12345 can make operands unaligned. */
12346 if (can_create_pseudo_p ()
12347 && SSE_REG_MODE_P (mode)
12348 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12349 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12353 /* ix86_expand_vector_move_misalign() does not like constants ... */
12354 if (CONSTANT_P (op1)
12355 || (GET_CODE (op1) == SUBREG
12356 && CONSTANT_P (SUBREG_REG (op1))))
12357 op1 = validize_mem (force_const_mem (mode, op1));
12359 /* ... nor both arguments in memory. */
12360 if (!register_operand (op0, mode)
12361 && !register_operand (op1, mode))
12362 op1 = force_reg (mode, op1);
12364 tmp[0] = op0; tmp[1] = op1;
12365 ix86_expand_vector_move_misalign (mode, tmp);
12369 /* Make operand1 a register if it isn't already. */
12370 if (can_create_pseudo_p ()
12371 && !register_operand (op0, mode)
12372 && !register_operand (op1, mode))
12374 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12378 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12381 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12382 straight to ix86_expand_vector_move. */
12383 /* Code generation for scalar reg-reg moves of single and double precision data:
12384 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12388 if (x86_sse_partial_reg_dependency == true)
12393 Code generation for scalar loads of double precision data:
12394 if (x86_sse_split_regs == true)
12395 movlpd mem, reg (gas syntax)
12399 Code generation for unaligned packed loads of single precision data
12400 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12401 if (x86_sse_unaligned_move_optimal)
12404 if (x86_sse_partial_reg_dependency == true)
12416 Code generation for unaligned packed loads of double precision data
12417 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12418 if (x86_sse_unaligned_move_optimal)
12421 if (x86_sse_split_regs == true)
12434 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12443 switch (GET_MODE_CLASS (mode))
12445 case MODE_VECTOR_INT:
12447 switch (GET_MODE_SIZE (mode))
12450 op0 = gen_lowpart (V16QImode, op0);
12451 op1 = gen_lowpart (V16QImode, op1);
12452 emit_insn (gen_avx_movdqu (op0, op1));
12455 op0 = gen_lowpart (V32QImode, op0);
12456 op1 = gen_lowpart (V32QImode, op1);
12457 emit_insn (gen_avx_movdqu256 (op0, op1));
12460 gcc_unreachable ();
12463 case MODE_VECTOR_FLOAT:
12464 op0 = gen_lowpart (mode, op0);
12465 op1 = gen_lowpart (mode, op1);
12470 emit_insn (gen_avx_movups (op0, op1));
12473 emit_insn (gen_avx_movups256 (op0, op1));
12476 emit_insn (gen_avx_movupd (op0, op1));
12479 emit_insn (gen_avx_movupd256 (op0, op1));
12482 gcc_unreachable ();
12487 gcc_unreachable ();
12495 /* If we're optimizing for size, movups is the smallest. */
12496 if (optimize_insn_for_size_p ())
12498 op0 = gen_lowpart (V4SFmode, op0);
12499 op1 = gen_lowpart (V4SFmode, op1);
12500 emit_insn (gen_sse_movups (op0, op1));
12504 /* ??? If we have typed data, then it would appear that using
12505 movdqu is the only way to get unaligned data loaded with
12507 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12509 op0 = gen_lowpart (V16QImode, op0);
12510 op1 = gen_lowpart (V16QImode, op1);
12511 emit_insn (gen_sse2_movdqu (op0, op1));
12515 if (TARGET_SSE2 && mode == V2DFmode)
12519 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12521 op0 = gen_lowpart (V2DFmode, op0);
12522 op1 = gen_lowpart (V2DFmode, op1);
12523 emit_insn (gen_sse2_movupd (op0, op1));
12527 /* When SSE registers are split into halves, we can avoid
12528 writing to the top half twice. */
12529 if (TARGET_SSE_SPLIT_REGS)
12531 emit_clobber (op0);
12536 /* ??? Not sure about the best option for the Intel chips.
12537 The following would seem to satisfy; the register is
12538 entirely cleared, breaking the dependency chain. We
12539 then store to the upper half, with a dependency depth
12540 of one. A rumor has it that Intel recommends two movsd
12541 followed by an unpacklpd, but this is unconfirmed. And
12542 given that the dependency depth of the unpacklpd would
12543 still be one, I'm not sure why this would be better. */
12544 zero = CONST0_RTX (V2DFmode);
12547 m = adjust_address (op1, DFmode, 0);
12548 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12549 m = adjust_address (op1, DFmode, 8);
12550 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12554 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12556 op0 = gen_lowpart (V4SFmode, op0);
12557 op1 = gen_lowpart (V4SFmode, op1);
12558 emit_insn (gen_sse_movups (op0, op1));
12562 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12563 emit_move_insn (op0, CONST0_RTX (mode));
12565 emit_clobber (op0);
12567 if (mode != V4SFmode)
12568 op0 = gen_lowpart (V4SFmode, op0);
12569 m = adjust_address (op1, V2SFmode, 0);
12570 emit_insn (gen_sse_loadlps (op0, op0, m));
12571 m = adjust_address (op1, V2SFmode, 8);
12572 emit_insn (gen_sse_loadhps (op0, op0, m));
12575 else if (MEM_P (op0))
12577 /* If we're optimizing for size, movups is the smallest. */
12578 if (optimize_insn_for_size_p ())
12580 op0 = gen_lowpart (V4SFmode, op0);
12581 op1 = gen_lowpart (V4SFmode, op1);
12582 emit_insn (gen_sse_movups (op0, op1));
12586 /* ??? Similar to above, only less clear because of quote
12587 typeless stores unquote. */
12588 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12589 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12591 op0 = gen_lowpart (V16QImode, op0);
12592 op1 = gen_lowpart (V16QImode, op1);
12593 emit_insn (gen_sse2_movdqu (op0, op1));
12597 if (TARGET_SSE2 && mode == V2DFmode)
12599 m = adjust_address (op0, DFmode, 0);
12600 emit_insn (gen_sse2_storelpd (m, op1));
12601 m = adjust_address (op0, DFmode, 8);
12602 emit_insn (gen_sse2_storehpd (m, op1));
12606 if (mode != V4SFmode)
12607 op1 = gen_lowpart (V4SFmode, op1);
12608 m = adjust_address (op0, V2SFmode, 0);
12609 emit_insn (gen_sse_storelps (m, op1));
12610 m = adjust_address (op0, V2SFmode, 8);
12611 emit_insn (gen_sse_storehps (m, op1));
12615 gcc_unreachable ();
12618 /* Expand a push in MODE. This is some mode for which we do not support
12619 proper push instructions, at least from the registers that we expect
12620 the value to live in. */
12623 ix86_expand_push (enum machine_mode mode, rtx x)
12627 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12628 GEN_INT (-GET_MODE_SIZE (mode)),
12629 stack_pointer_rtx, 1, OPTAB_DIRECT);
12630 if (tmp != stack_pointer_rtx)
12631 emit_move_insn (stack_pointer_rtx, tmp);
12633 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12635 /* When we push an operand onto stack, it has to be aligned at least
12636 at the function argument boundary. However since we don't have
12637 the argument type, we can't determine the actual argument
12639 emit_move_insn (tmp, x);
12642 /* Helper function of ix86_fixup_binary_operands to canonicalize
12643 operand order. Returns true if the operands should be swapped. */
12646 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12649 rtx dst = operands[0];
12650 rtx src1 = operands[1];
12651 rtx src2 = operands[2];
12653 /* If the operation is not commutative, we can't do anything. */
12654 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12657 /* Highest priority is that src1 should match dst. */
12658 if (rtx_equal_p (dst, src1))
12660 if (rtx_equal_p (dst, src2))
12663 /* Next highest priority is that immediate constants come second. */
12664 if (immediate_operand (src2, mode))
12666 if (immediate_operand (src1, mode))
12669 /* Lowest priority is that memory references should come second. */
12679 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12680 destination to use for the operation. If different from the true
12681 destination in operands[0], a copy operation will be required. */
12684 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12687 rtx dst = operands[0];
12688 rtx src1 = operands[1];
12689 rtx src2 = operands[2];
12691 /* Canonicalize operand order. */
12692 if (ix86_swap_binary_operands_p (code, mode, operands))
12696 /* It is invalid to swap operands of different modes. */
12697 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12704 /* Both source operands cannot be in memory. */
12705 if (MEM_P (src1) && MEM_P (src2))
12707 /* Optimization: Only read from memory once. */
12708 if (rtx_equal_p (src1, src2))
12710 src2 = force_reg (mode, src2);
12714 src2 = force_reg (mode, src2);
12717 /* If the destination is memory, and we do not have matching source
12718 operands, do things in registers. */
12719 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12720 dst = gen_reg_rtx (mode);
12722 /* Source 1 cannot be a constant. */
12723 if (CONSTANT_P (src1))
12724 src1 = force_reg (mode, src1);
12726 /* Source 1 cannot be a non-matching memory. */
12727 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12728 src1 = force_reg (mode, src1);
12730 operands[1] = src1;
12731 operands[2] = src2;
12735 /* Similarly, but assume that the destination has already been
12736 set up properly. */
12739 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12740 enum machine_mode mode, rtx operands[])
12742 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12743 gcc_assert (dst == operands[0]);
12746 /* Attempt to expand a binary operator. Make the expansion closer to the
12747 actual machine, then just general_operand, which will allow 3 separate
12748 memory references (one output, two input) in a single insn. */
12751 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12754 rtx src1, src2, dst, op, clob;
12756 dst = ix86_fixup_binary_operands (code, mode, operands);
12757 src1 = operands[1];
12758 src2 = operands[2];
12760 /* Emit the instruction. */
12762 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12763 if (reload_in_progress)
12765 /* Reload doesn't know about the flags register, and doesn't know that
12766 it doesn't want to clobber it. We can only do this with PLUS. */
12767 gcc_assert (code == PLUS);
12772 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12773 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12776 /* Fix up the destination if needed. */
12777 if (dst != operands[0])
12778 emit_move_insn (operands[0], dst);
12781 /* Return TRUE or FALSE depending on whether the binary operator meets the
12782 appropriate constraints. */
12785 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12788 rtx dst = operands[0];
12789 rtx src1 = operands[1];
12790 rtx src2 = operands[2];
12792 /* Both source operands cannot be in memory. */
12793 if (MEM_P (src1) && MEM_P (src2))
12796 /* Canonicalize operand order for commutative operators. */
12797 if (ix86_swap_binary_operands_p (code, mode, operands))
12804 /* If the destination is memory, we must have a matching source operand. */
12805 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12808 /* Source 1 cannot be a constant. */
12809 if (CONSTANT_P (src1))
12812 /* Source 1 cannot be a non-matching memory. */
12813 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12819 /* Attempt to expand a unary operator. Make the expansion closer to the
12820 actual machine, then just general_operand, which will allow 2 separate
12821 memory references (one output, one input) in a single insn. */
12824 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12827 int matching_memory;
12828 rtx src, dst, op, clob;
12833 /* If the destination is memory, and we do not have matching source
12834 operands, do things in registers. */
12835 matching_memory = 0;
12838 if (rtx_equal_p (dst, src))
12839 matching_memory = 1;
12841 dst = gen_reg_rtx (mode);
12844 /* When source operand is memory, destination must match. */
12845 if (MEM_P (src) && !matching_memory)
12846 src = force_reg (mode, src);
12848 /* Emit the instruction. */
12850 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12851 if (reload_in_progress || code == NOT)
12853 /* Reload doesn't know about the flags register, and doesn't know that
12854 it doesn't want to clobber it. */
12855 gcc_assert (code == NOT);
12860 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12861 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12864 /* Fix up the destination if needed. */
12865 if (dst != operands[0])
12866 emit_move_insn (operands[0], dst);
12869 /* Return TRUE or FALSE depending on whether the unary operator meets the
12870 appropriate constraints. */
12873 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12874 enum machine_mode mode ATTRIBUTE_UNUSED,
12875 rtx operands[2] ATTRIBUTE_UNUSED)
12877 /* If one of operands is memory, source and destination must match. */
12878 if ((MEM_P (operands[0])
12879 || MEM_P (operands[1]))
12880 && ! rtx_equal_p (operands[0], operands[1]))
12885 /* Post-reload splitter for converting an SF or DFmode value in an
12886 SSE register into an unsigned SImode. */
12889 ix86_split_convert_uns_si_sse (rtx operands[])
12891 enum machine_mode vecmode;
12892 rtx value, large, zero_or_two31, input, two31, x;
12894 large = operands[1];
12895 zero_or_two31 = operands[2];
12896 input = operands[3];
12897 two31 = operands[4];
12898 vecmode = GET_MODE (large);
12899 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12901 /* Load up the value into the low element. We must ensure that the other
12902 elements are valid floats -- zero is the easiest such value. */
12905 if (vecmode == V4SFmode)
12906 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12908 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12912 input = gen_rtx_REG (vecmode, REGNO (input));
12913 emit_move_insn (value, CONST0_RTX (vecmode));
12914 if (vecmode == V4SFmode)
12915 emit_insn (gen_sse_movss (value, value, input));
12917 emit_insn (gen_sse2_movsd (value, value, input));
12920 emit_move_insn (large, two31);
12921 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12923 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12924 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12926 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12927 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12929 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12930 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12932 large = gen_rtx_REG (V4SImode, REGNO (large));
12933 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12935 x = gen_rtx_REG (V4SImode, REGNO (value));
12936 if (vecmode == V4SFmode)
12937 emit_insn (gen_sse2_cvttps2dq (x, value));
12939 emit_insn (gen_sse2_cvttpd2dq (x, value));
12942 emit_insn (gen_xorv4si3 (value, value, large));
12945 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12946 Expects the 64-bit DImode to be supplied in a pair of integral
12947 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12948 -mfpmath=sse, !optimize_size only. */
12951 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12953 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12954 rtx int_xmm, fp_xmm;
12955 rtx biases, exponents;
12958 int_xmm = gen_reg_rtx (V4SImode);
12959 if (TARGET_INTER_UNIT_MOVES)
12960 emit_insn (gen_movdi_to_sse (int_xmm, input));
12961 else if (TARGET_SSE_SPLIT_REGS)
12963 emit_clobber (int_xmm);
12964 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12968 x = gen_reg_rtx (V2DImode);
12969 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12970 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12973 x = gen_rtx_CONST_VECTOR (V4SImode,
12974 gen_rtvec (4, GEN_INT (0x43300000UL),
12975 GEN_INT (0x45300000UL),
12976 const0_rtx, const0_rtx));
12977 exponents = validize_mem (force_const_mem (V4SImode, x));
12979 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12980 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
12982 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12983 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12984 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12985 (0x1.0p84 + double(fp_value_hi_xmm)).
12986 Note these exponents differ by 32. */
12988 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
12990 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12991 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12992 real_ldexp (&bias_lo_rvt, &dconst1, 52);
12993 real_ldexp (&bias_hi_rvt, &dconst1, 84);
12994 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
12995 x = const_double_from_real_value (bias_hi_rvt, DFmode);
12996 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
12997 biases = validize_mem (force_const_mem (V2DFmode, biases));
12998 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13000 /* Add the upper and lower DFmode values together. */
13002 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13005 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13006 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13007 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13010 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13013 /* Not used, but eases macroization of patterns. */
13015 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13016 rtx input ATTRIBUTE_UNUSED)
13018 gcc_unreachable ();
13021 /* Convert an unsigned SImode value into a DFmode. Only currently used
13022 for SSE, but applicable anywhere. */
13025 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13027 REAL_VALUE_TYPE TWO31r;
13030 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13031 NULL, 1, OPTAB_DIRECT);
13033 fp = gen_reg_rtx (DFmode);
13034 emit_insn (gen_floatsidf2 (fp, x));
13036 real_ldexp (&TWO31r, &dconst1, 31);
13037 x = const_double_from_real_value (TWO31r, DFmode);
13039 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13041 emit_move_insn (target, x);
13044 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13045 32-bit mode; otherwise we have a direct convert instruction. */
13048 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13050 REAL_VALUE_TYPE TWO32r;
13051 rtx fp_lo, fp_hi, x;
13053 fp_lo = gen_reg_rtx (DFmode);
13054 fp_hi = gen_reg_rtx (DFmode);
13056 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13058 real_ldexp (&TWO32r, &dconst1, 32);
13059 x = const_double_from_real_value (TWO32r, DFmode);
13060 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13062 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13064 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13067 emit_move_insn (target, x);
13070 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13071 For x86_32, -mfpmath=sse, !optimize_size only. */
13073 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13075 REAL_VALUE_TYPE ONE16r;
13076 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13078 real_ldexp (&ONE16r, &dconst1, 16);
13079 x = const_double_from_real_value (ONE16r, SFmode);
13080 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13081 NULL, 0, OPTAB_DIRECT);
13082 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13083 NULL, 0, OPTAB_DIRECT);
13084 fp_hi = gen_reg_rtx (SFmode);
13085 fp_lo = gen_reg_rtx (SFmode);
13086 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13087 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13088 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13090 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13092 if (!rtx_equal_p (target, fp_hi))
13093 emit_move_insn (target, fp_hi);
13096 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13097 then replicate the value for all elements of the vector
13101 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13108 v = gen_rtvec (4, value, value, value, value);
13109 return gen_rtx_CONST_VECTOR (V4SImode, v);
13113 v = gen_rtvec (2, value, value);
13114 return gen_rtx_CONST_VECTOR (V2DImode, v);
13118 v = gen_rtvec (4, value, value, value, value);
13120 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13121 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13122 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13126 v = gen_rtvec (2, value, value);
13128 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13129 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13132 gcc_unreachable ();
13136 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13137 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13138 for an SSE register. If VECT is true, then replicate the mask for
13139 all elements of the vector register. If INVERT is true, then create
13140 a mask excluding the sign bit. */
13143 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13145 enum machine_mode vec_mode, imode;
13146 HOST_WIDE_INT hi, lo;
13151 /* Find the sign bit, sign extended to 2*HWI. */
13157 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13158 lo = 0x80000000, hi = lo < 0;
13164 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13165 if (HOST_BITS_PER_WIDE_INT >= 64)
13166 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13168 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13173 vec_mode = VOIDmode;
13174 if (HOST_BITS_PER_WIDE_INT >= 64)
13177 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13184 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13188 lo = ~lo, hi = ~hi;
13194 mask = immed_double_const (lo, hi, imode);
13196 vec = gen_rtvec (2, v, mask);
13197 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13198 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13205 gcc_unreachable ();
13209 lo = ~lo, hi = ~hi;
13211 /* Force this value into the low part of a fp vector constant. */
13212 mask = immed_double_const (lo, hi, imode);
13213 mask = gen_lowpart (mode, mask);
13215 if (vec_mode == VOIDmode)
13216 return force_reg (mode, mask);
13218 v = ix86_build_const_vector (mode, vect, mask);
13219 return force_reg (vec_mode, v);
13222 /* Generate code for floating point ABS or NEG. */
13225 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13228 rtx mask, set, use, clob, dst, src;
13229 bool use_sse = false;
13230 bool vector_mode = VECTOR_MODE_P (mode);
13231 enum machine_mode elt_mode = mode;
13235 elt_mode = GET_MODE_INNER (mode);
13238 else if (mode == TFmode)
13240 else if (TARGET_SSE_MATH)
13241 use_sse = SSE_FLOAT_MODE_P (mode);
13243 /* NEG and ABS performed with SSE use bitwise mask operations.
13244 Create the appropriate mask now. */
13246 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13255 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13256 set = gen_rtx_SET (VOIDmode, dst, set);
13261 set = gen_rtx_fmt_e (code, mode, src);
13262 set = gen_rtx_SET (VOIDmode, dst, set);
13265 use = gen_rtx_USE (VOIDmode, mask);
13266 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13267 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13268 gen_rtvec (3, set, use, clob)));
13275 /* Expand a copysign operation. Special case operand 0 being a constant. */
13278 ix86_expand_copysign (rtx operands[])
13280 enum machine_mode mode;
13281 rtx dest, op0, op1, mask, nmask;
13283 dest = operands[0];
13287 mode = GET_MODE (dest);
13289 if (GET_CODE (op0) == CONST_DOUBLE)
13291 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13293 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13294 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13296 if (mode == SFmode || mode == DFmode)
13298 enum machine_mode vmode;
13300 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13302 if (op0 == CONST0_RTX (mode))
13303 op0 = CONST0_RTX (vmode);
13308 if (mode == SFmode)
13309 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13310 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13312 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13314 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13317 else if (op0 != CONST0_RTX (mode))
13318 op0 = force_reg (mode, op0);
13320 mask = ix86_build_signbit_mask (mode, 0, 0);
13322 if (mode == SFmode)
13323 copysign_insn = gen_copysignsf3_const;
13324 else if (mode == DFmode)
13325 copysign_insn = gen_copysigndf3_const;
13327 copysign_insn = gen_copysigntf3_const;
13329 emit_insn (copysign_insn (dest, op0, op1, mask));
13333 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13335 nmask = ix86_build_signbit_mask (mode, 0, 1);
13336 mask = ix86_build_signbit_mask (mode, 0, 0);
13338 if (mode == SFmode)
13339 copysign_insn = gen_copysignsf3_var;
13340 else if (mode == DFmode)
13341 copysign_insn = gen_copysigndf3_var;
13343 copysign_insn = gen_copysigntf3_var;
13345 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13349 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13350 be a constant, and so has already been expanded into a vector constant. */
13353 ix86_split_copysign_const (rtx operands[])
13355 enum machine_mode mode, vmode;
13356 rtx dest, op0, op1, mask, x;
13358 dest = operands[0];
13361 mask = operands[3];
13363 mode = GET_MODE (dest);
13364 vmode = GET_MODE (mask);
13366 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13367 x = gen_rtx_AND (vmode, dest, mask);
13368 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13370 if (op0 != CONST0_RTX (vmode))
13372 x = gen_rtx_IOR (vmode, dest, op0);
13373 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13377 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13378 so we have to do two masks. */
13381 ix86_split_copysign_var (rtx operands[])
13383 enum machine_mode mode, vmode;
13384 rtx dest, scratch, op0, op1, mask, nmask, x;
13386 dest = operands[0];
13387 scratch = operands[1];
13390 nmask = operands[4];
13391 mask = operands[5];
13393 mode = GET_MODE (dest);
13394 vmode = GET_MODE (mask);
13396 if (rtx_equal_p (op0, op1))
13398 /* Shouldn't happen often (it's useless, obviously), but when it does
13399 we'd generate incorrect code if we continue below. */
13400 emit_move_insn (dest, op0);
13404 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13406 gcc_assert (REGNO (op1) == REGNO (scratch));
13408 x = gen_rtx_AND (vmode, scratch, mask);
13409 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13412 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13413 x = gen_rtx_NOT (vmode, dest);
13414 x = gen_rtx_AND (vmode, x, op0);
13415 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13419 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13421 x = gen_rtx_AND (vmode, scratch, mask);
13423 else /* alternative 2,4 */
13425 gcc_assert (REGNO (mask) == REGNO (scratch));
13426 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13427 x = gen_rtx_AND (vmode, scratch, op1);
13429 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13431 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13433 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13434 x = gen_rtx_AND (vmode, dest, nmask);
13436 else /* alternative 3,4 */
13438 gcc_assert (REGNO (nmask) == REGNO (dest));
13440 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13441 x = gen_rtx_AND (vmode, dest, op0);
13443 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13446 x = gen_rtx_IOR (vmode, dest, scratch);
13447 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13450 /* Return TRUE or FALSE depending on whether the first SET in INSN
13451 has source and destination with matching CC modes, and that the
13452 CC mode is at least as constrained as REQ_MODE. */
13455 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13458 enum machine_mode set_mode;
13460 set = PATTERN (insn);
13461 if (GET_CODE (set) == PARALLEL)
13462 set = XVECEXP (set, 0, 0);
13463 gcc_assert (GET_CODE (set) == SET);
13464 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13466 set_mode = GET_MODE (SET_DEST (set));
13470 if (req_mode != CCNOmode
13471 && (req_mode != CCmode
13472 || XEXP (SET_SRC (set), 1) != const0_rtx))
13476 if (req_mode == CCGCmode)
13480 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13484 if (req_mode == CCZmode)
13495 gcc_unreachable ();
13498 return (GET_MODE (SET_SRC (set)) == set_mode);
13501 /* Generate insn patterns to do an integer compare of OPERANDS. */
13504 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13506 enum machine_mode cmpmode;
13509 cmpmode = SELECT_CC_MODE (code, op0, op1);
13510 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13512 /* This is very simple, but making the interface the same as in the
13513 FP case makes the rest of the code easier. */
13514 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13515 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13517 /* Return the test that should be put into the flags user, i.e.
13518 the bcc, scc, or cmov instruction. */
13519 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13522 /* Figure out whether to use ordered or unordered fp comparisons.
13523 Return the appropriate mode to use. */
13526 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13528 /* ??? In order to make all comparisons reversible, we do all comparisons
13529 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13530 all forms trapping and nontrapping comparisons, we can make inequality
13531 comparisons trapping again, since it results in better code when using
13532 FCOM based compares. */
13533 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13537 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13539 enum machine_mode mode = GET_MODE (op0);
13541 if (SCALAR_FLOAT_MODE_P (mode))
13543 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13544 return ix86_fp_compare_mode (code);
13549 /* Only zero flag is needed. */
13550 case EQ: /* ZF=0 */
13551 case NE: /* ZF!=0 */
13553 /* Codes needing carry flag. */
13554 case GEU: /* CF=0 */
13555 case LTU: /* CF=1 */
13556 /* Detect overflow checks. They need just the carry flag. */
13557 if (GET_CODE (op0) == PLUS
13558 && rtx_equal_p (op1, XEXP (op0, 0)))
13562 case GTU: /* CF=0 & ZF=0 */
13563 case LEU: /* CF=1 | ZF=1 */
13564 /* Detect overflow checks. They need just the carry flag. */
13565 if (GET_CODE (op0) == MINUS
13566 && rtx_equal_p (op1, XEXP (op0, 0)))
13570 /* Codes possibly doable only with sign flag when
13571 comparing against zero. */
13572 case GE: /* SF=OF or SF=0 */
13573 case LT: /* SF<>OF or SF=1 */
13574 if (op1 == const0_rtx)
13577 /* For other cases Carry flag is not required. */
13579 /* Codes doable only with sign flag when comparing
13580 against zero, but we miss jump instruction for it
13581 so we need to use relational tests against overflow
13582 that thus needs to be zero. */
13583 case GT: /* ZF=0 & SF=OF */
13584 case LE: /* ZF=1 | SF<>OF */
13585 if (op1 == const0_rtx)
13589 /* strcmp pattern do (use flags) and combine may ask us for proper
13594 gcc_unreachable ();
13598 /* Return the fixed registers used for condition codes. */
13601 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13608 /* If two condition code modes are compatible, return a condition code
13609 mode which is compatible with both. Otherwise, return
13612 static enum machine_mode
13613 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13618 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13621 if ((m1 == CCGCmode && m2 == CCGOCmode)
13622 || (m1 == CCGOCmode && m2 == CCGCmode))
13628 gcc_unreachable ();
13658 /* These are only compatible with themselves, which we already
13664 /* Split comparison code CODE into comparisons we can do using branch
13665 instructions. BYPASS_CODE is comparison code for branch that will
13666 branch around FIRST_CODE and SECOND_CODE. If some of branches
13667 is not required, set value to UNKNOWN.
13668 We never require more than two branches. */
13671 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13672 enum rtx_code *first_code,
13673 enum rtx_code *second_code)
13675 *first_code = code;
13676 *bypass_code = UNKNOWN;
13677 *second_code = UNKNOWN;
13679 /* The fcomi comparison sets flags as follows:
13689 case GT: /* GTU - CF=0 & ZF=0 */
13690 case GE: /* GEU - CF=0 */
13691 case ORDERED: /* PF=0 */
13692 case UNORDERED: /* PF=1 */
13693 case UNEQ: /* EQ - ZF=1 */
13694 case UNLT: /* LTU - CF=1 */
13695 case UNLE: /* LEU - CF=1 | ZF=1 */
13696 case LTGT: /* EQ - ZF=0 */
13698 case LT: /* LTU - CF=1 - fails on unordered */
13699 *first_code = UNLT;
13700 *bypass_code = UNORDERED;
13702 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13703 *first_code = UNLE;
13704 *bypass_code = UNORDERED;
13706 case EQ: /* EQ - ZF=1 - fails on unordered */
13707 *first_code = UNEQ;
13708 *bypass_code = UNORDERED;
13710 case NE: /* NE - ZF=0 - fails on unordered */
13711 *first_code = LTGT;
13712 *second_code = UNORDERED;
13714 case UNGE: /* GEU - CF=0 - fails on unordered */
13716 *second_code = UNORDERED;
13718 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13720 *second_code = UNORDERED;
13723 gcc_unreachable ();
13725 if (!TARGET_IEEE_FP)
13727 *second_code = UNKNOWN;
13728 *bypass_code = UNKNOWN;
13732 /* Return cost of comparison done fcom + arithmetics operations on AX.
13733 All following functions do use number of instructions as a cost metrics.
13734 In future this should be tweaked to compute bytes for optimize_size and
13735 take into account performance of various instructions on various CPUs. */
13737 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13739 if (!TARGET_IEEE_FP)
13741 /* The cost of code output by ix86_expand_fp_compare. */
13765 gcc_unreachable ();
13769 /* Return cost of comparison done using fcomi operation.
13770 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13772 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13774 enum rtx_code bypass_code, first_code, second_code;
13775 /* Return arbitrarily high cost when instruction is not supported - this
13776 prevents gcc from using it. */
13779 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13780 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13783 /* Return cost of comparison done using sahf operation.
13784 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13786 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13788 enum rtx_code bypass_code, first_code, second_code;
13789 /* Return arbitrarily high cost when instruction is not preferred - this
13790 avoids gcc from using it. */
13791 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13793 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13794 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13797 /* Compute cost of the comparison done using any method.
13798 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13800 ix86_fp_comparison_cost (enum rtx_code code)
13802 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13805 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13806 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13808 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13809 if (min > sahf_cost)
13811 if (min > fcomi_cost)
13816 /* Return true if we should use an FCOMI instruction for this
13820 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13822 enum rtx_code swapped_code = swap_condition (code);
13824 return ((ix86_fp_comparison_cost (code)
13825 == ix86_fp_comparison_fcomi_cost (code))
13826 || (ix86_fp_comparison_cost (swapped_code)
13827 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13830 /* Swap, force into registers, or otherwise massage the two operands
13831 to a fp comparison. The operands are updated in place; the new
13832 comparison code is returned. */
13834 static enum rtx_code
13835 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13837 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13838 rtx op0 = *pop0, op1 = *pop1;
13839 enum machine_mode op_mode = GET_MODE (op0);
13840 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13842 /* All of the unordered compare instructions only work on registers.
13843 The same is true of the fcomi compare instructions. The XFmode
13844 compare instructions require registers except when comparing
13845 against zero or when converting operand 1 from fixed point to
13849 && (fpcmp_mode == CCFPUmode
13850 || (op_mode == XFmode
13851 && ! (standard_80387_constant_p (op0) == 1
13852 || standard_80387_constant_p (op1) == 1)
13853 && GET_CODE (op1) != FLOAT)
13854 || ix86_use_fcomi_compare (code)))
13856 op0 = force_reg (op_mode, op0);
13857 op1 = force_reg (op_mode, op1);
13861 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13862 things around if they appear profitable, otherwise force op0
13863 into a register. */
13865 if (standard_80387_constant_p (op0) == 0
13867 && ! (standard_80387_constant_p (op1) == 0
13871 tmp = op0, op0 = op1, op1 = tmp;
13872 code = swap_condition (code);
13876 op0 = force_reg (op_mode, op0);
13878 if (CONSTANT_P (op1))
13880 int tmp = standard_80387_constant_p (op1);
13882 op1 = validize_mem (force_const_mem (op_mode, op1));
13886 op1 = force_reg (op_mode, op1);
13889 op1 = force_reg (op_mode, op1);
13893 /* Try to rearrange the comparison to make it cheaper. */
13894 if (ix86_fp_comparison_cost (code)
13895 > ix86_fp_comparison_cost (swap_condition (code))
13896 && (REG_P (op1) || can_create_pseudo_p ()))
13899 tmp = op0, op0 = op1, op1 = tmp;
13900 code = swap_condition (code);
13902 op0 = force_reg (op_mode, op0);
13910 /* Convert comparison codes we use to represent FP comparison to integer
13911 code that will result in proper branch. Return UNKNOWN if no such code
13915 ix86_fp_compare_code_to_integer (enum rtx_code code)
13944 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13947 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13948 rtx *second_test, rtx *bypass_test)
13950 enum machine_mode fpcmp_mode, intcmp_mode;
13952 int cost = ix86_fp_comparison_cost (code);
13953 enum rtx_code bypass_code, first_code, second_code;
13955 fpcmp_mode = ix86_fp_compare_mode (code);
13956 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13959 *second_test = NULL_RTX;
13961 *bypass_test = NULL_RTX;
13963 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13965 /* Do fcomi/sahf based test when profitable. */
13966 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13967 && (bypass_code == UNKNOWN || bypass_test)
13968 && (second_code == UNKNOWN || second_test))
13970 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13971 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13977 gcc_assert (TARGET_SAHF);
13980 scratch = gen_reg_rtx (HImode);
13981 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
13983 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
13986 /* The FP codes work out to act like unsigned. */
13987 intcmp_mode = fpcmp_mode;
13989 if (bypass_code != UNKNOWN)
13990 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
13991 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13993 if (second_code != UNKNOWN)
13994 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
13995 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14000 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14001 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14002 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14004 scratch = gen_reg_rtx (HImode);
14005 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14007 /* In the unordered case, we have to check C2 for NaN's, which
14008 doesn't happen to work out to anything nice combination-wise.
14009 So do some bit twiddling on the value we've got in AH to come
14010 up with an appropriate set of condition codes. */
14012 intcmp_mode = CCNOmode;
14017 if (code == GT || !TARGET_IEEE_FP)
14019 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14024 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14025 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14026 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14027 intcmp_mode = CCmode;
14033 if (code == LT && TARGET_IEEE_FP)
14035 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14036 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14037 intcmp_mode = CCmode;
14042 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14048 if (code == GE || !TARGET_IEEE_FP)
14050 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14055 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14056 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14063 if (code == LE && TARGET_IEEE_FP)
14065 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14066 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14067 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14068 intcmp_mode = CCmode;
14073 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14079 if (code == EQ && TARGET_IEEE_FP)
14081 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14082 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14083 intcmp_mode = CCmode;
14088 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14095 if (code == NE && TARGET_IEEE_FP)
14097 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14098 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14104 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14110 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14114 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14119 gcc_unreachable ();
14123 /* Return the test that should be put into the flags user, i.e.
14124 the bcc, scc, or cmov instruction. */
14125 return gen_rtx_fmt_ee (code, VOIDmode,
14126 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14131 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14134 op0 = ix86_compare_op0;
14135 op1 = ix86_compare_op1;
14138 *second_test = NULL_RTX;
14140 *bypass_test = NULL_RTX;
14142 if (ix86_compare_emitted)
14144 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14145 ix86_compare_emitted = NULL_RTX;
14147 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14149 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14150 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14151 second_test, bypass_test);
14154 ret = ix86_expand_int_compare (code, op0, op1);
14159 /* Return true if the CODE will result in nontrivial jump sequence. */
14161 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14163 enum rtx_code bypass_code, first_code, second_code;
14166 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14167 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14171 ix86_expand_branch (enum rtx_code code, rtx label)
14175 /* If we have emitted a compare insn, go straight to simple.
14176 ix86_expand_compare won't emit anything if ix86_compare_emitted
14178 if (ix86_compare_emitted)
14181 switch (GET_MODE (ix86_compare_op0))
14187 tmp = ix86_expand_compare (code, NULL, NULL);
14188 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14189 gen_rtx_LABEL_REF (VOIDmode, label),
14191 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14200 enum rtx_code bypass_code, first_code, second_code;
14202 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14203 &ix86_compare_op1);
14205 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14207 /* Check whether we will use the natural sequence with one jump. If
14208 so, we can expand jump early. Otherwise delay expansion by
14209 creating compound insn to not confuse optimizers. */
14210 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14212 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14213 gen_rtx_LABEL_REF (VOIDmode, label),
14214 pc_rtx, NULL_RTX, NULL_RTX);
14218 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14219 ix86_compare_op0, ix86_compare_op1);
14220 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14221 gen_rtx_LABEL_REF (VOIDmode, label),
14223 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14225 use_fcomi = ix86_use_fcomi_compare (code);
14226 vec = rtvec_alloc (3 + !use_fcomi);
14227 RTVEC_ELT (vec, 0) = tmp;
14229 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14231 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14234 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14236 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14245 /* Expand DImode branch into multiple compare+branch. */
14247 rtx lo[2], hi[2], label2;
14248 enum rtx_code code1, code2, code3;
14249 enum machine_mode submode;
14251 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14253 tmp = ix86_compare_op0;
14254 ix86_compare_op0 = ix86_compare_op1;
14255 ix86_compare_op1 = tmp;
14256 code = swap_condition (code);
14258 if (GET_MODE (ix86_compare_op0) == DImode)
14260 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14261 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14266 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14267 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14271 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14272 avoid two branches. This costs one extra insn, so disable when
14273 optimizing for size. */
14275 if ((code == EQ || code == NE)
14276 && (!optimize_insn_for_size_p ()
14277 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14282 if (hi[1] != const0_rtx)
14283 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14284 NULL_RTX, 0, OPTAB_WIDEN);
14287 if (lo[1] != const0_rtx)
14288 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14289 NULL_RTX, 0, OPTAB_WIDEN);
14291 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14292 NULL_RTX, 0, OPTAB_WIDEN);
14294 ix86_compare_op0 = tmp;
14295 ix86_compare_op1 = const0_rtx;
14296 ix86_expand_branch (code, label);
14300 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14301 op1 is a constant and the low word is zero, then we can just
14302 examine the high word. Similarly for low word -1 and
14303 less-or-equal-than or greater-than. */
14305 if (CONST_INT_P (hi[1]))
14308 case LT: case LTU: case GE: case GEU:
14309 if (lo[1] == const0_rtx)
14311 ix86_compare_op0 = hi[0];
14312 ix86_compare_op1 = hi[1];
14313 ix86_expand_branch (code, label);
14317 case LE: case LEU: case GT: case GTU:
14318 if (lo[1] == constm1_rtx)
14320 ix86_compare_op0 = hi[0];
14321 ix86_compare_op1 = hi[1];
14322 ix86_expand_branch (code, label);
14330 /* Otherwise, we need two or three jumps. */
14332 label2 = gen_label_rtx ();
14335 code2 = swap_condition (code);
14336 code3 = unsigned_condition (code);
14340 case LT: case GT: case LTU: case GTU:
14343 case LE: code1 = LT; code2 = GT; break;
14344 case GE: code1 = GT; code2 = LT; break;
14345 case LEU: code1 = LTU; code2 = GTU; break;
14346 case GEU: code1 = GTU; code2 = LTU; break;
14348 case EQ: code1 = UNKNOWN; code2 = NE; break;
14349 case NE: code2 = UNKNOWN; break;
14352 gcc_unreachable ();
14357 * if (hi(a) < hi(b)) goto true;
14358 * if (hi(a) > hi(b)) goto false;
14359 * if (lo(a) < lo(b)) goto true;
14363 ix86_compare_op0 = hi[0];
14364 ix86_compare_op1 = hi[1];
14366 if (code1 != UNKNOWN)
14367 ix86_expand_branch (code1, label);
14368 if (code2 != UNKNOWN)
14369 ix86_expand_branch (code2, label2);
14371 ix86_compare_op0 = lo[0];
14372 ix86_compare_op1 = lo[1];
14373 ix86_expand_branch (code3, label);
14375 if (code2 != UNKNOWN)
14376 emit_label (label2);
14381 gcc_unreachable ();
14385 /* Split branch based on floating point condition. */
14387 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14388 rtx target1, rtx target2, rtx tmp, rtx pushed)
14390 rtx second, bypass;
14391 rtx label = NULL_RTX;
14393 int bypass_probability = -1, second_probability = -1, probability = -1;
14396 if (target2 != pc_rtx)
14399 code = reverse_condition_maybe_unordered (code);
14404 condition = ix86_expand_fp_compare (code, op1, op2,
14405 tmp, &second, &bypass);
14407 /* Remove pushed operand from stack. */
14409 ix86_free_from_memory (GET_MODE (pushed));
14411 if (split_branch_probability >= 0)
14413 /* Distribute the probabilities across the jumps.
14414 Assume the BYPASS and SECOND to be always test
14416 probability = split_branch_probability;
14418 /* Value of 1 is low enough to make no need for probability
14419 to be updated. Later we may run some experiments and see
14420 if unordered values are more frequent in practice. */
14422 bypass_probability = 1;
14424 second_probability = 1;
14426 if (bypass != NULL_RTX)
14428 label = gen_label_rtx ();
14429 i = emit_jump_insn (gen_rtx_SET
14431 gen_rtx_IF_THEN_ELSE (VOIDmode,
14433 gen_rtx_LABEL_REF (VOIDmode,
14436 if (bypass_probability >= 0)
14438 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14439 GEN_INT (bypass_probability),
14442 i = emit_jump_insn (gen_rtx_SET
14444 gen_rtx_IF_THEN_ELSE (VOIDmode,
14445 condition, target1, target2)));
14446 if (probability >= 0)
14448 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14449 GEN_INT (probability),
14451 if (second != NULL_RTX)
14453 i = emit_jump_insn (gen_rtx_SET
14455 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14457 if (second_probability >= 0)
14459 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14460 GEN_INT (second_probability),
14463 if (label != NULL_RTX)
14464 emit_label (label);
14468 ix86_expand_setcc (enum rtx_code code, rtx dest)
14470 rtx ret, tmp, tmpreg, equiv;
14471 rtx second_test, bypass_test;
14473 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14474 return 0; /* FAIL */
14476 gcc_assert (GET_MODE (dest) == QImode);
14478 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14479 PUT_MODE (ret, QImode);
14484 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14485 if (bypass_test || second_test)
14487 rtx test = second_test;
14489 rtx tmp2 = gen_reg_rtx (QImode);
14492 gcc_assert (!second_test);
14493 test = bypass_test;
14495 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14497 PUT_MODE (test, QImode);
14498 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14501 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14503 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14506 /* Attach a REG_EQUAL note describing the comparison result. */
14507 if (ix86_compare_op0 && ix86_compare_op1)
14509 equiv = simplify_gen_relational (code, QImode,
14510 GET_MODE (ix86_compare_op0),
14511 ix86_compare_op0, ix86_compare_op1);
14512 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14515 return 1; /* DONE */
14518 /* Expand comparison setting or clearing carry flag. Return true when
14519 successful and set pop for the operation. */
14521 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14523 enum machine_mode mode =
14524 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14526 /* Do not handle DImode compares that go through special path. */
14527 if (mode == (TARGET_64BIT ? TImode : DImode))
14530 if (SCALAR_FLOAT_MODE_P (mode))
14532 rtx second_test = NULL, bypass_test = NULL;
14533 rtx compare_op, compare_seq;
14535 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14537 /* Shortcut: following common codes never translate
14538 into carry flag compares. */
14539 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14540 || code == ORDERED || code == UNORDERED)
14543 /* These comparisons require zero flag; swap operands so they won't. */
14544 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14545 && !TARGET_IEEE_FP)
14550 code = swap_condition (code);
14553 /* Try to expand the comparison and verify that we end up with
14554 carry flag based comparison. This fails to be true only when
14555 we decide to expand comparison using arithmetic that is not
14556 too common scenario. */
14558 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14559 &second_test, &bypass_test);
14560 compare_seq = get_insns ();
14563 if (second_test || bypass_test)
14566 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14567 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14568 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14570 code = GET_CODE (compare_op);
14572 if (code != LTU && code != GEU)
14575 emit_insn (compare_seq);
14580 if (!INTEGRAL_MODE_P (mode))
14589 /* Convert a==0 into (unsigned)a<1. */
14592 if (op1 != const0_rtx)
14595 code = (code == EQ ? LTU : GEU);
14598 /* Convert a>b into b<a or a>=b-1. */
14601 if (CONST_INT_P (op1))
14603 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14604 /* Bail out on overflow. We still can swap operands but that
14605 would force loading of the constant into register. */
14606 if (op1 == const0_rtx
14607 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14609 code = (code == GTU ? GEU : LTU);
14616 code = (code == GTU ? LTU : GEU);
14620 /* Convert a>=0 into (unsigned)a<0x80000000. */
14623 if (mode == DImode || op1 != const0_rtx)
14625 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14626 code = (code == LT ? GEU : LTU);
14630 if (mode == DImode || op1 != constm1_rtx)
14632 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14633 code = (code == LE ? GEU : LTU);
14639 /* Swapping operands may cause constant to appear as first operand. */
14640 if (!nonimmediate_operand (op0, VOIDmode))
14642 if (!can_create_pseudo_p ())
14644 op0 = force_reg (mode, op0);
14646 ix86_compare_op0 = op0;
14647 ix86_compare_op1 = op1;
14648 *pop = ix86_expand_compare (code, NULL, NULL);
14649 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14654 ix86_expand_int_movcc (rtx operands[])
14656 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14657 rtx compare_seq, compare_op;
14658 rtx second_test, bypass_test;
14659 enum machine_mode mode = GET_MODE (operands[0]);
14660 bool sign_bit_compare_p = false;;
14663 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14664 compare_seq = get_insns ();
14667 compare_code = GET_CODE (compare_op);
14669 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14670 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14671 sign_bit_compare_p = true;
14673 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14674 HImode insns, we'd be swallowed in word prefix ops. */
14676 if ((mode != HImode || TARGET_FAST_PREFIX)
14677 && (mode != (TARGET_64BIT ? TImode : DImode))
14678 && CONST_INT_P (operands[2])
14679 && CONST_INT_P (operands[3]))
14681 rtx out = operands[0];
14682 HOST_WIDE_INT ct = INTVAL (operands[2]);
14683 HOST_WIDE_INT cf = INTVAL (operands[3]);
14684 HOST_WIDE_INT diff;
14687 /* Sign bit compares are better done using shifts than we do by using
14689 if (sign_bit_compare_p
14690 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14691 ix86_compare_op1, &compare_op))
14693 /* Detect overlap between destination and compare sources. */
14696 if (!sign_bit_compare_p)
14698 bool fpcmp = false;
14700 compare_code = GET_CODE (compare_op);
14702 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14703 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14706 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14709 /* To simplify rest of code, restrict to the GEU case. */
14710 if (compare_code == LTU)
14712 HOST_WIDE_INT tmp = ct;
14715 compare_code = reverse_condition (compare_code);
14716 code = reverse_condition (code);
14721 PUT_CODE (compare_op,
14722 reverse_condition_maybe_unordered
14723 (GET_CODE (compare_op)));
14725 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14729 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14730 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14731 tmp = gen_reg_rtx (mode);
14733 if (mode == DImode)
14734 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14736 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14740 if (code == GT || code == GE)
14741 code = reverse_condition (code);
14744 HOST_WIDE_INT tmp = ct;
14749 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14750 ix86_compare_op1, VOIDmode, 0, -1);
14763 tmp = expand_simple_binop (mode, PLUS,
14765 copy_rtx (tmp), 1, OPTAB_DIRECT);
14776 tmp = expand_simple_binop (mode, IOR,
14778 copy_rtx (tmp), 1, OPTAB_DIRECT);
14780 else if (diff == -1 && ct)
14790 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14792 tmp = expand_simple_binop (mode, PLUS,
14793 copy_rtx (tmp), GEN_INT (cf),
14794 copy_rtx (tmp), 1, OPTAB_DIRECT);
14802 * andl cf - ct, dest
14812 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14815 tmp = expand_simple_binop (mode, AND,
14817 gen_int_mode (cf - ct, mode),
14818 copy_rtx (tmp), 1, OPTAB_DIRECT);
14820 tmp = expand_simple_binop (mode, PLUS,
14821 copy_rtx (tmp), GEN_INT (ct),
14822 copy_rtx (tmp), 1, OPTAB_DIRECT);
14825 if (!rtx_equal_p (tmp, out))
14826 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14828 return 1; /* DONE */
14833 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14836 tmp = ct, ct = cf, cf = tmp;
14839 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14841 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14843 /* We may be reversing unordered compare to normal compare, that
14844 is not valid in general (we may convert non-trapping condition
14845 to trapping one), however on i386 we currently emit all
14846 comparisons unordered. */
14847 compare_code = reverse_condition_maybe_unordered (compare_code);
14848 code = reverse_condition_maybe_unordered (code);
14852 compare_code = reverse_condition (compare_code);
14853 code = reverse_condition (code);
14857 compare_code = UNKNOWN;
14858 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14859 && CONST_INT_P (ix86_compare_op1))
14861 if (ix86_compare_op1 == const0_rtx
14862 && (code == LT || code == GE))
14863 compare_code = code;
14864 else if (ix86_compare_op1 == constm1_rtx)
14868 else if (code == GT)
14873 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14874 if (compare_code != UNKNOWN
14875 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14876 && (cf == -1 || ct == -1))
14878 /* If lea code below could be used, only optimize
14879 if it results in a 2 insn sequence. */
14881 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14882 || diff == 3 || diff == 5 || diff == 9)
14883 || (compare_code == LT && ct == -1)
14884 || (compare_code == GE && cf == -1))
14887 * notl op1 (if necessary)
14895 code = reverse_condition (code);
14898 out = emit_store_flag (out, code, ix86_compare_op0,
14899 ix86_compare_op1, VOIDmode, 0, -1);
14901 out = expand_simple_binop (mode, IOR,
14903 out, 1, OPTAB_DIRECT);
14904 if (out != operands[0])
14905 emit_move_insn (operands[0], out);
14907 return 1; /* DONE */
14912 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14913 || diff == 3 || diff == 5 || diff == 9)
14914 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14916 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14922 * lea cf(dest*(ct-cf)),dest
14926 * This also catches the degenerate setcc-only case.
14932 out = emit_store_flag (out, code, ix86_compare_op0,
14933 ix86_compare_op1, VOIDmode, 0, 1);
14936 /* On x86_64 the lea instruction operates on Pmode, so we need
14937 to get arithmetics done in proper mode to match. */
14939 tmp = copy_rtx (out);
14943 out1 = copy_rtx (out);
14944 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14948 tmp = gen_rtx_PLUS (mode, tmp, out1);
14954 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14957 if (!rtx_equal_p (tmp, out))
14960 out = force_operand (tmp, copy_rtx (out));
14962 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14964 if (!rtx_equal_p (out, operands[0]))
14965 emit_move_insn (operands[0], copy_rtx (out));
14967 return 1; /* DONE */
14971 * General case: Jumpful:
14972 * xorl dest,dest cmpl op1, op2
14973 * cmpl op1, op2 movl ct, dest
14974 * setcc dest jcc 1f
14975 * decl dest movl cf, dest
14976 * andl (cf-ct),dest 1:
14979 * Size 20. Size 14.
14981 * This is reasonably steep, but branch mispredict costs are
14982 * high on modern cpus, so consider failing only if optimizing
14986 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14987 && BRANCH_COST (optimize_insn_for_speed_p (),
14992 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14997 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14999 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15001 /* We may be reversing unordered compare to normal compare,
15002 that is not valid in general (we may convert non-trapping
15003 condition to trapping one), however on i386 we currently
15004 emit all comparisons unordered. */
15005 code = reverse_condition_maybe_unordered (code);
15009 code = reverse_condition (code);
15010 if (compare_code != UNKNOWN)
15011 compare_code = reverse_condition (compare_code);
15015 if (compare_code != UNKNOWN)
15017 /* notl op1 (if needed)
15022 For x < 0 (resp. x <= -1) there will be no notl,
15023 so if possible swap the constants to get rid of the
15025 True/false will be -1/0 while code below (store flag
15026 followed by decrement) is 0/-1, so the constants need
15027 to be exchanged once more. */
15029 if (compare_code == GE || !cf)
15031 code = reverse_condition (code);
15036 HOST_WIDE_INT tmp = cf;
15041 out = emit_store_flag (out, code, ix86_compare_op0,
15042 ix86_compare_op1, VOIDmode, 0, -1);
15046 out = emit_store_flag (out, code, ix86_compare_op0,
15047 ix86_compare_op1, VOIDmode, 0, 1);
15049 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15050 copy_rtx (out), 1, OPTAB_DIRECT);
15053 out = expand_simple_binop (mode, AND, copy_rtx (out),
15054 gen_int_mode (cf - ct, mode),
15055 copy_rtx (out), 1, OPTAB_DIRECT);
15057 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15058 copy_rtx (out), 1, OPTAB_DIRECT);
15059 if (!rtx_equal_p (out, operands[0]))
15060 emit_move_insn (operands[0], copy_rtx (out));
15062 return 1; /* DONE */
15066 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15068 /* Try a few things more with specific constants and a variable. */
15071 rtx var, orig_out, out, tmp;
15073 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15074 return 0; /* FAIL */
15076 /* If one of the two operands is an interesting constant, load a
15077 constant with the above and mask it in with a logical operation. */
15079 if (CONST_INT_P (operands[2]))
15082 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15083 operands[3] = constm1_rtx, op = and_optab;
15084 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15085 operands[3] = const0_rtx, op = ior_optab;
15087 return 0; /* FAIL */
15089 else if (CONST_INT_P (operands[3]))
15092 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15093 operands[2] = constm1_rtx, op = and_optab;
15094 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15095 operands[2] = const0_rtx, op = ior_optab;
15097 return 0; /* FAIL */
15100 return 0; /* FAIL */
15102 orig_out = operands[0];
15103 tmp = gen_reg_rtx (mode);
15106 /* Recurse to get the constant loaded. */
15107 if (ix86_expand_int_movcc (operands) == 0)
15108 return 0; /* FAIL */
15110 /* Mask in the interesting variable. */
15111 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15113 if (!rtx_equal_p (out, orig_out))
15114 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15116 return 1; /* DONE */
15120 * For comparison with above,
15130 if (! nonimmediate_operand (operands[2], mode))
15131 operands[2] = force_reg (mode, operands[2]);
15132 if (! nonimmediate_operand (operands[3], mode))
15133 operands[3] = force_reg (mode, operands[3]);
15135 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15137 rtx tmp = gen_reg_rtx (mode);
15138 emit_move_insn (tmp, operands[3]);
15141 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15143 rtx tmp = gen_reg_rtx (mode);
15144 emit_move_insn (tmp, operands[2]);
15148 if (! register_operand (operands[2], VOIDmode)
15150 || ! register_operand (operands[3], VOIDmode)))
15151 operands[2] = force_reg (mode, operands[2]);
15154 && ! register_operand (operands[3], VOIDmode))
15155 operands[3] = force_reg (mode, operands[3]);
15157 emit_insn (compare_seq);
15158 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15159 gen_rtx_IF_THEN_ELSE (mode,
15160 compare_op, operands[2],
15163 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15164 gen_rtx_IF_THEN_ELSE (mode,
15166 copy_rtx (operands[3]),
15167 copy_rtx (operands[0]))));
15169 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15170 gen_rtx_IF_THEN_ELSE (mode,
15172 copy_rtx (operands[2]),
15173 copy_rtx (operands[0]))));
15175 return 1; /* DONE */
15178 /* Swap, force into registers, or otherwise massage the two operands
15179 to an sse comparison with a mask result. Thus we differ a bit from
15180 ix86_prepare_fp_compare_args which expects to produce a flags result.
15182 The DEST operand exists to help determine whether to commute commutative
15183 operators. The POP0/POP1 operands are updated in place. The new
15184 comparison code is returned, or UNKNOWN if not implementable. */
15186 static enum rtx_code
15187 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15188 rtx *pop0, rtx *pop1)
15196 /* We have no LTGT as an operator. We could implement it with
15197 NE & ORDERED, but this requires an extra temporary. It's
15198 not clear that it's worth it. */
15205 /* These are supported directly. */
15212 /* For commutative operators, try to canonicalize the destination
15213 operand to be first in the comparison - this helps reload to
15214 avoid extra moves. */
15215 if (!dest || !rtx_equal_p (dest, *pop1))
15223 /* These are not supported directly. Swap the comparison operands
15224 to transform into something that is supported. */
15228 code = swap_condition (code);
15232 gcc_unreachable ();
15238 /* Detect conditional moves that exactly match min/max operational
15239 semantics. Note that this is IEEE safe, as long as we don't
15240 interchange the operands.
15242 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15243 and TRUE if the operation is successful and instructions are emitted. */
15246 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15247 rtx cmp_op1, rtx if_true, rtx if_false)
15249 enum machine_mode mode;
15255 else if (code == UNGE)
15258 if_true = if_false;
15264 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15266 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15271 mode = GET_MODE (dest);
15273 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15274 but MODE may be a vector mode and thus not appropriate. */
15275 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15277 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15280 if_true = force_reg (mode, if_true);
15281 v = gen_rtvec (2, if_true, if_false);
15282 tmp = gen_rtx_UNSPEC (mode, v, u);
15286 code = is_min ? SMIN : SMAX;
15287 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15290 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15294 /* Expand an sse vector comparison. Return the register with the result. */
15297 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15298 rtx op_true, rtx op_false)
15300 enum machine_mode mode = GET_MODE (dest);
15303 cmp_op0 = force_reg (mode, cmp_op0);
15304 if (!nonimmediate_operand (cmp_op1, mode))
15305 cmp_op1 = force_reg (mode, cmp_op1);
15308 || reg_overlap_mentioned_p (dest, op_true)
15309 || reg_overlap_mentioned_p (dest, op_false))
15310 dest = gen_reg_rtx (mode);
15312 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15313 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15318 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15319 operations. This is used for both scalar and vector conditional moves. */
15322 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15324 enum machine_mode mode = GET_MODE (dest);
15327 if (op_false == CONST0_RTX (mode))
15329 op_true = force_reg (mode, op_true);
15330 x = gen_rtx_AND (mode, cmp, op_true);
15331 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15333 else if (op_true == CONST0_RTX (mode))
15335 op_false = force_reg (mode, op_false);
15336 x = gen_rtx_NOT (mode, cmp);
15337 x = gen_rtx_AND (mode, x, op_false);
15338 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15340 else if (TARGET_SSE5)
15342 rtx pcmov = gen_rtx_SET (mode, dest,
15343 gen_rtx_IF_THEN_ELSE (mode, cmp,
15350 op_true = force_reg (mode, op_true);
15351 op_false = force_reg (mode, op_false);
15353 t2 = gen_reg_rtx (mode);
15355 t3 = gen_reg_rtx (mode);
15359 x = gen_rtx_AND (mode, op_true, cmp);
15360 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15362 x = gen_rtx_NOT (mode, cmp);
15363 x = gen_rtx_AND (mode, x, op_false);
15364 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15366 x = gen_rtx_IOR (mode, t3, t2);
15367 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15371 /* Expand a floating-point conditional move. Return true if successful. */
15374 ix86_expand_fp_movcc (rtx operands[])
15376 enum machine_mode mode = GET_MODE (operands[0]);
15377 enum rtx_code code = GET_CODE (operands[1]);
15378 rtx tmp, compare_op, second_test, bypass_test;
15380 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15382 enum machine_mode cmode;
15384 /* Since we've no cmove for sse registers, don't force bad register
15385 allocation just to gain access to it. Deny movcc when the
15386 comparison mode doesn't match the move mode. */
15387 cmode = GET_MODE (ix86_compare_op0);
15388 if (cmode == VOIDmode)
15389 cmode = GET_MODE (ix86_compare_op1);
15393 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15395 &ix86_compare_op1);
15396 if (code == UNKNOWN)
15399 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15400 ix86_compare_op1, operands[2],
15404 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15405 ix86_compare_op1, operands[2], operands[3]);
15406 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15410 /* The floating point conditional move instructions don't directly
15411 support conditions resulting from a signed integer comparison. */
15413 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15415 /* The floating point conditional move instructions don't directly
15416 support signed integer comparisons. */
15418 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15420 gcc_assert (!second_test && !bypass_test);
15421 tmp = gen_reg_rtx (QImode);
15422 ix86_expand_setcc (code, tmp);
15424 ix86_compare_op0 = tmp;
15425 ix86_compare_op1 = const0_rtx;
15426 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15428 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15430 tmp = gen_reg_rtx (mode);
15431 emit_move_insn (tmp, operands[3]);
15434 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15436 tmp = gen_reg_rtx (mode);
15437 emit_move_insn (tmp, operands[2]);
15441 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15442 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15443 operands[2], operands[3])));
15445 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15446 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15447 operands[3], operands[0])));
15449 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15450 gen_rtx_IF_THEN_ELSE (mode, second_test,
15451 operands[2], operands[0])));
15456 /* Expand a floating-point vector conditional move; a vcond operation
15457 rather than a movcc operation. */
15460 ix86_expand_fp_vcond (rtx operands[])
15462 enum rtx_code code = GET_CODE (operands[3]);
15465 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15466 &operands[4], &operands[5]);
15467 if (code == UNKNOWN)
15470 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15471 operands[5], operands[1], operands[2]))
15474 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15475 operands[1], operands[2]);
15476 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15480 /* Expand a signed/unsigned integral vector conditional move. */
15483 ix86_expand_int_vcond (rtx operands[])
15485 enum machine_mode mode = GET_MODE (operands[0]);
15486 enum rtx_code code = GET_CODE (operands[3]);
15487 bool negate = false;
15490 cop0 = operands[4];
15491 cop1 = operands[5];
15493 /* SSE5 supports all of the comparisons on all vector int types. */
15496 /* Canonicalize the comparison to EQ, GT, GTU. */
15507 code = reverse_condition (code);
15513 code = reverse_condition (code);
15519 code = swap_condition (code);
15520 x = cop0, cop0 = cop1, cop1 = x;
15524 gcc_unreachable ();
15527 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15528 if (mode == V2DImode)
15533 /* SSE4.1 supports EQ. */
15534 if (!TARGET_SSE4_1)
15540 /* SSE4.2 supports GT/GTU. */
15541 if (!TARGET_SSE4_2)
15546 gcc_unreachable ();
15550 /* Unsigned parallel compare is not supported by the hardware. Play some
15551 tricks to turn this into a signed comparison against 0. */
15554 cop0 = force_reg (mode, cop0);
15563 /* Perform a parallel modulo subtraction. */
15564 t1 = gen_reg_rtx (mode);
15565 emit_insn ((mode == V4SImode
15567 : gen_subv2di3) (t1, cop0, cop1));
15569 /* Extract the original sign bit of op0. */
15570 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15572 t2 = gen_reg_rtx (mode);
15573 emit_insn ((mode == V4SImode
15575 : gen_andv2di3) (t2, cop0, mask));
15577 /* XOR it back into the result of the subtraction. This results
15578 in the sign bit set iff we saw unsigned underflow. */
15579 x = gen_reg_rtx (mode);
15580 emit_insn ((mode == V4SImode
15582 : gen_xorv2di3) (x, t1, t2));
15590 /* Perform a parallel unsigned saturating subtraction. */
15591 x = gen_reg_rtx (mode);
15592 emit_insn (gen_rtx_SET (VOIDmode, x,
15593 gen_rtx_US_MINUS (mode, cop0, cop1)));
15600 gcc_unreachable ();
15604 cop1 = CONST0_RTX (mode);
15608 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15609 operands[1+negate], operands[2-negate]);
15611 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15612 operands[2-negate]);
15616 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15617 true if we should do zero extension, else sign extension. HIGH_P is
15618 true if we want the N/2 high elements, else the low elements. */
15621 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15623 enum machine_mode imode = GET_MODE (operands[1]);
15624 rtx (*unpack)(rtx, rtx, rtx);
15631 unpack = gen_vec_interleave_highv16qi;
15633 unpack = gen_vec_interleave_lowv16qi;
15637 unpack = gen_vec_interleave_highv8hi;
15639 unpack = gen_vec_interleave_lowv8hi;
15643 unpack = gen_vec_interleave_highv4si;
15645 unpack = gen_vec_interleave_lowv4si;
15648 gcc_unreachable ();
15651 dest = gen_lowpart (imode, operands[0]);
15654 se = force_reg (imode, CONST0_RTX (imode));
15656 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15657 operands[1], pc_rtx, pc_rtx);
15659 emit_insn (unpack (dest, operands[1], se));
15662 /* This function performs the same task as ix86_expand_sse_unpack,
15663 but with SSE4.1 instructions. */
15666 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15668 enum machine_mode imode = GET_MODE (operands[1]);
15669 rtx (*unpack)(rtx, rtx);
15676 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15678 unpack = gen_sse4_1_extendv8qiv8hi2;
15682 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15684 unpack = gen_sse4_1_extendv4hiv4si2;
15688 unpack = gen_sse4_1_zero_extendv2siv2di2;
15690 unpack = gen_sse4_1_extendv2siv2di2;
15693 gcc_unreachable ();
15696 dest = operands[0];
15699 /* Shift higher 8 bytes to lower 8 bytes. */
15700 src = gen_reg_rtx (imode);
15701 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15702 gen_lowpart (TImode, operands[1]),
15708 emit_insn (unpack (dest, src));
15711 /* This function performs the same task as ix86_expand_sse_unpack,
15712 but with sse5 instructions. */
15715 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15717 enum machine_mode imode = GET_MODE (operands[1]);
15718 int pperm_bytes[16];
15720 int h = (high_p) ? 8 : 0;
15723 rtvec v = rtvec_alloc (16);
15726 rtx op0 = operands[0], op1 = operands[1];
15731 vs = rtvec_alloc (8);
15732 h2 = (high_p) ? 8 : 0;
15733 for (i = 0; i < 8; i++)
15735 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15736 pperm_bytes[2*i+1] = ((unsigned_p)
15738 : PPERM_SIGN | PPERM_SRC2 | i | h);
15741 for (i = 0; i < 16; i++)
15742 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15744 for (i = 0; i < 8; i++)
15745 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15747 p = gen_rtx_PARALLEL (VOIDmode, vs);
15748 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15750 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15752 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15756 vs = rtvec_alloc (4);
15757 h2 = (high_p) ? 4 : 0;
15758 for (i = 0; i < 4; i++)
15760 sign_extend = ((unsigned_p)
15762 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15763 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15764 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15765 pperm_bytes[4*i+2] = sign_extend;
15766 pperm_bytes[4*i+3] = sign_extend;
15769 for (i = 0; i < 16; i++)
15770 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15772 for (i = 0; i < 4; i++)
15773 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15775 p = gen_rtx_PARALLEL (VOIDmode, vs);
15776 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15778 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15780 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15784 vs = rtvec_alloc (2);
15785 h2 = (high_p) ? 2 : 0;
15786 for (i = 0; i < 2; i++)
15788 sign_extend = ((unsigned_p)
15790 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15791 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15792 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15793 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15794 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15795 pperm_bytes[8*i+4] = sign_extend;
15796 pperm_bytes[8*i+5] = sign_extend;
15797 pperm_bytes[8*i+6] = sign_extend;
15798 pperm_bytes[8*i+7] = sign_extend;
15801 for (i = 0; i < 16; i++)
15802 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15804 for (i = 0; i < 2; i++)
15805 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15807 p = gen_rtx_PARALLEL (VOIDmode, vs);
15808 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15810 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15812 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15816 gcc_unreachable ();
15822 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15823 next narrower integer vector type */
15825 ix86_expand_sse5_pack (rtx operands[3])
15827 enum machine_mode imode = GET_MODE (operands[0]);
15828 int pperm_bytes[16];
15830 rtvec v = rtvec_alloc (16);
15832 rtx op0 = operands[0];
15833 rtx op1 = operands[1];
15834 rtx op2 = operands[2];
15839 for (i = 0; i < 8; i++)
15841 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15842 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15845 for (i = 0; i < 16; i++)
15846 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15848 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15849 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15853 for (i = 0; i < 4; i++)
15855 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15856 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15857 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15858 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15861 for (i = 0; i < 16; i++)
15862 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15864 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15865 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15869 for (i = 0; i < 2; i++)
15871 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15872 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15873 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15874 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15875 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15876 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15877 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15878 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15881 for (i = 0; i < 16; i++)
15882 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15884 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15885 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15889 gcc_unreachable ();
15895 /* Expand conditional increment or decrement using adb/sbb instructions.
15896 The default case using setcc followed by the conditional move can be
15897 done by generic code. */
15899 ix86_expand_int_addcc (rtx operands[])
15901 enum rtx_code code = GET_CODE (operands[1]);
15903 rtx val = const0_rtx;
15904 bool fpcmp = false;
15905 enum machine_mode mode = GET_MODE (operands[0]);
15907 if (operands[3] != const1_rtx
15908 && operands[3] != constm1_rtx)
15910 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15911 ix86_compare_op1, &compare_op))
15913 code = GET_CODE (compare_op);
15915 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15916 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15919 code = ix86_fp_compare_code_to_integer (code);
15926 PUT_CODE (compare_op,
15927 reverse_condition_maybe_unordered
15928 (GET_CODE (compare_op)));
15930 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15932 PUT_MODE (compare_op, mode);
15934 /* Construct either adc or sbb insn. */
15935 if ((code == LTU) == (operands[3] == constm1_rtx))
15937 switch (GET_MODE (operands[0]))
15940 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15943 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15946 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15949 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15952 gcc_unreachable ();
15957 switch (GET_MODE (operands[0]))
15960 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15963 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15966 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15969 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15972 gcc_unreachable ();
15975 return 1; /* DONE */
15979 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15980 works for floating pointer parameters and nonoffsetable memories.
15981 For pushes, it returns just stack offsets; the values will be saved
15982 in the right order. Maximally three parts are generated. */
15985 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
15990 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
15992 size = (GET_MODE_SIZE (mode) + 4) / 8;
15994 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
15995 gcc_assert (size >= 2 && size <= 4);
15997 /* Optimize constant pool reference to immediates. This is used by fp
15998 moves, that force all constants to memory to allow combining. */
15999 if (MEM_P (operand) && MEM_READONLY_P (operand))
16001 rtx tmp = maybe_get_pool_constant (operand);
16006 if (MEM_P (operand) && !offsettable_memref_p (operand))
16008 /* The only non-offsetable memories we handle are pushes. */
16009 int ok = push_operand (operand, VOIDmode);
16013 operand = copy_rtx (operand);
16014 PUT_MODE (operand, Pmode);
16015 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16019 if (GET_CODE (operand) == CONST_VECTOR)
16021 enum machine_mode imode = int_mode_for_mode (mode);
16022 /* Caution: if we looked through a constant pool memory above,
16023 the operand may actually have a different mode now. That's
16024 ok, since we want to pun this all the way back to an integer. */
16025 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16026 gcc_assert (operand != NULL);
16032 if (mode == DImode)
16033 split_di (&operand, 1, &parts[0], &parts[1]);
16038 if (REG_P (operand))
16040 gcc_assert (reload_completed);
16041 for (i = 0; i < size; i++)
16042 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16044 else if (offsettable_memref_p (operand))
16046 operand = adjust_address (operand, SImode, 0);
16047 parts[0] = operand;
16048 for (i = 1; i < size; i++)
16049 parts[i] = adjust_address (operand, SImode, 4 * i);
16051 else if (GET_CODE (operand) == CONST_DOUBLE)
16056 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16060 real_to_target (l, &r, mode);
16061 parts[3] = gen_int_mode (l[3], SImode);
16062 parts[2] = gen_int_mode (l[2], SImode);
16065 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16066 parts[2] = gen_int_mode (l[2], SImode);
16069 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16072 gcc_unreachable ();
16074 parts[1] = gen_int_mode (l[1], SImode);
16075 parts[0] = gen_int_mode (l[0], SImode);
16078 gcc_unreachable ();
16083 if (mode == TImode)
16084 split_ti (&operand, 1, &parts[0], &parts[1]);
16085 if (mode == XFmode || mode == TFmode)
16087 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16088 if (REG_P (operand))
16090 gcc_assert (reload_completed);
16091 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16092 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16094 else if (offsettable_memref_p (operand))
16096 operand = adjust_address (operand, DImode, 0);
16097 parts[0] = operand;
16098 parts[1] = adjust_address (operand, upper_mode, 8);
16100 else if (GET_CODE (operand) == CONST_DOUBLE)
16105 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16106 real_to_target (l, &r, mode);
16108 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16109 if (HOST_BITS_PER_WIDE_INT >= 64)
16112 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16113 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16116 parts[0] = immed_double_const (l[0], l[1], DImode);
16118 if (upper_mode == SImode)
16119 parts[1] = gen_int_mode (l[2], SImode);
16120 else if (HOST_BITS_PER_WIDE_INT >= 64)
16123 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16124 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16127 parts[1] = immed_double_const (l[2], l[3], DImode);
16130 gcc_unreachable ();
16137 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16138 Return false when normal moves are needed; true when all required
16139 insns have been emitted. Operands 2-4 contain the input values
16140 int the correct order; operands 5-7 contain the output values. */
16143 ix86_split_long_move (rtx operands[])
16148 int collisions = 0;
16149 enum machine_mode mode = GET_MODE (operands[0]);
16150 bool collisionparts[4];
16152 /* The DFmode expanders may ask us to move double.
16153 For 64bit target this is single move. By hiding the fact
16154 here we simplify i386.md splitters. */
16155 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16157 /* Optimize constant pool reference to immediates. This is used by
16158 fp moves, that force all constants to memory to allow combining. */
16160 if (MEM_P (operands[1])
16161 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16162 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16163 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16164 if (push_operand (operands[0], VOIDmode))
16166 operands[0] = copy_rtx (operands[0]);
16167 PUT_MODE (operands[0], Pmode);
16170 operands[0] = gen_lowpart (DImode, operands[0]);
16171 operands[1] = gen_lowpart (DImode, operands[1]);
16172 emit_move_insn (operands[0], operands[1]);
16176 /* The only non-offsettable memory we handle is push. */
16177 if (push_operand (operands[0], VOIDmode))
16180 gcc_assert (!MEM_P (operands[0])
16181 || offsettable_memref_p (operands[0]));
16183 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16184 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16186 /* When emitting push, take care for source operands on the stack. */
16187 if (push && MEM_P (operands[1])
16188 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16189 for (i = 0; i < nparts - 1; i++)
16190 part[1][i] = change_address (part[1][i],
16191 GET_MODE (part[1][i]),
16192 XEXP (part[1][i + 1], 0));
16194 /* We need to do copy in the right order in case an address register
16195 of the source overlaps the destination. */
16196 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16200 for (i = 0; i < nparts; i++)
16203 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16204 if (collisionparts[i])
16208 /* Collision in the middle part can be handled by reordering. */
16209 if (collisions == 1 && nparts == 3 && collisionparts [1])
16211 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16212 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16214 else if (collisions == 1
16216 && (collisionparts [1] || collisionparts [2]))
16218 if (collisionparts [1])
16220 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16221 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16225 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16226 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16230 /* If there are more collisions, we can't handle it by reordering.
16231 Do an lea to the last part and use only one colliding move. */
16232 else if (collisions > 1)
16238 base = part[0][nparts - 1];
16240 /* Handle the case when the last part isn't valid for lea.
16241 Happens in 64-bit mode storing the 12-byte XFmode. */
16242 if (GET_MODE (base) != Pmode)
16243 base = gen_rtx_REG (Pmode, REGNO (base));
16245 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16246 part[1][0] = replace_equiv_address (part[1][0], base);
16247 for (i = 1; i < nparts; i++)
16249 tmp = plus_constant (base, UNITS_PER_WORD * i);
16250 part[1][i] = replace_equiv_address (part[1][i], tmp);
16261 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16262 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
16263 emit_move_insn (part[0][2], part[1][2]);
16265 else if (nparts == 4)
16267 emit_move_insn (part[0][3], part[1][3]);
16268 emit_move_insn (part[0][2], part[1][2]);
16273 /* In 64bit mode we don't have 32bit push available. In case this is
16274 register, it is OK - we will just use larger counterpart. We also
16275 retype memory - these comes from attempt to avoid REX prefix on
16276 moving of second half of TFmode value. */
16277 if (GET_MODE (part[1][1]) == SImode)
16279 switch (GET_CODE (part[1][1]))
16282 part[1][1] = adjust_address (part[1][1], DImode, 0);
16286 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16290 gcc_unreachable ();
16293 if (GET_MODE (part[1][0]) == SImode)
16294 part[1][0] = part[1][1];
16297 emit_move_insn (part[0][1], part[1][1]);
16298 emit_move_insn (part[0][0], part[1][0]);
16302 /* Choose correct order to not overwrite the source before it is copied. */
16303 if ((REG_P (part[0][0])
16304 && REG_P (part[1][1])
16305 && (REGNO (part[0][0]) == REGNO (part[1][1])
16307 && REGNO (part[0][0]) == REGNO (part[1][2]))
16309 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16311 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16313 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16315 operands[2 + i] = part[0][j];
16316 operands[6 + i] = part[1][j];
16321 for (i = 0; i < nparts; i++)
16323 operands[2 + i] = part[0][i];
16324 operands[6 + i] = part[1][i];
16328 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16329 if (optimize_insn_for_size_p ())
16331 for (j = 0; j < nparts - 1; j++)
16332 if (CONST_INT_P (operands[6 + j])
16333 && operands[6 + j] != const0_rtx
16334 && REG_P (operands[2 + j]))
16335 for (i = j; i < nparts - 1; i++)
16336 if (CONST_INT_P (operands[7 + i])
16337 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16338 operands[7 + i] = operands[2 + j];
16341 for (i = 0; i < nparts; i++)
16342 emit_move_insn (operands[2 + i], operands[6 + i]);
16347 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16348 left shift by a constant, either using a single shift or
16349 a sequence of add instructions. */
16352 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16356 emit_insn ((mode == DImode
16358 : gen_adddi3) (operand, operand, operand));
16360 else if (!optimize_insn_for_size_p ()
16361 && count * ix86_cost->add <= ix86_cost->shift_const)
16364 for (i=0; i<count; i++)
16366 emit_insn ((mode == DImode
16368 : gen_adddi3) (operand, operand, operand));
16372 emit_insn ((mode == DImode
16374 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16378 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16380 rtx low[2], high[2];
16382 const int single_width = mode == DImode ? 32 : 64;
16384 if (CONST_INT_P (operands[2]))
16386 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16387 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16389 if (count >= single_width)
16391 emit_move_insn (high[0], low[1]);
16392 emit_move_insn (low[0], const0_rtx);
16394 if (count > single_width)
16395 ix86_expand_ashl_const (high[0], count - single_width, mode);
16399 if (!rtx_equal_p (operands[0], operands[1]))
16400 emit_move_insn (operands[0], operands[1]);
16401 emit_insn ((mode == DImode
16403 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16404 ix86_expand_ashl_const (low[0], count, mode);
16409 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16411 if (operands[1] == const1_rtx)
16413 /* Assuming we've chosen a QImode capable registers, then 1 << N
16414 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16415 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16417 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16419 ix86_expand_clear (low[0]);
16420 ix86_expand_clear (high[0]);
16421 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16423 d = gen_lowpart (QImode, low[0]);
16424 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16425 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16426 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16428 d = gen_lowpart (QImode, high[0]);
16429 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16430 s = gen_rtx_NE (QImode, flags, const0_rtx);
16431 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16434 /* Otherwise, we can get the same results by manually performing
16435 a bit extract operation on bit 5/6, and then performing the two
16436 shifts. The two methods of getting 0/1 into low/high are exactly
16437 the same size. Avoiding the shift in the bit extract case helps
16438 pentium4 a bit; no one else seems to care much either way. */
16443 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16444 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16446 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16447 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16449 emit_insn ((mode == DImode
16451 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16452 emit_insn ((mode == DImode
16454 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16455 emit_move_insn (low[0], high[0]);
16456 emit_insn ((mode == DImode
16458 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16461 emit_insn ((mode == DImode
16463 : gen_ashldi3) (low[0], low[0], operands[2]));
16464 emit_insn ((mode == DImode
16466 : gen_ashldi3) (high[0], high[0], operands[2]));
16470 if (operands[1] == constm1_rtx)
16472 /* For -1 << N, we can avoid the shld instruction, because we
16473 know that we're shifting 0...31/63 ones into a -1. */
16474 emit_move_insn (low[0], constm1_rtx);
16475 if (optimize_insn_for_size_p ())
16476 emit_move_insn (high[0], low[0]);
16478 emit_move_insn (high[0], constm1_rtx);
16482 if (!rtx_equal_p (operands[0], operands[1]))
16483 emit_move_insn (operands[0], operands[1]);
16485 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16486 emit_insn ((mode == DImode
16488 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16491 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16493 if (TARGET_CMOVE && scratch)
16495 ix86_expand_clear (scratch);
16496 emit_insn ((mode == DImode
16497 ? gen_x86_shift_adj_1
16498 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16502 emit_insn ((mode == DImode
16503 ? gen_x86_shift_adj_2
16504 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16508 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16510 rtx low[2], high[2];
16512 const int single_width = mode == DImode ? 32 : 64;
16514 if (CONST_INT_P (operands[2]))
16516 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16517 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16519 if (count == single_width * 2 - 1)
16521 emit_move_insn (high[0], high[1]);
16522 emit_insn ((mode == DImode
16524 : gen_ashrdi3) (high[0], high[0],
16525 GEN_INT (single_width - 1)));
16526 emit_move_insn (low[0], high[0]);
16529 else if (count >= single_width)
16531 emit_move_insn (low[0], high[1]);
16532 emit_move_insn (high[0], low[0]);
16533 emit_insn ((mode == DImode
16535 : gen_ashrdi3) (high[0], high[0],
16536 GEN_INT (single_width - 1)));
16537 if (count > single_width)
16538 emit_insn ((mode == DImode
16540 : gen_ashrdi3) (low[0], low[0],
16541 GEN_INT (count - single_width)));
16545 if (!rtx_equal_p (operands[0], operands[1]))
16546 emit_move_insn (operands[0], operands[1]);
16547 emit_insn ((mode == DImode
16549 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16550 emit_insn ((mode == DImode
16552 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16557 if (!rtx_equal_p (operands[0], operands[1]))
16558 emit_move_insn (operands[0], operands[1]);
16560 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16562 emit_insn ((mode == DImode
16564 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16565 emit_insn ((mode == DImode
16567 : gen_ashrdi3) (high[0], high[0], operands[2]));
16569 if (TARGET_CMOVE && scratch)
16571 emit_move_insn (scratch, high[0]);
16572 emit_insn ((mode == DImode
16574 : gen_ashrdi3) (scratch, scratch,
16575 GEN_INT (single_width - 1)));
16576 emit_insn ((mode == DImode
16577 ? gen_x86_shift_adj_1
16578 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16582 emit_insn ((mode == DImode
16583 ? gen_x86_shift_adj_3
16584 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16589 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16591 rtx low[2], high[2];
16593 const int single_width = mode == DImode ? 32 : 64;
16595 if (CONST_INT_P (operands[2]))
16597 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16598 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16600 if (count >= single_width)
16602 emit_move_insn (low[0], high[1]);
16603 ix86_expand_clear (high[0]);
16605 if (count > single_width)
16606 emit_insn ((mode == DImode
16608 : gen_lshrdi3) (low[0], low[0],
16609 GEN_INT (count - single_width)));
16613 if (!rtx_equal_p (operands[0], operands[1]))
16614 emit_move_insn (operands[0], operands[1]);
16615 emit_insn ((mode == DImode
16617 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16618 emit_insn ((mode == DImode
16620 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16625 if (!rtx_equal_p (operands[0], operands[1]))
16626 emit_move_insn (operands[0], operands[1]);
16628 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16630 emit_insn ((mode == DImode
16632 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16633 emit_insn ((mode == DImode
16635 : gen_lshrdi3) (high[0], high[0], operands[2]));
16637 /* Heh. By reversing the arguments, we can reuse this pattern. */
16638 if (TARGET_CMOVE && scratch)
16640 ix86_expand_clear (scratch);
16641 emit_insn ((mode == DImode
16642 ? gen_x86_shift_adj_1
16643 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16647 emit_insn ((mode == DImode
16648 ? gen_x86_shift_adj_2
16649 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16653 /* Predict just emitted jump instruction to be taken with probability PROB. */
16655 predict_jump (int prob)
16657 rtx insn = get_last_insn ();
16658 gcc_assert (JUMP_P (insn));
16660 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16665 /* Helper function for the string operations below. Dest VARIABLE whether
16666 it is aligned to VALUE bytes. If true, jump to the label. */
16668 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16670 rtx label = gen_label_rtx ();
16671 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16672 if (GET_MODE (variable) == DImode)
16673 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16675 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16676 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16679 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16681 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16685 /* Adjust COUNTER by the VALUE. */
16687 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16689 if (GET_MODE (countreg) == DImode)
16690 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16692 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16695 /* Zero extend possibly SImode EXP to Pmode register. */
16697 ix86_zero_extend_to_Pmode (rtx exp)
16700 if (GET_MODE (exp) == VOIDmode)
16701 return force_reg (Pmode, exp);
16702 if (GET_MODE (exp) == Pmode)
16703 return copy_to_mode_reg (Pmode, exp);
16704 r = gen_reg_rtx (Pmode);
16705 emit_insn (gen_zero_extendsidi2 (r, exp));
16709 /* Divide COUNTREG by SCALE. */
16711 scale_counter (rtx countreg, int scale)
16714 rtx piece_size_mask;
16718 if (CONST_INT_P (countreg))
16719 return GEN_INT (INTVAL (countreg) / scale);
16720 gcc_assert (REG_P (countreg));
16722 piece_size_mask = GEN_INT (scale - 1);
16723 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16724 GEN_INT (exact_log2 (scale)),
16725 NULL, 1, OPTAB_DIRECT);
16729 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16730 DImode for constant loop counts. */
16732 static enum machine_mode
16733 counter_mode (rtx count_exp)
16735 if (GET_MODE (count_exp) != VOIDmode)
16736 return GET_MODE (count_exp);
16737 if (GET_CODE (count_exp) != CONST_INT)
16739 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16744 /* When SRCPTR is non-NULL, output simple loop to move memory
16745 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16746 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16747 equivalent loop to set memory by VALUE (supposed to be in MODE).
16749 The size is rounded down to whole number of chunk size moved at once.
16750 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16754 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16755 rtx destptr, rtx srcptr, rtx value,
16756 rtx count, enum machine_mode mode, int unroll,
16759 rtx out_label, top_label, iter, tmp;
16760 enum machine_mode iter_mode = counter_mode (count);
16761 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16762 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16768 top_label = gen_label_rtx ();
16769 out_label = gen_label_rtx ();
16770 iter = gen_reg_rtx (iter_mode);
16772 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16773 NULL, 1, OPTAB_DIRECT);
16774 /* Those two should combine. */
16775 if (piece_size == const1_rtx)
16777 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16779 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16781 emit_move_insn (iter, const0_rtx);
16783 emit_label (top_label);
16785 tmp = convert_modes (Pmode, iter_mode, iter, true);
16786 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16787 destmem = change_address (destmem, mode, x_addr);
16791 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16792 srcmem = change_address (srcmem, mode, y_addr);
16794 /* When unrolling for chips that reorder memory reads and writes,
16795 we can save registers by using single temporary.
16796 Also using 4 temporaries is overkill in 32bit mode. */
16797 if (!TARGET_64BIT && 0)
16799 for (i = 0; i < unroll; i++)
16804 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16806 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16808 emit_move_insn (destmem, srcmem);
16814 gcc_assert (unroll <= 4);
16815 for (i = 0; i < unroll; i++)
16817 tmpreg[i] = gen_reg_rtx (mode);
16821 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16823 emit_move_insn (tmpreg[i], srcmem);
16825 for (i = 0; i < unroll; i++)
16830 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16832 emit_move_insn (destmem, tmpreg[i]);
16837 for (i = 0; i < unroll; i++)
16841 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16842 emit_move_insn (destmem, value);
16845 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16846 true, OPTAB_LIB_WIDEN);
16848 emit_move_insn (iter, tmp);
16850 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16852 if (expected_size != -1)
16854 expected_size /= GET_MODE_SIZE (mode) * unroll;
16855 if (expected_size == 0)
16857 else if (expected_size > REG_BR_PROB_BASE)
16858 predict_jump (REG_BR_PROB_BASE - 1);
16860 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16863 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16864 iter = ix86_zero_extend_to_Pmode (iter);
16865 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16866 true, OPTAB_LIB_WIDEN);
16867 if (tmp != destptr)
16868 emit_move_insn (destptr, tmp);
16871 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16872 true, OPTAB_LIB_WIDEN);
16874 emit_move_insn (srcptr, tmp);
16876 emit_label (out_label);
16879 /* Output "rep; mov" instruction.
16880 Arguments have same meaning as for previous function */
16882 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16883 rtx destptr, rtx srcptr,
16885 enum machine_mode mode)
16891 /* If the size is known, it is shorter to use rep movs. */
16892 if (mode == QImode && CONST_INT_P (count)
16893 && !(INTVAL (count) & 3))
16896 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16897 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16898 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16899 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16900 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16901 if (mode != QImode)
16903 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16904 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16905 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16906 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16907 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16908 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16912 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16913 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16915 if (CONST_INT_P (count))
16917 count = GEN_INT (INTVAL (count)
16918 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16919 destmem = shallow_copy_rtx (destmem);
16920 srcmem = shallow_copy_rtx (srcmem);
16921 set_mem_size (destmem, count);
16922 set_mem_size (srcmem, count);
16926 if (MEM_SIZE (destmem))
16927 set_mem_size (destmem, NULL_RTX);
16928 if (MEM_SIZE (srcmem))
16929 set_mem_size (srcmem, NULL_RTX);
16931 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16935 /* Output "rep; stos" instruction.
16936 Arguments have same meaning as for previous function */
16938 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16939 rtx count, enum machine_mode mode,
16945 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16946 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16947 value = force_reg (mode, gen_lowpart (mode, value));
16948 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16949 if (mode != QImode)
16951 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16952 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16953 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16956 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16957 if (orig_value == const0_rtx && CONST_INT_P (count))
16959 count = GEN_INT (INTVAL (count)
16960 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16961 destmem = shallow_copy_rtx (destmem);
16962 set_mem_size (destmem, count);
16964 else if (MEM_SIZE (destmem))
16965 set_mem_size (destmem, NULL_RTX);
16966 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16970 emit_strmov (rtx destmem, rtx srcmem,
16971 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16973 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16974 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16975 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16978 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16980 expand_movmem_epilogue (rtx destmem, rtx srcmem,
16981 rtx destptr, rtx srcptr, rtx count, int max_size)
16984 if (CONST_INT_P (count))
16986 HOST_WIDE_INT countval = INTVAL (count);
16989 if ((countval & 0x10) && max_size > 16)
16993 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16994 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
16997 gcc_unreachable ();
17000 if ((countval & 0x08) && max_size > 8)
17003 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17006 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17007 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17011 if ((countval & 0x04) && max_size > 4)
17013 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17016 if ((countval & 0x02) && max_size > 2)
17018 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17021 if ((countval & 0x01) && max_size > 1)
17023 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17030 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17031 count, 1, OPTAB_DIRECT);
17032 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17033 count, QImode, 1, 4);
17037 /* When there are stringops, we can cheaply increase dest and src pointers.
17038 Otherwise we save code size by maintaining offset (zero is readily
17039 available from preceding rep operation) and using x86 addressing modes.
17041 if (TARGET_SINGLE_STRINGOP)
17045 rtx label = ix86_expand_aligntest (count, 4, true);
17046 src = change_address (srcmem, SImode, srcptr);
17047 dest = change_address (destmem, SImode, destptr);
17048 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17049 emit_label (label);
17050 LABEL_NUSES (label) = 1;
17054 rtx label = ix86_expand_aligntest (count, 2, true);
17055 src = change_address (srcmem, HImode, srcptr);
17056 dest = change_address (destmem, HImode, destptr);
17057 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17058 emit_label (label);
17059 LABEL_NUSES (label) = 1;
17063 rtx label = ix86_expand_aligntest (count, 1, true);
17064 src = change_address (srcmem, QImode, srcptr);
17065 dest = change_address (destmem, QImode, destptr);
17066 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17067 emit_label (label);
17068 LABEL_NUSES (label) = 1;
17073 rtx offset = force_reg (Pmode, const0_rtx);
17078 rtx label = ix86_expand_aligntest (count, 4, true);
17079 src = change_address (srcmem, SImode, srcptr);
17080 dest = change_address (destmem, SImode, destptr);
17081 emit_move_insn (dest, src);
17082 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17083 true, OPTAB_LIB_WIDEN);
17085 emit_move_insn (offset, tmp);
17086 emit_label (label);
17087 LABEL_NUSES (label) = 1;
17091 rtx label = ix86_expand_aligntest (count, 2, true);
17092 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17093 src = change_address (srcmem, HImode, tmp);
17094 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17095 dest = change_address (destmem, HImode, tmp);
17096 emit_move_insn (dest, src);
17097 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17098 true, OPTAB_LIB_WIDEN);
17100 emit_move_insn (offset, tmp);
17101 emit_label (label);
17102 LABEL_NUSES (label) = 1;
17106 rtx label = ix86_expand_aligntest (count, 1, true);
17107 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17108 src = change_address (srcmem, QImode, tmp);
17109 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17110 dest = change_address (destmem, QImode, tmp);
17111 emit_move_insn (dest, src);
17112 emit_label (label);
17113 LABEL_NUSES (label) = 1;
17118 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17120 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17121 rtx count, int max_size)
17124 expand_simple_binop (counter_mode (count), AND, count,
17125 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17126 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17127 gen_lowpart (QImode, value), count, QImode,
17131 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17133 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17137 if (CONST_INT_P (count))
17139 HOST_WIDE_INT countval = INTVAL (count);
17142 if ((countval & 0x10) && max_size > 16)
17146 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17147 emit_insn (gen_strset (destptr, dest, value));
17148 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17149 emit_insn (gen_strset (destptr, dest, value));
17152 gcc_unreachable ();
17155 if ((countval & 0x08) && max_size > 8)
17159 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17160 emit_insn (gen_strset (destptr, dest, value));
17164 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17165 emit_insn (gen_strset (destptr, dest, value));
17166 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17167 emit_insn (gen_strset (destptr, dest, value));
17171 if ((countval & 0x04) && max_size > 4)
17173 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17174 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17177 if ((countval & 0x02) && max_size > 2)
17179 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17180 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17183 if ((countval & 0x01) && max_size > 1)
17185 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17186 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17193 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17198 rtx label = ix86_expand_aligntest (count, 16, true);
17201 dest = change_address (destmem, DImode, destptr);
17202 emit_insn (gen_strset (destptr, dest, value));
17203 emit_insn (gen_strset (destptr, dest, value));
17207 dest = change_address (destmem, SImode, destptr);
17208 emit_insn (gen_strset (destptr, dest, value));
17209 emit_insn (gen_strset (destptr, dest, value));
17210 emit_insn (gen_strset (destptr, dest, value));
17211 emit_insn (gen_strset (destptr, dest, value));
17213 emit_label (label);
17214 LABEL_NUSES (label) = 1;
17218 rtx label = ix86_expand_aligntest (count, 8, true);
17221 dest = change_address (destmem, DImode, destptr);
17222 emit_insn (gen_strset (destptr, dest, value));
17226 dest = change_address (destmem, SImode, destptr);
17227 emit_insn (gen_strset (destptr, dest, value));
17228 emit_insn (gen_strset (destptr, dest, value));
17230 emit_label (label);
17231 LABEL_NUSES (label) = 1;
17235 rtx label = ix86_expand_aligntest (count, 4, true);
17236 dest = change_address (destmem, SImode, destptr);
17237 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17238 emit_label (label);
17239 LABEL_NUSES (label) = 1;
17243 rtx label = ix86_expand_aligntest (count, 2, true);
17244 dest = change_address (destmem, HImode, destptr);
17245 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17246 emit_label (label);
17247 LABEL_NUSES (label) = 1;
17251 rtx label = ix86_expand_aligntest (count, 1, true);
17252 dest = change_address (destmem, QImode, destptr);
17253 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17254 emit_label (label);
17255 LABEL_NUSES (label) = 1;
17259 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17260 DESIRED_ALIGNMENT. */
17262 expand_movmem_prologue (rtx destmem, rtx srcmem,
17263 rtx destptr, rtx srcptr, rtx count,
17264 int align, int desired_alignment)
17266 if (align <= 1 && desired_alignment > 1)
17268 rtx label = ix86_expand_aligntest (destptr, 1, false);
17269 srcmem = change_address (srcmem, QImode, srcptr);
17270 destmem = change_address (destmem, QImode, destptr);
17271 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17272 ix86_adjust_counter (count, 1);
17273 emit_label (label);
17274 LABEL_NUSES (label) = 1;
17276 if (align <= 2 && desired_alignment > 2)
17278 rtx label = ix86_expand_aligntest (destptr, 2, false);
17279 srcmem = change_address (srcmem, HImode, srcptr);
17280 destmem = change_address (destmem, HImode, destptr);
17281 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17282 ix86_adjust_counter (count, 2);
17283 emit_label (label);
17284 LABEL_NUSES (label) = 1;
17286 if (align <= 4 && desired_alignment > 4)
17288 rtx label = ix86_expand_aligntest (destptr, 4, false);
17289 srcmem = change_address (srcmem, SImode, srcptr);
17290 destmem = change_address (destmem, SImode, destptr);
17291 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17292 ix86_adjust_counter (count, 4);
17293 emit_label (label);
17294 LABEL_NUSES (label) = 1;
17296 gcc_assert (desired_alignment <= 8);
17299 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17300 ALIGN_BYTES is how many bytes need to be copied. */
17302 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17303 int desired_align, int align_bytes)
17306 rtx src_size, dst_size;
17308 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17309 if (src_align_bytes >= 0)
17310 src_align_bytes = desired_align - src_align_bytes;
17311 src_size = MEM_SIZE (src);
17312 dst_size = MEM_SIZE (dst);
17313 if (align_bytes & 1)
17315 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17316 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17318 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17320 if (align_bytes & 2)
17322 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17323 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17324 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17325 set_mem_align (dst, 2 * BITS_PER_UNIT);
17326 if (src_align_bytes >= 0
17327 && (src_align_bytes & 1) == (align_bytes & 1)
17328 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17329 set_mem_align (src, 2 * BITS_PER_UNIT);
17331 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17333 if (align_bytes & 4)
17335 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17336 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17337 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17338 set_mem_align (dst, 4 * BITS_PER_UNIT);
17339 if (src_align_bytes >= 0)
17341 unsigned int src_align = 0;
17342 if ((src_align_bytes & 3) == (align_bytes & 3))
17344 else if ((src_align_bytes & 1) == (align_bytes & 1))
17346 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17347 set_mem_align (src, src_align * BITS_PER_UNIT);
17350 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17352 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17353 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17354 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17355 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17356 if (src_align_bytes >= 0)
17358 unsigned int src_align = 0;
17359 if ((src_align_bytes & 7) == (align_bytes & 7))
17361 else if ((src_align_bytes & 3) == (align_bytes & 3))
17363 else if ((src_align_bytes & 1) == (align_bytes & 1))
17365 if (src_align > (unsigned int) desired_align)
17366 src_align = desired_align;
17367 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17368 set_mem_align (src, src_align * BITS_PER_UNIT);
17371 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17373 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17378 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17379 DESIRED_ALIGNMENT. */
17381 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17382 int align, int desired_alignment)
17384 if (align <= 1 && desired_alignment > 1)
17386 rtx label = ix86_expand_aligntest (destptr, 1, false);
17387 destmem = change_address (destmem, QImode, destptr);
17388 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17389 ix86_adjust_counter (count, 1);
17390 emit_label (label);
17391 LABEL_NUSES (label) = 1;
17393 if (align <= 2 && desired_alignment > 2)
17395 rtx label = ix86_expand_aligntest (destptr, 2, false);
17396 destmem = change_address (destmem, HImode, destptr);
17397 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17398 ix86_adjust_counter (count, 2);
17399 emit_label (label);
17400 LABEL_NUSES (label) = 1;
17402 if (align <= 4 && desired_alignment > 4)
17404 rtx label = ix86_expand_aligntest (destptr, 4, false);
17405 destmem = change_address (destmem, SImode, destptr);
17406 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17407 ix86_adjust_counter (count, 4);
17408 emit_label (label);
17409 LABEL_NUSES (label) = 1;
17411 gcc_assert (desired_alignment <= 8);
17414 /* Set enough from DST to align DST known to by aligned by ALIGN to
17415 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17417 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17418 int desired_align, int align_bytes)
17421 rtx dst_size = MEM_SIZE (dst);
17422 if (align_bytes & 1)
17424 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17426 emit_insn (gen_strset (destreg, dst,
17427 gen_lowpart (QImode, value)));
17429 if (align_bytes & 2)
17431 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17432 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17433 set_mem_align (dst, 2 * BITS_PER_UNIT);
17435 emit_insn (gen_strset (destreg, dst,
17436 gen_lowpart (HImode, value)));
17438 if (align_bytes & 4)
17440 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17441 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17442 set_mem_align (dst, 4 * BITS_PER_UNIT);
17444 emit_insn (gen_strset (destreg, dst,
17445 gen_lowpart (SImode, value)));
17447 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17448 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17449 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17451 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17455 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17456 static enum stringop_alg
17457 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17458 int *dynamic_check)
17460 const struct stringop_algs * algs;
17461 bool optimize_for_speed;
17462 /* Algorithms using the rep prefix want at least edi and ecx;
17463 additionally, memset wants eax and memcpy wants esi. Don't
17464 consider such algorithms if the user has appropriated those
17465 registers for their own purposes. */
17466 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17468 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17470 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17471 || (alg != rep_prefix_1_byte \
17472 && alg != rep_prefix_4_byte \
17473 && alg != rep_prefix_8_byte))
17474 const struct processor_costs *cost;
17476 /* Even if the string operation call is cold, we still might spend a lot
17477 of time processing large blocks. */
17478 if (optimize_function_for_size_p (cfun)
17479 || (optimize_insn_for_size_p ()
17480 && expected_size != -1 && expected_size < 256))
17481 optimize_for_speed = false;
17483 optimize_for_speed = true;
17485 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17487 *dynamic_check = -1;
17489 algs = &cost->memset[TARGET_64BIT != 0];
17491 algs = &cost->memcpy[TARGET_64BIT != 0];
17492 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17493 return stringop_alg;
17494 /* rep; movq or rep; movl is the smallest variant. */
17495 else if (!optimize_for_speed)
17497 if (!count || (count & 3))
17498 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17500 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17502 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17504 else if (expected_size != -1 && expected_size < 4)
17505 return loop_1_byte;
17506 else if (expected_size != -1)
17509 enum stringop_alg alg = libcall;
17510 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17512 /* We get here if the algorithms that were not libcall-based
17513 were rep-prefix based and we are unable to use rep prefixes
17514 based on global register usage. Break out of the loop and
17515 use the heuristic below. */
17516 if (algs->size[i].max == 0)
17518 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17520 enum stringop_alg candidate = algs->size[i].alg;
17522 if (candidate != libcall && ALG_USABLE_P (candidate))
17524 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17525 last non-libcall inline algorithm. */
17526 if (TARGET_INLINE_ALL_STRINGOPS)
17528 /* When the current size is best to be copied by a libcall,
17529 but we are still forced to inline, run the heuristic below
17530 that will pick code for medium sized blocks. */
17531 if (alg != libcall)
17535 else if (ALG_USABLE_P (candidate))
17539 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17541 /* When asked to inline the call anyway, try to pick meaningful choice.
17542 We look for maximal size of block that is faster to copy by hand and
17543 take blocks of at most of that size guessing that average size will
17544 be roughly half of the block.
17546 If this turns out to be bad, we might simply specify the preferred
17547 choice in ix86_costs. */
17548 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17549 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17552 enum stringop_alg alg;
17554 bool any_alg_usable_p = true;
17556 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17558 enum stringop_alg candidate = algs->size[i].alg;
17559 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17561 if (candidate != libcall && candidate
17562 && ALG_USABLE_P (candidate))
17563 max = algs->size[i].max;
17565 /* If there aren't any usable algorithms, then recursing on
17566 smaller sizes isn't going to find anything. Just return the
17567 simple byte-at-a-time copy loop. */
17568 if (!any_alg_usable_p)
17570 /* Pick something reasonable. */
17571 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17572 *dynamic_check = 128;
17573 return loop_1_byte;
17577 alg = decide_alg (count, max / 2, memset, dynamic_check);
17578 gcc_assert (*dynamic_check == -1);
17579 gcc_assert (alg != libcall);
17580 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17581 *dynamic_check = max;
17584 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17585 #undef ALG_USABLE_P
17588 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17589 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17591 decide_alignment (int align,
17592 enum stringop_alg alg,
17595 int desired_align = 0;
17599 gcc_unreachable ();
17601 case unrolled_loop:
17602 desired_align = GET_MODE_SIZE (Pmode);
17604 case rep_prefix_8_byte:
17607 case rep_prefix_4_byte:
17608 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17609 copying whole cacheline at once. */
17610 if (TARGET_PENTIUMPRO)
17615 case rep_prefix_1_byte:
17616 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17617 copying whole cacheline at once. */
17618 if (TARGET_PENTIUMPRO)
17632 if (desired_align < align)
17633 desired_align = align;
17634 if (expected_size != -1 && expected_size < 4)
17635 desired_align = align;
17636 return desired_align;
17639 /* Return the smallest power of 2 greater than VAL. */
17641 smallest_pow2_greater_than (int val)
17649 /* Expand string move (memcpy) operation. Use i386 string operations when
17650 profitable. expand_setmem contains similar code. The code depends upon
17651 architecture, block size and alignment, but always has the same
17654 1) Prologue guard: Conditional that jumps up to epilogues for small
17655 blocks that can be handled by epilogue alone. This is faster but
17656 also needed for correctness, since prologue assume the block is larger
17657 than the desired alignment.
17659 Optional dynamic check for size and libcall for large
17660 blocks is emitted here too, with -minline-stringops-dynamically.
17662 2) Prologue: copy first few bytes in order to get destination aligned
17663 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17664 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17665 We emit either a jump tree on power of two sized blocks, or a byte loop.
17667 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17668 with specified algorithm.
17670 4) Epilogue: code copying tail of the block that is too small to be
17671 handled by main body (or up to size guarded by prologue guard). */
17674 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17675 rtx expected_align_exp, rtx expected_size_exp)
17681 rtx jump_around_label = NULL;
17682 HOST_WIDE_INT align = 1;
17683 unsigned HOST_WIDE_INT count = 0;
17684 HOST_WIDE_INT expected_size = -1;
17685 int size_needed = 0, epilogue_size_needed;
17686 int desired_align = 0, align_bytes = 0;
17687 enum stringop_alg alg;
17689 bool need_zero_guard = false;
17691 if (CONST_INT_P (align_exp))
17692 align = INTVAL (align_exp);
17693 /* i386 can do misaligned access on reasonably increased cost. */
17694 if (CONST_INT_P (expected_align_exp)
17695 && INTVAL (expected_align_exp) > align)
17696 align = INTVAL (expected_align_exp);
17697 /* ALIGN is the minimum of destination and source alignment, but we care here
17698 just about destination alignment. */
17699 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17700 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17702 if (CONST_INT_P (count_exp))
17703 count = expected_size = INTVAL (count_exp);
17704 if (CONST_INT_P (expected_size_exp) && count == 0)
17705 expected_size = INTVAL (expected_size_exp);
17707 /* Make sure we don't need to care about overflow later on. */
17708 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17711 /* Step 0: Decide on preferred algorithm, desired alignment and
17712 size of chunks to be copied by main loop. */
17714 alg = decide_alg (count, expected_size, false, &dynamic_check);
17715 desired_align = decide_alignment (align, alg, expected_size);
17717 if (!TARGET_ALIGN_STRINGOPS)
17718 align = desired_align;
17720 if (alg == libcall)
17722 gcc_assert (alg != no_stringop);
17724 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17725 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17726 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17731 gcc_unreachable ();
17733 need_zero_guard = true;
17734 size_needed = GET_MODE_SIZE (Pmode);
17736 case unrolled_loop:
17737 need_zero_guard = true;
17738 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17740 case rep_prefix_8_byte:
17743 case rep_prefix_4_byte:
17746 case rep_prefix_1_byte:
17750 need_zero_guard = true;
17755 epilogue_size_needed = size_needed;
17757 /* Step 1: Prologue guard. */
17759 /* Alignment code needs count to be in register. */
17760 if (CONST_INT_P (count_exp) && desired_align > align)
17762 if (INTVAL (count_exp) > desired_align
17763 && INTVAL (count_exp) > size_needed)
17766 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17767 if (align_bytes <= 0)
17770 align_bytes = desired_align - align_bytes;
17772 if (align_bytes == 0)
17773 count_exp = force_reg (counter_mode (count_exp), count_exp);
17775 gcc_assert (desired_align >= 1 && align >= 1);
17777 /* Ensure that alignment prologue won't copy past end of block. */
17778 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17780 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17781 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17782 Make sure it is power of 2. */
17783 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17787 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17789 /* If main algorithm works on QImode, no epilogue is needed.
17790 For small sizes just don't align anything. */
17791 if (size_needed == 1)
17792 desired_align = align;
17799 label = gen_label_rtx ();
17800 emit_cmp_and_jump_insns (count_exp,
17801 GEN_INT (epilogue_size_needed),
17802 LTU, 0, counter_mode (count_exp), 1, label);
17803 if (expected_size == -1 || expected_size < epilogue_size_needed)
17804 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17806 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17810 /* Emit code to decide on runtime whether library call or inline should be
17812 if (dynamic_check != -1)
17814 if (CONST_INT_P (count_exp))
17816 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17818 emit_block_move_via_libcall (dst, src, count_exp, false);
17819 count_exp = const0_rtx;
17825 rtx hot_label = gen_label_rtx ();
17826 jump_around_label = gen_label_rtx ();
17827 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17828 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17829 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17830 emit_block_move_via_libcall (dst, src, count_exp, false);
17831 emit_jump (jump_around_label);
17832 emit_label (hot_label);
17836 /* Step 2: Alignment prologue. */
17838 if (desired_align > align)
17840 if (align_bytes == 0)
17842 /* Except for the first move in epilogue, we no longer know
17843 constant offset in aliasing info. It don't seems to worth
17844 the pain to maintain it for the first move, so throw away
17846 src = change_address (src, BLKmode, srcreg);
17847 dst = change_address (dst, BLKmode, destreg);
17848 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17853 /* If we know how many bytes need to be stored before dst is
17854 sufficiently aligned, maintain aliasing info accurately. */
17855 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17856 desired_align, align_bytes);
17857 count_exp = plus_constant (count_exp, -align_bytes);
17858 count -= align_bytes;
17860 if (need_zero_guard
17861 && (count < (unsigned HOST_WIDE_INT) size_needed
17862 || (align_bytes == 0
17863 && count < ((unsigned HOST_WIDE_INT) size_needed
17864 + desired_align - align))))
17866 /* It is possible that we copied enough so the main loop will not
17868 gcc_assert (size_needed > 1);
17869 if (label == NULL_RTX)
17870 label = gen_label_rtx ();
17871 emit_cmp_and_jump_insns (count_exp,
17872 GEN_INT (size_needed),
17873 LTU, 0, counter_mode (count_exp), 1, label);
17874 if (expected_size == -1
17875 || expected_size < (desired_align - align) / 2 + size_needed)
17876 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17878 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17881 if (label && size_needed == 1)
17883 emit_label (label);
17884 LABEL_NUSES (label) = 1;
17886 epilogue_size_needed = 1;
17888 else if (label == NULL_RTX)
17889 epilogue_size_needed = size_needed;
17891 /* Step 3: Main loop. */
17897 gcc_unreachable ();
17899 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17900 count_exp, QImode, 1, expected_size);
17903 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17904 count_exp, Pmode, 1, expected_size);
17906 case unrolled_loop:
17907 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17908 registers for 4 temporaries anyway. */
17909 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17910 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
17913 case rep_prefix_8_byte:
17914 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17917 case rep_prefix_4_byte:
17918 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17921 case rep_prefix_1_byte:
17922 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17926 /* Adjust properly the offset of src and dest memory for aliasing. */
17927 if (CONST_INT_P (count_exp))
17929 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17930 (count / size_needed) * size_needed);
17931 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17932 (count / size_needed) * size_needed);
17936 src = change_address (src, BLKmode, srcreg);
17937 dst = change_address (dst, BLKmode, destreg);
17940 /* Step 4: Epilogue to copy the remaining bytes. */
17944 /* When the main loop is done, COUNT_EXP might hold original count,
17945 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17946 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17947 bytes. Compensate if needed. */
17949 if (size_needed < epilogue_size_needed)
17952 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17953 GEN_INT (size_needed - 1), count_exp, 1,
17955 if (tmp != count_exp)
17956 emit_move_insn (count_exp, tmp);
17958 emit_label (label);
17959 LABEL_NUSES (label) = 1;
17962 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17963 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17964 epilogue_size_needed);
17965 if (jump_around_label)
17966 emit_label (jump_around_label);
17970 /* Helper function for memcpy. For QImode value 0xXY produce
17971 0xXYXYXYXY of wide specified by MODE. This is essentially
17972 a * 0x10101010, but we can do slightly better than
17973 synth_mult by unwinding the sequence by hand on CPUs with
17976 promote_duplicated_reg (enum machine_mode mode, rtx val)
17978 enum machine_mode valmode = GET_MODE (val);
17980 int nops = mode == DImode ? 3 : 2;
17982 gcc_assert (mode == SImode || mode == DImode);
17983 if (val == const0_rtx)
17984 return copy_to_mode_reg (mode, const0_rtx);
17985 if (CONST_INT_P (val))
17987 HOST_WIDE_INT v = INTVAL (val) & 255;
17991 if (mode == DImode)
17992 v |= (v << 16) << 16;
17993 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
17996 if (valmode == VOIDmode)
17998 if (valmode != QImode)
17999 val = gen_lowpart (QImode, val);
18000 if (mode == QImode)
18002 if (!TARGET_PARTIAL_REG_STALL)
18004 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18005 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18006 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18007 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18009 rtx reg = convert_modes (mode, QImode, val, true);
18010 tmp = promote_duplicated_reg (mode, const1_rtx);
18011 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18016 rtx reg = convert_modes (mode, QImode, val, true);
18018 if (!TARGET_PARTIAL_REG_STALL)
18019 if (mode == SImode)
18020 emit_insn (gen_movsi_insv_1 (reg, reg));
18022 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18025 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18026 NULL, 1, OPTAB_DIRECT);
18028 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18030 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18031 NULL, 1, OPTAB_DIRECT);
18032 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18033 if (mode == SImode)
18035 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18036 NULL, 1, OPTAB_DIRECT);
18037 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18042 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18043 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18044 alignment from ALIGN to DESIRED_ALIGN. */
18046 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18051 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18052 promoted_val = promote_duplicated_reg (DImode, val);
18053 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18054 promoted_val = promote_duplicated_reg (SImode, val);
18055 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18056 promoted_val = promote_duplicated_reg (HImode, val);
18058 promoted_val = val;
18060 return promoted_val;
18063 /* Expand string clear operation (bzero). Use i386 string operations when
18064 profitable. See expand_movmem comment for explanation of individual
18065 steps performed. */
18067 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18068 rtx expected_align_exp, rtx expected_size_exp)
18073 rtx jump_around_label = NULL;
18074 HOST_WIDE_INT align = 1;
18075 unsigned HOST_WIDE_INT count = 0;
18076 HOST_WIDE_INT expected_size = -1;
18077 int size_needed = 0, epilogue_size_needed;
18078 int desired_align = 0, align_bytes = 0;
18079 enum stringop_alg alg;
18080 rtx promoted_val = NULL;
18081 bool force_loopy_epilogue = false;
18083 bool need_zero_guard = false;
18085 if (CONST_INT_P (align_exp))
18086 align = INTVAL (align_exp);
18087 /* i386 can do misaligned access on reasonably increased cost. */
18088 if (CONST_INT_P (expected_align_exp)
18089 && INTVAL (expected_align_exp) > align)
18090 align = INTVAL (expected_align_exp);
18091 if (CONST_INT_P (count_exp))
18092 count = expected_size = INTVAL (count_exp);
18093 if (CONST_INT_P (expected_size_exp) && count == 0)
18094 expected_size = INTVAL (expected_size_exp);
18096 /* Make sure we don't need to care about overflow later on. */
18097 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18100 /* Step 0: Decide on preferred algorithm, desired alignment and
18101 size of chunks to be copied by main loop. */
18103 alg = decide_alg (count, expected_size, true, &dynamic_check);
18104 desired_align = decide_alignment (align, alg, expected_size);
18106 if (!TARGET_ALIGN_STRINGOPS)
18107 align = desired_align;
18109 if (alg == libcall)
18111 gcc_assert (alg != no_stringop);
18113 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18114 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18119 gcc_unreachable ();
18121 need_zero_guard = true;
18122 size_needed = GET_MODE_SIZE (Pmode);
18124 case unrolled_loop:
18125 need_zero_guard = true;
18126 size_needed = GET_MODE_SIZE (Pmode) * 4;
18128 case rep_prefix_8_byte:
18131 case rep_prefix_4_byte:
18134 case rep_prefix_1_byte:
18138 need_zero_guard = true;
18142 epilogue_size_needed = size_needed;
18144 /* Step 1: Prologue guard. */
18146 /* Alignment code needs count to be in register. */
18147 if (CONST_INT_P (count_exp) && desired_align > align)
18149 if (INTVAL (count_exp) > desired_align
18150 && INTVAL (count_exp) > size_needed)
18153 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18154 if (align_bytes <= 0)
18157 align_bytes = desired_align - align_bytes;
18159 if (align_bytes == 0)
18161 enum machine_mode mode = SImode;
18162 if (TARGET_64BIT && (count & ~0xffffffff))
18164 count_exp = force_reg (mode, count_exp);
18167 /* Do the cheap promotion to allow better CSE across the
18168 main loop and epilogue (ie one load of the big constant in the
18169 front of all code. */
18170 if (CONST_INT_P (val_exp))
18171 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18172 desired_align, align);
18173 /* Ensure that alignment prologue won't copy past end of block. */
18174 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18176 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18177 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18178 Make sure it is power of 2. */
18179 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18181 /* To improve performance of small blocks, we jump around the VAL
18182 promoting mode. This mean that if the promoted VAL is not constant,
18183 we might not use it in the epilogue and have to use byte
18185 if (epilogue_size_needed > 2 && !promoted_val)
18186 force_loopy_epilogue = true;
18189 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18191 /* If main algorithm works on QImode, no epilogue is needed.
18192 For small sizes just don't align anything. */
18193 if (size_needed == 1)
18194 desired_align = align;
18201 label = gen_label_rtx ();
18202 emit_cmp_and_jump_insns (count_exp,
18203 GEN_INT (epilogue_size_needed),
18204 LTU, 0, counter_mode (count_exp), 1, label);
18205 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18206 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18208 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18211 if (dynamic_check != -1)
18213 rtx hot_label = gen_label_rtx ();
18214 jump_around_label = gen_label_rtx ();
18215 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18216 LEU, 0, counter_mode (count_exp), 1, hot_label);
18217 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18218 set_storage_via_libcall (dst, count_exp, val_exp, false);
18219 emit_jump (jump_around_label);
18220 emit_label (hot_label);
18223 /* Step 2: Alignment prologue. */
18225 /* Do the expensive promotion once we branched off the small blocks. */
18227 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18228 desired_align, align);
18229 gcc_assert (desired_align >= 1 && align >= 1);
18231 if (desired_align > align)
18233 if (align_bytes == 0)
18235 /* Except for the first move in epilogue, we no longer know
18236 constant offset in aliasing info. It don't seems to worth
18237 the pain to maintain it for the first move, so throw away
18239 dst = change_address (dst, BLKmode, destreg);
18240 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18245 /* If we know how many bytes need to be stored before dst is
18246 sufficiently aligned, maintain aliasing info accurately. */
18247 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18248 desired_align, align_bytes);
18249 count_exp = plus_constant (count_exp, -align_bytes);
18250 count -= align_bytes;
18252 if (need_zero_guard
18253 && (count < (unsigned HOST_WIDE_INT) size_needed
18254 || (align_bytes == 0
18255 && count < ((unsigned HOST_WIDE_INT) size_needed
18256 + desired_align - align))))
18258 /* It is possible that we copied enough so the main loop will not
18260 gcc_assert (size_needed > 1);
18261 if (label == NULL_RTX)
18262 label = gen_label_rtx ();
18263 emit_cmp_and_jump_insns (count_exp,
18264 GEN_INT (size_needed),
18265 LTU, 0, counter_mode (count_exp), 1, label);
18266 if (expected_size == -1
18267 || expected_size < (desired_align - align) / 2 + size_needed)
18268 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18270 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18273 if (label && size_needed == 1)
18275 emit_label (label);
18276 LABEL_NUSES (label) = 1;
18278 promoted_val = val_exp;
18279 epilogue_size_needed = 1;
18281 else if (label == NULL_RTX)
18282 epilogue_size_needed = size_needed;
18284 /* Step 3: Main loop. */
18290 gcc_unreachable ();
18292 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18293 count_exp, QImode, 1, expected_size);
18296 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18297 count_exp, Pmode, 1, expected_size);
18299 case unrolled_loop:
18300 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18301 count_exp, Pmode, 4, expected_size);
18303 case rep_prefix_8_byte:
18304 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18307 case rep_prefix_4_byte:
18308 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18311 case rep_prefix_1_byte:
18312 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18316 /* Adjust properly the offset of src and dest memory for aliasing. */
18317 if (CONST_INT_P (count_exp))
18318 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18319 (count / size_needed) * size_needed);
18321 dst = change_address (dst, BLKmode, destreg);
18323 /* Step 4: Epilogue to copy the remaining bytes. */
18327 /* When the main loop is done, COUNT_EXP might hold original count,
18328 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18329 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18330 bytes. Compensate if needed. */
18332 if (size_needed < epilogue_size_needed)
18335 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18336 GEN_INT (size_needed - 1), count_exp, 1,
18338 if (tmp != count_exp)
18339 emit_move_insn (count_exp, tmp);
18341 emit_label (label);
18342 LABEL_NUSES (label) = 1;
18345 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18347 if (force_loopy_epilogue)
18348 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18349 epilogue_size_needed);
18351 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18352 epilogue_size_needed);
18354 if (jump_around_label)
18355 emit_label (jump_around_label);
18359 /* Expand the appropriate insns for doing strlen if not just doing
18362 out = result, initialized with the start address
18363 align_rtx = alignment of the address.
18364 scratch = scratch register, initialized with the startaddress when
18365 not aligned, otherwise undefined
18367 This is just the body. It needs the initializations mentioned above and
18368 some address computing at the end. These things are done in i386.md. */
18371 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18375 rtx align_2_label = NULL_RTX;
18376 rtx align_3_label = NULL_RTX;
18377 rtx align_4_label = gen_label_rtx ();
18378 rtx end_0_label = gen_label_rtx ();
18380 rtx tmpreg = gen_reg_rtx (SImode);
18381 rtx scratch = gen_reg_rtx (SImode);
18385 if (CONST_INT_P (align_rtx))
18386 align = INTVAL (align_rtx);
18388 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18390 /* Is there a known alignment and is it less than 4? */
18393 rtx scratch1 = gen_reg_rtx (Pmode);
18394 emit_move_insn (scratch1, out);
18395 /* Is there a known alignment and is it not 2? */
18398 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18399 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18401 /* Leave just the 3 lower bits. */
18402 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18403 NULL_RTX, 0, OPTAB_WIDEN);
18405 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18406 Pmode, 1, align_4_label);
18407 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18408 Pmode, 1, align_2_label);
18409 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18410 Pmode, 1, align_3_label);
18414 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18415 check if is aligned to 4 - byte. */
18417 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18418 NULL_RTX, 0, OPTAB_WIDEN);
18420 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18421 Pmode, 1, align_4_label);
18424 mem = change_address (src, QImode, out);
18426 /* Now compare the bytes. */
18428 /* Compare the first n unaligned byte on a byte per byte basis. */
18429 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18430 QImode, 1, end_0_label);
18432 /* Increment the address. */
18433 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18435 /* Not needed with an alignment of 2 */
18438 emit_label (align_2_label);
18440 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18443 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18445 emit_label (align_3_label);
18448 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18451 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18454 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18455 align this loop. It gives only huge programs, but does not help to
18457 emit_label (align_4_label);
18459 mem = change_address (src, SImode, out);
18460 emit_move_insn (scratch, mem);
18461 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18463 /* This formula yields a nonzero result iff one of the bytes is zero.
18464 This saves three branches inside loop and many cycles. */
18466 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18467 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18468 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18469 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18470 gen_int_mode (0x80808080, SImode)));
18471 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18476 rtx reg = gen_reg_rtx (SImode);
18477 rtx reg2 = gen_reg_rtx (Pmode);
18478 emit_move_insn (reg, tmpreg);
18479 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18481 /* If zero is not in the first two bytes, move two bytes forward. */
18482 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18483 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18484 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18485 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18486 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18489 /* Emit lea manually to avoid clobbering of flags. */
18490 emit_insn (gen_rtx_SET (SImode, reg2,
18491 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18493 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18494 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18495 emit_insn (gen_rtx_SET (VOIDmode, out,
18496 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18503 rtx end_2_label = gen_label_rtx ();
18504 /* Is zero in the first two bytes? */
18506 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18507 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18508 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18509 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18510 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18512 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18513 JUMP_LABEL (tmp) = end_2_label;
18515 /* Not in the first two. Move two bytes forward. */
18516 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18517 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18519 emit_label (end_2_label);
18523 /* Avoid branch in fixing the byte. */
18524 tmpreg = gen_lowpart (QImode, tmpreg);
18525 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18526 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18527 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18529 emit_label (end_0_label);
18532 /* Expand strlen. */
18535 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18537 rtx addr, scratch1, scratch2, scratch3, scratch4;
18539 /* The generic case of strlen expander is long. Avoid it's
18540 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18542 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18543 && !TARGET_INLINE_ALL_STRINGOPS
18544 && !optimize_insn_for_size_p ()
18545 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18548 addr = force_reg (Pmode, XEXP (src, 0));
18549 scratch1 = gen_reg_rtx (Pmode);
18551 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18552 && !optimize_insn_for_size_p ())
18554 /* Well it seems that some optimizer does not combine a call like
18555 foo(strlen(bar), strlen(bar));
18556 when the move and the subtraction is done here. It does calculate
18557 the length just once when these instructions are done inside of
18558 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18559 often used and I use one fewer register for the lifetime of
18560 output_strlen_unroll() this is better. */
18562 emit_move_insn (out, addr);
18564 ix86_expand_strlensi_unroll_1 (out, src, align);
18566 /* strlensi_unroll_1 returns the address of the zero at the end of
18567 the string, like memchr(), so compute the length by subtracting
18568 the start address. */
18569 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18575 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18576 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18579 scratch2 = gen_reg_rtx (Pmode);
18580 scratch3 = gen_reg_rtx (Pmode);
18581 scratch4 = force_reg (Pmode, constm1_rtx);
18583 emit_move_insn (scratch3, addr);
18584 eoschar = force_reg (QImode, eoschar);
18586 src = replace_equiv_address_nv (src, scratch3);
18588 /* If .md starts supporting :P, this can be done in .md. */
18589 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18590 scratch4), UNSPEC_SCAS);
18591 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18592 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18593 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18598 /* For given symbol (function) construct code to compute address of it's PLT
18599 entry in large x86-64 PIC model. */
18601 construct_plt_address (rtx symbol)
18603 rtx tmp = gen_reg_rtx (Pmode);
18604 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18606 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18607 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18609 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18610 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18615 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18617 rtx pop, int sibcall)
18619 rtx use = NULL, call;
18620 enum calling_abi function_call_abi;
18622 if (callarg2 && INTVAL (callarg2) == -2)
18623 function_call_abi = MS_ABI;
18625 function_call_abi = SYSV_ABI;
18626 if (pop == const0_rtx)
18628 gcc_assert (!TARGET_64BIT || !pop);
18630 if (TARGET_MACHO && !TARGET_64BIT)
18633 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18634 fnaddr = machopic_indirect_call_target (fnaddr);
18639 /* Static functions and indirect calls don't need the pic register. */
18640 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18641 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18642 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18643 use_reg (&use, pic_offset_table_rtx);
18646 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18648 rtx al = gen_rtx_REG (QImode, AX_REG);
18649 emit_move_insn (al, callarg2);
18650 use_reg (&use, al);
18653 if (ix86_cmodel == CM_LARGE_PIC
18654 && GET_CODE (fnaddr) == MEM
18655 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18656 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18657 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18658 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
18660 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18661 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18663 if (sibcall && TARGET_64BIT
18664 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
18667 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18668 fnaddr = gen_rtx_REG (Pmode, R11_REG);
18669 emit_move_insn (fnaddr, addr);
18670 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18673 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18675 call = gen_rtx_SET (VOIDmode, retval, call);
18678 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18679 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18680 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18681 gcc_assert (ix86_cfun_abi () != MS_ABI || function_call_abi != SYSV_ABI);
18683 /* We need to represent that SI and DI registers are clobbered
18685 if (ix86_cfun_abi () == MS_ABI && function_call_abi == SYSV_ABI)
18687 static int clobbered_registers[] = {
18688 XMM6_REG, XMM7_REG, XMM8_REG,
18689 XMM9_REG, XMM10_REG, XMM11_REG,
18690 XMM12_REG, XMM13_REG, XMM14_REG,
18691 XMM15_REG, SI_REG, DI_REG
18694 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18695 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18696 UNSPEC_MS_TO_SYSV_CALL);
18700 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18701 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18704 (SSE_REGNO_P (clobbered_registers[i])
18706 clobbered_registers[i]));
18708 call = gen_rtx_PARALLEL (VOIDmode,
18709 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18713 call = emit_call_insn (call);
18715 CALL_INSN_FUNCTION_USAGE (call) = use;
18719 /* Clear stack slot assignments remembered from previous functions.
18720 This is called from INIT_EXPANDERS once before RTL is emitted for each
18723 static struct machine_function *
18724 ix86_init_machine_status (void)
18726 struct machine_function *f;
18728 f = GGC_CNEW (struct machine_function);
18729 f->use_fast_prologue_epilogue_nregs = -1;
18730 f->tls_descriptor_call_expanded_p = 0;
18731 f->call_abi = DEFAULT_ABI;
18736 /* Return a MEM corresponding to a stack slot with mode MODE.
18737 Allocate a new slot if necessary.
18739 The RTL for a function can have several slots available: N is
18740 which slot to use. */
18743 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18745 struct stack_local_entry *s;
18747 gcc_assert (n < MAX_386_STACK_LOCALS);
18749 /* Virtual slot is valid only before vregs are instantiated. */
18750 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18752 for (s = ix86_stack_locals; s; s = s->next)
18753 if (s->mode == mode && s->n == n)
18754 return copy_rtx (s->rtl);
18756 s = (struct stack_local_entry *)
18757 ggc_alloc (sizeof (struct stack_local_entry));
18760 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18762 s->next = ix86_stack_locals;
18763 ix86_stack_locals = s;
18767 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18769 static GTY(()) rtx ix86_tls_symbol;
18771 ix86_tls_get_addr (void)
18774 if (!ix86_tls_symbol)
18776 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18777 (TARGET_ANY_GNU_TLS
18779 ? "___tls_get_addr"
18780 : "__tls_get_addr");
18783 return ix86_tls_symbol;
18786 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18788 static GTY(()) rtx ix86_tls_module_base_symbol;
18790 ix86_tls_module_base (void)
18793 if (!ix86_tls_module_base_symbol)
18795 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18796 "_TLS_MODULE_BASE_");
18797 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18798 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18801 return ix86_tls_module_base_symbol;
18804 /* Calculate the length of the memory address in the instruction
18805 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18808 memory_address_length (rtx addr)
18810 struct ix86_address parts;
18811 rtx base, index, disp;
18815 if (GET_CODE (addr) == PRE_DEC
18816 || GET_CODE (addr) == POST_INC
18817 || GET_CODE (addr) == PRE_MODIFY
18818 || GET_CODE (addr) == POST_MODIFY)
18821 ok = ix86_decompose_address (addr, &parts);
18824 if (parts.base && GET_CODE (parts.base) == SUBREG)
18825 parts.base = SUBREG_REG (parts.base);
18826 if (parts.index && GET_CODE (parts.index) == SUBREG)
18827 parts.index = SUBREG_REG (parts.index);
18830 index = parts.index;
18835 - esp as the base always wants an index,
18836 - ebp as the base always wants a displacement. */
18838 /* Register Indirect. */
18839 if (base && !index && !disp)
18841 /* esp (for its index) and ebp (for its displacement) need
18842 the two-byte modrm form. */
18843 if (addr == stack_pointer_rtx
18844 || addr == arg_pointer_rtx
18845 || addr == frame_pointer_rtx
18846 || addr == hard_frame_pointer_rtx)
18850 /* Direct Addressing. */
18851 else if (disp && !base && !index)
18856 /* Find the length of the displacement constant. */
18859 if (base && satisfies_constraint_K (disp))
18864 /* ebp always wants a displacement. */
18865 else if (base == hard_frame_pointer_rtx)
18868 /* An index requires the two-byte modrm form.... */
18870 /* ...like esp, which always wants an index. */
18871 || base == stack_pointer_rtx
18872 || base == arg_pointer_rtx
18873 || base == frame_pointer_rtx)
18880 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18881 is set, expect that insn have 8bit immediate alternative. */
18883 ix86_attr_length_immediate_default (rtx insn, int shortform)
18887 extract_insn_cached (insn);
18888 for (i = recog_data.n_operands - 1; i >= 0; --i)
18889 if (CONSTANT_P (recog_data.operand[i]))
18892 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
18896 switch (get_attr_mode (insn))
18907 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18912 fatal_insn ("unknown insn mode", insn);
18918 /* Compute default value for "length_address" attribute. */
18920 ix86_attr_length_address_default (rtx insn)
18924 if (get_attr_type (insn) == TYPE_LEA)
18926 rtx set = PATTERN (insn);
18928 if (GET_CODE (set) == PARALLEL)
18929 set = XVECEXP (set, 0, 0);
18931 gcc_assert (GET_CODE (set) == SET);
18933 return memory_address_length (SET_SRC (set));
18936 extract_insn_cached (insn);
18937 for (i = recog_data.n_operands - 1; i >= 0; --i)
18938 if (MEM_P (recog_data.operand[i]))
18940 return memory_address_length (XEXP (recog_data.operand[i], 0));
18946 /* Compute default value for "length_vex" attribute. It includes
18947 2 or 3 byte VEX prefix and 1 opcode byte. */
18950 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
18955 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18956 byte VEX prefix. */
18957 if (!has_0f_opcode || has_vex_w)
18960 /* We can always use 2 byte VEX prefix in 32bit. */
18964 extract_insn_cached (insn);
18966 for (i = recog_data.n_operands - 1; i >= 0; --i)
18967 if (REG_P (recog_data.operand[i]))
18969 /* REX.W bit uses 3 byte VEX prefix. */
18970 if (GET_MODE (recog_data.operand[i]) == DImode)
18975 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18976 if (MEM_P (recog_data.operand[i])
18977 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
18984 /* Return the maximum number of instructions a cpu can issue. */
18987 ix86_issue_rate (void)
18991 case PROCESSOR_PENTIUM:
18995 case PROCESSOR_PENTIUMPRO:
18996 case PROCESSOR_PENTIUM4:
18997 case PROCESSOR_ATHLON:
18999 case PROCESSOR_AMDFAM10:
19000 case PROCESSOR_NOCONA:
19001 case PROCESSOR_GENERIC32:
19002 case PROCESSOR_GENERIC64:
19005 case PROCESSOR_CORE2:
19013 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19014 by DEP_INSN and nothing set by DEP_INSN. */
19017 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19021 /* Simplify the test for uninteresting insns. */
19022 if (insn_type != TYPE_SETCC
19023 && insn_type != TYPE_ICMOV
19024 && insn_type != TYPE_FCMOV
19025 && insn_type != TYPE_IBR)
19028 if ((set = single_set (dep_insn)) != 0)
19030 set = SET_DEST (set);
19033 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19034 && XVECLEN (PATTERN (dep_insn), 0) == 2
19035 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19036 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19038 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19039 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19044 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19047 /* This test is true if the dependent insn reads the flags but
19048 not any other potentially set register. */
19049 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19052 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19058 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19059 address with operands set by DEP_INSN. */
19062 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19066 if (insn_type == TYPE_LEA
19069 addr = PATTERN (insn);
19071 if (GET_CODE (addr) == PARALLEL)
19072 addr = XVECEXP (addr, 0, 0);
19074 gcc_assert (GET_CODE (addr) == SET);
19076 addr = SET_SRC (addr);
19081 extract_insn_cached (insn);
19082 for (i = recog_data.n_operands - 1; i >= 0; --i)
19083 if (MEM_P (recog_data.operand[i]))
19085 addr = XEXP (recog_data.operand[i], 0);
19092 return modified_in_p (addr, dep_insn);
19096 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19098 enum attr_type insn_type, dep_insn_type;
19099 enum attr_memory memory;
19101 int dep_insn_code_number;
19103 /* Anti and output dependencies have zero cost on all CPUs. */
19104 if (REG_NOTE_KIND (link) != 0)
19107 dep_insn_code_number = recog_memoized (dep_insn);
19109 /* If we can't recognize the insns, we can't really do anything. */
19110 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19113 insn_type = get_attr_type (insn);
19114 dep_insn_type = get_attr_type (dep_insn);
19118 case PROCESSOR_PENTIUM:
19119 /* Address Generation Interlock adds a cycle of latency. */
19120 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19123 /* ??? Compares pair with jump/setcc. */
19124 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19127 /* Floating point stores require value to be ready one cycle earlier. */
19128 if (insn_type == TYPE_FMOV
19129 && get_attr_memory (insn) == MEMORY_STORE
19130 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19134 case PROCESSOR_PENTIUMPRO:
19135 memory = get_attr_memory (insn);
19137 /* INT->FP conversion is expensive. */
19138 if (get_attr_fp_int_src (dep_insn))
19141 /* There is one cycle extra latency between an FP op and a store. */
19142 if (insn_type == TYPE_FMOV
19143 && (set = single_set (dep_insn)) != NULL_RTX
19144 && (set2 = single_set (insn)) != NULL_RTX
19145 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19146 && MEM_P (SET_DEST (set2)))
19149 /* Show ability of reorder buffer to hide latency of load by executing
19150 in parallel with previous instruction in case
19151 previous instruction is not needed to compute the address. */
19152 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19153 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19155 /* Claim moves to take one cycle, as core can issue one load
19156 at time and the next load can start cycle later. */
19157 if (dep_insn_type == TYPE_IMOV
19158 || dep_insn_type == TYPE_FMOV)
19166 memory = get_attr_memory (insn);
19168 /* The esp dependency is resolved before the instruction is really
19170 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19171 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19174 /* INT->FP conversion is expensive. */
19175 if (get_attr_fp_int_src (dep_insn))
19178 /* Show ability of reorder buffer to hide latency of load by executing
19179 in parallel with previous instruction in case
19180 previous instruction is not needed to compute the address. */
19181 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19182 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19184 /* Claim moves to take one cycle, as core can issue one load
19185 at time and the next load can start cycle later. */
19186 if (dep_insn_type == TYPE_IMOV
19187 || dep_insn_type == TYPE_FMOV)
19196 case PROCESSOR_ATHLON:
19198 case PROCESSOR_AMDFAM10:
19199 case PROCESSOR_GENERIC32:
19200 case PROCESSOR_GENERIC64:
19201 memory = get_attr_memory (insn);
19203 /* Show ability of reorder buffer to hide latency of load by executing
19204 in parallel with previous instruction in case
19205 previous instruction is not needed to compute the address. */
19206 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19207 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19209 enum attr_unit unit = get_attr_unit (insn);
19212 /* Because of the difference between the length of integer and
19213 floating unit pipeline preparation stages, the memory operands
19214 for floating point are cheaper.
19216 ??? For Athlon it the difference is most probably 2. */
19217 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19220 loadcost = TARGET_ATHLON ? 2 : 0;
19222 if (cost >= loadcost)
19235 /* How many alternative schedules to try. This should be as wide as the
19236 scheduling freedom in the DFA, but no wider. Making this value too
19237 large results extra work for the scheduler. */
19240 ia32_multipass_dfa_lookahead (void)
19244 case PROCESSOR_PENTIUM:
19247 case PROCESSOR_PENTIUMPRO:
19257 /* Compute the alignment given to a constant that is being placed in memory.
19258 EXP is the constant and ALIGN is the alignment that the object would
19260 The value of this function is used instead of that alignment to align
19264 ix86_constant_alignment (tree exp, int align)
19266 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19267 || TREE_CODE (exp) == INTEGER_CST)
19269 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19271 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19274 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19275 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19276 return BITS_PER_WORD;
19281 /* Compute the alignment for a static variable.
19282 TYPE is the data type, and ALIGN is the alignment that
19283 the object would ordinarily have. The value of this function is used
19284 instead of that alignment to align the object. */
19287 ix86_data_alignment (tree type, int align)
19289 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19291 if (AGGREGATE_TYPE_P (type)
19292 && TYPE_SIZE (type)
19293 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19294 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19295 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19296 && align < max_align)
19299 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19300 to 16byte boundary. */
19303 if (AGGREGATE_TYPE_P (type)
19304 && TYPE_SIZE (type)
19305 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19306 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19307 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19311 if (TREE_CODE (type) == ARRAY_TYPE)
19313 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19315 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19318 else if (TREE_CODE (type) == COMPLEX_TYPE)
19321 if (TYPE_MODE (type) == DCmode && align < 64)
19323 if ((TYPE_MODE (type) == XCmode
19324 || TYPE_MODE (type) == TCmode) && align < 128)
19327 else if ((TREE_CODE (type) == RECORD_TYPE
19328 || TREE_CODE (type) == UNION_TYPE
19329 || TREE_CODE (type) == QUAL_UNION_TYPE)
19330 && TYPE_FIELDS (type))
19332 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19334 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19337 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19338 || TREE_CODE (type) == INTEGER_TYPE)
19340 if (TYPE_MODE (type) == DFmode && align < 64)
19342 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19349 /* Compute the alignment for a local variable or a stack slot. EXP is
19350 the data type or decl itself, MODE is the widest mode available and
19351 ALIGN is the alignment that the object would ordinarily have. The
19352 value of this macro is used instead of that alignment to align the
19356 ix86_local_alignment (tree exp, enum machine_mode mode,
19357 unsigned int align)
19361 if (exp && DECL_P (exp))
19363 type = TREE_TYPE (exp);
19372 /* Don't do dynamic stack realignment for long long objects with
19373 -mpreferred-stack-boundary=2. */
19376 && ix86_preferred_stack_boundary < 64
19377 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19378 && (!type || !TYPE_USER_ALIGN (type))
19379 && (!decl || !DECL_USER_ALIGN (decl)))
19382 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19383 register in MODE. We will return the largest alignment of XF
19387 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19388 align = GET_MODE_ALIGNMENT (DFmode);
19392 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19393 to 16byte boundary. */
19396 if (AGGREGATE_TYPE_P (type)
19397 && TYPE_SIZE (type)
19398 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19399 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19400 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19403 if (TREE_CODE (type) == ARRAY_TYPE)
19405 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19407 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19410 else if (TREE_CODE (type) == COMPLEX_TYPE)
19412 if (TYPE_MODE (type) == DCmode && align < 64)
19414 if ((TYPE_MODE (type) == XCmode
19415 || TYPE_MODE (type) == TCmode) && align < 128)
19418 else if ((TREE_CODE (type) == RECORD_TYPE
19419 || TREE_CODE (type) == UNION_TYPE
19420 || TREE_CODE (type) == QUAL_UNION_TYPE)
19421 && TYPE_FIELDS (type))
19423 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19425 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19428 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19429 || TREE_CODE (type) == INTEGER_TYPE)
19432 if (TYPE_MODE (type) == DFmode && align < 64)
19434 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19440 /* Emit RTL insns to initialize the variable parts of a trampoline.
19441 FNADDR is an RTX for the address of the function's pure code.
19442 CXT is an RTX for the static chain value for the function. */
19444 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19448 /* Compute offset from the end of the jmp to the target function. */
19449 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19450 plus_constant (tramp, 10),
19451 NULL_RTX, 1, OPTAB_DIRECT);
19452 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19453 gen_int_mode (0xb9, QImode));
19454 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19455 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19456 gen_int_mode (0xe9, QImode));
19457 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19462 /* Try to load address using shorter movl instead of movabs.
19463 We may want to support movq for kernel mode, but kernel does not use
19464 trampolines at the moment. */
19465 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19467 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19468 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19469 gen_int_mode (0xbb41, HImode));
19470 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19471 gen_lowpart (SImode, fnaddr));
19476 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19477 gen_int_mode (0xbb49, HImode));
19478 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19482 /* Load static chain using movabs to r10. */
19483 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19484 gen_int_mode (0xba49, HImode));
19485 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19488 /* Jump to the r11 */
19489 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19490 gen_int_mode (0xff49, HImode));
19491 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19492 gen_int_mode (0xe3, QImode));
19494 gcc_assert (offset <= TRAMPOLINE_SIZE);
19497 #ifdef ENABLE_EXECUTE_STACK
19498 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19499 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19503 /* Codes for all the SSE/MMX builtins. */
19506 IX86_BUILTIN_ADDPS,
19507 IX86_BUILTIN_ADDSS,
19508 IX86_BUILTIN_DIVPS,
19509 IX86_BUILTIN_DIVSS,
19510 IX86_BUILTIN_MULPS,
19511 IX86_BUILTIN_MULSS,
19512 IX86_BUILTIN_SUBPS,
19513 IX86_BUILTIN_SUBSS,
19515 IX86_BUILTIN_CMPEQPS,
19516 IX86_BUILTIN_CMPLTPS,
19517 IX86_BUILTIN_CMPLEPS,
19518 IX86_BUILTIN_CMPGTPS,
19519 IX86_BUILTIN_CMPGEPS,
19520 IX86_BUILTIN_CMPNEQPS,
19521 IX86_BUILTIN_CMPNLTPS,
19522 IX86_BUILTIN_CMPNLEPS,
19523 IX86_BUILTIN_CMPNGTPS,
19524 IX86_BUILTIN_CMPNGEPS,
19525 IX86_BUILTIN_CMPORDPS,
19526 IX86_BUILTIN_CMPUNORDPS,
19527 IX86_BUILTIN_CMPEQSS,
19528 IX86_BUILTIN_CMPLTSS,
19529 IX86_BUILTIN_CMPLESS,
19530 IX86_BUILTIN_CMPNEQSS,
19531 IX86_BUILTIN_CMPNLTSS,
19532 IX86_BUILTIN_CMPNLESS,
19533 IX86_BUILTIN_CMPNGTSS,
19534 IX86_BUILTIN_CMPNGESS,
19535 IX86_BUILTIN_CMPORDSS,
19536 IX86_BUILTIN_CMPUNORDSS,
19538 IX86_BUILTIN_COMIEQSS,
19539 IX86_BUILTIN_COMILTSS,
19540 IX86_BUILTIN_COMILESS,
19541 IX86_BUILTIN_COMIGTSS,
19542 IX86_BUILTIN_COMIGESS,
19543 IX86_BUILTIN_COMINEQSS,
19544 IX86_BUILTIN_UCOMIEQSS,
19545 IX86_BUILTIN_UCOMILTSS,
19546 IX86_BUILTIN_UCOMILESS,
19547 IX86_BUILTIN_UCOMIGTSS,
19548 IX86_BUILTIN_UCOMIGESS,
19549 IX86_BUILTIN_UCOMINEQSS,
19551 IX86_BUILTIN_CVTPI2PS,
19552 IX86_BUILTIN_CVTPS2PI,
19553 IX86_BUILTIN_CVTSI2SS,
19554 IX86_BUILTIN_CVTSI642SS,
19555 IX86_BUILTIN_CVTSS2SI,
19556 IX86_BUILTIN_CVTSS2SI64,
19557 IX86_BUILTIN_CVTTPS2PI,
19558 IX86_BUILTIN_CVTTSS2SI,
19559 IX86_BUILTIN_CVTTSS2SI64,
19561 IX86_BUILTIN_MAXPS,
19562 IX86_BUILTIN_MAXSS,
19563 IX86_BUILTIN_MINPS,
19564 IX86_BUILTIN_MINSS,
19566 IX86_BUILTIN_LOADUPS,
19567 IX86_BUILTIN_STOREUPS,
19568 IX86_BUILTIN_MOVSS,
19570 IX86_BUILTIN_MOVHLPS,
19571 IX86_BUILTIN_MOVLHPS,
19572 IX86_BUILTIN_LOADHPS,
19573 IX86_BUILTIN_LOADLPS,
19574 IX86_BUILTIN_STOREHPS,
19575 IX86_BUILTIN_STORELPS,
19577 IX86_BUILTIN_MASKMOVQ,
19578 IX86_BUILTIN_MOVMSKPS,
19579 IX86_BUILTIN_PMOVMSKB,
19581 IX86_BUILTIN_MOVNTPS,
19582 IX86_BUILTIN_MOVNTQ,
19584 IX86_BUILTIN_LOADDQU,
19585 IX86_BUILTIN_STOREDQU,
19587 IX86_BUILTIN_PACKSSWB,
19588 IX86_BUILTIN_PACKSSDW,
19589 IX86_BUILTIN_PACKUSWB,
19591 IX86_BUILTIN_PADDB,
19592 IX86_BUILTIN_PADDW,
19593 IX86_BUILTIN_PADDD,
19594 IX86_BUILTIN_PADDQ,
19595 IX86_BUILTIN_PADDSB,
19596 IX86_BUILTIN_PADDSW,
19597 IX86_BUILTIN_PADDUSB,
19598 IX86_BUILTIN_PADDUSW,
19599 IX86_BUILTIN_PSUBB,
19600 IX86_BUILTIN_PSUBW,
19601 IX86_BUILTIN_PSUBD,
19602 IX86_BUILTIN_PSUBQ,
19603 IX86_BUILTIN_PSUBSB,
19604 IX86_BUILTIN_PSUBSW,
19605 IX86_BUILTIN_PSUBUSB,
19606 IX86_BUILTIN_PSUBUSW,
19609 IX86_BUILTIN_PANDN,
19613 IX86_BUILTIN_PAVGB,
19614 IX86_BUILTIN_PAVGW,
19616 IX86_BUILTIN_PCMPEQB,
19617 IX86_BUILTIN_PCMPEQW,
19618 IX86_BUILTIN_PCMPEQD,
19619 IX86_BUILTIN_PCMPGTB,
19620 IX86_BUILTIN_PCMPGTW,
19621 IX86_BUILTIN_PCMPGTD,
19623 IX86_BUILTIN_PMADDWD,
19625 IX86_BUILTIN_PMAXSW,
19626 IX86_BUILTIN_PMAXUB,
19627 IX86_BUILTIN_PMINSW,
19628 IX86_BUILTIN_PMINUB,
19630 IX86_BUILTIN_PMULHUW,
19631 IX86_BUILTIN_PMULHW,
19632 IX86_BUILTIN_PMULLW,
19634 IX86_BUILTIN_PSADBW,
19635 IX86_BUILTIN_PSHUFW,
19637 IX86_BUILTIN_PSLLW,
19638 IX86_BUILTIN_PSLLD,
19639 IX86_BUILTIN_PSLLQ,
19640 IX86_BUILTIN_PSRAW,
19641 IX86_BUILTIN_PSRAD,
19642 IX86_BUILTIN_PSRLW,
19643 IX86_BUILTIN_PSRLD,
19644 IX86_BUILTIN_PSRLQ,
19645 IX86_BUILTIN_PSLLWI,
19646 IX86_BUILTIN_PSLLDI,
19647 IX86_BUILTIN_PSLLQI,
19648 IX86_BUILTIN_PSRAWI,
19649 IX86_BUILTIN_PSRADI,
19650 IX86_BUILTIN_PSRLWI,
19651 IX86_BUILTIN_PSRLDI,
19652 IX86_BUILTIN_PSRLQI,
19654 IX86_BUILTIN_PUNPCKHBW,
19655 IX86_BUILTIN_PUNPCKHWD,
19656 IX86_BUILTIN_PUNPCKHDQ,
19657 IX86_BUILTIN_PUNPCKLBW,
19658 IX86_BUILTIN_PUNPCKLWD,
19659 IX86_BUILTIN_PUNPCKLDQ,
19661 IX86_BUILTIN_SHUFPS,
19663 IX86_BUILTIN_RCPPS,
19664 IX86_BUILTIN_RCPSS,
19665 IX86_BUILTIN_RSQRTPS,
19666 IX86_BUILTIN_RSQRTPS_NR,
19667 IX86_BUILTIN_RSQRTSS,
19668 IX86_BUILTIN_RSQRTF,
19669 IX86_BUILTIN_SQRTPS,
19670 IX86_BUILTIN_SQRTPS_NR,
19671 IX86_BUILTIN_SQRTSS,
19673 IX86_BUILTIN_UNPCKHPS,
19674 IX86_BUILTIN_UNPCKLPS,
19676 IX86_BUILTIN_ANDPS,
19677 IX86_BUILTIN_ANDNPS,
19679 IX86_BUILTIN_XORPS,
19682 IX86_BUILTIN_LDMXCSR,
19683 IX86_BUILTIN_STMXCSR,
19684 IX86_BUILTIN_SFENCE,
19686 /* 3DNow! Original */
19687 IX86_BUILTIN_FEMMS,
19688 IX86_BUILTIN_PAVGUSB,
19689 IX86_BUILTIN_PF2ID,
19690 IX86_BUILTIN_PFACC,
19691 IX86_BUILTIN_PFADD,
19692 IX86_BUILTIN_PFCMPEQ,
19693 IX86_BUILTIN_PFCMPGE,
19694 IX86_BUILTIN_PFCMPGT,
19695 IX86_BUILTIN_PFMAX,
19696 IX86_BUILTIN_PFMIN,
19697 IX86_BUILTIN_PFMUL,
19698 IX86_BUILTIN_PFRCP,
19699 IX86_BUILTIN_PFRCPIT1,
19700 IX86_BUILTIN_PFRCPIT2,
19701 IX86_BUILTIN_PFRSQIT1,
19702 IX86_BUILTIN_PFRSQRT,
19703 IX86_BUILTIN_PFSUB,
19704 IX86_BUILTIN_PFSUBR,
19705 IX86_BUILTIN_PI2FD,
19706 IX86_BUILTIN_PMULHRW,
19708 /* 3DNow! Athlon Extensions */
19709 IX86_BUILTIN_PF2IW,
19710 IX86_BUILTIN_PFNACC,
19711 IX86_BUILTIN_PFPNACC,
19712 IX86_BUILTIN_PI2FW,
19713 IX86_BUILTIN_PSWAPDSI,
19714 IX86_BUILTIN_PSWAPDSF,
19717 IX86_BUILTIN_ADDPD,
19718 IX86_BUILTIN_ADDSD,
19719 IX86_BUILTIN_DIVPD,
19720 IX86_BUILTIN_DIVSD,
19721 IX86_BUILTIN_MULPD,
19722 IX86_BUILTIN_MULSD,
19723 IX86_BUILTIN_SUBPD,
19724 IX86_BUILTIN_SUBSD,
19726 IX86_BUILTIN_CMPEQPD,
19727 IX86_BUILTIN_CMPLTPD,
19728 IX86_BUILTIN_CMPLEPD,
19729 IX86_BUILTIN_CMPGTPD,
19730 IX86_BUILTIN_CMPGEPD,
19731 IX86_BUILTIN_CMPNEQPD,
19732 IX86_BUILTIN_CMPNLTPD,
19733 IX86_BUILTIN_CMPNLEPD,
19734 IX86_BUILTIN_CMPNGTPD,
19735 IX86_BUILTIN_CMPNGEPD,
19736 IX86_BUILTIN_CMPORDPD,
19737 IX86_BUILTIN_CMPUNORDPD,
19738 IX86_BUILTIN_CMPEQSD,
19739 IX86_BUILTIN_CMPLTSD,
19740 IX86_BUILTIN_CMPLESD,
19741 IX86_BUILTIN_CMPNEQSD,
19742 IX86_BUILTIN_CMPNLTSD,
19743 IX86_BUILTIN_CMPNLESD,
19744 IX86_BUILTIN_CMPORDSD,
19745 IX86_BUILTIN_CMPUNORDSD,
19747 IX86_BUILTIN_COMIEQSD,
19748 IX86_BUILTIN_COMILTSD,
19749 IX86_BUILTIN_COMILESD,
19750 IX86_BUILTIN_COMIGTSD,
19751 IX86_BUILTIN_COMIGESD,
19752 IX86_BUILTIN_COMINEQSD,
19753 IX86_BUILTIN_UCOMIEQSD,
19754 IX86_BUILTIN_UCOMILTSD,
19755 IX86_BUILTIN_UCOMILESD,
19756 IX86_BUILTIN_UCOMIGTSD,
19757 IX86_BUILTIN_UCOMIGESD,
19758 IX86_BUILTIN_UCOMINEQSD,
19760 IX86_BUILTIN_MAXPD,
19761 IX86_BUILTIN_MAXSD,
19762 IX86_BUILTIN_MINPD,
19763 IX86_BUILTIN_MINSD,
19765 IX86_BUILTIN_ANDPD,
19766 IX86_BUILTIN_ANDNPD,
19768 IX86_BUILTIN_XORPD,
19770 IX86_BUILTIN_SQRTPD,
19771 IX86_BUILTIN_SQRTSD,
19773 IX86_BUILTIN_UNPCKHPD,
19774 IX86_BUILTIN_UNPCKLPD,
19776 IX86_BUILTIN_SHUFPD,
19778 IX86_BUILTIN_LOADUPD,
19779 IX86_BUILTIN_STOREUPD,
19780 IX86_BUILTIN_MOVSD,
19782 IX86_BUILTIN_LOADHPD,
19783 IX86_BUILTIN_LOADLPD,
19785 IX86_BUILTIN_CVTDQ2PD,
19786 IX86_BUILTIN_CVTDQ2PS,
19788 IX86_BUILTIN_CVTPD2DQ,
19789 IX86_BUILTIN_CVTPD2PI,
19790 IX86_BUILTIN_CVTPD2PS,
19791 IX86_BUILTIN_CVTTPD2DQ,
19792 IX86_BUILTIN_CVTTPD2PI,
19794 IX86_BUILTIN_CVTPI2PD,
19795 IX86_BUILTIN_CVTSI2SD,
19796 IX86_BUILTIN_CVTSI642SD,
19798 IX86_BUILTIN_CVTSD2SI,
19799 IX86_BUILTIN_CVTSD2SI64,
19800 IX86_BUILTIN_CVTSD2SS,
19801 IX86_BUILTIN_CVTSS2SD,
19802 IX86_BUILTIN_CVTTSD2SI,
19803 IX86_BUILTIN_CVTTSD2SI64,
19805 IX86_BUILTIN_CVTPS2DQ,
19806 IX86_BUILTIN_CVTPS2PD,
19807 IX86_BUILTIN_CVTTPS2DQ,
19809 IX86_BUILTIN_MOVNTI,
19810 IX86_BUILTIN_MOVNTPD,
19811 IX86_BUILTIN_MOVNTDQ,
19813 IX86_BUILTIN_MOVQ128,
19816 IX86_BUILTIN_MASKMOVDQU,
19817 IX86_BUILTIN_MOVMSKPD,
19818 IX86_BUILTIN_PMOVMSKB128,
19820 IX86_BUILTIN_PACKSSWB128,
19821 IX86_BUILTIN_PACKSSDW128,
19822 IX86_BUILTIN_PACKUSWB128,
19824 IX86_BUILTIN_PADDB128,
19825 IX86_BUILTIN_PADDW128,
19826 IX86_BUILTIN_PADDD128,
19827 IX86_BUILTIN_PADDQ128,
19828 IX86_BUILTIN_PADDSB128,
19829 IX86_BUILTIN_PADDSW128,
19830 IX86_BUILTIN_PADDUSB128,
19831 IX86_BUILTIN_PADDUSW128,
19832 IX86_BUILTIN_PSUBB128,
19833 IX86_BUILTIN_PSUBW128,
19834 IX86_BUILTIN_PSUBD128,
19835 IX86_BUILTIN_PSUBQ128,
19836 IX86_BUILTIN_PSUBSB128,
19837 IX86_BUILTIN_PSUBSW128,
19838 IX86_BUILTIN_PSUBUSB128,
19839 IX86_BUILTIN_PSUBUSW128,
19841 IX86_BUILTIN_PAND128,
19842 IX86_BUILTIN_PANDN128,
19843 IX86_BUILTIN_POR128,
19844 IX86_BUILTIN_PXOR128,
19846 IX86_BUILTIN_PAVGB128,
19847 IX86_BUILTIN_PAVGW128,
19849 IX86_BUILTIN_PCMPEQB128,
19850 IX86_BUILTIN_PCMPEQW128,
19851 IX86_BUILTIN_PCMPEQD128,
19852 IX86_BUILTIN_PCMPGTB128,
19853 IX86_BUILTIN_PCMPGTW128,
19854 IX86_BUILTIN_PCMPGTD128,
19856 IX86_BUILTIN_PMADDWD128,
19858 IX86_BUILTIN_PMAXSW128,
19859 IX86_BUILTIN_PMAXUB128,
19860 IX86_BUILTIN_PMINSW128,
19861 IX86_BUILTIN_PMINUB128,
19863 IX86_BUILTIN_PMULUDQ,
19864 IX86_BUILTIN_PMULUDQ128,
19865 IX86_BUILTIN_PMULHUW128,
19866 IX86_BUILTIN_PMULHW128,
19867 IX86_BUILTIN_PMULLW128,
19869 IX86_BUILTIN_PSADBW128,
19870 IX86_BUILTIN_PSHUFHW,
19871 IX86_BUILTIN_PSHUFLW,
19872 IX86_BUILTIN_PSHUFD,
19874 IX86_BUILTIN_PSLLDQI128,
19875 IX86_BUILTIN_PSLLWI128,
19876 IX86_BUILTIN_PSLLDI128,
19877 IX86_BUILTIN_PSLLQI128,
19878 IX86_BUILTIN_PSRAWI128,
19879 IX86_BUILTIN_PSRADI128,
19880 IX86_BUILTIN_PSRLDQI128,
19881 IX86_BUILTIN_PSRLWI128,
19882 IX86_BUILTIN_PSRLDI128,
19883 IX86_BUILTIN_PSRLQI128,
19885 IX86_BUILTIN_PSLLDQ128,
19886 IX86_BUILTIN_PSLLW128,
19887 IX86_BUILTIN_PSLLD128,
19888 IX86_BUILTIN_PSLLQ128,
19889 IX86_BUILTIN_PSRAW128,
19890 IX86_BUILTIN_PSRAD128,
19891 IX86_BUILTIN_PSRLW128,
19892 IX86_BUILTIN_PSRLD128,
19893 IX86_BUILTIN_PSRLQ128,
19895 IX86_BUILTIN_PUNPCKHBW128,
19896 IX86_BUILTIN_PUNPCKHWD128,
19897 IX86_BUILTIN_PUNPCKHDQ128,
19898 IX86_BUILTIN_PUNPCKHQDQ128,
19899 IX86_BUILTIN_PUNPCKLBW128,
19900 IX86_BUILTIN_PUNPCKLWD128,
19901 IX86_BUILTIN_PUNPCKLDQ128,
19902 IX86_BUILTIN_PUNPCKLQDQ128,
19904 IX86_BUILTIN_CLFLUSH,
19905 IX86_BUILTIN_MFENCE,
19906 IX86_BUILTIN_LFENCE,
19909 IX86_BUILTIN_ADDSUBPS,
19910 IX86_BUILTIN_HADDPS,
19911 IX86_BUILTIN_HSUBPS,
19912 IX86_BUILTIN_MOVSHDUP,
19913 IX86_BUILTIN_MOVSLDUP,
19914 IX86_BUILTIN_ADDSUBPD,
19915 IX86_BUILTIN_HADDPD,
19916 IX86_BUILTIN_HSUBPD,
19917 IX86_BUILTIN_LDDQU,
19919 IX86_BUILTIN_MONITOR,
19920 IX86_BUILTIN_MWAIT,
19923 IX86_BUILTIN_PHADDW,
19924 IX86_BUILTIN_PHADDD,
19925 IX86_BUILTIN_PHADDSW,
19926 IX86_BUILTIN_PHSUBW,
19927 IX86_BUILTIN_PHSUBD,
19928 IX86_BUILTIN_PHSUBSW,
19929 IX86_BUILTIN_PMADDUBSW,
19930 IX86_BUILTIN_PMULHRSW,
19931 IX86_BUILTIN_PSHUFB,
19932 IX86_BUILTIN_PSIGNB,
19933 IX86_BUILTIN_PSIGNW,
19934 IX86_BUILTIN_PSIGND,
19935 IX86_BUILTIN_PALIGNR,
19936 IX86_BUILTIN_PABSB,
19937 IX86_BUILTIN_PABSW,
19938 IX86_BUILTIN_PABSD,
19940 IX86_BUILTIN_PHADDW128,
19941 IX86_BUILTIN_PHADDD128,
19942 IX86_BUILTIN_PHADDSW128,
19943 IX86_BUILTIN_PHSUBW128,
19944 IX86_BUILTIN_PHSUBD128,
19945 IX86_BUILTIN_PHSUBSW128,
19946 IX86_BUILTIN_PMADDUBSW128,
19947 IX86_BUILTIN_PMULHRSW128,
19948 IX86_BUILTIN_PSHUFB128,
19949 IX86_BUILTIN_PSIGNB128,
19950 IX86_BUILTIN_PSIGNW128,
19951 IX86_BUILTIN_PSIGND128,
19952 IX86_BUILTIN_PALIGNR128,
19953 IX86_BUILTIN_PABSB128,
19954 IX86_BUILTIN_PABSW128,
19955 IX86_BUILTIN_PABSD128,
19957 /* AMDFAM10 - SSE4A New Instructions. */
19958 IX86_BUILTIN_MOVNTSD,
19959 IX86_BUILTIN_MOVNTSS,
19960 IX86_BUILTIN_EXTRQI,
19961 IX86_BUILTIN_EXTRQ,
19962 IX86_BUILTIN_INSERTQI,
19963 IX86_BUILTIN_INSERTQ,
19966 IX86_BUILTIN_BLENDPD,
19967 IX86_BUILTIN_BLENDPS,
19968 IX86_BUILTIN_BLENDVPD,
19969 IX86_BUILTIN_BLENDVPS,
19970 IX86_BUILTIN_PBLENDVB128,
19971 IX86_BUILTIN_PBLENDW128,
19976 IX86_BUILTIN_INSERTPS128,
19978 IX86_BUILTIN_MOVNTDQA,
19979 IX86_BUILTIN_MPSADBW128,
19980 IX86_BUILTIN_PACKUSDW128,
19981 IX86_BUILTIN_PCMPEQQ,
19982 IX86_BUILTIN_PHMINPOSUW128,
19984 IX86_BUILTIN_PMAXSB128,
19985 IX86_BUILTIN_PMAXSD128,
19986 IX86_BUILTIN_PMAXUD128,
19987 IX86_BUILTIN_PMAXUW128,
19989 IX86_BUILTIN_PMINSB128,
19990 IX86_BUILTIN_PMINSD128,
19991 IX86_BUILTIN_PMINUD128,
19992 IX86_BUILTIN_PMINUW128,
19994 IX86_BUILTIN_PMOVSXBW128,
19995 IX86_BUILTIN_PMOVSXBD128,
19996 IX86_BUILTIN_PMOVSXBQ128,
19997 IX86_BUILTIN_PMOVSXWD128,
19998 IX86_BUILTIN_PMOVSXWQ128,
19999 IX86_BUILTIN_PMOVSXDQ128,
20001 IX86_BUILTIN_PMOVZXBW128,
20002 IX86_BUILTIN_PMOVZXBD128,
20003 IX86_BUILTIN_PMOVZXBQ128,
20004 IX86_BUILTIN_PMOVZXWD128,
20005 IX86_BUILTIN_PMOVZXWQ128,
20006 IX86_BUILTIN_PMOVZXDQ128,
20008 IX86_BUILTIN_PMULDQ128,
20009 IX86_BUILTIN_PMULLD128,
20011 IX86_BUILTIN_ROUNDPD,
20012 IX86_BUILTIN_ROUNDPS,
20013 IX86_BUILTIN_ROUNDSD,
20014 IX86_BUILTIN_ROUNDSS,
20016 IX86_BUILTIN_PTESTZ,
20017 IX86_BUILTIN_PTESTC,
20018 IX86_BUILTIN_PTESTNZC,
20020 IX86_BUILTIN_VEC_INIT_V2SI,
20021 IX86_BUILTIN_VEC_INIT_V4HI,
20022 IX86_BUILTIN_VEC_INIT_V8QI,
20023 IX86_BUILTIN_VEC_EXT_V2DF,
20024 IX86_BUILTIN_VEC_EXT_V2DI,
20025 IX86_BUILTIN_VEC_EXT_V4SF,
20026 IX86_BUILTIN_VEC_EXT_V4SI,
20027 IX86_BUILTIN_VEC_EXT_V8HI,
20028 IX86_BUILTIN_VEC_EXT_V2SI,
20029 IX86_BUILTIN_VEC_EXT_V4HI,
20030 IX86_BUILTIN_VEC_EXT_V16QI,
20031 IX86_BUILTIN_VEC_SET_V2DI,
20032 IX86_BUILTIN_VEC_SET_V4SF,
20033 IX86_BUILTIN_VEC_SET_V4SI,
20034 IX86_BUILTIN_VEC_SET_V8HI,
20035 IX86_BUILTIN_VEC_SET_V4HI,
20036 IX86_BUILTIN_VEC_SET_V16QI,
20038 IX86_BUILTIN_VEC_PACK_SFIX,
20041 IX86_BUILTIN_CRC32QI,
20042 IX86_BUILTIN_CRC32HI,
20043 IX86_BUILTIN_CRC32SI,
20044 IX86_BUILTIN_CRC32DI,
20046 IX86_BUILTIN_PCMPESTRI128,
20047 IX86_BUILTIN_PCMPESTRM128,
20048 IX86_BUILTIN_PCMPESTRA128,
20049 IX86_BUILTIN_PCMPESTRC128,
20050 IX86_BUILTIN_PCMPESTRO128,
20051 IX86_BUILTIN_PCMPESTRS128,
20052 IX86_BUILTIN_PCMPESTRZ128,
20053 IX86_BUILTIN_PCMPISTRI128,
20054 IX86_BUILTIN_PCMPISTRM128,
20055 IX86_BUILTIN_PCMPISTRA128,
20056 IX86_BUILTIN_PCMPISTRC128,
20057 IX86_BUILTIN_PCMPISTRO128,
20058 IX86_BUILTIN_PCMPISTRS128,
20059 IX86_BUILTIN_PCMPISTRZ128,
20061 IX86_BUILTIN_PCMPGTQ,
20063 /* AES instructions */
20064 IX86_BUILTIN_AESENC128,
20065 IX86_BUILTIN_AESENCLAST128,
20066 IX86_BUILTIN_AESDEC128,
20067 IX86_BUILTIN_AESDECLAST128,
20068 IX86_BUILTIN_AESIMC128,
20069 IX86_BUILTIN_AESKEYGENASSIST128,
20071 /* PCLMUL instruction */
20072 IX86_BUILTIN_PCLMULQDQ128,
20075 IX86_BUILTIN_ADDPD256,
20076 IX86_BUILTIN_ADDPS256,
20077 IX86_BUILTIN_ADDSUBPD256,
20078 IX86_BUILTIN_ADDSUBPS256,
20079 IX86_BUILTIN_ANDPD256,
20080 IX86_BUILTIN_ANDPS256,
20081 IX86_BUILTIN_ANDNPD256,
20082 IX86_BUILTIN_ANDNPS256,
20083 IX86_BUILTIN_BLENDPD256,
20084 IX86_BUILTIN_BLENDPS256,
20085 IX86_BUILTIN_BLENDVPD256,
20086 IX86_BUILTIN_BLENDVPS256,
20087 IX86_BUILTIN_DIVPD256,
20088 IX86_BUILTIN_DIVPS256,
20089 IX86_BUILTIN_DPPS256,
20090 IX86_BUILTIN_HADDPD256,
20091 IX86_BUILTIN_HADDPS256,
20092 IX86_BUILTIN_HSUBPD256,
20093 IX86_BUILTIN_HSUBPS256,
20094 IX86_BUILTIN_MAXPD256,
20095 IX86_BUILTIN_MAXPS256,
20096 IX86_BUILTIN_MINPD256,
20097 IX86_BUILTIN_MINPS256,
20098 IX86_BUILTIN_MULPD256,
20099 IX86_BUILTIN_MULPS256,
20100 IX86_BUILTIN_ORPD256,
20101 IX86_BUILTIN_ORPS256,
20102 IX86_BUILTIN_SHUFPD256,
20103 IX86_BUILTIN_SHUFPS256,
20104 IX86_BUILTIN_SUBPD256,
20105 IX86_BUILTIN_SUBPS256,
20106 IX86_BUILTIN_XORPD256,
20107 IX86_BUILTIN_XORPS256,
20108 IX86_BUILTIN_CMPSD,
20109 IX86_BUILTIN_CMPSS,
20110 IX86_BUILTIN_CMPPD,
20111 IX86_BUILTIN_CMPPS,
20112 IX86_BUILTIN_CMPPD256,
20113 IX86_BUILTIN_CMPPS256,
20114 IX86_BUILTIN_CVTDQ2PD256,
20115 IX86_BUILTIN_CVTDQ2PS256,
20116 IX86_BUILTIN_CVTPD2PS256,
20117 IX86_BUILTIN_CVTPS2DQ256,
20118 IX86_BUILTIN_CVTPS2PD256,
20119 IX86_BUILTIN_CVTTPD2DQ256,
20120 IX86_BUILTIN_CVTPD2DQ256,
20121 IX86_BUILTIN_CVTTPS2DQ256,
20122 IX86_BUILTIN_EXTRACTF128PD256,
20123 IX86_BUILTIN_EXTRACTF128PS256,
20124 IX86_BUILTIN_EXTRACTF128SI256,
20125 IX86_BUILTIN_VZEROALL,
20126 IX86_BUILTIN_VZEROUPPER,
20127 IX86_BUILTIN_VZEROUPPER_REX64,
20128 IX86_BUILTIN_VPERMILVARPD,
20129 IX86_BUILTIN_VPERMILVARPS,
20130 IX86_BUILTIN_VPERMILVARPD256,
20131 IX86_BUILTIN_VPERMILVARPS256,
20132 IX86_BUILTIN_VPERMILPD,
20133 IX86_BUILTIN_VPERMILPS,
20134 IX86_BUILTIN_VPERMILPD256,
20135 IX86_BUILTIN_VPERMILPS256,
20136 IX86_BUILTIN_VPERM2F128PD256,
20137 IX86_BUILTIN_VPERM2F128PS256,
20138 IX86_BUILTIN_VPERM2F128SI256,
20139 IX86_BUILTIN_VBROADCASTSS,
20140 IX86_BUILTIN_VBROADCASTSD256,
20141 IX86_BUILTIN_VBROADCASTSS256,
20142 IX86_BUILTIN_VBROADCASTPD256,
20143 IX86_BUILTIN_VBROADCASTPS256,
20144 IX86_BUILTIN_VINSERTF128PD256,
20145 IX86_BUILTIN_VINSERTF128PS256,
20146 IX86_BUILTIN_VINSERTF128SI256,
20147 IX86_BUILTIN_LOADUPD256,
20148 IX86_BUILTIN_LOADUPS256,
20149 IX86_BUILTIN_STOREUPD256,
20150 IX86_BUILTIN_STOREUPS256,
20151 IX86_BUILTIN_LDDQU256,
20152 IX86_BUILTIN_MOVNTDQ256,
20153 IX86_BUILTIN_MOVNTPD256,
20154 IX86_BUILTIN_MOVNTPS256,
20155 IX86_BUILTIN_LOADDQU256,
20156 IX86_BUILTIN_STOREDQU256,
20157 IX86_BUILTIN_MASKLOADPD,
20158 IX86_BUILTIN_MASKLOADPS,
20159 IX86_BUILTIN_MASKSTOREPD,
20160 IX86_BUILTIN_MASKSTOREPS,
20161 IX86_BUILTIN_MASKLOADPD256,
20162 IX86_BUILTIN_MASKLOADPS256,
20163 IX86_BUILTIN_MASKSTOREPD256,
20164 IX86_BUILTIN_MASKSTOREPS256,
20165 IX86_BUILTIN_MOVSHDUP256,
20166 IX86_BUILTIN_MOVSLDUP256,
20167 IX86_BUILTIN_MOVDDUP256,
20169 IX86_BUILTIN_SQRTPD256,
20170 IX86_BUILTIN_SQRTPS256,
20171 IX86_BUILTIN_SQRTPS_NR256,
20172 IX86_BUILTIN_RSQRTPS256,
20173 IX86_BUILTIN_RSQRTPS_NR256,
20175 IX86_BUILTIN_RCPPS256,
20177 IX86_BUILTIN_ROUNDPD256,
20178 IX86_BUILTIN_ROUNDPS256,
20180 IX86_BUILTIN_UNPCKHPD256,
20181 IX86_BUILTIN_UNPCKLPD256,
20182 IX86_BUILTIN_UNPCKHPS256,
20183 IX86_BUILTIN_UNPCKLPS256,
20185 IX86_BUILTIN_SI256_SI,
20186 IX86_BUILTIN_PS256_PS,
20187 IX86_BUILTIN_PD256_PD,
20188 IX86_BUILTIN_SI_SI256,
20189 IX86_BUILTIN_PS_PS256,
20190 IX86_BUILTIN_PD_PD256,
20192 IX86_BUILTIN_VTESTZPD,
20193 IX86_BUILTIN_VTESTCPD,
20194 IX86_BUILTIN_VTESTNZCPD,
20195 IX86_BUILTIN_VTESTZPS,
20196 IX86_BUILTIN_VTESTCPS,
20197 IX86_BUILTIN_VTESTNZCPS,
20198 IX86_BUILTIN_VTESTZPD256,
20199 IX86_BUILTIN_VTESTCPD256,
20200 IX86_BUILTIN_VTESTNZCPD256,
20201 IX86_BUILTIN_VTESTZPS256,
20202 IX86_BUILTIN_VTESTCPS256,
20203 IX86_BUILTIN_VTESTNZCPS256,
20204 IX86_BUILTIN_PTESTZ256,
20205 IX86_BUILTIN_PTESTC256,
20206 IX86_BUILTIN_PTESTNZC256,
20208 IX86_BUILTIN_MOVMSKPD256,
20209 IX86_BUILTIN_MOVMSKPS256,
20211 /* TFmode support builtins. */
20213 IX86_BUILTIN_FABSQ,
20214 IX86_BUILTIN_COPYSIGNQ,
20216 /* SSE5 instructions */
20217 IX86_BUILTIN_FMADDSS,
20218 IX86_BUILTIN_FMADDSD,
20219 IX86_BUILTIN_FMADDPS,
20220 IX86_BUILTIN_FMADDPD,
20221 IX86_BUILTIN_FMSUBSS,
20222 IX86_BUILTIN_FMSUBSD,
20223 IX86_BUILTIN_FMSUBPS,
20224 IX86_BUILTIN_FMSUBPD,
20225 IX86_BUILTIN_FNMADDSS,
20226 IX86_BUILTIN_FNMADDSD,
20227 IX86_BUILTIN_FNMADDPS,
20228 IX86_BUILTIN_FNMADDPD,
20229 IX86_BUILTIN_FNMSUBSS,
20230 IX86_BUILTIN_FNMSUBSD,
20231 IX86_BUILTIN_FNMSUBPS,
20232 IX86_BUILTIN_FNMSUBPD,
20233 IX86_BUILTIN_PCMOV,
20234 IX86_BUILTIN_PCMOV_V2DI,
20235 IX86_BUILTIN_PCMOV_V4SI,
20236 IX86_BUILTIN_PCMOV_V8HI,
20237 IX86_BUILTIN_PCMOV_V16QI,
20238 IX86_BUILTIN_PCMOV_V4SF,
20239 IX86_BUILTIN_PCMOV_V2DF,
20240 IX86_BUILTIN_PPERM,
20241 IX86_BUILTIN_PERMPS,
20242 IX86_BUILTIN_PERMPD,
20243 IX86_BUILTIN_PMACSSWW,
20244 IX86_BUILTIN_PMACSWW,
20245 IX86_BUILTIN_PMACSSWD,
20246 IX86_BUILTIN_PMACSWD,
20247 IX86_BUILTIN_PMACSSDD,
20248 IX86_BUILTIN_PMACSDD,
20249 IX86_BUILTIN_PMACSSDQL,
20250 IX86_BUILTIN_PMACSSDQH,
20251 IX86_BUILTIN_PMACSDQL,
20252 IX86_BUILTIN_PMACSDQH,
20253 IX86_BUILTIN_PMADCSSWD,
20254 IX86_BUILTIN_PMADCSWD,
20255 IX86_BUILTIN_PHADDBW,
20256 IX86_BUILTIN_PHADDBD,
20257 IX86_BUILTIN_PHADDBQ,
20258 IX86_BUILTIN_PHADDWD,
20259 IX86_BUILTIN_PHADDWQ,
20260 IX86_BUILTIN_PHADDDQ,
20261 IX86_BUILTIN_PHADDUBW,
20262 IX86_BUILTIN_PHADDUBD,
20263 IX86_BUILTIN_PHADDUBQ,
20264 IX86_BUILTIN_PHADDUWD,
20265 IX86_BUILTIN_PHADDUWQ,
20266 IX86_BUILTIN_PHADDUDQ,
20267 IX86_BUILTIN_PHSUBBW,
20268 IX86_BUILTIN_PHSUBWD,
20269 IX86_BUILTIN_PHSUBDQ,
20270 IX86_BUILTIN_PROTB,
20271 IX86_BUILTIN_PROTW,
20272 IX86_BUILTIN_PROTD,
20273 IX86_BUILTIN_PROTQ,
20274 IX86_BUILTIN_PROTB_IMM,
20275 IX86_BUILTIN_PROTW_IMM,
20276 IX86_BUILTIN_PROTD_IMM,
20277 IX86_BUILTIN_PROTQ_IMM,
20278 IX86_BUILTIN_PSHLB,
20279 IX86_BUILTIN_PSHLW,
20280 IX86_BUILTIN_PSHLD,
20281 IX86_BUILTIN_PSHLQ,
20282 IX86_BUILTIN_PSHAB,
20283 IX86_BUILTIN_PSHAW,
20284 IX86_BUILTIN_PSHAD,
20285 IX86_BUILTIN_PSHAQ,
20286 IX86_BUILTIN_FRCZSS,
20287 IX86_BUILTIN_FRCZSD,
20288 IX86_BUILTIN_FRCZPS,
20289 IX86_BUILTIN_FRCZPD,
20290 IX86_BUILTIN_CVTPH2PS,
20291 IX86_BUILTIN_CVTPS2PH,
20293 IX86_BUILTIN_COMEQSS,
20294 IX86_BUILTIN_COMNESS,
20295 IX86_BUILTIN_COMLTSS,
20296 IX86_BUILTIN_COMLESS,
20297 IX86_BUILTIN_COMGTSS,
20298 IX86_BUILTIN_COMGESS,
20299 IX86_BUILTIN_COMUEQSS,
20300 IX86_BUILTIN_COMUNESS,
20301 IX86_BUILTIN_COMULTSS,
20302 IX86_BUILTIN_COMULESS,
20303 IX86_BUILTIN_COMUGTSS,
20304 IX86_BUILTIN_COMUGESS,
20305 IX86_BUILTIN_COMORDSS,
20306 IX86_BUILTIN_COMUNORDSS,
20307 IX86_BUILTIN_COMFALSESS,
20308 IX86_BUILTIN_COMTRUESS,
20310 IX86_BUILTIN_COMEQSD,
20311 IX86_BUILTIN_COMNESD,
20312 IX86_BUILTIN_COMLTSD,
20313 IX86_BUILTIN_COMLESD,
20314 IX86_BUILTIN_COMGTSD,
20315 IX86_BUILTIN_COMGESD,
20316 IX86_BUILTIN_COMUEQSD,
20317 IX86_BUILTIN_COMUNESD,
20318 IX86_BUILTIN_COMULTSD,
20319 IX86_BUILTIN_COMULESD,
20320 IX86_BUILTIN_COMUGTSD,
20321 IX86_BUILTIN_COMUGESD,
20322 IX86_BUILTIN_COMORDSD,
20323 IX86_BUILTIN_COMUNORDSD,
20324 IX86_BUILTIN_COMFALSESD,
20325 IX86_BUILTIN_COMTRUESD,
20327 IX86_BUILTIN_COMEQPS,
20328 IX86_BUILTIN_COMNEPS,
20329 IX86_BUILTIN_COMLTPS,
20330 IX86_BUILTIN_COMLEPS,
20331 IX86_BUILTIN_COMGTPS,
20332 IX86_BUILTIN_COMGEPS,
20333 IX86_BUILTIN_COMUEQPS,
20334 IX86_BUILTIN_COMUNEPS,
20335 IX86_BUILTIN_COMULTPS,
20336 IX86_BUILTIN_COMULEPS,
20337 IX86_BUILTIN_COMUGTPS,
20338 IX86_BUILTIN_COMUGEPS,
20339 IX86_BUILTIN_COMORDPS,
20340 IX86_BUILTIN_COMUNORDPS,
20341 IX86_BUILTIN_COMFALSEPS,
20342 IX86_BUILTIN_COMTRUEPS,
20344 IX86_BUILTIN_COMEQPD,
20345 IX86_BUILTIN_COMNEPD,
20346 IX86_BUILTIN_COMLTPD,
20347 IX86_BUILTIN_COMLEPD,
20348 IX86_BUILTIN_COMGTPD,
20349 IX86_BUILTIN_COMGEPD,
20350 IX86_BUILTIN_COMUEQPD,
20351 IX86_BUILTIN_COMUNEPD,
20352 IX86_BUILTIN_COMULTPD,
20353 IX86_BUILTIN_COMULEPD,
20354 IX86_BUILTIN_COMUGTPD,
20355 IX86_BUILTIN_COMUGEPD,
20356 IX86_BUILTIN_COMORDPD,
20357 IX86_BUILTIN_COMUNORDPD,
20358 IX86_BUILTIN_COMFALSEPD,
20359 IX86_BUILTIN_COMTRUEPD,
20361 IX86_BUILTIN_PCOMEQUB,
20362 IX86_BUILTIN_PCOMNEUB,
20363 IX86_BUILTIN_PCOMLTUB,
20364 IX86_BUILTIN_PCOMLEUB,
20365 IX86_BUILTIN_PCOMGTUB,
20366 IX86_BUILTIN_PCOMGEUB,
20367 IX86_BUILTIN_PCOMFALSEUB,
20368 IX86_BUILTIN_PCOMTRUEUB,
20369 IX86_BUILTIN_PCOMEQUW,
20370 IX86_BUILTIN_PCOMNEUW,
20371 IX86_BUILTIN_PCOMLTUW,
20372 IX86_BUILTIN_PCOMLEUW,
20373 IX86_BUILTIN_PCOMGTUW,
20374 IX86_BUILTIN_PCOMGEUW,
20375 IX86_BUILTIN_PCOMFALSEUW,
20376 IX86_BUILTIN_PCOMTRUEUW,
20377 IX86_BUILTIN_PCOMEQUD,
20378 IX86_BUILTIN_PCOMNEUD,
20379 IX86_BUILTIN_PCOMLTUD,
20380 IX86_BUILTIN_PCOMLEUD,
20381 IX86_BUILTIN_PCOMGTUD,
20382 IX86_BUILTIN_PCOMGEUD,
20383 IX86_BUILTIN_PCOMFALSEUD,
20384 IX86_BUILTIN_PCOMTRUEUD,
20385 IX86_BUILTIN_PCOMEQUQ,
20386 IX86_BUILTIN_PCOMNEUQ,
20387 IX86_BUILTIN_PCOMLTUQ,
20388 IX86_BUILTIN_PCOMLEUQ,
20389 IX86_BUILTIN_PCOMGTUQ,
20390 IX86_BUILTIN_PCOMGEUQ,
20391 IX86_BUILTIN_PCOMFALSEUQ,
20392 IX86_BUILTIN_PCOMTRUEUQ,
20394 IX86_BUILTIN_PCOMEQB,
20395 IX86_BUILTIN_PCOMNEB,
20396 IX86_BUILTIN_PCOMLTB,
20397 IX86_BUILTIN_PCOMLEB,
20398 IX86_BUILTIN_PCOMGTB,
20399 IX86_BUILTIN_PCOMGEB,
20400 IX86_BUILTIN_PCOMFALSEB,
20401 IX86_BUILTIN_PCOMTRUEB,
20402 IX86_BUILTIN_PCOMEQW,
20403 IX86_BUILTIN_PCOMNEW,
20404 IX86_BUILTIN_PCOMLTW,
20405 IX86_BUILTIN_PCOMLEW,
20406 IX86_BUILTIN_PCOMGTW,
20407 IX86_BUILTIN_PCOMGEW,
20408 IX86_BUILTIN_PCOMFALSEW,
20409 IX86_BUILTIN_PCOMTRUEW,
20410 IX86_BUILTIN_PCOMEQD,
20411 IX86_BUILTIN_PCOMNED,
20412 IX86_BUILTIN_PCOMLTD,
20413 IX86_BUILTIN_PCOMLED,
20414 IX86_BUILTIN_PCOMGTD,
20415 IX86_BUILTIN_PCOMGED,
20416 IX86_BUILTIN_PCOMFALSED,
20417 IX86_BUILTIN_PCOMTRUED,
20418 IX86_BUILTIN_PCOMEQQ,
20419 IX86_BUILTIN_PCOMNEQ,
20420 IX86_BUILTIN_PCOMLTQ,
20421 IX86_BUILTIN_PCOMLEQ,
20422 IX86_BUILTIN_PCOMGTQ,
20423 IX86_BUILTIN_PCOMGEQ,
20424 IX86_BUILTIN_PCOMFALSEQ,
20425 IX86_BUILTIN_PCOMTRUEQ,
20430 /* Table for the ix86 builtin decls. */
20431 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20433 /* Table of all of the builtin functions that are possible with different ISA's
20434 but are waiting to be built until a function is declared to use that
20436 struct builtin_isa GTY(())
20438 tree type; /* builtin type to use in the declaration */
20439 const char *name; /* function name */
20440 int isa; /* isa_flags this builtin is defined for */
20441 bool const_p; /* true if the declaration is constant */
20444 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20447 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20448 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20449 * function decl in the ix86_builtins array. Returns the function decl or
20450 * NULL_TREE, if the builtin was not added.
20452 * If the front end has a special hook for builtin functions, delay adding
20453 * builtin functions that aren't in the current ISA until the ISA is changed
20454 * with function specific optimization. Doing so, can save about 300K for the
20455 * default compiler. When the builtin is expanded, check at that time whether
20458 * If the front end doesn't have a special hook, record all builtins, even if
20459 * it isn't an instruction set in the current ISA in case the user uses
20460 * function specific options for a different ISA, so that we don't get scope
20461 * errors if a builtin is added in the middle of a function scope. */
20464 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20466 tree decl = NULL_TREE;
20468 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20470 ix86_builtins_isa[(int) code].isa = mask;
20472 if ((mask & ix86_isa_flags) != 0
20473 || (lang_hooks.builtin_function
20474 == lang_hooks.builtin_function_ext_scope))
20477 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20479 ix86_builtins[(int) code] = decl;
20480 ix86_builtins_isa[(int) code].type = NULL_TREE;
20484 ix86_builtins[(int) code] = NULL_TREE;
20485 ix86_builtins_isa[(int) code].const_p = false;
20486 ix86_builtins_isa[(int) code].type = type;
20487 ix86_builtins_isa[(int) code].name = name;
20494 /* Like def_builtin, but also marks the function decl "const". */
20497 def_builtin_const (int mask, const char *name, tree type,
20498 enum ix86_builtins code)
20500 tree decl = def_builtin (mask, name, type, code);
20502 TREE_READONLY (decl) = 1;
20504 ix86_builtins_isa[(int) code].const_p = true;
20509 /* Add any new builtin functions for a given ISA that may not have been
20510 declared. This saves a bit of space compared to adding all of the
20511 declarations to the tree, even if we didn't use them. */
20514 ix86_add_new_builtins (int isa)
20519 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20521 if ((ix86_builtins_isa[i].isa & isa) != 0
20522 && ix86_builtins_isa[i].type != NULL_TREE)
20524 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20525 ix86_builtins_isa[i].type,
20526 i, BUILT_IN_MD, NULL,
20529 ix86_builtins[i] = decl;
20530 ix86_builtins_isa[i].type = NULL_TREE;
20531 if (ix86_builtins_isa[i].const_p)
20532 TREE_READONLY (decl) = 1;
20537 /* Bits for builtin_description.flag. */
20539 /* Set when we don't support the comparison natively, and should
20540 swap_comparison in order to support it. */
20541 #define BUILTIN_DESC_SWAP_OPERANDS 1
20543 struct builtin_description
20545 const unsigned int mask;
20546 const enum insn_code icode;
20547 const char *const name;
20548 const enum ix86_builtins code;
20549 const enum rtx_code comparison;
20553 static const struct builtin_description bdesc_comi[] =
20555 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20556 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20557 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20558 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20559 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20560 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20561 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20562 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20563 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20564 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20565 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20566 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20567 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20568 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20569 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20570 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20574 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20577 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20581 static const struct builtin_description bdesc_pcmpestr[] =
20584 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20585 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20586 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20587 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20588 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20589 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20590 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20593 static const struct builtin_description bdesc_pcmpistr[] =
20596 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20597 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20598 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20599 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20600 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20601 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20602 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20605 /* Special builtin types */
20606 enum ix86_special_builtin_type
20608 SPECIAL_FTYPE_UNKNOWN,
20610 V32QI_FTYPE_PCCHAR,
20611 V16QI_FTYPE_PCCHAR,
20613 V8SF_FTYPE_PCFLOAT,
20615 V4DF_FTYPE_PCDOUBLE,
20616 V4SF_FTYPE_PCFLOAT,
20617 V2DF_FTYPE_PCDOUBLE,
20618 V8SF_FTYPE_PCV8SF_V8SF,
20619 V4DF_FTYPE_PCV4DF_V4DF,
20620 V4SF_FTYPE_V4SF_PCV2SF,
20621 V4SF_FTYPE_PCV4SF_V4SF,
20622 V2DF_FTYPE_V2DF_PCDOUBLE,
20623 V2DF_FTYPE_PCV2DF_V2DF,
20625 VOID_FTYPE_PV2SF_V4SF,
20626 VOID_FTYPE_PV4DI_V4DI,
20627 VOID_FTYPE_PV2DI_V2DI,
20628 VOID_FTYPE_PCHAR_V32QI,
20629 VOID_FTYPE_PCHAR_V16QI,
20630 VOID_FTYPE_PFLOAT_V8SF,
20631 VOID_FTYPE_PFLOAT_V4SF,
20632 VOID_FTYPE_PDOUBLE_V4DF,
20633 VOID_FTYPE_PDOUBLE_V2DF,
20635 VOID_FTYPE_PINT_INT,
20636 VOID_FTYPE_PV8SF_V8SF_V8SF,
20637 VOID_FTYPE_PV4DF_V4DF_V4DF,
20638 VOID_FTYPE_PV4SF_V4SF_V4SF,
20639 VOID_FTYPE_PV2DF_V2DF_V2DF
20642 /* Builtin types */
20643 enum ix86_builtin_type
20646 FLOAT128_FTYPE_FLOAT128,
20648 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20649 INT_FTYPE_V8SF_V8SF_PTEST,
20650 INT_FTYPE_V4DI_V4DI_PTEST,
20651 INT_FTYPE_V4DF_V4DF_PTEST,
20652 INT_FTYPE_V4SF_V4SF_PTEST,
20653 INT_FTYPE_V2DI_V2DI_PTEST,
20654 INT_FTYPE_V2DF_V2DF_PTEST,
20686 V4SF_FTYPE_V4SF_VEC_MERGE,
20695 V2DF_FTYPE_V2DF_VEC_MERGE,
20706 V16QI_FTYPE_V16QI_V16QI,
20707 V16QI_FTYPE_V8HI_V8HI,
20708 V8QI_FTYPE_V8QI_V8QI,
20709 V8QI_FTYPE_V4HI_V4HI,
20710 V8HI_FTYPE_V8HI_V8HI,
20711 V8HI_FTYPE_V8HI_V8HI_COUNT,
20712 V8HI_FTYPE_V16QI_V16QI,
20713 V8HI_FTYPE_V4SI_V4SI,
20714 V8HI_FTYPE_V8HI_SI_COUNT,
20715 V8SF_FTYPE_V8SF_V8SF,
20716 V8SF_FTYPE_V8SF_V8SI,
20717 V4SI_FTYPE_V4SI_V4SI,
20718 V4SI_FTYPE_V4SI_V4SI_COUNT,
20719 V4SI_FTYPE_V8HI_V8HI,
20720 V4SI_FTYPE_V4SF_V4SF,
20721 V4SI_FTYPE_V2DF_V2DF,
20722 V4SI_FTYPE_V4SI_SI_COUNT,
20723 V4HI_FTYPE_V4HI_V4HI,
20724 V4HI_FTYPE_V4HI_V4HI_COUNT,
20725 V4HI_FTYPE_V8QI_V8QI,
20726 V4HI_FTYPE_V2SI_V2SI,
20727 V4HI_FTYPE_V4HI_SI_COUNT,
20728 V4DF_FTYPE_V4DF_V4DF,
20729 V4DF_FTYPE_V4DF_V4DI,
20730 V4SF_FTYPE_V4SF_V4SF,
20731 V4SF_FTYPE_V4SF_V4SF_SWAP,
20732 V4SF_FTYPE_V4SF_V4SI,
20733 V4SF_FTYPE_V4SF_V2SI,
20734 V4SF_FTYPE_V4SF_V2DF,
20735 V4SF_FTYPE_V4SF_DI,
20736 V4SF_FTYPE_V4SF_SI,
20737 V2DI_FTYPE_V2DI_V2DI,
20738 V2DI_FTYPE_V2DI_V2DI_COUNT,
20739 V2DI_FTYPE_V16QI_V16QI,
20740 V2DI_FTYPE_V4SI_V4SI,
20741 V2DI_FTYPE_V2DI_V16QI,
20742 V2DI_FTYPE_V2DF_V2DF,
20743 V2DI_FTYPE_V2DI_SI_COUNT,
20744 V2SI_FTYPE_V2SI_V2SI,
20745 V2SI_FTYPE_V2SI_V2SI_COUNT,
20746 V2SI_FTYPE_V4HI_V4HI,
20747 V2SI_FTYPE_V2SF_V2SF,
20748 V2SI_FTYPE_V2SI_SI_COUNT,
20749 V2DF_FTYPE_V2DF_V2DF,
20750 V2DF_FTYPE_V2DF_V2DF_SWAP,
20751 V2DF_FTYPE_V2DF_V4SF,
20752 V2DF_FTYPE_V2DF_V2DI,
20753 V2DF_FTYPE_V2DF_DI,
20754 V2DF_FTYPE_V2DF_SI,
20755 V2SF_FTYPE_V2SF_V2SF,
20756 V1DI_FTYPE_V1DI_V1DI,
20757 V1DI_FTYPE_V1DI_V1DI_COUNT,
20758 V1DI_FTYPE_V8QI_V8QI,
20759 V1DI_FTYPE_V2SI_V2SI,
20760 V1DI_FTYPE_V1DI_SI_COUNT,
20761 UINT64_FTYPE_UINT64_UINT64,
20762 UINT_FTYPE_UINT_UINT,
20763 UINT_FTYPE_UINT_USHORT,
20764 UINT_FTYPE_UINT_UCHAR,
20765 V8HI_FTYPE_V8HI_INT,
20766 V4SI_FTYPE_V4SI_INT,
20767 V4HI_FTYPE_V4HI_INT,
20768 V8SF_FTYPE_V8SF_INT,
20769 V4SI_FTYPE_V8SI_INT,
20770 V4SF_FTYPE_V8SF_INT,
20771 V2DF_FTYPE_V4DF_INT,
20772 V4DF_FTYPE_V4DF_INT,
20773 V4SF_FTYPE_V4SF_INT,
20774 V2DI_FTYPE_V2DI_INT,
20775 V2DI2TI_FTYPE_V2DI_INT,
20776 V2DF_FTYPE_V2DF_INT,
20777 V16QI_FTYPE_V16QI_V16QI_V16QI,
20778 V8SF_FTYPE_V8SF_V8SF_V8SF,
20779 V4DF_FTYPE_V4DF_V4DF_V4DF,
20780 V4SF_FTYPE_V4SF_V4SF_V4SF,
20781 V2DF_FTYPE_V2DF_V2DF_V2DF,
20782 V16QI_FTYPE_V16QI_V16QI_INT,
20783 V8SI_FTYPE_V8SI_V8SI_INT,
20784 V8SI_FTYPE_V8SI_V4SI_INT,
20785 V8HI_FTYPE_V8HI_V8HI_INT,
20786 V8SF_FTYPE_V8SF_V8SF_INT,
20787 V8SF_FTYPE_V8SF_V4SF_INT,
20788 V4SI_FTYPE_V4SI_V4SI_INT,
20789 V4DF_FTYPE_V4DF_V4DF_INT,
20790 V4DF_FTYPE_V4DF_V2DF_INT,
20791 V4SF_FTYPE_V4SF_V4SF_INT,
20792 V2DI_FTYPE_V2DI_V2DI_INT,
20793 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20794 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20795 V2DF_FTYPE_V2DF_V2DF_INT,
20796 V2DI_FTYPE_V2DI_UINT_UINT,
20797 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20800 /* Special builtins with variable number of arguments. */
20801 static const struct builtin_description bdesc_special_args[] =
20804 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20807 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20810 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20811 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20812 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20814 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20815 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20816 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20817 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20819 /* SSE or 3DNow!A */
20820 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20821 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20824 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20827 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20829 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20830 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20838 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20841 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20844 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20845 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20850 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20860 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
20867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20870 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20873 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20876 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20880 /* Builtins with variable number of arguments. */
20881 static const struct builtin_description bdesc_args[] =
20884 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20885 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20886 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20887 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20888 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20889 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20891 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20892 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20893 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20894 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20895 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20896 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20897 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20898 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20900 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20901 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20903 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20904 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20905 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20906 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20908 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20909 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20910 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20911 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20912 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20913 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20915 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20916 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20917 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20918 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20919 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20920 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20922 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20923 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20924 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20926 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20928 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20929 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20930 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20931 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20932 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20933 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20935 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20936 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20937 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20938 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20939 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20940 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20942 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20943 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20944 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20945 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20948 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20949 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20950 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20951 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20953 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20954 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20955 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20956 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20957 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20958 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20959 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20960 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20961 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20962 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20963 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20964 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20965 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20966 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20967 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20970 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20971 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20972 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20973 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20974 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20975 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20978 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20980 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20982 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20984 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20985 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20986 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20987 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20988 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20989 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20993 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20994 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20995 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20996 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20998 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20999 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21003 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21004 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21005 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21006 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21007 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21008 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21009 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21010 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21011 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21012 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21025 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21026 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21027 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21028 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21030 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21031 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21032 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21033 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21035 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21036 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21037 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21038 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21039 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21041 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21042 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21043 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21045 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21047 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21048 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21049 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21051 /* SSE MMX or 3Dnow!A */
21052 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21053 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21054 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21056 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21057 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21058 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21059 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21061 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21062 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21064 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21067 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21070 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21072 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21085 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21086 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21092 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21093 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21094 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21095 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21108 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21111 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21112 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21113 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21114 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21115 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21116 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21123 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21127 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21129 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21130 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21133 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21136 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21138 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21139 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21140 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21141 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21142 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21143 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21144 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21145 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21152 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21156 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21157 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21159 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21161 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21162 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21168 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21169 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21170 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21171 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21172 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21174 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21175 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21176 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21192 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21201 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21206 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21207 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21208 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21209 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21210 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21211 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21214 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21215 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21216 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21217 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21218 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21219 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21221 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21222 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21223 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21224 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21232 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21233 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21238 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21239 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21242 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21243 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21245 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21246 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21247 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21248 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21249 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21250 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21253 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21254 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21255 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21256 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21257 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21258 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21260 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21261 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21262 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21263 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21264 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21265 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21266 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21267 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21268 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21269 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21270 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21271 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21272 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21273 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21274 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21275 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21276 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21277 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21278 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21279 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21280 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21281 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21282 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21283 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21286 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21287 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21290 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21291 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21292 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21293 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21294 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21295 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21296 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21297 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21298 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21299 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21301 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21302 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21303 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21304 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21305 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21306 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21307 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21308 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21309 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21310 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21311 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21312 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21313 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21315 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21316 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21317 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21318 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21319 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21320 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21321 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21322 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21323 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21324 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21325 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21326 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21328 /* SSE4.1 and SSE5 */
21329 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21330 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21331 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21332 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21334 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21335 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21336 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21339 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21340 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21341 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21342 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21343 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21346 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21347 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21348 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21349 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21352 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21353 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21355 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21356 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21357 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21358 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21361 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21364 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21365 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21368 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21369 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21372 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21373 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21374 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21375 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21376 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21377 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21378 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21379 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21380 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21381 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21382 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21383 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21384 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21385 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21386 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21387 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21388 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21389 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21397 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21398 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21399 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21400 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21401 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21403 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21404 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21405 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21406 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21407 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21409 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21410 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21411 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21412 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21413 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21433 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21435 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21437 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21439 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21443 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21446 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21447 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21448 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21449 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21451 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21452 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21453 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21454 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21455 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21456 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21458 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21459 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21460 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21461 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21462 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21463 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21464 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21466 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21467 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21468 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21469 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21470 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21471 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21472 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21474 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21475 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21479 enum multi_arg_type {
21489 MULTI_ARG_3_PERMPS,
21490 MULTI_ARG_3_PERMPD,
21497 MULTI_ARG_2_DI_IMM,
21498 MULTI_ARG_2_SI_IMM,
21499 MULTI_ARG_2_HI_IMM,
21500 MULTI_ARG_2_QI_IMM,
21501 MULTI_ARG_2_SF_CMP,
21502 MULTI_ARG_2_DF_CMP,
21503 MULTI_ARG_2_DI_CMP,
21504 MULTI_ARG_2_SI_CMP,
21505 MULTI_ARG_2_HI_CMP,
21506 MULTI_ARG_2_QI_CMP,
21529 static const struct builtin_description bdesc_multi_arg[] =
21531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21559 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21563 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21564 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21565 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21566 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21567 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21568 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21569 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21570 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21571 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21572 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21573 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21574 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21575 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21576 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21577 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21578 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21579 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21580 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21581 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21582 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21583 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21584 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21585 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21586 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21587 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21588 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21589 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21590 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21591 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21592 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21593 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21594 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21595 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21596 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21597 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21598 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21599 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21600 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21601 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21602 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21603 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21604 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21605 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21607 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21608 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21609 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21610 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21611 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21612 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21613 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21614 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21615 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21616 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21617 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21618 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21619 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21620 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21621 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21622 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21624 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21625 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21626 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21627 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21628 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21629 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21630 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21631 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21632 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21633 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21634 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21635 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21636 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21637 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21638 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21639 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21641 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21642 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21643 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21644 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21645 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21646 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21647 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21648 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21649 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21650 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21651 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21652 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21653 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21654 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21655 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21656 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21658 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21659 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21660 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21661 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21662 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21663 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21664 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21665 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21666 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21667 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21668 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21669 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21670 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21671 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21672 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21673 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21675 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21676 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21677 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21678 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21679 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21680 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21681 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21683 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21684 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21685 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21686 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21687 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21688 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21689 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21691 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21692 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21693 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21699 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21700 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21701 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21707 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21708 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21709 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21715 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21716 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21718 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21719 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21720 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21721 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21724 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21727 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21732 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21733 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21736 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21737 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21739 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21740 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21741 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21742 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21743 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21744 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21745 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21746 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21748 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21749 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21750 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21751 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21752 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21753 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21754 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21755 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21757 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21758 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21759 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21760 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21761 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21762 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21763 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21764 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21767 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21768 in the current target ISA to allow the user to compile particular modules
21769 with different target specific options that differ from the command line
21772 ix86_init_mmx_sse_builtins (void)
21774 const struct builtin_description * d;
21777 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21778 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21779 tree V1DI_type_node
21780 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21781 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21782 tree V2DI_type_node
21783 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21784 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21785 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21786 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21787 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21788 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21789 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21791 tree pchar_type_node = build_pointer_type (char_type_node);
21792 tree pcchar_type_node
21793 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21794 tree pfloat_type_node = build_pointer_type (float_type_node);
21795 tree pcfloat_type_node
21796 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21797 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21798 tree pcv2sf_type_node
21799 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21800 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21801 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21804 tree int_ftype_v4sf_v4sf
21805 = build_function_type_list (integer_type_node,
21806 V4SF_type_node, V4SF_type_node, NULL_TREE);
21807 tree v4si_ftype_v4sf_v4sf
21808 = build_function_type_list (V4SI_type_node,
21809 V4SF_type_node, V4SF_type_node, NULL_TREE);
21810 /* MMX/SSE/integer conversions. */
21811 tree int_ftype_v4sf
21812 = build_function_type_list (integer_type_node,
21813 V4SF_type_node, NULL_TREE);
21814 tree int64_ftype_v4sf
21815 = build_function_type_list (long_long_integer_type_node,
21816 V4SF_type_node, NULL_TREE);
21817 tree int_ftype_v8qi
21818 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21819 tree v4sf_ftype_v4sf_int
21820 = build_function_type_list (V4SF_type_node,
21821 V4SF_type_node, integer_type_node, NULL_TREE);
21822 tree v4sf_ftype_v4sf_int64
21823 = build_function_type_list (V4SF_type_node,
21824 V4SF_type_node, long_long_integer_type_node,
21826 tree v4sf_ftype_v4sf_v2si
21827 = build_function_type_list (V4SF_type_node,
21828 V4SF_type_node, V2SI_type_node, NULL_TREE);
21830 /* Miscellaneous. */
21831 tree v8qi_ftype_v4hi_v4hi
21832 = build_function_type_list (V8QI_type_node,
21833 V4HI_type_node, V4HI_type_node, NULL_TREE);
21834 tree v4hi_ftype_v2si_v2si
21835 = build_function_type_list (V4HI_type_node,
21836 V2SI_type_node, V2SI_type_node, NULL_TREE);
21837 tree v4sf_ftype_v4sf_v4sf_int
21838 = build_function_type_list (V4SF_type_node,
21839 V4SF_type_node, V4SF_type_node,
21840 integer_type_node, NULL_TREE);
21841 tree v2si_ftype_v4hi_v4hi
21842 = build_function_type_list (V2SI_type_node,
21843 V4HI_type_node, V4HI_type_node, NULL_TREE);
21844 tree v4hi_ftype_v4hi_int
21845 = build_function_type_list (V4HI_type_node,
21846 V4HI_type_node, integer_type_node, NULL_TREE);
21847 tree v2si_ftype_v2si_int
21848 = build_function_type_list (V2SI_type_node,
21849 V2SI_type_node, integer_type_node, NULL_TREE);
21850 tree v1di_ftype_v1di_int
21851 = build_function_type_list (V1DI_type_node,
21852 V1DI_type_node, integer_type_node, NULL_TREE);
21854 tree void_ftype_void
21855 = build_function_type (void_type_node, void_list_node);
21856 tree void_ftype_unsigned
21857 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21858 tree void_ftype_unsigned_unsigned
21859 = build_function_type_list (void_type_node, unsigned_type_node,
21860 unsigned_type_node, NULL_TREE);
21861 tree void_ftype_pcvoid_unsigned_unsigned
21862 = build_function_type_list (void_type_node, const_ptr_type_node,
21863 unsigned_type_node, unsigned_type_node,
21865 tree unsigned_ftype_void
21866 = build_function_type (unsigned_type_node, void_list_node);
21867 tree v2si_ftype_v4sf
21868 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21869 /* Loads/stores. */
21870 tree void_ftype_v8qi_v8qi_pchar
21871 = build_function_type_list (void_type_node,
21872 V8QI_type_node, V8QI_type_node,
21873 pchar_type_node, NULL_TREE);
21874 tree v4sf_ftype_pcfloat
21875 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21876 tree v4sf_ftype_v4sf_pcv2sf
21877 = build_function_type_list (V4SF_type_node,
21878 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21879 tree void_ftype_pv2sf_v4sf
21880 = build_function_type_list (void_type_node,
21881 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21882 tree void_ftype_pfloat_v4sf
21883 = build_function_type_list (void_type_node,
21884 pfloat_type_node, V4SF_type_node, NULL_TREE);
21885 tree void_ftype_pdi_di
21886 = build_function_type_list (void_type_node,
21887 pdi_type_node, long_long_unsigned_type_node,
21889 tree void_ftype_pv2di_v2di
21890 = build_function_type_list (void_type_node,
21891 pv2di_type_node, V2DI_type_node, NULL_TREE);
21892 /* Normal vector unops. */
21893 tree v4sf_ftype_v4sf
21894 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21895 tree v16qi_ftype_v16qi
21896 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21897 tree v8hi_ftype_v8hi
21898 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21899 tree v4si_ftype_v4si
21900 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21901 tree v8qi_ftype_v8qi
21902 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21903 tree v4hi_ftype_v4hi
21904 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21906 /* Normal vector binops. */
21907 tree v4sf_ftype_v4sf_v4sf
21908 = build_function_type_list (V4SF_type_node,
21909 V4SF_type_node, V4SF_type_node, NULL_TREE);
21910 tree v8qi_ftype_v8qi_v8qi
21911 = build_function_type_list (V8QI_type_node,
21912 V8QI_type_node, V8QI_type_node, NULL_TREE);
21913 tree v4hi_ftype_v4hi_v4hi
21914 = build_function_type_list (V4HI_type_node,
21915 V4HI_type_node, V4HI_type_node, NULL_TREE);
21916 tree v2si_ftype_v2si_v2si
21917 = build_function_type_list (V2SI_type_node,
21918 V2SI_type_node, V2SI_type_node, NULL_TREE);
21919 tree v1di_ftype_v1di_v1di
21920 = build_function_type_list (V1DI_type_node,
21921 V1DI_type_node, V1DI_type_node, NULL_TREE);
21922 tree v1di_ftype_v1di_v1di_int
21923 = build_function_type_list (V1DI_type_node,
21924 V1DI_type_node, V1DI_type_node,
21925 integer_type_node, NULL_TREE);
21926 tree v2si_ftype_v2sf
21927 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21928 tree v2sf_ftype_v2si
21929 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21930 tree v2si_ftype_v2si
21931 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21932 tree v2sf_ftype_v2sf
21933 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21934 tree v2sf_ftype_v2sf_v2sf
21935 = build_function_type_list (V2SF_type_node,
21936 V2SF_type_node, V2SF_type_node, NULL_TREE);
21937 tree v2si_ftype_v2sf_v2sf
21938 = build_function_type_list (V2SI_type_node,
21939 V2SF_type_node, V2SF_type_node, NULL_TREE);
21940 tree pint_type_node = build_pointer_type (integer_type_node);
21941 tree pdouble_type_node = build_pointer_type (double_type_node);
21942 tree pcdouble_type_node = build_pointer_type (
21943 build_type_variant (double_type_node, 1, 0));
21944 tree int_ftype_v2df_v2df
21945 = build_function_type_list (integer_type_node,
21946 V2DF_type_node, V2DF_type_node, NULL_TREE);
21948 tree void_ftype_pcvoid
21949 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21950 tree v4sf_ftype_v4si
21951 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21952 tree v4si_ftype_v4sf
21953 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21954 tree v2df_ftype_v4si
21955 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21956 tree v4si_ftype_v2df
21957 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21958 tree v4si_ftype_v2df_v2df
21959 = build_function_type_list (V4SI_type_node,
21960 V2DF_type_node, V2DF_type_node, NULL_TREE);
21961 tree v2si_ftype_v2df
21962 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21963 tree v4sf_ftype_v2df
21964 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21965 tree v2df_ftype_v2si
21966 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21967 tree v2df_ftype_v4sf
21968 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21969 tree int_ftype_v2df
21970 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21971 tree int64_ftype_v2df
21972 = build_function_type_list (long_long_integer_type_node,
21973 V2DF_type_node, NULL_TREE);
21974 tree v2df_ftype_v2df_int
21975 = build_function_type_list (V2DF_type_node,
21976 V2DF_type_node, integer_type_node, NULL_TREE);
21977 tree v2df_ftype_v2df_int64
21978 = build_function_type_list (V2DF_type_node,
21979 V2DF_type_node, long_long_integer_type_node,
21981 tree v4sf_ftype_v4sf_v2df
21982 = build_function_type_list (V4SF_type_node,
21983 V4SF_type_node, V2DF_type_node, NULL_TREE);
21984 tree v2df_ftype_v2df_v4sf
21985 = build_function_type_list (V2DF_type_node,
21986 V2DF_type_node, V4SF_type_node, NULL_TREE);
21987 tree v2df_ftype_v2df_v2df_int
21988 = build_function_type_list (V2DF_type_node,
21989 V2DF_type_node, V2DF_type_node,
21992 tree v2df_ftype_v2df_pcdouble
21993 = build_function_type_list (V2DF_type_node,
21994 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21995 tree void_ftype_pdouble_v2df
21996 = build_function_type_list (void_type_node,
21997 pdouble_type_node, V2DF_type_node, NULL_TREE);
21998 tree void_ftype_pint_int
21999 = build_function_type_list (void_type_node,
22000 pint_type_node, integer_type_node, NULL_TREE);
22001 tree void_ftype_v16qi_v16qi_pchar
22002 = build_function_type_list (void_type_node,
22003 V16QI_type_node, V16QI_type_node,
22004 pchar_type_node, NULL_TREE);
22005 tree v2df_ftype_pcdouble
22006 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22007 tree v2df_ftype_v2df_v2df
22008 = build_function_type_list (V2DF_type_node,
22009 V2DF_type_node, V2DF_type_node, NULL_TREE);
22010 tree v16qi_ftype_v16qi_v16qi
22011 = build_function_type_list (V16QI_type_node,
22012 V16QI_type_node, V16QI_type_node, NULL_TREE);
22013 tree v8hi_ftype_v8hi_v8hi
22014 = build_function_type_list (V8HI_type_node,
22015 V8HI_type_node, V8HI_type_node, NULL_TREE);
22016 tree v4si_ftype_v4si_v4si
22017 = build_function_type_list (V4SI_type_node,
22018 V4SI_type_node, V4SI_type_node, NULL_TREE);
22019 tree v2di_ftype_v2di_v2di
22020 = build_function_type_list (V2DI_type_node,
22021 V2DI_type_node, V2DI_type_node, NULL_TREE);
22022 tree v2di_ftype_v2df_v2df
22023 = build_function_type_list (V2DI_type_node,
22024 V2DF_type_node, V2DF_type_node, NULL_TREE);
22025 tree v2df_ftype_v2df
22026 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22027 tree v2di_ftype_v2di_int
22028 = build_function_type_list (V2DI_type_node,
22029 V2DI_type_node, integer_type_node, NULL_TREE);
22030 tree v2di_ftype_v2di_v2di_int
22031 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22032 V2DI_type_node, integer_type_node, NULL_TREE);
22033 tree v4si_ftype_v4si_int
22034 = build_function_type_list (V4SI_type_node,
22035 V4SI_type_node, integer_type_node, NULL_TREE);
22036 tree v8hi_ftype_v8hi_int
22037 = build_function_type_list (V8HI_type_node,
22038 V8HI_type_node, integer_type_node, NULL_TREE);
22039 tree v4si_ftype_v8hi_v8hi
22040 = build_function_type_list (V4SI_type_node,
22041 V8HI_type_node, V8HI_type_node, NULL_TREE);
22042 tree v1di_ftype_v8qi_v8qi
22043 = build_function_type_list (V1DI_type_node,
22044 V8QI_type_node, V8QI_type_node, NULL_TREE);
22045 tree v1di_ftype_v2si_v2si
22046 = build_function_type_list (V1DI_type_node,
22047 V2SI_type_node, V2SI_type_node, NULL_TREE);
22048 tree v2di_ftype_v16qi_v16qi
22049 = build_function_type_list (V2DI_type_node,
22050 V16QI_type_node, V16QI_type_node, NULL_TREE);
22051 tree v2di_ftype_v4si_v4si
22052 = build_function_type_list (V2DI_type_node,
22053 V4SI_type_node, V4SI_type_node, NULL_TREE);
22054 tree int_ftype_v16qi
22055 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22056 tree v16qi_ftype_pcchar
22057 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22058 tree void_ftype_pchar_v16qi
22059 = build_function_type_list (void_type_node,
22060 pchar_type_node, V16QI_type_node, NULL_TREE);
22062 tree v2di_ftype_v2di_unsigned_unsigned
22063 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22064 unsigned_type_node, unsigned_type_node,
22066 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22067 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22068 unsigned_type_node, unsigned_type_node,
22070 tree v2di_ftype_v2di_v16qi
22071 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22073 tree v2df_ftype_v2df_v2df_v2df
22074 = build_function_type_list (V2DF_type_node,
22075 V2DF_type_node, V2DF_type_node,
22076 V2DF_type_node, NULL_TREE);
22077 tree v4sf_ftype_v4sf_v4sf_v4sf
22078 = build_function_type_list (V4SF_type_node,
22079 V4SF_type_node, V4SF_type_node,
22080 V4SF_type_node, NULL_TREE);
22081 tree v8hi_ftype_v16qi
22082 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22084 tree v4si_ftype_v16qi
22085 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22087 tree v2di_ftype_v16qi
22088 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22090 tree v4si_ftype_v8hi
22091 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22093 tree v2di_ftype_v8hi
22094 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22096 tree v2di_ftype_v4si
22097 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22099 tree v2di_ftype_pv2di
22100 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22102 tree v16qi_ftype_v16qi_v16qi_int
22103 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22104 V16QI_type_node, integer_type_node,
22106 tree v16qi_ftype_v16qi_v16qi_v16qi
22107 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22108 V16QI_type_node, V16QI_type_node,
22110 tree v8hi_ftype_v8hi_v8hi_int
22111 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22112 V8HI_type_node, integer_type_node,
22114 tree v4si_ftype_v4si_v4si_int
22115 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22116 V4SI_type_node, integer_type_node,
22118 tree int_ftype_v2di_v2di
22119 = build_function_type_list (integer_type_node,
22120 V2DI_type_node, V2DI_type_node,
22122 tree int_ftype_v16qi_int_v16qi_int_int
22123 = build_function_type_list (integer_type_node,
22130 tree v16qi_ftype_v16qi_int_v16qi_int_int
22131 = build_function_type_list (V16QI_type_node,
22138 tree int_ftype_v16qi_v16qi_int
22139 = build_function_type_list (integer_type_node,
22145 /* SSE5 instructions */
22146 tree v2di_ftype_v2di_v2di_v2di
22147 = build_function_type_list (V2DI_type_node,
22153 tree v4si_ftype_v4si_v4si_v4si
22154 = build_function_type_list (V4SI_type_node,
22160 tree v4si_ftype_v4si_v4si_v2di
22161 = build_function_type_list (V4SI_type_node,
22167 tree v8hi_ftype_v8hi_v8hi_v8hi
22168 = build_function_type_list (V8HI_type_node,
22174 tree v8hi_ftype_v8hi_v8hi_v4si
22175 = build_function_type_list (V8HI_type_node,
22181 tree v2df_ftype_v2df_v2df_v16qi
22182 = build_function_type_list (V2DF_type_node,
22188 tree v4sf_ftype_v4sf_v4sf_v16qi
22189 = build_function_type_list (V4SF_type_node,
22195 tree v2di_ftype_v2di_si
22196 = build_function_type_list (V2DI_type_node,
22201 tree v4si_ftype_v4si_si
22202 = build_function_type_list (V4SI_type_node,
22207 tree v8hi_ftype_v8hi_si
22208 = build_function_type_list (V8HI_type_node,
22213 tree v16qi_ftype_v16qi_si
22214 = build_function_type_list (V16QI_type_node,
22218 tree v4sf_ftype_v4hi
22219 = build_function_type_list (V4SF_type_node,
22223 tree v4hi_ftype_v4sf
22224 = build_function_type_list (V4HI_type_node,
22228 tree v2di_ftype_v2di
22229 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22231 tree v16qi_ftype_v8hi_v8hi
22232 = build_function_type_list (V16QI_type_node,
22233 V8HI_type_node, V8HI_type_node,
22235 tree v8hi_ftype_v4si_v4si
22236 = build_function_type_list (V8HI_type_node,
22237 V4SI_type_node, V4SI_type_node,
22239 tree v8hi_ftype_v16qi_v16qi
22240 = build_function_type_list (V8HI_type_node,
22241 V16QI_type_node, V16QI_type_node,
22243 tree v4hi_ftype_v8qi_v8qi
22244 = build_function_type_list (V4HI_type_node,
22245 V8QI_type_node, V8QI_type_node,
22247 tree unsigned_ftype_unsigned_uchar
22248 = build_function_type_list (unsigned_type_node,
22249 unsigned_type_node,
22250 unsigned_char_type_node,
22252 tree unsigned_ftype_unsigned_ushort
22253 = build_function_type_list (unsigned_type_node,
22254 unsigned_type_node,
22255 short_unsigned_type_node,
22257 tree unsigned_ftype_unsigned_unsigned
22258 = build_function_type_list (unsigned_type_node,
22259 unsigned_type_node,
22260 unsigned_type_node,
22262 tree uint64_ftype_uint64_uint64
22263 = build_function_type_list (long_long_unsigned_type_node,
22264 long_long_unsigned_type_node,
22265 long_long_unsigned_type_node,
22267 tree float_ftype_float
22268 = build_function_type_list (float_type_node,
22273 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22275 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22277 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22279 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22281 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22283 tree v8sf_ftype_v8sf
22284 = build_function_type_list (V8SF_type_node,
22287 tree v8si_ftype_v8sf
22288 = build_function_type_list (V8SI_type_node,
22291 tree v8sf_ftype_v8si
22292 = build_function_type_list (V8SF_type_node,
22295 tree v4si_ftype_v4df
22296 = build_function_type_list (V4SI_type_node,
22299 tree v4df_ftype_v4df
22300 = build_function_type_list (V4DF_type_node,
22303 tree v4df_ftype_v4si
22304 = build_function_type_list (V4DF_type_node,
22307 tree v4df_ftype_v4sf
22308 = build_function_type_list (V4DF_type_node,
22311 tree v4sf_ftype_v4df
22312 = build_function_type_list (V4SF_type_node,
22315 tree v8sf_ftype_v8sf_v8sf
22316 = build_function_type_list (V8SF_type_node,
22317 V8SF_type_node, V8SF_type_node,
22319 tree v4df_ftype_v4df_v4df
22320 = build_function_type_list (V4DF_type_node,
22321 V4DF_type_node, V4DF_type_node,
22323 tree v8sf_ftype_v8sf_int
22324 = build_function_type_list (V8SF_type_node,
22325 V8SF_type_node, integer_type_node,
22327 tree v4si_ftype_v8si_int
22328 = build_function_type_list (V4SI_type_node,
22329 V8SI_type_node, integer_type_node,
22331 tree v4df_ftype_v4df_int
22332 = build_function_type_list (V4DF_type_node,
22333 V4DF_type_node, integer_type_node,
22335 tree v4sf_ftype_v8sf_int
22336 = build_function_type_list (V4SF_type_node,
22337 V8SF_type_node, integer_type_node,
22339 tree v2df_ftype_v4df_int
22340 = build_function_type_list (V2DF_type_node,
22341 V4DF_type_node, integer_type_node,
22343 tree v8sf_ftype_v8sf_v8sf_int
22344 = build_function_type_list (V8SF_type_node,
22345 V8SF_type_node, V8SF_type_node,
22348 tree v8sf_ftype_v8sf_v8sf_v8sf
22349 = build_function_type_list (V8SF_type_node,
22350 V8SF_type_node, V8SF_type_node,
22353 tree v4df_ftype_v4df_v4df_v4df
22354 = build_function_type_list (V4DF_type_node,
22355 V4DF_type_node, V4DF_type_node,
22358 tree v8si_ftype_v8si_v8si_int
22359 = build_function_type_list (V8SI_type_node,
22360 V8SI_type_node, V8SI_type_node,
22363 tree v4df_ftype_v4df_v4df_int
22364 = build_function_type_list (V4DF_type_node,
22365 V4DF_type_node, V4DF_type_node,
22368 tree v8sf_ftype_pcfloat
22369 = build_function_type_list (V8SF_type_node,
22372 tree v4df_ftype_pcdouble
22373 = build_function_type_list (V4DF_type_node,
22374 pcdouble_type_node,
22376 tree pcv4sf_type_node
22377 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22378 tree pcv2df_type_node
22379 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22380 tree v8sf_ftype_pcv4sf
22381 = build_function_type_list (V8SF_type_node,
22384 tree v4df_ftype_pcv2df
22385 = build_function_type_list (V4DF_type_node,
22388 tree v32qi_ftype_pcchar
22389 = build_function_type_list (V32QI_type_node,
22392 tree void_ftype_pchar_v32qi
22393 = build_function_type_list (void_type_node,
22394 pchar_type_node, V32QI_type_node,
22396 tree v8si_ftype_v8si_v4si_int
22397 = build_function_type_list (V8SI_type_node,
22398 V8SI_type_node, V4SI_type_node,
22401 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22402 tree void_ftype_pv4di_v4di
22403 = build_function_type_list (void_type_node,
22404 pv4di_type_node, V4DI_type_node,
22406 tree v8sf_ftype_v8sf_v4sf_int
22407 = build_function_type_list (V8SF_type_node,
22408 V8SF_type_node, V4SF_type_node,
22411 tree v4df_ftype_v4df_v2df_int
22412 = build_function_type_list (V4DF_type_node,
22413 V4DF_type_node, V2DF_type_node,
22416 tree void_ftype_pfloat_v8sf
22417 = build_function_type_list (void_type_node,
22418 pfloat_type_node, V8SF_type_node,
22420 tree void_ftype_pdouble_v4df
22421 = build_function_type_list (void_type_node,
22422 pdouble_type_node, V4DF_type_node,
22424 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22425 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22426 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22427 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22428 tree pcv8sf_type_node
22429 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22430 tree pcv4df_type_node
22431 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22432 tree v8sf_ftype_pcv8sf_v8sf
22433 = build_function_type_list (V8SF_type_node,
22434 pcv8sf_type_node, V8SF_type_node,
22436 tree v4df_ftype_pcv4df_v4df
22437 = build_function_type_list (V4DF_type_node,
22438 pcv4df_type_node, V4DF_type_node,
22440 tree v4sf_ftype_pcv4sf_v4sf
22441 = build_function_type_list (V4SF_type_node,
22442 pcv4sf_type_node, V4SF_type_node,
22444 tree v2df_ftype_pcv2df_v2df
22445 = build_function_type_list (V2DF_type_node,
22446 pcv2df_type_node, V2DF_type_node,
22448 tree void_ftype_pv8sf_v8sf_v8sf
22449 = build_function_type_list (void_type_node,
22450 pv8sf_type_node, V8SF_type_node,
22453 tree void_ftype_pv4df_v4df_v4df
22454 = build_function_type_list (void_type_node,
22455 pv4df_type_node, V4DF_type_node,
22458 tree void_ftype_pv4sf_v4sf_v4sf
22459 = build_function_type_list (void_type_node,
22460 pv4sf_type_node, V4SF_type_node,
22463 tree void_ftype_pv2df_v2df_v2df
22464 = build_function_type_list (void_type_node,
22465 pv2df_type_node, V2DF_type_node,
22468 tree v4df_ftype_v2df
22469 = build_function_type_list (V4DF_type_node,
22472 tree v8sf_ftype_v4sf
22473 = build_function_type_list (V8SF_type_node,
22476 tree v8si_ftype_v4si
22477 = build_function_type_list (V8SI_type_node,
22480 tree v2df_ftype_v4df
22481 = build_function_type_list (V2DF_type_node,
22484 tree v4sf_ftype_v8sf
22485 = build_function_type_list (V4SF_type_node,
22488 tree v4si_ftype_v8si
22489 = build_function_type_list (V4SI_type_node,
22492 tree int_ftype_v4df
22493 = build_function_type_list (integer_type_node,
22496 tree int_ftype_v8sf
22497 = build_function_type_list (integer_type_node,
22500 tree int_ftype_v8sf_v8sf
22501 = build_function_type_list (integer_type_node,
22502 V8SF_type_node, V8SF_type_node,
22504 tree int_ftype_v4di_v4di
22505 = build_function_type_list (integer_type_node,
22506 V4DI_type_node, V4DI_type_node,
22508 tree int_ftype_v4df_v4df
22509 = build_function_type_list (integer_type_node,
22510 V4DF_type_node, V4DF_type_node,
22512 tree v8sf_ftype_v8sf_v8si
22513 = build_function_type_list (V8SF_type_node,
22514 V8SF_type_node, V8SI_type_node,
22516 tree v4df_ftype_v4df_v4di
22517 = build_function_type_list (V4DF_type_node,
22518 V4DF_type_node, V4DI_type_node,
22520 tree v4sf_ftype_v4sf_v4si
22521 = build_function_type_list (V4SF_type_node,
22522 V4SF_type_node, V4SI_type_node, NULL_TREE);
22523 tree v2df_ftype_v2df_v2di
22524 = build_function_type_list (V2DF_type_node,
22525 V2DF_type_node, V2DI_type_node, NULL_TREE);
22529 /* Add all special builtins with variable number of operands. */
22530 for (i = 0, d = bdesc_special_args;
22531 i < ARRAY_SIZE (bdesc_special_args);
22539 switch ((enum ix86_special_builtin_type) d->flag)
22541 case VOID_FTYPE_VOID:
22542 type = void_ftype_void;
22544 case V32QI_FTYPE_PCCHAR:
22545 type = v32qi_ftype_pcchar;
22547 case V16QI_FTYPE_PCCHAR:
22548 type = v16qi_ftype_pcchar;
22550 case V8SF_FTYPE_PCV4SF:
22551 type = v8sf_ftype_pcv4sf;
22553 case V8SF_FTYPE_PCFLOAT:
22554 type = v8sf_ftype_pcfloat;
22556 case V4DF_FTYPE_PCV2DF:
22557 type = v4df_ftype_pcv2df;
22559 case V4DF_FTYPE_PCDOUBLE:
22560 type = v4df_ftype_pcdouble;
22562 case V4SF_FTYPE_PCFLOAT:
22563 type = v4sf_ftype_pcfloat;
22565 case V2DI_FTYPE_PV2DI:
22566 type = v2di_ftype_pv2di;
22568 case V2DF_FTYPE_PCDOUBLE:
22569 type = v2df_ftype_pcdouble;
22571 case V8SF_FTYPE_PCV8SF_V8SF:
22572 type = v8sf_ftype_pcv8sf_v8sf;
22574 case V4DF_FTYPE_PCV4DF_V4DF:
22575 type = v4df_ftype_pcv4df_v4df;
22577 case V4SF_FTYPE_V4SF_PCV2SF:
22578 type = v4sf_ftype_v4sf_pcv2sf;
22580 case V4SF_FTYPE_PCV4SF_V4SF:
22581 type = v4sf_ftype_pcv4sf_v4sf;
22583 case V2DF_FTYPE_V2DF_PCDOUBLE:
22584 type = v2df_ftype_v2df_pcdouble;
22586 case V2DF_FTYPE_PCV2DF_V2DF:
22587 type = v2df_ftype_pcv2df_v2df;
22589 case VOID_FTYPE_PV2SF_V4SF:
22590 type = void_ftype_pv2sf_v4sf;
22592 case VOID_FTYPE_PV4DI_V4DI:
22593 type = void_ftype_pv4di_v4di;
22595 case VOID_FTYPE_PV2DI_V2DI:
22596 type = void_ftype_pv2di_v2di;
22598 case VOID_FTYPE_PCHAR_V32QI:
22599 type = void_ftype_pchar_v32qi;
22601 case VOID_FTYPE_PCHAR_V16QI:
22602 type = void_ftype_pchar_v16qi;
22604 case VOID_FTYPE_PFLOAT_V8SF:
22605 type = void_ftype_pfloat_v8sf;
22607 case VOID_FTYPE_PFLOAT_V4SF:
22608 type = void_ftype_pfloat_v4sf;
22610 case VOID_FTYPE_PDOUBLE_V4DF:
22611 type = void_ftype_pdouble_v4df;
22613 case VOID_FTYPE_PDOUBLE_V2DF:
22614 type = void_ftype_pdouble_v2df;
22616 case VOID_FTYPE_PDI_DI:
22617 type = void_ftype_pdi_di;
22619 case VOID_FTYPE_PINT_INT:
22620 type = void_ftype_pint_int;
22622 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22623 type = void_ftype_pv8sf_v8sf_v8sf;
22625 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22626 type = void_ftype_pv4df_v4df_v4df;
22628 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22629 type = void_ftype_pv4sf_v4sf_v4sf;
22631 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22632 type = void_ftype_pv2df_v2df_v2df;
22635 gcc_unreachable ();
22638 def_builtin (d->mask, d->name, type, d->code);
22641 /* Add all builtins with variable number of operands. */
22642 for (i = 0, d = bdesc_args;
22643 i < ARRAY_SIZE (bdesc_args);
22651 switch ((enum ix86_builtin_type) d->flag)
22653 case FLOAT_FTYPE_FLOAT:
22654 type = float_ftype_float;
22656 case INT_FTYPE_V8SF_V8SF_PTEST:
22657 type = int_ftype_v8sf_v8sf;
22659 case INT_FTYPE_V4DI_V4DI_PTEST:
22660 type = int_ftype_v4di_v4di;
22662 case INT_FTYPE_V4DF_V4DF_PTEST:
22663 type = int_ftype_v4df_v4df;
22665 case INT_FTYPE_V4SF_V4SF_PTEST:
22666 type = int_ftype_v4sf_v4sf;
22668 case INT_FTYPE_V2DI_V2DI_PTEST:
22669 type = int_ftype_v2di_v2di;
22671 case INT_FTYPE_V2DF_V2DF_PTEST:
22672 type = int_ftype_v2df_v2df;
22674 case INT64_FTYPE_V4SF:
22675 type = int64_ftype_v4sf;
22677 case INT64_FTYPE_V2DF:
22678 type = int64_ftype_v2df;
22680 case INT_FTYPE_V16QI:
22681 type = int_ftype_v16qi;
22683 case INT_FTYPE_V8QI:
22684 type = int_ftype_v8qi;
22686 case INT_FTYPE_V8SF:
22687 type = int_ftype_v8sf;
22689 case INT_FTYPE_V4DF:
22690 type = int_ftype_v4df;
22692 case INT_FTYPE_V4SF:
22693 type = int_ftype_v4sf;
22695 case INT_FTYPE_V2DF:
22696 type = int_ftype_v2df;
22698 case V16QI_FTYPE_V16QI:
22699 type = v16qi_ftype_v16qi;
22701 case V8SI_FTYPE_V8SF:
22702 type = v8si_ftype_v8sf;
22704 case V8SI_FTYPE_V4SI:
22705 type = v8si_ftype_v4si;
22707 case V8HI_FTYPE_V8HI:
22708 type = v8hi_ftype_v8hi;
22710 case V8HI_FTYPE_V16QI:
22711 type = v8hi_ftype_v16qi;
22713 case V8QI_FTYPE_V8QI:
22714 type = v8qi_ftype_v8qi;
22716 case V8SF_FTYPE_V8SF:
22717 type = v8sf_ftype_v8sf;
22719 case V8SF_FTYPE_V8SI:
22720 type = v8sf_ftype_v8si;
22722 case V8SF_FTYPE_V4SF:
22723 type = v8sf_ftype_v4sf;
22725 case V4SI_FTYPE_V4DF:
22726 type = v4si_ftype_v4df;
22728 case V4SI_FTYPE_V4SI:
22729 type = v4si_ftype_v4si;
22731 case V4SI_FTYPE_V16QI:
22732 type = v4si_ftype_v16qi;
22734 case V4SI_FTYPE_V8SI:
22735 type = v4si_ftype_v8si;
22737 case V4SI_FTYPE_V8HI:
22738 type = v4si_ftype_v8hi;
22740 case V4SI_FTYPE_V4SF:
22741 type = v4si_ftype_v4sf;
22743 case V4SI_FTYPE_V2DF:
22744 type = v4si_ftype_v2df;
22746 case V4HI_FTYPE_V4HI:
22747 type = v4hi_ftype_v4hi;
22749 case V4DF_FTYPE_V4DF:
22750 type = v4df_ftype_v4df;
22752 case V4DF_FTYPE_V4SI:
22753 type = v4df_ftype_v4si;
22755 case V4DF_FTYPE_V4SF:
22756 type = v4df_ftype_v4sf;
22758 case V4DF_FTYPE_V2DF:
22759 type = v4df_ftype_v2df;
22761 case V4SF_FTYPE_V4SF:
22762 case V4SF_FTYPE_V4SF_VEC_MERGE:
22763 type = v4sf_ftype_v4sf;
22765 case V4SF_FTYPE_V8SF:
22766 type = v4sf_ftype_v8sf;
22768 case V4SF_FTYPE_V4SI:
22769 type = v4sf_ftype_v4si;
22771 case V4SF_FTYPE_V4DF:
22772 type = v4sf_ftype_v4df;
22774 case V4SF_FTYPE_V2DF:
22775 type = v4sf_ftype_v2df;
22777 case V2DI_FTYPE_V2DI:
22778 type = v2di_ftype_v2di;
22780 case V2DI_FTYPE_V16QI:
22781 type = v2di_ftype_v16qi;
22783 case V2DI_FTYPE_V8HI:
22784 type = v2di_ftype_v8hi;
22786 case V2DI_FTYPE_V4SI:
22787 type = v2di_ftype_v4si;
22789 case V2SI_FTYPE_V2SI:
22790 type = v2si_ftype_v2si;
22792 case V2SI_FTYPE_V4SF:
22793 type = v2si_ftype_v4sf;
22795 case V2SI_FTYPE_V2DF:
22796 type = v2si_ftype_v2df;
22798 case V2SI_FTYPE_V2SF:
22799 type = v2si_ftype_v2sf;
22801 case V2DF_FTYPE_V4DF:
22802 type = v2df_ftype_v4df;
22804 case V2DF_FTYPE_V4SF:
22805 type = v2df_ftype_v4sf;
22807 case V2DF_FTYPE_V2DF:
22808 case V2DF_FTYPE_V2DF_VEC_MERGE:
22809 type = v2df_ftype_v2df;
22811 case V2DF_FTYPE_V2SI:
22812 type = v2df_ftype_v2si;
22814 case V2DF_FTYPE_V4SI:
22815 type = v2df_ftype_v4si;
22817 case V2SF_FTYPE_V2SF:
22818 type = v2sf_ftype_v2sf;
22820 case V2SF_FTYPE_V2SI:
22821 type = v2sf_ftype_v2si;
22823 case V16QI_FTYPE_V16QI_V16QI:
22824 type = v16qi_ftype_v16qi_v16qi;
22826 case V16QI_FTYPE_V8HI_V8HI:
22827 type = v16qi_ftype_v8hi_v8hi;
22829 case V8QI_FTYPE_V8QI_V8QI:
22830 type = v8qi_ftype_v8qi_v8qi;
22832 case V8QI_FTYPE_V4HI_V4HI:
22833 type = v8qi_ftype_v4hi_v4hi;
22835 case V8HI_FTYPE_V8HI_V8HI:
22836 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22837 type = v8hi_ftype_v8hi_v8hi;
22839 case V8HI_FTYPE_V16QI_V16QI:
22840 type = v8hi_ftype_v16qi_v16qi;
22842 case V8HI_FTYPE_V4SI_V4SI:
22843 type = v8hi_ftype_v4si_v4si;
22845 case V8HI_FTYPE_V8HI_SI_COUNT:
22846 type = v8hi_ftype_v8hi_int;
22848 case V8SF_FTYPE_V8SF_V8SF:
22849 type = v8sf_ftype_v8sf_v8sf;
22851 case V8SF_FTYPE_V8SF_V8SI:
22852 type = v8sf_ftype_v8sf_v8si;
22854 case V4SI_FTYPE_V4SI_V4SI:
22855 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22856 type = v4si_ftype_v4si_v4si;
22858 case V4SI_FTYPE_V8HI_V8HI:
22859 type = v4si_ftype_v8hi_v8hi;
22861 case V4SI_FTYPE_V4SF_V4SF:
22862 type = v4si_ftype_v4sf_v4sf;
22864 case V4SI_FTYPE_V2DF_V2DF:
22865 type = v4si_ftype_v2df_v2df;
22867 case V4SI_FTYPE_V4SI_SI_COUNT:
22868 type = v4si_ftype_v4si_int;
22870 case V4HI_FTYPE_V4HI_V4HI:
22871 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22872 type = v4hi_ftype_v4hi_v4hi;
22874 case V4HI_FTYPE_V8QI_V8QI:
22875 type = v4hi_ftype_v8qi_v8qi;
22877 case V4HI_FTYPE_V2SI_V2SI:
22878 type = v4hi_ftype_v2si_v2si;
22880 case V4HI_FTYPE_V4HI_SI_COUNT:
22881 type = v4hi_ftype_v4hi_int;
22883 case V4DF_FTYPE_V4DF_V4DF:
22884 type = v4df_ftype_v4df_v4df;
22886 case V4DF_FTYPE_V4DF_V4DI:
22887 type = v4df_ftype_v4df_v4di;
22889 case V4SF_FTYPE_V4SF_V4SF:
22890 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22891 type = v4sf_ftype_v4sf_v4sf;
22893 case V4SF_FTYPE_V4SF_V4SI:
22894 type = v4sf_ftype_v4sf_v4si;
22896 case V4SF_FTYPE_V4SF_V2SI:
22897 type = v4sf_ftype_v4sf_v2si;
22899 case V4SF_FTYPE_V4SF_V2DF:
22900 type = v4sf_ftype_v4sf_v2df;
22902 case V4SF_FTYPE_V4SF_DI:
22903 type = v4sf_ftype_v4sf_int64;
22905 case V4SF_FTYPE_V4SF_SI:
22906 type = v4sf_ftype_v4sf_int;
22908 case V2DI_FTYPE_V2DI_V2DI:
22909 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22910 type = v2di_ftype_v2di_v2di;
22912 case V2DI_FTYPE_V16QI_V16QI:
22913 type = v2di_ftype_v16qi_v16qi;
22915 case V2DI_FTYPE_V4SI_V4SI:
22916 type = v2di_ftype_v4si_v4si;
22918 case V2DI_FTYPE_V2DI_V16QI:
22919 type = v2di_ftype_v2di_v16qi;
22921 case V2DI_FTYPE_V2DF_V2DF:
22922 type = v2di_ftype_v2df_v2df;
22924 case V2DI_FTYPE_V2DI_SI_COUNT:
22925 type = v2di_ftype_v2di_int;
22927 case V2SI_FTYPE_V2SI_V2SI:
22928 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22929 type = v2si_ftype_v2si_v2si;
22931 case V2SI_FTYPE_V4HI_V4HI:
22932 type = v2si_ftype_v4hi_v4hi;
22934 case V2SI_FTYPE_V2SF_V2SF:
22935 type = v2si_ftype_v2sf_v2sf;
22937 case V2SI_FTYPE_V2SI_SI_COUNT:
22938 type = v2si_ftype_v2si_int;
22940 case V2DF_FTYPE_V2DF_V2DF:
22941 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22942 type = v2df_ftype_v2df_v2df;
22944 case V2DF_FTYPE_V2DF_V4SF:
22945 type = v2df_ftype_v2df_v4sf;
22947 case V2DF_FTYPE_V2DF_V2DI:
22948 type = v2df_ftype_v2df_v2di;
22950 case V2DF_FTYPE_V2DF_DI:
22951 type = v2df_ftype_v2df_int64;
22953 case V2DF_FTYPE_V2DF_SI:
22954 type = v2df_ftype_v2df_int;
22956 case V2SF_FTYPE_V2SF_V2SF:
22957 type = v2sf_ftype_v2sf_v2sf;
22959 case V1DI_FTYPE_V1DI_V1DI:
22960 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22961 type = v1di_ftype_v1di_v1di;
22963 case V1DI_FTYPE_V8QI_V8QI:
22964 type = v1di_ftype_v8qi_v8qi;
22966 case V1DI_FTYPE_V2SI_V2SI:
22967 type = v1di_ftype_v2si_v2si;
22969 case V1DI_FTYPE_V1DI_SI_COUNT:
22970 type = v1di_ftype_v1di_int;
22972 case UINT64_FTYPE_UINT64_UINT64:
22973 type = uint64_ftype_uint64_uint64;
22975 case UINT_FTYPE_UINT_UINT:
22976 type = unsigned_ftype_unsigned_unsigned;
22978 case UINT_FTYPE_UINT_USHORT:
22979 type = unsigned_ftype_unsigned_ushort;
22981 case UINT_FTYPE_UINT_UCHAR:
22982 type = unsigned_ftype_unsigned_uchar;
22984 case V8HI_FTYPE_V8HI_INT:
22985 type = v8hi_ftype_v8hi_int;
22987 case V8SF_FTYPE_V8SF_INT:
22988 type = v8sf_ftype_v8sf_int;
22990 case V4SI_FTYPE_V4SI_INT:
22991 type = v4si_ftype_v4si_int;
22993 case V4SI_FTYPE_V8SI_INT:
22994 type = v4si_ftype_v8si_int;
22996 case V4HI_FTYPE_V4HI_INT:
22997 type = v4hi_ftype_v4hi_int;
22999 case V4DF_FTYPE_V4DF_INT:
23000 type = v4df_ftype_v4df_int;
23002 case V4SF_FTYPE_V4SF_INT:
23003 type = v4sf_ftype_v4sf_int;
23005 case V4SF_FTYPE_V8SF_INT:
23006 type = v4sf_ftype_v8sf_int;
23008 case V2DI_FTYPE_V2DI_INT:
23009 case V2DI2TI_FTYPE_V2DI_INT:
23010 type = v2di_ftype_v2di_int;
23012 case V2DF_FTYPE_V2DF_INT:
23013 type = v2df_ftype_v2df_int;
23015 case V2DF_FTYPE_V4DF_INT:
23016 type = v2df_ftype_v4df_int;
23018 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23019 type = v16qi_ftype_v16qi_v16qi_v16qi;
23021 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23022 type = v8sf_ftype_v8sf_v8sf_v8sf;
23024 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23025 type = v4df_ftype_v4df_v4df_v4df;
23027 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23028 type = v4sf_ftype_v4sf_v4sf_v4sf;
23030 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23031 type = v2df_ftype_v2df_v2df_v2df;
23033 case V16QI_FTYPE_V16QI_V16QI_INT:
23034 type = v16qi_ftype_v16qi_v16qi_int;
23036 case V8SI_FTYPE_V8SI_V8SI_INT:
23037 type = v8si_ftype_v8si_v8si_int;
23039 case V8SI_FTYPE_V8SI_V4SI_INT:
23040 type = v8si_ftype_v8si_v4si_int;
23042 case V8HI_FTYPE_V8HI_V8HI_INT:
23043 type = v8hi_ftype_v8hi_v8hi_int;
23045 case V8SF_FTYPE_V8SF_V8SF_INT:
23046 type = v8sf_ftype_v8sf_v8sf_int;
23048 case V8SF_FTYPE_V8SF_V4SF_INT:
23049 type = v8sf_ftype_v8sf_v4sf_int;
23051 case V4SI_FTYPE_V4SI_V4SI_INT:
23052 type = v4si_ftype_v4si_v4si_int;
23054 case V4DF_FTYPE_V4DF_V4DF_INT:
23055 type = v4df_ftype_v4df_v4df_int;
23057 case V4DF_FTYPE_V4DF_V2DF_INT:
23058 type = v4df_ftype_v4df_v2df_int;
23060 case V4SF_FTYPE_V4SF_V4SF_INT:
23061 type = v4sf_ftype_v4sf_v4sf_int;
23063 case V2DI_FTYPE_V2DI_V2DI_INT:
23064 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23065 type = v2di_ftype_v2di_v2di_int;
23067 case V2DF_FTYPE_V2DF_V2DF_INT:
23068 type = v2df_ftype_v2df_v2df_int;
23070 case V2DI_FTYPE_V2DI_UINT_UINT:
23071 type = v2di_ftype_v2di_unsigned_unsigned;
23073 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23074 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23076 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23077 type = v1di_ftype_v1di_v1di_int;
23080 gcc_unreachable ();
23083 def_builtin_const (d->mask, d->name, type, d->code);
23086 /* pcmpestr[im] insns. */
23087 for (i = 0, d = bdesc_pcmpestr;
23088 i < ARRAY_SIZE (bdesc_pcmpestr);
23091 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23092 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23094 ftype = int_ftype_v16qi_int_v16qi_int_int;
23095 def_builtin_const (d->mask, d->name, ftype, d->code);
23098 /* pcmpistr[im] insns. */
23099 for (i = 0, d = bdesc_pcmpistr;
23100 i < ARRAY_SIZE (bdesc_pcmpistr);
23103 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23104 ftype = v16qi_ftype_v16qi_v16qi_int;
23106 ftype = int_ftype_v16qi_v16qi_int;
23107 def_builtin_const (d->mask, d->name, ftype, d->code);
23110 /* comi/ucomi insns. */
23111 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23112 if (d->mask == OPTION_MASK_ISA_SSE2)
23113 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23115 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23118 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23119 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23121 /* SSE or 3DNow!A */
23122 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23125 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23127 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23128 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23131 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23132 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23135 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23136 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23137 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23138 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23139 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23140 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23143 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23146 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23147 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23149 /* Access to the vec_init patterns. */
23150 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23151 integer_type_node, NULL_TREE);
23152 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23154 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23155 short_integer_type_node,
23156 short_integer_type_node,
23157 short_integer_type_node, NULL_TREE);
23158 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23160 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23161 char_type_node, char_type_node,
23162 char_type_node, char_type_node,
23163 char_type_node, char_type_node,
23164 char_type_node, NULL_TREE);
23165 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23167 /* Access to the vec_extract patterns. */
23168 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23169 integer_type_node, NULL_TREE);
23170 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23172 ftype = build_function_type_list (long_long_integer_type_node,
23173 V2DI_type_node, integer_type_node,
23175 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23177 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23178 integer_type_node, NULL_TREE);
23179 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23181 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23182 integer_type_node, NULL_TREE);
23183 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23185 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23186 integer_type_node, NULL_TREE);
23187 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23189 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23190 integer_type_node, NULL_TREE);
23191 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23193 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23194 integer_type_node, NULL_TREE);
23195 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23197 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23198 integer_type_node, NULL_TREE);
23199 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23201 /* Access to the vec_set patterns. */
23202 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23204 integer_type_node, NULL_TREE);
23205 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23207 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23209 integer_type_node, NULL_TREE);
23210 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23212 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23214 integer_type_node, NULL_TREE);
23215 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23217 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23219 integer_type_node, NULL_TREE);
23220 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23222 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23224 integer_type_node, NULL_TREE);
23225 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23227 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23229 integer_type_node, NULL_TREE);
23230 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23232 /* Add SSE5 multi-arg argument instructions */
23233 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23235 tree mtype = NULL_TREE;
23240 switch ((enum multi_arg_type)d->flag)
23242 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23243 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23244 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23245 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23246 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23247 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23248 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23249 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23250 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23251 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23252 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23253 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23254 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23255 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23256 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23257 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23258 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23259 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23260 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23261 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23262 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23263 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23264 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23265 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23266 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23267 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23268 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23269 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23270 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23271 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23272 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23273 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23274 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23275 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23276 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23277 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23278 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23279 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23280 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23281 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23282 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23283 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23284 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23285 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23286 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23287 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23288 case MULTI_ARG_UNKNOWN:
23290 gcc_unreachable ();
23294 def_builtin_const (d->mask, d->name, mtype, d->code);
23298 /* Internal method for ix86_init_builtins. */
23301 ix86_init_builtins_va_builtins_abi (void)
23303 tree ms_va_ref, sysv_va_ref;
23304 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23305 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23306 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23307 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23311 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23312 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23313 ms_va_ref = build_reference_type (ms_va_list_type_node);
23315 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23318 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23319 fnvoid_va_start_ms =
23320 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23321 fnvoid_va_end_sysv =
23322 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23323 fnvoid_va_start_sysv =
23324 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23326 fnvoid_va_copy_ms =
23327 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23329 fnvoid_va_copy_sysv =
23330 build_function_type_list (void_type_node, sysv_va_ref,
23331 sysv_va_ref, NULL_TREE);
23333 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23334 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23335 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23336 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23337 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23338 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23339 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23340 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23341 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23342 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23343 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23344 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23348 ix86_init_builtins (void)
23350 tree float128_type_node = make_node (REAL_TYPE);
23353 /* The __float80 type. */
23354 if (TYPE_MODE (long_double_type_node) == XFmode)
23355 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23359 /* The __float80 type. */
23360 tree float80_type_node = make_node (REAL_TYPE);
23362 TYPE_PRECISION (float80_type_node) = 80;
23363 layout_type (float80_type_node);
23364 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23368 /* The __float128 type. */
23369 TYPE_PRECISION (float128_type_node) = 128;
23370 layout_type (float128_type_node);
23371 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23374 /* TFmode support builtins. */
23375 ftype = build_function_type (float128_type_node, void_list_node);
23376 decl = add_builtin_function ("__builtin_infq", ftype,
23377 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23379 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23381 /* We will expand them to normal call if SSE2 isn't available since
23382 they are used by libgcc. */
23383 ftype = build_function_type_list (float128_type_node,
23384 float128_type_node,
23386 decl = add_builtin_function ("__builtin_fabsq", ftype,
23387 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23388 "__fabstf2", NULL_TREE);
23389 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23390 TREE_READONLY (decl) = 1;
23392 ftype = build_function_type_list (float128_type_node,
23393 float128_type_node,
23394 float128_type_node,
23396 decl = add_builtin_function ("__builtin_copysignq", ftype,
23397 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23398 "__copysigntf3", NULL_TREE);
23399 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23400 TREE_READONLY (decl) = 1;
23402 ix86_init_mmx_sse_builtins ();
23404 ix86_init_builtins_va_builtins_abi ();
23407 /* Errors in the source file can cause expand_expr to return const0_rtx
23408 where we expect a vector. To avoid crashing, use one of the vector
23409 clear instructions. */
23411 safe_vector_operand (rtx x, enum machine_mode mode)
23413 if (x == const0_rtx)
23414 x = CONST0_RTX (mode);
23418 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23421 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23424 tree arg0 = CALL_EXPR_ARG (exp, 0);
23425 tree arg1 = CALL_EXPR_ARG (exp, 1);
23426 rtx op0 = expand_normal (arg0);
23427 rtx op1 = expand_normal (arg1);
23428 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23429 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23430 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23432 if (VECTOR_MODE_P (mode0))
23433 op0 = safe_vector_operand (op0, mode0);
23434 if (VECTOR_MODE_P (mode1))
23435 op1 = safe_vector_operand (op1, mode1);
23437 if (optimize || !target
23438 || GET_MODE (target) != tmode
23439 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23440 target = gen_reg_rtx (tmode);
23442 if (GET_MODE (op1) == SImode && mode1 == TImode)
23444 rtx x = gen_reg_rtx (V4SImode);
23445 emit_insn (gen_sse2_loadd (x, op1));
23446 op1 = gen_lowpart (TImode, x);
23449 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23450 op0 = copy_to_mode_reg (mode0, op0);
23451 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23452 op1 = copy_to_mode_reg (mode1, op1);
23454 pat = GEN_FCN (icode) (target, op0, op1);
23463 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23466 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23467 enum multi_arg_type m_type,
23468 enum insn_code sub_code)
23473 bool comparison_p = false;
23475 bool last_arg_constant = false;
23476 int num_memory = 0;
23479 enum machine_mode mode;
23482 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23486 case MULTI_ARG_3_SF:
23487 case MULTI_ARG_3_DF:
23488 case MULTI_ARG_3_DI:
23489 case MULTI_ARG_3_SI:
23490 case MULTI_ARG_3_SI_DI:
23491 case MULTI_ARG_3_HI:
23492 case MULTI_ARG_3_HI_SI:
23493 case MULTI_ARG_3_QI:
23494 case MULTI_ARG_3_PERMPS:
23495 case MULTI_ARG_3_PERMPD:
23499 case MULTI_ARG_2_SF:
23500 case MULTI_ARG_2_DF:
23501 case MULTI_ARG_2_DI:
23502 case MULTI_ARG_2_SI:
23503 case MULTI_ARG_2_HI:
23504 case MULTI_ARG_2_QI:
23508 case MULTI_ARG_2_DI_IMM:
23509 case MULTI_ARG_2_SI_IMM:
23510 case MULTI_ARG_2_HI_IMM:
23511 case MULTI_ARG_2_QI_IMM:
23513 last_arg_constant = true;
23516 case MULTI_ARG_1_SF:
23517 case MULTI_ARG_1_DF:
23518 case MULTI_ARG_1_DI:
23519 case MULTI_ARG_1_SI:
23520 case MULTI_ARG_1_HI:
23521 case MULTI_ARG_1_QI:
23522 case MULTI_ARG_1_SI_DI:
23523 case MULTI_ARG_1_HI_DI:
23524 case MULTI_ARG_1_HI_SI:
23525 case MULTI_ARG_1_QI_DI:
23526 case MULTI_ARG_1_QI_SI:
23527 case MULTI_ARG_1_QI_HI:
23528 case MULTI_ARG_1_PH2PS:
23529 case MULTI_ARG_1_PS2PH:
23533 case MULTI_ARG_2_SF_CMP:
23534 case MULTI_ARG_2_DF_CMP:
23535 case MULTI_ARG_2_DI_CMP:
23536 case MULTI_ARG_2_SI_CMP:
23537 case MULTI_ARG_2_HI_CMP:
23538 case MULTI_ARG_2_QI_CMP:
23540 comparison_p = true;
23543 case MULTI_ARG_2_SF_TF:
23544 case MULTI_ARG_2_DF_TF:
23545 case MULTI_ARG_2_DI_TF:
23546 case MULTI_ARG_2_SI_TF:
23547 case MULTI_ARG_2_HI_TF:
23548 case MULTI_ARG_2_QI_TF:
23553 case MULTI_ARG_UNKNOWN:
23555 gcc_unreachable ();
23558 if (optimize || !target
23559 || GET_MODE (target) != tmode
23560 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23561 target = gen_reg_rtx (tmode);
23563 gcc_assert (nargs <= 4);
23565 for (i = 0; i < nargs; i++)
23567 tree arg = CALL_EXPR_ARG (exp, i);
23568 rtx op = expand_normal (arg);
23569 int adjust = (comparison_p) ? 1 : 0;
23570 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23572 if (last_arg_constant && i == nargs-1)
23574 if (GET_CODE (op) != CONST_INT)
23576 error ("last argument must be an immediate");
23577 return gen_reg_rtx (tmode);
23582 if (VECTOR_MODE_P (mode))
23583 op = safe_vector_operand (op, mode);
23585 /* If we aren't optimizing, only allow one memory operand to be
23587 if (memory_operand (op, mode))
23590 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23593 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23595 op = force_reg (mode, op);
23599 args[i].mode = mode;
23605 pat = GEN_FCN (icode) (target, args[0].op);
23610 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23611 GEN_INT ((int)sub_code));
23612 else if (! comparison_p)
23613 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23616 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23620 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23625 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23629 gcc_unreachable ();
23639 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23640 insns with vec_merge. */
23643 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23647 tree arg0 = CALL_EXPR_ARG (exp, 0);
23648 rtx op1, op0 = expand_normal (arg0);
23649 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23650 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23652 if (optimize || !target
23653 || GET_MODE (target) != tmode
23654 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23655 target = gen_reg_rtx (tmode);
23657 if (VECTOR_MODE_P (mode0))
23658 op0 = safe_vector_operand (op0, mode0);
23660 if ((optimize && !register_operand (op0, mode0))
23661 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23662 op0 = copy_to_mode_reg (mode0, op0);
23665 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23666 op1 = copy_to_mode_reg (mode0, op1);
23668 pat = GEN_FCN (icode) (target, op0, op1);
23675 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23678 ix86_expand_sse_compare (const struct builtin_description *d,
23679 tree exp, rtx target, bool swap)
23682 tree arg0 = CALL_EXPR_ARG (exp, 0);
23683 tree arg1 = CALL_EXPR_ARG (exp, 1);
23684 rtx op0 = expand_normal (arg0);
23685 rtx op1 = expand_normal (arg1);
23687 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23688 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23689 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23690 enum rtx_code comparison = d->comparison;
23692 if (VECTOR_MODE_P (mode0))
23693 op0 = safe_vector_operand (op0, mode0);
23694 if (VECTOR_MODE_P (mode1))
23695 op1 = safe_vector_operand (op1, mode1);
23697 /* Swap operands if we have a comparison that isn't available in
23701 rtx tmp = gen_reg_rtx (mode1);
23702 emit_move_insn (tmp, op1);
23707 if (optimize || !target
23708 || GET_MODE (target) != tmode
23709 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23710 target = gen_reg_rtx (tmode);
23712 if ((optimize && !register_operand (op0, mode0))
23713 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23714 op0 = copy_to_mode_reg (mode0, op0);
23715 if ((optimize && !register_operand (op1, mode1))
23716 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23717 op1 = copy_to_mode_reg (mode1, op1);
23719 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23720 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23727 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23730 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23734 tree arg0 = CALL_EXPR_ARG (exp, 0);
23735 tree arg1 = CALL_EXPR_ARG (exp, 1);
23736 rtx op0 = expand_normal (arg0);
23737 rtx op1 = expand_normal (arg1);
23738 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23739 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23740 enum rtx_code comparison = d->comparison;
23742 if (VECTOR_MODE_P (mode0))
23743 op0 = safe_vector_operand (op0, mode0);
23744 if (VECTOR_MODE_P (mode1))
23745 op1 = safe_vector_operand (op1, mode1);
23747 /* Swap operands if we have a comparison that isn't available in
23749 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23756 target = gen_reg_rtx (SImode);
23757 emit_move_insn (target, const0_rtx);
23758 target = gen_rtx_SUBREG (QImode, target, 0);
23760 if ((optimize && !register_operand (op0, mode0))
23761 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23762 op0 = copy_to_mode_reg (mode0, op0);
23763 if ((optimize && !register_operand (op1, mode1))
23764 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23765 op1 = copy_to_mode_reg (mode1, op1);
23767 pat = GEN_FCN (d->icode) (op0, op1);
23771 emit_insn (gen_rtx_SET (VOIDmode,
23772 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23773 gen_rtx_fmt_ee (comparison, QImode,
23777 return SUBREG_REG (target);
23780 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23783 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23787 tree arg0 = CALL_EXPR_ARG (exp, 0);
23788 tree arg1 = CALL_EXPR_ARG (exp, 1);
23789 rtx op0 = expand_normal (arg0);
23790 rtx op1 = expand_normal (arg1);
23791 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23792 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23793 enum rtx_code comparison = d->comparison;
23795 if (VECTOR_MODE_P (mode0))
23796 op0 = safe_vector_operand (op0, mode0);
23797 if (VECTOR_MODE_P (mode1))
23798 op1 = safe_vector_operand (op1, mode1);
23800 target = gen_reg_rtx (SImode);
23801 emit_move_insn (target, const0_rtx);
23802 target = gen_rtx_SUBREG (QImode, target, 0);
23804 if ((optimize && !register_operand (op0, mode0))
23805 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23806 op0 = copy_to_mode_reg (mode0, op0);
23807 if ((optimize && !register_operand (op1, mode1))
23808 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23809 op1 = copy_to_mode_reg (mode1, op1);
23811 pat = GEN_FCN (d->icode) (op0, op1);
23815 emit_insn (gen_rtx_SET (VOIDmode,
23816 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23817 gen_rtx_fmt_ee (comparison, QImode,
23821 return SUBREG_REG (target);
23824 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23827 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23828 tree exp, rtx target)
23831 tree arg0 = CALL_EXPR_ARG (exp, 0);
23832 tree arg1 = CALL_EXPR_ARG (exp, 1);
23833 tree arg2 = CALL_EXPR_ARG (exp, 2);
23834 tree arg3 = CALL_EXPR_ARG (exp, 3);
23835 tree arg4 = CALL_EXPR_ARG (exp, 4);
23836 rtx scratch0, scratch1;
23837 rtx op0 = expand_normal (arg0);
23838 rtx op1 = expand_normal (arg1);
23839 rtx op2 = expand_normal (arg2);
23840 rtx op3 = expand_normal (arg3);
23841 rtx op4 = expand_normal (arg4);
23842 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23844 tmode0 = insn_data[d->icode].operand[0].mode;
23845 tmode1 = insn_data[d->icode].operand[1].mode;
23846 modev2 = insn_data[d->icode].operand[2].mode;
23847 modei3 = insn_data[d->icode].operand[3].mode;
23848 modev4 = insn_data[d->icode].operand[4].mode;
23849 modei5 = insn_data[d->icode].operand[5].mode;
23850 modeimm = insn_data[d->icode].operand[6].mode;
23852 if (VECTOR_MODE_P (modev2))
23853 op0 = safe_vector_operand (op0, modev2);
23854 if (VECTOR_MODE_P (modev4))
23855 op2 = safe_vector_operand (op2, modev4);
23857 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23858 op0 = copy_to_mode_reg (modev2, op0);
23859 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23860 op1 = copy_to_mode_reg (modei3, op1);
23861 if ((optimize && !register_operand (op2, modev4))
23862 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23863 op2 = copy_to_mode_reg (modev4, op2);
23864 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23865 op3 = copy_to_mode_reg (modei5, op3);
23867 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23869 error ("the fifth argument must be a 8-bit immediate");
23873 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23875 if (optimize || !target
23876 || GET_MODE (target) != tmode0
23877 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23878 target = gen_reg_rtx (tmode0);
23880 scratch1 = gen_reg_rtx (tmode1);
23882 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23884 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23886 if (optimize || !target
23887 || GET_MODE (target) != tmode1
23888 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23889 target = gen_reg_rtx (tmode1);
23891 scratch0 = gen_reg_rtx (tmode0);
23893 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23897 gcc_assert (d->flag);
23899 scratch0 = gen_reg_rtx (tmode0);
23900 scratch1 = gen_reg_rtx (tmode1);
23902 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23912 target = gen_reg_rtx (SImode);
23913 emit_move_insn (target, const0_rtx);
23914 target = gen_rtx_SUBREG (QImode, target, 0);
23917 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23918 gen_rtx_fmt_ee (EQ, QImode,
23919 gen_rtx_REG ((enum machine_mode) d->flag,
23922 return SUBREG_REG (target);
23929 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23932 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23933 tree exp, rtx target)
23936 tree arg0 = CALL_EXPR_ARG (exp, 0);
23937 tree arg1 = CALL_EXPR_ARG (exp, 1);
23938 tree arg2 = CALL_EXPR_ARG (exp, 2);
23939 rtx scratch0, scratch1;
23940 rtx op0 = expand_normal (arg0);
23941 rtx op1 = expand_normal (arg1);
23942 rtx op2 = expand_normal (arg2);
23943 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23945 tmode0 = insn_data[d->icode].operand[0].mode;
23946 tmode1 = insn_data[d->icode].operand[1].mode;
23947 modev2 = insn_data[d->icode].operand[2].mode;
23948 modev3 = insn_data[d->icode].operand[3].mode;
23949 modeimm = insn_data[d->icode].operand[4].mode;
23951 if (VECTOR_MODE_P (modev2))
23952 op0 = safe_vector_operand (op0, modev2);
23953 if (VECTOR_MODE_P (modev3))
23954 op1 = safe_vector_operand (op1, modev3);
23956 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23957 op0 = copy_to_mode_reg (modev2, op0);
23958 if ((optimize && !register_operand (op1, modev3))
23959 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23960 op1 = copy_to_mode_reg (modev3, op1);
23962 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23964 error ("the third argument must be a 8-bit immediate");
23968 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23970 if (optimize || !target
23971 || GET_MODE (target) != tmode0
23972 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23973 target = gen_reg_rtx (tmode0);
23975 scratch1 = gen_reg_rtx (tmode1);
23977 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23979 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23981 if (optimize || !target
23982 || GET_MODE (target) != tmode1
23983 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23984 target = gen_reg_rtx (tmode1);
23986 scratch0 = gen_reg_rtx (tmode0);
23988 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23992 gcc_assert (d->flag);
23994 scratch0 = gen_reg_rtx (tmode0);
23995 scratch1 = gen_reg_rtx (tmode1);
23997 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24007 target = gen_reg_rtx (SImode);
24008 emit_move_insn (target, const0_rtx);
24009 target = gen_rtx_SUBREG (QImode, target, 0);
24012 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24013 gen_rtx_fmt_ee (EQ, QImode,
24014 gen_rtx_REG ((enum machine_mode) d->flag,
24017 return SUBREG_REG (target);
24023 /* Subroutine of ix86_expand_builtin to take care of insns with
24024 variable number of operands. */
24027 ix86_expand_args_builtin (const struct builtin_description *d,
24028 tree exp, rtx target)
24030 rtx pat, real_target;
24031 unsigned int i, nargs;
24032 unsigned int nargs_constant = 0;
24033 int num_memory = 0;
24037 enum machine_mode mode;
24039 bool last_arg_count = false;
24040 enum insn_code icode = d->icode;
24041 const struct insn_data *insn_p = &insn_data[icode];
24042 enum machine_mode tmode = insn_p->operand[0].mode;
24043 enum machine_mode rmode = VOIDmode;
24045 enum rtx_code comparison = d->comparison;
24047 switch ((enum ix86_builtin_type) d->flag)
24049 case INT_FTYPE_V8SF_V8SF_PTEST:
24050 case INT_FTYPE_V4DI_V4DI_PTEST:
24051 case INT_FTYPE_V4DF_V4DF_PTEST:
24052 case INT_FTYPE_V4SF_V4SF_PTEST:
24053 case INT_FTYPE_V2DI_V2DI_PTEST:
24054 case INT_FTYPE_V2DF_V2DF_PTEST:
24055 return ix86_expand_sse_ptest (d, exp, target);
24056 case FLOAT128_FTYPE_FLOAT128:
24057 case FLOAT_FTYPE_FLOAT:
24058 case INT64_FTYPE_V4SF:
24059 case INT64_FTYPE_V2DF:
24060 case INT_FTYPE_V16QI:
24061 case INT_FTYPE_V8QI:
24062 case INT_FTYPE_V8SF:
24063 case INT_FTYPE_V4DF:
24064 case INT_FTYPE_V4SF:
24065 case INT_FTYPE_V2DF:
24066 case V16QI_FTYPE_V16QI:
24067 case V8SI_FTYPE_V8SF:
24068 case V8SI_FTYPE_V4SI:
24069 case V8HI_FTYPE_V8HI:
24070 case V8HI_FTYPE_V16QI:
24071 case V8QI_FTYPE_V8QI:
24072 case V8SF_FTYPE_V8SF:
24073 case V8SF_FTYPE_V8SI:
24074 case V8SF_FTYPE_V4SF:
24075 case V4SI_FTYPE_V4SI:
24076 case V4SI_FTYPE_V16QI:
24077 case V4SI_FTYPE_V4SF:
24078 case V4SI_FTYPE_V8SI:
24079 case V4SI_FTYPE_V8HI:
24080 case V4SI_FTYPE_V4DF:
24081 case V4SI_FTYPE_V2DF:
24082 case V4HI_FTYPE_V4HI:
24083 case V4DF_FTYPE_V4DF:
24084 case V4DF_FTYPE_V4SI:
24085 case V4DF_FTYPE_V4SF:
24086 case V4DF_FTYPE_V2DF:
24087 case V4SF_FTYPE_V4SF:
24088 case V4SF_FTYPE_V4SI:
24089 case V4SF_FTYPE_V8SF:
24090 case V4SF_FTYPE_V4DF:
24091 case V4SF_FTYPE_V2DF:
24092 case V2DI_FTYPE_V2DI:
24093 case V2DI_FTYPE_V16QI:
24094 case V2DI_FTYPE_V8HI:
24095 case V2DI_FTYPE_V4SI:
24096 case V2DF_FTYPE_V2DF:
24097 case V2DF_FTYPE_V4SI:
24098 case V2DF_FTYPE_V4DF:
24099 case V2DF_FTYPE_V4SF:
24100 case V2DF_FTYPE_V2SI:
24101 case V2SI_FTYPE_V2SI:
24102 case V2SI_FTYPE_V4SF:
24103 case V2SI_FTYPE_V2SF:
24104 case V2SI_FTYPE_V2DF:
24105 case V2SF_FTYPE_V2SF:
24106 case V2SF_FTYPE_V2SI:
24109 case V4SF_FTYPE_V4SF_VEC_MERGE:
24110 case V2DF_FTYPE_V2DF_VEC_MERGE:
24111 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24112 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24113 case V16QI_FTYPE_V16QI_V16QI:
24114 case V16QI_FTYPE_V8HI_V8HI:
24115 case V8QI_FTYPE_V8QI_V8QI:
24116 case V8QI_FTYPE_V4HI_V4HI:
24117 case V8HI_FTYPE_V8HI_V8HI:
24118 case V8HI_FTYPE_V16QI_V16QI:
24119 case V8HI_FTYPE_V4SI_V4SI:
24120 case V8SF_FTYPE_V8SF_V8SF:
24121 case V8SF_FTYPE_V8SF_V8SI:
24122 case V4SI_FTYPE_V4SI_V4SI:
24123 case V4SI_FTYPE_V8HI_V8HI:
24124 case V4SI_FTYPE_V4SF_V4SF:
24125 case V4SI_FTYPE_V2DF_V2DF:
24126 case V4HI_FTYPE_V4HI_V4HI:
24127 case V4HI_FTYPE_V8QI_V8QI:
24128 case V4HI_FTYPE_V2SI_V2SI:
24129 case V4DF_FTYPE_V4DF_V4DF:
24130 case V4DF_FTYPE_V4DF_V4DI:
24131 case V4SF_FTYPE_V4SF_V4SF:
24132 case V4SF_FTYPE_V4SF_V4SI:
24133 case V4SF_FTYPE_V4SF_V2SI:
24134 case V4SF_FTYPE_V4SF_V2DF:
24135 case V4SF_FTYPE_V4SF_DI:
24136 case V4SF_FTYPE_V4SF_SI:
24137 case V2DI_FTYPE_V2DI_V2DI:
24138 case V2DI_FTYPE_V16QI_V16QI:
24139 case V2DI_FTYPE_V4SI_V4SI:
24140 case V2DI_FTYPE_V2DI_V16QI:
24141 case V2DI_FTYPE_V2DF_V2DF:
24142 case V2SI_FTYPE_V2SI_V2SI:
24143 case V2SI_FTYPE_V4HI_V4HI:
24144 case V2SI_FTYPE_V2SF_V2SF:
24145 case V2DF_FTYPE_V2DF_V2DF:
24146 case V2DF_FTYPE_V2DF_V4SF:
24147 case V2DF_FTYPE_V2DF_V2DI:
24148 case V2DF_FTYPE_V2DF_DI:
24149 case V2DF_FTYPE_V2DF_SI:
24150 case V2SF_FTYPE_V2SF_V2SF:
24151 case V1DI_FTYPE_V1DI_V1DI:
24152 case V1DI_FTYPE_V8QI_V8QI:
24153 case V1DI_FTYPE_V2SI_V2SI:
24154 if (comparison == UNKNOWN)
24155 return ix86_expand_binop_builtin (icode, exp, target);
24158 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24159 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24160 gcc_assert (comparison != UNKNOWN);
24164 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24165 case V8HI_FTYPE_V8HI_SI_COUNT:
24166 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24167 case V4SI_FTYPE_V4SI_SI_COUNT:
24168 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24169 case V4HI_FTYPE_V4HI_SI_COUNT:
24170 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24171 case V2DI_FTYPE_V2DI_SI_COUNT:
24172 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24173 case V2SI_FTYPE_V2SI_SI_COUNT:
24174 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24175 case V1DI_FTYPE_V1DI_SI_COUNT:
24177 last_arg_count = true;
24179 case UINT64_FTYPE_UINT64_UINT64:
24180 case UINT_FTYPE_UINT_UINT:
24181 case UINT_FTYPE_UINT_USHORT:
24182 case UINT_FTYPE_UINT_UCHAR:
24185 case V2DI2TI_FTYPE_V2DI_INT:
24188 nargs_constant = 1;
24190 case V8HI_FTYPE_V8HI_INT:
24191 case V8SF_FTYPE_V8SF_INT:
24192 case V4SI_FTYPE_V4SI_INT:
24193 case V4SI_FTYPE_V8SI_INT:
24194 case V4HI_FTYPE_V4HI_INT:
24195 case V4DF_FTYPE_V4DF_INT:
24196 case V4SF_FTYPE_V4SF_INT:
24197 case V4SF_FTYPE_V8SF_INT:
24198 case V2DI_FTYPE_V2DI_INT:
24199 case V2DF_FTYPE_V2DF_INT:
24200 case V2DF_FTYPE_V4DF_INT:
24202 nargs_constant = 1;
24204 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24205 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24206 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24207 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24208 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24211 case V16QI_FTYPE_V16QI_V16QI_INT:
24212 case V8HI_FTYPE_V8HI_V8HI_INT:
24213 case V8SI_FTYPE_V8SI_V8SI_INT:
24214 case V8SI_FTYPE_V8SI_V4SI_INT:
24215 case V8SF_FTYPE_V8SF_V8SF_INT:
24216 case V8SF_FTYPE_V8SF_V4SF_INT:
24217 case V4SI_FTYPE_V4SI_V4SI_INT:
24218 case V4DF_FTYPE_V4DF_V4DF_INT:
24219 case V4DF_FTYPE_V4DF_V2DF_INT:
24220 case V4SF_FTYPE_V4SF_V4SF_INT:
24221 case V2DI_FTYPE_V2DI_V2DI_INT:
24222 case V2DF_FTYPE_V2DF_V2DF_INT:
24224 nargs_constant = 1;
24226 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24229 nargs_constant = 1;
24231 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24234 nargs_constant = 1;
24236 case V2DI_FTYPE_V2DI_UINT_UINT:
24238 nargs_constant = 2;
24240 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24242 nargs_constant = 2;
24245 gcc_unreachable ();
24248 gcc_assert (nargs <= ARRAY_SIZE (args));
24250 if (comparison != UNKNOWN)
24252 gcc_assert (nargs == 2);
24253 return ix86_expand_sse_compare (d, exp, target, swap);
24256 if (rmode == VOIDmode || rmode == tmode)
24260 || GET_MODE (target) != tmode
24261 || ! (*insn_p->operand[0].predicate) (target, tmode))
24262 target = gen_reg_rtx (tmode);
24263 real_target = target;
24267 target = gen_reg_rtx (rmode);
24268 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24271 for (i = 0; i < nargs; i++)
24273 tree arg = CALL_EXPR_ARG (exp, i);
24274 rtx op = expand_normal (arg);
24275 enum machine_mode mode = insn_p->operand[i + 1].mode;
24276 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24278 if (last_arg_count && (i + 1) == nargs)
24280 /* SIMD shift insns take either an 8-bit immediate or
24281 register as count. But builtin functions take int as
24282 count. If count doesn't match, we put it in register. */
24285 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24286 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24287 op = copy_to_reg (op);
24290 else if ((nargs - i) <= nargs_constant)
24295 case CODE_FOR_sse4_1_roundpd:
24296 case CODE_FOR_sse4_1_roundps:
24297 case CODE_FOR_sse4_1_roundsd:
24298 case CODE_FOR_sse4_1_roundss:
24299 case CODE_FOR_sse4_1_blendps:
24300 case CODE_FOR_avx_blendpd256:
24301 case CODE_FOR_avx_vpermilv4df:
24302 case CODE_FOR_avx_roundpd256:
24303 case CODE_FOR_avx_roundps256:
24304 error ("the last argument must be a 4-bit immediate");
24307 case CODE_FOR_sse4_1_blendpd:
24308 case CODE_FOR_avx_vpermilv2df:
24309 error ("the last argument must be a 2-bit immediate");
24312 case CODE_FOR_avx_vextractf128v4df:
24313 case CODE_FOR_avx_vextractf128v8sf:
24314 case CODE_FOR_avx_vextractf128v8si:
24315 case CODE_FOR_avx_vinsertf128v4df:
24316 case CODE_FOR_avx_vinsertf128v8sf:
24317 case CODE_FOR_avx_vinsertf128v8si:
24318 error ("the last argument must be a 1-bit immediate");
24321 case CODE_FOR_avx_cmpsdv2df3:
24322 case CODE_FOR_avx_cmpssv4sf3:
24323 case CODE_FOR_avx_cmppdv2df3:
24324 case CODE_FOR_avx_cmppsv4sf3:
24325 case CODE_FOR_avx_cmppdv4df3:
24326 case CODE_FOR_avx_cmppsv8sf3:
24327 error ("the last argument must be a 5-bit immediate");
24331 switch (nargs_constant)
24334 if ((nargs - i) == nargs_constant)
24336 error ("the next to last argument must be an 8-bit immediate");
24340 error ("the last argument must be an 8-bit immediate");
24343 gcc_unreachable ();
24350 if (VECTOR_MODE_P (mode))
24351 op = safe_vector_operand (op, mode);
24353 /* If we aren't optimizing, only allow one memory operand to
24355 if (memory_operand (op, mode))
24358 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24360 if (optimize || !match || num_memory > 1)
24361 op = copy_to_mode_reg (mode, op);
24365 op = copy_to_reg (op);
24366 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24371 args[i].mode = mode;
24377 pat = GEN_FCN (icode) (real_target, args[0].op);
24380 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24383 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24387 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24388 args[2].op, args[3].op);
24391 gcc_unreachable ();
24401 /* Subroutine of ix86_expand_builtin to take care of special insns
24402 with variable number of operands. */
24405 ix86_expand_special_args_builtin (const struct builtin_description *d,
24406 tree exp, rtx target)
24410 unsigned int i, nargs, arg_adjust, memory;
24414 enum machine_mode mode;
24416 enum insn_code icode = d->icode;
24417 bool last_arg_constant = false;
24418 const struct insn_data *insn_p = &insn_data[icode];
24419 enum machine_mode tmode = insn_p->operand[0].mode;
24420 enum { load, store } klass;
24422 switch ((enum ix86_special_builtin_type) d->flag)
24424 case VOID_FTYPE_VOID:
24425 emit_insn (GEN_FCN (icode) (target));
24427 case V2DI_FTYPE_PV2DI:
24428 case V32QI_FTYPE_PCCHAR:
24429 case V16QI_FTYPE_PCCHAR:
24430 case V8SF_FTYPE_PCV4SF:
24431 case V8SF_FTYPE_PCFLOAT:
24432 case V4SF_FTYPE_PCFLOAT:
24433 case V4DF_FTYPE_PCV2DF:
24434 case V4DF_FTYPE_PCDOUBLE:
24435 case V2DF_FTYPE_PCDOUBLE:
24440 case VOID_FTYPE_PV2SF_V4SF:
24441 case VOID_FTYPE_PV4DI_V4DI:
24442 case VOID_FTYPE_PV2DI_V2DI:
24443 case VOID_FTYPE_PCHAR_V32QI:
24444 case VOID_FTYPE_PCHAR_V16QI:
24445 case VOID_FTYPE_PFLOAT_V8SF:
24446 case VOID_FTYPE_PFLOAT_V4SF:
24447 case VOID_FTYPE_PDOUBLE_V4DF:
24448 case VOID_FTYPE_PDOUBLE_V2DF:
24449 case VOID_FTYPE_PDI_DI:
24450 case VOID_FTYPE_PINT_INT:
24453 /* Reserve memory operand for target. */
24454 memory = ARRAY_SIZE (args);
24456 case V4SF_FTYPE_V4SF_PCV2SF:
24457 case V2DF_FTYPE_V2DF_PCDOUBLE:
24462 case V8SF_FTYPE_PCV8SF_V8SF:
24463 case V4DF_FTYPE_PCV4DF_V4DF:
24464 case V4SF_FTYPE_PCV4SF_V4SF:
24465 case V2DF_FTYPE_PCV2DF_V2DF:
24470 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24471 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24472 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24473 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24476 /* Reserve memory operand for target. */
24477 memory = ARRAY_SIZE (args);
24480 gcc_unreachable ();
24483 gcc_assert (nargs <= ARRAY_SIZE (args));
24485 if (klass == store)
24487 arg = CALL_EXPR_ARG (exp, 0);
24488 op = expand_normal (arg);
24489 gcc_assert (target == 0);
24490 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24498 || GET_MODE (target) != tmode
24499 || ! (*insn_p->operand[0].predicate) (target, tmode))
24500 target = gen_reg_rtx (tmode);
24503 for (i = 0; i < nargs; i++)
24505 enum machine_mode mode = insn_p->operand[i + 1].mode;
24508 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24509 op = expand_normal (arg);
24510 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24512 if (last_arg_constant && (i + 1) == nargs)
24518 error ("the last argument must be an 8-bit immediate");
24526 /* This must be the memory operand. */
24527 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24528 gcc_assert (GET_MODE (op) == mode
24529 || GET_MODE (op) == VOIDmode);
24533 /* This must be register. */
24534 if (VECTOR_MODE_P (mode))
24535 op = safe_vector_operand (op, mode);
24537 gcc_assert (GET_MODE (op) == mode
24538 || GET_MODE (op) == VOIDmode);
24539 op = copy_to_mode_reg (mode, op);
24544 args[i].mode = mode;
24550 pat = GEN_FCN (icode) (target, args[0].op);
24553 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24556 gcc_unreachable ();
24562 return klass == store ? 0 : target;
24565 /* Return the integer constant in ARG. Constrain it to be in the range
24566 of the subparts of VEC_TYPE; issue an error if not. */
24569 get_element_number (tree vec_type, tree arg)
24571 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24573 if (!host_integerp (arg, 1)
24574 || (elt = tree_low_cst (arg, 1), elt > max))
24576 error ("selector must be an integer constant in the range 0..%wi", max);
24583 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24584 ix86_expand_vector_init. We DO have language-level syntax for this, in
24585 the form of (type){ init-list }. Except that since we can't place emms
24586 instructions from inside the compiler, we can't allow the use of MMX
24587 registers unless the user explicitly asks for it. So we do *not* define
24588 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24589 we have builtins invoked by mmintrin.h that gives us license to emit
24590 these sorts of instructions. */
24593 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24595 enum machine_mode tmode = TYPE_MODE (type);
24596 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24597 int i, n_elt = GET_MODE_NUNITS (tmode);
24598 rtvec v = rtvec_alloc (n_elt);
24600 gcc_assert (VECTOR_MODE_P (tmode));
24601 gcc_assert (call_expr_nargs (exp) == n_elt);
24603 for (i = 0; i < n_elt; ++i)
24605 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24606 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24609 if (!target || !register_operand (target, tmode))
24610 target = gen_reg_rtx (tmode);
24612 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24616 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24617 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24618 had a language-level syntax for referencing vector elements. */
24621 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24623 enum machine_mode tmode, mode0;
24628 arg0 = CALL_EXPR_ARG (exp, 0);
24629 arg1 = CALL_EXPR_ARG (exp, 1);
24631 op0 = expand_normal (arg0);
24632 elt = get_element_number (TREE_TYPE (arg0), arg1);
24634 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24635 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24636 gcc_assert (VECTOR_MODE_P (mode0));
24638 op0 = force_reg (mode0, op0);
24640 if (optimize || !target || !register_operand (target, tmode))
24641 target = gen_reg_rtx (tmode);
24643 ix86_expand_vector_extract (true, target, op0, elt);
24648 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24649 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24650 a language-level syntax for referencing vector elements. */
24653 ix86_expand_vec_set_builtin (tree exp)
24655 enum machine_mode tmode, mode1;
24656 tree arg0, arg1, arg2;
24658 rtx op0, op1, target;
24660 arg0 = CALL_EXPR_ARG (exp, 0);
24661 arg1 = CALL_EXPR_ARG (exp, 1);
24662 arg2 = CALL_EXPR_ARG (exp, 2);
24664 tmode = TYPE_MODE (TREE_TYPE (arg0));
24665 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24666 gcc_assert (VECTOR_MODE_P (tmode));
24668 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24669 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24670 elt = get_element_number (TREE_TYPE (arg0), arg2);
24672 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24673 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24675 op0 = force_reg (tmode, op0);
24676 op1 = force_reg (mode1, op1);
24678 /* OP0 is the source of these builtin functions and shouldn't be
24679 modified. Create a copy, use it and return it as target. */
24680 target = gen_reg_rtx (tmode);
24681 emit_move_insn (target, op0);
24682 ix86_expand_vector_set (true, target, op1, elt);
24687 /* Expand an expression EXP that calls a built-in function,
24688 with result going to TARGET if that's convenient
24689 (and in mode MODE if that's convenient).
24690 SUBTARGET may be used as the target for computing one of EXP's operands.
24691 IGNORE is nonzero if the value is to be ignored. */
24694 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24695 enum machine_mode mode ATTRIBUTE_UNUSED,
24696 int ignore ATTRIBUTE_UNUSED)
24698 const struct builtin_description *d;
24700 enum insn_code icode;
24701 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24702 tree arg0, arg1, arg2;
24703 rtx op0, op1, op2, pat;
24704 enum machine_mode mode0, mode1, mode2;
24705 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24707 /* Determine whether the builtin function is available under the current ISA.
24708 Originally the builtin was not created if it wasn't applicable to the
24709 current ISA based on the command line switches. With function specific
24710 options, we need to check in the context of the function making the call
24711 whether it is supported. */
24712 if (ix86_builtins_isa[fcode].isa
24713 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24715 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24716 NULL, NULL, false);
24719 error ("%qE needs unknown isa option", fndecl);
24722 gcc_assert (opts != NULL);
24723 error ("%qE needs isa option %s", fndecl, opts);
24731 case IX86_BUILTIN_MASKMOVQ:
24732 case IX86_BUILTIN_MASKMOVDQU:
24733 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24734 ? CODE_FOR_mmx_maskmovq
24735 : CODE_FOR_sse2_maskmovdqu);
24736 /* Note the arg order is different from the operand order. */
24737 arg1 = CALL_EXPR_ARG (exp, 0);
24738 arg2 = CALL_EXPR_ARG (exp, 1);
24739 arg0 = CALL_EXPR_ARG (exp, 2);
24740 op0 = expand_normal (arg0);
24741 op1 = expand_normal (arg1);
24742 op2 = expand_normal (arg2);
24743 mode0 = insn_data[icode].operand[0].mode;
24744 mode1 = insn_data[icode].operand[1].mode;
24745 mode2 = insn_data[icode].operand[2].mode;
24747 op0 = force_reg (Pmode, op0);
24748 op0 = gen_rtx_MEM (mode1, op0);
24750 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24751 op0 = copy_to_mode_reg (mode0, op0);
24752 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24753 op1 = copy_to_mode_reg (mode1, op1);
24754 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24755 op2 = copy_to_mode_reg (mode2, op2);
24756 pat = GEN_FCN (icode) (op0, op1, op2);
24762 case IX86_BUILTIN_LDMXCSR:
24763 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24764 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24765 emit_move_insn (target, op0);
24766 emit_insn (gen_sse_ldmxcsr (target));
24769 case IX86_BUILTIN_STMXCSR:
24770 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24771 emit_insn (gen_sse_stmxcsr (target));
24772 return copy_to_mode_reg (SImode, target);
24774 case IX86_BUILTIN_CLFLUSH:
24775 arg0 = CALL_EXPR_ARG (exp, 0);
24776 op0 = expand_normal (arg0);
24777 icode = CODE_FOR_sse2_clflush;
24778 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24779 op0 = copy_to_mode_reg (Pmode, op0);
24781 emit_insn (gen_sse2_clflush (op0));
24784 case IX86_BUILTIN_MONITOR:
24785 arg0 = CALL_EXPR_ARG (exp, 0);
24786 arg1 = CALL_EXPR_ARG (exp, 1);
24787 arg2 = CALL_EXPR_ARG (exp, 2);
24788 op0 = expand_normal (arg0);
24789 op1 = expand_normal (arg1);
24790 op2 = expand_normal (arg2);
24792 op0 = copy_to_mode_reg (Pmode, op0);
24794 op1 = copy_to_mode_reg (SImode, op1);
24796 op2 = copy_to_mode_reg (SImode, op2);
24797 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24800 case IX86_BUILTIN_MWAIT:
24801 arg0 = CALL_EXPR_ARG (exp, 0);
24802 arg1 = CALL_EXPR_ARG (exp, 1);
24803 op0 = expand_normal (arg0);
24804 op1 = expand_normal (arg1);
24806 op0 = copy_to_mode_reg (SImode, op0);
24808 op1 = copy_to_mode_reg (SImode, op1);
24809 emit_insn (gen_sse3_mwait (op0, op1));
24812 case IX86_BUILTIN_VEC_INIT_V2SI:
24813 case IX86_BUILTIN_VEC_INIT_V4HI:
24814 case IX86_BUILTIN_VEC_INIT_V8QI:
24815 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24817 case IX86_BUILTIN_VEC_EXT_V2DF:
24818 case IX86_BUILTIN_VEC_EXT_V2DI:
24819 case IX86_BUILTIN_VEC_EXT_V4SF:
24820 case IX86_BUILTIN_VEC_EXT_V4SI:
24821 case IX86_BUILTIN_VEC_EXT_V8HI:
24822 case IX86_BUILTIN_VEC_EXT_V2SI:
24823 case IX86_BUILTIN_VEC_EXT_V4HI:
24824 case IX86_BUILTIN_VEC_EXT_V16QI:
24825 return ix86_expand_vec_ext_builtin (exp, target);
24827 case IX86_BUILTIN_VEC_SET_V2DI:
24828 case IX86_BUILTIN_VEC_SET_V4SF:
24829 case IX86_BUILTIN_VEC_SET_V4SI:
24830 case IX86_BUILTIN_VEC_SET_V8HI:
24831 case IX86_BUILTIN_VEC_SET_V4HI:
24832 case IX86_BUILTIN_VEC_SET_V16QI:
24833 return ix86_expand_vec_set_builtin (exp);
24835 case IX86_BUILTIN_INFQ:
24837 REAL_VALUE_TYPE inf;
24841 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24843 tmp = validize_mem (force_const_mem (mode, tmp));
24846 target = gen_reg_rtx (mode);
24848 emit_move_insn (target, tmp);
24856 for (i = 0, d = bdesc_special_args;
24857 i < ARRAY_SIZE (bdesc_special_args);
24859 if (d->code == fcode)
24860 return ix86_expand_special_args_builtin (d, exp, target);
24862 for (i = 0, d = bdesc_args;
24863 i < ARRAY_SIZE (bdesc_args);
24865 if (d->code == fcode)
24868 case IX86_BUILTIN_FABSQ:
24869 case IX86_BUILTIN_COPYSIGNQ:
24871 /* Emit a normal call if SSE2 isn't available. */
24872 return expand_call (exp, target, ignore);
24874 return ix86_expand_args_builtin (d, exp, target);
24877 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24878 if (d->code == fcode)
24879 return ix86_expand_sse_comi (d, exp, target);
24881 for (i = 0, d = bdesc_pcmpestr;
24882 i < ARRAY_SIZE (bdesc_pcmpestr);
24884 if (d->code == fcode)
24885 return ix86_expand_sse_pcmpestr (d, exp, target);
24887 for (i = 0, d = bdesc_pcmpistr;
24888 i < ARRAY_SIZE (bdesc_pcmpistr);
24890 if (d->code == fcode)
24891 return ix86_expand_sse_pcmpistr (d, exp, target);
24893 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24894 if (d->code == fcode)
24895 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24896 (enum multi_arg_type)d->flag,
24899 gcc_unreachable ();
24902 /* Returns a function decl for a vectorized version of the builtin function
24903 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24904 if it is not available. */
24907 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24910 enum machine_mode in_mode, out_mode;
24913 if (TREE_CODE (type_out) != VECTOR_TYPE
24914 || TREE_CODE (type_in) != VECTOR_TYPE)
24917 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24918 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24919 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24920 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24924 case BUILT_IN_SQRT:
24925 if (out_mode == DFmode && out_n == 2
24926 && in_mode == DFmode && in_n == 2)
24927 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24930 case BUILT_IN_SQRTF:
24931 if (out_mode == SFmode && out_n == 4
24932 && in_mode == SFmode && in_n == 4)
24933 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24936 case BUILT_IN_LRINT:
24937 if (out_mode == SImode && out_n == 4
24938 && in_mode == DFmode && in_n == 2)
24939 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24942 case BUILT_IN_LRINTF:
24943 if (out_mode == SImode && out_n == 4
24944 && in_mode == SFmode && in_n == 4)
24945 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24952 /* Dispatch to a handler for a vectorization library. */
24953 if (ix86_veclib_handler)
24954 return (*ix86_veclib_handler)(fn, type_out, type_in);
24959 /* Handler for an SVML-style interface to
24960 a library with vectorized intrinsics. */
24963 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24966 tree fntype, new_fndecl, args;
24969 enum machine_mode el_mode, in_mode;
24972 /* The SVML is suitable for unsafe math only. */
24973 if (!flag_unsafe_math_optimizations)
24976 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24977 n = TYPE_VECTOR_SUBPARTS (type_out);
24978 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24979 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24980 if (el_mode != in_mode
24988 case BUILT_IN_LOG10:
24990 case BUILT_IN_TANH:
24992 case BUILT_IN_ATAN:
24993 case BUILT_IN_ATAN2:
24994 case BUILT_IN_ATANH:
24995 case BUILT_IN_CBRT:
24996 case BUILT_IN_SINH:
24998 case BUILT_IN_ASINH:
24999 case BUILT_IN_ASIN:
25000 case BUILT_IN_COSH:
25002 case BUILT_IN_ACOSH:
25003 case BUILT_IN_ACOS:
25004 if (el_mode != DFmode || n != 2)
25008 case BUILT_IN_EXPF:
25009 case BUILT_IN_LOGF:
25010 case BUILT_IN_LOG10F:
25011 case BUILT_IN_POWF:
25012 case BUILT_IN_TANHF:
25013 case BUILT_IN_TANF:
25014 case BUILT_IN_ATANF:
25015 case BUILT_IN_ATAN2F:
25016 case BUILT_IN_ATANHF:
25017 case BUILT_IN_CBRTF:
25018 case BUILT_IN_SINHF:
25019 case BUILT_IN_SINF:
25020 case BUILT_IN_ASINHF:
25021 case BUILT_IN_ASINF:
25022 case BUILT_IN_COSHF:
25023 case BUILT_IN_COSF:
25024 case BUILT_IN_ACOSHF:
25025 case BUILT_IN_ACOSF:
25026 if (el_mode != SFmode || n != 4)
25034 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25036 if (fn == BUILT_IN_LOGF)
25037 strcpy (name, "vmlsLn4");
25038 else if (fn == BUILT_IN_LOG)
25039 strcpy (name, "vmldLn2");
25042 sprintf (name, "vmls%s", bname+10);
25043 name[strlen (name)-1] = '4';
25046 sprintf (name, "vmld%s2", bname+10);
25048 /* Convert to uppercase. */
25052 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25053 args = TREE_CHAIN (args))
25057 fntype = build_function_type_list (type_out, type_in, NULL);
25059 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25061 /* Build a function declaration for the vectorized function. */
25062 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25063 TREE_PUBLIC (new_fndecl) = 1;
25064 DECL_EXTERNAL (new_fndecl) = 1;
25065 DECL_IS_NOVOPS (new_fndecl) = 1;
25066 TREE_READONLY (new_fndecl) = 1;
25071 /* Handler for an ACML-style interface to
25072 a library with vectorized intrinsics. */
25075 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25077 char name[20] = "__vr.._";
25078 tree fntype, new_fndecl, args;
25081 enum machine_mode el_mode, in_mode;
25084 /* The ACML is 64bits only and suitable for unsafe math only as
25085 it does not correctly support parts of IEEE with the required
25086 precision such as denormals. */
25088 || !flag_unsafe_math_optimizations)
25091 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25092 n = TYPE_VECTOR_SUBPARTS (type_out);
25093 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25094 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25095 if (el_mode != in_mode
25105 case BUILT_IN_LOG2:
25106 case BUILT_IN_LOG10:
25109 if (el_mode != DFmode
25114 case BUILT_IN_SINF:
25115 case BUILT_IN_COSF:
25116 case BUILT_IN_EXPF:
25117 case BUILT_IN_POWF:
25118 case BUILT_IN_LOGF:
25119 case BUILT_IN_LOG2F:
25120 case BUILT_IN_LOG10F:
25123 if (el_mode != SFmode
25132 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25133 sprintf (name + 7, "%s", bname+10);
25136 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25137 args = TREE_CHAIN (args))
25141 fntype = build_function_type_list (type_out, type_in, NULL);
25143 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25145 /* Build a function declaration for the vectorized function. */
25146 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25147 TREE_PUBLIC (new_fndecl) = 1;
25148 DECL_EXTERNAL (new_fndecl) = 1;
25149 DECL_IS_NOVOPS (new_fndecl) = 1;
25150 TREE_READONLY (new_fndecl) = 1;
25156 /* Returns a decl of a function that implements conversion of an integer vector
25157 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25158 side of the conversion.
25159 Return NULL_TREE if it is not available. */
25162 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25164 if (TREE_CODE (type) != VECTOR_TYPE)
25170 switch (TYPE_MODE (type))
25173 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25178 case FIX_TRUNC_EXPR:
25179 switch (TYPE_MODE (type))
25182 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25192 /* Returns a code for a target-specific builtin that implements
25193 reciprocal of the function, or NULL_TREE if not available. */
25196 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25197 bool sqrt ATTRIBUTE_UNUSED)
25199 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25200 && flag_finite_math_only && !flag_trapping_math
25201 && flag_unsafe_math_optimizations))
25205 /* Machine dependent builtins. */
25208 /* Vectorized version of sqrt to rsqrt conversion. */
25209 case IX86_BUILTIN_SQRTPS_NR:
25210 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25216 /* Normal builtins. */
25219 /* Sqrt to rsqrt conversion. */
25220 case BUILT_IN_SQRTF:
25221 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25228 /* Store OPERAND to the memory after reload is completed. This means
25229 that we can't easily use assign_stack_local. */
25231 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25235 gcc_assert (reload_completed);
25236 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25238 result = gen_rtx_MEM (mode,
25239 gen_rtx_PLUS (Pmode,
25241 GEN_INT (-RED_ZONE_SIZE)));
25242 emit_move_insn (result, operand);
25244 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25250 operand = gen_lowpart (DImode, operand);
25254 gen_rtx_SET (VOIDmode,
25255 gen_rtx_MEM (DImode,
25256 gen_rtx_PRE_DEC (DImode,
25257 stack_pointer_rtx)),
25261 gcc_unreachable ();
25263 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25272 split_di (&operand, 1, operands, operands + 1);
25274 gen_rtx_SET (VOIDmode,
25275 gen_rtx_MEM (SImode,
25276 gen_rtx_PRE_DEC (Pmode,
25277 stack_pointer_rtx)),
25280 gen_rtx_SET (VOIDmode,
25281 gen_rtx_MEM (SImode,
25282 gen_rtx_PRE_DEC (Pmode,
25283 stack_pointer_rtx)),
25288 /* Store HImodes as SImodes. */
25289 operand = gen_lowpart (SImode, operand);
25293 gen_rtx_SET (VOIDmode,
25294 gen_rtx_MEM (GET_MODE (operand),
25295 gen_rtx_PRE_DEC (SImode,
25296 stack_pointer_rtx)),
25300 gcc_unreachable ();
25302 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25307 /* Free operand from the memory. */
25309 ix86_free_from_memory (enum machine_mode mode)
25311 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25315 if (mode == DImode || TARGET_64BIT)
25319 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25320 to pop or add instruction if registers are available. */
25321 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25322 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25327 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25328 QImode must go into class Q_REGS.
25329 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25330 movdf to do mem-to-mem moves through integer regs. */
25332 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25334 enum machine_mode mode = GET_MODE (x);
25336 /* We're only allowed to return a subclass of CLASS. Many of the
25337 following checks fail for NO_REGS, so eliminate that early. */
25338 if (regclass == NO_REGS)
25341 /* All classes can load zeros. */
25342 if (x == CONST0_RTX (mode))
25345 /* Force constants into memory if we are loading a (nonzero) constant into
25346 an MMX or SSE register. This is because there are no MMX/SSE instructions
25347 to load from a constant. */
25349 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25352 /* Prefer SSE regs only, if we can use them for math. */
25353 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25354 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25356 /* Floating-point constants need more complex checks. */
25357 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25359 /* General regs can load everything. */
25360 if (reg_class_subset_p (regclass, GENERAL_REGS))
25363 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25364 zero above. We only want to wind up preferring 80387 registers if
25365 we plan on doing computation with them. */
25367 && standard_80387_constant_p (x))
25369 /* Limit class to non-sse. */
25370 if (regclass == FLOAT_SSE_REGS)
25372 if (regclass == FP_TOP_SSE_REGS)
25374 if (regclass == FP_SECOND_SSE_REGS)
25375 return FP_SECOND_REG;
25376 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25383 /* Generally when we see PLUS here, it's the function invariant
25384 (plus soft-fp const_int). Which can only be computed into general
25386 if (GET_CODE (x) == PLUS)
25387 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25389 /* QImode constants are easy to load, but non-constant QImode data
25390 must go into Q_REGS. */
25391 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25393 if (reg_class_subset_p (regclass, Q_REGS))
25395 if (reg_class_subset_p (Q_REGS, regclass))
25403 /* Discourage putting floating-point values in SSE registers unless
25404 SSE math is being used, and likewise for the 387 registers. */
25406 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25408 enum machine_mode mode = GET_MODE (x);
25410 /* Restrict the output reload class to the register bank that we are doing
25411 math on. If we would like not to return a subset of CLASS, reject this
25412 alternative: if reload cannot do this, it will still use its choice. */
25413 mode = GET_MODE (x);
25414 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25415 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25417 if (X87_FLOAT_MODE_P (mode))
25419 if (regclass == FP_TOP_SSE_REGS)
25421 else if (regclass == FP_SECOND_SSE_REGS)
25422 return FP_SECOND_REG;
25424 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25430 static enum reg_class
25431 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25432 enum machine_mode mode,
25433 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25435 /* QImode spills from non-QI registers require
25436 intermediate register on 32bit targets. */
25437 if (!in_p && mode == QImode && !TARGET_64BIT
25438 && (rclass == GENERAL_REGS
25439 || rclass == LEGACY_REGS
25440 || rclass == INDEX_REGS))
25449 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25450 regno = true_regnum (x);
25452 /* Return Q_REGS if the operand is in memory. */
25460 /* If we are copying between general and FP registers, we need a memory
25461 location. The same is true for SSE and MMX registers.
25463 To optimize register_move_cost performance, allow inline variant.
25465 The macro can't work reliably when one of the CLASSES is class containing
25466 registers from multiple units (SSE, MMX, integer). We avoid this by never
25467 combining those units in single alternative in the machine description.
25468 Ensure that this constraint holds to avoid unexpected surprises.
25470 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25471 enforce these sanity checks. */
25474 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25475 enum machine_mode mode, int strict)
25477 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25478 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25479 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25480 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25481 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25482 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25484 gcc_assert (!strict);
25488 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25491 /* ??? This is a lie. We do have moves between mmx/general, and for
25492 mmx/sse2. But by saying we need secondary memory we discourage the
25493 register allocator from using the mmx registers unless needed. */
25494 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25497 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25499 /* SSE1 doesn't have any direct moves from other classes. */
25503 /* If the target says that inter-unit moves are more expensive
25504 than moving through memory, then don't generate them. */
25505 if (!TARGET_INTER_UNIT_MOVES)
25508 /* Between SSE and general, we have moves no larger than word size. */
25509 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25517 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25518 enum machine_mode mode, int strict)
25520 return inline_secondary_memory_needed (class1, class2, mode, strict);
25523 /* Return true if the registers in CLASS cannot represent the change from
25524 modes FROM to TO. */
25527 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25528 enum reg_class regclass)
25533 /* x87 registers can't do subreg at all, as all values are reformatted
25534 to extended precision. */
25535 if (MAYBE_FLOAT_CLASS_P (regclass))
25538 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25540 /* Vector registers do not support QI or HImode loads. If we don't
25541 disallow a change to these modes, reload will assume it's ok to
25542 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25543 the vec_dupv4hi pattern. */
25544 if (GET_MODE_SIZE (from) < 4)
25547 /* Vector registers do not support subreg with nonzero offsets, which
25548 are otherwise valid for integer registers. Since we can't see
25549 whether we have a nonzero offset from here, prohibit all
25550 nonparadoxical subregs changing size. */
25551 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25558 /* Return the cost of moving data of mode M between a
25559 register and memory. A value of 2 is the default; this cost is
25560 relative to those in `REGISTER_MOVE_COST'.
25562 This function is used extensively by register_move_cost that is used to
25563 build tables at startup. Make it inline in this case.
25564 When IN is 2, return maximum of in and out move cost.
25566 If moving between registers and memory is more expensive than
25567 between two registers, you should define this macro to express the
25570 Model also increased moving costs of QImode registers in non
25574 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25578 if (FLOAT_CLASS_P (regclass))
25596 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25597 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25599 if (SSE_CLASS_P (regclass))
25602 switch (GET_MODE_SIZE (mode))
25617 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25618 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25620 if (MMX_CLASS_P (regclass))
25623 switch (GET_MODE_SIZE (mode))
25635 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25636 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25638 switch (GET_MODE_SIZE (mode))
25641 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25644 return ix86_cost->int_store[0];
25645 if (TARGET_PARTIAL_REG_DEPENDENCY
25646 && optimize_function_for_speed_p (cfun))
25647 cost = ix86_cost->movzbl_load;
25649 cost = ix86_cost->int_load[0];
25651 return MAX (cost, ix86_cost->int_store[0]);
25657 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25659 return ix86_cost->movzbl_load;
25661 return ix86_cost->int_store[0] + 4;
25666 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25667 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25669 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25670 if (mode == TFmode)
25673 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25675 cost = ix86_cost->int_load[2];
25677 cost = ix86_cost->int_store[2];
25678 return (cost * (((int) GET_MODE_SIZE (mode)
25679 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25684 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25686 return inline_memory_move_cost (mode, regclass, in);
25690 /* Return the cost of moving data from a register in class CLASS1 to
25691 one in class CLASS2.
25693 It is not required that the cost always equal 2 when FROM is the same as TO;
25694 on some machines it is expensive to move between registers if they are not
25695 general registers. */
25698 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25699 enum reg_class class2)
25701 /* In case we require secondary memory, compute cost of the store followed
25702 by load. In order to avoid bad register allocation choices, we need
25703 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25705 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25709 cost += inline_memory_move_cost (mode, class1, 2);
25710 cost += inline_memory_move_cost (mode, class2, 2);
25712 /* In case of copying from general_purpose_register we may emit multiple
25713 stores followed by single load causing memory size mismatch stall.
25714 Count this as arbitrarily high cost of 20. */
25715 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25718 /* In the case of FP/MMX moves, the registers actually overlap, and we
25719 have to switch modes in order to treat them differently. */
25720 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25721 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25727 /* Moves between SSE/MMX and integer unit are expensive. */
25728 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25729 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25731 /* ??? By keeping returned value relatively high, we limit the number
25732 of moves between integer and MMX/SSE registers for all targets.
25733 Additionally, high value prevents problem with x86_modes_tieable_p(),
25734 where integer modes in MMX/SSE registers are not tieable
25735 because of missing QImode and HImode moves to, from or between
25736 MMX/SSE registers. */
25737 return MAX (8, ix86_cost->mmxsse_to_integer);
25739 if (MAYBE_FLOAT_CLASS_P (class1))
25740 return ix86_cost->fp_move;
25741 if (MAYBE_SSE_CLASS_P (class1))
25742 return ix86_cost->sse_move;
25743 if (MAYBE_MMX_CLASS_P (class1))
25744 return ix86_cost->mmx_move;
25748 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25751 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25753 /* Flags and only flags can only hold CCmode values. */
25754 if (CC_REGNO_P (regno))
25755 return GET_MODE_CLASS (mode) == MODE_CC;
25756 if (GET_MODE_CLASS (mode) == MODE_CC
25757 || GET_MODE_CLASS (mode) == MODE_RANDOM
25758 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25760 if (FP_REGNO_P (regno))
25761 return VALID_FP_MODE_P (mode);
25762 if (SSE_REGNO_P (regno))
25764 /* We implement the move patterns for all vector modes into and
25765 out of SSE registers, even when no operation instructions
25766 are available. OImode move is available only when AVX is
25768 return ((TARGET_AVX && mode == OImode)
25769 || VALID_AVX256_REG_MODE (mode)
25770 || VALID_SSE_REG_MODE (mode)
25771 || VALID_SSE2_REG_MODE (mode)
25772 || VALID_MMX_REG_MODE (mode)
25773 || VALID_MMX_REG_MODE_3DNOW (mode));
25775 if (MMX_REGNO_P (regno))
25777 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25778 so if the register is available at all, then we can move data of
25779 the given mode into or out of it. */
25780 return (VALID_MMX_REG_MODE (mode)
25781 || VALID_MMX_REG_MODE_3DNOW (mode));
25784 if (mode == QImode)
25786 /* Take care for QImode values - they can be in non-QI regs,
25787 but then they do cause partial register stalls. */
25788 if (regno <= BX_REG || TARGET_64BIT)
25790 if (!TARGET_PARTIAL_REG_STALL)
25792 return reload_in_progress || reload_completed;
25794 /* We handle both integer and floats in the general purpose registers. */
25795 else if (VALID_INT_MODE_P (mode))
25797 else if (VALID_FP_MODE_P (mode))
25799 else if (VALID_DFP_MODE_P (mode))
25801 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25802 on to use that value in smaller contexts, this can easily force a
25803 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25804 supporting DImode, allow it. */
25805 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25811 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25812 tieable integer mode. */
25815 ix86_tieable_integer_mode_p (enum machine_mode mode)
25824 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25827 return TARGET_64BIT;
25834 /* Return true if MODE1 is accessible in a register that can hold MODE2
25835 without copying. That is, all register classes that can hold MODE2
25836 can also hold MODE1. */
25839 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25841 if (mode1 == mode2)
25844 if (ix86_tieable_integer_mode_p (mode1)
25845 && ix86_tieable_integer_mode_p (mode2))
25848 /* MODE2 being XFmode implies fp stack or general regs, which means we
25849 can tie any smaller floating point modes to it. Note that we do not
25850 tie this with TFmode. */
25851 if (mode2 == XFmode)
25852 return mode1 == SFmode || mode1 == DFmode;
25854 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25855 that we can tie it with SFmode. */
25856 if (mode2 == DFmode)
25857 return mode1 == SFmode;
25859 /* If MODE2 is only appropriate for an SSE register, then tie with
25860 any other mode acceptable to SSE registers. */
25861 if (GET_MODE_SIZE (mode2) == 16
25862 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25863 return (GET_MODE_SIZE (mode1) == 16
25864 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25866 /* If MODE2 is appropriate for an MMX register, then tie
25867 with any other mode acceptable to MMX registers. */
25868 if (GET_MODE_SIZE (mode2) == 8
25869 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25870 return (GET_MODE_SIZE (mode1) == 8
25871 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25876 /* Compute a (partial) cost for rtx X. Return true if the complete
25877 cost has been computed, and false if subexpressions should be
25878 scanned. In either case, *TOTAL contains the cost result. */
25881 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25883 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25884 enum machine_mode mode = GET_MODE (x);
25885 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25893 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25895 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25897 else if (flag_pic && SYMBOLIC_CONST (x)
25899 || (!GET_CODE (x) != LABEL_REF
25900 && (GET_CODE (x) != SYMBOL_REF
25901 || !SYMBOL_REF_LOCAL_P (x)))))
25908 if (mode == VOIDmode)
25911 switch (standard_80387_constant_p (x))
25916 default: /* Other constants */
25921 /* Start with (MEM (SYMBOL_REF)), since that's where
25922 it'll probably end up. Add a penalty for size. */
25923 *total = (COSTS_N_INSNS (1)
25924 + (flag_pic != 0 && !TARGET_64BIT)
25925 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25931 /* The zero extensions is often completely free on x86_64, so make
25932 it as cheap as possible. */
25933 if (TARGET_64BIT && mode == DImode
25934 && GET_MODE (XEXP (x, 0)) == SImode)
25936 else if (TARGET_ZERO_EXTEND_WITH_AND)
25937 *total = cost->add;
25939 *total = cost->movzx;
25943 *total = cost->movsx;
25947 if (CONST_INT_P (XEXP (x, 1))
25948 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25950 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25953 *total = cost->add;
25956 if ((value == 2 || value == 3)
25957 && cost->lea <= cost->shift_const)
25959 *total = cost->lea;
25969 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25971 if (CONST_INT_P (XEXP (x, 1)))
25973 if (INTVAL (XEXP (x, 1)) > 32)
25974 *total = cost->shift_const + COSTS_N_INSNS (2);
25976 *total = cost->shift_const * 2;
25980 if (GET_CODE (XEXP (x, 1)) == AND)
25981 *total = cost->shift_var * 2;
25983 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25988 if (CONST_INT_P (XEXP (x, 1)))
25989 *total = cost->shift_const;
25991 *total = cost->shift_var;
25996 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25998 /* ??? SSE scalar cost should be used here. */
25999 *total = cost->fmul;
26002 else if (X87_FLOAT_MODE_P (mode))
26004 *total = cost->fmul;
26007 else if (FLOAT_MODE_P (mode))
26009 /* ??? SSE vector cost should be used here. */
26010 *total = cost->fmul;
26015 rtx op0 = XEXP (x, 0);
26016 rtx op1 = XEXP (x, 1);
26018 if (CONST_INT_P (XEXP (x, 1)))
26020 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26021 for (nbits = 0; value != 0; value &= value - 1)
26025 /* This is arbitrary. */
26028 /* Compute costs correctly for widening multiplication. */
26029 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26030 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26031 == GET_MODE_SIZE (mode))
26033 int is_mulwiden = 0;
26034 enum machine_mode inner_mode = GET_MODE (op0);
26036 if (GET_CODE (op0) == GET_CODE (op1))
26037 is_mulwiden = 1, op1 = XEXP (op1, 0);
26038 else if (CONST_INT_P (op1))
26040 if (GET_CODE (op0) == SIGN_EXTEND)
26041 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26044 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26048 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26051 *total = (cost->mult_init[MODE_INDEX (mode)]
26052 + nbits * cost->mult_bit
26053 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26062 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26063 /* ??? SSE cost should be used here. */
26064 *total = cost->fdiv;
26065 else if (X87_FLOAT_MODE_P (mode))
26066 *total = cost->fdiv;
26067 else if (FLOAT_MODE_P (mode))
26068 /* ??? SSE vector cost should be used here. */
26069 *total = cost->fdiv;
26071 *total = cost->divide[MODE_INDEX (mode)];
26075 if (GET_MODE_CLASS (mode) == MODE_INT
26076 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26078 if (GET_CODE (XEXP (x, 0)) == PLUS
26079 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26080 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26081 && CONSTANT_P (XEXP (x, 1)))
26083 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26084 if (val == 2 || val == 4 || val == 8)
26086 *total = cost->lea;
26087 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26088 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26089 outer_code, speed);
26090 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26094 else if (GET_CODE (XEXP (x, 0)) == MULT
26095 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26097 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26098 if (val == 2 || val == 4 || val == 8)
26100 *total = cost->lea;
26101 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26102 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26106 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26108 *total = cost->lea;
26109 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26110 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26111 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26118 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26120 /* ??? SSE cost should be used here. */
26121 *total = cost->fadd;
26124 else if (X87_FLOAT_MODE_P (mode))
26126 *total = cost->fadd;
26129 else if (FLOAT_MODE_P (mode))
26131 /* ??? SSE vector cost should be used here. */
26132 *total = cost->fadd;
26140 if (!TARGET_64BIT && mode == DImode)
26142 *total = (cost->add * 2
26143 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26144 << (GET_MODE (XEXP (x, 0)) != DImode))
26145 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26146 << (GET_MODE (XEXP (x, 1)) != DImode)));
26152 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26154 /* ??? SSE cost should be used here. */
26155 *total = cost->fchs;
26158 else if (X87_FLOAT_MODE_P (mode))
26160 *total = cost->fchs;
26163 else if (FLOAT_MODE_P (mode))
26165 /* ??? SSE vector cost should be used here. */
26166 *total = cost->fchs;
26172 if (!TARGET_64BIT && mode == DImode)
26173 *total = cost->add * 2;
26175 *total = cost->add;
26179 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26180 && XEXP (XEXP (x, 0), 1) == const1_rtx
26181 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26182 && XEXP (x, 1) == const0_rtx)
26184 /* This kind of construct is implemented using test[bwl].
26185 Treat it as if we had an AND. */
26186 *total = (cost->add
26187 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26188 + rtx_cost (const1_rtx, outer_code, speed));
26194 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26199 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26200 /* ??? SSE cost should be used here. */
26201 *total = cost->fabs;
26202 else if (X87_FLOAT_MODE_P (mode))
26203 *total = cost->fabs;
26204 else if (FLOAT_MODE_P (mode))
26205 /* ??? SSE vector cost should be used here. */
26206 *total = cost->fabs;
26210 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26211 /* ??? SSE cost should be used here. */
26212 *total = cost->fsqrt;
26213 else if (X87_FLOAT_MODE_P (mode))
26214 *total = cost->fsqrt;
26215 else if (FLOAT_MODE_P (mode))
26216 /* ??? SSE vector cost should be used here. */
26217 *total = cost->fsqrt;
26221 if (XINT (x, 1) == UNSPEC_TP)
26232 static int current_machopic_label_num;
26234 /* Given a symbol name and its associated stub, write out the
26235 definition of the stub. */
26238 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26240 unsigned int length;
26241 char *binder_name, *symbol_name, lazy_ptr_name[32];
26242 int label = ++current_machopic_label_num;
26244 /* For 64-bit we shouldn't get here. */
26245 gcc_assert (!TARGET_64BIT);
26247 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26248 symb = (*targetm.strip_name_encoding) (symb);
26250 length = strlen (stub);
26251 binder_name = XALLOCAVEC (char, length + 32);
26252 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26254 length = strlen (symb);
26255 symbol_name = XALLOCAVEC (char, length + 32);
26256 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26258 sprintf (lazy_ptr_name, "L%d$lz", label);
26261 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26263 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26265 fprintf (file, "%s:\n", stub);
26266 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26270 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26271 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26272 fprintf (file, "\tjmp\t*%%edx\n");
26275 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26277 fprintf (file, "%s:\n", binder_name);
26281 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26282 fprintf (file, "\tpushl\t%%eax\n");
26285 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26287 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26289 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26290 fprintf (file, "%s:\n", lazy_ptr_name);
26291 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26292 fprintf (file, "\t.long %s\n", binder_name);
26296 darwin_x86_file_end (void)
26298 darwin_file_end ();
26301 #endif /* TARGET_MACHO */
26303 /* Order the registers for register allocator. */
26306 x86_order_regs_for_local_alloc (void)
26311 /* First allocate the local general purpose registers. */
26312 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26313 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26314 reg_alloc_order [pos++] = i;
26316 /* Global general purpose registers. */
26317 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26318 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26319 reg_alloc_order [pos++] = i;
26321 /* x87 registers come first in case we are doing FP math
26323 if (!TARGET_SSE_MATH)
26324 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26325 reg_alloc_order [pos++] = i;
26327 /* SSE registers. */
26328 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26329 reg_alloc_order [pos++] = i;
26330 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26331 reg_alloc_order [pos++] = i;
26333 /* x87 registers. */
26334 if (TARGET_SSE_MATH)
26335 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26336 reg_alloc_order [pos++] = i;
26338 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26339 reg_alloc_order [pos++] = i;
26341 /* Initialize the rest of array as we do not allocate some registers
26343 while (pos < FIRST_PSEUDO_REGISTER)
26344 reg_alloc_order [pos++] = 0;
26347 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26348 struct attribute_spec.handler. */
26350 ix86_handle_abi_attribute (tree *node, tree name,
26351 tree args ATTRIBUTE_UNUSED,
26352 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26354 if (TREE_CODE (*node) != FUNCTION_TYPE
26355 && TREE_CODE (*node) != METHOD_TYPE
26356 && TREE_CODE (*node) != FIELD_DECL
26357 && TREE_CODE (*node) != TYPE_DECL)
26359 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26360 IDENTIFIER_POINTER (name));
26361 *no_add_attrs = true;
26366 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26367 IDENTIFIER_POINTER (name));
26368 *no_add_attrs = true;
26372 /* Can combine regparm with all attributes but fastcall. */
26373 if (is_attribute_p ("ms_abi", name))
26375 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26377 error ("ms_abi and sysv_abi attributes are not compatible");
26382 else if (is_attribute_p ("sysv_abi", name))
26384 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26386 error ("ms_abi and sysv_abi attributes are not compatible");
26395 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26396 struct attribute_spec.handler. */
26398 ix86_handle_struct_attribute (tree *node, tree name,
26399 tree args ATTRIBUTE_UNUSED,
26400 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26403 if (DECL_P (*node))
26405 if (TREE_CODE (*node) == TYPE_DECL)
26406 type = &TREE_TYPE (*node);
26411 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26412 || TREE_CODE (*type) == UNION_TYPE)))
26414 warning (OPT_Wattributes, "%qs attribute ignored",
26415 IDENTIFIER_POINTER (name));
26416 *no_add_attrs = true;
26419 else if ((is_attribute_p ("ms_struct", name)
26420 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26421 || ((is_attribute_p ("gcc_struct", name)
26422 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26424 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26425 IDENTIFIER_POINTER (name));
26426 *no_add_attrs = true;
26433 ix86_ms_bitfield_layout_p (const_tree record_type)
26435 return (TARGET_MS_BITFIELD_LAYOUT &&
26436 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26437 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26440 /* Returns an expression indicating where the this parameter is
26441 located on entry to the FUNCTION. */
26444 x86_this_parameter (tree function)
26446 tree type = TREE_TYPE (function);
26447 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26452 const int *parm_regs;
26454 if (ix86_function_type_abi (type) == MS_ABI)
26455 parm_regs = x86_64_ms_abi_int_parameter_registers;
26457 parm_regs = x86_64_int_parameter_registers;
26458 return gen_rtx_REG (DImode, parm_regs[aggr]);
26461 nregs = ix86_function_regparm (type, function);
26463 if (nregs > 0 && !stdarg_p (type))
26467 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26468 regno = aggr ? DX_REG : CX_REG;
26476 return gen_rtx_MEM (SImode,
26477 plus_constant (stack_pointer_rtx, 4));
26480 return gen_rtx_REG (SImode, regno);
26483 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26486 /* Determine whether x86_output_mi_thunk can succeed. */
26489 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26490 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26491 HOST_WIDE_INT vcall_offset, const_tree function)
26493 /* 64-bit can handle anything. */
26497 /* For 32-bit, everything's fine if we have one free register. */
26498 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26501 /* Need a free register for vcall_offset. */
26505 /* Need a free register for GOT references. */
26506 if (flag_pic && !(*targetm.binds_local_p) (function))
26509 /* Otherwise ok. */
26513 /* Output the assembler code for a thunk function. THUNK_DECL is the
26514 declaration for the thunk function itself, FUNCTION is the decl for
26515 the target function. DELTA is an immediate constant offset to be
26516 added to THIS. If VCALL_OFFSET is nonzero, the word at
26517 *(*this + vcall_offset) should be added to THIS. */
26520 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26521 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26522 HOST_WIDE_INT vcall_offset, tree function)
26525 rtx this_param = x86_this_parameter (function);
26528 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26529 pull it in now and let DELTA benefit. */
26530 if (REG_P (this_param))
26531 this_reg = this_param;
26532 else if (vcall_offset)
26534 /* Put the this parameter into %eax. */
26535 xops[0] = this_param;
26536 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26537 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26540 this_reg = NULL_RTX;
26542 /* Adjust the this parameter by a fixed constant. */
26545 xops[0] = GEN_INT (delta);
26546 xops[1] = this_reg ? this_reg : this_param;
26549 if (!x86_64_general_operand (xops[0], DImode))
26551 tmp = gen_rtx_REG (DImode, R10_REG);
26553 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26555 xops[1] = this_param;
26557 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26560 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26563 /* Adjust the this parameter by a value stored in the vtable. */
26567 tmp = gen_rtx_REG (DImode, R10_REG);
26570 int tmp_regno = CX_REG;
26571 if (lookup_attribute ("fastcall",
26572 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26573 tmp_regno = AX_REG;
26574 tmp = gen_rtx_REG (SImode, tmp_regno);
26577 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26579 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26581 /* Adjust the this parameter. */
26582 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26583 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26585 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26586 xops[0] = GEN_INT (vcall_offset);
26588 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26589 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26591 xops[1] = this_reg;
26592 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26595 /* If necessary, drop THIS back to its stack slot. */
26596 if (this_reg && this_reg != this_param)
26598 xops[0] = this_reg;
26599 xops[1] = this_param;
26600 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26603 xops[0] = XEXP (DECL_RTL (function), 0);
26606 if (!flag_pic || (*targetm.binds_local_p) (function))
26607 output_asm_insn ("jmp\t%P0", xops);
26608 /* All thunks should be in the same object as their target,
26609 and thus binds_local_p should be true. */
26610 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26611 gcc_unreachable ();
26614 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26615 tmp = gen_rtx_CONST (Pmode, tmp);
26616 tmp = gen_rtx_MEM (QImode, tmp);
26618 output_asm_insn ("jmp\t%A0", xops);
26623 if (!flag_pic || (*targetm.binds_local_p) (function))
26624 output_asm_insn ("jmp\t%P0", xops);
26629 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26630 tmp = (gen_rtx_SYMBOL_REF
26632 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26633 tmp = gen_rtx_MEM (QImode, tmp);
26635 output_asm_insn ("jmp\t%0", xops);
26638 #endif /* TARGET_MACHO */
26640 tmp = gen_rtx_REG (SImode, CX_REG);
26641 output_set_got (tmp, NULL_RTX);
26644 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26645 output_asm_insn ("jmp\t{*}%1", xops);
26651 x86_file_start (void)
26653 default_file_start ();
26655 darwin_file_start ();
26657 if (X86_FILE_START_VERSION_DIRECTIVE)
26658 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26659 if (X86_FILE_START_FLTUSED)
26660 fputs ("\t.global\t__fltused\n", asm_out_file);
26661 if (ix86_asm_dialect == ASM_INTEL)
26662 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26666 x86_field_alignment (tree field, int computed)
26668 enum machine_mode mode;
26669 tree type = TREE_TYPE (field);
26671 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26673 mode = TYPE_MODE (strip_array_types (type));
26674 if (mode == DFmode || mode == DCmode
26675 || GET_MODE_CLASS (mode) == MODE_INT
26676 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26677 return MIN (32, computed);
26681 /* Output assembler code to FILE to increment profiler label # LABELNO
26682 for profiling a function entry. */
26684 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26688 #ifndef NO_PROFILE_COUNTERS
26689 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26692 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26693 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26695 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26699 #ifndef NO_PROFILE_COUNTERS
26700 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26701 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26703 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26707 #ifndef NO_PROFILE_COUNTERS
26708 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26709 PROFILE_COUNT_REGISTER);
26711 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26715 /* We don't have exact information about the insn sizes, but we may assume
26716 quite safely that we are informed about all 1 byte insns and memory
26717 address sizes. This is enough to eliminate unnecessary padding in
26721 min_insn_size (rtx insn)
26725 if (!INSN_P (insn) || !active_insn_p (insn))
26728 /* Discard alignments we've emit and jump instructions. */
26729 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26730 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26733 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26734 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26737 /* Important case - calls are always 5 bytes.
26738 It is common to have many calls in the row. */
26740 && symbolic_reference_mentioned_p (PATTERN (insn))
26741 && !SIBLING_CALL_P (insn))
26743 if (get_attr_length (insn) <= 1)
26746 /* For normal instructions we may rely on the sizes of addresses
26747 and the presence of symbol to require 4 bytes of encoding.
26748 This is not the case for jumps where references are PC relative. */
26749 if (!JUMP_P (insn))
26751 l = get_attr_length_address (insn);
26752 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26761 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26765 ix86_avoid_jump_misspredicts (void)
26767 rtx insn, start = get_insns ();
26768 int nbytes = 0, njumps = 0;
26771 /* Look for all minimal intervals of instructions containing 4 jumps.
26772 The intervals are bounded by START and INSN. NBYTES is the total
26773 size of instructions in the interval including INSN and not including
26774 START. When the NBYTES is smaller than 16 bytes, it is possible
26775 that the end of START and INSN ends up in the same 16byte page.
26777 The smallest offset in the page INSN can start is the case where START
26778 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26779 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26781 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26784 nbytes += min_insn_size (insn);
26786 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26787 INSN_UID (insn), min_insn_size (insn));
26789 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26790 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26798 start = NEXT_INSN (start);
26799 if ((JUMP_P (start)
26800 && GET_CODE (PATTERN (start)) != ADDR_VEC
26801 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26803 njumps--, isjump = 1;
26806 nbytes -= min_insn_size (start);
26808 gcc_assert (njumps >= 0);
26810 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26811 INSN_UID (start), INSN_UID (insn), nbytes);
26813 if (njumps == 3 && isjump && nbytes < 16)
26815 int padsize = 15 - nbytes + min_insn_size (insn);
26818 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26819 INSN_UID (insn), padsize);
26820 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26825 /* AMD Athlon works faster
26826 when RET is not destination of conditional jump or directly preceded
26827 by other jump instruction. We avoid the penalty by inserting NOP just
26828 before the RET instructions in such cases. */
26830 ix86_pad_returns (void)
26835 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26837 basic_block bb = e->src;
26838 rtx ret = BB_END (bb);
26840 bool replace = false;
26842 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26843 || optimize_bb_for_size_p (bb))
26845 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26846 if (active_insn_p (prev) || LABEL_P (prev))
26848 if (prev && LABEL_P (prev))
26853 FOR_EACH_EDGE (e, ei, bb->preds)
26854 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26855 && !(e->flags & EDGE_FALLTHRU))
26860 prev = prev_active_insn (ret);
26862 && ((JUMP_P (prev) && any_condjump_p (prev))
26865 /* Empty functions get branch mispredict even when the jump destination
26866 is not visible to us. */
26867 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26872 emit_insn_before (gen_return_internal_long (), ret);
26878 /* Implement machine specific optimizations. We implement padding of returns
26879 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26883 if (TARGET_PAD_RETURNS && optimize
26884 && optimize_function_for_speed_p (cfun))
26885 ix86_pad_returns ();
26886 if (TARGET_FOUR_JUMP_LIMIT && optimize
26887 && optimize_function_for_speed_p (cfun))
26888 ix86_avoid_jump_misspredicts ();
26891 /* Return nonzero when QImode register that must be represented via REX prefix
26894 x86_extended_QIreg_mentioned_p (rtx insn)
26897 extract_insn_cached (insn);
26898 for (i = 0; i < recog_data.n_operands; i++)
26899 if (REG_P (recog_data.operand[i])
26900 && REGNO (recog_data.operand[i]) > BX_REG)
26905 /* Return nonzero when P points to register encoded via REX prefix.
26906 Called via for_each_rtx. */
26908 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26910 unsigned int regno;
26913 regno = REGNO (*p);
26914 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26917 /* Return true when INSN mentions register that must be encoded using REX
26920 x86_extended_reg_mentioned_p (rtx insn)
26922 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26923 extended_reg_mentioned_1, NULL);
26926 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26927 optabs would emit if we didn't have TFmode patterns. */
26930 x86_emit_floatuns (rtx operands[2])
26932 rtx neglab, donelab, i0, i1, f0, in, out;
26933 enum machine_mode mode, inmode;
26935 inmode = GET_MODE (operands[1]);
26936 gcc_assert (inmode == SImode || inmode == DImode);
26939 in = force_reg (inmode, operands[1]);
26940 mode = GET_MODE (out);
26941 neglab = gen_label_rtx ();
26942 donelab = gen_label_rtx ();
26943 f0 = gen_reg_rtx (mode);
26945 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26947 expand_float (out, in, 0);
26949 emit_jump_insn (gen_jump (donelab));
26952 emit_label (neglab);
26954 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26956 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26958 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26960 expand_float (f0, i0, 0);
26962 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26964 emit_label (donelab);
26967 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26968 with all elements equal to VAR. Return true if successful. */
26971 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26972 rtx target, rtx val)
26974 enum machine_mode hmode, smode, wsmode, wvmode;
26989 val = force_reg (GET_MODE_INNER (mode), val);
26990 x = gen_rtx_VEC_DUPLICATE (mode, val);
26991 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26997 if (TARGET_SSE || TARGET_3DNOW_A)
26999 val = gen_lowpart (SImode, val);
27000 x = gen_rtx_TRUNCATE (HImode, val);
27001 x = gen_rtx_VEC_DUPLICATE (mode, x);
27002 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27024 /* Extend HImode to SImode using a paradoxical SUBREG. */
27025 tmp1 = gen_reg_rtx (SImode);
27026 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27027 /* Insert the SImode value as low element of V4SImode vector. */
27028 tmp2 = gen_reg_rtx (V4SImode);
27029 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27030 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27031 CONST0_RTX (V4SImode),
27033 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27034 /* Cast the V4SImode vector back to a V8HImode vector. */
27035 tmp1 = gen_reg_rtx (V8HImode);
27036 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27037 /* Duplicate the low short through the whole low SImode word. */
27038 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27039 /* Cast the V8HImode vector back to a V4SImode vector. */
27040 tmp2 = gen_reg_rtx (V4SImode);
27041 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27042 /* Replicate the low element of the V4SImode vector. */
27043 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27044 /* Cast the V2SImode back to V8HImode, and store in target. */
27045 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27056 /* Extend QImode to SImode using a paradoxical SUBREG. */
27057 tmp1 = gen_reg_rtx (SImode);
27058 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27059 /* Insert the SImode value as low element of V4SImode vector. */
27060 tmp2 = gen_reg_rtx (V4SImode);
27061 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27062 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27063 CONST0_RTX (V4SImode),
27065 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27066 /* Cast the V4SImode vector back to a V16QImode vector. */
27067 tmp1 = gen_reg_rtx (V16QImode);
27068 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27069 /* Duplicate the low byte through the whole low SImode word. */
27070 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27071 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27072 /* Cast the V16QImode vector back to a V4SImode vector. */
27073 tmp2 = gen_reg_rtx (V4SImode);
27074 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27075 /* Replicate the low element of the V4SImode vector. */
27076 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27077 /* Cast the V2SImode back to V16QImode, and store in target. */
27078 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27086 /* Replicate the value once into the next wider mode and recurse. */
27087 val = convert_modes (wsmode, smode, val, true);
27088 x = expand_simple_binop (wsmode, ASHIFT, val,
27089 GEN_INT (GET_MODE_BITSIZE (smode)),
27090 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27091 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27093 x = gen_reg_rtx (wvmode);
27094 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27095 gcc_unreachable ();
27096 emit_move_insn (target, gen_lowpart (mode, x));
27119 rtx tmp = gen_reg_rtx (hmode);
27120 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27121 emit_insn (gen_rtx_SET (VOIDmode, target,
27122 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27131 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27132 whose ONE_VAR element is VAR, and other elements are zero. Return true
27136 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27137 rtx target, rtx var, int one_var)
27139 enum machine_mode vsimode;
27142 bool use_vector_set = false;
27147 /* For SSE4.1, we normally use vector set. But if the second
27148 element is zero and inter-unit moves are OK, we use movq
27150 use_vector_set = (TARGET_64BIT
27152 && !(TARGET_INTER_UNIT_MOVES
27158 use_vector_set = TARGET_SSE4_1;
27161 use_vector_set = TARGET_SSE2;
27164 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27171 use_vector_set = TARGET_AVX;
27174 /* Use ix86_expand_vector_set in 64bit mode only. */
27175 use_vector_set = TARGET_AVX && TARGET_64BIT;
27181 if (use_vector_set)
27183 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27184 var = force_reg (GET_MODE_INNER (mode), var);
27185 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27201 var = force_reg (GET_MODE_INNER (mode), var);
27202 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27203 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27208 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27209 new_target = gen_reg_rtx (mode);
27211 new_target = target;
27212 var = force_reg (GET_MODE_INNER (mode), var);
27213 x = gen_rtx_VEC_DUPLICATE (mode, var);
27214 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27215 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27218 /* We need to shuffle the value to the correct position, so
27219 create a new pseudo to store the intermediate result. */
27221 /* With SSE2, we can use the integer shuffle insns. */
27222 if (mode != V4SFmode && TARGET_SSE2)
27224 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27226 GEN_INT (one_var == 1 ? 0 : 1),
27227 GEN_INT (one_var == 2 ? 0 : 1),
27228 GEN_INT (one_var == 3 ? 0 : 1)));
27229 if (target != new_target)
27230 emit_move_insn (target, new_target);
27234 /* Otherwise convert the intermediate result to V4SFmode and
27235 use the SSE1 shuffle instructions. */
27236 if (mode != V4SFmode)
27238 tmp = gen_reg_rtx (V4SFmode);
27239 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27244 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27246 GEN_INT (one_var == 1 ? 0 : 1),
27247 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27248 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27250 if (mode != V4SFmode)
27251 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27252 else if (tmp != target)
27253 emit_move_insn (target, tmp);
27255 else if (target != new_target)
27256 emit_move_insn (target, new_target);
27261 vsimode = V4SImode;
27267 vsimode = V2SImode;
27273 /* Zero extend the variable element to SImode and recurse. */
27274 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27276 x = gen_reg_rtx (vsimode);
27277 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27279 gcc_unreachable ();
27281 emit_move_insn (target, gen_lowpart (mode, x));
27289 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27290 consisting of the values in VALS. It is known that all elements
27291 except ONE_VAR are constants. Return true if successful. */
27294 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27295 rtx target, rtx vals, int one_var)
27297 rtx var = XVECEXP (vals, 0, one_var);
27298 enum machine_mode wmode;
27301 const_vec = copy_rtx (vals);
27302 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27303 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27311 /* For the two element vectors, it's just as easy to use
27312 the general case. */
27316 /* Use ix86_expand_vector_set in 64bit mode only. */
27339 /* There's no way to set one QImode entry easily. Combine
27340 the variable value with its adjacent constant value, and
27341 promote to an HImode set. */
27342 x = XVECEXP (vals, 0, one_var ^ 1);
27345 var = convert_modes (HImode, QImode, var, true);
27346 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27347 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27348 x = GEN_INT (INTVAL (x) & 0xff);
27352 var = convert_modes (HImode, QImode, var, true);
27353 x = gen_int_mode (INTVAL (x) << 8, HImode);
27355 if (x != const0_rtx)
27356 var = expand_simple_binop (HImode, IOR, var, x, var,
27357 1, OPTAB_LIB_WIDEN);
27359 x = gen_reg_rtx (wmode);
27360 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27361 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27363 emit_move_insn (target, gen_lowpart (mode, x));
27370 emit_move_insn (target, const_vec);
27371 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27375 /* A subroutine of ix86_expand_vector_init_general. Use vector
27376 concatenate to handle the most general case: all values variable,
27377 and none identical. */
27380 ix86_expand_vector_init_concat (enum machine_mode mode,
27381 rtx target, rtx *ops, int n)
27383 enum machine_mode cmode, hmode = VOIDmode;
27384 rtx first[8], second[4];
27424 gcc_unreachable ();
27427 if (!register_operand (ops[1], cmode))
27428 ops[1] = force_reg (cmode, ops[1]);
27429 if (!register_operand (ops[0], cmode))
27430 ops[0] = force_reg (cmode, ops[0]);
27431 emit_insn (gen_rtx_SET (VOIDmode, target,
27432 gen_rtx_VEC_CONCAT (mode, ops[0],
27452 gcc_unreachable ();
27468 gcc_unreachable ();
27473 /* FIXME: We process inputs backward to help RA. PR 36222. */
27476 for (; i > 0; i -= 2, j--)
27478 first[j] = gen_reg_rtx (cmode);
27479 v = gen_rtvec (2, ops[i - 1], ops[i]);
27480 ix86_expand_vector_init (false, first[j],
27481 gen_rtx_PARALLEL (cmode, v));
27487 gcc_assert (hmode != VOIDmode);
27488 for (i = j = 0; i < n; i += 2, j++)
27490 second[j] = gen_reg_rtx (hmode);
27491 ix86_expand_vector_init_concat (hmode, second [j],
27495 ix86_expand_vector_init_concat (mode, target, second, n);
27498 ix86_expand_vector_init_concat (mode, target, first, n);
27502 gcc_unreachable ();
27506 /* A subroutine of ix86_expand_vector_init_general. Use vector
27507 interleave to handle the most general case: all values variable,
27508 and none identical. */
27511 ix86_expand_vector_init_interleave (enum machine_mode mode,
27512 rtx target, rtx *ops, int n)
27514 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27517 rtx (*gen_load_even) (rtx, rtx, rtx);
27518 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27519 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27524 gen_load_even = gen_vec_setv8hi;
27525 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27526 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27527 inner_mode = HImode;
27528 first_imode = V4SImode;
27529 second_imode = V2DImode;
27530 third_imode = VOIDmode;
27533 gen_load_even = gen_vec_setv16qi;
27534 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27535 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27536 inner_mode = QImode;
27537 first_imode = V8HImode;
27538 second_imode = V4SImode;
27539 third_imode = V2DImode;
27542 gcc_unreachable ();
27545 for (i = 0; i < n; i++)
27547 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27548 op0 = gen_reg_rtx (SImode);
27549 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27551 /* Insert the SImode value as low element of V4SImode vector. */
27552 op1 = gen_reg_rtx (V4SImode);
27553 op0 = gen_rtx_VEC_MERGE (V4SImode,
27554 gen_rtx_VEC_DUPLICATE (V4SImode,
27556 CONST0_RTX (V4SImode),
27558 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27560 /* Cast the V4SImode vector back to a vector in orignal mode. */
27561 op0 = gen_reg_rtx (mode);
27562 emit_move_insn (op0, gen_lowpart (mode, op1));
27564 /* Load even elements into the second positon. */
27565 emit_insn ((*gen_load_even) (op0,
27566 force_reg (inner_mode,
27570 /* Cast vector to FIRST_IMODE vector. */
27571 ops[i] = gen_reg_rtx (first_imode);
27572 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27575 /* Interleave low FIRST_IMODE vectors. */
27576 for (i = j = 0; i < n; i += 2, j++)
27578 op0 = gen_reg_rtx (first_imode);
27579 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27581 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27582 ops[j] = gen_reg_rtx (second_imode);
27583 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27586 /* Interleave low SECOND_IMODE vectors. */
27587 switch (second_imode)
27590 for (i = j = 0; i < n / 2; i += 2, j++)
27592 op0 = gen_reg_rtx (second_imode);
27593 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27596 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27598 ops[j] = gen_reg_rtx (third_imode);
27599 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27601 second_imode = V2DImode;
27602 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27606 op0 = gen_reg_rtx (second_imode);
27607 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27610 /* Cast the SECOND_IMODE vector back to a vector on original
27612 emit_insn (gen_rtx_SET (VOIDmode, target,
27613 gen_lowpart (mode, op0)));
27617 gcc_unreachable ();
27621 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27622 all values variable, and none identical. */
27625 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27626 rtx target, rtx vals)
27628 rtx ops[32], op0, op1;
27629 enum machine_mode half_mode = VOIDmode;
27636 if (!mmx_ok && !TARGET_SSE)
27648 n = GET_MODE_NUNITS (mode);
27649 for (i = 0; i < n; i++)
27650 ops[i] = XVECEXP (vals, 0, i);
27651 ix86_expand_vector_init_concat (mode, target, ops, n);
27655 half_mode = V16QImode;
27659 half_mode = V8HImode;
27663 n = GET_MODE_NUNITS (mode);
27664 for (i = 0; i < n; i++)
27665 ops[i] = XVECEXP (vals, 0, i);
27666 op0 = gen_reg_rtx (half_mode);
27667 op1 = gen_reg_rtx (half_mode);
27668 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27670 ix86_expand_vector_init_interleave (half_mode, op1,
27671 &ops [n >> 1], n >> 2);
27672 emit_insn (gen_rtx_SET (VOIDmode, target,
27673 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27677 if (!TARGET_SSE4_1)
27685 /* Don't use ix86_expand_vector_init_interleave if we can't
27686 move from GPR to SSE register directly. */
27687 if (!TARGET_INTER_UNIT_MOVES)
27690 n = GET_MODE_NUNITS (mode);
27691 for (i = 0; i < n; i++)
27692 ops[i] = XVECEXP (vals, 0, i);
27693 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27701 gcc_unreachable ();
27705 int i, j, n_elts, n_words, n_elt_per_word;
27706 enum machine_mode inner_mode;
27707 rtx words[4], shift;
27709 inner_mode = GET_MODE_INNER (mode);
27710 n_elts = GET_MODE_NUNITS (mode);
27711 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27712 n_elt_per_word = n_elts / n_words;
27713 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27715 for (i = 0; i < n_words; ++i)
27717 rtx word = NULL_RTX;
27719 for (j = 0; j < n_elt_per_word; ++j)
27721 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27722 elt = convert_modes (word_mode, inner_mode, elt, true);
27728 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27729 word, 1, OPTAB_LIB_WIDEN);
27730 word = expand_simple_binop (word_mode, IOR, word, elt,
27731 word, 1, OPTAB_LIB_WIDEN);
27739 emit_move_insn (target, gen_lowpart (mode, words[0]));
27740 else if (n_words == 2)
27742 rtx tmp = gen_reg_rtx (mode);
27743 emit_clobber (tmp);
27744 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27745 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27746 emit_move_insn (target, tmp);
27748 else if (n_words == 4)
27750 rtx tmp = gen_reg_rtx (V4SImode);
27751 gcc_assert (word_mode == SImode);
27752 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27753 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27754 emit_move_insn (target, gen_lowpart (mode, tmp));
27757 gcc_unreachable ();
27761 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27762 instructions unless MMX_OK is true. */
27765 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27767 enum machine_mode mode = GET_MODE (target);
27768 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27769 int n_elts = GET_MODE_NUNITS (mode);
27770 int n_var = 0, one_var = -1;
27771 bool all_same = true, all_const_zero = true;
27775 for (i = 0; i < n_elts; ++i)
27777 x = XVECEXP (vals, 0, i);
27778 if (!(CONST_INT_P (x)
27779 || GET_CODE (x) == CONST_DOUBLE
27780 || GET_CODE (x) == CONST_FIXED))
27781 n_var++, one_var = i;
27782 else if (x != CONST0_RTX (inner_mode))
27783 all_const_zero = false;
27784 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27788 /* Constants are best loaded from the constant pool. */
27791 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27795 /* If all values are identical, broadcast the value. */
27797 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27798 XVECEXP (vals, 0, 0)))
27801 /* Values where only one field is non-constant are best loaded from
27802 the pool and overwritten via move later. */
27806 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27807 XVECEXP (vals, 0, one_var),
27811 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27815 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27819 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27821 enum machine_mode mode = GET_MODE (target);
27822 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27823 enum machine_mode half_mode;
27824 bool use_vec_merge = false;
27826 static rtx (*gen_extract[6][2]) (rtx, rtx)
27828 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27829 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27830 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27831 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27832 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27833 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27835 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27837 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27838 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27839 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27840 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27841 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27842 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27852 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27853 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27855 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27857 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27858 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27864 use_vec_merge = TARGET_SSE4_1;
27872 /* For the two element vectors, we implement a VEC_CONCAT with
27873 the extraction of the other element. */
27875 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27876 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27879 op0 = val, op1 = tmp;
27881 op0 = tmp, op1 = val;
27883 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27884 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27889 use_vec_merge = TARGET_SSE4_1;
27896 use_vec_merge = true;
27900 /* tmp = target = A B C D */
27901 tmp = copy_to_reg (target);
27902 /* target = A A B B */
27903 emit_insn (gen_sse_unpcklps (target, target, target));
27904 /* target = X A B B */
27905 ix86_expand_vector_set (false, target, val, 0);
27906 /* target = A X C D */
27907 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27908 GEN_INT (1), GEN_INT (0),
27909 GEN_INT (2+4), GEN_INT (3+4)));
27913 /* tmp = target = A B C D */
27914 tmp = copy_to_reg (target);
27915 /* tmp = X B C D */
27916 ix86_expand_vector_set (false, tmp, val, 0);
27917 /* target = A B X D */
27918 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27919 GEN_INT (0), GEN_INT (1),
27920 GEN_INT (0+4), GEN_INT (3+4)));
27924 /* tmp = target = A B C D */
27925 tmp = copy_to_reg (target);
27926 /* tmp = X B C D */
27927 ix86_expand_vector_set (false, tmp, val, 0);
27928 /* target = A B X D */
27929 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27930 GEN_INT (0), GEN_INT (1),
27931 GEN_INT (2+4), GEN_INT (0+4)));
27935 gcc_unreachable ();
27940 use_vec_merge = TARGET_SSE4_1;
27944 /* Element 0 handled by vec_merge below. */
27947 use_vec_merge = true;
27953 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27954 store into element 0, then shuffle them back. */
27958 order[0] = GEN_INT (elt);
27959 order[1] = const1_rtx;
27960 order[2] = const2_rtx;
27961 order[3] = GEN_INT (3);
27962 order[elt] = const0_rtx;
27964 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27965 order[1], order[2], order[3]));
27967 ix86_expand_vector_set (false, target, val, 0);
27969 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27970 order[1], order[2], order[3]));
27974 /* For SSE1, we have to reuse the V4SF code. */
27975 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27976 gen_lowpart (SFmode, val), elt);
27981 use_vec_merge = TARGET_SSE2;
27984 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27988 use_vec_merge = TARGET_SSE4_1;
27995 half_mode = V16QImode;
28001 half_mode = V8HImode;
28007 half_mode = V4SImode;
28013 half_mode = V2DImode;
28019 half_mode = V4SFmode;
28025 half_mode = V2DFmode;
28031 /* Compute offset. */
28035 gcc_assert (i <= 1);
28037 /* Extract the half. */
28038 tmp = gen_reg_rtx (half_mode);
28039 emit_insn ((*gen_extract[j][i]) (tmp, target));
28041 /* Put val in tmp at elt. */
28042 ix86_expand_vector_set (false, tmp, val, elt);
28045 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28054 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28055 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28056 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28060 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28062 emit_move_insn (mem, target);
28064 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28065 emit_move_insn (tmp, val);
28067 emit_move_insn (target, mem);
28072 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28074 enum machine_mode mode = GET_MODE (vec);
28075 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28076 bool use_vec_extr = false;
28089 use_vec_extr = true;
28093 use_vec_extr = TARGET_SSE4_1;
28105 tmp = gen_reg_rtx (mode);
28106 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28107 GEN_INT (elt), GEN_INT (elt),
28108 GEN_INT (elt+4), GEN_INT (elt+4)));
28112 tmp = gen_reg_rtx (mode);
28113 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28117 gcc_unreachable ();
28120 use_vec_extr = true;
28125 use_vec_extr = TARGET_SSE4_1;
28139 tmp = gen_reg_rtx (mode);
28140 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28141 GEN_INT (elt), GEN_INT (elt),
28142 GEN_INT (elt), GEN_INT (elt)));
28146 tmp = gen_reg_rtx (mode);
28147 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28151 gcc_unreachable ();
28154 use_vec_extr = true;
28159 /* For SSE1, we have to reuse the V4SF code. */
28160 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28161 gen_lowpart (V4SFmode, vec), elt);
28167 use_vec_extr = TARGET_SSE2;
28170 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28174 use_vec_extr = TARGET_SSE4_1;
28178 /* ??? Could extract the appropriate HImode element and shift. */
28185 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28186 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28188 /* Let the rtl optimizers know about the zero extension performed. */
28189 if (inner_mode == QImode || inner_mode == HImode)
28191 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28192 target = gen_lowpart (SImode, target);
28195 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28199 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28201 emit_move_insn (mem, vec);
28203 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28204 emit_move_insn (target, tmp);
28208 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28209 pattern to reduce; DEST is the destination; IN is the input vector. */
28212 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28214 rtx tmp1, tmp2, tmp3;
28216 tmp1 = gen_reg_rtx (V4SFmode);
28217 tmp2 = gen_reg_rtx (V4SFmode);
28218 tmp3 = gen_reg_rtx (V4SFmode);
28220 emit_insn (gen_sse_movhlps (tmp1, in, in));
28221 emit_insn (fn (tmp2, tmp1, in));
28223 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28224 GEN_INT (1), GEN_INT (1),
28225 GEN_INT (1+4), GEN_INT (1+4)));
28226 emit_insn (fn (dest, tmp2, tmp3));
28229 /* Target hook for scalar_mode_supported_p. */
28231 ix86_scalar_mode_supported_p (enum machine_mode mode)
28233 if (DECIMAL_FLOAT_MODE_P (mode))
28235 else if (mode == TFmode)
28238 return default_scalar_mode_supported_p (mode);
28241 /* Implements target hook vector_mode_supported_p. */
28243 ix86_vector_mode_supported_p (enum machine_mode mode)
28245 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28247 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28249 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28251 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28253 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28258 /* Target hook for c_mode_for_suffix. */
28259 static enum machine_mode
28260 ix86_c_mode_for_suffix (char suffix)
28270 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28272 We do this in the new i386 backend to maintain source compatibility
28273 with the old cc0-based compiler. */
28276 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28277 tree inputs ATTRIBUTE_UNUSED,
28280 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28282 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28287 /* Implements target vector targetm.asm.encode_section_info. This
28288 is not used by netware. */
28290 static void ATTRIBUTE_UNUSED
28291 ix86_encode_section_info (tree decl, rtx rtl, int first)
28293 default_encode_section_info (decl, rtl, first);
28295 if (TREE_CODE (decl) == VAR_DECL
28296 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28297 && ix86_in_large_data_p (decl))
28298 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28301 /* Worker function for REVERSE_CONDITION. */
28304 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28306 return (mode != CCFPmode && mode != CCFPUmode
28307 ? reverse_condition (code)
28308 : reverse_condition_maybe_unordered (code));
28311 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28315 output_387_reg_move (rtx insn, rtx *operands)
28317 if (REG_P (operands[0]))
28319 if (REG_P (operands[1])
28320 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28322 if (REGNO (operands[0]) == FIRST_STACK_REG)
28323 return output_387_ffreep (operands, 0);
28324 return "fstp\t%y0";
28326 if (STACK_TOP_P (operands[0]))
28327 return "fld%z1\t%y1";
28330 else if (MEM_P (operands[0]))
28332 gcc_assert (REG_P (operands[1]));
28333 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28334 return "fstp%z0\t%y0";
28337 /* There is no non-popping store to memory for XFmode.
28338 So if we need one, follow the store with a load. */
28339 if (GET_MODE (operands[0]) == XFmode)
28340 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28342 return "fst%z0\t%y0";
28349 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28350 FP status register is set. */
28353 ix86_emit_fp_unordered_jump (rtx label)
28355 rtx reg = gen_reg_rtx (HImode);
28358 emit_insn (gen_x86_fnstsw_1 (reg));
28360 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28362 emit_insn (gen_x86_sahf_1 (reg));
28364 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28365 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28369 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28371 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28372 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28375 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28376 gen_rtx_LABEL_REF (VOIDmode, label),
28378 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28380 emit_jump_insn (temp);
28381 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28384 /* Output code to perform a log1p XFmode calculation. */
28386 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28388 rtx label1 = gen_label_rtx ();
28389 rtx label2 = gen_label_rtx ();
28391 rtx tmp = gen_reg_rtx (XFmode);
28392 rtx tmp2 = gen_reg_rtx (XFmode);
28394 emit_insn (gen_absxf2 (tmp, op1));
28395 emit_insn (gen_cmpxf (tmp,
28396 CONST_DOUBLE_FROM_REAL_VALUE (
28397 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28399 emit_jump_insn (gen_bge (label1));
28401 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28402 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28403 emit_jump (label2);
28405 emit_label (label1);
28406 emit_move_insn (tmp, CONST1_RTX (XFmode));
28407 emit_insn (gen_addxf3 (tmp, op1, tmp));
28408 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28409 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28411 emit_label (label2);
28414 /* Output code to perform a Newton-Rhapson approximation of a single precision
28415 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28417 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28419 rtx x0, x1, e0, e1, two;
28421 x0 = gen_reg_rtx (mode);
28422 e0 = gen_reg_rtx (mode);
28423 e1 = gen_reg_rtx (mode);
28424 x1 = gen_reg_rtx (mode);
28426 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28428 if (VECTOR_MODE_P (mode))
28429 two = ix86_build_const_vector (SFmode, true, two);
28431 two = force_reg (mode, two);
28433 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28435 /* x0 = rcp(b) estimate */
28436 emit_insn (gen_rtx_SET (VOIDmode, x0,
28437 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28440 emit_insn (gen_rtx_SET (VOIDmode, e0,
28441 gen_rtx_MULT (mode, x0, b)));
28443 emit_insn (gen_rtx_SET (VOIDmode, e1,
28444 gen_rtx_MINUS (mode, two, e0)));
28446 emit_insn (gen_rtx_SET (VOIDmode, x1,
28447 gen_rtx_MULT (mode, x0, e1)));
28449 emit_insn (gen_rtx_SET (VOIDmode, res,
28450 gen_rtx_MULT (mode, a, x1)));
28453 /* Output code to perform a Newton-Rhapson approximation of a
28454 single precision floating point [reciprocal] square root. */
28456 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28459 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28462 x0 = gen_reg_rtx (mode);
28463 e0 = gen_reg_rtx (mode);
28464 e1 = gen_reg_rtx (mode);
28465 e2 = gen_reg_rtx (mode);
28466 e3 = gen_reg_rtx (mode);
28468 real_from_integer (&r, VOIDmode, -3, -1, 0);
28469 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28471 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28472 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28474 if (VECTOR_MODE_P (mode))
28476 mthree = ix86_build_const_vector (SFmode, true, mthree);
28477 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28480 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28481 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28483 /* x0 = rsqrt(a) estimate */
28484 emit_insn (gen_rtx_SET (VOIDmode, x0,
28485 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28488 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28493 zero = gen_reg_rtx (mode);
28494 mask = gen_reg_rtx (mode);
28496 zero = force_reg (mode, CONST0_RTX(mode));
28497 emit_insn (gen_rtx_SET (VOIDmode, mask,
28498 gen_rtx_NE (mode, zero, a)));
28500 emit_insn (gen_rtx_SET (VOIDmode, x0,
28501 gen_rtx_AND (mode, x0, mask)));
28505 emit_insn (gen_rtx_SET (VOIDmode, e0,
28506 gen_rtx_MULT (mode, x0, a)));
28508 emit_insn (gen_rtx_SET (VOIDmode, e1,
28509 gen_rtx_MULT (mode, e0, x0)));
28512 mthree = force_reg (mode, mthree);
28513 emit_insn (gen_rtx_SET (VOIDmode, e2,
28514 gen_rtx_PLUS (mode, e1, mthree)));
28516 mhalf = force_reg (mode, mhalf);
28518 /* e3 = -.5 * x0 */
28519 emit_insn (gen_rtx_SET (VOIDmode, e3,
28520 gen_rtx_MULT (mode, x0, mhalf)));
28522 /* e3 = -.5 * e0 */
28523 emit_insn (gen_rtx_SET (VOIDmode, e3,
28524 gen_rtx_MULT (mode, e0, mhalf)));
28525 /* ret = e2 * e3 */
28526 emit_insn (gen_rtx_SET (VOIDmode, res,
28527 gen_rtx_MULT (mode, e2, e3)));
28530 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28532 static void ATTRIBUTE_UNUSED
28533 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28536 /* With Binutils 2.15, the "@unwind" marker must be specified on
28537 every occurrence of the ".eh_frame" section, not just the first
28540 && strcmp (name, ".eh_frame") == 0)
28542 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28543 flags & SECTION_WRITE ? "aw" : "a");
28546 default_elf_asm_named_section (name, flags, decl);
28549 /* Return the mangling of TYPE if it is an extended fundamental type. */
28551 static const char *
28552 ix86_mangle_type (const_tree type)
28554 type = TYPE_MAIN_VARIANT (type);
28556 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28557 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28560 switch (TYPE_MODE (type))
28563 /* __float128 is "g". */
28566 /* "long double" or __float80 is "e". */
28573 /* For 32-bit code we can save PIC register setup by using
28574 __stack_chk_fail_local hidden function instead of calling
28575 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28576 register, so it is better to call __stack_chk_fail directly. */
28579 ix86_stack_protect_fail (void)
28581 return TARGET_64BIT
28582 ? default_external_stack_protect_fail ()
28583 : default_hidden_stack_protect_fail ();
28586 /* Select a format to encode pointers in exception handling data. CODE
28587 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28588 true if the symbol may be affected by dynamic relocations.
28590 ??? All x86 object file formats are capable of representing this.
28591 After all, the relocation needed is the same as for the call insn.
28592 Whether or not a particular assembler allows us to enter such, I
28593 guess we'll have to see. */
28595 asm_preferred_eh_data_format (int code, int global)
28599 int type = DW_EH_PE_sdata8;
28601 || ix86_cmodel == CM_SMALL_PIC
28602 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28603 type = DW_EH_PE_sdata4;
28604 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28606 if (ix86_cmodel == CM_SMALL
28607 || (ix86_cmodel == CM_MEDIUM && code))
28608 return DW_EH_PE_udata4;
28609 return DW_EH_PE_absptr;
28612 /* Expand copysign from SIGN to the positive value ABS_VALUE
28613 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28616 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28618 enum machine_mode mode = GET_MODE (sign);
28619 rtx sgn = gen_reg_rtx (mode);
28620 if (mask == NULL_RTX)
28622 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28623 if (!VECTOR_MODE_P (mode))
28625 /* We need to generate a scalar mode mask in this case. */
28626 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28627 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28628 mask = gen_reg_rtx (mode);
28629 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28633 mask = gen_rtx_NOT (mode, mask);
28634 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28635 gen_rtx_AND (mode, mask, sign)));
28636 emit_insn (gen_rtx_SET (VOIDmode, result,
28637 gen_rtx_IOR (mode, abs_value, sgn)));
28640 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28641 mask for masking out the sign-bit is stored in *SMASK, if that is
28644 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28646 enum machine_mode mode = GET_MODE (op0);
28649 xa = gen_reg_rtx (mode);
28650 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28651 if (!VECTOR_MODE_P (mode))
28653 /* We need to generate a scalar mode mask in this case. */
28654 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28655 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28656 mask = gen_reg_rtx (mode);
28657 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28659 emit_insn (gen_rtx_SET (VOIDmode, xa,
28660 gen_rtx_AND (mode, op0, mask)));
28668 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28669 swapping the operands if SWAP_OPERANDS is true. The expanded
28670 code is a forward jump to a newly created label in case the
28671 comparison is true. The generated label rtx is returned. */
28673 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28674 bool swap_operands)
28685 label = gen_label_rtx ();
28686 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28687 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28688 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28689 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28690 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28691 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28692 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28693 JUMP_LABEL (tmp) = label;
28698 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28699 using comparison code CODE. Operands are swapped for the comparison if
28700 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28702 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28703 bool swap_operands)
28705 enum machine_mode mode = GET_MODE (op0);
28706 rtx mask = gen_reg_rtx (mode);
28715 if (mode == DFmode)
28716 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28717 gen_rtx_fmt_ee (code, mode, op0, op1)));
28719 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28720 gen_rtx_fmt_ee (code, mode, op0, op1)));
28725 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28726 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28728 ix86_gen_TWO52 (enum machine_mode mode)
28730 REAL_VALUE_TYPE TWO52r;
28733 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28734 TWO52 = const_double_from_real_value (TWO52r, mode);
28735 TWO52 = force_reg (mode, TWO52);
28740 /* Expand SSE sequence for computing lround from OP1 storing
28743 ix86_expand_lround (rtx op0, rtx op1)
28745 /* C code for the stuff we're doing below:
28746 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28749 enum machine_mode mode = GET_MODE (op1);
28750 const struct real_format *fmt;
28751 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28754 /* load nextafter (0.5, 0.0) */
28755 fmt = REAL_MODE_FORMAT (mode);
28756 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28757 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28759 /* adj = copysign (0.5, op1) */
28760 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28761 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28763 /* adj = op1 + adj */
28764 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28766 /* op0 = (imode)adj */
28767 expand_fix (op0, adj, 0);
28770 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28773 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28775 /* C code for the stuff we're doing below (for do_floor):
28777 xi -= (double)xi > op1 ? 1 : 0;
28780 enum machine_mode fmode = GET_MODE (op1);
28781 enum machine_mode imode = GET_MODE (op0);
28782 rtx ireg, freg, label, tmp;
28784 /* reg = (long)op1 */
28785 ireg = gen_reg_rtx (imode);
28786 expand_fix (ireg, op1, 0);
28788 /* freg = (double)reg */
28789 freg = gen_reg_rtx (fmode);
28790 expand_float (freg, ireg, 0);
28792 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28793 label = ix86_expand_sse_compare_and_jump (UNLE,
28794 freg, op1, !do_floor);
28795 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28796 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28797 emit_move_insn (ireg, tmp);
28799 emit_label (label);
28800 LABEL_NUSES (label) = 1;
28802 emit_move_insn (op0, ireg);
28805 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28806 result in OPERAND0. */
28808 ix86_expand_rint (rtx operand0, rtx operand1)
28810 /* C code for the stuff we're doing below:
28811 xa = fabs (operand1);
28812 if (!isless (xa, 2**52))
28814 xa = xa + 2**52 - 2**52;
28815 return copysign (xa, operand1);
28817 enum machine_mode mode = GET_MODE (operand0);
28818 rtx res, xa, label, TWO52, mask;
28820 res = gen_reg_rtx (mode);
28821 emit_move_insn (res, operand1);
28823 /* xa = abs (operand1) */
28824 xa = ix86_expand_sse_fabs (res, &mask);
28826 /* if (!isless (xa, TWO52)) goto label; */
28827 TWO52 = ix86_gen_TWO52 (mode);
28828 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28830 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28831 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28833 ix86_sse_copysign_to_positive (res, xa, res, mask);
28835 emit_label (label);
28836 LABEL_NUSES (label) = 1;
28838 emit_move_insn (operand0, res);
28841 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28844 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28846 /* C code for the stuff we expand below.
28847 double xa = fabs (x), x2;
28848 if (!isless (xa, TWO52))
28850 xa = xa + TWO52 - TWO52;
28851 x2 = copysign (xa, x);
28860 enum machine_mode mode = GET_MODE (operand0);
28861 rtx xa, TWO52, tmp, label, one, res, mask;
28863 TWO52 = ix86_gen_TWO52 (mode);
28865 /* Temporary for holding the result, initialized to the input
28866 operand to ease control flow. */
28867 res = gen_reg_rtx (mode);
28868 emit_move_insn (res, operand1);
28870 /* xa = abs (operand1) */
28871 xa = ix86_expand_sse_fabs (res, &mask);
28873 /* if (!isless (xa, TWO52)) goto label; */
28874 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28876 /* xa = xa + TWO52 - TWO52; */
28877 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28878 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28880 /* xa = copysign (xa, operand1) */
28881 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28883 /* generate 1.0 or -1.0 */
28884 one = force_reg (mode,
28885 const_double_from_real_value (do_floor
28886 ? dconst1 : dconstm1, mode));
28888 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28889 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28890 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28891 gen_rtx_AND (mode, one, tmp)));
28892 /* We always need to subtract here to preserve signed zero. */
28893 tmp = expand_simple_binop (mode, MINUS,
28894 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28895 emit_move_insn (res, tmp);
28897 emit_label (label);
28898 LABEL_NUSES (label) = 1;
28900 emit_move_insn (operand0, res);
28903 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28906 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28908 /* C code for the stuff we expand below.
28909 double xa = fabs (x), x2;
28910 if (!isless (xa, TWO52))
28912 x2 = (double)(long)x;
28919 if (HONOR_SIGNED_ZEROS (mode))
28920 return copysign (x2, x);
28923 enum machine_mode mode = GET_MODE (operand0);
28924 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28926 TWO52 = ix86_gen_TWO52 (mode);
28928 /* Temporary for holding the result, initialized to the input
28929 operand to ease control flow. */
28930 res = gen_reg_rtx (mode);
28931 emit_move_insn (res, operand1);
28933 /* xa = abs (operand1) */
28934 xa = ix86_expand_sse_fabs (res, &mask);
28936 /* if (!isless (xa, TWO52)) goto label; */
28937 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28939 /* xa = (double)(long)x */
28940 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28941 expand_fix (xi, res, 0);
28942 expand_float (xa, xi, 0);
28945 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28947 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28948 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28949 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28950 gen_rtx_AND (mode, one, tmp)));
28951 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28952 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28953 emit_move_insn (res, tmp);
28955 if (HONOR_SIGNED_ZEROS (mode))
28956 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28958 emit_label (label);
28959 LABEL_NUSES (label) = 1;
28961 emit_move_insn (operand0, res);
28964 /* Expand SSE sequence for computing round from OPERAND1 storing
28965 into OPERAND0. Sequence that works without relying on DImode truncation
28966 via cvttsd2siq that is only available on 64bit targets. */
28968 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28970 /* C code for the stuff we expand below.
28971 double xa = fabs (x), xa2, x2;
28972 if (!isless (xa, TWO52))
28974 Using the absolute value and copying back sign makes
28975 -0.0 -> -0.0 correct.
28976 xa2 = xa + TWO52 - TWO52;
28981 else if (dxa > 0.5)
28983 x2 = copysign (xa2, x);
28986 enum machine_mode mode = GET_MODE (operand0);
28987 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28989 TWO52 = ix86_gen_TWO52 (mode);
28991 /* Temporary for holding the result, initialized to the input
28992 operand to ease control flow. */
28993 res = gen_reg_rtx (mode);
28994 emit_move_insn (res, operand1);
28996 /* xa = abs (operand1) */
28997 xa = ix86_expand_sse_fabs (res, &mask);
28999 /* if (!isless (xa, TWO52)) goto label; */
29000 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29002 /* xa2 = xa + TWO52 - TWO52; */
29003 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29004 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29006 /* dxa = xa2 - xa; */
29007 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29009 /* generate 0.5, 1.0 and -0.5 */
29010 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29011 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29012 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29016 tmp = gen_reg_rtx (mode);
29017 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29018 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29019 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29020 gen_rtx_AND (mode, one, tmp)));
29021 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29022 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29023 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29024 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29025 gen_rtx_AND (mode, one, tmp)));
29026 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29028 /* res = copysign (xa2, operand1) */
29029 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29031 emit_label (label);
29032 LABEL_NUSES (label) = 1;
29034 emit_move_insn (operand0, res);
29037 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29040 ix86_expand_trunc (rtx operand0, rtx operand1)
29042 /* C code for SSE variant we expand below.
29043 double xa = fabs (x), x2;
29044 if (!isless (xa, TWO52))
29046 x2 = (double)(long)x;
29047 if (HONOR_SIGNED_ZEROS (mode))
29048 return copysign (x2, x);
29051 enum machine_mode mode = GET_MODE (operand0);
29052 rtx xa, xi, TWO52, label, res, mask;
29054 TWO52 = ix86_gen_TWO52 (mode);
29056 /* Temporary for holding the result, initialized to the input
29057 operand to ease control flow. */
29058 res = gen_reg_rtx (mode);
29059 emit_move_insn (res, operand1);
29061 /* xa = abs (operand1) */
29062 xa = ix86_expand_sse_fabs (res, &mask);
29064 /* if (!isless (xa, TWO52)) goto label; */
29065 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29067 /* x = (double)(long)x */
29068 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29069 expand_fix (xi, res, 0);
29070 expand_float (res, xi, 0);
29072 if (HONOR_SIGNED_ZEROS (mode))
29073 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29075 emit_label (label);
29076 LABEL_NUSES (label) = 1;
29078 emit_move_insn (operand0, res);
29081 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29084 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29086 enum machine_mode mode = GET_MODE (operand0);
29087 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29089 /* C code for SSE variant we expand below.
29090 double xa = fabs (x), x2;
29091 if (!isless (xa, TWO52))
29093 xa2 = xa + TWO52 - TWO52;
29097 x2 = copysign (xa2, x);
29101 TWO52 = ix86_gen_TWO52 (mode);
29103 /* Temporary for holding the result, initialized to the input
29104 operand to ease control flow. */
29105 res = gen_reg_rtx (mode);
29106 emit_move_insn (res, operand1);
29108 /* xa = abs (operand1) */
29109 xa = ix86_expand_sse_fabs (res, &smask);
29111 /* if (!isless (xa, TWO52)) goto label; */
29112 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29114 /* res = xa + TWO52 - TWO52; */
29115 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29116 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29117 emit_move_insn (res, tmp);
29120 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29122 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29123 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29124 emit_insn (gen_rtx_SET (VOIDmode, mask,
29125 gen_rtx_AND (mode, mask, one)));
29126 tmp = expand_simple_binop (mode, MINUS,
29127 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29128 emit_move_insn (res, tmp);
29130 /* res = copysign (res, operand1) */
29131 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29133 emit_label (label);
29134 LABEL_NUSES (label) = 1;
29136 emit_move_insn (operand0, res);
29139 /* Expand SSE sequence for computing round from OPERAND1 storing
29142 ix86_expand_round (rtx operand0, rtx operand1)
29144 /* C code for the stuff we're doing below:
29145 double xa = fabs (x);
29146 if (!isless (xa, TWO52))
29148 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29149 return copysign (xa, x);
29151 enum machine_mode mode = GET_MODE (operand0);
29152 rtx res, TWO52, xa, label, xi, half, mask;
29153 const struct real_format *fmt;
29154 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29156 /* Temporary for holding the result, initialized to the input
29157 operand to ease control flow. */
29158 res = gen_reg_rtx (mode);
29159 emit_move_insn (res, operand1);
29161 TWO52 = ix86_gen_TWO52 (mode);
29162 xa = ix86_expand_sse_fabs (res, &mask);
29163 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29165 /* load nextafter (0.5, 0.0) */
29166 fmt = REAL_MODE_FORMAT (mode);
29167 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29168 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29170 /* xa = xa + 0.5 */
29171 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29172 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29174 /* xa = (double)(int64_t)xa */
29175 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29176 expand_fix (xi, xa, 0);
29177 expand_float (xa, xi, 0);
29179 /* res = copysign (xa, operand1) */
29180 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29182 emit_label (label);
29183 LABEL_NUSES (label) = 1;
29185 emit_move_insn (operand0, res);
29189 /* Validate whether a SSE5 instruction is valid or not.
29190 OPERANDS is the array of operands.
29191 NUM is the number of operands.
29192 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29193 NUM_MEMORY is the maximum number of memory operands to accept.
29194 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29197 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29198 bool uses_oc0, int num_memory, bool commutative)
29204 /* Count the number of memory arguments */
29207 for (i = 0; i < num; i++)
29209 enum machine_mode mode = GET_MODE (operands[i]);
29210 if (register_operand (operands[i], mode))
29213 else if (memory_operand (operands[i], mode))
29215 mem_mask |= (1 << i);
29221 rtx pattern = PATTERN (insn);
29223 /* allow 0 for pcmov */
29224 if (GET_CODE (pattern) != SET
29225 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29227 || operands[i] != CONST0_RTX (mode))
29232 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29233 a memory operation. */
29234 if (num_memory < 0)
29236 num_memory = -num_memory;
29237 if ((mem_mask & (1 << (num-1))) != 0)
29239 mem_mask &= ~(1 << (num-1));
29244 /* If there were no memory operations, allow the insn */
29248 /* Do not allow the destination register to be a memory operand. */
29249 else if (mem_mask & (1 << 0))
29252 /* If there are too many memory operations, disallow the instruction. While
29253 the hardware only allows 1 memory reference, before register allocation
29254 for some insns, we allow two memory operations sometimes in order to allow
29255 code like the following to be optimized:
29257 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29259 or similar cases that are vectorized into using the fmaddss
29261 else if (mem_count > num_memory)
29264 /* Don't allow more than one memory operation if not optimizing. */
29265 else if (mem_count > 1 && !optimize)
29268 else if (num == 4 && mem_count == 1)
29270 /* formats (destination is the first argument), example fmaddss:
29271 xmm1, xmm1, xmm2, xmm3/mem
29272 xmm1, xmm1, xmm2/mem, xmm3
29273 xmm1, xmm2, xmm3/mem, xmm1
29274 xmm1, xmm2/mem, xmm3, xmm1 */
29276 return ((mem_mask == (1 << 1))
29277 || (mem_mask == (1 << 2))
29278 || (mem_mask == (1 << 3)));
29280 /* format, example pmacsdd:
29281 xmm1, xmm2, xmm3/mem, xmm1 */
29283 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29285 return (mem_mask == (1 << 2));
29288 else if (num == 4 && num_memory == 2)
29290 /* If there are two memory operations, we can load one of the memory ops
29291 into the destination register. This is for optimizing the
29292 multiply/add ops, which the combiner has optimized both the multiply
29293 and the add insns to have a memory operation. We have to be careful
29294 that the destination doesn't overlap with the inputs. */
29295 rtx op0 = operands[0];
29297 if (reg_mentioned_p (op0, operands[1])
29298 || reg_mentioned_p (op0, operands[2])
29299 || reg_mentioned_p (op0, operands[3]))
29302 /* formats (destination is the first argument), example fmaddss:
29303 xmm1, xmm1, xmm2, xmm3/mem
29304 xmm1, xmm1, xmm2/mem, xmm3
29305 xmm1, xmm2, xmm3/mem, xmm1
29306 xmm1, xmm2/mem, xmm3, xmm1
29308 For the oc0 case, we will load either operands[1] or operands[3] into
29309 operands[0], so any combination of 2 memory operands is ok. */
29313 /* format, example pmacsdd:
29314 xmm1, xmm2, xmm3/mem, xmm1
29316 For the integer multiply/add instructions be more restrictive and
29317 require operands[2] and operands[3] to be the memory operands. */
29319 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29321 return (mem_mask == ((1 << 2) | (1 << 3)));
29324 else if (num == 3 && num_memory == 1)
29326 /* formats, example protb:
29327 xmm1, xmm2, xmm3/mem
29328 xmm1, xmm2/mem, xmm3 */
29330 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29332 /* format, example comeq:
29333 xmm1, xmm2, xmm3/mem */
29335 return (mem_mask == (1 << 2));
29339 gcc_unreachable ();
29345 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29346 hardware will allow by using the destination register to load one of the
29347 memory operations. Presently this is used by the multiply/add routines to
29348 allow 2 memory references. */
29351 ix86_expand_sse5_multiple_memory (rtx operands[],
29353 enum machine_mode mode)
29355 rtx op0 = operands[0];
29357 || memory_operand (op0, mode)
29358 || reg_mentioned_p (op0, operands[1])
29359 || reg_mentioned_p (op0, operands[2])
29360 || reg_mentioned_p (op0, operands[3]))
29361 gcc_unreachable ();
29363 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29364 the destination register. */
29365 if (memory_operand (operands[1], mode))
29367 emit_move_insn (op0, operands[1]);
29370 else if (memory_operand (operands[3], mode))
29372 emit_move_insn (op0, operands[3]);
29376 gcc_unreachable ();
29382 /* Table of valid machine attributes. */
29383 static const struct attribute_spec ix86_attribute_table[] =
29385 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29386 /* Stdcall attribute says callee is responsible for popping arguments
29387 if they are not variable. */
29388 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29389 /* Fastcall attribute says callee is responsible for popping arguments
29390 if they are not variable. */
29391 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29392 /* Cdecl attribute says the callee is a normal C declaration */
29393 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29394 /* Regparm attribute specifies how many integer arguments are to be
29395 passed in registers. */
29396 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29397 /* Sseregparm attribute says we are using x86_64 calling conventions
29398 for FP arguments. */
29399 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29400 /* force_align_arg_pointer says this function realigns the stack at entry. */
29401 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29402 false, true, true, ix86_handle_cconv_attribute },
29403 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29404 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29405 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29406 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29408 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29409 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29410 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29411 SUBTARGET_ATTRIBUTE_TABLE,
29413 /* ms_abi and sysv_abi calling convention function attributes. */
29414 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29415 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29417 { NULL, 0, 0, false, false, false, NULL }
29420 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29422 x86_builtin_vectorization_cost (bool runtime_test)
29424 /* If the branch of the runtime test is taken - i.e. - the vectorized
29425 version is skipped - this incurs a misprediction cost (because the
29426 vectorized version is expected to be the fall-through). So we subtract
29427 the latency of a mispredicted branch from the costs that are incured
29428 when the vectorized version is executed.
29430 TODO: The values in individual target tables have to be tuned or new
29431 fields may be needed. For eg. on K8, the default branch path is the
29432 not-taken path. If the taken path is predicted correctly, the minimum
29433 penalty of going down the taken-path is 1 cycle. If the taken-path is
29434 not predicted correctly, then the minimum penalty is 10 cycles. */
29438 return (-(ix86_cost->cond_taken_branch_cost));
29444 /* This function returns the calling abi specific va_list type node.
29445 It returns the FNDECL specific va_list type. */
29448 ix86_fn_abi_va_list (tree fndecl)
29453 return va_list_type_node;
29454 gcc_assert (fndecl != NULL_TREE);
29455 abi = ix86_function_abi ((const_tree) fndecl);
29458 return ms_va_list_type_node;
29460 return sysv_va_list_type_node;
29463 /* Returns the canonical va_list type specified by TYPE. If there
29464 is no valid TYPE provided, it return NULL_TREE. */
29467 ix86_canonical_va_list_type (tree type)
29471 /* Resolve references and pointers to va_list type. */
29472 if (INDIRECT_REF_P (type))
29473 type = TREE_TYPE (type);
29474 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29475 type = TREE_TYPE (type);
29479 wtype = va_list_type_node;
29480 gcc_assert (wtype != NULL_TREE);
29482 if (TREE_CODE (wtype) == ARRAY_TYPE)
29484 /* If va_list is an array type, the argument may have decayed
29485 to a pointer type, e.g. by being passed to another function.
29486 In that case, unwrap both types so that we can compare the
29487 underlying records. */
29488 if (TREE_CODE (htype) == ARRAY_TYPE
29489 || POINTER_TYPE_P (htype))
29491 wtype = TREE_TYPE (wtype);
29492 htype = TREE_TYPE (htype);
29495 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29496 return va_list_type_node;
29497 wtype = sysv_va_list_type_node;
29498 gcc_assert (wtype != NULL_TREE);
29500 if (TREE_CODE (wtype) == ARRAY_TYPE)
29502 /* If va_list is an array type, the argument may have decayed
29503 to a pointer type, e.g. by being passed to another function.
29504 In that case, unwrap both types so that we can compare the
29505 underlying records. */
29506 if (TREE_CODE (htype) == ARRAY_TYPE
29507 || POINTER_TYPE_P (htype))
29509 wtype = TREE_TYPE (wtype);
29510 htype = TREE_TYPE (htype);
29513 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29514 return sysv_va_list_type_node;
29515 wtype = ms_va_list_type_node;
29516 gcc_assert (wtype != NULL_TREE);
29518 if (TREE_CODE (wtype) == ARRAY_TYPE)
29520 /* If va_list is an array type, the argument may have decayed
29521 to a pointer type, e.g. by being passed to another function.
29522 In that case, unwrap both types so that we can compare the
29523 underlying records. */
29524 if (TREE_CODE (htype) == ARRAY_TYPE
29525 || POINTER_TYPE_P (htype))
29527 wtype = TREE_TYPE (wtype);
29528 htype = TREE_TYPE (htype);
29531 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29532 return ms_va_list_type_node;
29535 return std_canonical_va_list_type (type);
29538 /* Iterate through the target-specific builtin types for va_list.
29539 IDX denotes the iterator, *PTREE is set to the result type of
29540 the va_list builtin, and *PNAME to its internal type.
29541 Returns zero if there is no element for this index, otherwise
29542 IDX should be increased upon the next call.
29543 Note, do not iterate a base builtin's name like __builtin_va_list.
29544 Used from c_common_nodes_and_builtins. */
29547 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29553 *ptree = ms_va_list_type_node;
29554 *pname = "__builtin_ms_va_list";
29557 *ptree = sysv_va_list_type_node;
29558 *pname = "__builtin_sysv_va_list";
29566 /* Initialize the GCC target structure. */
29567 #undef TARGET_RETURN_IN_MEMORY
29568 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29570 #undef TARGET_ATTRIBUTE_TABLE
29571 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29572 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29573 # undef TARGET_MERGE_DECL_ATTRIBUTES
29574 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29577 #undef TARGET_COMP_TYPE_ATTRIBUTES
29578 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29580 #undef TARGET_INIT_BUILTINS
29581 #define TARGET_INIT_BUILTINS ix86_init_builtins
29582 #undef TARGET_EXPAND_BUILTIN
29583 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29585 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29586 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29587 ix86_builtin_vectorized_function
29589 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29590 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29592 #undef TARGET_BUILTIN_RECIPROCAL
29593 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29595 #undef TARGET_ASM_FUNCTION_EPILOGUE
29596 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29598 #undef TARGET_ENCODE_SECTION_INFO
29599 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29600 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29602 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29605 #undef TARGET_ASM_OPEN_PAREN
29606 #define TARGET_ASM_OPEN_PAREN ""
29607 #undef TARGET_ASM_CLOSE_PAREN
29608 #define TARGET_ASM_CLOSE_PAREN ""
29610 #undef TARGET_ASM_ALIGNED_HI_OP
29611 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29612 #undef TARGET_ASM_ALIGNED_SI_OP
29613 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29615 #undef TARGET_ASM_ALIGNED_DI_OP
29616 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29619 #undef TARGET_ASM_UNALIGNED_HI_OP
29620 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29621 #undef TARGET_ASM_UNALIGNED_SI_OP
29622 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29623 #undef TARGET_ASM_UNALIGNED_DI_OP
29624 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29626 #undef TARGET_SCHED_ADJUST_COST
29627 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29628 #undef TARGET_SCHED_ISSUE_RATE
29629 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29630 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29631 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29632 ia32_multipass_dfa_lookahead
29634 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29635 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29638 #undef TARGET_HAVE_TLS
29639 #define TARGET_HAVE_TLS true
29641 #undef TARGET_CANNOT_FORCE_CONST_MEM
29642 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29643 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29644 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29646 #undef TARGET_DELEGITIMIZE_ADDRESS
29647 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29649 #undef TARGET_MS_BITFIELD_LAYOUT_P
29650 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29653 #undef TARGET_BINDS_LOCAL_P
29654 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29656 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29657 #undef TARGET_BINDS_LOCAL_P
29658 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29661 #undef TARGET_ASM_OUTPUT_MI_THUNK
29662 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29663 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29664 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29666 #undef TARGET_ASM_FILE_START
29667 #define TARGET_ASM_FILE_START x86_file_start
29669 #undef TARGET_DEFAULT_TARGET_FLAGS
29670 #define TARGET_DEFAULT_TARGET_FLAGS \
29672 | TARGET_SUBTARGET_DEFAULT \
29673 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29675 #undef TARGET_HANDLE_OPTION
29676 #define TARGET_HANDLE_OPTION ix86_handle_option
29678 #undef TARGET_RTX_COSTS
29679 #define TARGET_RTX_COSTS ix86_rtx_costs
29680 #undef TARGET_ADDRESS_COST
29681 #define TARGET_ADDRESS_COST ix86_address_cost
29683 #undef TARGET_FIXED_CONDITION_CODE_REGS
29684 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29685 #undef TARGET_CC_MODES_COMPATIBLE
29686 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29688 #undef TARGET_MACHINE_DEPENDENT_REORG
29689 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29691 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29692 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29694 #undef TARGET_BUILD_BUILTIN_VA_LIST
29695 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29697 #undef TARGET_FN_ABI_VA_LIST
29698 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29700 #undef TARGET_CANONICAL_VA_LIST_TYPE
29701 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29703 #undef TARGET_EXPAND_BUILTIN_VA_START
29704 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29706 #undef TARGET_MD_ASM_CLOBBERS
29707 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29709 #undef TARGET_PROMOTE_PROTOTYPES
29710 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29711 #undef TARGET_STRUCT_VALUE_RTX
29712 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29713 #undef TARGET_SETUP_INCOMING_VARARGS
29714 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29715 #undef TARGET_MUST_PASS_IN_STACK
29716 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29717 #undef TARGET_PASS_BY_REFERENCE
29718 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29719 #undef TARGET_INTERNAL_ARG_POINTER
29720 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29721 #undef TARGET_UPDATE_STACK_BOUNDARY
29722 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29723 #undef TARGET_GET_DRAP_RTX
29724 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29725 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29726 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29727 #undef TARGET_STRICT_ARGUMENT_NAMING
29728 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29730 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29731 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29733 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29734 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29736 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29737 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29739 #undef TARGET_C_MODE_FOR_SUFFIX
29740 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29743 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29744 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29747 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29748 #undef TARGET_INSERT_ATTRIBUTES
29749 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29752 #undef TARGET_MANGLE_TYPE
29753 #define TARGET_MANGLE_TYPE ix86_mangle_type
29755 #undef TARGET_STACK_PROTECT_FAIL
29756 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29758 #undef TARGET_FUNCTION_VALUE
29759 #define TARGET_FUNCTION_VALUE ix86_function_value
29761 #undef TARGET_SECONDARY_RELOAD
29762 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29764 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29765 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29767 #undef TARGET_SET_CURRENT_FUNCTION
29768 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29770 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29771 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29773 #undef TARGET_OPTION_SAVE
29774 #define TARGET_OPTION_SAVE ix86_function_specific_save
29776 #undef TARGET_OPTION_RESTORE
29777 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29779 #undef TARGET_OPTION_PRINT
29780 #define TARGET_OPTION_PRINT ix86_function_specific_print
29782 #undef TARGET_OPTION_CAN_INLINE_P
29783 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29785 #undef TARGET_EXPAND_TO_RTL_HOOK
29786 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29788 struct gcc_target targetm = TARGET_INITIALIZER;
29790 #include "gt-i386.h"
projects / platform / upstream / gcc.git / blob