2 * Copyright (C) 2007-2013 Free Software Foundation, Inc.
4 * This file is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 3, or (at your option) any
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * Under Section 7 of GPL version 3, you are granted additional
15 * permissions described in the GCC Runtime Library Exception, version
16 * 3.1, as published by the Free Software Foundation.
18 * You should have received a copy of the GNU General Public License and
19 * a copy of the GCC Runtime Library Exception along with this program;
20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 * <http://www.gnu.org/licenses/>.
25 #define bit_SSE3 (1 << 0)
26 #define bit_PCLMUL (1 << 1)
27 #define bit_LZCNT (1 << 5)
28 #define bit_SSSE3 (1 << 9)
29 #define bit_FMA (1 << 12)
30 #define bit_CMPXCHG16B (1 << 13)
31 #define bit_SSE4_1 (1 << 19)
32 #define bit_SSE4_2 (1 << 20)
33 #define bit_MOVBE (1 << 22)
34 #define bit_POPCNT (1 << 23)
35 #define bit_AES (1 << 25)
36 #define bit_XSAVE (1 << 26)
37 #define bit_OSXSAVE (1 << 27)
38 #define bit_AVX (1 << 28)
39 #define bit_F16C (1 << 29)
40 #define bit_RDRND (1 << 30)
43 #define bit_CMPXCHG8B (1 << 8)
44 #define bit_CMOV (1 << 15)
45 #define bit_MMX (1 << 23)
46 #define bit_FXSAVE (1 << 24)
47 #define bit_SSE (1 << 25)
48 #define bit_SSE2 (1 << 26)
50 /* Extended Features */
52 #define bit_LAHF_LM (1 << 0)
53 #define bit_ABM (1 << 5)
54 #define bit_SSE4a (1 << 6)
55 #define bit_PRFCHW (1 << 8)
56 #define bit_XOP (1 << 11)
57 #define bit_LWP (1 << 15)
58 #define bit_FMA4 (1 << 16)
59 #define bit_TBM (1 << 21)
62 #define bit_MMXEXT (1 << 22)
63 #define bit_LM (1 << 29)
64 #define bit_3DNOWP (1 << 30)
65 #define bit_3DNOW (1 << 31)
67 /* Extended Features (%eax == 7) */
68 #define bit_FSGSBASE (1 << 0)
69 #define bit_BMI (1 << 3)
70 #define bit_HLE (1 << 4)
71 #define bit_AVX2 (1 << 5)
72 #define bit_BMI2 (1 << 8)
73 #define bit_RTM (1 << 11)
74 #define bit_RDSEED (1 << 18)
75 #define bit_ADX (1 << 19)
77 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
78 #define bit_XSAVEOPT (1 << 0)
80 /* Signatures for different CPU implementations as returned in uses
81 of cpuid with level 0. */
82 #define signature_AMD_ebx 0x68747541
83 #define signature_AMD_ecx 0x444d4163
84 #define signature_AMD_edx 0x69746e65
86 #define signature_CENTAUR_ebx 0x746e6543
87 #define signature_CENTAUR_ecx 0x736c7561
88 #define signature_CENTAUR_edx 0x48727561
90 #define signature_CYRIX_ebx 0x69727943
91 #define signature_CYRIX_ecx 0x64616574
92 #define signature_CYRIX_edx 0x736e4978
94 #define signature_INTEL_ebx 0x756e6547
95 #define signature_INTEL_ecx 0x6c65746e
96 #define signature_INTEL_edx 0x49656e69
98 #define signature_TM1_ebx 0x6e617254
99 #define signature_TM1_ecx 0x55504361
100 #define signature_TM1_edx 0x74656d73
102 #define signature_TM2_ebx 0x756e6547
103 #define signature_TM2_ecx 0x3638784d
104 #define signature_TM2_edx 0x54656e69
106 #define signature_NSC_ebx 0x646f6547
107 #define signature_NSC_ecx 0x43534e20
108 #define signature_NSC_edx 0x79622065
110 #define signature_NEXGEN_ebx 0x4778654e
111 #define signature_NEXGEN_ecx 0x6e657669
112 #define signature_NEXGEN_edx 0x72446e65
114 #define signature_RISE_ebx 0x65736952
115 #define signature_RISE_ecx 0x65736952
116 #define signature_RISE_edx 0x65736952
118 #define signature_SIS_ebx 0x20536953
119 #define signature_SIS_ecx 0x20536953
120 #define signature_SIS_edx 0x20536953
122 #define signature_UMC_ebx 0x20434d55
123 #define signature_UMC_ecx 0x20434d55
124 #define signature_UMC_edx 0x20434d55
126 #define signature_VIA_ebx 0x20414956
127 #define signature_VIA_ecx 0x20414956
128 #define signature_VIA_edx 0x20414956
130 #define signature_VORTEX_ebx 0x74726f56
131 #define signature_VORTEX_ecx 0x436f5320
132 #define signature_VORTEX_edx 0x36387865
134 #if defined(__i386__) && defined(__PIC__)
135 /* %ebx may be the PIC register. */
137 #define __cpuid(level, a, b, c, d) \
138 __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
140 "xchg{l}\t{%%}ebx, %k1\n\t" \
141 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
144 #define __cpuid_count(level, count, a, b, c, d) \
145 __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
147 "xchg{l}\t{%%}ebx, %k1\n\t" \
148 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
149 : "0" (level), "2" (count))
151 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
152 nor alternatives in i386 code. */
153 #define __cpuid(level, a, b, c, d) \
154 __asm__ ("xchgl\t%%ebx, %k1\n\t" \
156 "xchgl\t%%ebx, %k1\n\t" \
157 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
160 #define __cpuid_count(level, count, a, b, c, d) \
161 __asm__ ("xchgl\t%%ebx, %k1\n\t" \
163 "xchgl\t%%ebx, %k1\n\t" \
164 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
165 : "0" (level), "2" (count))
167 #elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
168 /* %rbx may be the PIC register. */
169 #define __cpuid(level, a, b, c, d) \
170 __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
172 "xchg{q}\t{%%}rbx, %q1\n\t" \
173 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
176 #define __cpuid_count(level, count, a, b, c, d) \
177 __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
179 "xchg{q}\t{%%}rbx, %q1\n\t" \
180 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
181 : "0" (level), "2" (count))
183 #define __cpuid(level, a, b, c, d) \
184 __asm__ ("cpuid\n\t" \
185 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
188 #define __cpuid_count(level, count, a, b, c, d) \
189 __asm__ ("cpuid\n\t" \
190 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
191 : "0" (level), "2" (count))
194 /* Return highest supported input value for cpuid instruction. ext can
195 be either 0x0 or 0x8000000 to return highest supported value for
196 basic or extended cpuid information. Function returns 0 if cpuid
197 is not supported or whatever cpuid returns in eax register. If sig
198 pointer is non-null, then first four bytes of the signature
199 (as found in ebx register) are returned in location pointed by sig. */
201 static __inline unsigned int
202 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
204 unsigned int __eax, __ebx, __ecx, __edx;
207 /* See if we can use cpuid. On AMD64 we always can. */
209 __asm__ ("pushf{l|d}\n\t"
212 "mov{l}\t{%0, %1|%1, %0}\n\t"
213 "xor{l}\t{%2, %0|%0, %2}\n\t"
219 : "=&r" (__eax), "=&r" (__ebx)
222 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
223 nor alternatives in i386 code. */
224 __asm__ ("pushfl\n\t"
234 : "=&r" (__eax), "=&r" (__ebx)
238 if (!((__eax ^ __ebx) & 0x00200000))
242 /* Host supports cpuid. Return highest supported cpuid input value. */
243 __cpuid (__ext, __eax, __ebx, __ecx, __edx);
251 /* Return cpuid data for requested cpuid level, as found in returned
252 eax, ebx, ecx and edx registers. The function checks if cpuid is
253 supported and returns 1 for valid cpuid information or 0 for
254 unsupported cpuid level. All pointers are required to be non-null. */
257 __get_cpuid (unsigned int __level,
258 unsigned int *__eax, unsigned int *__ebx,
259 unsigned int *__ecx, unsigned int *__edx)
261 unsigned int __ext = __level & 0x80000000;
263 if (__get_cpuid_max (__ext, 0) < __level)
266 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);