1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have an insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
61 ;; ----------------------------------------------------------------------
63 ;; ----------------------------------------------------------------------
65 (define_attr "cpu" "h8300,h8300h"
66 (const (symbol_ref "cpu_type")))
68 (define_attr "type" "branch,arith"
69 (const_string "arith"))
71 ;; The size of instructions in bytes.
73 (define_attr "length" ""
74 (cond [(eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
77 (le (minus (match_dup 0) (pc))
80 (if_then_else (and (eq_attr "cpu" "h8300h")
81 (and (ge (minus (pc) (match_dup 0))
83 (le (minus (pc) (match_dup 0))
89 ;; The necessity of instruction length adjustment.
91 (define_attr "adjust_length" "yes,no"
92 (cond [(eq_attr "type" "branch") (const_string "no")]
93 (const_string "yes")))
95 ;; Condition code settings.
97 ;; none - insn does not affect cc
98 ;; none_0hit - insn does not affect cc but it does modify operand 0
99 ;; This attribute is used to keep track of when operand 0 changes.
100 ;; See the description of NOTICE_UPDATE_CC for more info.
101 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
102 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
103 ;; compare - compare instruction
104 ;; clobber - value of cc is unknown
106 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
107 (const_string "clobber"))
109 ;; ----------------------------------------------------------------------
111 ;; ----------------------------------------------------------------------
115 (define_insn "pushqi1_h8300"
116 [(parallel [(set (reg:HI SP_REG)
117 (plus:HI (reg:HI SP_REG) (const_int -2)))
118 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
119 (match_operand:QI 0 "register_operand" "r"))])]
122 [(set_attr "length" "2")
123 (set_attr "cc" "clobber")])
125 (define_insn "pushqi1_h8300hs"
126 [(parallel [(set (reg:SI SP_REG)
127 (plus:SI (reg:SI SP_REG) (const_int -4)))
128 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
129 (match_operand:QI 0 "register_operand" "r"))])]
130 "TARGET_H8300H || TARGET_H8300S"
132 [(set_attr "length" "4")
133 (set_attr "cc" "clobber")])
135 (define_expand "pushqi1"
136 [(use (match_operand:QI 0 "register_operand" ""))]
141 emit_insn (gen_pushqi1_h8300 (operands[0]));
143 emit_insn (gen_pushqi1_h8300hs (operands[0]));
148 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
149 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
151 && (register_operand (operands[0], QImode)
152 || register_operand (operands[1], QImode))"
160 [(set_attr "length" "2,2,2,2,4,4")
161 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
164 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
165 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
166 "(TARGET_H8300H || TARGET_H8300S)
167 && (register_operand (operands[0], QImode)
168 || register_operand (operands[1], QImode))"
176 [(set_attr "length" "2,2,2,2,8,8")
177 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
179 (define_expand "movqi"
180 [(set (match_operand:QI 0 "general_operand_dst" "")
181 (match_operand:QI 1 "general_operand_src" ""))]
185 /* One of the ops has to be in a register. */
186 if (!register_operand (operand0, QImode)
187 && !register_operand (operand1, QImode))
189 operands[1] = copy_to_mode_reg (QImode, operand1);
193 (define_insn "movstrictqi"
194 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
195 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
202 [(set_attr_alternative "length"
203 [(const_int 2) (const_int 2) (const_int 2)
204 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
205 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
209 (define_expand "pushhi1_h8300"
210 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
211 (match_operand:HI 0 "register_operand" ""))]
215 (define_insn "pushhi1_h8300hs"
216 [(parallel [(set (reg:SI SP_REG)
217 (plus:SI (reg:SI SP_REG) (const_int -4)))
218 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
219 (match_operand:HI 0 "register_operand" "r"))])]
220 "TARGET_H8300H || TARGET_H8300S"
222 [(set_attr "length" "4")
223 (set_attr "cc" "clobber")])
225 (define_expand "pushhi1"
226 [(use (match_operand:HI 0 "register_operand" ""))]
231 emit_insn (gen_pushhi1_h8300 (operands[0]));
233 emit_insn (gen_pushhi1_h8300hs (operands[0]));
238 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
239 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
241 && (register_operand (operands[0], HImode)
242 || register_operand (operands[1], HImode))
243 && !(GET_CODE (operands[0]) == MEM
244 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
245 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
246 && GET_CODE (operands[1]) == REG
247 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
255 [(set_attr "length" "2,2,2,4,4,4")
256 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
259 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
260 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
261 "(TARGET_H8300H || TARGET_H8300S)
262 && (register_operand (operands[0], HImode)
263 || register_operand (operands[1], HImode))"
271 [(set_attr "length" "2,2,2,4,8,8")
272 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
274 (define_expand "movhi"
275 [(set (match_operand:HI 0 "general_operand_dst" "")
276 (match_operand:HI 1 "general_operand_src" ""))]
280 /* One of the ops has to be in a register. */
281 if (!register_operand (operand1, HImode)
282 && !register_operand (operand0, HImode))
284 operands[1] = copy_to_mode_reg (HImode, operand1);
288 (define_insn "movstricthi"
289 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
290 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
297 [(set_attr_alternative "length"
298 [(const_int 2) (const_int 2) (const_int 4)
299 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
300 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
304 (define_expand "movsi"
305 [(set (match_operand:SI 0 "general_operand_dst" "")
306 (match_operand:SI 1 "general_operand_src" ""))]
312 if (do_movsi (operands))
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, SImode)
319 && !register_operand (operand0, SImode))
321 operands[1] = copy_to_mode_reg (SImode, operand1);
326 (define_expand "movsf"
327 [(set (match_operand:SF 0 "general_operand_dst" "")
328 (match_operand:SF 1 "general_operand_src" ""))]
334 if (do_movsi (operands))
339 /* One of the ops has to be in a register. */
340 if (!register_operand (operand1, SFmode)
341 && !register_operand (operand0, SFmode))
343 operands[1] = copy_to_mode_reg (SFmode, operand1);
348 (define_insn "movsi_h8300"
349 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
350 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
352 && (register_operand (operands[0], SImode)
353 || register_operand (operands[1], SImode))"
357 switch (which_alternative)
360 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
362 if (REGNO (operands[0]) < REGNO (operands[1]))
363 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
365 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
367 /* Make sure we don't trample the register we index with. */
368 if (GET_CODE (operands[1]) == MEM)
370 rtx inside = XEXP (operands[1], 0);
375 else if (GET_CODE (inside) == PLUS)
377 rtx lhs = XEXP (inside, 0);
378 rtx rhs = XEXP (inside, 1);
379 if (REG_P (lhs)) rn = REGNO (lhs);
380 if (REG_P (rhs)) rn = REGNO (rhs);
383 if (rn == REGNO (operands[0]))
385 /* Move the second word first. */
386 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
390 /* See if either half is zero. If so, use sub.w to clear
392 if (GET_CODE (operands[1]) == CONST_INT)
394 if ((INTVAL (operands[1]) & 0xffff) == 0)
395 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
396 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
397 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
399 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
402 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
404 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
406 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
411 [(set_attr "length" "4,4,8,8,4,4")
412 (set_attr "cc" "clobber")])
414 (define_insn "movsf_h8300"
415 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
416 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
418 && (register_operand (operands[0], SFmode)
419 || register_operand (operands[1], SFmode))"
422 /* Copy of the movsi stuff. */
424 switch (which_alternative)
427 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
429 if (REGNO (operands[0]) < REGNO (operands[1]))
430 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
432 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
434 /* Make sure we don't trample the register we index with. */
435 if (GET_CODE (operands[1]) == MEM)
437 rtx inside = XEXP (operands[1], 0);
442 else if (GET_CODE (inside) == PLUS)
444 rtx lhs = XEXP (inside, 0);
445 rtx rhs = XEXP (inside, 1);
446 if (REG_P (lhs)) rn = REGNO (lhs);
447 if (REG_P (rhs)) rn = REGNO (rhs);
450 if (rn == REGNO (operands[0]))
451 /* Move the second word first. */
452 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
454 /* Move the first word first. */
455 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
458 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
460 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
462 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
467 [(set_attr "length" "4,4,8,8,4,4")
468 (set_attr "cc" "clobber")])
470 (define_insn "movsi_h8300hs"
471 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
472 (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
473 "(TARGET_H8300S || TARGET_H8300H)
474 && (register_operand (operands[0], SImode)
475 || register_operand (operands[1], SImode))
476 && !(GET_CODE (operands[0]) == MEM
477 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
478 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
479 && GET_CODE (operands[1]) == REG
480 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
483 switch (which_alternative)
486 return \"sub.l %S0,%S0\";
490 return \"clrmac\;ldmac %1,macl\";
492 return \"stmac macl,%0\";
494 if (GET_CODE (operands[1]) == CONST_INT)
496 int val = INTVAL (operands[1]);
498 /* Look for constants which can be made by adding an 8-bit
499 number to zero in one of the two low bytes. */
500 if (val == (val & 0xff))
502 operands[1] = GEN_INT ((char) val & 0xff);
503 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
506 if (val == (val & 0xff00))
508 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
509 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
512 /* Look for constants that can be obtained by subs, inc, and
514 switch (val & 0xffffffff)
517 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
519 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
521 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
524 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
526 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
529 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
531 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
534 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
536 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
540 return \"mov.l %S1,%S0\";
542 [(set_attr "length" "2,2,6,10,10,4,4,2,6,4")
543 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
545 (define_insn "movsf_h8300h"
546 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
547 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
548 "(TARGET_H8300H || TARGET_H8300S)
549 && (register_operand (operands[0], SFmode)
550 || register_operand (operands[1], SFmode))"
558 [(set_attr "length" "2,2,10,10,4,4")
559 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
561 ;; ----------------------------------------------------------------------
563 ;; ----------------------------------------------------------------------
566 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
568 (match_operand 1 "const_int_operand" "n,n")))]
571 [(set_attr "length" "2,4")
572 (set_attr "cc" "set_zn,set_zn")])
575 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
577 (match_operand 1 "const_int_operand" "n")))]
580 [(set_attr "length" "2")
581 (set_attr "cc" "set_zn")])
584 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
586 (match_operand 1 "const_int_operand" "n,n")))]
587 "TARGET_H8300H || TARGET_H8300S"
589 [(set_attr "length" "2,8")
590 (set_attr "cc" "set_zn,set_zn")])
593 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
595 (match_operand 1 "const_int_operand" "n")))]
596 "(TARGET_H8300H || TARGET_H8300S)
597 && INTVAL (operands[1]) <= 15"
599 [(set_attr "length" "2")
600 (set_attr "cc" "set_zn")])
604 (and:HI (match_operand:HI 0 "register_operand" "r")
605 (match_operand:HI 1 "single_one_operand" "n")))]
609 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
610 if (INTVAL (operands[1]) > 128)
612 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
613 return \"btst\\t%V1,%t0\";
615 return \"btst\\t%V1,%s0\";
617 [(set_attr "length" "2")
618 (set_attr "cc" "set_zn")])
622 (and:SI (match_operand:SI 0 "register_operand" "r")
623 (match_operand:SI 1 "single_one_operand" "n")))]
624 "(TARGET_H8300H || TARGET_H8300S)
625 && (INTVAL (operands[1]) & 0xffff) != 0"
628 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
629 if (INTVAL (operands[1]) > 128)
631 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
632 return \"btst\\t%V1,%x0\";
634 return \"btst\\t%V1,%w0\";
636 [(set_attr "length" "2")
637 (set_attr "cc" "set_zn")])
640 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
643 [(set_attr "length" "2")
644 (set_attr "cc" "set_znv")])
647 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
650 [(set_attr "length" "2")
651 (set_attr "cc" "set_znv")])
655 (and:HI (match_operand:HI 0 "register_operand" "r")
659 [(set_attr "length" "2")
660 (set_attr "cc" "set_znv")])
663 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
664 "TARGET_H8300H || TARGET_H8300S"
666 [(set_attr "length" "2")
667 (set_attr "cc" "set_znv")])
671 (and:SI (match_operand:SI 0 "register_operand" "r")
672 (const_int -65536)))]
675 [(set_attr "length" "2")
676 (set_attr "cc" "set_znv")])
680 (compare:QI (match_operand:QI 0 "register_operand" "r")
681 (match_operand:QI 1 "nonmemory_operand" "rn")))]
684 [(set_attr "length" "2")
685 (set_attr "cc" "compare")])
687 (define_expand "cmphi"
689 (compare:HI (match_operand:HI 0 "register_operand" "")
690 (match_operand:HI 1 "nonmemory_operand" "")))]
694 /* Force operand1 into a register if we're compiling
696 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
697 operands[1] = force_reg (HImode, operands[1]);
702 (compare:HI (match_operand:HI 0 "register_operand" "r")
703 (match_operand:HI 1 "register_operand" "r")))]
706 [(set_attr "length" "2")
707 (set_attr "cc" "compare")])
711 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
712 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
713 "TARGET_H8300H || TARGET_H8300S"
715 [(set_attr "length" "2,4")
716 (set_attr "cc" "compare,compare")])
720 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
721 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
722 "TARGET_H8300H || TARGET_H8300S"
724 [(set_attr "length" "2,6")
725 (set_attr "cc" "compare,compare")])
727 ;; ----------------------------------------------------------------------
729 ;; ----------------------------------------------------------------------
731 (define_insn "addqi3"
732 [(set (match_operand:QI 0 "register_operand" "=r")
733 (plus:QI (match_operand:QI 1 "register_operand" "%0")
734 (match_operand:QI 2 "nonmemory_operand" "rn")))]
737 [(set_attr "length" "2")
738 (set_attr "cc" "set_zn")])
740 (define_expand "addhi3"
741 [(set (match_operand:HI 0 "register_operand" "")
742 (plus:HI (match_operand:HI 1 "register_operand" "")
743 (match_operand:HI 2 "nonmemory_operand" "")))]
748 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
749 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
750 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
755 add.b %s2,%s0\;addx %t2,%t0
757 mov.w %T1,%T0\;add.w %T2,%T0"
758 [(set_attr "length" "2,2,4,2,6")
759 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
762 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
763 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
764 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
765 "TARGET_H8300H || TARGET_H8300S"
771 [(set_attr "length" "2,2,4,2")
772 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
775 [(set (match_operand:HI 0 "register_operand" "")
776 (plus:HI (match_dup 0)
777 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
780 "split_adds_subs (HImode, operands); DONE;")
782 (define_expand "addsi3"
783 [(set (match_operand:SI 0 "register_operand" "")
784 (plus:SI (match_operand:SI 1 "register_operand" "")
785 (match_operand:SI 2 "nonmemory_operand" "")))]
789 (define_insn "addsi_h8300"
790 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
791 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
792 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
795 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
796 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
797 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
798 [(set_attr "length" "8,6,10")
799 (set_attr "cc" "clobber")])
801 (define_insn "addsi_h8300h"
802 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
803 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
804 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
805 "TARGET_H8300H || TARGET_H8300S"
811 [(set_attr "length" "2,2,6,2")
812 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
815 [(set (match_operand:SI 0 "register_operand" "")
816 (plus:SI (match_dup 0)
817 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
818 "TARGET_H8300H || TARGET_H8300S"
820 "split_adds_subs (SImode, operands); DONE;")
822 ;; ----------------------------------------------------------------------
823 ;; SUBTRACT INSTRUCTIONS
824 ;; ----------------------------------------------------------------------
826 (define_insn "subqi3"
827 [(set (match_operand:QI 0 "register_operand" "=r")
828 (minus:QI (match_operand:QI 1 "register_operand" "0")
829 (match_operand:QI 2 "register_operand" "r")))]
832 [(set_attr "length" "2")
833 (set_attr "cc" "set_zn")])
835 (define_expand "subhi3"
836 [(set (match_operand:HI 0 "register_operand" "")
837 (minus:HI (match_operand:HI 1 "general_operand" "")
838 (match_operand:HI 2 "nonmemory_operand" "")))]
843 [(set (match_operand:HI 0 "register_operand" "=r,&r")
844 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
845 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
849 add.b %E2,%s0\;addx %F2,%t0"
850 [(set_attr "length" "2,4")
851 (set_attr "cc" "set_zn,clobber")])
854 [(set (match_operand:HI 0 "register_operand" "=r,&r")
855 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
856 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
857 "TARGET_H8300H || TARGET_H8300S"
861 [(set_attr "length" "2,4")
862 (set_attr "cc" "set_zn,set_zn")])
864 (define_expand "subsi3"
865 [(set (match_operand:SI 0 "register_operand" "")
866 (minus:SI (match_operand:SI 1 "register_operand" "")
867 (match_operand:SI 2 "nonmemory_operand" "")))]
871 (define_insn "subsi3_h8300"
872 [(set (match_operand:SI 0 "register_operand" "=r")
873 (minus:SI (match_operand:SI 1 "register_operand" "0")
874 (match_operand:SI 2 "register_operand" "r")))]
876 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
877 [(set_attr "length" "6")
878 (set_attr "cc" "clobber")])
880 (define_insn "subsi3_h8300h"
881 [(set (match_operand:SI 0 "register_operand" "=r,r")
882 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
883 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
884 "TARGET_H8300H || TARGET_H8300S"
888 [(set_attr "length" "2,6")
889 (set_attr "cc" "set_zn,set_zn")])
891 ;; ----------------------------------------------------------------------
892 ;; MULTIPLY INSTRUCTIONS
893 ;; ----------------------------------------------------------------------
895 ;; Note that the H8/300 can only handle umulqihi3.
897 (define_insn "mulqihi3"
898 [(set (match_operand:HI 0 "register_operand" "=r")
899 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
900 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
901 "TARGET_H8300H || TARGET_H8300S"
903 [(set_attr "length" "4")
904 (set_attr "cc" "set_zn")])
906 (define_insn "mulhisi3"
907 [(set (match_operand:SI 0 "register_operand" "=r")
908 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
909 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
910 "TARGET_H8300H || TARGET_H8300S"
912 [(set_attr "length" "4")
913 (set_attr "cc" "set_zn")])
915 (define_insn "umulqihi3"
916 [(set (match_operand:HI 0 "register_operand" "=r")
917 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
918 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
921 [(set_attr "length" "2")
922 (set_attr "cc" "none_0hit")])
924 (define_insn "umulhisi3"
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
927 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
928 "TARGET_H8300H || TARGET_H8300S"
930 [(set_attr "length" "2")
931 (set_attr "cc" "none_0hit")])
933 ;; This is a "bridge" instruction. Combine can't cram enough insns
934 ;; together to crate a MAC instruction directly, but it can create
935 ;; this instruction, which then allows combine to create the real
938 ;; Unfortunately, if combine doesn't create a MAC instruction, this
939 ;; insn must generate reasonably correct code. Egad.
941 [(set (match_operand:SI 0 "register_operand" "=a")
944 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
946 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
948 "clrmac\;mac @%2+,@%1+"
949 [(set_attr "length" "6")
950 (set_attr "cc" "none_0hit")])
953 [(set (match_operand:SI 0 "register_operand" "=a")
955 (sign_extend:SI (mem:HI
956 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
957 (sign_extend:SI (mem:HI
958 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
959 (match_operand:SI 3 "register_operand" "0")))]
962 [(set_attr "length" "4")
963 (set_attr "cc" "none_0hit")])
965 ;; ----------------------------------------------------------------------
966 ;; DIVIDE/MOD INSTRUCTIONS
967 ;; ----------------------------------------------------------------------
969 (define_insn "udivmodqi4"
970 [(set (match_operand:QI 0 "register_operand" "=r")
973 (match_operand:HI 1 "register_operand" "0")
974 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
975 (set (match_operand:QI 3 "register_operand" "=r")
979 (zero_extend:HI (match_dup 2)))))]
983 if (find_reg_note (insn, REG_UNUSED, operands[3]))
984 return \"divxu.b\\t%X2,%T0\";
986 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
988 [(set_attr "length" "4")
989 (set_attr "cc" "clobber")])
991 (define_insn "divmodqi4"
992 [(set (match_operand:QI 0 "register_operand" "=r")
995 (match_operand:HI 1 "register_operand" "0")
996 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
997 (set (match_operand:QI 3 "register_operand" "=r")
1001 (sign_extend:HI (match_dup 2)))))]
1002 "TARGET_H8300H || TARGET_H8300S"
1005 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1006 return \"divxs.b\\t%X2,%T0\";
1008 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1010 [(set_attr "length" "6")
1011 (set_attr "cc" "clobber")])
1013 (define_insn "udivmodhi4"
1014 [(set (match_operand:HI 0 "register_operand" "=r")
1017 (match_operand:SI 1 "register_operand" "0")
1018 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1019 (set (match_operand:HI 3 "register_operand" "=r")
1023 (zero_extend:SI (match_dup 2)))))]
1024 "TARGET_H8300H || TARGET_H8300S"
1027 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1028 return \"divxu.w\\t%T2,%S0\";
1030 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1032 [(set_attr "length" "4")
1033 (set_attr "cc" "clobber")])
1035 (define_insn "divmodhi4"
1036 [(set (match_operand:HI 0 "register_operand" "=r")
1039 (match_operand:SI 1 "register_operand" "0")
1040 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1041 (set (match_operand:HI 3 "register_operand" "=r")
1045 (sign_extend:SI (match_dup 2)))))]
1046 "TARGET_H8300H || TARGET_H8300S"
1049 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1050 return \"divxs.w\\t%T2,%S0\";
1052 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1054 [(set_attr "length" "6")
1055 (set_attr "cc" "clobber")])
1057 ;; ----------------------------------------------------------------------
1059 ;; ----------------------------------------------------------------------
1062 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1063 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1064 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1065 "register_operand (operands[0], QImode)
1066 || single_zero_operand (operands[2], QImode)"
1070 [(set_attr "length" "2,8")
1071 (set_attr "adjust_length" "no")
1072 (set_attr "cc" "set_znv,none_0hit")])
1074 (define_expand "andqi3"
1075 [(set (match_operand:QI 0 "bit_operand" "")
1076 (and:QI (match_operand:QI 1 "bit_operand" "")
1077 (match_operand:QI 2 "nonmemory_operand" "")))]
1081 if (fix_bit_operand (operands, 0, AND))
1085 (define_expand "andhi3"
1086 [(set (match_operand:HI 0 "register_operand" "")
1087 (and:HI (match_operand:HI 1 "register_operand" "")
1088 (match_operand:HI 2 "nonmemory_operand" "")))]
1092 (define_insn "*andorqi3"
1093 [(set (match_operand:QI 0 "register_operand" "=r")
1094 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1095 (match_operand:QI 3 "single_one_operand" "n"))
1096 (match_operand:QI 1 "register_operand" "0")))]
1098 "bld\\t%V3,%X2\;bst\\t%V3,%X0"
1099 [(set_attr "length" "4")
1100 (set_attr "cc" "clobber")])
1102 (define_insn "*andorhi3"
1103 [(set (match_operand:HI 0 "register_operand" "=r")
1104 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1105 (match_operand:HI 3 "single_one_operand" "n"))
1106 (match_operand:HI 1 "register_operand" "0")))]
1110 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1111 if (INTVAL (operands[3]) > 128)
1113 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1114 return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
1116 return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
1118 [(set_attr "length" "4")
1119 (set_attr "cc" "clobber")])
1121 (define_insn "*andorsi3"
1122 [(set (match_operand:SI 0 "register_operand" "=r")
1123 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1124 (match_operand:SI 3 "single_one_operand" "n"))
1125 (match_operand:SI 1 "register_operand" "0")))]
1126 "(INTVAL (operands[3]) & 0xffff) != 0"
1129 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1130 if (INTVAL (operands[3]) > 128)
1132 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1133 return \"bld\\t%V3,%x2\;bst\\t%V3,%x0\";
1135 return \"bld\\t%V3,%w2\;bst\\t%V3,%w0\";
1137 [(set_attr "length" "4")
1138 (set_attr "cc" "clobber")])
1140 (define_expand "andsi3"
1141 [(set (match_operand:SI 0 "register_operand" "")
1142 (and:SI (match_operand:SI 1 "register_operand" "")
1143 (match_operand:SI 2 "nonmemory_operand" "")))]
1147 ;; ----------------------------------------------------------------------
1149 ;; ----------------------------------------------------------------------
1152 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1153 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1154 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1155 "register_operand (operands[0], QImode)
1156 || single_one_operand (operands[2], QImode)"
1160 [(set_attr "length" "2,8")
1161 (set_attr "adjust_length" "no")
1162 (set_attr "cc" "set_znv,none_0hit")])
1164 (define_expand "iorqi3"
1165 [(set (match_operand:QI 0 "bit_operand" "")
1166 (ior:QI (match_operand:QI 1 "bit_operand" "")
1167 (match_operand:QI 2 "nonmemory_operand" "")))]
1171 if (fix_bit_operand (operands, 1, IOR))
1175 (define_expand "iorhi3"
1176 [(set (match_operand:HI 0 "register_operand" "")
1177 (ior:HI (match_operand:HI 1 "register_operand" "")
1178 (match_operand:HI 2 "nonmemory_operand" "")))]
1182 (define_expand "iorsi3"
1183 [(set (match_operand:SI 0 "register_operand" "")
1184 (ior:SI (match_operand:SI 1 "register_operand" "")
1185 (match_operand:SI 2 "nonmemory_operand" "")))]
1189 ;; ----------------------------------------------------------------------
1191 ;; ----------------------------------------------------------------------
1194 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1195 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1196 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1197 "register_operand (operands[0], QImode)
1198 || single_one_operand (operands[2], QImode)"
1202 [(set_attr "length" "2,8")
1203 (set_attr "adjust_length" "no")
1204 (set_attr "cc" "set_znv,none_0hit")])
1206 (define_expand "xorqi3"
1207 [(set (match_operand:QI 0 "bit_operand" "")
1208 (xor:QI (match_operand:QI 1 "bit_operand" "")
1209 (match_operand:QI 2 "nonmemory_operand" "")))]
1213 if (fix_bit_operand (operands, 1, XOR))
1217 (define_expand "xorhi3"
1218 [(set (match_operand:HI 0 "register_operand" "")
1219 (xor:HI (match_operand:HI 1 "register_operand" "")
1220 (match_operand:HI 2 "nonmemory_operand" "")))]
1224 (define_expand "xorsi3"
1225 [(set (match_operand:SI 0 "register_operand" "")
1226 (xor:SI (match_operand:SI 1 "register_operand" "")
1227 (match_operand:SI 2 "nonmemory_operand" "")))]
1231 ;; ----------------------------------------------------------------------
1232 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1233 ;; ----------------------------------------------------------------------
1236 [(set (match_operand:HI 0 "register_operand" "=r")
1237 (match_operator:HI 3 "bit_operator"
1238 [(match_operand:HI 1 "register_operand" "%0")
1239 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1241 "* return output_logical_op (HImode, operands);"
1242 [(set (attr "length")
1243 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1245 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1248 [(set (match_operand:SI 0 "register_operand" "=r")
1249 (match_operator:SI 3 "bit_operator"
1250 [(match_operand:SI 1 "register_operand" "%0")
1251 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1253 "* return output_logical_op (SImode, operands);"
1254 [(set (attr "length")
1255 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1257 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1259 ;; ----------------------------------------------------------------------
1260 ;; NEGATION INSTRUCTIONS
1261 ;; ----------------------------------------------------------------------
1263 (define_insn "negqi2"
1264 [(set (match_operand:QI 0 "register_operand" "=r")
1265 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1268 [(set_attr "length" "2")
1269 (set_attr "cc" "set_zn")])
1271 (define_expand "neghi2"
1272 [(set (match_operand:HI 0 "register_operand" "")
1273 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1279 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1284 (define_expand "neghi2_h8300"
1286 (not:HI (match_operand:HI 1 "register_operand" "")))
1287 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1288 (set (match_operand:HI 0 "register_operand" "")
1291 "operands[2] = gen_reg_rtx (HImode);")
1293 (define_insn "neghi2_h8300h"
1294 [(set (match_operand:HI 0 "register_operand" "=r")
1295 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1296 "TARGET_H8300H || TARGET_H8300S"
1298 [(set_attr "length" "2")
1299 (set_attr "cc" "set_zn")])
1301 (define_expand "negsi2"
1302 [(set (match_operand:SI 0 "register_operand" "")
1303 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1309 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1314 (define_expand "negsi2_h8300"
1316 (not:SI (match_operand:SI 1 "register_operand" "")))
1317 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1318 (set (match_operand:SI 0 "register_operand" "")
1321 "operands[2] = gen_reg_rtx (SImode);")
1323 (define_insn "negsi2_h8300h"
1324 [(set (match_operand:SI 0 "register_operand" "=r")
1325 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1326 "TARGET_H8300H || TARGET_H8300S"
1328 [(set_attr "length" "2")
1329 (set_attr "cc" "set_zn")])
1331 ;; ----------------------------------------------------------------------
1333 ;; ----------------------------------------------------------------------
1335 (define_insn "one_cmplqi2"
1336 [(set (match_operand:QI 0 "register_operand" "=r")
1337 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1340 [(set_attr "length" "2")
1341 (set_attr "cc" "set_znv")])
1343 (define_expand "one_cmplhi2"
1344 [(set (match_operand:HI 0 "register_operand" "=r")
1345 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1350 [(set (match_operand:HI 0 "register_operand" "=r")
1351 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1354 [(set_attr "cc" "clobber")
1355 (set_attr "length" "4")])
1358 [(set (match_operand:HI 0 "register_operand" "=r")
1359 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1360 "TARGET_H8300H || TARGET_H8300S"
1362 [(set_attr "cc" "set_znv")
1363 (set_attr "length" "2")])
1365 (define_expand "one_cmplsi2"
1366 [(set (match_operand:SI 0 "register_operand" "=r")
1367 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1372 [(set (match_operand:SI 0 "register_operand" "=r")
1373 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1375 "not %w0\;not %x0\;not %y0\;not %z0"
1376 [(set_attr "cc" "clobber")
1377 (set_attr "length" "8")])
1380 [(set (match_operand:SI 0 "register_operand" "=r")
1381 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1382 "TARGET_H8300H || TARGET_H8300S"
1384 [(set_attr "cc" "set_znv")
1385 (set_attr "length" "2")])
1387 ;; ----------------------------------------------------------------------
1388 ;; JUMP INSTRUCTIONS
1389 ;; ----------------------------------------------------------------------
1391 ;; Conditional jump instructions
1393 (define_expand "ble"
1395 (if_then_else (le (cc0)
1397 (label_ref (match_operand 0 "" ""))
1402 (define_expand "bleu"
1404 (if_then_else (leu (cc0)
1406 (label_ref (match_operand 0 "" ""))
1411 (define_expand "bge"
1413 (if_then_else (ge (cc0)
1415 (label_ref (match_operand 0 "" ""))
1420 (define_expand "bgeu"
1422 (if_then_else (geu (cc0)
1424 (label_ref (match_operand 0 "" ""))
1429 (define_expand "blt"
1431 (if_then_else (lt (cc0)
1433 (label_ref (match_operand 0 "" ""))
1438 (define_expand "bltu"
1440 (if_then_else (ltu (cc0)
1442 (label_ref (match_operand 0 "" ""))
1447 (define_expand "bgt"
1449 (if_then_else (gt (cc0)
1451 (label_ref (match_operand 0 "" ""))
1456 (define_expand "bgtu"
1458 (if_then_else (gtu (cc0)
1460 (label_ref (match_operand 0 "" ""))
1465 (define_expand "beq"
1467 (if_then_else (eq (cc0)
1469 (label_ref (match_operand 0 "" ""))
1474 (define_expand "bne"
1476 (if_then_else (ne (cc0)
1478 (label_ref (match_operand 0 "" ""))
1483 (define_insn "branch_true"
1485 (if_then_else (match_operator 1 "comparison_operator"
1486 [(cc0) (const_int 0)])
1487 (label_ref (match_operand 0 "" ""))
1492 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1493 && (GET_CODE (operands[1]) == GT
1494 || GET_CODE (operands[1]) == GE
1495 || GET_CODE (operands[1]) == LE
1496 || GET_CODE (operands[1]) == LT))
1498 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1502 if (get_attr_length (insn) == 2)
1503 return \"b%j1 %l0\";
1504 else if (get_attr_length (insn) == 4)
1505 return \"b%j1 %l0:16\";
1507 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1509 [(set_attr "type" "branch")
1510 (set_attr "cc" "none")])
1512 (define_insn "branch_false"
1514 (if_then_else (match_operator 1 "comparison_operator"
1515 [(cc0) (const_int 0)])
1517 (label_ref (match_operand 0 "" ""))))]
1521 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1522 && (GET_CODE (operands[1]) == GT
1523 || GET_CODE (operands[1]) == GE
1524 || GET_CODE (operands[1]) == LE
1525 || GET_CODE (operands[1]) == LT))
1527 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1531 if (get_attr_length (insn) == 2)
1532 return \"b%k1 %l0\";
1533 else if (get_attr_length (insn) == 4)
1534 return \"b%k1 %l0:16\";
1536 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1538 [(set_attr "type" "branch")
1539 (set_attr "cc" "none")])
1541 ;; Unconditional and other jump instructions.
1545 (label_ref (match_operand 0 "" "")))]
1549 if (get_attr_length (insn) == 2)
1551 else if (get_attr_length (insn) == 4)
1552 return \"bra %l0:16\";
1554 return \"jmp @%l0\";
1556 [(set_attr "type" "branch")
1557 (set_attr "cc" "none")])
1559 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1561 (define_expand "tablejump"
1562 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1563 (use (label_ref (match_operand 1 "" "")))])]
1567 (define_insn "tablejump_h8300"
1568 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1569 (use (label_ref (match_operand 1 "" "")))]
1572 [(set_attr "cc" "none")
1573 (set_attr "length" "2")])
1575 (define_insn "tablejump_h8300h"
1576 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1577 (use (label_ref (match_operand 1 "" "")))]
1578 "TARGET_H8300H || TARGET_H8300S"
1580 [(set_attr "cc" "none")
1581 (set_attr "length" "2")])
1583 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1585 (define_expand "indirect_jump"
1586 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1590 (define_insn "indirect_jump_h8300"
1591 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1594 [(set_attr "cc" "none")
1595 (set_attr "length" "2")])
1597 (define_insn "indirect_jump_h8300h"
1598 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1599 "TARGET_H8300H || TARGET_H8300S"
1601 [(set_attr "cc" "none")
1602 (set_attr "length" "2")])
1604 ;; Call subroutine with no return value.
1606 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1609 [(call (match_operand:QI 0 "call_insn_operand" "or")
1610 (match_operand:HI 1 "general_operand" "g"))]
1614 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1615 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1616 return \"jsr\\t@%0:8\";
1618 return \"jsr\\t%0\";
1620 [(set_attr "cc" "clobber")
1621 (set (attr "length")
1622 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1626 ;; Call subroutine, returning value in operand 0
1627 ;; (which must be a hard register).
1629 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1631 (define_insn "call_value"
1632 [(set (match_operand 0 "" "=r")
1633 (call (match_operand:QI 1 "call_insn_operand" "or")
1634 (match_operand:HI 2 "general_operand" "g")))]
1638 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1639 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1640 return \"jsr\\t@%1:8\";
1642 return \"jsr\\t%1\";
1644 [(set_attr "cc" "clobber")
1645 (set (attr "length")
1646 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1654 [(set_attr "cc" "none")
1655 (set_attr "length" "2")])
1657 ;; ----------------------------------------------------------------------
1658 ;; EXTEND INSTRUCTIONS
1659 ;; ----------------------------------------------------------------------
1661 (define_expand "zero_extendqihi2"
1662 [(set (match_operand:HI 0 "register_operand" "")
1663 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1668 [(set (match_operand:HI 0 "register_operand" "=r,r")
1669 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1673 mov.b %R1,%s0\;mov.b #0,%t0"
1674 [(set_attr "length" "2,10")
1675 (set_attr "cc" "clobber,clobber")])
1678 [(set (match_operand:HI 0 "register_operand" "=r,r")
1679 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1680 "TARGET_H8300H || TARGET_H8300S"
1683 mov.b %R1,%s0\;extu.w %T0"
1684 [(set_attr "length" "2,10")
1685 (set_attr "cc" "set_znv,set_znv")])
1687 ;; The compiler can synthesize a H8/300H variant of this which is
1688 ;; just as efficient as one that we'd create
1689 (define_insn "zero_extendqisi2"
1690 [(set (match_operand:SI 0 "register_operand" "=r,r")
1691 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1694 mov.b #0,%x0\;sub.w %e0,%e0
1695 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1696 [(set_attr "length" "4,6")
1697 (set_attr "cc" "clobber,clobber")])
1699 (define_expand "zero_extendhisi2"
1700 [(set (match_operand:SI 0 "register_operand" "")
1701 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1705 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1707 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1708 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1712 mov.w %f1,%f0\;sub.w %e0,%e0
1713 mov.w %e1,%f0\;sub.w %e0,%e0"
1714 [(set_attr "length" "2,4,4")
1715 (set_attr "cc" "clobber,clobber,clobber")])
1718 [(set (match_operand:SI 0 "register_operand" "=r")
1719 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1720 "TARGET_H8300H || TARGET_H8300S"
1722 [(set_attr "length" "2")
1723 (set_attr "cc" "set_znv")])
1725 (define_expand "extendqihi2"
1726 [(set (match_operand:HI 0 "register_operand" "")
1727 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1732 [(set (match_operand:HI 0 "register_operand" "=r,r")
1733 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1736 bld #7,%s0\;subx %t0,%t0
1737 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1738 [(set_attr "length" "4,8")
1739 (set_attr "cc" "clobber,clobber")])
1742 [(set (match_operand:HI 0 "register_operand" "=r")
1743 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1744 "TARGET_H8300H || TARGET_H8300S"
1746 [(set_attr "length" "2")
1747 (set_attr "cc" "set_znv")])
1749 ;; The compiler can synthesize a H8/300H variant of this which is
1750 ;; just as efficient as one that we'd create
1751 (define_insn "extendqisi2"
1752 [(set (match_operand:SI 0 "register_operand" "=r,r")
1753 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1756 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1757 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1758 [(set_attr "length" "8,10")
1759 (set_attr "cc" "clobber,clobber")])
1761 (define_expand "extendhisi2"
1762 [(set (match_operand:SI 0 "register_operand" "")
1763 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1768 [(set (match_operand:SI 0 "register_operand" "=r,r")
1769 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1772 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1773 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1774 [(set_attr "length" "6,8")
1775 (set_attr "cc" "clobber,clobber")])
1778 [(set (match_operand:SI 0 "register_operand" "=r")
1779 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1780 "TARGET_H8300H || TARGET_H8300S"
1782 [(set_attr "length" "2")
1783 (set_attr "cc" "set_znv")])
1785 ;; ----------------------------------------------------------------------
1787 ;; ----------------------------------------------------------------------
1789 ;; We make some attempt to provide real efficient shifting. One example is
1790 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1791 ;; reg and moving 0 into the former reg.
1793 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1794 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1795 ;; give the optimizer more cracks at the code. However, we wish to do things
1796 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1797 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1798 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1799 ;; to detect cases it can optimize.
1801 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1802 ;; easier "do it at insn emit time" route.
1806 (define_expand "ashlqi3"
1807 [(set (match_operand:QI 0 "register_operand" "")
1808 (ashift:QI (match_operand:QI 1 "register_operand" "")
1809 (match_operand:QI 2 "nonmemory_operand" "")))]
1811 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
1813 (define_expand "ashrqi3"
1814 [(set (match_operand:QI 0 "register_operand" "")
1815 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1816 (match_operand:QI 2 "nonmemory_operand" "")))]
1818 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
1820 (define_expand "lshrqi3"
1821 [(set (match_operand:QI 0 "register_operand" "")
1822 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1823 (match_operand:QI 2 "nonmemory_operand" "")))]
1825 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
1828 [(set (match_operand:QI 0 "register_operand" "=r,r")
1829 (match_operator:QI 3 "nshift_operator"
1830 [ (match_operand:QI 1 "register_operand" "0,0")
1831 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
1832 (clobber (match_scratch:QI 4 "=X,&r"))]
1834 "* return output_a_shift (operands);"
1835 [(set (attr "length")
1836 (symbol_ref "compute_a_shift_length (insn, operands)"))
1837 (set_attr "cc" "clobber")])
1841 (define_expand "ashlhi3"
1842 [(set (match_operand:HI 0 "register_operand" "")
1843 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1844 (match_operand:QI 2 "nonmemory_operand" "")))]
1846 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
1848 (define_expand "lshrhi3"
1849 [(set (match_operand:HI 0 "register_operand" "")
1850 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1851 (match_operand:QI 2 "nonmemory_operand" "")))]
1853 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
1855 (define_expand "ashrhi3"
1856 [(set (match_operand:HI 0 "register_operand" "")
1857 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1858 (match_operand:QI 2 "nonmemory_operand" "")))]
1860 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
1863 [(set (match_operand:HI 0 "register_operand" "=r,r")
1864 (match_operator:HI 3 "nshift_operator"
1865 [ (match_operand:HI 1 "register_operand" "0,0")
1866 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
1867 (clobber (match_scratch:QI 4 "=X,&r"))]
1869 "* return output_a_shift (operands);"
1870 [(set (attr "length")
1871 (symbol_ref "compute_a_shift_length (insn, operands)"))
1872 (set_attr "cc" "clobber")])
1876 (define_expand "ashlsi3"
1877 [(set (match_operand:SI 0 "register_operand" "")
1878 (ashift:SI (match_operand:SI 1 "general_operand" "")
1879 (match_operand:QI 2 "nonmemory_operand" "")))]
1881 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
1883 (define_expand "lshrsi3"
1884 [(set (match_operand:SI 0 "register_operand" "")
1885 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
1886 (match_operand:QI 2 "nonmemory_operand" "")))]
1888 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
1890 (define_expand "ashrsi3"
1891 [(set (match_operand:SI 0 "register_operand" "")
1892 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
1893 (match_operand:QI 2 "nonmemory_operand" "")))]
1895 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
1898 [(set (match_operand:SI 0 "register_operand" "=r,r")
1899 (match_operator:SI 3 "nshift_operator"
1900 [ (match_operand:SI 1 "register_operand" "0,0")
1901 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
1902 (clobber (match_scratch:QI 4 "=X,&r"))]
1904 "* return output_a_shift (operands);"
1905 [(set (attr "length")
1906 (symbol_ref "compute_a_shift_length (insn, operands)"))
1907 (set_attr "cc" "clobber")])
1909 ;; ----------------------------------------------------------------------
1911 ;; ----------------------------------------------------------------------
1913 (define_expand "rotlqi3"
1914 [(set (match_operand:QI 0 "register_operand" "")
1915 (rotate:QI (match_operand:QI 1 "register_operand" "")
1916 (match_operand:QI 2 "nonmemory_operand" "")))]
1918 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1920 (define_insn "*rotlqi3_1"
1921 [(set (match_operand:QI 0 "register_operand" "=r")
1922 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1923 (match_operand:QI 2 "immediate_operand" "")))]
1925 "* return emit_a_rotate (ROTATE, operands);"
1926 [(set_attr "length" "20")
1927 (set_attr "cc" "clobber")])
1929 (define_expand "rotlhi3"
1930 [(set (match_operand:HI 0 "register_operand" "")
1931 (rotate:HI (match_operand:HI 1 "register_operand" "")
1932 (match_operand:QI 2 "nonmemory_operand" "")))]
1934 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1936 (define_insn "*rotlhi3_1"
1937 [(set (match_operand:HI 0 "register_operand" "=r")
1938 (rotate:HI (match_operand:HI 1 "register_operand" "0")
1939 (match_operand:QI 2 "immediate_operand" "")))]
1941 "* return emit_a_rotate (ROTATE, operands);"
1942 [(set_attr "length" "20")
1943 (set_attr "cc" "clobber")])
1945 (define_expand "rotlsi3"
1946 [(set (match_operand:SI 0 "register_operand" "")
1947 (rotate:SI (match_operand:SI 1 "register_operand" "")
1948 (match_operand:QI 2 "nonmemory_operand" "")))]
1949 "TARGET_H8300H || TARGET_H8300S"
1950 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1952 (define_insn "*rotlsi3_1"
1953 [(set (match_operand:SI 0 "register_operand" "=r")
1954 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1955 (match_operand:QI 2 "immediate_operand" "")))]
1956 "TARGET_H8300H || TARGET_H8300S"
1957 "* return emit_a_rotate (ROTATE, operands);"
1958 [(set_attr "length" "20")
1959 (set_attr "cc" "clobber")])
1961 ;; -----------------------------------------------------------------
1963 ;; -----------------------------------------------------------------
1964 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1965 ;; instructions so let's use them as well as we can.
1967 ;; You'll never believe all these patterns perform one basic action --
1968 ;; load a bit from the source, optionally invert the bit, then store it
1969 ;; in the destination (which is known to be zero).
1971 ;; Combine obviously need some work to better identify this situation and
1972 ;; canonicalize the form better.
1975 ;; Normal loads with a 16bit destination.
1979 [(set (match_operand:HI 0 "register_operand" "=&r")
1980 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1982 (match_operand:HI 2 "immediate_operand" "n")))]
1984 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1985 [(set_attr "cc" "clobber")
1986 (set_attr "length" "6")])
1989 ;; Inverted loads with a 16bit destination.
1993 [(set (match_operand:HI 0 "register_operand" "=&r")
1994 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
1995 (match_operand:HI 3 "const_int_operand" "n"))
1997 (match_operand:HI 2 "const_int_operand" "n")))]
1999 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2000 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2001 [(set_attr "cc" "clobber")
2002 (set_attr "length" "8")])
2005 ;; Normal loads with a 32bit destination.
2009 [(set (match_operand:SI 0 "register_operand" "=&r")
2010 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2012 (match_operand 2 "const_int_operand" "n")))]
2014 && INTVAL (operands[2]) < 16"
2015 "* return output_simode_bld (0, operands);"
2016 [(set_attr "cc" "clobber")
2017 (set_attr "length" "6")])
2020 [(set (match_operand:SI 0 "register_operand" "=r")
2021 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2023 (match_operand 2 "const_int_operand" "n")))]
2024 "(TARGET_H8300H || TARGET_H8300S)
2025 && INTVAL (operands[2]) < 16"
2026 "* return output_simode_bld (0, operands);"
2027 [(set_attr "cc" "clobber")
2028 (set_attr "length" "6")])
2031 ;; Inverted loads with a 32bit destination.
2035 [(set (match_operand:SI 0 "register_operand" "=&r")
2036 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2037 (match_operand:HI 3 "const_int_operand" "n"))
2039 (match_operand 2 "const_int_operand" "n")))]
2041 && INTVAL (operands[2]) < 16
2042 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2043 "* return output_simode_bld (1, operands);"
2044 [(set_attr "cc" "clobber")
2045 (set_attr "length" "6")])
2048 [(set (match_operand:SI 0 "register_operand" "=r")
2049 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
2050 (match_operand 3 "const_int_operand" "n"))
2052 (match_operand 2 "const_int_operand" "n")))]
2053 "(TARGET_H8300H || TARGET_H8300S)
2054 && INTVAL (operands[2]) < 16
2055 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2056 "* return output_simode_bld (1, operands);"
2057 [(set_attr "cc" "clobber")
2058 (set_attr "length" "6")])
2060 (define_expand "insv"
2061 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2062 (match_operand:HI 1 "general_operand" "")
2063 (match_operand:HI 2 "general_operand" ""))
2064 (match_operand:HI 3 "general_operand" ""))]
2068 /* We only have single bit bit-field instructions. */
2069 if (INTVAL (operands[1]) != 1)
2072 /* For now, we don't allow memory operands. */
2073 if (GET_CODE (operands[0]) == MEM
2074 || GET_CODE (operands[3]) == MEM)
2079 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2081 (match_operand:HI 1 "immediate_operand" "n"))
2082 (match_operand:HI 2 "register_operand" "r"))]
2084 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2085 [(set_attr "cc" "clobber")
2086 (set_attr "length" "4")])
2088 (define_expand "extzv"
2089 [(set (match_operand:HI 0 "register_operand" "")
2090 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2091 (match_operand:HI 2 "general_operand" "")
2092 (match_operand:HI 3 "general_operand" "")))]
2096 /* We only have single bit bit-field instructions. */
2097 if (INTVAL (operands[2]) != 1)
2100 /* For now, we don't allow memory operands. */
2101 if (GET_CODE (operands[1]) == MEM)
2105 ;; BAND, BOR, and BXOR patterns
2108 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2109 (match_operator:HI 4 "bit_operator"
2110 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2112 (match_operand:HI 2 "immediate_operand" "n"))
2113 (match_operand:HI 3 "bit_operand" "0")]))]
2115 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2116 [(set_attr "cc" "clobber")
2117 (set_attr "length" "6")
2118 (set_attr "adjust_length" "no")])
2121 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2122 (match_operator:HI 5 "bit_operator"
2123 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2125 (match_operand:HI 2 "immediate_operand" "n"))
2126 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2128 (match_operand:HI 4 "immediate_operand" "n"))]))]
2130 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2131 [(set_attr "cc" "clobber")
2132 (set_attr "length" "6")
2133 (set_attr "adjust_length" "no")])
2135 ;; -----------------------------------------------------------------
2137 ;; -----------------------------------------------------------------
2140 [(set (match_operand:HI 0 "register_operand" "=r")
2141 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2142 (match_operand:HI 2 "register_operand" "0")))]
2143 "REG_P (operands[0])
2144 && REG_P (operands[1])
2145 && REGNO (operands[0]) != REGNO (operands[1])"
2147 [(set_attr "cc" "clobber")
2148 (set_attr "length" "2")])
2151 [(set (match_operand:SI 0 "register_operand" "=r")
2152 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2153 (match_operand:SI 2 "register_operand" "0")))]
2154 "(TARGET_H8300H || TARGET_H8300S)
2155 && REG_P (operands[0])
2156 && REG_P (operands[1])
2157 && (REGNO (operands[0]) != REGNO (operands[1]))"
2159 [(set_attr "cc" "clobber")
2160 (set_attr "length" "2")])
2163 [(set (match_operand:SI 0 "register_operand" "=r")
2164 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2165 (match_operand:SI 2 "register_operand" "0")))]
2166 "REG_P (operands[0])
2167 && REG_P (operands[1])
2168 && REGNO (operands[0]) != REGNO (operands[1])"
2170 [(set_attr "cc" "clobber")
2171 (set_attr "length" "2")])
2174 [(set (match_operand:HI 0 "register_operand" "=r")
2175 (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2176 (match_operand:HI 2 "register_operand" "0")))]
2177 "REG_P (operands[0])
2178 && REG_P (operands[1])
2179 && REGNO (operands[0]) != REGNO (operands[1])"
2181 [(set_attr "cc" "clobber")
2182 (set_attr "length" "2")])
2185 [(set (match_operand:SI 0 "register_operand" "=r")
2186 (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2187 (match_operand:SI 2 "register_operand" "0")))]
2188 "(TARGET_H8300H || TARGET_H8300S)
2189 && REG_P (operands[0])
2190 && REG_P (operands[1])
2191 && (REGNO (operands[0]) != REGNO (operands[1]))"
2193 [(set_attr "cc" "clobber")
2194 (set_attr "length" "2")])
2197 [(set (match_operand:SI 0 "register_operand" "=r")
2198 (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2199 (match_operand:SI 2 "register_operand" "0")))]
2200 "REG_P (operands[0])
2201 && REG_P (operands[1])
2202 && REGNO (operands[0]) != REGNO (operands[1])"
2204 [(set_attr "cc" "clobber")
2205 (set_attr "length" "2")])
2208 [(set (match_operand:HI 0 "register_operand" "=r")
2209 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2210 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2212 "REG_P (operands[0])
2213 && REG_P (operands[2])
2214 && REGNO (operands[0]) != REGNO (operands[2])"
2216 [(set_attr "cc" "clobber")
2217 (set_attr "length" "2")])
2220 [(set (match_operand:SI 0 "register_operand" "=r")
2221 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2222 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2224 "(TARGET_H8300H || TARGET_H8300S)
2225 && REG_P (operands[0])
2226 && REG_P (operands[2])
2227 && (REGNO (operands[0]) != REGNO (operands[2]))"
2229 [(set_attr "cc" "clobber")
2230 (set_attr "length" "2")])
2232 ;; Storing a part of HImode to QImode.
2235 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2236 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2240 [(set_attr "cc" "set_znv")
2241 (set_attr "length" "8")])
2243 ;; Storing a part of SImode to QImode.
2246 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2247 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2251 [(set_attr "cc" "set_znv")
2252 (set_attr "length" "8")])
2255 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2256 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2258 (clobber (match_scratch:SI 2 "=&r"))]
2259 "TARGET_H8300H || TARGET_H8300S"
2260 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
2261 [(set_attr "cc" "set_znv")
2262 (set_attr "length" "8")])
2265 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2266 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2268 (clobber (match_scratch:SI 2 "=&r"))]
2269 "TARGET_H8300H || TARGET_H8300S"
2270 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
2271 [(set_attr "cc" "set_znv")
2272 (set_attr "length" "8")])
2274 (define_insn_and_split ""
2276 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2280 (label_ref (match_operand 1 "" ""))
2288 (if_then_else (ge (cc0)
2290 (label_ref (match_dup 1))
2294 (define_insn_and_split ""
2296 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2300 (label_ref (match_operand 1 "" ""))
2308 (if_then_else (lt (cc0)
2310 (label_ref (match_dup 1))