1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2013 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
36 #include "diagnostic-core.h"
42 #include "tm-constrs.h"
44 #include "target-def.h"
51 /* Usable when we have an amount to add or subtract, and want the
52 optimal size of the insn. */
53 #define ADDITIVE_SIZE_MODIFIER(size) \
54 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
56 #define LOSE_AND_RETURN(msgid, x) \
59 cris_operand_lossage (msgid, x); \
63 enum cris_retinsn_type
64 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
66 /* Per-function machine data. */
67 struct GTY(()) machine_function
69 int needs_return_address_on_stack;
71 /* This is the number of registers we save in the prologue due to
75 enum cris_retinsn_type return_type;
78 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
80 static char cris_output_insn_is_bound = 0;
82 /* In code for output macros, this is how we know whether e.g. constant
83 goes in code or in a static initializer. */
84 static int in_code = 0;
86 /* Fix for reg_overlap_mentioned_p. */
87 static int cris_reg_overlap_mentioned_p (rtx, rtx);
89 static enum machine_mode cris_promote_function_mode (const_tree, enum machine_mode,
90 int *, const_tree, int);
92 static void cris_print_base (rtx, FILE *);
94 static void cris_print_index (rtx, FILE *);
96 static void cris_output_addr_const (FILE *, rtx);
98 static struct machine_function * cris_init_machine_status (void);
100 static rtx cris_struct_value_rtx (tree, int);
102 static void cris_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
103 tree type, int *, int);
105 static int cris_initial_frame_pointer_offset (void);
107 static void cris_operand_lossage (const char *, rtx);
109 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
111 static void cris_print_operand (FILE *, rtx, int);
113 static void cris_print_operand_address (FILE *, rtx);
115 static bool cris_print_operand_punct_valid_p (unsigned char code);
117 static bool cris_output_addr_const_extra (FILE *, rtx);
119 static void cris_conditional_register_usage (void);
121 static void cris_asm_output_mi_thunk
122 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
124 static void cris_file_start (void);
125 static void cris_init_libfuncs (void);
127 static reg_class_t cris_preferred_reload_class (rtx, reg_class_t);
129 static int cris_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
130 static int cris_memory_move_cost (enum machine_mode, reg_class_t, bool);
131 static bool cris_rtx_costs (rtx, int, int, int, int *, bool);
132 static int cris_address_cost (rtx, enum machine_mode, addr_space_t, bool);
133 static bool cris_pass_by_reference (cumulative_args_t, enum machine_mode,
135 static int cris_arg_partial_bytes (cumulative_args_t, enum machine_mode,
137 static rtx cris_function_arg (cumulative_args_t, enum machine_mode,
139 static rtx cris_function_incoming_arg (cumulative_args_t,
140 enum machine_mode, const_tree, bool);
141 static void cris_function_arg_advance (cumulative_args_t, enum machine_mode,
143 static tree cris_md_asm_clobbers (tree, tree, tree);
145 static void cris_option_override (void);
147 static bool cris_frame_pointer_required (void);
149 static void cris_asm_trampoline_template (FILE *);
150 static void cris_trampoline_init (rtx, tree, rtx);
152 static rtx cris_function_value(const_tree, const_tree, bool);
153 static rtx cris_libcall_value (enum machine_mode, const_rtx);
154 static bool cris_function_value_regno_p (const unsigned int);
155 static void cris_file_end (void);
157 /* This is the parsed result of the "-max-stack-stackframe=" option. If
158 it (still) is zero, then there was no such option given. */
159 int cris_max_stackframe = 0;
161 /* This is the parsed result of the "-march=" option, if given. */
162 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
166 #undef TARGET_ASM_ALIGNED_SI_OP
167 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
168 #undef TARGET_ASM_ALIGNED_DI_OP
169 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
171 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
172 available in ELF. These "normal" pseudos do not have any alignment
173 constraints or side-effects. */
174 #undef TARGET_ASM_UNALIGNED_HI_OP
175 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
177 #undef TARGET_ASM_UNALIGNED_SI_OP
178 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
180 #undef TARGET_ASM_UNALIGNED_DI_OP
181 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
183 #undef TARGET_PRINT_OPERAND
184 #define TARGET_PRINT_OPERAND cris_print_operand
185 #undef TARGET_PRINT_OPERAND_ADDRESS
186 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
187 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
188 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
189 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
190 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
192 #undef TARGET_CONDITIONAL_REGISTER_USAGE
193 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
195 #undef TARGET_ASM_OUTPUT_MI_THUNK
196 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
197 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
198 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
200 #undef TARGET_ASM_FILE_START
201 #define TARGET_ASM_FILE_START cris_file_start
202 #undef TARGET_ASM_FILE_END
203 #define TARGET_ASM_FILE_END cris_file_end
205 #undef TARGET_INIT_LIBFUNCS
206 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
208 #undef TARGET_LEGITIMATE_ADDRESS_P
209 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
211 #undef TARGET_PREFERRED_RELOAD_CLASS
212 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
214 #undef TARGET_REGISTER_MOVE_COST
215 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
216 #undef TARGET_MEMORY_MOVE_COST
217 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
218 #undef TARGET_RTX_COSTS
219 #define TARGET_RTX_COSTS cris_rtx_costs
220 #undef TARGET_ADDRESS_COST
221 #define TARGET_ADDRESS_COST cris_address_cost
223 #undef TARGET_PROMOTE_FUNCTION_MODE
224 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
226 #undef TARGET_STRUCT_VALUE_RTX
227 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
228 #undef TARGET_SETUP_INCOMING_VARARGS
229 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
230 #undef TARGET_PASS_BY_REFERENCE
231 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
232 #undef TARGET_ARG_PARTIAL_BYTES
233 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
234 #undef TARGET_FUNCTION_ARG
235 #define TARGET_FUNCTION_ARG cris_function_arg
236 #undef TARGET_FUNCTION_INCOMING_ARG
237 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
238 #undef TARGET_FUNCTION_ARG_ADVANCE
239 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
240 #undef TARGET_MD_ASM_CLOBBERS
241 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
242 #undef TARGET_FRAME_POINTER_REQUIRED
243 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
245 #undef TARGET_OPTION_OVERRIDE
246 #define TARGET_OPTION_OVERRIDE cris_option_override
248 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
249 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
250 #undef TARGET_TRAMPOLINE_INIT
251 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
253 #undef TARGET_FUNCTION_VALUE
254 #define TARGET_FUNCTION_VALUE cris_function_value
255 #undef TARGET_LIBCALL_VALUE
256 #define TARGET_LIBCALL_VALUE cris_libcall_value
257 #undef TARGET_FUNCTION_VALUE_REGNO_P
258 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
260 struct gcc_target targetm = TARGET_INITIALIZER;
262 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
265 cris_movem_load_rest_p (rtx op, int offs)
267 unsigned int reg_count = XVECLEN (op, 0) - offs;
273 unsigned int regno = 0;
275 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
276 other than (MEM reg). */
278 || GET_CODE (XVECEXP (op, 0, offs)) != SET
279 || !REG_P (SET_DEST (XVECEXP (op, 0, offs)))
280 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs))))
283 /* Check a possible post-inc indicator. */
284 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
286 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
287 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
293 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
294 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
295 || !CONST_INT_P (inc)
296 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
306 regno = reg_count - 1;
309 elt = XVECEXP (op, 0, offs);
310 src_addr = XEXP (SET_SRC (elt), 0);
312 if (GET_CODE (elt) != SET
313 || !REG_P (SET_DEST (elt))
314 || GET_MODE (SET_DEST (elt)) != SImode
315 || REGNO (SET_DEST (elt)) != regno
316 || !MEM_P (SET_SRC (elt))
317 || GET_MODE (SET_SRC (elt)) != SImode
318 || !memory_address_p (SImode, src_addr))
321 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
323 rtx elt = XVECEXP (op, 0, i);
326 if (GET_CODE (elt) != SET
327 || !REG_P (SET_DEST (elt))
328 || GET_MODE (SET_DEST (elt)) != SImode
329 || REGNO (SET_DEST (elt)) != regno
330 || !MEM_P (SET_SRC (elt))
331 || GET_MODE (SET_SRC (elt)) != SImode
332 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
333 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
334 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
335 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
342 /* Worker function for predicate for the parallel contents in a movem
346 cris_store_multiple_op_p (rtx op)
348 int reg_count = XVECLEN (op, 0);
359 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
360 other than (MEM reg) and (MEM (PLUS reg const)). */
364 elt = XVECEXP (op, 0, 0);
366 if (GET_CODE (elt) != SET)
369 dest = SET_DEST (elt);
371 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest))
374 dest_addr = XEXP (dest, 0);
376 /* Check a possible post-inc indicator. */
377 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
379 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
380 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
386 || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
387 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
388 || !CONST_INT_P (inc)
389 /* Support increment by number of registers, and by the offset
390 of the destination, if it has the form (MEM (PLUS reg
392 || !((REG_P (dest_addr)
393 && REGNO (dest_addr) == REGNO (reg)
394 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
395 || (GET_CODE (dest_addr) == PLUS
396 && REG_P (XEXP (dest_addr, 0))
397 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
398 && CONST_INT_P (XEXP (dest_addr, 1))
399 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
410 regno = reg_count - 1;
413 if (GET_CODE (elt) != SET
414 || !REG_P (SET_SRC (elt))
415 || GET_MODE (SET_SRC (elt)) != SImode
416 || REGNO (SET_SRC (elt)) != (unsigned int) regno
417 || !MEM_P (SET_DEST (elt))
418 || GET_MODE (SET_DEST (elt)) != SImode)
421 if (REG_P (dest_addr))
423 dest_base = dest_addr;
426 else if (GET_CODE (dest_addr) == PLUS
427 && REG_P (XEXP (dest_addr, 0))
428 && CONST_INT_P (XEXP (dest_addr, 1)))
430 dest_base = XEXP (dest_addr, 0);
431 offset = INTVAL (XEXP (dest_addr, 1));
436 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
438 rtx elt = XVECEXP (op, 0, i);
441 if (GET_CODE (elt) != SET
442 || !REG_P (SET_SRC (elt))
443 || GET_MODE (SET_SRC (elt)) != SImode
444 || REGNO (SET_SRC (elt)) != (unsigned int) regno
445 || !MEM_P (SET_DEST (elt))
446 || GET_MODE (SET_DEST (elt)) != SImode
447 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
448 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
449 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
450 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
457 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
460 cris_conditional_register_usage (void)
462 /* FIXME: This isn't nice. We should be able to use that register for
463 something else if the PIC table isn't needed. */
465 fixed_regs[PIC_OFFSET_TABLE_REGNUM]
466 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
468 /* Allow use of ACR (PC in pre-V32) and tweak order. */
471 static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32;
474 fixed_regs[CRIS_ACR_REGNUM] = 0;
477 i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]);
479 reg_alloc_order[i] = reg_alloc_order_v32[i];
482 if (TARGET_HAS_MUL_INSNS)
483 fixed_regs[CRIS_MOF_REGNUM] = 0;
485 /* On early versions, we must use the 16-bit condition-code register,
486 which has another name. */
487 if (cris_cpu_version < 8)
488 reg_names[CRIS_CC0_REGNUM] = "ccr";
491 /* Return crtl->uses_pic_offset_table. For use in cris.md,
492 since some generated files do not include function.h. */
495 cris_cfun_uses_pic_table (void)
497 return crtl->uses_pic_offset_table;
500 /* Given an rtx, return the text string corresponding to the CODE of X.
501 Intended for use in the assembly language output section of a
507 cris_output_insn_is_bound = 0;
508 switch (GET_CODE (x))
519 /* This function is for retrieving a part of an instruction name for
520 an operator, for immediate output. If that ever happens for
521 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
523 internal_error ("MULT case in cris_op_str");
559 /* Used to control the sign/zero-extend character for the 'E' modifier.
561 cris_output_insn_is_bound = 1;
566 return "Unknown operator";
571 /* Emit an error message when we're in an asm, and a fatal error for
572 "normal" insns. Formatted output isn't easily implemented, since we
573 use output_operand_lossage to output the actual message and handle the
574 categorization of the error. */
577 cris_operand_lossage (const char *msgid, rtx op)
580 output_operand_lossage ("%s", msgid);
583 /* Print an index part of an address to file. */
586 cris_print_index (rtx index, FILE *file)
588 /* Make the index "additive" unless we'll output a negative number, in
589 which case the sign character is free (as in free beer). */
590 if (!CONST_INT_P (index) || INTVAL (index) >= 0)
594 fprintf (file, "$%s.b", reg_names[REGNO (index)]);
595 else if (CONSTANT_P (index))
596 cris_output_addr_const (file, index);
597 else if (GET_CODE (index) == MULT)
599 fprintf (file, "$%s.",
600 reg_names[REGNO (XEXP (index, 0))]);
602 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
604 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
606 rtx inner = XEXP (index, 0);
607 rtx inner_inner = XEXP (inner, 0);
609 if (GET_CODE (inner_inner) == POST_INC)
611 fprintf (file, "[$%s+].",
612 reg_names[REGNO (XEXP (inner_inner, 0))]);
613 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
617 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
619 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
622 else if (MEM_P (index))
624 rtx inner = XEXP (index, 0);
625 if (GET_CODE (inner) == POST_INC)
626 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
628 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
631 cris_operand_lossage ("unexpected index-type in cris_print_index",
635 /* Print a base rtx of an address to file. */
638 cris_print_base (rtx base, FILE *file)
641 fprintf (file, "$%s", reg_names[REGNO (base)]);
642 else if (GET_CODE (base) == POST_INC)
644 gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM);
645 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
648 cris_operand_lossage ("unexpected base-type in cris_print_base",
652 /* Usable as a guard in expressions. */
655 cris_fatal (char *arg)
657 internal_error (arg);
659 /* We'll never get here; this is just to appease compilers. */
663 /* Return nonzero if REGNO is an ordinary register that *needs* to be
664 saved together with other registers, possibly by a MOVEM instruction,
665 or is saved for target-independent reasons. There may be
666 target-dependent reasons to save the register anyway; this is just a
667 wrapper for a complicated conditional. */
670 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
673 (((df_regs_ever_live_p (regno)
674 && !call_used_regs[regno])
675 || (regno == PIC_OFFSET_TABLE_REGNUM
677 /* It is saved anyway, if there would be a gap. */
679 && df_regs_ever_live_p (regno + 1)
680 && !call_used_regs[regno + 1]))))
681 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
682 && regno != CRIS_SRP_REGNUM)
683 || (crtl->calls_eh_return
684 && (regno == EH_RETURN_DATA_REGNO (0)
685 || regno == EH_RETURN_DATA_REGNO (1)
686 || regno == EH_RETURN_DATA_REGNO (2)
687 || regno == EH_RETURN_DATA_REGNO (3)));
690 /* The PRINT_OPERAND worker. */
693 cris_print_operand (FILE *file, rtx x, int code)
697 /* Size-strings corresponding to MULT expressions. */
698 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
700 /* New code entries should just be added to the switch below. If
701 handling is finished, just return. If handling was just a
702 modification of the operand, the modified operand should be put in
703 "operand", and then do a break to let default handling
704 (zero-modifier) output the operand. */
709 /* Print the unsigned supplied integer as if it were signed
710 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
711 if (!satisfies_constraint_O (x))
712 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
713 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
714 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
718 /* Print assembler code for operator. */
719 fprintf (file, "%s", cris_op_str (operand));
724 /* A movem modifier working on a parallel; output the register
728 if (GET_CODE (x) != PARALLEL)
729 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
731 /* The second item can be (set reg (plus reg const)) to denote a
734 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
736 : XVECLEN (x, 0) - 1);
738 fprintf (file, "$%s", reg_names [regno]);
744 /* A similar movem modifier; output the memory operand. */
747 if (GET_CODE (x) != PARALLEL)
748 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
750 /* The lowest mem operand is in the first item, but perhaps it
751 needs to be output as postincremented. */
752 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0)))
753 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
754 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
756 /* The second item can be a (set reg (plus reg const)) to denote
758 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
760 /* It's a post-increment, if the address is a naked (reg). */
762 addr = gen_rtx_POST_INC (SImode, addr);
765 /* Otherwise, it's a side-effect; RN=RN+M. */
766 fprintf (file, "[$%s=$%s%s%d]",
767 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
768 reg_names [REGNO (XEXP (addr, 0))],
769 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
770 (int) INTVAL (XEXP (addr, 1)));
774 output_address (addr);
779 /* Adjust a power of two to its log2. */
780 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 )
781 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
782 fprintf (file, "%d", exact_log2 (INTVAL (x)));
786 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
787 respectively. This modifier also terminates the inhibiting
788 effects of the 'x' modifier. */
789 cris_output_insn_is_bound = 0;
790 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
794 if (INTVAL (x) <= 255)
796 else if (INTVAL (x) <= 65535)
806 /* For a non-integer, print the size of the operand. */
807 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
808 ? 'd' : GET_MODE (x) == HImode ? 'w'
809 : GET_MODE (x) == QImode ? 'b'
810 /* If none of the above, emit an erroneous size letter. */
816 /* Const_int: print b for -127 <= x <= 255,
817 w for -32768 <= x <= 65535, else die. */
819 || INTVAL (x) < -32768 || INTVAL (x) > 65535)
820 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
821 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
825 /* If this is a GOT-symbol, print the size-letter corresponding to
826 -fpic/-fPIC. For everything else, print "d". */
828 && GET_CODE (x) == CONST
829 && GET_CODE (XEXP (x, 0)) == UNSPEC
830 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD)
835 /* Output a 'nop' if there's nothing for the delay slot.
836 This method stolen from the sparc files. */
837 if (dbr_sequence_length () == 0)
838 fputs ("\n\tnop", file);
842 /* Output directive for alignment padded with "nop" insns.
843 Optimizing for size, it's plain 4-byte alignment, otherwise we
844 align the section to a cache-line (32 bytes) and skip at max 2
845 bytes, i.e. we skip if it's the last insn on a cache-line. The
846 latter is faster by a small amount (for two test-programs 99.6%
847 and 99.9%) and larger by a small amount (ditto 100.1% and
848 100.2%). This is supposed to be the simplest yet performance-
849 wise least intrusive way to make sure the immediately following
850 (supposed) muls/mulu insn isn't located at the end of a
854 ? ".p2alignw 2,0x050f\n\t"
855 : ".p2alignw 5,0x050f,2\n\t", file);
859 /* The PIC register. */
861 internal_error ("invalid use of ':' modifier");
862 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
866 /* Print high (most significant) part of something. */
867 switch (GET_CODE (operand))
870 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
871 value is kept here, and so may be other than 0 or -1. */
872 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
873 INTVAL (operand_subword (operand, 1, 0, DImode)));
877 /* High part of a long long constant. */
878 if (GET_MODE (operand) == VOIDmode)
880 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
884 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
887 /* Print reg + 1. Check that there's not an attempt to print
888 high-parts of registers like stack-pointer or higher, except
889 for SRP (where the "high part" is MOF). */
890 if (REGNO (operand) > STACK_POINTER_REGNUM - 2
891 && (REGNO (operand) != CRIS_SRP_REGNUM
892 || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM
893 || fixed_regs[CRIS_MOF_REGNUM] != 0))
894 LOSE_AND_RETURN ("bad register", operand);
895 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
899 /* Adjust memory address to high part. */
901 rtx adj_mem = operand;
903 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
905 /* Adjust so we can use two SImode in DImode.
906 Calling adj_offsettable_operand will make sure it is an
907 offsettable address. Don't do this for a postincrement
908 though; it should remain as it was. */
909 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
911 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
913 output_address (XEXP (adj_mem, 0));
918 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
922 /* Strip the MEM expression. */
923 operand = XEXP (operand, 0);
927 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
928 iterators and attributes in cris.md to avoid the need for %x
929 and %E (and %e) and state passed between those modifiers. */
930 cris_output_insn_is_bound = 0;
933 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
934 cris_output_insn_is_bound is nonzero. */
935 if (GET_CODE (operand) != SIGN_EXTEND
936 && GET_CODE (operand) != ZERO_EXTEND
937 && !CONST_INT_P (operand))
938 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
940 if (cris_output_insn_is_bound)
942 cris_output_insn_is_bound = 0;
946 putc (GET_CODE (operand) == SIGN_EXTEND
947 || (CONST_INT_P (operand) && INTVAL (operand) < 0)
952 /* Print the size letter of the inner element. We can do it by
953 calling ourselves with the 's' modifier. */
954 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
955 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
956 cris_print_operand (file, XEXP (operand, 0), 's');
960 /* Print the least significant part of operand. */
961 if (GET_CODE (operand) == CONST_DOUBLE)
963 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
966 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand))
968 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
969 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
972 /* Otherwise the least significant part equals the normal part,
973 so handle it normally. */
977 /* When emitting an add for the high part of a DImode constant, we
978 want to use addq for 0 and adds.w for -1. */
979 if (!CONST_INT_P (operand))
980 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
981 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
985 /* For const_int operands, print the additive mnemonic and the
986 modified operand (byte-sized operands don't save anything):
987 N=MIN_INT..-65536: add.d N
988 -65535..-64: subu.w -N
992 65536..MAX_INT: add.d N.
993 (Emitted mnemonics are capitalized to simplify testing.)
994 For anything else (N.B: only register is valid), print "add.d". */
997 fprintf (file, "Add.d ");
999 /* Deal with printing the operand by dropping through to the
1006 gcc_assert (CONST_INT_P (operand));
1008 val = INTVAL (operand);
1009 if (!IN_RANGE (val, -65535, 65535))
1010 fprintf (file, "Add.d %d", val);
1011 else if (val <= -64)
1012 fprintf (file, "Subu.w %d", -val);
1014 fprintf (file, "Subq %d", -val);
1016 fprintf (file, "Addq %d", val);
1017 else if (val <= 65535)
1018 fprintf (file, "Addu.w %d", val);
1024 /* If the operand is an integer -31..31, print "q" else ".d". */
1025 if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31))
1026 fprintf (file, "q");
1028 fprintf (file, ".d");
1032 /* If this is a GOT symbol, force it to be emitted as :GOT and
1033 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1034 Avoid making this too much of a special case. */
1035 if (flag_pic == 1 && CONSTANT_P (operand))
1037 int flag_pic_save = flag_pic;
1040 cris_output_addr_const (file, operand);
1041 flag_pic = flag_pic_save;
1047 /* When emitting an sub for the high part of a DImode constant, we
1048 want to use subq for 0 and subs.w for -1. */
1049 if (!CONST_INT_P (operand))
1050 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
1051 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
1055 /* Print the operand as the index-part of an address.
1056 Easiest way out is to use cris_print_index. */
1057 cris_print_index (operand, file);
1061 /* Print the size letter for an operand to a MULT, which must be a
1062 const_int with a suitable value. */
1063 if (!CONST_INT_P (operand) || INTVAL (operand) > 4)
1064 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
1065 fprintf (file, "%s", mults[INTVAL (operand)]);
1069 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1071 && GET_CODE (operand) == CONST
1072 && GET_CODE (XEXP (operand, 0)) == UNSPEC
1073 && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD)
1074 fprintf (file, "u.w");
1076 fprintf (file, ".d");
1080 /* No code, print as usual. */
1084 LOSE_AND_RETURN ("invalid operand modifier letter", x);
1087 /* Print an operand as without a modifier letter. */
1088 switch (GET_CODE (operand))
1091 if (REGNO (operand) > 15
1092 && REGNO (operand) != CRIS_MOF_REGNUM
1093 && REGNO (operand) != CRIS_SRP_REGNUM
1094 && REGNO (operand) != CRIS_CC0_REGNUM)
1095 internal_error ("internal error: bad register: %d", REGNO (operand));
1096 fprintf (file, "$%s", reg_names[REGNO (operand)]);
1100 output_address (XEXP (operand, 0));
1104 if (GET_MODE (operand) == VOIDmode)
1105 /* A long long constant. */
1106 output_addr_const (file, operand);
1109 /* Only single precision is allowed as plain operands the
1110 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1115 /* FIXME: Perhaps check overflow of the "single". */
1116 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
1117 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1119 fprintf (file, "0x%lx", l);
1126 cris_output_addr_const (file, operand);
1132 /* For a (MULT (reg X) const_int) we output "rX.S". */
1133 int i = CONST_INT_P (XEXP (operand, 1))
1134 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1135 rtx reg = CONST_INT_P (XEXP (operand, 1))
1136 ? XEXP (operand, 0) : XEXP (operand, 1);
1139 || (!CONST_INT_P (XEXP (operand, 0))
1140 && !CONST_INT_P (XEXP (operand, 1))))
1141 LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1143 cris_print_base (reg, file);
1144 fprintf (file, ".%c",
1145 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1147 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1153 /* No need to handle all strange variants, let output_addr_const
1155 if (CONSTANT_P (operand))
1157 cris_output_addr_const (file, operand);
1161 LOSE_AND_RETURN ("unexpected operand", x);
1166 cris_print_operand_punct_valid_p (unsigned char code)
1168 return (code == '#' || code == '!' || code == ':');
1171 /* The PRINT_OPERAND_ADDRESS worker. */
1174 cris_print_operand_address (FILE *file, rtx x)
1176 /* All these were inside MEM:s so output indirection characters. */
1179 if (CONSTANT_ADDRESS_P (x))
1180 cris_output_addr_const (file, x);
1181 else if (cris_base_or_autoincr_p (x, true))
1182 cris_print_base (x, file);
1183 else if (GET_CODE (x) == PLUS)
1189 if (cris_base_p (x1, true))
1191 cris_print_base (x1, file);
1192 cris_print_index (x2, file);
1194 else if (cris_base_p (x2, true))
1196 cris_print_base (x2, file);
1197 cris_print_index (x1, file);
1200 LOSE_AND_RETURN ("unrecognized address", x);
1204 /* A DIP. Output more indirection characters. */
1206 cris_print_base (XEXP (x, 0), file);
1210 LOSE_AND_RETURN ("unrecognized address", x);
1215 /* The RETURN_ADDR_RTX worker.
1216 We mark that the return address is used, either by EH or
1217 __builtin_return_address, for use by the function prologue and
1218 epilogue. FIXME: This isn't optimal; we just use the mark in the
1219 prologue and epilogue to say that the return address is to be stored
1220 in the stack frame. We could return SRP for leaf-functions and use the
1221 initial-value machinery. */
1224 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1226 cfun->machine->needs_return_address_on_stack = 1;
1228 /* The return-address is stored just above the saved frame-pointer (if
1229 present). Apparently we can't eliminate from the frame-pointer in
1230 that direction, so use the incoming args (maybe pretended) pointer. */
1232 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4))
1236 /* Accessor used in cris.md:return because cfun->machine isn't available
1240 cris_return_address_on_stack (void)
1242 return df_regs_ever_live_p (CRIS_SRP_REGNUM)
1243 || cfun->machine->needs_return_address_on_stack;
1246 /* Accessor used in cris.md:return because cfun->machine isn't available
1250 cris_return_address_on_stack_for_return (void)
1252 return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1253 : cris_return_address_on_stack ();
1256 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1257 handles FP -> SP elimination offset. */
1260 cris_initial_frame_pointer_offset (void)
1264 /* Initial offset is 0 if we don't have a frame pointer. */
1266 bool got_really_used = false;
1268 if (crtl->uses_pic_offset_table)
1270 push_topmost_sequence ();
1272 = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1274 pop_topmost_sequence ();
1277 /* And 4 for each register pushed. */
1278 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1279 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1282 /* And then, last, we add the locals allocated. */
1283 offs += get_frame_size ();
1285 /* And more; the accumulated args size. */
1286 offs += crtl->outgoing_args_size;
1288 /* Then round it off, in case we use aligned stack. */
1289 if (TARGET_STACK_ALIGN)
1290 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1295 /* The INITIAL_ELIMINATION_OFFSET worker.
1296 Calculate the difference between imaginary registers such as frame
1297 pointer and the stack pointer. Used to eliminate the frame pointer
1298 and imaginary arg pointer. */
1301 cris_initial_elimination_offset (int fromreg, int toreg)
1304 = cris_initial_frame_pointer_offset ();
1306 /* We should be able to use regs_ever_live and related prologue
1307 information here, or alpha should not as well. */
1308 bool return_address_on_stack = cris_return_address_on_stack ();
1310 /* Here we act as if the frame-pointer were needed. */
1311 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1313 if (fromreg == ARG_POINTER_REGNUM
1314 && toreg == FRAME_POINTER_REGNUM)
1315 return ap_fp_offset;
1317 /* Between the frame pointer and the stack are only "normal" stack
1318 variables and saved registers. */
1319 if (fromreg == FRAME_POINTER_REGNUM
1320 && toreg == STACK_POINTER_REGNUM)
1321 return fp_sp_offset;
1323 /* We need to balance out the frame pointer here. */
1324 if (fromreg == ARG_POINTER_REGNUM
1325 && toreg == STACK_POINTER_REGNUM)
1326 return ap_fp_offset + fp_sp_offset - 4;
1331 /* Nonzero if X is a hard reg that can be used as an index. */
1333 reg_ok_for_base_p (const_rtx x, bool strict)
1335 return ((! strict && ! HARD_REGISTER_P (x))
1336 || REGNO_OK_FOR_BASE_P (REGNO (x)));
1339 /* Nonzero if X is a hard reg that can be used as an index. */
1341 reg_ok_for_index_p (const_rtx x, bool strict)
1343 return reg_ok_for_base_p (x, strict);
1346 /* No symbol can be used as an index (or more correct, as a base) together
1347 with a register with PIC; the PIC register must be there. */
1350 cris_constant_index_p (const_rtx x)
1352 return (CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true)));
1355 /* True if X is a valid base register. */
1358 cris_base_p (const_rtx x, bool strict)
1360 return (REG_P (x) && reg_ok_for_base_p (x, strict));
1363 /* True if X is a valid index register. */
1366 cris_index_p (const_rtx x, bool strict)
1368 return (REG_P (x) && reg_ok_for_index_p (x, strict));
1371 /* True if X is a valid base register with or without autoincrement. */
1374 cris_base_or_autoincr_p (const_rtx x, bool strict)
1376 return (cris_base_p (x, strict)
1377 || (GET_CODE (x) == POST_INC
1378 && cris_base_p (XEXP (x, 0), strict)
1379 && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM));
1382 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1385 cris_bdap_index_p (const_rtx x, bool strict)
1388 && GET_MODE (x) == SImode
1389 && cris_base_or_autoincr_p (XEXP (x, 0), strict))
1390 || (GET_CODE (x) == SIGN_EXTEND
1391 && MEM_P (XEXP (x, 0))
1392 && (GET_MODE (XEXP (x, 0)) == HImode
1393 || GET_MODE (XEXP (x, 0)) == QImode)
1394 && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict)));
1397 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1400 cris_biap_index_p (const_rtx x, bool strict)
1402 return (cris_index_p (x, strict)
1403 || (GET_CODE (x) == MULT
1404 && cris_index_p (XEXP (x, 0), strict)
1405 && cris_scale_int_operand (XEXP (x, 1), VOIDmode)));
1408 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1410 A PIC operand looks like a normal symbol here. At output we dress it
1411 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1412 symbol) so we exclude all addressing modes where we can't replace a
1413 plain "symbol" with that. A global PIC symbol does not fit anywhere
1414 here (but is thankfully a general_operand in itself). A local PIC
1415 symbol is valid for the plain "symbol + offset" case. */
1418 cris_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1422 if (cris_base_or_autoincr_p (x, strict))
1424 else if (TARGET_V32)
1425 /* Nothing else is valid then. */
1427 else if (cris_constant_index_p (x))
1430 else if (GET_CODE (x) == PLUS)
1435 if ((cris_base_p (x1, strict) && cris_constant_index_p (x2))
1436 || (cris_base_p (x2, strict) && cris_constant_index_p (x1))
1437 /* BDAP Rs[+], Rd. */
1438 || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1439 && ((cris_base_p (x1, strict)
1440 && cris_bdap_index_p (x2, strict))
1441 || (cris_base_p (x2, strict)
1442 && cris_bdap_index_p (x1, strict))
1444 || (cris_base_p (x1, strict)
1445 && cris_biap_index_p (x2, strict))
1446 || (cris_base_p (x2, strict)
1447 && cris_biap_index_p (x1, strict)))))
1452 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1453 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1454 && cris_base_or_autoincr_p (XEXP (x, 0), strict))
1461 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1464 cris_reload_address_legitimized (rtx x,
1465 enum machine_mode mode ATTRIBUTE_UNUSED,
1466 int opnum ATTRIBUTE_UNUSED,
1468 int ind_levels ATTRIBUTE_UNUSED)
1470 enum reload_type type = (enum reload_type) itype;
1474 if (GET_CODE (x) != PLUS)
1482 op1p = &XEXP (x, 1);
1487 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
1489 rtx op00 = XEXP (op0, 0);
1490 rtx op000 = XEXP (op00, 0);
1491 rtx *op000p = &XEXP (op00, 0);
1493 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1495 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1497 bool something_reloaded = false;
1499 if (GET_CODE (op000) == POST_INC
1500 && REG_P (XEXP (op000, 0))
1501 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1502 /* No, this gets too complicated and is too rare to care
1503 about trying to improve on the general code Here.
1504 As the return-value is an all-or-nothing indicator, we
1505 punt on the other register too. */
1509 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1511 /* The address of the inner mem is a pseudo or wrong
1512 reg: reload that. */
1513 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1514 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1515 something_reloaded = true;
1518 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1520 /* Base register is a pseudo or wrong reg: reload it. */
1521 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1522 GET_MODE (x), VOIDmode, 0, 0,
1524 something_reloaded = true;
1527 gcc_assert (something_reloaded);
1537 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1539 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1540 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1541 out a constant into the constant pool, we will trap this case and
1542 return something a bit more sane. FIXME: Check if this is a bug.
1543 Beware that we must not "override" classes that can be specified as
1544 constraint letters, or else asm operands using them will fail when
1545 they need to be reloaded. FIXME: Investigate whether that constitutes
1549 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
1551 if (rclass != ACR_REGS
1552 && rclass != MOF_REGS
1553 && rclass != MOF_SRP_REGS
1554 && rclass != SRP_REGS
1555 && rclass != CC0_REGS
1556 && rclass != SPECIAL_REGS)
1557 return GENERAL_REGS;
1562 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1565 cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1566 reg_class_t from, reg_class_t to)
1568 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1569 their move cost within that class is higher. How about 7? That's 3
1570 for a move to a GENERAL_REGS register, 3 for the move from the
1571 GENERAL_REGS register, and 1 for the increased register pressure.
1572 Also, it's higher than the memory move cost, as it should.
1573 We also do this for ALL_REGS, since we don't want that class to be
1574 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1575 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1576 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1577 used when a GENERAL_REGS should be used, even if there are call-saved
1578 GENERAL_REGS left to allocate. This is because the fall-back when
1579 the most preferred register class isn't available, isn't the next
1580 (or next good) wider register class, but the *most widest* register
1581 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1583 if ((reg_classes_intersect_p (from, SPECIAL_REGS)
1584 && reg_classes_intersect_p (to, SPECIAL_REGS))
1585 || from == ALL_REGS || to == ALL_REGS)
1588 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1589 generally prefer GENERAL_REGS. */
1590 if (reg_classes_intersect_p (from, SPECIAL_REGS)
1591 || reg_classes_intersect_p (to, SPECIAL_REGS))
1597 /* Worker function for TARGET_MEMORY_MOVE_COST.
1599 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1603 cris_memory_move_cost (enum machine_mode mode,
1604 reg_class_t rclass ATTRIBUTE_UNUSED,
1605 bool in ATTRIBUTE_UNUSED)
1614 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1615 FIXME: this code is historical; its functionality should be
1616 refactored to look at insn attributes and moved to
1617 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1620 cris_normal_notice_update_cc (rtx exp, rtx insn)
1622 /* "Normal" means, for:
1627 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1628 register or (v32 and (...) is -32..-1), then CC does not change.
1629 CC_NO_OVERFLOW unless (...) is reg or mem.
1638 (set (reg1) (mem (bdap/biap)))
1639 (set (reg2) (bdap/biap))):
1640 CC is (reg1) and (mem (reg2))
1643 (set (mem (bdap/biap)) (reg1)) [or 0]
1644 (set (reg2) (bdap/biap))):
1647 (where reg and mem includes strict_low_parts variants thereof)
1649 For all others, assume CC is clobbered.
1650 Note that we do not have to care about setting CC_NO_OVERFLOW,
1651 since the overflow flag is set to 0 (i.e. right) for
1652 instructions where it does not have any sane sense, but where
1653 other flags have meanings. (This includes shifts; the carry is
1656 Note that there are other parallel constructs we could match,
1657 but we don't do that yet. */
1659 if (GET_CODE (exp) == SET)
1661 /* FIXME: Check when this happens. It looks like we should
1662 actually do a CC_STATUS_INIT here to be safe. */
1663 if (SET_DEST (exp) == pc_rtx)
1666 /* Record CC0 changes, so we do not have to output multiple
1668 if (SET_DEST (exp) == cc0_rtx)
1672 if (GET_CODE (SET_SRC (exp)) == COMPARE
1673 && XEXP (SET_SRC (exp), 1) == const0_rtx)
1674 cc_status.value1 = XEXP (SET_SRC (exp), 0);
1676 cc_status.value1 = SET_SRC (exp);
1678 /* Handle flags for the special btstq on one bit. */
1679 if (GET_CODE (cc_status.value1) == ZERO_EXTRACT
1680 && XEXP (cc_status.value1, 1) == const1_rtx)
1682 if (CONST_INT_P (XEXP (cc_status.value1, 0)))
1684 cc_status.flags = CC_INVERTED;
1686 /* A one-bit btstq. */
1687 cc_status.flags = CC_Z_IN_NOT_N;
1690 else if (GET_CODE (SET_SRC (exp)) == COMPARE)
1692 if (!REG_P (XEXP (SET_SRC (exp), 0))
1693 && XEXP (SET_SRC (exp), 1) != const0_rtx)
1694 /* For some reason gcc will not canonicalize compare
1695 operations, reversing the sign by itself if
1696 operands are in wrong order. */
1697 /* (But NOT inverted; eq is still eq.) */
1698 cc_status.flags = CC_REVERSED;
1700 /* This seems to be overlooked by gcc. FIXME: Check again.
1701 FIXME: Is it really safe? */
1703 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1704 XEXP (SET_SRC (exp), 0),
1705 XEXP (SET_SRC (exp), 1));
1709 else if (REG_P (SET_DEST (exp))
1710 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1711 && REG_P (XEXP (SET_DEST (exp), 0))))
1713 /* A register is set; normally CC is set to show that no
1714 test insn is needed. Catch the exceptions. */
1716 /* If not to cc0, then no "set"s in non-natural mode give
1718 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1719 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1721 /* ... except add:s and sub:s in DImode. */
1722 if (GET_MODE (SET_DEST (exp)) == DImode
1723 && (GET_CODE (SET_SRC (exp)) == PLUS
1724 || GET_CODE (SET_SRC (exp)) == MINUS))
1727 cc_status.value1 = SET_DEST (exp);
1728 cc_status.value2 = SET_SRC (exp);
1730 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1732 cc_status.value2 = 0;
1734 /* Add and sub may set V, which gets us
1735 unoptimizable results in "gt" and "le" condition
1737 cc_status.flags |= CC_NO_OVERFLOW;
1742 else if (SET_SRC (exp) == const0_rtx
1743 || (REG_P (SET_SRC (exp))
1744 && (REGNO (SET_SRC (exp))
1745 > CRIS_LAST_GENERAL_REGISTER))
1747 && REG_P (SET_DEST (exp))
1748 && satisfies_constraint_I (SET_SRC (exp))))
1750 /* There's no CC0 change for this case. Just check
1752 if (cc_status.value1
1753 && modified_in_p (cc_status.value1, insn))
1754 cc_status.value1 = 0;
1756 if (cc_status.value2
1757 && modified_in_p (cc_status.value2, insn))
1758 cc_status.value2 = 0;
1765 cc_status.value1 = SET_DEST (exp);
1766 cc_status.value2 = SET_SRC (exp);
1768 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1770 cc_status.value2 = 0;
1772 /* Some operations may set V, which gets us
1773 unoptimizable results in "gt" and "le" condition
1775 if (GET_CODE (SET_SRC (exp)) == PLUS
1776 || GET_CODE (SET_SRC (exp)) == MINUS
1777 || GET_CODE (SET_SRC (exp)) == NEG)
1778 cc_status.flags |= CC_NO_OVERFLOW;
1780 /* For V32, nothing with a register destination sets
1781 C and V usefully. */
1783 cc_status.flags |= CC_NO_OVERFLOW;
1788 else if (MEM_P (SET_DEST (exp))
1789 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1790 && MEM_P (XEXP (SET_DEST (exp), 0))))
1792 /* When SET to MEM, then CC is not changed (except for
1794 if (cc_status.value1
1795 && modified_in_p (cc_status.value1, insn))
1796 cc_status.value1 = 0;
1798 if (cc_status.value2
1799 && modified_in_p (cc_status.value2, insn))
1800 cc_status.value2 = 0;
1805 else if (GET_CODE (exp) == PARALLEL)
1807 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1808 && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1809 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1811 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1812 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1)))
1816 /* For "move.S [rx=ry+o],rz", say CC reflects
1817 value1=rz and value2=[rx] */
1818 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1820 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1821 XEXP (XVECEXP (exp, 0, 1), 0));
1823 /* Huh? A side-effect cannot change the destination
1825 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1827 internal_error ("internal error: sideeffect-insn affecting main effect");
1829 /* For V32, moves to registers don't set C and V. */
1831 cc_status.flags |= CC_NO_OVERFLOW;
1834 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1835 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1836 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0)))
1838 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1839 say flags are not changed, except for overlap. */
1840 if (cc_status.value1
1841 && modified_in_p (cc_status.value1, insn))
1842 cc_status.value1 = 0;
1844 if (cc_status.value2
1845 && modified_in_p (cc_status.value2, insn))
1846 cc_status.value2 = 0;
1853 /* If we got here, the case wasn't covered by the code above. */
1857 /* This function looks into the pattern to see how this insn affects
1860 Used when to eliminate test insns before a condition-code user,
1861 such as a "scc" insn or a conditional branch. This includes
1862 checking if the entities that cc was updated by, are changed by the
1865 Currently a jumble of the old peek-inside-the-insn and the newer
1866 check-cc-attribute methods. */
1869 cris_notice_update_cc (rtx exp, rtx insn)
1871 enum attr_cc attrval = get_attr_cc (insn);
1873 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1874 to still set CC_REVERSED as below, since that's required by some
1875 compare insn alternatives. (FIXME: GCC should do this virtual
1876 operand swap by itself.) A test-case that may otherwise fail is
1877 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1882 if (attrval == CC_REV)
1883 cc_status.flags = CC_REVERSED;
1887 /* Slowly, we're converting to using attributes to control the setting
1888 of condition-code status. */
1892 /* Even if it is "none", a setting may clobber a previous
1893 cc-value, so check. */
1894 if (GET_CODE (exp) == SET)
1896 if (cc_status.value1
1897 && modified_in_p (cc_status.value1, insn))
1898 cc_status.value1 = 0;
1900 if (cc_status.value2
1901 && modified_in_p (cc_status.value2, insn))
1902 cc_status.value2 = 0;
1913 cris_normal_notice_update_cc (exp, insn);
1915 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1916 can change bge => bpl and blt => bmi by passing on to the cc0
1917 user that V should not be considered; bgt and ble are taken
1918 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1919 if (attrval == CC_NOOV32 && TARGET_V32)
1920 cc_status.flags |= CC_NO_OVERFLOW;
1924 internal_error ("unknown cc_attr value");
1930 /* Return != 0 if the return sequence for the current function is short,
1931 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1932 registers must be saved, so return 0 then. */
1935 cris_simple_epilogue (void)
1938 unsigned int reglimit = STACK_POINTER_REGNUM;
1939 bool got_really_used = false;
1941 if (! reload_completed
1942 || frame_pointer_needed
1943 || get_frame_size () != 0
1944 || crtl->args.pretend_args_size
1946 || crtl->outgoing_args_size
1947 || crtl->calls_eh_return
1949 /* If we're not supposed to emit prologue and epilogue, we must
1950 not emit return-type instructions. */
1951 || !TARGET_PROLOGUE_EPILOGUE)
1954 /* Can't return from stacked return address with v32. */
1955 if (TARGET_V32 && cris_return_address_on_stack ())
1958 if (crtl->uses_pic_offset_table)
1960 push_topmost_sequence ();
1962 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
1963 pop_topmost_sequence ();
1966 /* No simple epilogue if there are saved registers. */
1967 for (regno = 0; regno < reglimit; regno++)
1968 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1974 /* Emit checking that MEM is aligned for an access in MODE, failing
1975 that, executing a "break 8" (or call to abort, if "break 8" is
1979 cris_emit_trap_for_misalignment (rtx mem)
1981 rtx addr, reg, ok_label, andop, jmp;
1982 int natural_alignment;
1983 gcc_assert (MEM_P (mem));
1985 natural_alignment = GET_MODE_SIZE (GET_MODE (mem));
1986 addr = XEXP (mem, 0);
1987 reg = force_reg (Pmode, addr);
1988 ok_label = gen_label_rtx ();
1990 /* This will yield a btstq without a separate register used, usually -
1991 with the exception for PRE hoisting the "and" but not the branch
1992 around the trap: see gcc.dg/target/cris/sync-3s.c. */
1993 andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1));
1994 emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ,
1995 NULL_RTX, Pmode, 1, ok_label);
1996 jmp = get_last_insn ();
1997 gcc_assert (JUMP_P (jmp));
1999 /* While this isn't mudflap, it is a similar kind of assertion.
2000 If PRED_MUDFLAP stops working, use something else or introduce a
2001 more suitable assertion predication type. */
2002 predict_insn_def (jmp, PRED_MUDFLAP, TAKEN);
2003 expand_builtin_trap ();
2004 emit_label (ok_label);
2007 /* Expand a return insn (just one insn) marked as using SRP or stack
2008 slot depending on parameter ON_STACK. */
2011 cris_expand_return (bool on_stack)
2013 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2014 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2015 GCC expect just (return) to do the right thing when optimizing, so
2016 we do that until they're fixed. Currently, all return insns in a
2017 function must be the same (not really a limiting factor) so we need
2018 to check that it doesn't change half-way through. */
2019 emit_jump_insn (ret_rtx);
2021 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
2022 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
2024 cfun->machine->return_type
2025 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
2028 /* Compute a (partial) cost for rtx X. Return true if the complete
2029 cost has been computed, and false if subexpressions should be
2030 scanned. In either case, *TOTAL contains the cost result. */
2033 cris_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
2040 HOST_WIDE_INT val = INTVAL (x);
2043 else if (val < 32 && val >= -32)
2045 /* Eight or 16 bits are a word and cycle more expensive. */
2046 else if (val <= 32767 && val >= -32768)
2048 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2049 another word. FIXME: This isn't linear to 16 bits. */
2065 if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x)))
2068 /* Make 0.0 cheap, else test-insns will not be used. */
2073 /* If we have one arm of an ADDI, make sure it gets the cost of
2074 one insn, i.e. zero cost for this operand, and just the cost
2075 of the PLUS, as the insn is created by combine from a PLUS
2076 and an ASHIFT, and the MULT cost below would make the
2077 combined value be larger than the separate insns. The insn
2078 validity is checked elsewhere by combine.
2080 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2081 function should be rewritten. */
2082 if (outer_code == PLUS && cris_biap_index_p (x, false))
2088 /* Identify values that are no powers of two. Powers of 2 are
2089 taken care of already and those values should not be changed. */
2090 if (!CONST_INT_P (XEXP (x, 1))
2091 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
2093 /* If we have a multiply insn, then the cost is between
2094 1 and 2 "fast" instructions. */
2095 if (TARGET_HAS_MUL_INSNS)
2097 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2101 /* Estimate as 4 + 4 * #ofbits. */
2102 *total = COSTS_N_INSNS (132);
2111 if (!CONST_INT_P (XEXP (x, 1))
2112 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
2114 /* Estimate this as 4 + 8 * #of bits. */
2115 *total = COSTS_N_INSNS (260);
2121 if (CONST_INT_P (XEXP (x, 1))
2122 /* Two constants may actually happen before optimization. */
2123 && !CONST_INT_P (XEXP (x, 0))
2124 && !satisfies_constraint_I (XEXP (x, 1)))
2127 = (rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code,
2129 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0))));
2135 if (outer_code != COMPARE)
2139 case ZERO_EXTEND: case SIGN_EXTEND:
2140 *total = rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, opno, speed);
2148 /* The ADDRESS_COST worker. */
2151 cris_address_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED,
2152 addr_space_t as ATTRIBUTE_UNUSED,
2153 bool speed ATTRIBUTE_UNUSED)
2155 /* The metric to use for the cost-macros is unclear.
2156 The metric used here is (the number of cycles needed) / 2,
2157 where we consider equal a cycle for a word of code and a cycle to
2158 read memory. FIXME: Adding "+ 1" to all values would avoid
2159 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2160 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2161 Unfortunately(?) such a hack would expose other pessimizations,
2162 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2163 loop there, without apparent reason. */
2165 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2166 if (cris_base_or_autoincr_p (x, false))
2169 /* An indirect mem must be a DIP. This means two bytes extra for code,
2170 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2174 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2175 an extra DIP prefix and 4 bytes of constant in most cases. */
2179 /* Handle BIAP and BDAP prefixes. */
2180 if (GET_CODE (x) == PLUS)
2182 rtx tem1 = XEXP (x, 0);
2183 rtx tem2 = XEXP (x, 1);
2185 /* Local extended canonicalization rule: the first operand must
2186 be REG, unless it's an operation (MULT). */
2187 if (!REG_P (tem1) && GET_CODE (tem1) != MULT)
2188 tem1 = tem2, tem2 = XEXP (x, 0);
2190 /* We'll "assume" we have canonical RTX now. */
2191 gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT);
2193 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2194 recognize the typical MULT which is always in tem1 because of
2195 insn canonicalization. */
2196 if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false))
2200 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2201 PLUS is always found in tem2. */
2202 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
2205 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2207 if (satisfies_constraint_L (tem2))
2210 /* A BDAP with some other constant is 2 bytes extra. */
2211 if (CONSTANT_P (tem2))
2212 return (2 + 2 + 2) / 2;
2214 /* BDAP with something indirect should have a higher cost than
2215 BIAP with register. FIXME: Should it cost like a MEM or more? */
2216 return (2 + 2 + 2) / 2;
2219 /* What else? Return a high cost. It matters only for valid
2220 addressing modes. */
2224 /* Check various objections to the side-effect. Used in the test-part
2225 of an anonymous insn describing an insn with a possible side-effect.
2226 Returns nonzero if the implied side-effect is ok.
2229 ops : An array of rtx:es. lreg, rreg, rval,
2230 The variables multop and other_op are indexes into this,
2231 or -1 if they are not applicable.
2232 lreg : The register that gets assigned in the side-effect.
2233 rreg : One register in the side-effect expression
2234 rval : The other register, or an int.
2235 multop : An integer to multiply rval with.
2236 other_op : One of the entities of the main effect,
2237 whose mode we must consider. */
2240 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
2241 int lreg, int rreg, int rval,
2242 int multop, int other_op)
2244 /* Find what value to multiply with, for rx =ry + rz * n. */
2245 int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
2247 rtx reg_rtx = ops[rreg];
2248 rtx val_rtx = ops[rval];
2250 /* The operands may be swapped. Canonicalize them in reg_rtx and
2251 val_rtx, where reg_rtx always is a reg (for this constraint to
2253 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2254 reg_rtx = val_rtx, val_rtx = ops[rreg];
2256 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2257 we have no business. */
2258 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2261 /* Don't do this when -mno-split. */
2262 if (!TARGET_SIDE_EFFECT_PREFIXES)
2265 /* The mult expression may be hidden in lreg. FIXME: Add more
2266 commentary about that. */
2267 if (GET_CODE (val_rtx) == MULT)
2269 mult = INTVAL (XEXP (val_rtx, 1));
2270 val_rtx = XEXP (val_rtx, 0);
2274 /* First check the "other operand". */
2277 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
2280 /* Check if the lvalue register is the same as the "other
2281 operand". If so, the result is undefined and we shouldn't do
2282 this. FIXME: Check again. */
2283 if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed)
2284 && cris_base_p (ops[other_op],
2285 reload_in_progress || reload_completed)
2286 && REGNO (ops[lreg]) == REGNO (ops[other_op]))
2287 || rtx_equal_p (ops[other_op], ops[lreg]))
2291 /* Do not accept frame_pointer_rtx as any operand. */
2292 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
2293 || ops[rval] == frame_pointer_rtx
2294 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
2298 && ! cris_base_p (val_rtx, reload_in_progress || reload_completed))
2301 /* Do not allow rx = rx + n if a normal add or sub with same size
2303 if (rtx_equal_p (ops[lreg], reg_rtx)
2304 && CONST_INT_P (val_rtx)
2305 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
2308 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2309 if (CONSTANT_P (val_rtx))
2313 && cris_base_or_autoincr_p (XEXP (val_rtx, 0),
2314 reload_in_progress || reload_completed))
2317 if (GET_CODE (val_rtx) == SIGN_EXTEND
2318 && MEM_P (XEXP (val_rtx, 0))
2319 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0),
2320 reload_in_progress || reload_completed))
2323 /* If we got here, it's not a valid addressing mode. */
2326 else if (code == MULT
2328 && cris_base_p (val_rtx,
2329 reload_in_progress || reload_completed)))
2331 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2332 if (rtx_equal_p (ops[lreg], reg_rtx)
2333 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
2336 /* Do not allow bad multiply-values. */
2337 if (mult != 1 && mult != 2 && mult != 4)
2340 /* Only allow r + ... */
2341 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2344 /* If we got here, all seems ok.
2345 (All checks need to be done above). */
2349 /* If we get here, the caller got its initial tests wrong. */
2350 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2353 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2354 insn for other reasons. */
2357 cris_cc0_user_requires_cmp (rtx insn)
2359 rtx cc0_user = NULL;
2363 gcc_assert (insn != NULL);
2368 cc0_user = next_cc0_user (insn);
2369 if (cc0_user == NULL)
2372 body = PATTERN (cc0_user);
2373 set = single_set (cc0_user);
2375 /* Users can be sCC and bCC. */
2376 if (JUMP_P (cc0_user)
2377 && GET_CODE (body) == SET
2378 && SET_DEST (body) == pc_rtx
2379 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
2380 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx)
2383 GET_CODE (XEXP (SET_SRC (body), 0)) == GT
2384 || GET_CODE (XEXP (SET_SRC (body), 0)) == LE;
2389 GET_CODE (SET_SRC (body)) == GT
2390 || GET_CODE (SET_SRC (body)) == LE;
2396 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2397 does not handle the case where the IN operand is strict_low_part; it
2398 does handle it for X. Test-case in Axis-20010516. This function takes
2399 care of that for THIS port. FIXME: strict_low_part is going away
2403 cris_reg_overlap_mentioned_p (rtx x, rtx in)
2405 /* The function reg_overlap_mentioned now handles when X is
2406 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2407 if (GET_CODE (in) == STRICT_LOW_PART)
2410 return reg_overlap_mentioned_p (x, in);
2413 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2414 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2418 cris_valid_pic_const (const_rtx x, bool any_operand)
2420 gcc_assert (flag_pic);
2422 switch (GET_CODE (x))
2431 if (GET_CODE (x) != CONST)
2436 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2437 if (GET_CODE (x) == PLUS
2438 && GET_CODE (XEXP (x, 0)) == UNSPEC
2439 && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
2440 || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL)
2441 && CONST_INT_P (XEXP (x, 1)))
2444 if (GET_CODE (x) == UNSPEC)
2445 switch (XINT (x, 1))
2447 /* A PCREL operand is only valid for call and movsi. */
2448 case CRIS_UNSPEC_PLT_PCREL:
2449 case CRIS_UNSPEC_PCREL:
2450 return !any_operand;
2452 case CRIS_UNSPEC_PLT_GOTREL:
2453 case CRIS_UNSPEC_PLTGOTREAD:
2454 case CRIS_UNSPEC_GOTREAD:
2455 case CRIS_UNSPEC_GOTREL:
2461 return cris_pic_symbol_type_of (x) == cris_no_symbol;
2464 /* Helper function to find the right PIC-type symbol to generate,
2465 given the original (non-PIC) representation. */
2467 enum cris_pic_symbol_type
2468 cris_pic_symbol_type_of (const_rtx x)
2470 switch (GET_CODE (x))
2473 return SYMBOL_REF_LOCAL_P (x)
2474 ? cris_rel_symbol : cris_got_symbol;
2477 return cris_rel_symbol;
2480 return cris_pic_symbol_type_of (XEXP (x, 0));
2485 enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0));
2486 enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1));
2488 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
2490 if (t1 == cris_got_symbol || t1 == cris_got_symbol)
2491 return cris_got_symbol_needing_fixup;
2493 return t1 != cris_no_symbol ? t1 : t2;
2498 return cris_no_symbol;
2501 /* Likely an offsettability-test attempting to add a constant to
2502 a GOTREAD symbol, which can't be handled. */
2503 return cris_invalid_pic_symbol;
2506 fatal_insn ("unrecognized supposed constant", x);
2512 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2515 cris_legitimate_pic_operand (rtx x)
2517 /* Symbols are not valid PIC operands as-is; just constants. */
2518 return cris_valid_pic_const (x, true);
2521 /* Queue an .ident string in the queue of top-level asm statements.
2522 If the front-end is done, we must be being called from toplev.c.
2523 In that case, do nothing. */
2525 cris_asm_output_ident (const char *string)
2527 if (cgraph_state != CGRAPH_STATE_PARSING)
2530 default_asm_output_ident_directive (string);
2533 /* The ASM_OUTPUT_CASE_END worker. */
2536 cris_asm_output_case_end (FILE *stream, int num, rtx table)
2538 /* Step back, over the label for the table, to the actual casejump and
2539 assert that we find only what's expected. */
2540 rtx whole_jump_insn = prev_nonnote_nondebug_insn (table);
2541 gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn));
2542 whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn);
2543 gcc_assert (whole_jump_insn != NULL_RTX
2544 && (JUMP_P (whole_jump_insn)
2545 || (TARGET_V32 && INSN_P (whole_jump_insn)
2546 && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE)));
2547 /* Get the pattern of the casejump, so we can extract the default label. */
2548 whole_jump_insn = PATTERN (whole_jump_insn);
2552 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2553 filled. We also output the offset word a little differently. */
2555 = (GET_CODE (whole_jump_insn) == SEQUENCE
2556 ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn);
2558 asm_fprintf (stream,
2559 "\t.word %LL%d-.%s\n",
2560 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2561 (parallel_jump, 0, 0),
2563 (TARGET_PDEBUG ? "; default" : ""));
2567 asm_fprintf (stream,
2568 "\t.word %LL%d-%LL%d%s\n",
2569 CODE_LABEL_NUMBER (XEXP
2571 (XEXP (XVECEXP (whole_jump_insn, 0, 0), 1),
2574 (TARGET_PDEBUG ? "; default" : ""));
2577 /* The TARGET_OPTION_OVERRIDE worker.
2578 As is the norm, this also parses -mfoo=bar type parameters. */
2581 cris_option_override (void)
2583 if (cris_max_stackframe_str)
2585 cris_max_stackframe = atoi (cris_max_stackframe_str);
2587 /* Do some sanity checking. */
2588 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2589 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2590 cris_max_stackframe, 0x20000000);
2593 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2594 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2595 cris_cpu_version = CRIS_CPU_SVINTO;
2596 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2597 cris_cpu_version = CRIS_CPU_ETRAX4;
2599 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2603 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2605 if (strcmp ("etrax4", cris_cpu_str) == 0)
2606 cris_cpu_version = 3;
2608 if (strcmp ("svinto", cris_cpu_str) == 0
2609 || strcmp ("etrax100", cris_cpu_str) == 0)
2610 cris_cpu_version = 8;
2612 if (strcmp ("ng", cris_cpu_str) == 0
2613 || strcmp ("etrax100lx", cris_cpu_str) == 0)
2614 cris_cpu_version = 10;
2616 if (cris_cpu_version < 0 || cris_cpu_version > 32)
2617 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2620 /* Set the target flags. */
2621 if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2622 target_flags |= MASK_ETRAX4_ADD;
2624 /* If this is Svinto or higher, align for 32 bit accesses. */
2625 if (cris_cpu_version >= CRIS_CPU_SVINTO)
2627 |= (MASK_SVINTO | MASK_ALIGN_BY_32
2628 | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2631 /* Note that we do not add new flags when it can be completely
2632 described with a macro that uses -mcpu=X. So
2633 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2639 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2641 if (strcmp ("etrax4", cris_tune_str) == 0)
2644 if (strcmp ("svinto", cris_tune_str) == 0
2645 || strcmp ("etrax100", cris_tune_str) == 0)
2648 if (strcmp ("ng", cris_tune_str) == 0
2649 || strcmp ("etrax100lx", cris_tune_str) == 0)
2652 if (cris_tune < 0 || cris_tune > 32)
2653 error ("unknown CRIS cpu version specification in -mtune= : %s",
2656 if (cris_tune >= CRIS_CPU_SVINTO)
2657 /* We have currently nothing more to tune than alignment for
2660 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2661 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2664 if (cris_cpu_version >= CRIS_CPU_V32)
2665 target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG);
2669 /* Use error rather than warning, so invalid use is easily
2670 detectable. Still change to the values we expect, to avoid
2674 error ("-fPIC and -fpic are not supported in this configuration");
2678 /* Turn off function CSE. We need to have the addresses reach the
2679 call expanders to get PLT-marked, as they could otherwise be
2680 compared against zero directly or indirectly. After visiting the
2681 call expanders they will then be cse:ed, as the call expanders
2682 force_reg the addresses, effectively forcing flag_no_function_cse
2684 flag_no_function_cse = 1;
2687 /* Set the per-function-data initializer. */
2688 init_machine_status = cris_init_machine_status;
2691 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2694 cris_asm_output_mi_thunk (FILE *stream,
2695 tree thunkdecl ATTRIBUTE_UNUSED,
2696 HOST_WIDE_INT delta,
2697 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2700 /* Make sure unwind info is emitted for the thunk if needed. */
2701 final_start_function (emit_barrier (), stream, 1);
2704 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2705 ADDITIVE_SIZE_MODIFIER (delta), delta,
2706 reg_names[CRIS_FIRST_ARG_REG]);
2708 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2709 ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2710 reg_names[CRIS_FIRST_ARG_REG]);
2714 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2716 name = (* targetm.strip_name_encoding) (name);
2720 fprintf (stream, "\tba ");
2721 assemble_name (stream, name);
2722 fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX);
2726 fprintf (stream, "add.d ");
2727 assemble_name (stream, name);
2728 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2733 fprintf (stream, "jump ");
2734 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2735 fprintf (stream, "\n");
2738 fprintf (stream, "\tnop\n");
2741 final_end_function ();
2744 /* Boilerplate emitted at start of file.
2746 NO_APP *only at file start* means faster assembly. It also means
2747 comments are not allowed. In some cases comments will be output
2748 for debugging purposes. Make sure they are allowed then. */
2750 cris_file_start (void)
2752 /* These expressions can vary at run time, so we cannot put
2753 them into TARGET_INITIALIZER. */
2754 targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2756 default_file_start ();
2759 /* Output that goes at the end of the file, similarly. */
2762 cris_file_end (void)
2764 /* For CRIS, the default is to assume *no* executable stack, so output
2765 an executable-stack-note only when needed. */
2766 if (TARGET_LINUX && trampolines_created)
2767 file_end_indicate_exec_stack ();
2770 /* Rename the function calls for integer multiply and divide. */
2772 cris_init_libfuncs (void)
2774 set_optab_libfunc (smul_optab, SImode, "__Mul");
2775 set_optab_libfunc (sdiv_optab, SImode, "__Div");
2776 set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2777 set_optab_libfunc (smod_optab, SImode, "__Mod");
2778 set_optab_libfunc (umod_optab, SImode, "__Umod");
2780 /* Atomic data being unaligned is unfortunately a reality.
2782 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS)
2784 set_optab_libfunc (sync_compare_and_swap_optab, SImode,
2785 "__cris_atcmpxchgr32");
2786 set_optab_libfunc (sync_compare_and_swap_optab, HImode,
2787 "__cris_atcmpxchgr16");
2791 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2795 cris_init_expanders (void)
2797 /* Nothing here at the moment. */
2800 /* Zero initialization is OK for all current fields. */
2802 static struct machine_function *
2803 cris_init_machine_status (void)
2805 return ggc_alloc_cleared_machine_function ();
2808 /* Split a 2 word move (DI or presumably DF) into component parts.
2809 Originally a copy of gen_split_move_double in m32r.c. */
2812 cris_split_movdx (rtx *operands)
2814 enum machine_mode mode = GET_MODE (operands[0]);
2815 rtx dest = operands[0];
2816 rtx src = operands[1];
2819 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2820 longer happen; after reload there are no SUBREGs any more, and we're
2821 only called after reload. */
2822 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2827 int dregno = REGNO (dest);
2829 /* Reg-to-reg copy. */
2832 int sregno = REGNO (src);
2834 int reverse = (dregno == sregno + 1);
2836 /* We normally copy the low-numbered register first. However, if
2837 the first register operand 0 is the same as the second register of
2838 operand 1, we must copy in the opposite order. */
2839 emit_insn (gen_rtx_SET (VOIDmode,
2840 operand_subword (dest, reverse, TRUE, mode),
2841 operand_subword (src, reverse, TRUE, mode)));
2843 emit_insn (gen_rtx_SET (VOIDmode,
2844 operand_subword (dest, !reverse, TRUE, mode),
2845 operand_subword (src, !reverse, TRUE, mode)));
2847 /* Constant-to-reg copy. */
2848 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
2851 split_double (src, &words[0], &words[1]);
2852 emit_insn (gen_rtx_SET (VOIDmode,
2853 operand_subword (dest, 0, TRUE, mode),
2856 emit_insn (gen_rtx_SET (VOIDmode,
2857 operand_subword (dest, 1, TRUE, mode),
2860 /* Mem-to-reg copy. */
2861 else if (MEM_P (src))
2863 /* If the high-address word is used in the address, we must load it
2864 last. Otherwise, load it first. */
2865 rtx addr = XEXP (src, 0);
2867 = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
2869 /* The original code implies that we can't do
2870 move.x [rN+],rM move.x [rN],rM+1
2871 when rN is dead, because of REG_NOTES damage. That is
2872 consistent with what I've seen, so don't try it.
2874 We have two different cases here; if the addr is POST_INC,
2875 just pass it through, otherwise add constants. */
2877 if (GET_CODE (addr) == POST_INC)
2882 /* Whenever we emit insns with post-incremented
2883 addresses ourselves, we must add a post-inc note
2885 mem = change_address (src, SImode, addr);
2887 = gen_rtx_SET (VOIDmode,
2888 operand_subword (dest, 0, TRUE, mode), mem);
2889 insn = emit_insn (insn);
2890 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2892 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2895 mem = copy_rtx (mem);
2897 = gen_rtx_SET (VOIDmode,
2898 operand_subword (dest, 1, TRUE, mode), mem);
2899 insn = emit_insn (insn);
2900 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2902 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2907 /* Make sure we don't get any other addresses with
2908 embedded postincrements. They should be stopped in
2909 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2911 if (side_effects_p (addr))
2912 fatal_insn ("unexpected side-effects in address", addr);
2914 emit_insn (gen_rtx_SET
2916 operand_subword (dest, reverse, TRUE, mode),
2919 plus_constant (Pmode, addr,
2920 reverse * UNITS_PER_WORD))));
2921 emit_insn (gen_rtx_SET
2923 operand_subword (dest, ! reverse, TRUE, mode),
2926 plus_constant (Pmode, addr,
2932 internal_error ("unknown src");
2934 /* Reg-to-mem copy or clear mem. */
2935 else if (MEM_P (dest)
2937 || src == const0_rtx
2938 || src == CONST0_RTX (DFmode)))
2940 rtx addr = XEXP (dest, 0);
2942 if (GET_CODE (addr) == POST_INC)
2947 /* Whenever we emit insns with post-incremented addresses
2948 ourselves, we must add a post-inc note manually. */
2949 mem = change_address (dest, SImode, addr);
2951 = gen_rtx_SET (VOIDmode,
2952 mem, operand_subword (src, 0, TRUE, mode));
2953 insn = emit_insn (insn);
2954 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2956 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2959 mem = copy_rtx (mem);
2961 = gen_rtx_SET (VOIDmode,
2963 operand_subword (src, 1, TRUE, mode));
2964 insn = emit_insn (insn);
2965 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2967 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2972 /* Make sure we don't get any other addresses with embedded
2973 postincrements. They should be stopped in
2974 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2975 if (side_effects_p (addr))
2976 fatal_insn ("unexpected side-effects in address", addr);
2978 emit_insn (gen_rtx_SET
2980 change_address (dest, SImode, addr),
2981 operand_subword (src, 0, TRUE, mode)));
2983 emit_insn (gen_rtx_SET
2985 change_address (dest, SImode,
2986 plus_constant (Pmode, addr,
2988 operand_subword (src, 1, TRUE, mode)));
2993 internal_error ("unknown dest");
3000 /* The expander for the prologue pattern name. */
3003 cris_expand_prologue (void)
3006 int size = get_frame_size ();
3007 /* Shorten the used name for readability. */
3008 int cfoa_size = crtl->outgoing_args_size;
3009 int last_movem_reg = -1;
3012 int return_address_on_stack = cris_return_address_on_stack ();
3013 int got_really_used = false;
3014 int n_movem_regs = 0;
3015 int pretend = crtl->args.pretend_args_size;
3017 /* Don't do anything if no prologues or epilogues are wanted. */
3018 if (!TARGET_PROLOGUE_EPILOGUE)
3021 CRIS_ASSERT (size >= 0);
3023 if (crtl->uses_pic_offset_table)
3025 /* A reference may have been optimized out (like the abort () in
3026 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3028 push_topmost_sequence ();
3030 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
3031 pop_topmost_sequence ();
3034 /* Align the size to what's best for the CPU model. */
3035 if (TARGET_STACK_ALIGN)
3036 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3040 /* See also cris_setup_incoming_varargs where
3041 cfun->machine->stdarg_regs is set. There are other setters of
3042 crtl->args.pretend_args_size than stdarg handling, like
3043 for an argument passed with parts in R13 and stack. We must
3044 not store R13 into the pretend-area for that case, as GCC does
3045 that itself. "Our" store would be marked as redundant and GCC
3046 will attempt to remove it, which will then be flagged as an
3047 internal error; trying to remove a frame-related insn. */
3048 int stdarg_regs = cfun->machine->stdarg_regs;
3050 framesize += pretend;
3052 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
3054 regno--, pretend -= 4, stdarg_regs--)
3056 insn = emit_insn (gen_rtx_SET (VOIDmode,
3058 plus_constant (Pmode,
3061 /* FIXME: When dwarf2 frame output and unless asynchronous
3062 exceptions, make dwarf2 bundle together all stack
3063 adjustments like it does for registers between stack
3065 RTX_FRAME_RELATED_P (insn) = 1;
3067 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3068 set_mem_alias_set (mem, get_varargs_alias_set ());
3069 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
3071 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3072 the value isn't restored, so we don't want to tell dwarf2
3073 that it's been stored to stack, else EH handling info would
3077 /* For other setters of crtl->args.pretend_args_size, we
3078 just adjust the stack by leaving the remaining size in
3079 "pretend", handled below. */
3082 /* Save SRP if not a leaf function. */
3083 if (return_address_on_stack)
3085 insn = emit_insn (gen_rtx_SET (VOIDmode,
3087 plus_constant (Pmode, stack_pointer_rtx,
3090 RTX_FRAME_RELATED_P (insn) = 1;
3092 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3093 set_mem_alias_set (mem, get_frame_alias_set ());
3094 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM));
3095 RTX_FRAME_RELATED_P (insn) = 1;
3099 /* Set up the frame pointer, if needed. */
3100 if (frame_pointer_needed)
3102 insn = emit_insn (gen_rtx_SET (VOIDmode,
3104 plus_constant (Pmode, stack_pointer_rtx,
3107 RTX_FRAME_RELATED_P (insn) = 1;
3109 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3110 set_mem_alias_set (mem, get_frame_alias_set ());
3111 insn = emit_move_insn (mem, frame_pointer_rtx);
3112 RTX_FRAME_RELATED_P (insn) = 1;
3114 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3115 RTX_FRAME_RELATED_P (insn) = 1;
3120 /* Between frame-pointer and saved registers lie the area for local
3121 variables. If we get here with "pretended" size remaining, count
3122 it into the general stack size. */
3125 /* Get a contiguous sequence of registers, starting with R0, that need
3127 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
3129 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3133 /* Check if movem may be used for registers so far. */
3134 if (regno == last_movem_reg + 1)
3135 /* Yes, update next expected register. */
3136 last_movem_reg = regno;
3139 /* We cannot use movem for all registers. We have to flush
3140 any movem:ed registers we got so far. */
3141 if (last_movem_reg != -1)
3144 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
3146 /* It is a win to use a side-effect assignment for
3147 64 <= size <= 128. But side-effect on movem was
3148 not usable for CRIS v0..3. Also only do it if
3149 side-effects insns are allowed. */
3150 if ((last_movem_reg + 1) * 4 + size >= 64
3151 && (last_movem_reg + 1) * 4 + size <= 128
3152 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
3153 && TARGET_SIDE_EFFECT_PREFIXES)
3156 = gen_rtx_MEM (SImode,
3157 plus_constant (Pmode, stack_pointer_rtx,
3158 -(n_saved * 4 + size)));
3159 set_mem_alias_set (mem, get_frame_alias_set ());
3161 = cris_emit_movem_store (mem, GEN_INT (n_saved),
3162 -(n_saved * 4 + size),
3168 = gen_rtx_SET (VOIDmode,
3170 plus_constant (Pmode, stack_pointer_rtx,
3171 -(n_saved * 4 + size)));
3172 insn = emit_insn (insn);
3173 RTX_FRAME_RELATED_P (insn) = 1;
3175 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3176 set_mem_alias_set (mem, get_frame_alias_set ());
3177 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3181 framesize += n_saved * 4 + size;
3182 last_movem_reg = -1;
3186 insn = emit_insn (gen_rtx_SET (VOIDmode,
3188 plus_constant (Pmode,
3191 RTX_FRAME_RELATED_P (insn) = 1;
3193 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3194 set_mem_alias_set (mem, get_frame_alias_set ());
3195 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
3196 RTX_FRAME_RELATED_P (insn) = 1;
3198 framesize += 4 + size;
3204 /* Check after, if we could movem all registers. This is the normal case. */
3205 if (last_movem_reg != -1)
3208 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
3210 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3211 do it if side-effects insns are allowed. */
3212 if ((last_movem_reg + 1) * 4 + size >= 64
3213 && (last_movem_reg + 1) * 4 + size <= 128
3214 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
3215 && TARGET_SIDE_EFFECT_PREFIXES)
3218 = gen_rtx_MEM (SImode,
3219 plus_constant (Pmode, stack_pointer_rtx,
3220 -(n_saved * 4 + size)));
3221 set_mem_alias_set (mem, get_frame_alias_set ());
3222 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3223 -(n_saved * 4 + size), true);
3228 = gen_rtx_SET (VOIDmode,
3230 plus_constant (Pmode, stack_pointer_rtx,
3231 -(n_saved * 4 + size)));
3232 insn = emit_insn (insn);
3233 RTX_FRAME_RELATED_P (insn) = 1;
3235 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3236 set_mem_alias_set (mem, get_frame_alias_set ());
3237 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
3240 framesize += n_saved * 4 + size;
3241 /* We have to put outgoing argument space after regs. */
3244 insn = emit_insn (gen_rtx_SET (VOIDmode,
3246 plus_constant (Pmode,
3249 RTX_FRAME_RELATED_P (insn) = 1;
3250 framesize += cfoa_size;
3253 else if ((size + cfoa_size) > 0)
3255 insn = emit_insn (gen_rtx_SET (VOIDmode,
3257 plus_constant (Pmode,
3259 -(cfoa_size + size))));
3260 RTX_FRAME_RELATED_P (insn) = 1;
3261 framesize += size + cfoa_size;
3264 /* Set up the PIC register, if it is used. */
3265 if (got_really_used)
3268 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
3269 emit_move_insn (pic_offset_table_rtx, got);
3271 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3272 follow exceptional paths and tries to delete the GOT load as
3273 unused, if it isn't used on the non-exceptional paths. Other
3274 ports have similar or other cover-ups, or plain bugs marking
3275 the GOT register load as maybe-dead. To see this, remove the
3276 line below and try libsupc++/vec.cc or a trivial
3277 "static void y (); void x () {try {y ();} catch (...) {}}". */
3278 emit_use (pic_offset_table_rtx);
3281 if (cris_max_stackframe && framesize > cris_max_stackframe)
3282 warning (0, "stackframe too big: %d bytes", framesize);
3285 /* The expander for the epilogue pattern. */
3288 cris_expand_epilogue (void)
3291 int size = get_frame_size ();
3292 int last_movem_reg = -1;
3293 int argspace_offset = crtl->outgoing_args_size;
3294 int pretend = crtl->args.pretend_args_size;
3296 bool return_address_on_stack = cris_return_address_on_stack ();
3297 /* A reference may have been optimized out
3298 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3299 so check that it's still used. */
3300 int got_really_used = false;
3301 int n_movem_regs = 0;
3303 if (!TARGET_PROLOGUE_EPILOGUE)
3306 if (crtl->uses_pic_offset_table)
3308 /* A reference may have been optimized out (like the abort () in
3309 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3311 push_topmost_sequence ();
3313 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
3314 pop_topmost_sequence ();
3317 /* Align byte count of stack frame. */
3318 if (TARGET_STACK_ALIGN)
3319 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3321 /* Check how many saved regs we can movem. They start at r0 and must
3324 regno < FIRST_PSEUDO_REGISTER;
3326 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3330 if (regno == last_movem_reg + 1)
3331 last_movem_reg = regno;
3336 /* If there was only one register that really needed to be saved
3337 through movem, don't use movem. */
3338 if (n_movem_regs == 1)
3339 last_movem_reg = -1;
3341 /* Now emit "normal" move insns for all regs higher than the movem
3343 for (regno = FIRST_PSEUDO_REGISTER - 1;
3344 regno > last_movem_reg;
3346 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3350 if (argspace_offset)
3352 /* There is an area for outgoing parameters located before
3353 the saved registers. We have to adjust for that. */
3354 emit_insn (gen_rtx_SET (VOIDmode,
3356 plus_constant (Pmode, stack_pointer_rtx,
3358 /* Make sure we only do this once. */
3359 argspace_offset = 0;
3362 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3363 stack_pointer_rtx));
3364 set_mem_alias_set (mem, get_frame_alias_set ());
3365 insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem);
3367 /* Whenever we emit insns with post-incremented addresses
3368 ourselves, we must add a post-inc note manually. */
3370 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3373 /* If we have any movem-restore, do it now. */
3374 if (last_movem_reg != -1)
3378 if (argspace_offset)
3380 emit_insn (gen_rtx_SET (VOIDmode,
3382 plus_constant (Pmode, stack_pointer_rtx,
3384 argspace_offset = 0;
3387 mem = gen_rtx_MEM (SImode,
3388 gen_rtx_POST_INC (SImode, stack_pointer_rtx));
3389 set_mem_alias_set (mem, get_frame_alias_set ());
3391 = emit_insn (cris_gen_movem_load (mem,
3392 GEN_INT (last_movem_reg + 1), 0));
3393 /* Whenever we emit insns with post-incremented addresses
3394 ourselves, we must add a post-inc note manually. */
3395 if (side_effects_p (PATTERN (insn)))
3397 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3400 /* If we don't clobber all of the allocated stack area (we've already
3401 deallocated saved registers), GCC might want to schedule loads from
3402 the stack to *after* the stack-pointer restore, which introduces an
3403 interrupt race condition. This happened for the initial-value
3404 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3405 other failure for that test). It also happened for the stack slot
3406 for the return value in (one version of)
3407 linux/fs/dcache.c:__d_lookup, at least with "-O2
3408 -fno-omit-frame-pointer". */
3410 /* Restore frame pointer if necessary. */
3411 if (frame_pointer_needed)
3415 emit_insn (gen_cris_frame_deallocated_barrier ());
3417 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
3418 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3419 stack_pointer_rtx));
3420 set_mem_alias_set (mem, get_frame_alias_set ());
3421 insn = emit_move_insn (frame_pointer_rtx, mem);
3423 /* Whenever we emit insns with post-incremented addresses
3424 ourselves, we must add a post-inc note manually. */
3426 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3428 else if ((size + argspace_offset) != 0)
3430 emit_insn (gen_cris_frame_deallocated_barrier ());
3432 /* If there was no frame-pointer to restore sp from, we must
3433 explicitly deallocate local variables. */
3435 /* Handle space for outgoing parameters that hasn't been handled
3437 size += argspace_offset;
3439 emit_insn (gen_rtx_SET (VOIDmode,
3441 plus_constant (Pmode, stack_pointer_rtx, size)));
3444 /* If this function has no pushed register parameters
3445 (stdargs/varargs), and if it is not a leaf function, then we have
3446 the return address on the stack. */
3447 if (return_address_on_stack && pretend == 0)
3449 if (TARGET_V32 || crtl->calls_eh_return)
3453 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
3454 mem = gen_rtx_MEM (SImode,
3455 gen_rtx_POST_INC (SImode,
3456 stack_pointer_rtx));
3457 set_mem_alias_set (mem, get_frame_alias_set ());
3458 insn = emit_move_insn (srpreg, mem);
3460 /* Whenever we emit insns with post-incremented addresses
3461 ourselves, we must add a post-inc note manually. */
3463 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3465 if (crtl->calls_eh_return)
3466 emit_insn (gen_addsi3 (stack_pointer_rtx,
3468 gen_rtx_raw_REG (SImode,
3469 CRIS_STACKADJ_REG)));
3470 cris_expand_return (false);
3473 cris_expand_return (true);
3478 /* If we pushed some register parameters, then adjust the stack for
3482 /* If SRP is stored on the way, we need to restore it first. */
3483 if (return_address_on_stack)
3486 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
3489 mem = gen_rtx_MEM (SImode,
3490 gen_rtx_POST_INC (SImode,
3491 stack_pointer_rtx));
3492 set_mem_alias_set (mem, get_frame_alias_set ());
3493 insn = emit_move_insn (srpreg, mem);
3495 /* Whenever we emit insns with post-incremented addresses
3496 ourselves, we must add a post-inc note manually. */
3498 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3501 emit_insn (gen_rtx_SET (VOIDmode,
3503 plus_constant (Pmode, stack_pointer_rtx,
3507 /* Perform the "physical" unwinding that the EH machinery calculated. */
3508 if (crtl->calls_eh_return)
3509 emit_insn (gen_addsi3 (stack_pointer_rtx,
3511 gen_rtx_raw_REG (SImode,
3512 CRIS_STACKADJ_REG)));
3513 cris_expand_return (false);
3516 /* Worker function for generating movem from mem for load_multiple. */
3519 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
3521 int nregs = INTVAL (nregs_rtx);
3525 rtx srcreg = XEXP (src, 0);
3526 unsigned int regno = nregs - 1;
3535 if (GET_CODE (srcreg) == POST_INC)
3536 srcreg = XEXP (srcreg, 0);
3538 CRIS_ASSERT (REG_P (srcreg));
3540 /* Don't use movem for just one insn. The insns are equivalent except
3541 for the pipeline hazard (on v32); movem does not forward the loaded
3542 registers so there's a three cycles penalty for their use. */
3544 return gen_movsi (gen_rtx_REG (SImode, 0), src);
3546 vec = rtvec_alloc (nprefix + nregs
3547 + (GET_CODE (XEXP (src, 0)) == POST_INC));
3549 if (GET_CODE (XEXP (src, 0)) == POST_INC)
3551 RTVEC_ELT (vec, nprefix + 1)
3552 = gen_rtx_SET (VOIDmode, srcreg,
3553 plus_constant (Pmode, srcreg, nregs * 4));
3557 src = replace_equiv_address (src, srcreg);
3558 RTVEC_ELT (vec, nprefix)
3559 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src);
3562 for (i = 1; i < nregs; i++, eltno++)
3564 RTVEC_ELT (vec, nprefix + eltno)
3565 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno),
3566 adjust_address_nv (src, SImode, i * 4));
3570 return gen_rtx_PARALLEL (VOIDmode, vec);
3573 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3574 are added that the dwarf2 machinery understands. */
3577 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3580 int nregs = INTVAL (nregs_rtx);
3585 rtx destreg = XEXP (dest, 0);
3586 unsigned int regno = nregs - 1;
3595 if (GET_CODE (destreg) == POST_INC)
3596 increment += nregs * 4;
3598 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3599 destreg = XEXP (destreg, 0);
3601 CRIS_ASSERT (REG_P (destreg));
3603 /* Don't use movem for just one insn. The insns are equivalent except
3604 for the pipeline hazard (on v32); movem does not forward the loaded
3605 registers so there's a three cycles penalty for use. */
3608 rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0));
3612 insn = emit_insn (mov);
3614 RTX_FRAME_RELATED_P (insn) = 1;
3618 /* If there was a request for a side-effect, create the ordinary
3620 vec = rtvec_alloc (2);
3622 RTVEC_ELT (vec, 0) = mov;
3623 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg,
3624 plus_constant (Pmode, destreg,
3628 RTX_FRAME_RELATED_P (mov) = 1;
3629 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3634 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3636 = gen_rtx_SET (VOIDmode,
3637 replace_equiv_address (dest,
3638 plus_constant (Pmode, destreg,
3640 gen_rtx_REG (SImode, regno));
3643 /* The dwarf2 info wants this mark on each component in a parallel
3644 that's part of the prologue (though it's optional on the first
3647 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3652 = gen_rtx_SET (VOIDmode, destreg,
3653 plus_constant (Pmode, destreg,
3655 ? increment : nregs * 4));
3659 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3661 /* Don't call adjust_address_nv on a post-incremented address if
3663 if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3664 dest = replace_equiv_address (dest, destreg);
3667 for (i = 1; i < nregs; i++, eltno++)
3669 RTVEC_ELT (vec, eltno)
3670 = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4),
3671 gen_rtx_REG (SImode, regno));
3673 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3678 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3680 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3681 we need to keep the stack adjustment separate, after the
3682 MEM-setters. Else the stack-adjustment in the second component of
3683 the parallel would be mishandled; the offsets for the SETs that
3684 follow it would be wrong. We prepare for this by adding a
3685 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3686 followed by the increment. Note that we have FRAME_RELATED_P on
3687 all the SETs, including the original stack adjustment SET in the
3693 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3694 XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0));
3695 for (i = 1; i < nregs; i++)
3697 = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1));
3698 XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1));
3699 add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq);
3702 RTX_FRAME_RELATED_P (insn) = 1;
3708 /* Worker function for expanding the address for PIC function calls. */
3711 cris_expand_pic_call_address (rtx *opp)
3715 gcc_assert (MEM_P (op));
3718 /* It might be that code can be generated that jumps to 0 (or to a
3719 specific address). Don't die on that. (There is a
3721 if (CONSTANT_ADDRESS_P (op) && !CONST_INT_P (op))
3723 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op);
3725 CRIS_ASSERT (can_create_pseudo_p ());
3727 /* For local symbols (non-PLT), just get the plain symbol
3728 reference into a register. For symbols that can be PLT, make
3730 if (t == cris_rel_symbol)
3732 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3733 into a register caused performance regression for 3.2.1,
3734 observable in __floatdidf and elsewhere in libgcc. */
3737 rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op);
3738 HOST_WIDE_INT offs = get_integer_term (op);
3740 /* We can't get calls to sym+N, N integer, can we? */
3741 gcc_assert (offs == 0);
3743 op = gen_rtx_CONST (Pmode,
3744 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
3745 CRIS_UNSPEC_PCREL));
3748 op = force_reg (Pmode, op);
3750 else if (t == cris_got_symbol)
3752 if (TARGET_AVOID_GOTPLT)
3754 /* Change a "jsr sym" into (allocate register rM, rO)
3755 "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM"
3756 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3757 "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))"
3760 gcc_assert (can_create_pseudo_p ());
3761 crtl->uses_pic_offset_table = 1;
3762 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3764 ? CRIS_UNSPEC_PLT_PCREL
3765 : CRIS_UNSPEC_PLT_GOTREL);
3766 tem = gen_rtx_CONST (Pmode, tem);
3771 rm = gen_reg_rtx (Pmode);
3772 emit_move_insn (rm, tem);
3773 ro = gen_reg_rtx (Pmode);
3774 if (expand_binop (Pmode, add_optab, rm,
3775 pic_offset_table_rtx,
3776 ro, 0, OPTAB_LIB_WIDEN) != ro)
3777 internal_error ("expand_binop failed in movsi got");
3783 /* Change a "jsr sym" into (allocate register rM, rO)
3784 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3785 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3786 marked as not trapping and not aliasing. No "move.d
3787 [rO],rP" as that would invite to re-use of a value
3788 that should not be reused. FIXME: Need a peephole2
3789 for cases when this is cse:d from the call, to change
3790 back to just get the PLT entry address, so we don't
3791 resolve the same symbol over and over (the memory
3792 access of the PLTGOT isn't constant). */
3793 rtx tem, mem, rm, ro;
3795 gcc_assert (can_create_pseudo_p ());
3796 crtl->uses_pic_offset_table = 1;
3797 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3798 CRIS_UNSPEC_PLTGOTREAD);
3799 rm = gen_reg_rtx (Pmode);
3800 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3801 ro = gen_reg_rtx (Pmode);
3802 if (expand_binop (Pmode, add_optab, rm,
3803 pic_offset_table_rtx,
3804 ro, 0, OPTAB_LIB_WIDEN) != ro)
3805 internal_error ("expand_binop failed in movsi got");
3806 mem = gen_rtx_MEM (Pmode, ro);
3808 /* This MEM doesn't alias anything. Whether it aliases
3809 other same symbols is unimportant. */
3810 set_mem_alias_set (mem, new_alias_set ());
3811 MEM_NOTRAP_P (mem) = 1;
3816 /* Can't possibly get a GOT-needing-fixup for a function-call,
3818 fatal_insn ("unidentifiable call op", op);
3820 *opp = replace_equiv_address (*opp, op);
3824 /* Make sure operands are in the right order for an addsi3 insn as
3825 generated by a define_split. Nothing but REG_P as the first
3826 operand is recognized by addsi3 after reload. OPERANDS contains
3827 the operands, with the first at OPERANDS[N] and the second at
3831 cris_order_for_addsi3 (rtx *operands, int n)
3833 if (!REG_P (operands[n]))
3835 rtx tem = operands[n];
3836 operands[n] = operands[n + 1];
3837 operands[n + 1] = tem;
3841 /* Use from within code, from e.g. PRINT_OPERAND and
3842 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3843 different things depending on whether code operand or constant is
3847 cris_output_addr_const (FILE *file, rtx x)
3850 output_addr_const (file, x);
3854 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3857 cris_asm_output_symbol_ref (FILE *file, rtx x)
3859 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3861 if (flag_pic && in_code > 0)
3863 const char *origstr = XSTR (x, 0);
3865 str = (* targetm.strip_name_encoding) (origstr);
3866 assemble_name (file, str);
3869 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3870 output_operand_lossage ("PIC register isn't set up");
3873 assemble_name (file, XSTR (x, 0));
3876 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3879 cris_asm_output_label_ref (FILE *file, char *buf)
3881 if (flag_pic && in_code > 0)
3883 assemble_name (file, buf);
3886 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3887 internal_error ("emitting PIC operand, but PIC register "
3891 assemble_name (file, buf);
3894 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3897 cris_output_addr_const_extra (FILE *file, rtx xconst)
3899 switch (GET_CODE (xconst))
3904 x = XVECEXP (xconst, 0, 0);
3905 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3906 || GET_CODE (x) == LABEL_REF
3907 || GET_CODE (x) == CONST);
3908 output_addr_const (file, x);
3909 switch (XINT (xconst, 1))
3911 case CRIS_UNSPEC_PCREL:
3912 /* We only get this with -fpic/PIC to tell it apart from an
3913 invalid symbol. We can't tell here, but it should only
3914 be the operand of a call or movsi. */
3915 gcc_assert (TARGET_V32 && flag_pic);
3918 case CRIS_UNSPEC_PLT_PCREL:
3919 gcc_assert (TARGET_V32);
3920 fprintf (file, ":PLT");
3923 case CRIS_UNSPEC_PLT_GOTREL:
3924 gcc_assert (!TARGET_V32);
3925 fprintf (file, ":PLTG");
3928 case CRIS_UNSPEC_GOTREL:
3929 gcc_assert (!TARGET_V32);
3930 fprintf (file, ":GOTOFF");
3933 case CRIS_UNSPEC_GOTREAD:
3935 fprintf (file, ":GOT16");
3937 fprintf (file, ":GOT");
3940 case CRIS_UNSPEC_PLTGOTREAD:
3942 fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3944 fprintf (file, CRIS_GOTPLT_SUFFIX);
3957 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3960 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3961 int incoming ATTRIBUTE_UNUSED)
3963 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
3966 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3969 cris_setup_incoming_varargs (cumulative_args_t ca_v,
3970 enum machine_mode mode ATTRIBUTE_UNUSED,
3971 tree type ATTRIBUTE_UNUSED,
3972 int *pretend_arg_size,
3975 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
3977 if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
3979 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
3980 cfun->machine->stdarg_regs = stdarg_regs;
3981 *pretend_arg_size = stdarg_regs * 4;
3985 fprintf (asm_out_file,
3986 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3987 ca->regs, *pretend_arg_size, second_time);
3990 /* Return true if TYPE must be passed by invisible reference.
3991 For cris, we pass <= 8 bytes by value, others by reference. */
3994 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
3995 enum machine_mode mode, const_tree type,
3996 bool named ATTRIBUTE_UNUSED)
3998 return (targetm.calls.must_pass_in_stack (mode, type)
3999 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
4002 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4003 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4004 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4007 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
4008 enum machine_mode mode,
4009 int *punsignedp ATTRIBUTE_UNUSED,
4010 const_tree fntype ATTRIBUTE_UNUSED,
4013 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4014 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4015 Maybe pointless as of now, but let's keep the old behavior. */
4016 if (for_return == 1)
4018 return CRIS_PROMOTED_MODE (mode, *punsignedp, type);
4021 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4025 cris_function_value(const_tree type,
4026 const_tree func ATTRIBUTE_UNUSED,
4027 bool outgoing ATTRIBUTE_UNUSED)
4029 return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG);
4032 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4036 cris_libcall_value (enum machine_mode mode,
4037 const_rtx fun ATTRIBUTE_UNUSED)
4039 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG);
4042 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4046 cris_function_value_regno_p (const unsigned int regno)
4048 return (regno == CRIS_FIRST_ARG_REG);
4052 cris_arg_partial_bytes (cumulative_args_t ca, enum machine_mode mode,
4053 tree type, bool named ATTRIBUTE_UNUSED)
4055 if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1
4056 && !targetm.calls.must_pass_in_stack (mode, type)
4057 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
4058 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
4059 return UNITS_PER_WORD;
4065 cris_function_arg_1 (cumulative_args_t ca_v,
4066 enum machine_mode mode ATTRIBUTE_UNUSED,
4067 const_tree type ATTRIBUTE_UNUSED,
4068 bool named, bool incoming)
4070 const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4072 if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS)
4073 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs);
4078 /* Worker function for TARGET_FUNCTION_ARG.
4079 The void_type_node is sent as a "closing" call. */
4082 cris_function_arg (cumulative_args_t ca, enum machine_mode mode,
4083 const_tree type, bool named)
4085 return cris_function_arg_1 (ca, mode, type, named, false);
4088 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4090 The differences between this and the previous, is that this one checks
4091 that an argument is named, since incoming stdarg/varargs arguments are
4092 pushed onto the stack, and we don't have to check against the "closing"
4093 void_type_node TYPE parameter. */
4096 cris_function_incoming_arg (cumulative_args_t ca, enum machine_mode mode,
4097 const_tree type, bool named)
4099 return cris_function_arg_1 (ca, mode, type, named, true);
4102 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4105 cris_function_arg_advance (cumulative_args_t ca_v, enum machine_mode mode,
4106 const_tree type, bool named ATTRIBUTE_UNUSED)
4108 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4110 ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4;
4113 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
4116 cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers)
4118 HARD_REG_SET mof_set;
4122 CLEAR_HARD_REG_SET (mof_set);
4123 SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM);
4125 /* For the time being, all asms clobber condition codes. Revisit when
4126 there's a reasonable use for inputs/outputs that mention condition
4129 = tree_cons (NULL_TREE,
4130 build_string (strlen (reg_names[CRIS_CC0_REGNUM]),
4131 reg_names[CRIS_CC0_REGNUM]),
4134 for (t = outputs; t != NULL; t = TREE_CHAIN (t))
4136 tree val = TREE_VALUE (t);
4138 /* The constraint letter for the singleton register class of MOF
4139 is 'h'. If it's mentioned in the constraints, the asm is
4140 MOF-aware and adding it to the clobbers would cause it to have
4141 impossible constraints. */
4142 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
4144 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
4148 for (t = inputs; t != NULL; t = TREE_CHAIN (t))
4150 tree val = TREE_VALUE (t);
4152 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
4154 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
4158 return tree_cons (NULL_TREE,
4159 build_string (strlen (reg_names[CRIS_MOF_REGNUM]),
4160 reg_names[CRIS_MOF_REGNUM]),
4164 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4166 Really only needed if the stack frame has variable length (alloca
4167 or variable sized local arguments (GNU C extension). See PR39499 and
4168 PR38609 for the reason this isn't just 0. */
4171 cris_frame_pointer_required (void)
4173 return !crtl->sp_is_unchanging;
4176 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4178 This looks too complicated, and it is. I assigned r7 to be the
4179 static chain register, but it is call-saved, so we have to save it,
4180 and come back to restore it after the call, so we have to save srp...
4181 Anyway, trampolines are rare enough that we can cope with this
4182 somewhat lack of elegance.
4183 (Do not be tempted to "straighten up" whitespace in the asms; the
4184 assembler #NO_APP state mandates strict spacing). */
4185 /* ??? See the i386 regparm=3 implementation that pushes the static
4186 chain value to the stack in the trampoline, and uses a call-saved
4187 register when called directly. */
4190 cris_asm_trampoline_template (FILE *f)
4194 /* This normally-unused nop insn acts as an instruction to
4195 the simulator to flush its instruction cache. None of
4196 the other instructions in the trampoline template suits
4197 as a trigger for V32. The pc-relative addressing mode
4198 works nicely as a trigger for V10.
4199 FIXME: Have specific V32 template (possibly avoiding the
4200 use of a special instruction). */
4201 fprintf (f, "\tclearf x\n");
4202 /* We have to use a register as an intermediate, choosing
4203 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4204 so we can use it for address indirection and jsr target. */
4205 fprintf (f, "\tmove $r1,$mof\n");
4207 fprintf (f, "\tmove.d 0,$r1\n");
4208 fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]);
4209 fprintf (f, "\taddq 6,$r1\n");
4210 fprintf (f, "\tmove $mof,[$r1]\n");
4211 fprintf (f, "\taddq 6,$r1\n");
4212 fprintf (f, "\tmove $srp,[$r1]\n");
4214 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4216 fprintf (f, "\tmove.d 0,$r1\n");
4217 fprintf (f, "\tjsr $r1\n");
4218 fprintf (f, "\tsetf\n");
4220 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4222 fprintf (f, "\tmove.d 0,$r1\n");
4224 fprintf (f, "\tmove.d 0,$r9\n");
4225 fprintf (f, "\tjump $r9\n");
4226 fprintf (f, "\tsetf\n");
4230 fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]);
4231 fprintf (f, "\tmove $srp,[$pc+22]\n");
4232 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4233 fprintf (f, "\tjsr 0\n");
4234 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4235 fprintf (f, "\tjump 0\n");
4239 /* Implement TARGET_TRAMPOLINE_INIT. */
4242 cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
4244 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4245 rtx tramp = XEXP (m_tramp, 0);
4248 emit_block_move (m_tramp, assemble_trampoline_template (),
4249 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
4253 mem = adjust_address (m_tramp, SImode, 6);
4254 emit_move_insn (mem, plus_constant (Pmode, tramp, 38));
4255 mem = adjust_address (m_tramp, SImode, 22);
4256 emit_move_insn (mem, chain_value);
4257 mem = adjust_address (m_tramp, SImode, 28);
4258 emit_move_insn (mem, fnaddr);
4262 mem = adjust_address (m_tramp, SImode, 10);
4263 emit_move_insn (mem, chain_value);
4264 mem = adjust_address (m_tramp, SImode, 16);
4265 emit_move_insn (mem, fnaddr);
4268 /* Note that there is no need to do anything with the cache for
4269 sake of a trampoline. */
4274 /* Various small functions to replace macros. Only called from a
4275 debugger. They might collide with gcc functions or system functions,
4276 so only emit them when '#if 1' above. */
4278 enum rtx_code Get_code (rtx);
4283 return GET_CODE (x);
4286 const char *Get_mode (rtx);
4291 return GET_MODE_NAME (GET_MODE (x));
4294 rtx Xexp (rtx, int);
4302 rtx Xvecexp (rtx, int, int);
4305 Xvecexp (rtx x, int n, int m)
4307 return XVECEXP (x, n, m);
4310 int Get_rtx_len (rtx);
4315 return GET_RTX_LENGTH (GET_CODE (x));
4318 /* Use upper-case to distinguish from local variables that are sometimes
4319 called next_insn and prev_insn. */
4321 rtx Next_insn (rtx);
4324 Next_insn (rtx insn)
4326 return NEXT_INSN (insn);
4329 rtx Prev_insn (rtx);
4332 Prev_insn (rtx insn)
4334 return PREV_INSN (insn);
4338 #include "gt-cris.h"
4342 * eval: (c-set-style "gnu")
4343 * indent-tabs-mode: t