1 /* Definitions of target machine for GNU compiler. Convex version.
2 Copyright (C) 1988, 1994, 1995, 1996, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Standard GCC variables that we reference. */
25 extern int target_flags;
27 /* Convex machine-specific flags
28 -mc1 target instruction set, libraries, scheduling
33 -margcount use standard calling sequence, with arg count word
34 -mno-argcount don't push arg count, depend on symbol table
35 -margcount-nop place arg count in a nop instruction (faster than push)
36 -mvolatile-cache use data cache for volatile mem refs (default)
37 -mvolatile-nocache bypass data cache for volatile mem refs
38 -mlong32 cc- and libc-compatible 32-bit longs
42 /* Macro to define tables used to set -mXXX flags.
43 This is a list in braces of pairs in braces,
44 each pair being { "NAME", VALUE }
45 where VALUE is the bits to set or minus the bits to clear.
46 An empty string NAME is used to identify the default VALUE. */
48 #ifndef TARGET_DEFAULT
49 #define TARGET_DEFAULT 0
52 #define TARGET_SWITCHES \
53 { { "c1", 001, N_("Generate code for c1") }, \
54 { "c2", 002, N_("Generate code for c2") }, \
55 { "c32", 004, N_("Generate code for c32") }, \
56 { "c34", 010, N_("Generate code for c34") }, \
57 { "c38", 020, N_("Generate code for c34") }, \
59 N_("Use standard calling sequence, with arg count word")}, \
60 { "argcount-nop", 0200, \
61 N_("Place arg count in a nop instruction (faster than push)") }, \
62 { "no-argcount", -0300, \
63 N_("Don't push arg count, depend on symbol table") }, \
64 { "volatile-cache", -0400, \
65 N_("Use data cache for volatile mem refs (default)") }, \
66 { "no-volatile-cache", 0400, \
67 N_("Don't use data cache for volatile mem refs") }, \
68 { "volatile-nocache", 0400, \
69 N_("Bypass data cache for volatile mem refs") }, \
70 { "long64", 01000, N_("Use 64-bit longs") }, \
71 { "long32", -01000, N_("Use cc- and libc-compatible 32-bit longs")},\
72 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
74 /* Macros used in the machine description to test the flags. */
76 #define TARGET_C1 (target_cpu == 0)
77 #define TARGET_C2 (target_cpu == 1)
78 #define TARGET_C34 (target_cpu == 2)
79 #define TARGET_C38 (target_cpu == 3)
80 #define TARGET_ARGCOUNT (target_flags & 0100)
81 #define TARGET_ARGCOUNT_NOP (target_flags & 0200)
82 #define TARGET_LONG64 (target_flags & 01000)
83 #define TARGET_VOLATILE_NOCACHE (target_flags & 0400)
85 #define OVERRIDE_OPTIONS \
88 if ((target_flags & 077) != ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 077)) \
89 target_flags &= ~ (TARGET_DEFAULT | TARGET_CPU_DEFAULT); \
90 if (target_flags & 001) \
92 else if (target_flags & 006) \
94 else if (target_flags & 010) \
96 else if (target_flags & 020) \
100 /* Names to predefine in the preprocessor for this target machine. */
102 #define CPP_PREDEFINES "-Dconvex -Dunix -Asystem=unix -Acpu=convex -Amachine=convex"
104 /* Print subsidiary information on the compiler version in use. */
106 #define TARGET_VERSION fprintf (stderr, " (convex)");
108 /* Target-dependent specs.
109 Some libraries come in c1 and c2+ versions; use the appropriate ones.
110 Make a target-dependent __convex_cxx__ define to relay the target cpu
111 to the program being compiled. */
113 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1
120 "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \
121 %{mc2:-D__convex_c2__} \
122 %{mc32:-D__convex_c32__} \
123 %{mc34:-D__convex_c34__} \
124 %{mc38:-D__convex_c38__} \
125 %{fno-builtin:-D__NO_INLINE} \
126 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
129 -D__stdc__ -D_LONGLONG \
130 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
131 %{!ansi:-D_POSIX_SOURCE} \
132 %{!ansi:-D_CONVEX_SOURCE}"
137 "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \
138 %{mc2:-D__convex_c2__} \
139 %{mc32:-D__convex_c32__} \
140 %{mc34:-D__convex_c34__} \
141 %{mc38:-D__convex_c38__} \
142 %{fno-builtin:-D__NO_INLINE} \
143 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
146 -D__stdc__ -D_LONGLONG \
147 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
148 %{!ansi:-D_POSIX_SOURCE} \
149 %{!ansi:-D_CONVEX_SOURCE}"
154 "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-lC1%{p:_p}%{pg:_p}}}}} \
155 %{mc2:-lC2%{p:_p}%{pg:_p}} \
156 %{mc32:-lC2%{p:_p}%{pg:_p}} \
157 %{mc34:-lC2%{p:_p}%{pg:_p}} \
158 %{mc38:-lC2%{p:_p}%{pg:_p}} \
163 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 2
170 "%{mc1:-D__convex_c1__} \
171 %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \
172 %{mc32:-D__convex_c32__} \
173 %{mc34:-D__convex_c34__} \
174 %{mc38:-D__convex_c38__} \
175 %{fno-builtin:-D__NO_INLINE} \
176 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
179 -D__stdc__ -D_LONGLONG \
180 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
181 %{!ansi:-D_POSIX_SOURCE} \
182 %{!ansi:-D_CONVEX_SOURCE}"
187 "%{mc1:-D__convex_c1__} \
188 %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \
189 %{mc32:-D__convex_c32__} \
190 %{mc34:-D__convex_c34__} \
191 %{mc38:-D__convex_c38__} \
192 %{fno-builtin:-D__NO_INLINE} \
193 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
196 -D__stdc__ -D_LONGLONG \
197 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
198 %{!ansi:-D_POSIX_SOURCE} \
199 %{!ansi:-D_CONVEX_SOURCE}"
204 "%{mc1:-lC1%{p:_p}%{pg:_p}} \
205 %{!mc1:%{!mc32:%{!mc34:%{!mc38:-lC2%{p:_p}%{pg:_p}}}}} \
206 %{mc32:-lC2%{p:_p}%{pg:_p}} \
207 %{mc34:-lC2%{p:_p}%{pg:_p}} \
208 %{mc38:-lC2%{p:_p}%{pg:_p}} \
213 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 4
220 "%{mc1:-D__convex_c1__} \
221 %{mc2:-D__convex_c2__} \
222 %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \
223 %{mc34:-D__convex_c34__} \
224 %{mc38:-D__convex_c38__} \
225 %{fno-builtin:-D__NO_INLINE} \
226 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
229 -D__stdc__ -D_LONGLONG \
230 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
231 %{!ansi:-D_POSIX_SOURCE} \
232 %{!ansi:-D_CONVEX_SOURCE}"
237 "%{mc1:-D__convex_c1__} \
238 %{mc2:-D__convex_c2__} \
239 %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \
240 %{mc34:-D__convex_c34__} \
241 %{mc38:-D__convex_c38__} \
242 %{fno-builtin:-D__NO_INLINE} \
243 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
246 -D__stdc__ -D_LONGLONG \
247 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
248 %{!ansi:-D_POSIX_SOURCE} \
249 %{!ansi:-D_CONVEX_SOURCE}"
254 "%{mc1:-lC1%{p:_p}%{pg:_p}} \
255 %{mc2:-lC2%{p:_p}%{pg:_p}} \
256 %{!mc1:%{!mc2:%{!mc34:%{!mc38:-lC2%{p:_p}%{pg:_p}}}}} \
257 %{mc34:-lC2%{p:_p}%{pg:_p}} \
258 %{mc38:-lC2%{p:_p}%{pg:_p}} \
263 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 010
270 "%{mc1:-D__convex_c1__} \
271 %{mc2:-D__convex_c2__} \
272 %{mc32:-D__convex_c32__} \
273 %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \
274 %{mc38:-D__convex_c38__} \
275 %{fno-builtin:-D__NO_INLINE} \
276 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
279 -D__stdc__ -D_LONGLONG \
280 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
281 %{!ansi:-D_POSIX_SOURCE} \
282 %{!ansi:-D_CONVEX_SOURCE}"
287 "%{mc1:-D__convex_c1__} \
288 %{mc2:-D__convex_c2__} \
289 %{mc32:-D__convex_c32__} \
290 %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \
291 %{mc38:-D__convex_c38__} \
292 %{fno-builtin:-D__NO_INLINE} \
293 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
296 -D__stdc__ -D_LONGLONG \
297 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
298 %{!ansi:-D_POSIX_SOURCE} \
299 %{!ansi:-D_CONVEX_SOURCE}"
304 "%{mc1:-lC1%{p:_p}%{pg:_p}} \
305 %{mc2:-lC2%{p:_p}%{pg:_p}} \
306 %{mc32:-lC2%{p:_p}%{pg:_p}} \
307 %{!mc1:%{!mc2:%{!mc32:%{!mc38:-lC2%{p:_p}%{pg:_p}}}}} \
308 %{mc38:-lC2%{p:_p}%{pg:_p}} \
313 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 020
320 "%{mc1:-D__convex_c1__} \
321 %{mc2:-D__convex_c2__} \
322 %{mc32:-D__convex_c32__} \
323 %{mc34:-D__convex_c34__} \
324 %{fno-builtin:-D__NO_INLINE} \
325 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
327 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \
329 -D__stdc__ -D_LONGLONG \
330 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
331 %{!ansi:-D_POSIX_SOURCE} \
332 %{!ansi:-D_CONVEX_SOURCE}"
337 "%{mc1:-D__convex_c1__} \
338 %{mc2:-D__convex_c2__} \
339 %{mc32:-D__convex_c32__} \
340 %{mc34:-D__convex_c34__} \
341 %{fno-builtin:-D__NO_INLINE} \
342 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
344 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \
346 -D__stdc__ -D_LONGLONG \
347 -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
348 %{!ansi:-D_POSIX_SOURCE} \
349 %{!ansi:-D_CONVEX_SOURCE}"
354 "%{mc1:-lC1%{p:_p}%{pg:_p}} \
355 %{mc2:-lC2%{p:_p}%{pg:_p}} \
356 %{mc32:-lC2%{p:_p}%{pg:_p}} \
357 %{mc34:-lC2%{p:_p}%{pg:_p}} \
358 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-lC2%{p:_p}%{pg:_p}}}}} \
367 #define ASM_SPEC "-fi"
375 -A_use_libc_sema=___ap$use_libc_sema \
376 %-A___gcc_cleanup=___ap$do_registered_functions \
379 #define STARTFILE_SPEC \
380 "%{!pg:%{!p:/usr/lib/crt/crt0.o}} \
381 %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \
382 %{pg:/usr/lib/crt/gcrt0.o} \
383 /usr/lib/crt/fpmode_i.o"
389 #define ASM_SPEC "-fn"
397 -A_use_libc_sema=___ap$use_libc_sema \
398 -A___gcc_cleanup=___ap$do_registered_functions \
401 #define STARTFILE_SPEC \
402 "%{!pg:%{!p:/usr/lib/crt/crt0.o}} \
403 %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \
404 %{pg:/usr/lib/crt/gcrt0.o}"
408 /* Use /path/libgcc.a instead of -lgcc, makes bootstrap work more smoothly. */
410 #define LINK_LIBGCC_SPECIAL_1
412 /* Since IEEE support was added to gcc, most things seem to like it
413 better if we disable exceptions and check afterward for infinity. */
417 #define REAL_VALUE_ISNAN(x) 0
418 #define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0x7ff0) == 0x7ff0)
420 #define REAL_VALUE_ISNAN(x) 0
421 #define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0xfff0) == 0x8000)
425 /* Target machine storage layout */
427 /* Define this if most significant bit is lowest numbered
428 in instructions that operate on numbered bit-fields. */
429 #define BITS_BIG_ENDIAN 1
431 /* Define this if most significant byte of a word is the lowest numbered. */
432 #define BYTES_BIG_ENDIAN 1
434 /* Define this if most significant word of a multiword number is numbered. */
435 #define WORDS_BIG_ENDIAN 1
437 /* Width in bits of a "word", which is the contents of a machine register.
438 Note that this is not necessarily the width of data type `int';
439 if using 16-bit ints on a 68000, this would still be 32.
440 But on a machine with 16-bit registers, this would be 16. */
441 #define BITS_PER_WORD 64
443 /* Width of a word, in units (bytes). */
444 #define UNITS_PER_WORD 8
446 /* Width in bits of a pointer.
447 See also the macro `Pmode' defined below. */
448 #define POINTER_SIZE 32
450 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
451 #define PARM_BOUNDARY 32
453 /* Boundary (in *bits*) on which stack pointer should be aligned. */
454 #define STACK_BOUNDARY 64
456 /* Allocation boundary (in *bits*) for the code of a function. */
457 #define FUNCTION_BOUNDARY 16
459 /* Alignment of field after `int : 0' in a structure. */
460 #define EMPTY_FIELD_BOUNDARY 32
462 /* Every structure's size must be a multiple of this. */
463 #define STRUCTURE_SIZE_BOUNDARY 8
465 /* A bitfield declared as `int' forces `int' alignment for the struct. */
466 #define PCC_BITFIELD_TYPE_MATTERS 1
468 /* No data type wants to be aligned rounder than this. */
469 /* beware of doubles in structs -- 64 is incompatible with cc */
470 #define BIGGEST_ALIGNMENT 32
472 /* Set this nonzero if move instructions will actually fail to work
473 when given unaligned data. */
474 #define STRICT_ALIGNMENT 0
476 /* Define sizes of basic C types to conform to ordinary usage -- these
477 types depend on BITS_PER_WORD otherwise. */
478 #define SHORT_TYPE_SIZE 16
479 #define INT_TYPE_SIZE 32
480 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
481 #define LONG_LONG_TYPE_SIZE 64
482 #define FLOAT_TYPE_SIZE 32
483 #define DOUBLE_TYPE_SIZE 64
484 #define LONG_DOUBLE_TYPE_SIZE 64
485 #define MAX_LONG_TYPE_SIZE 64
487 /* Declare the standard types used by builtins to match convex stddef.h --
488 with int rather than long. */
490 #define SIZE_TYPE "unsigned int"
491 #define PTRDIFF_TYPE "int"
493 /* Standard register usage. */
495 /* Number of actual hardware registers.
496 The hardware registers are assigned numbers for the compiler
497 from 0 to just below FIRST_PSEUDO_REGISTER.
498 All registers that the compiler knows about must be given numbers,
499 even those that are not normally considered general registers. */
500 #define FIRST_PSEUDO_REGISTER 16
502 /* 1 for registers that have pervasive standard uses
503 and are not available for the register allocator.
504 For Convex, these are AP, FP, and SP. */
505 #define FIXED_REGISTERS \
506 { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 }
508 /* 1 for registers not available across function calls.
509 These must include the FIXED_REGISTERS and also any
510 registers that can be used without being saved.
511 The latter must include the registers where values are returned
512 and the register where structure-value addresses are passed.
513 Aside from that, you can include as many other registers as you like. */
514 #define CALL_USED_REGISTERS \
515 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
517 /* List the order in which to allocate registers. Each register must be
518 listed once, even those in FIXED_REGISTERS.
519 For Convex, put S0 (the return register) last. */
520 #define REG_ALLOC_ORDER \
521 { 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 0, 8, 14, 15 }
523 /* Return number of consecutive hard regs needed starting at reg REGNO
524 to hold something of mode MODE.
525 This is ordinarily the length in words of a value of mode MODE
526 but can be less for certain modes in special long registers. */
527 #define HARD_REGNO_NREGS(REGNO, MODE) \
528 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
530 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
531 On Convex, S registers can hold any type, A registers any nonfloat. */
532 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
534 || (GET_MODE_SIZE (MODE) <= 4 && (MODE) != SFmode))
536 /* Value is 1 if it is a good idea to tie two pseudo registers
537 when one has mode MODE1 and one has mode MODE2.
538 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
539 for any hard reg, then this must be 0 for correct output. */
540 #define MODES_TIEABLE_P(MODE1, MODE2) \
541 ((GET_MODE_SIZE (MODE1) <= 4 && (MODE1) != SFmode) \
542 == (GET_MODE_SIZE (MODE2) <= 4 && (MODE2) != SFmode))
544 /* Specify the registers used for certain standard purposes.
545 The values of these macros are register numbers. */
550 /* Register to use for pushing function arguments. */
551 #define STACK_POINTER_REGNUM A0_REGNUM
553 /* Base register for access to local variables of the function. */
554 #define FRAME_POINTER_REGNUM (A0_REGNUM + 7)
556 /* Value should be nonzero if functions must have frame pointers.
557 Zero means the frame pointer need not be set up (and parms
558 may be accessed via the stack pointer) in functions that seem suitable.
559 This is computed in `reload', in reload1.c. */
560 #define FRAME_POINTER_REQUIRED 1
562 /* Base register for access to arguments of the function. */
563 #define ARG_POINTER_REGNUM (A0_REGNUM + 6)
565 /* Register in which static-chain is passed to a function.
566 Use S0, not an A reg, because this rare use would otherwise prevent
567 an A reg from being available to global-alloc across calls. */
568 #define STATIC_CHAIN_REGNUM S0_REGNUM
570 /* Register in which address to store a structure value
571 is passed to a function. */
572 #define STRUCT_VALUE_REGNUM (A0_REGNUM + 1)
574 /* Define the classes of registers for register constraints in the
575 machine description. Also define ranges of constants.
577 One of the classes must always be named ALL_REGS and include all hard regs.
578 If there is more than one class, another class must be named NO_REGS
579 and contain no registers.
581 The name GENERAL_REGS must be the name of a class (or an alias for
582 another name such as ALL_REGS). This is the class of registers
583 that is allowed by "g" or "r" in a register constraint.
584 Also, registers outside this class are allocated only when
585 instructions express preferences for them.
587 The classes must be numbered in nondecreasing order; that is,
588 a larger-numbered class must never be contained completely
589 in a smaller-numbered class.
591 For any two classes, it is very desirable that there be another
592 class that represents their union. */
594 /* Convex has classes A (address) and S (scalar).
595 A is further divided into SP_REGS (stack pointer) and INDEX_REGS.
596 SI_REGS is S_REGS + INDEX_REGS -- all the regs except SP. */
599 NO_REGS, S_REGS, INDEX_REGS, SP_REGS, A_REGS, SI_REGS,
600 ALL_REGS, LIM_REG_CLASSES
603 #define N_REG_CLASSES (int) LIM_REG_CLASSES
605 /* Since GENERAL_REGS is the same class as ALL_REGS,
606 don't give it a different class number; just make it an alias. */
608 #define GENERAL_REGS ALL_REGS
610 /* Give names of register classes as strings for dump file. */
612 #define REG_CLASS_NAMES \
613 {"NO_REGS", "S_REGS", "INDEX_REGS", "SP_REGS", "A_REGS", "SI_REGS", \
616 /* Define which registers fit in which classes.
617 This is an initializer for a vector of HARD_REG_SET
618 of length N_REG_CLASSES. */
620 #define REG_CLASS_CONTENTS \
621 { {0}, {0x00ff}, {0xfe00}, {0x0100}, {0xff00}, {0xfeff}, {0xffff} }
623 /* The same information, inverted:
624 Return the class number of the smallest class containing
625 reg number REGNO. This could be a conditional expression
626 or could index an array. */
628 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[REGNO])
630 #define S_REGNO_P(REGNO) ((unsigned)((REGNO) - S0_REGNUM) < 8)
631 #define A_REGNO_P(REGNO) ((unsigned)((REGNO) - A0_REGNUM) < 8)
633 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
634 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
636 /* The class value for index registers, and the one for base regs. */
638 #define INDEX_REG_CLASS INDEX_REGS
639 #define BASE_REG_CLASS INDEX_REGS
641 /* Get reg_class from a letter such as appears in the machine description. */
643 d => S_REGS ('s' is taken)
644 A => INDEX_REGS (i.e., A_REGS except sp) */
646 #define REG_CLASS_FROM_LETTER(C) \
647 reg_class_from_letter[(unsigned char) (C)]
649 /* The letters I, J, K, L and M in a register constraint string
650 can be used to stand for particular ranges of immediate operands.
651 This macro defines what the ranges are.
652 C is the letter, and VALUE is a constant value.
653 Return 1 if VALUE is in the range specified by C. */
654 /* 'I' is used to pass any CONST_INT and reject any CONST_DOUBLE.
655 CONST_DOUBLE integers are handled by G and H constraint chars. */
657 #define CONST_OK_FOR_LETTER_P(VALUE, C) 1
659 /* Similar, but for floating constants, and defining letters G and H.
660 Here VALUE is the CONST_DOUBLE rtx itself. */
662 value usable in ld.d (low word 0) or ld.l (high word all sign) */
664 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
665 (((C) == 'G' && LD_D_P (VALUE)) || \
666 ((C) == 'H' && LD_L_P (VALUE)) || \
669 #define LD_D_P(X) (const_double_low_int (X) == 0)
671 #define LD_L_P(X) (const_double_low_int (X) >= 0 \
672 ? const_double_high_int (X) == 0 \
673 : const_double_high_int (X) == -1)
675 /* Optional extra constraints for this machine.
676 For Convex, 'Q' means that OP is a volatile MEM.
677 For volatile scalars, we use instructions that bypass the data cache. */
679 #define EXTRA_CONSTRAINT(OP, C) \
680 ((C) == 'Q' ? (GET_CODE (OP) == MEM && MEM_VOLATILE_P (OP) \
681 && ! TARGET_C1 && TARGET_VOLATILE_NOCACHE) \
684 /* Given an rtx X being reloaded into a reg required to be
685 in class CLASS, return the class of reg to actually use.
686 In general this is just CLASS; but on some machines
687 in some cases it is preferable to use a more restrictive class. */
689 /* Put 2-word constants that can't be immediate operands into memory. */
691 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
692 ((GET_CODE (X) != CONST_DOUBLE \
693 || GET_MODE (X) == SFmode \
694 || LD_L_P (X) || LD_D_P (X)) ? (CLASS) : NO_REGS)
696 /* Return the maximum number of consecutive registers
697 needed to represent mode MODE in a register of class CLASS. */
698 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) + 7) / 8)
700 /* Stack layout; function entry, exit and calling. */
702 /* Define this if pushing a word on the stack
703 makes the stack pointer a smaller address. */
704 #define STACK_GROWS_DOWNWARD
706 /* Define this if the nominal address of the stack frame
707 is at the high-address end of the local variables;
708 that is, each additional local variable allocated
709 goes at a more negative offset in the frame. */
710 #define FRAME_GROWS_DOWNWARD
712 /* Define this if should default to -fcaller-saves. */
713 #define DEFAULT_CALLER_SAVES
715 /* Offset within stack frame to start allocating local variables at.
716 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
717 first local allocated. Otherwise, it is the offset to the BEGINNING
718 of the first local allocated. */
719 #define STARTING_FRAME_OFFSET 0
721 /* If we generate an insn to push BYTES bytes,
722 this says how many the stack pointer really advances by. */
723 #define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
725 /* Offset of first parameter from the argument pointer register value. */
726 #define FIRST_PARM_OFFSET(FNDECL) 0
728 /* Value is the number of bytes of arguments automatically
729 popped when returning from a subroutine call.
730 FUNDECL is the declaration node of the function (as a tree),
731 FUNTYPE is the data type of the function (as a tree),
732 or for a library call it is an identifier node for the subroutine name.
733 SIZE is the number of bytes of arguments passed on the stack. */
735 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
737 /* Define how to find the value returned by a function.
738 VALTYPE is the data type of the value (as a tree).
739 If the precise function being called is known, FUNC is its FUNCTION_DECL;
740 otherwise, FUNC is 0. */
742 #define FUNCTION_VALUE(VALTYPE, FUNC) \
743 gen_rtx (REG, TYPE_MODE (VALTYPE), S0_REGNUM)
745 /* Define how to find the value returned by a library function
746 assuming the value has mode MODE. */
748 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, S0_REGNUM)
750 /* Define this if PCC uses the nonreentrant convention for returning
751 structure and union values. */
753 #define PCC_STATIC_STRUCT_RETURN
755 /* 1 if N is a possible register number for a function value.
756 On the Convex, S0 is the only register thus used. */
758 #define FUNCTION_VALUE_REGNO_P(N) ((N) == S0_REGNUM)
760 /* 1 if N is a possible register number for function argument passing. */
762 #define FUNCTION_ARG_REGNO_P(N) 0
764 /* Define a data type for recording info about an argument list
765 during the scan of that argument list. This data type should
766 hold all necessary information about the function itself
767 and about the args processed so far, enough to enable macros
768 such as FUNCTION_ARG to determine where the next arg should go. */
769 /* On convex, simply count the arguments in case TARGET_ARGCOUNT is set. */
771 #define CUMULATIVE_ARGS int
773 /* Initialize a variable CUM of type CUMULATIVE_ARGS
774 for a call to a function whose data type is FNTYPE.
775 For a library call, FNTYPE is 0. */
777 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
780 /* Update the data in CUM to advance over an argument
781 of mode MODE and data type TYPE.
782 (TYPE is null for libcalls where that information may not be available.) */
784 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
787 /* Define where to put the arguments to a function.
788 Value is zero to push the argument on the stack,
789 or a hard register in which to store the argument.
791 MODE is the argument's machine mode.
792 TYPE is the data type of the argument (as a tree).
793 This is null for libcalls where that information may
795 CUM is a variable of type CUMULATIVE_ARGS which gives info about
796 the preceding args and about the function being called.
797 NAMED is nonzero if this argument is a named parameter
798 (otherwise it is an extra parameter matching an ellipsis).
800 Convex: all args go on the stack. But return the arg count
801 as the "next arg register" to be passed to gen_call. */
803 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
804 ((MODE) == VOIDmode ? GEN_INT ((CUM)) : 0)
806 /* Output assembler code for a block containing the constant parts
807 of a trampoline, leaving space for the variable parts. */
809 /* On convex, the code for a trampoline is
813 #define TRAMPOLINE_TEMPLATE(FILE) \
815 fprintf (FILE, "\tld.w #69696969,s0\n"); \
816 fprintf (FILE, "\tjmp 52525252\n"); \
819 /* Length in units of the trampoline for entering a nested function. */
821 #define TRAMPOLINE_SIZE 12
823 /* Emit RTL insns to initialize the variable parts of a trampoline.
824 FNADDR is an RTX for the address of the function's pure code.
825 CXT is an RTX for the static chain value for the function. */
827 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
829 emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 2)), CXT); \
830 emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 8)), FNADDR); \
831 emit_call_insn (gen_call_pop (gen_rtx (MEM, QImode, \
832 gen_rtx (SYMBOL_REF, Pmode, \
833 "__enable_execute_stack")), \
834 const0_rtx, const0_rtx, const0_rtx)); \
837 /* Output assembler code to FILE to increment profiler label # LABELNO
838 for profiling a function entry. */
840 #define FUNCTION_PROFILER(FILE, LABELNO) \
841 fprintf (FILE, "\tldea LP%d,a1\n\tcallq mcount\n", (LABELNO));
843 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
844 the stack pointer does not matter. The value is tested only in
845 functions that have frame pointers.
846 No definition is equivalent to always zero. */
848 #define EXIT_IGNORE_STACK 1
850 /* Store in the variable DEPTH the initial difference between the
851 frame pointer reg contents and the stack pointer reg contents,
852 as of the start of the function body. This depends on the layout
853 of the fixed parts of the stack frame and on how registers are saved. */
854 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
855 { (DEPTH) = (get_frame_size () + 7) & -8; }
857 /* Addressing modes, and classification of registers for them. */
859 /* #define HAVE_POST_INCREMENT 0 */
860 /* #define HAVE_POST_DECREMENT 0 */
862 /* #define HAVE_PRE_DECREMENT 0 */
863 /* #define HAVE_PRE_INCREMENT 0 */
865 /* Macros to check register numbers against specific register classes. */
867 /* These assume that REGNO is a hard or pseudo reg number.
868 They give nonzero only if REGNO is a hard reg of the suitable class
869 or a pseudo reg currently allocated to a suitable hard reg.
870 Since they use reg_renumber, they are safe only once reg_renumber
871 has been allocated, which happens in local-alloc.c. */
873 #define REGNO_OK_FOR_INDEX_P(regno) \
874 ((regno) <= LAST_VIRTUAL_REGISTER \
875 ? regno_ok_for_index_p[regno] \
876 : regno_ok_for_index_p[reg_renumber[regno]])
878 #define REGNO_OK_FOR_BASE_P(regno) REGNO_OK_FOR_INDEX_P (regno)
880 /* Maximum number of registers that can appear in a valid memory address. */
882 #define MAX_REGS_PER_ADDRESS 1
884 /* 1 if X is an rtx for a constant that is a valid address. */
886 #define CONSTANT_ADDRESS_P(X) \
887 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
888 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
889 || GET_CODE (X) == HIGH)
891 /* Nonzero if the constant value X is a legitimate general operand.
892 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
894 /* For convex, bounce 2-word constants that can't be immediate operands. */
896 #define LEGITIMATE_CONSTANT_P(X) \
897 (GET_CODE (X) != CONST_DOUBLE \
898 || GET_MODE (X) == SFmode \
899 || LD_L_P (X) || LD_D_P (X))
901 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
902 and check its validity for a certain class.
903 We have two alternate definitions for each of them.
904 The usual definition accepts all pseudo regs; the other rejects
905 them unless they have been allocated suitable hard regs.
906 The symbol REG_OK_STRICT causes the latter definition to be used.
908 Most source files want to accept pseudo regs in the hope that
909 they will get allocated to the class that the insn wants them to be in.
910 Source files for reload pass need to be strict.
911 After reload, it makes no difference, since pseudo regs have
912 been eliminated by then. */
914 #ifndef REG_OK_STRICT
916 /* Nonzero if X is a hard reg that can be used as an index
917 or if it is a pseudo reg. */
918 #define REG_OK_FOR_INDEX_P(X) \
919 (REGNO (X) > LAST_VIRTUAL_REGISTER || regno_ok_for_index_p[REGNO (X)])
921 /* Nonzero if X is a hard reg that can be used as a base reg
922 or if it is a pseudo reg. */
923 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
927 /* Nonzero if X is a hard reg that can be used as an index. */
928 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
930 /* Nonzero if X is a hard reg that can be used as a base reg. */
931 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
935 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
936 that is a valid memory address for an instruction.
937 The MODE argument is the machine mode for the MEM expression
938 that wants to use this address.
940 For Convex, valid addresses are
941 indirectable or (MEM indirectable)
942 where indirectable is
943 const, reg, (PLUS reg const)
945 We don't use indirection since with insn scheduling, load + indexing
948 /* 1 if X is an address that we could indirect through. */
949 #define INDIRECTABLE_ADDRESS_P(X) \
950 (CONSTANT_ADDRESS_P (X) \
951 || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
952 || (GET_CODE (X) == PLUS \
953 && GET_CODE (XEXP (X, 0)) == REG \
954 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
955 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
956 || (GET_CODE (X) == PLUS \
957 && GET_CODE (XEXP (X, 1)) == REG \
958 && REG_OK_FOR_BASE_P (XEXP (X, 1)) \
959 && CONSTANT_ADDRESS_P (XEXP (X, 0))))
961 /* Go to ADDR if X is a valid address. */
962 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
963 { register rtx xfoob = (X); \
964 if (INDIRECTABLE_ADDRESS_P (xfoob)) \
966 if (GET_CODE (xfoob) == PRE_DEC && XEXP (xfoob, 0) == stack_pointer_rtx) \
970 /* Try machine-dependent ways of modifying an illegitimate address
971 to be legitimate. If we find one, return the new, valid address.
972 This macro is used in only one place: `memory_address' in explow.c.
974 OLDX is the address as it was before break_out_memory_refs was called.
975 In some cases it is useful to look at this to decide what needs to be done.
977 MODE and WIN are passed so that this macro can use
978 GO_IF_LEGITIMATE_ADDRESS.
980 It is always safe for this macro to do nothing. It exists to recognize
981 opportunities to optimize the output.
983 For Convex, nothing needs to be done. */
985 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
987 /* Go to LABEL if ADDR (a legitimate address expression)
988 has an effect that depends on the machine mode it is used for. */
990 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
992 /* Specify the machine mode that this machine uses
993 for the index in the tablejump instruction. */
994 #define CASE_VECTOR_MODE SImode
996 /* Define as C expression which evaluates to nonzero if the tablejump
997 instruction expects the table to contain offsets from the address of the
999 Do not define this if the table should contain absolute addresses. */
1000 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1002 /* Define this if the case instruction drops through after the table
1003 when the index is out of range. Don't define it if the case insn
1004 jumps to the default label instead. */
1005 /* #define CASE_DROPS_THROUGH */
1007 /* Define this as 1 if `char' should by default be signed; else as 0. */
1008 #define DEFAULT_SIGNED_CHAR 1
1010 /* This flag, if defined, says the same insns that convert to a signed fixnum
1011 also convert validly to an unsigned one. */
1012 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1014 /* Max number of bytes we can move from memory to memory
1015 in one reasonably fast instruction. */
1018 /* Nonzero if access to memory by bytes is slow and undesirable. */
1019 #define SLOW_BYTE_ACCESS (! TARGET_C2)
1021 /* Define if shifts truncate the shift count
1022 which implies one can omit a sign-extension or zero-extension
1023 of a shift count. */
1024 /* #define SHIFT_COUNT_TRUNCATED */
1026 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1027 is done just by pretending it is already truncated. */
1028 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1030 /* On Convex, it is as good to call a constant function address as to
1031 call an address kept in a register. */
1032 #define NO_FUNCTION_CSE
1034 /* When a prototype says `char' or `short', really pass an `int'. */
1035 #define PROMOTE_PROTOTYPES 1
1037 /* Specify the machine mode that pointers have.
1038 After generation of rtl, the compiler makes no further distinction
1039 between pointers and any other objects of this machine mode. */
1040 #define Pmode SImode
1042 /* A function address in a call instruction
1043 is a byte address (for indexing purposes)
1044 so give the MEM rtx a byte's mode. */
1045 #define FUNCTION_MODE QImode
1047 /* Compute the cost of computing a constant rtl expression RTX
1048 whose rtx-code is CODE. The body of this macro is a portion
1049 of a switch statement. If the code is computed here,
1050 return it with a return statement. Otherwise, break from the switch. */
1052 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1057 case CONST_DOUBLE: \
1060 /* Provide the costs of a rtl expression. This is in the body of a
1063 #define RTX_COSTS(RTX,CODE,OUTER_CODE) \
1065 if (GET_CODE (XEXP (RTX, 0)) == REG \
1066 && REG_POINTER (XEXP (RTX, 0)) \
1067 && GET_CODE (XEXP (RTX, 1)) == CONST_INT) \
1071 return 4 * (char) (0x03060403 >> target_cpu * 8); \
1075 return 4 * (char) (0x03010403 >> target_cpu * 8); \
1079 /* Compute the cost of an address. This is meant to approximate the size
1080 and/or execution delay of an insn using that address. If the cost is
1081 approximated by the RTL complexity, including CONST_COSTS above, as
1082 is usually the case for CISC machines, this macro should not be defined.
1083 For aggressively RISCy machines, only one insn format is allowed, so
1084 this macro should be a constant. The value of this macro only matters
1085 for valid addresses. */
1087 #define ADDRESS_COST(RTX) 0
1089 /* Specify the cost of a branch insn; roughly the number of extra insns that
1090 should be added to avoid a branch. */
1092 #define BRANCH_COST 0
1094 /* Convex uses VAX or IEEE floats.
1095 Follow the host format. */
1096 #define TARGET_FLOAT_FORMAT HOST_FLOAT_FORMAT
1098 /* But must prevent real.c from constructing VAX dfloats */
1099 #define REAL_VALUE_ATOF(X,S) atof (X)
1101 /* Check a `double' value for validity for a particular machine mode. */
1102 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1103 (OVERFLOW = check_float_value (MODE, &D, OVERFLOW))
1105 /* Tell final.c how to eliminate redundant test instructions. */
1107 /* Here we define machine-dependent flags and fields in cc_status
1108 (see `conditions.h'). No extra ones are needed for convex. */
1110 /* Store in cc_status the expressions
1111 that the condition codes will describe
1112 after execution of an instruction whose pattern is EXP.
1113 Do not alter them if the instruction would not alter the cc's. */
1115 #define NOTICE_UPDATE_CC(EXP,INSN) {}
1117 /* Control the assembler format that we output. */
1119 /* Output at beginning of assembler file. */
1122 #define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode ieee\n")
1124 #define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode native\n")
1127 /* Output to assembler file text saying following lines
1128 may contain character constants, extra white space, comments, etc. */
1130 #define ASM_APP_ON ";APP\n"
1132 /* Output to assembler file text saying following lines
1133 no longer contain unusual constructs. */
1135 #define ASM_APP_OFF ";NO_APP\n"
1137 /* Alignment with Convex's assembler goes like this:
1138 .text can be .aligned up to a halfword.
1139 .data and .bss can be .aligned up to a longword.
1140 .lcomm is not supported, explicit declarations in .bss must be used instead.
1141 We get alignment for word and longword .text data by conventionally
1142 using .text 2 for word-aligned data and .text 3 for longword-aligned
1143 data. This requires that the data's size be a multiple of its alignment,
1144 which seems to be always true. */
1146 /* Output before read-only data. */
1148 #define TEXT_SECTION_ASM_OP (current_section_is_text = 1, "\t.text")
1150 /* Output before writable data. */
1152 #define DATA_SECTION_ASM_OP (current_section_is_text = 0, "\t.data")
1154 /* Output before uninitialized data. */
1156 #define BSS_SECTION_ASM_OP (current_section_is_text = 0, "\t.bss")
1158 /* This is how to output an assembler line
1159 that says to advance the location counter
1160 to a multiple of 2**LOG bytes. */
1162 #define ASM_OUTPUT_ALIGN(FILE,LOG) do { \
1163 if (current_section_is_text && (LOG) > 1) \
1164 fprintf (FILE, ".text %d\n", LOG); \
1165 else if (current_section_is_text) \
1166 fprintf (FILE, ".text\n.align %d\n", 1 << (LOG)); \
1168 fprintf (FILE, ".align %d\n", 1 << (LOG)); } while (0)
1170 /* How to refer to registers in assembler output.
1171 This sequence is indexed by compiler's hard-register-number (see above). */
1173 #define REGISTER_NAMES \
1175 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
1176 "sp", "a1", "a2", "a3", "a4", "a5", "ap", "fp", \
1179 /* This is BSD, so it wants DBX format. */
1181 #define DBX_DEBUGGING_INFO
1183 /* Do not break .stabs pseudos into continuations. */
1185 #define DBX_CONTIN_LENGTH 0
1187 /* This is the char to use for continuation (in case we need to turn
1188 continuation back on). */
1190 #define DBX_CONTIN_CHAR '?'
1192 /* Don't use stab extensions until GDB v4 port is available for convex. */
1194 #define DEFAULT_GDB_EXTENSIONS 0
1195 #define DBX_NO_XREFS
1197 /* This is how to output the definition of a user-level label named NAME,
1198 such as the label on a static function or variable NAME. */
1200 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1201 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1203 /* This is how to output a command to make the user-level label named NAME
1204 defined for reference from other files. */
1206 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1207 do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1209 /* The prefix to add to user-visible assembler symbols. */
1211 #define USER_LABEL_PREFIX "_"
1213 /* This is how to output an internal numbered label where
1214 PREFIX is the class of label and NUM is the number within the class. */
1216 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1217 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1219 /* Put case tables in .text 2, where they will be word-aligned */
1221 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
1222 ASM_OUTPUT_ALIGN (FILE, 2); \
1223 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM)
1225 #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \
1226 ASM_OUTPUT_ALIGN (FILE, 1)
1228 /* This is how to store into the string LABEL
1229 the symbol_ref name of an internal numbered label where
1230 PREFIX is the class of label and NUM is the number within the class.
1231 This is suitable for output with `assemble_name'. */
1233 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1234 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1236 /* This is how to output a string */
1238 #define ASM_OUTPUT_ASCII(FILE,STR,SIZE) do { \
1239 size_t i, limit = (SIZE); \
1240 fprintf ((FILE), "\tds.b \""); \
1241 for (i = 0; i < limit; i++) { \
1242 register int c = (STR)[i] & 0377; \
1243 if (c >= ' ' && c < 0177 && c != '\\' && c != '"') \
1246 fprintf ((FILE), "\\%03o", c);} \
1247 fprintf ((FILE), "\"\n");} while (0)
1249 /* This is how to output an insn to push a register on the stack.
1250 It need not be very fast code. */
1252 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1253 fprintf (FILE, "\tpsh.%c %s\n", \
1254 S_REGNO_P (REGNO) ? 'l' : 'w', \
1257 /* This is how to output an insn to pop a register from the stack.
1258 It need not be very fast code. */
1260 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1261 fprintf (FILE, "\tpop.%c %s\n", \
1262 S_REGNO_P (REGNO) ? 'l' : 'w', \
1265 /* This is how to output an element of a case-vector that is absolute. */
1267 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1268 fprintf (FILE, "\tds.w L%d\n", VALUE)
1270 /* This is how to output an element of a case-vector that is relative.
1271 (not used on Convex) */
1273 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1274 fprintf (FILE, "\tds.w L%d-L%d\n", VALUE, REL)
1276 /* This is how to output an assembler line
1277 that says to advance the location counter by SIZE bytes. */
1279 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1280 fprintf (FILE, "\tds.b %u(0)\n", (SIZE))
1282 /* This says how to output an assembler line
1283 to define a global common symbol. */
1285 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1286 ( fputs (".comm ", (FILE)), \
1287 assemble_name ((FILE), (NAME)), \
1288 fprintf ((FILE), ",%u\n", (ROUNDED)))
1290 /* This says how to output an assembler line
1291 to define a local common symbol. */
1293 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1295 assemble_name ((FILE), (NAME)), \
1296 fprintf ((FILE), ":\tbs.b %u\n", (ROUNDED)))
1298 /* Store in OUTPUT a string (made with alloca) containing
1299 an assembler-name for a local static variable named NAME.
1300 LABELNO is an integer which is different for each call. */
1302 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1303 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1304 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1306 /* Output an arg count before function entries. */
1308 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1309 asm_declare_function_name (FILE, NAME, DECL)
1311 /* Print an instruction operand X on file FILE.
1312 CODE is the code from the %-spec that requested printing this operand;
1313 if `%z3' was used to print operand 3, then CODE is 'z'. */
1315 #define PRINT_OPERAND(FILE, X, CODE) \
1316 print_operand (FILE, X, CODE)
1318 /* Print a memory operand whose address is X, on file FILE. */
1320 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1321 print_operand_address (FILE, ADDR)
1323 /* Do not put out GNU stabs for constructors and destructors.
1326 #define FASCIST_ASSEMBLER
1328 /* __gcc_cleanup is loader-aliased to __ap$do_registered_functions if we
1329 are linking against standard libc. */
1333 extern void __gcc_cleanup (); \
1334 if (__gcc_cleanup != _cleanup) \
1339 /* Header for convex.c.
1340 Here at the end so we can use types defined above. */
1342 extern int target_cpu;
1343 extern int current_section_is_text;
1344 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1345 extern enum reg_class reg_class_from_letter[256];
1346 extern char regno_ok_for_index_p_base[];
1347 #define regno_ok_for_index_p (regno_ok_for_index_p_base + 1)
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