1 ;; Machine description for GNU compiler,
2 ;; for ATMEL AVR micro controllers.
3 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
4 ;; 2009, 2010 Free Software Foundation, Inc.
5 ;; Contributed by Denis Chertykov (chertykov@gmail.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; Special characters after '%':
24 ;; A No effect (add 0).
25 ;; B Add 1 to REG number, MEM address or CONST_INT.
28 ;; j Branch condition.
29 ;; k Reverse branch condition.
30 ;;..m..Constant Direct Data memory address.
31 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
32 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
33 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
34 ;;..x..Constant Direct Program memory address.
35 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
36 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
45 (TMP_REGNO 0) ; temporary register r0
46 (ZERO_REGNO 1) ; zero register r1
52 (define_c_enum "unspec"
60 (define_c_enum "unspecv"
61 [UNSPECV_PROLOGUE_SAVES
62 UNSPECV_EPILOGUE_RESTORES
63 UNSPECV_WRITE_SP_IRQ_ON
64 UNSPECV_WRITE_SP_IRQ_OFF
74 (include "predicates.md")
75 (include "constraints.md")
77 ;; Condition code settings.
78 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
79 (const_string "none"))
81 (define_attr "type" "branch,branch1,arith,xcall"
82 (const_string "arith"))
84 (define_attr "mcu_have_movw" "yes,no"
85 (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
87 (const_string "no"))))
89 (define_attr "mcu_mega" "yes,no"
90 (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
92 (const_string "no"))))
95 ;; The size of instructions in bytes.
96 ;; XXX may depend from "cc"
98 (define_attr "length" ""
99 (cond [(eq_attr "type" "branch")
100 (if_then_else (and (ge (minus (pc) (match_dup 0))
102 (le (minus (pc) (match_dup 0))
105 (if_then_else (and (ge (minus (pc) (match_dup 0))
107 (le (minus (pc) (match_dup 0))
111 (eq_attr "type" "branch1")
112 (if_then_else (and (ge (minus (pc) (match_dup 0))
114 (le (minus (pc) (match_dup 0))
117 (if_then_else (and (ge (minus (pc) (match_dup 0))
119 (le (minus (pc) (match_dup 0))
123 (eq_attr "type" "xcall")
124 (if_then_else (eq_attr "mcu_mega" "no")
129 ;; Define mode iterator
130 (define_mode_iterator QISI [(QI "") (HI "") (SI "")])
131 (define_mode_iterator QIDI [(QI "") (HI "") (SI "") (DI "")])
132 (define_mode_iterator HIDI [(HI "") (SI "") (DI "")])
133 (define_mode_iterator HISI [(HI "") (SI "")])
135 ;;========================================================================
136 ;; The following is used by nonlocal_goto and setjmp.
137 ;; The receiver pattern will create no instructions since internally
138 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
139 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
140 ;; The 'null' receiver also avoids problems with optimisation
141 ;; not recognising incoming jmp and removing code that resets frame_pointer.
142 ;; The code derived from builtins.c.
144 (define_expand "nonlocal_goto_receiver"
146 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
149 emit_move_insn (virtual_stack_vars_rtx,
150 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
151 gen_int_mode (STARTING_FRAME_OFFSET,
153 /* This might change the hard frame pointer in ways that aren't
154 apparent to early optimization passes, so force a clobber. */
155 emit_clobber (hard_frame_pointer_rtx);
160 ;; Defining nonlocal_goto_receiver means we must also define this.
161 ;; even though its function is identical to that in builtins.c
163 (define_expand "nonlocal_goto"
165 (use (match_operand 0 "general_operand"))
166 (use (match_operand 1 "general_operand"))
167 (use (match_operand 2 "general_operand"))
168 (use (match_operand 3 "general_operand"))
172 rtx r_label = copy_to_reg (operands[1]);
173 rtx r_fp = operands[3];
174 rtx r_sp = operands[2];
176 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
178 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
180 emit_move_insn (hard_frame_pointer_rtx, r_fp);
181 emit_stack_restore (SAVE_NONLOCAL, r_sp);
183 emit_use (hard_frame_pointer_rtx);
184 emit_use (stack_pointer_rtx);
186 emit_indirect_jump (r_label);
192 (define_insn "*pushqi"
193 [(set (mem:QI (post_dec:HI (reg:HI REG_SP)))
194 (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
199 [(set_attr "length" "1,1")])
201 (define_insn "*pushhi"
202 [(set (mem:HI (post_dec:HI (reg:HI REG_SP)))
203 (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
207 push __zero_reg__\;push __zero_reg__"
208 [(set_attr "length" "2,2")])
210 (define_insn "*pushsi"
211 [(set (mem:SI (post_dec:HI (reg:HI REG_SP)))
212 (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
215 push %D0\;push %C0\;push %B0\;push %A0
216 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
217 [(set_attr "length" "4,4")])
219 (define_insn "*pushsf"
220 [(set (mem:SF (post_dec:HI (reg:HI REG_SP)))
221 (match_operand:SF 0 "register_operand" "r"))]
227 [(set_attr "length" "4")])
229 ;;========================================================================
231 ;; The last alternative (any immediate constant to any register) is
232 ;; very expensive. It should be optimized by peephole2 if a scratch
233 ;; register is available, but then that register could just as well be
234 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
235 ;; are call-saved registers, and most of LD_REGS are call-used registers,
236 ;; so this may still be a win for registers live across function calls.
238 (define_expand "movqi"
239 [(set (match_operand:QI 0 "nonimmediate_operand" "")
240 (match_operand:QI 1 "general_operand" ""))]
242 "/* One of the ops has to be in a register. */
243 if (!register_operand(operand0, QImode)
244 && ! (register_operand(operand1, QImode) || const0_rtx == operand1))
245 operands[1] = copy_to_mode_reg(QImode, operand1);
248 (define_insn "*movqi"
249 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
250 (match_operand:QI 1 "general_operand" "rL,i,rL,Qm,r,q,i"))]
251 "(register_operand (operands[0],QImode)
252 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
253 "* return output_movqi (insn, operands, NULL);"
254 [(set_attr "length" "1,1,5,5,1,1,4")
255 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
257 ;; This is used in peephole2 to optimize loading immediate constants
258 ;; if a scratch register from LD_REGS happens to be available.
260 (define_insn "*reload_inqi"
261 [(set (match_operand:QI 0 "register_operand" "=l")
262 (match_operand:QI 1 "immediate_operand" "i"))
263 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
267 [(set_attr "length" "2")
268 (set_attr "cc" "none")])
271 [(match_scratch:QI 2 "d")
272 (set (match_operand:QI 0 "l_register_operand" "")
273 (match_operand:QI 1 "immediate_operand" ""))]
274 "(operands[1] != const0_rtx
275 && operands[1] != const1_rtx
276 && operands[1] != constm1_rtx)"
277 [(parallel [(set (match_dup 0) (match_dup 1))
278 (clobber (match_dup 2))])]
281 ;;============================================================================
282 ;; move word (16 bit)
284 (define_expand "movhi"
285 [(set (match_operand:HI 0 "nonimmediate_operand" "")
286 (match_operand:HI 1 "general_operand" ""))]
290 /* One of the ops has to be in a register. */
291 if (!register_operand(operand0, HImode)
292 && !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
294 operands[1] = copy_to_mode_reg(HImode, operand1);
298 (define_insn "*movhi_sp"
299 [(set (match_operand:HI 0 "register_operand" "=q,r")
300 (match_operand:HI 1 "register_operand" "r,q"))]
301 "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode))
302 || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))"
303 "* return output_movhi (insn, operands, NULL);"
304 [(set_attr "length" "5,2")
305 (set_attr "cc" "none,none")])
307 (define_insn "movhi_sp_r_irq_off"
308 [(set (match_operand:HI 0 "stack_register_operand" "=q")
309 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
310 UNSPECV_WRITE_SP_IRQ_OFF))]
314 [(set_attr "length" "2")
315 (set_attr "cc" "none")])
317 (define_insn "movhi_sp_r_irq_on"
318 [(set (match_operand:HI 0 "stack_register_operand" "=q")
319 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
320 UNSPECV_WRITE_SP_IRQ_ON))]
326 [(set_attr "length" "4")
327 (set_attr "cc" "none")])
330 [(match_scratch:QI 2 "d")
331 (set (match_operand:HI 0 "l_register_operand" "")
332 (match_operand:HI 1 "immediate_operand" ""))]
333 "(operands[1] != const0_rtx
334 && operands[1] != constm1_rtx)"
335 [(parallel [(set (match_dup 0) (match_dup 1))
336 (clobber (match_dup 2))])]
339 ;; '*' because it is not used in rtl generation, only in above peephole
340 (define_insn "*reload_inhi"
341 [(set (match_operand:HI 0 "register_operand" "=r")
342 (match_operand:HI 1 "immediate_operand" "i"))
343 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
345 "* return output_reload_inhi (insn, operands, NULL);"
346 [(set_attr "length" "4")
347 (set_attr "cc" "none")])
349 (define_insn "*movhi"
350 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
351 (match_operand:HI 1 "general_operand" "rL,m,rL,i,i,r,q"))]
352 "(register_operand (operands[0],HImode)
353 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
354 "* return output_movhi (insn, operands, NULL);"
355 [(set_attr "length" "2,6,7,2,6,5,2")
356 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
358 (define_peephole2 ; movw
359 [(set (match_operand:QI 0 "even_register_operand" "")
360 (match_operand:QI 1 "even_register_operand" ""))
361 (set (match_operand:QI 2 "odd_register_operand" "")
362 (match_operand:QI 3 "odd_register_operand" ""))]
364 && REGNO (operands[0]) == REGNO (operands[2]) - 1
365 && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
366 [(set (match_dup 4) (match_dup 5))]
368 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
369 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
372 (define_peephole2 ; movw_r
373 [(set (match_operand:QI 0 "odd_register_operand" "")
374 (match_operand:QI 1 "odd_register_operand" ""))
375 (set (match_operand:QI 2 "even_register_operand" "")
376 (match_operand:QI 3 "even_register_operand" ""))]
378 && REGNO (operands[2]) == REGNO (operands[0]) - 1
379 && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
380 [(set (match_dup 4) (match_dup 5))]
382 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
383 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
386 ;;==========================================================================
387 ;; move double word (32 bit)
389 (define_expand "movsi"
390 [(set (match_operand:SI 0 "nonimmediate_operand" "")
391 (match_operand:SI 1 "general_operand" ""))]
395 /* One of the ops has to be in a register. */
396 if (!register_operand (operand0, SImode)
397 && !(register_operand (operand1, SImode) || const0_rtx == operand1))
399 operands[1] = copy_to_mode_reg (SImode, operand1);
405 (define_peephole2 ; *reload_insi
406 [(match_scratch:QI 2 "d")
407 (set (match_operand:SI 0 "l_register_operand" "")
408 (match_operand:SI 1 "const_int_operand" ""))
410 "(operands[1] != const0_rtx
411 && operands[1] != constm1_rtx)"
412 [(parallel [(set (match_dup 0) (match_dup 1))
413 (clobber (match_dup 2))])]
416 ;; '*' because it is not used in rtl generation.
417 (define_insn "*reload_insi"
418 [(set (match_operand:SI 0 "register_operand" "=r")
419 (match_operand:SI 1 "const_int_operand" "n"))
420 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
423 return output_reload_insisf (insn, operands, operands[2], NULL);
425 [(set_attr "length" "8")
426 (set_attr "cc" "clobber")])
429 (define_insn "*movsi"
430 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
431 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
432 "(register_operand (operands[0],SImode)
433 || register_operand (operands[1],SImode) || const0_rtx == operands[1])"
435 return output_movsisf (insn, operands, NULL_RTX, NULL);
437 [(set_attr "length" "4,4,8,9,4,10")
438 (set_attr "cc" "none,set_zn,clobber,clobber,clobber,clobber")])
440 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
441 ;; move floating point numbers (32 bit)
443 (define_expand "movsf"
444 [(set (match_operand:SF 0 "nonimmediate_operand" "")
445 (match_operand:SF 1 "general_operand" ""))]
449 /* One of the ops has to be in a register. */
450 if (!register_operand (operand1, SFmode)
451 && !register_operand (operand0, SFmode))
453 operands[1] = copy_to_mode_reg (SFmode, operand1);
457 (define_insn "*movsf"
458 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
459 (match_operand:SF 1 "general_operand" "r,G,Qm,rG,F,F"))]
460 "register_operand (operands[0], SFmode)
461 || register_operand (operands[1], SFmode)
462 || operands[1] == CONST0_RTX (SFmode)"
464 return output_movsisf (insn, operands, NULL_RTX, NULL);
466 [(set_attr "length" "4,4,8,9,4,10")
467 (set_attr "cc" "none,set_zn,clobber,clobber,clobber,clobber")])
469 (define_peephole2 ; *reload_insf
470 [(match_scratch:QI 2 "d")
471 (set (match_operand:SF 0 "l_register_operand" "")
472 (match_operand:SF 1 "const_double_operand" ""))
474 "operands[1] != CONST0_RTX (SFmode)"
475 [(parallel [(set (match_dup 0)
477 (clobber (match_dup 2))])]
480 ;; '*' because it is not used in rtl generation.
481 (define_insn "*reload_insf"
482 [(set (match_operand:SF 0 "register_operand" "=r")
483 (match_operand:SF 1 "const_double_operand" "F"))
484 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
487 return output_reload_insisf (insn, operands, operands[2], NULL);
489 [(set_attr "length" "8")
490 (set_attr "cc" "clobber")])
492 ;;=========================================================================
493 ;; move string (like memcpy)
494 ;; implement as RTL loop
496 (define_expand "movmemhi"
497 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
498 (match_operand:BLK 1 "memory_operand" ""))
499 (use (match_operand:HI 2 "const_int_operand" ""))
500 (use (match_operand:HI 3 "const_int_operand" ""))])]
505 enum machine_mode mode;
506 rtx label = gen_label_rtx ();
510 /* Copy pointers into new psuedos - they will be changed. */
511 rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
512 rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
514 /* Create rtx for tmp register - we use this as scratch. */
515 rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
517 if (GET_CODE (operands[2]) != CONST_INT)
520 count = INTVAL (operands[2]);
524 /* Work out branch probability for latter use. */
525 prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
527 /* See if constant fit 8 bits. */
528 mode = (count < 0x100) ? QImode : HImode;
529 /* Create loop counter register. */
530 loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
532 /* Now create RTL code for move loop. */
533 /* Label at top of loop. */
536 /* Move one byte into scratch and inc pointer. */
537 emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
538 emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
540 /* Move to mem and inc pointer. */
541 emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
542 emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
544 /* Decrement count. */
545 emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
547 /* Compare with zero and jump if not equal. */
548 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
550 /* Set jump probability based on loop count. */
551 jump = get_last_insn ();
552 add_reg_note (jump, REG_BR_PROB, GEN_INT (prob));
556 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
557 ;; memset (%0, %2, %1)
559 (define_expand "setmemhi"
560 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
561 (match_operand 2 "const_int_operand" ""))
562 (use (match_operand:HI 1 "const_int_operand" ""))
563 (use (match_operand:HI 3 "const_int_operand" "n"))
564 (clobber (match_scratch:HI 4 ""))
565 (clobber (match_dup 5))])]
570 enum machine_mode mode;
572 /* If value to set is not zero, use the library routine. */
573 if (operands[2] != const0_rtx)
576 if (GET_CODE (operands[1]) != CONST_INT)
579 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
580 mode = cnt8 ? QImode : HImode;
581 operands[5] = gen_rtx_SCRATCH (mode);
582 operands[1] = copy_to_mode_reg (mode,
583 gen_int_mode (INTVAL (operands[1]), mode));
584 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
585 operands[0] = gen_rtx_MEM (BLKmode, addr0);
588 (define_insn "*clrmemqi"
589 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
591 (use (match_operand:QI 1 "register_operand" "r"))
592 (use (match_operand:QI 2 "const_int_operand" "n"))
593 (clobber (match_scratch:HI 3 "=0"))
594 (clobber (match_scratch:QI 4 "=&1"))]
596 "st %a0+,__zero_reg__
599 [(set_attr "length" "3")
600 (set_attr "cc" "clobber")])
602 (define_insn "*clrmemhi"
603 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
605 (use (match_operand:HI 1 "register_operand" "!w,d"))
606 (use (match_operand:HI 2 "const_int_operand" "n,n"))
607 (clobber (match_scratch:HI 3 "=0,0"))
608 (clobber (match_scratch:HI 4 "=&1,&1"))]
611 if (which_alternative==0)
612 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
613 AS2 (sbiw,%A1,1) CR_TAB
616 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
617 AS2 (subi,%A1,1) CR_TAB
618 AS2 (sbci,%B1,0) CR_TAB
621 [(set_attr "length" "3,4")
622 (set_attr "cc" "clobber,clobber")])
624 (define_expand "strlenhi"
626 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
627 (match_operand:QI 2 "const_int_operand" "")
628 (match_operand:HI 3 "immediate_operand" "")]
630 (set (match_dup 4) (plus:HI (match_dup 4)
632 (set (match_operand:HI 0 "register_operand" "")
633 (minus:HI (match_dup 4)
638 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
640 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
641 operands[1] = gen_rtx_MEM (BLKmode, addr);
643 operands[4] = gen_reg_rtx (HImode);
646 (define_insn "*strlenhi"
647 [(set (match_operand:HI 0 "register_operand" "=e")
648 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
650 (match_operand:HI 2 "immediate_operand" "i")]
656 [(set_attr "length" "3")
657 (set_attr "cc" "clobber")])
659 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
662 (define_insn "addqi3"
663 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
664 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
665 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
672 [(set_attr "length" "1,1,1,1")
673 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
676 (define_expand "addhi3"
677 [(set (match_operand:HI 0 "register_operand" "")
678 (plus:HI (match_operand:HI 1 "register_operand" "")
679 (match_operand:HI 2 "nonmemory_operand" "")))]
683 if (GET_CODE (operands[2]) == CONST_INT)
685 short tmp = INTVAL (operands[2]);
686 operands[2] = GEN_INT(tmp);
691 (define_insn "*addhi3_zero_extend"
692 [(set (match_operand:HI 0 "register_operand" "=r")
693 (plus:HI (zero_extend:HI
694 (match_operand:QI 1 "register_operand" "r"))
695 (match_operand:HI 2 "register_operand" "0")))]
698 adc %B0,__zero_reg__"
699 [(set_attr "length" "2")
700 (set_attr "cc" "set_n")])
702 (define_insn "*addhi3_zero_extend1"
703 [(set (match_operand:HI 0 "register_operand" "=r")
704 (plus:HI (match_operand:HI 1 "register_operand" "%0")
706 (match_operand:QI 2 "register_operand" "r"))))]
709 adc %B0,__zero_reg__"
710 [(set_attr "length" "2")
711 (set_attr "cc" "set_n")])
713 (define_insn "*addhi3_sp_R_pc2"
714 [(set (match_operand:HI 1 "stack_register_operand" "=q")
715 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
716 (match_operand:HI 0 "avr_sp_immediate_operand" "R")))]
719 if (CONST_INT_P (operands[0]))
721 switch(INTVAL (operands[0]))
724 return \"rcall .\" CR_TAB
728 return \"rcall .\" CR_TAB
730 \"push __tmp_reg__\";
732 return \"rcall .\" CR_TAB
735 return \"rcall .\" CR_TAB
736 \"push __tmp_reg__\";
740 return \"push __tmp_reg__\";
744 return \"pop __tmp_reg__\";
746 return \"pop __tmp_reg__\" CR_TAB
749 return \"pop __tmp_reg__\" CR_TAB
750 \"pop __tmp_reg__\" CR_TAB
753 return \"pop __tmp_reg__\" CR_TAB
754 \"pop __tmp_reg__\" CR_TAB
755 \"pop __tmp_reg__\" CR_TAB
758 return \"pop __tmp_reg__\" CR_TAB
759 \"pop __tmp_reg__\" CR_TAB
760 \"pop __tmp_reg__\" CR_TAB
761 \"pop __tmp_reg__\" CR_TAB
767 [(set (attr "length")
768 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
769 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
770 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
771 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
772 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
773 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
774 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
775 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
776 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
777 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
778 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
779 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
782 (define_insn "*addhi3_sp_R_pc3"
783 [(set (match_operand:HI 1 "stack_register_operand" "=q")
784 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
785 (match_operand:QI 0 "avr_sp_immediate_operand" "R")))]
788 if (CONST_INT_P (operands[0]))
790 switch(INTVAL (operands[0]))
793 return \"rcall .\" CR_TAB
796 return \"rcall .\" CR_TAB
797 \"push __tmp_reg__\" CR_TAB
798 \"push __tmp_reg__\";
800 return \"rcall .\" CR_TAB
801 \"push __tmp_reg__\";
805 return \"push __tmp_reg__\" CR_TAB
806 \"push __tmp_reg__\";
808 return \"push __tmp_reg__\";
812 return \"pop __tmp_reg__\";
814 return \"pop __tmp_reg__\" CR_TAB
817 return \"pop __tmp_reg__\" CR_TAB
818 \"pop __tmp_reg__\" CR_TAB
821 return \"pop __tmp_reg__\" CR_TAB
822 \"pop __tmp_reg__\" CR_TAB
823 \"pop __tmp_reg__\" CR_TAB
826 return \"pop __tmp_reg__\" CR_TAB
827 \"pop __tmp_reg__\" CR_TAB
828 \"pop __tmp_reg__\" CR_TAB
829 \"pop __tmp_reg__\" CR_TAB
835 [(set (attr "length")
836 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
837 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
838 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
839 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
840 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
841 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
842 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
843 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
844 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
845 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
846 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
847 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
850 (define_insn "*addhi3"
851 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
853 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
854 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
857 add %A0,%A2\;adc %B0,%B2
860 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
861 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
862 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
863 [(set_attr "length" "2,1,1,2,3,3")
864 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
866 (define_insn "addsi3"
867 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
869 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
870 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
873 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
874 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
875 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
876 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
877 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
878 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
879 [(set_attr "length" "4,3,3,4,5,5")
880 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
882 (define_insn "*addsi3_zero_extend"
883 [(set (match_operand:SI 0 "register_operand" "=r")
884 (plus:SI (zero_extend:SI
885 (match_operand:QI 1 "register_operand" "r"))
886 (match_operand:SI 2 "register_operand" "0")))]
891 adc %D0,__zero_reg__"
892 [(set_attr "length" "4")
893 (set_attr "cc" "set_n")])
895 ;-----------------------------------------------------------------------------
897 (define_insn "subqi3"
898 [(set (match_operand:QI 0 "register_operand" "=r,d")
899 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
900 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
905 [(set_attr "length" "1,1")
906 (set_attr "cc" "set_czn,set_czn")])
908 (define_insn "subhi3"
909 [(set (match_operand:HI 0 "register_operand" "=r,d")
910 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
911 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
914 sub %A0,%A2\;sbc %B0,%B2
915 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
916 [(set_attr "length" "2,2")
917 (set_attr "cc" "set_czn,set_czn")])
919 (define_insn "*subhi3_zero_extend1"
920 [(set (match_operand:HI 0 "register_operand" "=r")
921 (minus:HI (match_operand:HI 1 "register_operand" "0")
923 (match_operand:QI 2 "register_operand" "r"))))]
926 sbc %B0,__zero_reg__"
927 [(set_attr "length" "2")
928 (set_attr "cc" "set_n")])
930 (define_insn "subsi3"
931 [(set (match_operand:SI 0 "register_operand" "=r,d")
932 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
933 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
936 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
937 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
938 [(set_attr "length" "4,4")
939 (set_attr "cc" "set_czn,set_czn")])
941 (define_insn "*subsi3_zero_extend"
942 [(set (match_operand:SI 0 "register_operand" "=r")
943 (minus:SI (match_operand:SI 1 "register_operand" "0")
945 (match_operand:QI 2 "register_operand" "r"))))]
950 sbc %D0,__zero_reg__"
951 [(set_attr "length" "4")
952 (set_attr "cc" "set_n")])
954 ;******************************************************************************
957 (define_expand "mulqi3"
958 [(set (match_operand:QI 0 "register_operand" "")
959 (mult:QI (match_operand:QI 1 "register_operand" "")
960 (match_operand:QI 2 "register_operand" "")))]
965 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
970 (define_insn "*mulqi3_enh"
971 [(set (match_operand:QI 0 "register_operand" "=r")
972 (mult:QI (match_operand:QI 1 "register_operand" "r")
973 (match_operand:QI 2 "register_operand" "r")))]
978 [(set_attr "length" "3")
979 (set_attr "cc" "clobber")])
981 (define_expand "mulqi3_call"
982 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
983 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
984 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
985 (clobber (reg:QI 22))])
986 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
990 (define_insn "*mulqi3_call"
991 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
992 (clobber (reg:QI 22))]
995 [(set_attr "type" "xcall")
996 (set_attr "cc" "clobber")])
998 (define_insn "mulqihi3"
999 [(set (match_operand:HI 0 "register_operand" "=r")
1000 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
1001 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
1006 [(set_attr "length" "3")
1007 (set_attr "cc" "clobber")])
1009 (define_insn "umulqihi3"
1010 [(set (match_operand:HI 0 "register_operand" "=r")
1011 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
1012 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1017 [(set_attr "length" "3")
1018 (set_attr "cc" "clobber")])
1020 (define_expand "mulhi3"
1021 [(set (match_operand:HI 0 "register_operand" "")
1022 (mult:HI (match_operand:HI 1 "register_operand" "")
1023 (match_operand:HI 2 "register_operand" "")))]
1029 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
1034 (define_insn "*mulhi3_enh"
1035 [(set (match_operand:HI 0 "register_operand" "=&r")
1036 (mult:HI (match_operand:HI 1 "register_operand" "r")
1037 (match_operand:HI 2 "register_operand" "r")))]
1046 [(set_attr "length" "7")
1047 (set_attr "cc" "clobber")])
1049 (define_expand "mulhi3_call"
1050 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1051 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1052 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1053 (clobber (reg:HI 22))
1054 (clobber (reg:QI 21))])
1055 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
1059 (define_insn "*mulhi3_call"
1060 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1061 (clobber (reg:HI 22))
1062 (clobber (reg:QI 21))]
1065 [(set_attr "type" "xcall")
1066 (set_attr "cc" "clobber")])
1068 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
1069 ;; All call-used registers clobbered otherwise - normal library call.
1070 (define_expand "mulsi3"
1071 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1072 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1073 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1074 (clobber (reg:HI 26))
1075 (clobber (reg:HI 30))])
1076 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
1080 (define_insn "*mulsi3_call"
1081 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1082 (clobber (reg:HI 26))
1083 (clobber (reg:HI 30))]
1086 [(set_attr "type" "xcall")
1087 (set_attr "cc" "clobber")])
1089 (define_expand "mulhisi3"
1091 (match_operand:HI 1 "register_operand" ""))
1093 (match_operand:HI 2 "register_operand" ""))
1095 (mult:SI (sign_extend:SI (reg:HI 18))
1096 (sign_extend:SI (reg:HI 20))))
1097 (set (match_operand:SI 0 "register_operand" "")
1102 (define_expand "umulhisi3"
1104 (match_operand:HI 1 "register_operand" ""))
1106 (match_operand:HI 2 "register_operand" ""))
1108 (mult:SI (zero_extend:SI (reg:HI 18))
1109 (zero_extend:SI (reg:HI 20))))
1110 (set (match_operand:SI 0 "register_operand" "")
1115 (define_insn "*mulhisi3_call"
1117 (mult:SI (sign_extend:SI (reg:HI 18))
1118 (sign_extend:SI (reg:HI 20))))]
1121 [(set_attr "type" "xcall")
1122 (set_attr "cc" "clobber")])
1124 (define_insn "*umulhisi3_call"
1126 (mult:SI (zero_extend:SI (reg:HI 18))
1127 (zero_extend:SI (reg:HI 20))))]
1129 "%~call __umulhisi3"
1130 [(set_attr "type" "xcall")
1131 (set_attr "cc" "clobber")])
1133 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
1136 ;; Generate libgcc.S calls ourselves, because:
1137 ;; - we know exactly which registers are clobbered (for QI and HI
1138 ;; modes, some of the call-used registers are preserved)
1139 ;; - we get both the quotient and the remainder at no extra cost
1140 ;; - we split the patterns only after the first CSE passes because
1141 ;; CSE has problems to operate on hard regs.
1143 (define_insn_and_split "divmodqi4"
1144 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1145 (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
1146 (match_operand:QI 2 "pseudo_register_operand" "")))
1147 (set (match_operand:QI 3 "pseudo_register_operand" "")
1148 (mod:QI (match_dup 1) (match_dup 2)))
1149 (clobber (reg:QI 22))
1150 (clobber (reg:QI 23))
1151 (clobber (reg:QI 24))
1152 (clobber (reg:QI 25))])]
1154 "this divmodqi4 pattern should have been splitted;"
1156 [(set (reg:QI 24) (match_dup 1))
1157 (set (reg:QI 22) (match_dup 2))
1158 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1159 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1160 (clobber (reg:QI 22))
1161 (clobber (reg:QI 23))])
1162 (set (match_dup 0) (reg:QI 24))
1163 (set (match_dup 3) (reg:QI 25))]
1166 (define_insn "*divmodqi4_call"
1167 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1168 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1169 (clobber (reg:QI 22))
1170 (clobber (reg:QI 23))]
1172 "%~call __divmodqi4"
1173 [(set_attr "type" "xcall")
1174 (set_attr "cc" "clobber")])
1176 (define_insn_and_split "udivmodqi4"
1177 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1178 (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
1179 (match_operand:QI 2 "pseudo_register_operand" "")))
1180 (set (match_operand:QI 3 "pseudo_register_operand" "")
1181 (umod:QI (match_dup 1) (match_dup 2)))
1182 (clobber (reg:QI 22))
1183 (clobber (reg:QI 23))
1184 (clobber (reg:QI 24))
1185 (clobber (reg:QI 25))])]
1187 "this udivmodqi4 pattern should have been splitted;"
1189 [(set (reg:QI 24) (match_dup 1))
1190 (set (reg:QI 22) (match_dup 2))
1191 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1192 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1193 (clobber (reg:QI 23))])
1194 (set (match_dup 0) (reg:QI 24))
1195 (set (match_dup 3) (reg:QI 25))]
1198 (define_insn "*udivmodqi4_call"
1199 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1200 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1201 (clobber (reg:QI 23))]
1203 "%~call __udivmodqi4"
1204 [(set_attr "type" "xcall")
1205 (set_attr "cc" "clobber")])
1207 (define_insn_and_split "divmodhi4"
1208 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1209 (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
1210 (match_operand:HI 2 "pseudo_register_operand" "")))
1211 (set (match_operand:HI 3 "pseudo_register_operand" "")
1212 (mod:HI (match_dup 1) (match_dup 2)))
1213 (clobber (reg:QI 21))
1214 (clobber (reg:HI 22))
1215 (clobber (reg:HI 24))
1216 (clobber (reg:HI 26))])]
1218 "this should have been splitted;"
1220 [(set (reg:HI 24) (match_dup 1))
1221 (set (reg:HI 22) (match_dup 2))
1222 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1223 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1224 (clobber (reg:HI 26))
1225 (clobber (reg:QI 21))])
1226 (set (match_dup 0) (reg:HI 22))
1227 (set (match_dup 3) (reg:HI 24))]
1230 (define_insn "*divmodhi4_call"
1231 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1232 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1233 (clobber (reg:HI 26))
1234 (clobber (reg:QI 21))]
1236 "%~call __divmodhi4"
1237 [(set_attr "type" "xcall")
1238 (set_attr "cc" "clobber")])
1240 (define_insn_and_split "udivmodhi4"
1241 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1242 (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
1243 (match_operand:HI 2 "pseudo_register_operand" "")))
1244 (set (match_operand:HI 3 "pseudo_register_operand" "")
1245 (umod:HI (match_dup 1) (match_dup 2)))
1246 (clobber (reg:QI 21))
1247 (clobber (reg:HI 22))
1248 (clobber (reg:HI 24))
1249 (clobber (reg:HI 26))])]
1251 "this udivmodhi4 pattern should have been splitted.;"
1253 [(set (reg:HI 24) (match_dup 1))
1254 (set (reg:HI 22) (match_dup 2))
1255 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1256 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1257 (clobber (reg:HI 26))
1258 (clobber (reg:QI 21))])
1259 (set (match_dup 0) (reg:HI 22))
1260 (set (match_dup 3) (reg:HI 24))]
1263 (define_insn "*udivmodhi4_call"
1264 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1265 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1266 (clobber (reg:HI 26))
1267 (clobber (reg:QI 21))]
1269 "%~call __udivmodhi4"
1270 [(set_attr "type" "xcall")
1271 (set_attr "cc" "clobber")])
1273 (define_insn_and_split "divmodsi4"
1274 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1275 (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
1276 (match_operand:SI 2 "pseudo_register_operand" "")))
1277 (set (match_operand:SI 3 "pseudo_register_operand" "")
1278 (mod:SI (match_dup 1) (match_dup 2)))
1279 (clobber (reg:SI 18))
1280 (clobber (reg:SI 22))
1281 (clobber (reg:HI 26))
1282 (clobber (reg:HI 30))])]
1284 "this divmodsi4 pattern should have been splitted;"
1286 [(set (reg:SI 22) (match_dup 1))
1287 (set (reg:SI 18) (match_dup 2))
1288 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1289 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1290 (clobber (reg:HI 26))
1291 (clobber (reg:HI 30))])
1292 (set (match_dup 0) (reg:SI 18))
1293 (set (match_dup 3) (reg:SI 22))]
1296 (define_insn "*divmodsi4_call"
1297 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1298 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1299 (clobber (reg:HI 26))
1300 (clobber (reg:HI 30))]
1302 "%~call __divmodsi4"
1303 [(set_attr "type" "xcall")
1304 (set_attr "cc" "clobber")])
1306 (define_insn_and_split "udivmodsi4"
1307 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1308 (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
1309 (match_operand:SI 2 "pseudo_register_operand" "")))
1310 (set (match_operand:SI 3 "pseudo_register_operand" "")
1311 (umod:SI (match_dup 1) (match_dup 2)))
1312 (clobber (reg:SI 18))
1313 (clobber (reg:SI 22))
1314 (clobber (reg:HI 26))
1315 (clobber (reg:HI 30))])]
1317 "this udivmodsi4 pattern should have been splitted;"
1319 [(set (reg:SI 22) (match_dup 1))
1320 (set (reg:SI 18) (match_dup 2))
1321 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1322 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1323 (clobber (reg:HI 26))
1324 (clobber (reg:HI 30))])
1325 (set (match_dup 0) (reg:SI 18))
1326 (set (match_dup 3) (reg:SI 22))]
1329 (define_insn "*udivmodsi4_call"
1330 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1331 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1332 (clobber (reg:HI 26))
1333 (clobber (reg:HI 30))]
1335 "%~call __udivmodsi4"
1336 [(set_attr "type" "xcall")
1337 (set_attr "cc" "clobber")])
1339 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
1342 (define_insn "andqi3"
1343 [(set (match_operand:QI 0 "register_operand" "=r,d")
1344 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
1345 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1350 [(set_attr "length" "1,1")
1351 (set_attr "cc" "set_zn,set_zn")])
1353 (define_insn "andhi3"
1354 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
1355 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
1356 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
1357 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1360 if (which_alternative==0)
1361 return ("and %A0,%A2" CR_TAB
1363 else if (which_alternative==1)
1365 if (GET_CODE (operands[2]) == CONST_INT)
1367 int mask = INTVAL (operands[2]);
1368 if ((mask & 0xff) != 0xff)
1369 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1370 if ((mask & 0xff00) != 0xff00)
1371 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1374 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
1375 AS2 (andi,%B0,hi8(%2)));
1377 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
1381 [(set_attr "length" "2,2,3")
1382 (set_attr "cc" "set_n,clobber,set_n")])
1384 (define_insn "andsi3"
1385 [(set (match_operand:SI 0 "register_operand" "=r,d")
1386 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1387 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1390 if (which_alternative==0)
1391 return ("and %0,%2" CR_TAB
1392 "and %B0,%B2" CR_TAB
1393 "and %C0,%C2" CR_TAB
1395 else if (which_alternative==1)
1397 if (GET_CODE (operands[2]) == CONST_INT)
1399 HOST_WIDE_INT mask = INTVAL (operands[2]);
1400 if ((mask & 0xff) != 0xff)
1401 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1402 if ((mask & 0xff00) != 0xff00)
1403 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1404 if ((mask & 0xff0000L) != 0xff0000L)
1405 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
1406 if ((mask & 0xff000000L) != 0xff000000L)
1407 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
1410 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
1411 AS2 (andi, %B0,hi8(%2)) CR_TAB
1412 AS2 (andi, %C0,hlo8(%2)) CR_TAB
1413 AS2 (andi, %D0,hhi8(%2)));
1417 [(set_attr "length" "4,4")
1418 (set_attr "cc" "set_n,clobber")])
1420 (define_peephole2 ; andi
1421 [(set (match_operand:QI 0 "d_register_operand" "")
1422 (and:QI (match_dup 0)
1423 (match_operand:QI 1 "const_int_operand" "")))
1425 (and:QI (match_dup 0)
1426 (match_operand:QI 2 "const_int_operand" "")))]
1428 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1430 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
1433 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1436 (define_insn "iorqi3"
1437 [(set (match_operand:QI 0 "register_operand" "=r,d")
1438 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
1439 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1444 [(set_attr "length" "1,1")
1445 (set_attr "cc" "set_zn,set_zn")])
1447 (define_insn "iorhi3"
1448 [(set (match_operand:HI 0 "register_operand" "=r,d")
1449 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1450 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
1453 if (which_alternative==0)
1454 return ("or %A0,%A2" CR_TAB
1456 if (GET_CODE (operands[2]) == CONST_INT)
1458 int mask = INTVAL (operands[2]);
1460 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1462 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1465 return (AS2 (ori,%0,lo8(%2)) CR_TAB
1466 AS2 (ori,%B0,hi8(%2)));
1468 [(set_attr "length" "2,2")
1469 (set_attr "cc" "set_n,clobber")])
1471 (define_insn "*iorhi3_clobber"
1472 [(set (match_operand:HI 0 "register_operand" "=r,r")
1473 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1474 (match_operand:HI 2 "immediate_operand" "M,i")))
1475 (clobber (match_scratch:QI 3 "=&d,&d"))]
1478 ldi %3,lo8(%2)\;or %A0,%3
1479 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
1480 [(set_attr "length" "2,4")
1481 (set_attr "cc" "clobber,set_n")])
1483 (define_insn "iorsi3"
1484 [(set (match_operand:SI 0 "register_operand" "=r,d")
1485 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1486 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1489 if (which_alternative==0)
1490 return ("or %0,%2" CR_TAB
1494 if (GET_CODE (operands[2]) == CONST_INT)
1496 HOST_WIDE_INT mask = INTVAL (operands[2]);
1498 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1500 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1501 if (mask & 0xff0000L)
1502 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
1503 if (mask & 0xff000000L)
1504 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
1507 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
1508 AS2 (ori, %B0,hi8(%2)) CR_TAB
1509 AS2 (ori, %C0,hlo8(%2)) CR_TAB
1510 AS2 (ori, %D0,hhi8(%2)));
1512 [(set_attr "length" "4,4")
1513 (set_attr "cc" "set_n,clobber")])
1515 (define_insn "*iorsi3_clobber"
1516 [(set (match_operand:SI 0 "register_operand" "=r,r")
1517 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1518 (match_operand:SI 2 "immediate_operand" "M,i")))
1519 (clobber (match_scratch:QI 3 "=&d,&d"))]
1522 ldi %3,lo8(%2)\;or %A0,%3
1523 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
1524 [(set_attr "length" "2,8")
1525 (set_attr "cc" "clobber,set_n")])
1527 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1530 (define_insn "xorqi3"
1531 [(set (match_operand:QI 0 "register_operand" "=r")
1532 (xor:QI (match_operand:QI 1 "register_operand" "%0")
1533 (match_operand:QI 2 "register_operand" "r")))]
1536 [(set_attr "length" "1")
1537 (set_attr "cc" "set_zn")])
1539 (define_insn "xorhi3"
1540 [(set (match_operand:HI 0 "register_operand" "=r")
1541 (xor:HI (match_operand:HI 1 "register_operand" "%0")
1542 (match_operand:HI 2 "register_operand" "r")))]
1546 [(set_attr "length" "2")
1547 (set_attr "cc" "set_n")])
1549 (define_insn "xorsi3"
1550 [(set (match_operand:SI 0 "register_operand" "=r")
1551 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1552 (match_operand:SI 2 "register_operand" "r")))]
1558 [(set_attr "length" "4")
1559 (set_attr "cc" "set_n")])
1561 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
1564 (define_expand "rotlqi3"
1565 [(set (match_operand:QI 0 "register_operand" "")
1566 (rotate:QI (match_operand:QI 1 "register_operand" "")
1567 (match_operand:QI 2 "const_int_operand" "")))]
1571 if (!CONST_INT_P (operands[2]) || (INTVAL (operands[2]) != 4))
1575 (define_insn "rotlqi3_4"
1576 [(set (match_operand:QI 0 "register_operand" "=r")
1577 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1581 [(set_attr "length" "1")
1582 (set_attr "cc" "none")])
1584 ;; Split all rotates of HI,SI and DImode registers where rotation is by
1585 ;; a whole number of bytes. The split creates the appropriate moves and
1586 ;; considers all overlap situations. DImode is split before reload.
1588 ;; HImode does not need scratch. Use attribute for this constraint.
1589 ;; Use QI scratch for DI mode as this is often split into byte sized operands.
1591 (define_mode_attr rotx [(DI "&r,&r,X") (SI "&r,&r,X") (HI "X,X,X")])
1592 (define_mode_attr rotsmode [(DI "QI") (SI "HI") (HI "QI")])
1594 (define_expand "rotl<mode>3"
1595 [(parallel [(set (match_operand:HIDI 0 "register_operand" "")
1596 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "")
1597 (match_operand:VOID 2 "const_int_operand" "")))
1598 (clobber (match_dup 3))])]
1602 if (CONST_INT_P (operands[2]) && 0 == (INTVAL (operands[2]) % 8))
1604 if (AVR_HAVE_MOVW && 0 == INTVAL (operands[2]) % 16)
1605 operands[3] = gen_reg_rtx (<rotsmode>mode);
1607 operands[3] = gen_reg_rtx (QImode);
1614 ;; Overlapping non-HImode registers often (but not always) need a scratch.
1615 ;; The best we can do is use early clobber alternative "#&r" so that
1616 ;; completely non-overlapping operands dont get a scratch but # so register
1617 ;; allocation does not prefer non-overlapping.
1620 ; Split word aligned rotates using scratch that is mode dependent.
1621 (define_insn_and_split "*rotw<mode>"
1622 [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
1623 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
1624 (match_operand 2 "immediate_operand" "n,n,n")))
1625 (clobber (match_operand:<rotsmode> 3 "register_operand" "=<rotx>" ))]
1626 "(CONST_INT_P (operands[2]) &&
1627 (0 == (INTVAL (operands[2]) % 16) && AVR_HAVE_MOVW))"
1629 "&& (reload_completed || <MODE>mode == DImode)"
1631 "avr_rotate_bytes (operands);
1636 ; Split byte aligned rotates using scratch that is always QI mode.
1637 (define_insn_and_split "*rotb<mode>"
1638 [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
1639 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
1640 (match_operand 2 "immediate_operand" "n,n,n")))
1641 (clobber (match_operand:QI 3 "register_operand" "=<rotx>" ))]
1642 "(CONST_INT_P (operands[2]) &&
1643 (8 == (INTVAL (operands[2]) % 16)
1644 || (!AVR_HAVE_MOVW && 0 == (INTVAL (operands[2]) % 16))))"
1646 "&& (reload_completed || <MODE>mode == DImode)"
1648 "avr_rotate_bytes (operands);
1653 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
1654 ;; arithmetic shift left
1656 (define_expand "ashlqi3"
1657 [(set (match_operand:QI 0 "register_operand" "")
1658 (ashift:QI (match_operand:QI 1 "register_operand" "")
1659 (match_operand:QI 2 "general_operand" "")))]
1663 (define_split ; ashlqi3_const4
1664 [(set (match_operand:QI 0 "d_register_operand" "")
1665 (ashift:QI (match_dup 0)
1668 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1669 (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
1672 (define_split ; ashlqi3_const5
1673 [(set (match_operand:QI 0 "d_register_operand" "")
1674 (ashift:QI (match_dup 0)
1677 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1678 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1679 (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
1682 (define_split ; ashlqi3_const6
1683 [(set (match_operand:QI 0 "d_register_operand" "")
1684 (ashift:QI (match_dup 0)
1687 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1688 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1689 (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
1692 (define_insn "*ashlqi3"
1693 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1694 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1695 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1697 "* return ashlqi3_out (insn, operands, NULL);"
1698 [(set_attr "length" "5,0,1,2,4,6,9")
1699 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1701 (define_insn "ashlhi3"
1702 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1703 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1704 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1706 "* return ashlhi3_out (insn, operands, NULL);"
1707 [(set_attr "length" "6,0,2,2,4,10,10")
1708 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1710 (define_insn "ashlsi3"
1711 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1712 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1713 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1715 "* return ashlsi3_out (insn, operands, NULL);"
1716 [(set_attr "length" "8,0,4,4,8,10,12")
1717 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1719 ;; Optimize if a scratch register from LD_REGS happens to be available.
1721 (define_peephole2 ; ashlqi3_l_const4
1722 [(set (match_operand:QI 0 "l_register_operand" "")
1723 (ashift:QI (match_dup 0)
1725 (match_scratch:QI 1 "d")]
1727 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1728 (set (match_dup 1) (const_int -16))
1729 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1732 (define_peephole2 ; ashlqi3_l_const5
1733 [(set (match_operand:QI 0 "l_register_operand" "")
1734 (ashift:QI (match_dup 0)
1736 (match_scratch:QI 1 "d")]
1738 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1739 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1740 (set (match_dup 1) (const_int -32))
1741 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1744 (define_peephole2 ; ashlqi3_l_const6
1745 [(set (match_operand:QI 0 "l_register_operand" "")
1746 (ashift:QI (match_dup 0)
1748 (match_scratch:QI 1 "d")]
1750 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1751 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1752 (set (match_dup 1) (const_int -64))
1753 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1757 [(match_scratch:QI 3 "d")
1758 (set (match_operand:HI 0 "register_operand" "")
1759 (ashift:HI (match_operand:HI 1 "register_operand" "")
1760 (match_operand:QI 2 "const_int_operand" "")))]
1762 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
1763 (clobber (match_dup 3))])]
1766 (define_insn "*ashlhi3_const"
1767 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1768 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1769 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1770 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1772 "* return ashlhi3_out (insn, operands, NULL);"
1773 [(set_attr "length" "0,2,2,4,10")
1774 (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
1777 [(match_scratch:QI 3 "d")
1778 (set (match_operand:SI 0 "register_operand" "")
1779 (ashift:SI (match_operand:SI 1 "register_operand" "")
1780 (match_operand:QI 2 "const_int_operand" "")))]
1782 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
1783 (clobber (match_dup 3))])]
1786 (define_insn "*ashlsi3_const"
1787 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1788 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1789 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1790 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1792 "* return ashlsi3_out (insn, operands, NULL);"
1793 [(set_attr "length" "0,4,4,10")
1794 (set_attr "cc" "none,set_n,clobber,clobber")])
1796 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1797 ;; arithmetic shift right
1799 (define_insn "ashrqi3"
1800 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1801 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
1802 (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
1804 "* return ashrqi3_out (insn, operands, NULL);"
1805 [(set_attr "length" "5,0,1,2,5,9")
1806 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
1808 (define_insn "ashrhi3"
1809 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1810 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1811 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1813 "* return ashrhi3_out (insn, operands, NULL);"
1814 [(set_attr "length" "6,0,2,4,4,10,10")
1815 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1817 (define_insn "ashrsi3"
1818 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1819 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1820 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1822 "* return ashrsi3_out (insn, operands, NULL);"
1823 [(set_attr "length" "8,0,4,6,8,10,12")
1824 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1826 ;; Optimize if a scratch register from LD_REGS happens to be available.
1829 [(match_scratch:QI 3 "d")
1830 (set (match_operand:HI 0 "register_operand" "")
1831 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1832 (match_operand:QI 2 "const_int_operand" "")))]
1834 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
1835 (clobber (match_dup 3))])]
1838 (define_insn "*ashrhi3_const"
1839 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1840 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1841 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1842 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1844 "* return ashrhi3_out (insn, operands, NULL);"
1845 [(set_attr "length" "0,2,4,4,10")
1846 (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
1849 [(match_scratch:QI 3 "d")
1850 (set (match_operand:SI 0 "register_operand" "")
1851 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1852 (match_operand:QI 2 "const_int_operand" "")))]
1854 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
1855 (clobber (match_dup 3))])]
1858 (define_insn "*ashrsi3_const"
1859 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1860 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1861 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1862 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1864 "* return ashrsi3_out (insn, operands, NULL);"
1865 [(set_attr "length" "0,4,4,10")
1866 (set_attr "cc" "none,clobber,set_n,clobber")])
1868 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1869 ;; logical shift right
1871 (define_expand "lshrqi3"
1872 [(set (match_operand:QI 0 "register_operand" "")
1873 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1874 (match_operand:QI 2 "general_operand" "")))]
1878 (define_split ; lshrqi3_const4
1879 [(set (match_operand:QI 0 "d_register_operand" "")
1880 (lshiftrt:QI (match_dup 0)
1883 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1884 (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
1887 (define_split ; lshrqi3_const5
1888 [(set (match_operand:QI 0 "d_register_operand" "")
1889 (lshiftrt:QI (match_dup 0)
1892 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1893 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1894 (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
1897 (define_split ; lshrqi3_const6
1898 [(set (match_operand:QI 0 "d_register_operand" "")
1899 (lshiftrt:QI (match_dup 0)
1902 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1903 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1904 (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
1907 (define_insn "*lshrqi3"
1908 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1909 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1910 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1912 "* return lshrqi3_out (insn, operands, NULL);"
1913 [(set_attr "length" "5,0,1,2,4,6,9")
1914 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1916 (define_insn "lshrhi3"
1917 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1918 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1919 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1921 "* return lshrhi3_out (insn, operands, NULL);"
1922 [(set_attr "length" "6,0,2,2,4,10,10")
1923 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1925 (define_insn "lshrsi3"
1926 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1927 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1928 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1930 "* return lshrsi3_out (insn, operands, NULL);"
1931 [(set_attr "length" "8,0,4,4,8,10,12")
1932 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1934 ;; Optimize if a scratch register from LD_REGS happens to be available.
1936 (define_peephole2 ; lshrqi3_l_const4
1937 [(set (match_operand:QI 0 "l_register_operand" "")
1938 (lshiftrt:QI (match_dup 0)
1940 (match_scratch:QI 1 "d")]
1942 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1943 (set (match_dup 1) (const_int 15))
1944 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1947 (define_peephole2 ; lshrqi3_l_const5
1948 [(set (match_operand:QI 0 "l_register_operand" "")
1949 (lshiftrt:QI (match_dup 0)
1951 (match_scratch:QI 1 "d")]
1953 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1954 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1955 (set (match_dup 1) (const_int 7))
1956 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1959 (define_peephole2 ; lshrqi3_l_const6
1960 [(set (match_operand:QI 0 "l_register_operand" "")
1961 (lshiftrt:QI (match_dup 0)
1963 (match_scratch:QI 1 "d")]
1965 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1966 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1967 (set (match_dup 1) (const_int 3))
1968 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1972 [(match_scratch:QI 3 "d")
1973 (set (match_operand:HI 0 "register_operand" "")
1974 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
1975 (match_operand:QI 2 "const_int_operand" "")))]
1977 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
1978 (clobber (match_dup 3))])]
1981 (define_insn "*lshrhi3_const"
1982 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1983 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1984 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1985 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1987 "* return lshrhi3_out (insn, operands, NULL);"
1988 [(set_attr "length" "0,2,2,4,10")
1989 (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
1992 [(match_scratch:QI 3 "d")
1993 (set (match_operand:SI 0 "register_operand" "")
1994 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1995 (match_operand:QI 2 "const_int_operand" "")))]
1997 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
1998 (clobber (match_dup 3))])]
2001 (define_insn "*lshrsi3_const"
2002 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2003 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
2004 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
2005 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
2007 "* return lshrsi3_out (insn, operands, NULL);"
2008 [(set_attr "length" "0,4,4,10")
2009 (set_attr "cc" "none,clobber,clobber,clobber")])
2011 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
2014 (define_insn "absqi2"
2015 [(set (match_operand:QI 0 "register_operand" "=r")
2016 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
2020 [(set_attr "length" "2")
2021 (set_attr "cc" "clobber")])
2024 (define_insn "abssf2"
2025 [(set (match_operand:SF 0 "register_operand" "=d,r")
2026 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
2031 [(set_attr "length" "1,2")
2032 (set_attr "cc" "set_n,clobber")])
2034 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
2037 (define_insn "negqi2"
2038 [(set (match_operand:QI 0 "register_operand" "=r")
2039 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
2042 [(set_attr "length" "1")
2043 (set_attr "cc" "set_zn")])
2045 (define_insn "neghi2"
2046 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
2047 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
2050 com %B0\;neg %A0\;sbci %B0,lo8(-1)
2051 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
2052 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
2053 [(set_attr "length" "3,4,4")
2054 (set_attr "cc" "set_czn,set_n,set_czn")])
2056 (define_insn "negsi2"
2057 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
2058 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
2061 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
2062 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
2063 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
2064 [(set_attr_alternative "length"
2067 (if_then_else (eq_attr "mcu_have_movw" "yes")
2070 (set_attr "cc" "set_czn,set_n,set_czn")])
2072 (define_insn "negsf2"
2073 [(set (match_operand:SF 0 "register_operand" "=d,r")
2074 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
2078 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
2079 [(set_attr "length" "1,4")
2080 (set_attr "cc" "set_n,set_n")])
2082 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2085 (define_insn "one_cmplqi2"
2086 [(set (match_operand:QI 0 "register_operand" "=r")
2087 (not:QI (match_operand:QI 1 "register_operand" "0")))]
2090 [(set_attr "length" "1")
2091 (set_attr "cc" "set_czn")])
2093 (define_insn "one_cmplhi2"
2094 [(set (match_operand:HI 0 "register_operand" "=r")
2095 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2099 [(set_attr "length" "2")
2100 (set_attr "cc" "set_n")])
2102 (define_insn "one_cmplsi2"
2103 [(set (match_operand:SI 0 "register_operand" "=r")
2104 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2110 [(set_attr "length" "4")
2111 (set_attr "cc" "set_n")])
2113 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2116 (define_insn "extendqihi2"
2117 [(set (match_operand:HI 0 "register_operand" "=r,r")
2118 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
2121 clr %B0\;sbrc %0,7\;com %B0
2122 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
2123 [(set_attr "length" "3,4")
2124 (set_attr "cc" "set_n,set_n")])
2126 (define_insn "extendqisi2"
2127 [(set (match_operand:SI 0 "register_operand" "=r,r")
2128 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
2131 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
2132 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
2133 [(set_attr "length" "5,6")
2134 (set_attr "cc" "set_n,set_n")])
2136 (define_insn "extendhisi2"
2137 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2138 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
2141 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
2142 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
2143 [(set_attr_alternative "length"
2145 (if_then_else (eq_attr "mcu_have_movw" "yes")
2148 (set_attr "cc" "set_n,set_n")])
2150 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2153 (define_insn_and_split "zero_extendqihi2"
2154 [(set (match_operand:HI 0 "register_operand" "=r")
2155 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
2159 [(set (match_dup 2) (match_dup 1))
2160 (set (match_dup 3) (const_int 0))]
2162 unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
2163 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
2165 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
2166 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
2169 (define_insn_and_split "zero_extendqisi2"
2170 [(set (match_operand:SI 0 "register_operand" "=r")
2171 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
2175 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
2176 (set (match_dup 3) (const_int 0))]
2178 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2179 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2181 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2182 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2185 (define_insn_and_split "zero_extendhisi2"
2186 [(set (match_operand:SI 0 "register_operand" "=r")
2187 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
2191 [(set (match_dup 2) (match_dup 1))
2192 (set (match_dup 3) (const_int 0))]
2194 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2195 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2197 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2198 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2201 (define_insn_and_split "zero_extendqidi2"
2202 [(set (match_operand:DI 0 "register_operand" "=r")
2203 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
2207 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2208 (set (match_dup 3) (const_int 0))]
2210 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2211 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2213 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2214 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2217 (define_insn_and_split "zero_extendhidi2"
2218 [(set (match_operand:DI 0 "register_operand" "=r")
2219 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
2223 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2224 (set (match_dup 3) (const_int 0))]
2226 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2227 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2229 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2230 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2233 (define_insn_and_split "zero_extendsidi2"
2234 [(set (match_operand:DI 0 "register_operand" "=r")
2235 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
2239 [(set (match_dup 2) (match_dup 1))
2240 (set (match_dup 3) (const_int 0))]
2242 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2243 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2245 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2246 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2249 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
2252 ; Optimize negated tests into reverse compare if overflow is undefined.
2253 (define_insn "*negated_tstqi"
2255 (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
2257 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2258 "cp __zero_reg__,%0"
2259 [(set_attr "cc" "compare")
2260 (set_attr "length" "1")])
2262 (define_insn "*reversed_tstqi"
2264 (compare (const_int 0)
2265 (match_operand:QI 0 "register_operand" "r")))]
2267 "cp __zero_reg__,%0"
2268 [(set_attr "cc" "compare")
2269 (set_attr "length" "2")])
2271 (define_insn "*negated_tsthi"
2273 (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
2275 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2276 "cp __zero_reg__,%A0
2277 cpc __zero_reg__,%B0"
2278 [(set_attr "cc" "compare")
2279 (set_attr "length" "2")])
2281 ;; Leave here the clobber used by the cmphi pattern for simplicity, even
2282 ;; though it is unused, because this pattern is synthesized by avr_reorg.
2283 (define_insn "*reversed_tsthi"
2285 (compare (const_int 0)
2286 (match_operand:HI 0 "register_operand" "r")))
2287 (clobber (match_scratch:QI 1 "=X"))]
2289 "cp __zero_reg__,%A0
2290 cpc __zero_reg__,%B0"
2291 [(set_attr "cc" "compare")
2292 (set_attr "length" "2")])
2294 (define_insn "*negated_tstsi"
2296 (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
2298 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2299 "cp __zero_reg__,%A0
2300 cpc __zero_reg__,%B0
2301 cpc __zero_reg__,%C0
2302 cpc __zero_reg__,%D0"
2303 [(set_attr "cc" "compare")
2304 (set_attr "length" "4")])
2306 (define_insn "*reversed_tstsi"
2308 (compare (const_int 0)
2309 (match_operand:SI 0 "register_operand" "r")))
2310 (clobber (match_scratch:QI 1 "=X"))]
2312 "cp __zero_reg__,%A0
2313 cpc __zero_reg__,%B0
2314 cpc __zero_reg__,%C0
2315 cpc __zero_reg__,%D0"
2316 [(set_attr "cc" "compare")
2317 (set_attr "length" "4")])
2320 (define_insn "*cmpqi"
2322 (compare (match_operand:QI 0 "register_operand" "r,r,d")
2323 (match_operand:QI 1 "nonmemory_operand" "L,r,i")))]
2329 [(set_attr "cc" "compare,compare,compare")
2330 (set_attr "length" "1,1,1")])
2332 (define_insn "*cmpqi_sign_extend"
2334 (compare (sign_extend:HI
2335 (match_operand:QI 0 "register_operand" "d"))
2336 (match_operand:HI 1 "const_int_operand" "n")))]
2337 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
2339 [(set_attr "cc" "compare")
2340 (set_attr "length" "1")])
2342 (define_insn "*cmphi"
2344 (compare (match_operand:HI 0 "register_operand" "!w,r,r,d,d,r,r")
2345 (match_operand:HI 1 "nonmemory_operand" "L,L,r,M,i,M,i")))
2346 (clobber (match_scratch:QI 2 "=X,X,X,X,&d,&d,&d"))]
2349 switch (which_alternative)
2352 return out_tsthi (insn, operands[0], NULL);
2355 return (AS2 (cp,%A0,%A1) CR_TAB
2358 if (reg_unused_after (insn, operands[0])
2359 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2360 && test_hard_reg_class (ADDW_REGS, operands[0]))
2361 return AS2 (sbiw,%0,%1);
2363 return (AS2 (cpi,%0,%1) CR_TAB
2364 AS2 (cpc,%B0,__zero_reg__));
2366 if (reg_unused_after (insn, operands[0]))
2367 return (AS2 (subi,%0,lo8(%1)) CR_TAB
2368 AS2 (sbci,%B0,hi8(%1)));
2370 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
2371 AS2 (cpi, %A0,lo8(%1)) CR_TAB
2374 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2375 AS2 (cp, %A0,%2) CR_TAB
2376 AS2 (cpc, %B0,__zero_reg__));
2379 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2380 AS2 (cp, %A0,%2) CR_TAB
2381 AS2 (ldi, %2,hi8(%1)) CR_TAB
2386 [(set_attr "cc" "compare,compare,compare,compare,compare,compare,compare")
2387 (set_attr "length" "1,2,2,2,3,3,4")])
2390 (define_insn "*cmpsi"
2392 (compare (match_operand:SI 0 "register_operand" "r,r,d,d,r,r")
2393 (match_operand:SI 1 "nonmemory_operand" "L,r,M,i,M,i")))
2394 (clobber (match_scratch:QI 2 "=X,X,X,&d,&d,&d"))]
2397 switch (which_alternative)
2400 return out_tstsi (insn, operands[0], NULL);
2403 return (AS2 (cp,%A0,%A1) CR_TAB
2404 AS2 (cpc,%B0,%B1) CR_TAB
2405 AS2 (cpc,%C0,%C1) CR_TAB
2408 if (reg_unused_after (insn, operands[0])
2409 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2410 && test_hard_reg_class (ADDW_REGS, operands[0]))
2411 return (AS2 (sbiw,%0,%1) CR_TAB
2412 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2413 AS2 (cpc,%D0,__zero_reg__));
2415 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
2416 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2417 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2418 AS2 (cpc,%D0,__zero_reg__));
2420 if (reg_unused_after (insn, operands[0]))
2421 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
2422 AS2 (sbci,%B0,hi8(%1)) CR_TAB
2423 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
2424 AS2 (sbci,%D0,hhi8(%1)));
2426 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB
2427 AS2 (ldi, %2,hi8(%1)) CR_TAB
2428 AS2 (cpc, %B0,%2) CR_TAB
2429 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2430 AS2 (cpc, %C0,%2) CR_TAB
2431 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2434 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
2435 AS2 (cp,%A0,%2) CR_TAB
2436 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2437 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2438 AS2 (cpc,%D0,__zero_reg__));
2440 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2441 AS2 (cp, %A0,%2) CR_TAB
2442 AS2 (ldi, %2,hi8(%1)) CR_TAB
2443 AS2 (cpc, %B0,%2) CR_TAB
2444 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2445 AS2 (cpc, %C0,%2) CR_TAB
2446 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2451 [(set_attr "cc" "compare,compare,compare,compare,compare,compare")
2452 (set_attr "length" "4,4,4,7,5,8")])
2455 ;; ----------------------------------------------------------------------
2456 ;; JUMP INSTRUCTIONS
2457 ;; ----------------------------------------------------------------------
2458 ;; Conditional jump instructions
2460 (define_expand "cbranchsi4"
2461 [(parallel [(set (cc0)
2462 (compare (match_operand:SI 1 "register_operand" "")
2463 (match_operand:SI 2 "nonmemory_operand" "")))
2464 (clobber (match_scratch:QI 4 ""))])
2467 (match_operator 0 "ordered_comparison_operator" [(cc0)
2469 (label_ref (match_operand 3 "" ""))
2473 (define_expand "cbranchhi4"
2474 [(parallel [(set (cc0)
2475 (compare (match_operand:HI 1 "register_operand" "")
2476 (match_operand:HI 2 "nonmemory_operand" "")))
2477 (clobber (match_scratch:QI 4 ""))])
2480 (match_operator 0 "ordered_comparison_operator" [(cc0)
2482 (label_ref (match_operand 3 "" ""))
2486 (define_expand "cbranchqi4"
2488 (compare (match_operand:QI 1 "register_operand" "")
2489 (match_operand:QI 2 "nonmemory_operand" "")))
2492 (match_operator 0 "ordered_comparison_operator" [(cc0)
2494 (label_ref (match_operand 3 "" ""))
2499 ;; Test a single bit in a QI/HI/SImode register.
2500 ;; Combine will create zero extract patterns for single bit tests.
2501 ;; permit any mode in source pattern by using VOIDmode.
2503 (define_insn "*sbrx_branch<mode>"
2506 (match_operator 0 "eqne_operator"
2508 (match_operand:VOID 1 "register_operand" "r")
2510 (match_operand 2 "const_int_operand" "n"))
2512 (label_ref (match_operand 3 "" ""))
2515 "* return avr_out_sbxx_branch (insn, operands);"
2516 [(set (attr "length")
2517 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2518 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2520 (if_then_else (eq_attr "mcu_mega" "no")
2523 (set_attr "cc" "clobber")])
2525 ;; Same test based on Bitwise AND RTL. Keep this incase gcc changes patterns.
2526 ;; or for old peepholes.
2527 ;; Fixme - bitwise Mask will not work for DImode
2529 (define_insn "*sbrx_and_branch<mode>"
2532 (match_operator 0 "eqne_operator"
2534 (match_operand:QISI 1 "register_operand" "r")
2535 (match_operand:QISI 2 "single_one_operand" "n"))
2537 (label_ref (match_operand 3 "" ""))
2541 HOST_WIDE_INT bitnumber;
2542 bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2]));
2543 operands[2] = GEN_INT (bitnumber);
2544 return avr_out_sbxx_branch (insn, operands);
2546 [(set (attr "length")
2547 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2548 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2550 (if_then_else (eq_attr "mcu_mega" "no")
2553 (set_attr "cc" "clobber")])
2555 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
2557 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2559 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2560 (label_ref (match_operand 1 "" ""))
2563 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
2567 (label_ref (match_dup 1))
2572 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2574 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2575 (label_ref (match_operand 1 "" ""))
2578 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
2582 (label_ref (match_dup 1))
2587 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2589 (clobber (match_operand:HI 2 ""))])
2590 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2591 (label_ref (match_operand 1 "" ""))
2594 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
2596 (label_ref (match_dup 1))
2601 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2603 (clobber (match_operand:HI 2 ""))])
2604 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2605 (label_ref (match_operand 1 "" ""))
2608 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
2610 (label_ref (match_dup 1))
2615 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2617 (clobber (match_operand:SI 2 ""))])
2618 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2619 (label_ref (match_operand 1 "" ""))
2622 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
2624 (label_ref (match_dup 1))
2626 "operands[2] = GEN_INT (-2147483647 - 1);")
2629 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2631 (clobber (match_operand:SI 2 ""))])
2632 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2633 (label_ref (match_operand 1 "" ""))
2636 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
2638 (label_ref (match_dup 1))
2640 "operands[2] = GEN_INT (-2147483647 - 1);")
2642 ;; ************************************************************************
2643 ;; Implementation of conditional jumps here.
2644 ;; Compare with 0 (test) jumps
2645 ;; ************************************************************************
2647 (define_insn "branch"
2649 (if_then_else (match_operator 1 "simple_comparison_operator"
2652 (label_ref (match_operand 0 "" ""))
2656 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2657 [(set_attr "type" "branch")
2658 (set_attr "cc" "clobber")])
2660 ;; ****************************************************************
2661 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
2662 ;; Convert them all to proper jumps.
2663 ;; ****************************************************************/
2665 (define_insn "difficult_branch"
2667 (if_then_else (match_operator 1 "difficult_comparison_operator"
2670 (label_ref (match_operand 0 "" ""))
2674 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2675 [(set_attr "type" "branch1")
2676 (set_attr "cc" "clobber")])
2680 (define_insn "rvbranch"
2682 (if_then_else (match_operator 1 "simple_comparison_operator"
2686 (label_ref (match_operand 0 "" ""))))]
2689 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2690 [(set_attr "type" "branch1")
2691 (set_attr "cc" "clobber")])
2693 (define_insn "difficult_rvbranch"
2695 (if_then_else (match_operator 1 "difficult_comparison_operator"
2699 (label_ref (match_operand 0 "" ""))))]
2702 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2703 [(set_attr "type" "branch")
2704 (set_attr "cc" "clobber")])
2706 ;; **************************************************************************
2707 ;; Unconditional and other jump instructions.
2711 (label_ref (match_operand 0 "" "")))]
2714 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
2715 return AS1 (jmp,%x0);
2716 return AS1 (rjmp,%x0);
2718 [(set (attr "length")
2719 (if_then_else (match_operand 0 "symbol_ref_operand" "")
2720 (if_then_else (eq_attr "mcu_mega" "no")
2723 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
2724 (le (minus (pc) (match_dup 0)) (const_int 2047)))
2727 (set_attr "cc" "none")])
2731 (define_expand "call"
2732 [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
2733 (match_operand:HI 1 "general_operand" ""))
2734 (use (const_int 0))])]
2735 ;; Operand 1 not used on the AVR.
2736 ;; Operand 2 is 1 for tail-call, 0 otherwise.
2740 (define_expand "sibcall"
2741 [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
2742 (match_operand:HI 1 "general_operand" ""))
2743 (use (const_int 1))])]
2744 ;; Operand 1 not used on the AVR.
2745 ;; Operand 2 is 1 for tail-call, 0 otherwise.
2751 (define_expand "call_value"
2752 [(parallel[(set (match_operand 0 "register_operand" "")
2753 (call (match_operand:HI 1 "call_insn_operand" "")
2754 (match_operand:HI 2 "general_operand" "")))
2755 (use (const_int 0))])]
2756 ;; Operand 2 not used on the AVR.
2757 ;; Operand 3 is 1 for tail-call, 0 otherwise.
2761 (define_expand "sibcall_value"
2762 [(parallel[(set (match_operand 0 "register_operand" "")
2763 (call (match_operand:HI 1 "call_insn_operand" "")
2764 (match_operand:HI 2 "general_operand" "")))
2765 (use (const_int 1))])]
2766 ;; Operand 2 not used on the AVR.
2767 ;; Operand 3 is 1 for tail-call, 0 otherwise.
2771 (define_insn "*call_insn"
2772 [(parallel[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s"))
2773 (match_operand:HI 1 "general_operand" "X,X,X,X"))
2774 (use (match_operand:HI 2 "const_int_operand" "L,L,P,P"))])]
2775 ;; Operand 1 not used on the AVR.
2776 ;; Operand 2 is 1 for tail-call, 0 otherwise.
2783 [(set_attr "cc" "clobber")
2784 (set_attr_alternative "length"
2786 (if_then_else (eq_attr "mcu_mega" "yes")
2790 (if_then_else (eq_attr "mcu_mega" "yes")
2794 (define_insn "*call_value_insn"
2795 [(parallel[(set (match_operand 0 "register_operand" "=r,r,r,r")
2796 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "z,s,z,s"))
2797 (match_operand:HI 2 "general_operand" "X,X,X,X")))
2798 (use (match_operand:HI 3 "const_int_operand" "L,L,P,P"))])]
2799 ;; Operand 2 not used on the AVR.
2800 ;; Operand 3 is 1 for tail-call, 0 otherwise.
2807 [(set_attr "cc" "clobber")
2808 (set_attr_alternative "length"
2810 (if_then_else (eq_attr "mcu_mega" "yes")
2814 (if_then_else (eq_attr "mcu_mega" "yes")
2822 [(set_attr "cc" "none")
2823 (set_attr "length" "1")])
2827 (define_expand "indirect_jump"
2828 [(set (pc) (match_operand:HI 0 "nonmemory_operand" ""))]
2830 " if ((!AVR_HAVE_JMP_CALL) && !register_operand(operand0, HImode))
2832 operands[0] = copy_to_mode_reg(HImode, operand0);
2837 (define_insn "*jcindirect_jump"
2838 [(set (pc) (match_operand:HI 0 "immediate_operand" "i"))]
2841 [(set_attr "length" "2")
2842 (set_attr "cc" "none")])
2845 (define_insn "*njcindirect_jump"
2846 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
2847 "!AVR_HAVE_EIJMP_EICALL"
2850 push %A0\;push %B0\;ret"
2851 [(set_attr "length" "1,3")
2852 (set_attr "cc" "none,none")])
2854 (define_insn "*indirect_jump_avr6"
2855 [(set (pc) (match_operand:HI 0 "register_operand" "z"))]
2856 "AVR_HAVE_EIJMP_EICALL"
2858 [(set_attr "length" "1")
2859 (set_attr "cc" "none")])
2863 ;; Table made from "rjmp" instructions for <=8K devices.
2864 (define_insn "*tablejump_rjmp"
2865 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
2867 (use (label_ref (match_operand 1 "" "")))
2868 (clobber (match_dup 0))]
2869 "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)"
2872 push %A0\;push %B0\;ret"
2873 [(set_attr "length" "1,3")
2874 (set_attr "cc" "none,none")])
2876 ;; Not a prologue, but similar idea - move the common piece of code to libgcc.
2877 (define_insn "*tablejump_lib"
2878 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2880 (use (label_ref (match_operand 1 "" "")))
2881 (clobber (match_dup 0))]
2882 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
2883 "%~jmp __tablejump2__"
2884 [(set_attr "length" "2")
2885 (set_attr "cc" "clobber")])
2887 (define_insn "*tablejump_enh"
2888 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2890 (use (label_ref (match_operand 1 "" "")))
2891 (clobber (match_dup 0))]
2892 "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX"
2899 [(set_attr "length" "6")
2900 (set_attr "cc" "clobber")])
2902 (define_insn "*tablejump"
2903 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2905 (use (label_ref (match_operand 1 "" "")))
2906 (clobber (match_dup 0))]
2907 "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL"
2916 [(set_attr "length" "8")
2917 (set_attr "cc" "clobber")])
2919 (define_expand "casesi"
2921 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
2922 (match_operand:HI 1 "register_operand" "")))
2923 (parallel [(set (cc0)
2924 (compare (match_dup 6)
2925 (match_operand:HI 2 "register_operand" "")))
2926 (clobber (match_scratch:QI 9 ""))])
2929 (if_then_else (gtu (cc0)
2931 (label_ref (match_operand 4 "" ""))
2935 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
2937 (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
2938 (use (label_ref (match_dup 3)))
2939 (clobber (match_dup 6))])]
2943 operands[6] = gen_reg_rtx (HImode);
2947 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2948 ;; This instruction sets Z flag
2951 [(set (cc0) (const_int 0))]
2954 [(set_attr "length" "1")
2955 (set_attr "cc" "compare")])
2957 ;; Clear/set/test a single bit in I/O address space.
2960 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2961 (and:QI (mem:QI (match_dup 0))
2962 (match_operand:QI 1 "single_zero_operand" "n")))]
2965 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
2966 return AS2 (cbi,%m0-0x20,%2);
2968 [(set_attr "length" "1")
2969 (set_attr "cc" "none")])
2972 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2973 (ior:QI (mem:QI (match_dup 0))
2974 (match_operand:QI 1 "single_one_operand" "n")))]
2977 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
2978 return AS2 (sbi,%m0-0x20,%2);
2980 [(set_attr "length" "1")
2981 (set_attr "cc" "none")])
2983 ;; Lower half of the I/O space - use sbic/sbis directly.
2984 (define_insn "*sbix_branch"
2987 (match_operator 0 "eqne_operator"
2989 (mem:QI (match_operand 1 "low_io_address_operand" "n"))
2991 (match_operand 2 "const_int_operand" "n"))
2993 (label_ref (match_operand 3 "" ""))
2996 "* return avr_out_sbxx_branch (insn, operands);"
2997 [(set (attr "length")
2998 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2999 (le (minus (pc) (match_dup 3)) (const_int 2046)))
3001 (if_then_else (eq_attr "mcu_mega" "no")
3004 (set_attr "cc" "clobber")])
3006 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
3007 (define_insn "*sbix_branch_bit7"
3010 (match_operator 0 "gelt_operator"
3011 [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
3013 (label_ref (match_operand 2 "" ""))
3017 operands[3] = operands[2];
3018 operands[2] = GEN_INT (7);
3019 return avr_out_sbxx_branch (insn, operands);
3021 [(set (attr "length")
3022 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
3023 (le (minus (pc) (match_dup 2)) (const_int 2046)))
3025 (if_then_else (eq_attr "mcu_mega" "no")
3028 (set_attr "cc" "clobber")])
3030 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
3031 (define_insn "*sbix_branch_tmp"
3034 (match_operator 0 "eqne_operator"
3036 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
3038 (match_operand 2 "const_int_operand" "n"))
3040 (label_ref (match_operand 3 "" ""))
3043 "* return avr_out_sbxx_branch (insn, operands);"
3044 [(set (attr "length")
3045 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
3046 (le (minus (pc) (match_dup 3)) (const_int 2045)))
3048 (if_then_else (eq_attr "mcu_mega" "no")
3051 (set_attr "cc" "clobber")])
3053 (define_insn "*sbix_branch_tmp_bit7"
3056 (match_operator 0 "gelt_operator"
3057 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
3059 (label_ref (match_operand 2 "" ""))
3063 operands[3] = operands[2];
3064 operands[2] = GEN_INT (7);
3065 return avr_out_sbxx_branch (insn, operands);
3067 [(set (attr "length")
3068 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
3069 (le (minus (pc) (match_dup 2)) (const_int 2045)))
3071 (if_then_else (eq_attr "mcu_mega" "no")
3074 (set_attr "cc" "clobber")])
3076 ;; ************************* Peepholes ********************************
3079 [(set (match_operand:SI 0 "d_register_operand" "")
3080 (plus:SI (match_dup 0)
3084 (compare (match_dup 0)
3086 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3088 (if_then_else (ne (cc0) (const_int 0))
3089 (label_ref (match_operand 2 "" ""))
3095 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3096 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
3097 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3098 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3100 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3101 AS2 (sbc,%B0,__zero_reg__) CR_TAB
3102 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3103 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3104 switch (avr_jump_mode (operands[2],insn))
3107 return AS1 (brcc,%2);
3109 return (AS1 (brcs,.+2) CR_TAB
3112 return (AS1 (brcs,.+4) CR_TAB
3117 [(set (match_operand:HI 0 "d_register_operand" "")
3118 (plus:HI (match_dup 0)
3122 (compare (match_dup 0)
3124 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3126 (if_then_else (ne (cc0) (const_int 0))
3127 (label_ref (match_operand 2 "" ""))
3133 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3134 output_asm_insn (AS2 (sbiw,%0,1), operands);
3136 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3137 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
3138 switch (avr_jump_mode (operands[2],insn))
3141 return AS1 (brcc,%2);
3143 return (AS1 (brcs,.+2) CR_TAB
3146 return (AS1 (brcs,.+4) CR_TAB
3151 [(set (match_operand:QI 0 "d_register_operand" "")
3152 (plus:QI (match_dup 0)
3155 (compare (match_dup 0)
3158 (if_then_else (ne (cc0) (const_int 0))
3159 (label_ref (match_operand 1 "" ""))
3165 cc_status.value1 = operands[0];
3166 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
3167 output_asm_insn (AS2 (subi,%A0,1), operands);
3168 switch (avr_jump_mode (operands[1],insn))
3171 return AS1 (brcc,%1);
3173 return (AS1 (brcs,.+2) CR_TAB
3176 return (AS1 (brcs,.+4) CR_TAB
3182 (compare (match_operand:QI 0 "register_operand" "")
3185 (if_then_else (eq (cc0) (const_int 0))
3186 (label_ref (match_operand 1 "" ""))
3188 "jump_over_one_insn_p (insn, operands[1])"
3189 "cpse %0,__zero_reg__")
3193 (compare (match_operand:QI 0 "register_operand" "")
3194 (match_operand:QI 1 "register_operand" "")))
3196 (if_then_else (eq (cc0) (const_int 0))
3197 (label_ref (match_operand 2 "" ""))
3199 "jump_over_one_insn_p (insn, operands[2])"
3202 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
3203 ;;prologue/epilogue support instructions
3205 (define_insn "popqi"
3206 [(set (match_operand:QI 0 "register_operand" "=r")
3207 (mem:QI (pre_inc:HI (reg:HI REG_SP))))]
3210 [(set_attr "cc" "none")
3211 (set_attr "length" "1")])
3213 ;; Enable Interrupts
3214 (define_insn "enable_interrupt"
3215 [(unspec_volatile [(const_int 1)] UNSPECV_ENABLE_IRQS)]
3218 [(set_attr "length" "1")
3219 (set_attr "cc" "none")])
3221 ;; Disable Interrupts
3222 (define_insn "disable_interrupt"
3223 [(unspec_volatile [(const_int 0)] UNSPECV_ENABLE_IRQS)]
3226 [(set_attr "length" "1")
3227 (set_attr "cc" "none")])
3229 ;; Library prologue saves
3230 (define_insn "call_prologue_saves"
3231 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
3232 (match_operand:HI 0 "immediate_operand" "")
3233 (set (reg:HI REG_SP) (minus:HI
3235 (match_operand:HI 1 "immediate_operand" "")))
3236 (use (reg:HI REG_X))
3237 (clobber (reg:HI REG_Z))]
3239 "ldi r30,lo8(gs(1f))
3241 %~jmp __prologue_saves__+((18 - %0) * 2)
3243 [(set_attr_alternative "length"
3244 [(if_then_else (eq_attr "mcu_mega" "yes")
3247 (set_attr "cc" "clobber")
3250 ; epilogue restores using library
3251 (define_insn "epilogue_restores"
3252 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
3253 (set (reg:HI REG_Y ) (plus:HI
3255 (match_operand:HI 0 "immediate_operand" "")))
3256 (set (reg:HI REG_SP) (reg:HI REG_Y))
3257 (clobber (reg:QI REG_Z))]
3260 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
3261 [(set_attr_alternative "length"
3262 [(if_then_else (eq_attr "mcu_mega" "yes")
3265 (set_attr "cc" "clobber")
3269 (define_insn "return"
3271 "reload_completed && avr_simple_epilogue ()"
3273 [(set_attr "cc" "none")
3274 (set_attr "length" "1")])
3276 (define_insn "return_from_epilogue"
3280 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
3281 && !cfun->machine->is_naked)"
3283 [(set_attr "cc" "none")
3284 (set_attr "length" "1")])
3286 (define_insn "return_from_interrupt_epilogue"
3290 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
3291 && !cfun->machine->is_naked)"
3293 [(set_attr "cc" "none")
3294 (set_attr "length" "1")])
3296 (define_insn "return_from_naked_epilogue"
3300 && cfun->machine->is_naked)"
3302 [(set_attr "cc" "none")
3303 (set_attr "length" "0")])
3305 (define_expand "prologue"
3314 (define_expand "epilogue"
3318 expand_epilogue (false /* sibcall_p */);
3322 (define_expand "sibcall_epilogue"
3326 expand_epilogue (true /* sibcall_p */);
3330 ;; Some instructions resp. instruction sequences available
3333 (define_insn "delay_cycles_1"
3334 [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
3336 UNSPECV_DELAY_CYCLES)
3337 (clobber (match_scratch:QI 1 "=&d"))]
3342 [(set_attr "length" "3")
3343 (set_attr "cc" "clobber")])
3345 (define_insn "delay_cycles_2"
3346 [(unspec_volatile [(match_operand:HI 0 "const_int_operand" "n")
3348 UNSPECV_DELAY_CYCLES)
3349 (clobber (match_scratch:HI 1 "=&w"))]
3355 [(set_attr "length" "4")
3356 (set_attr "cc" "clobber")])
3358 (define_insn "delay_cycles_3"
3359 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
3361 UNSPECV_DELAY_CYCLES)
3362 (clobber (match_scratch:QI 1 "=&d"))
3363 (clobber (match_scratch:QI 2 "=&d"))
3364 (clobber (match_scratch:QI 3 "=&d"))]
3373 [(set_attr "length" "7")
3374 (set_attr "cc" "clobber")])
3376 (define_insn "delay_cycles_4"
3377 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
3379 UNSPECV_DELAY_CYCLES)
3380 (clobber (match_scratch:QI 1 "=&d"))
3381 (clobber (match_scratch:QI 2 "=&d"))
3382 (clobber (match_scratch:QI 3 "=&d"))
3383 (clobber (match_scratch:QI 4 "=&d"))]
3394 [(set_attr "length" "9")
3395 (set_attr "cc" "clobber")])
3399 ;; NOP taking 1 or 2 Ticks
3401 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "P,K")]
3407 [(set_attr "length" "1")
3408 (set_attr "cc" "none")])
3411 (define_insn "sleep"
3412 [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)]
3415 [(set_attr "length" "1")
3416 (set_attr "cc" "none")])
3420 [(unspec_volatile [(const_int 0)] UNSPECV_WDR)]
3423 [(set_attr "length" "1")
3424 (set_attr "cc" "none")])
3427 (define_expand "fmul"
3429 (match_operand:QI 1 "register_operand" ""))
3431 (match_operand:QI 2 "register_operand" ""))
3432 (parallel [(set (reg:HI 22)
3433 (unspec:HI [(reg:QI 24)
3434 (reg:QI 25)] UNSPEC_FMUL))
3435 (clobber (reg:HI 24))])
3436 (set (match_operand:HI 0 "register_operand" "")
3442 emit_insn (gen_fmul_insn (operand0, operand1, operand2));
3447 (define_insn "fmul_insn"
3448 [(set (match_operand:HI 0 "register_operand" "=r")
3449 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
3450 (match_operand:QI 2 "register_operand" "a")]
3456 [(set_attr "length" "3")
3457 (set_attr "cc" "clobber")])
3459 (define_insn "*fmul.call"
3461 (unspec:HI [(reg:QI 24)
3462 (reg:QI 25)] UNSPEC_FMUL))
3463 (clobber (reg:HI 24))]
3466 [(set_attr "type" "xcall")
3467 (set_attr "cc" "clobber")])
3470 (define_expand "fmuls"
3472 (match_operand:QI 1 "register_operand" ""))
3474 (match_operand:QI 2 "register_operand" ""))
3475 (parallel [(set (reg:HI 22)
3476 (unspec:HI [(reg:QI 24)
3477 (reg:QI 25)] UNSPEC_FMULS))
3478 (clobber (reg:HI 24))])
3479 (set (match_operand:HI 0 "register_operand" "")
3485 emit_insn (gen_fmuls_insn (operand0, operand1, operand2));
3490 (define_insn "fmuls_insn"
3491 [(set (match_operand:HI 0 "register_operand" "=r")
3492 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
3493 (match_operand:QI 2 "register_operand" "a")]
3499 [(set_attr "length" "3")
3500 (set_attr "cc" "clobber")])
3502 (define_insn "*fmuls.call"
3504 (unspec:HI [(reg:QI 24)
3505 (reg:QI 25)] UNSPEC_FMULS))
3506 (clobber (reg:HI 24))]
3509 [(set_attr "type" "xcall")
3510 (set_attr "cc" "clobber")])
3513 (define_expand "fmulsu"
3515 (match_operand:QI 1 "register_operand" ""))
3517 (match_operand:QI 2 "register_operand" ""))
3518 (parallel [(set (reg:HI 22)
3519 (unspec:HI [(reg:QI 24)
3520 (reg:QI 25)] UNSPEC_FMULSU))
3521 (clobber (reg:HI 24))])
3522 (set (match_operand:HI 0 "register_operand" "")
3528 emit_insn (gen_fmulsu_insn (operand0, operand1, operand2));
3533 (define_insn "fmulsu_insn"
3534 [(set (match_operand:HI 0 "register_operand" "=r")
3535 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
3536 (match_operand:QI 2 "register_operand" "a")]
3542 [(set_attr "length" "3")
3543 (set_attr "cc" "clobber")])
3545 (define_insn "*fmulsu.call"
3547 (unspec:HI [(reg:QI 24)
3548 (reg:QI 25)] UNSPEC_FMULSU))
3549 (clobber (reg:HI 24))]
3552 [(set_attr "type" "xcall")
3553 (set_attr "cc" "clobber")])
3556 ;; Some combiner patterns dealing with bits.
3559 ;; Move bit $3.0 into bit $0.$4
3560 (define_insn "*movbitqi.1-6.a"
3561 [(set (match_operand:QI 0 "register_operand" "=r")
3562 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
3563 (match_operand:QI 2 "single_zero_operand" "n"))
3564 (and:QI (ashift:QI (match_operand:QI 3 "register_operand" "r")
3565 (match_operand:QI 4 "const_0_to_7_operand" "n"))
3566 (match_operand:QI 5 "single_one_operand" "n"))))]
3567 "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))
3568 && INTVAL(operands[4]) == exact_log2 (INTVAL(operands[5]) & GET_MODE_MASK (QImode))"
3569 "bst %3,0\;bld %0,%4"
3570 [(set_attr "length" "2")
3571 (set_attr "cc" "none")])
3573 ;; Move bit $3.0 into bit $0.$4
3574 ;; Variation of above. Unfortunately, there is no canonicalized representation
3575 ;; of moving around bits. So what we see here depends on how user writes down
3576 ;; bit manipulations.
3577 (define_insn "*movbitqi.1-6.b"
3578 [(set (match_operand:QI 0 "register_operand" "=r")
3579 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
3580 (match_operand:QI 2 "single_zero_operand" "n"))
3581 (ashift:QI (and:QI (match_operand:QI 3 "register_operand" "r")
3583 (match_operand:QI 4 "const_0_to_7_operand" "n"))))]
3584 "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
3585 "bst %3,0\;bld %0,%4"
3586 [(set_attr "length" "2")
3587 (set_attr "cc" "none")])
3589 ;; Move bit $3.0 into bit $0.0.
3590 ;; For bit 0, combiner generates slightly different pattern.
3591 (define_insn "*movbitqi.0"
3592 [(set (match_operand:QI 0 "register_operand" "=r")
3593 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
3594 (match_operand:QI 2 "single_zero_operand" "n"))
3595 (and:QI (match_operand:QI 3 "register_operand" "r")
3597 "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
3598 "bst %3,0\;bld %0,0"
3599 [(set_attr "length" "2")
3600 (set_attr "cc" "none")])
3602 ;; Move bit $2.0 into bit $0.7.
3603 ;; For bit 7, combiner generates slightly different pattern
3604 (define_insn "*movbitqi.7"
3605 [(set (match_operand:QI 0 "register_operand" "=r")
3606 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
3608 (ashift:QI (match_operand:QI 2 "register_operand" "r")
3611 "bst %2,0\;bld %0,7"
3612 [(set_attr "length" "2")
3613 (set_attr "cc" "none")])
3615 ;; Combiner transforms above four pattern into ZERO_EXTRACT if it sees MEM
3616 ;; and input/output match. We provide a special pattern for this, because
3617 ;; in contrast to a IN/BST/BLD/OUT sequence we need less registers and the
3618 ;; operation on I/O is atomic.
3619 (define_insn "*insv.io"
3620 [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "n,n,n"))
3622 (match_operand:QI 1 "const_0_to_7_operand" "n,n,n"))
3623 (match_operand:QI 2 "nonmemory_operand" "L,P,r"))]
3628 sbrc %2,0\;sbi %m0-0x20,%1\;sbrs %2,0\;cbi %m0-0x20,%1"
3629 [(set_attr "length" "1,1,4")
3630 (set_attr "cc" "none")])
3632 (define_insn "*insv.not.io"
3633 [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "n"))
3635 (match_operand:QI 1 "const_0_to_7_operand" "n"))
3636 (not:QI (match_operand:QI 2 "register_operand" "r")))]
3638 "sbrs %2,0\;sbi %m0-0x20,%1\;sbrc %2,0\;cbi %m0-0x20,%1"
3639 [(set_attr "length" "4")
3640 (set_attr "cc" "none")])
3642 ;; The insv expander.
3643 ;; We only support 1-bit inserts
3644 (define_expand "insv"
3645 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "")
3646 (match_operand:QI 1 "const1_operand" "") ; width
3647 (match_operand:QI 2 "const_0_to_7_operand" "")) ; pos
3648 (match_operand:QI 3 "nonmemory_operand" ""))]
3652 ;; Insert bit $2.0 into $0.$1
3653 (define_insn "*insv.reg"
3654 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
3656 (match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
3657 (match_operand:QI 2 "nonmemory_operand" "r,L,P,L,P"))]
3661 andi %0,lo8(~(1<<%1))
3665 [(set_attr "length" "2,1,1,2,2")
3666 (set_attr "cc" "none,set_zn,set_zn,none,none")])
3669 ;; Some combine patterns that try to fix bad code when a value is composed
3670 ;; from byte parts like in PR27663.
3671 ;; The patterns give some release but the code still is not optimal,
3672 ;; in particular when subreg lowering (-fsplit-wide-types) is turned on.
3673 ;; That switch obfuscates things here and in many other places.
3675 (define_insn_and_split "*ior<mode>qi.byte0"
3676 [(set (match_operand:HISI 0 "register_operand" "=r")
3678 (zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
3679 (match_operand:HISI 2 "register_operand" "0")))]
3684 (ior:QI (match_dup 3)
3687 operands[3] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, 0);
3690 (define_insn_and_split "*ior<mode>qi.byte1-3"
3691 [(set (match_operand:HISI 0 "register_operand" "=r")
3693 (ashift:HISI (zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
3694 (match_operand:QI 2 "const_8_16_24_operand" "n"))
3695 (match_operand:HISI 3 "register_operand" "0")))]
3696 "INTVAL(operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
3698 "&& reload_completed"
3700 (ior:QI (match_dup 4)
3703 int byteno = INTVAL(operands[2]) / BITS_PER_UNIT;
3704 operands[4] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, byteno);
3707 (define_expand "extzv"
3708 [(set (match_operand:QI 0 "register_operand" "")
3709 (zero_extract:QI (match_operand:QI 1 "register_operand" "")
3710 (match_operand:QI 2 "const1_operand" "")
3711 (match_operand:QI 3 "const_0_to_7_operand" "")))]
3715 (define_insn "*extzv"
3716 [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
3717 (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,0,r")
3719 (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,C04,n")))]
3723 mov %0,%1\;andi %0,1
3726 bst %1,%2\;clr %0\;bld %0,0"
3727 [(set_attr "length" "1,2,2,2,3")
3728 (set_attr "cc" "set_zn,set_zn,set_zn,set_zn,clobber")])
3730 (define_insn_and_split "*extzv.qihi1"
3731 [(set (match_operand:HI 0 "register_operand" "=r")
3732 (zero_extract:HI (match_operand:QI 1 "register_operand" "r")
3734 (match_operand:QI 2 "const_0_to_7_operand" "n")))]
3739 (zero_extract:QI (match_dup 1)
3745 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
3746 operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
3749 (define_insn_and_split "*extzv.qihi2"
3750 [(set (match_operand:HI 0 "register_operand" "=r")
3752 (zero_extract:QI (match_operand:QI 1 "register_operand" "r")
3754 (match_operand:QI 2 "const_0_to_7_operand" "n"))))]
3759 (zero_extract:QI (match_dup 1)
3765 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
3766 operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);