1 ;; Faraday FA606TE Pipeline Description
2 ;; Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 3, or (at your option) any later
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; These descriptions are based on the information contained in the
22 ;; FA606TE Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
24 ;; Modeled pipeline characteristics:
25 ;; LD -> any use: latency = 2 (1 cycle penalty).
26 ;; ALU -> any use: latency = 1 (0 cycle penalty).
28 ;; This automaton provides a pipeline description for the Faraday
31 ;; The model given here assumes that the condition for all conditional
32 ;; instructions is "true", i.e., that all of the instructions are
35 (define_automaton "fa606te")
37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
39 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
41 ;; There is a single pipeline
43 ;; The ALU pipeline has fetch, decode, execute, memory, and
44 ;; write stages. We only need to model the execute, memory and write
49 (define_cpu_unit "fa606te_core" "fa606te")
51 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
55 ;; ALU instructions require two cycles to execute, and use the ALU
56 ;; pipeline in each of the three stages. The results are available
57 ;; after the execute stage stage has finished.
59 ;; If the destination register is the PC, the pipelines are stalled
60 ;; for several cycles. That case is not modeled here.
63 (define_insn_reservation "606te_alu_op" 1
64 (and (eq_attr "tune" "fa606te")
65 (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg"))
68 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
69 ;; Multiplication Instructions
70 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
72 (define_insn_reservation "606te_mult1" 2
73 (and (eq_attr "tune" "fa606te")
74 (eq_attr "insn" "smlalxy"))
77 (define_insn_reservation "606te_mult2" 3
78 (and (eq_attr "tune" "fa606te")
79 (eq_attr "insn" "smlaxy,smulxy,smulwy,smlawy"))
82 (define_insn_reservation "606te_mult3" 4
83 (and (eq_attr "tune" "fa606te")
84 (eq_attr "insn" "mul,mla,muls,mlas"))
87 (define_insn_reservation "606te_mult4" 5
88 (and (eq_attr "tune" "fa606te")
89 (eq_attr "insn" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals"))
92 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
93 ;; Load/Store Instructions
94 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
96 ;; The models for load/store instructions do not accurately describe
97 ;; the difference between operations with a base register writeback
98 ;; (such as "ldm!"). These models assume that all memory references
101 (define_insn_reservation "606te_load1_op" 2
102 (and (eq_attr "tune" "fa606te")
103 (eq_attr "type" "load1,load_byte"))
106 (define_insn_reservation "606te_load2_op" 3
107 (and (eq_attr "tune" "fa606te")
108 (eq_attr "type" "load2"))
111 (define_insn_reservation "606te_load3_op" 4
112 (and (eq_attr "tune" "fa606te")
113 (eq_attr "type" "load3"))
116 (define_insn_reservation "606te_load4_op" 5
117 (and (eq_attr "tune" "fa606te")
118 (eq_attr "type" "load4"))
121 (define_insn_reservation "606te_store1_op" 0
122 (and (eq_attr "tune" "fa606te")
123 (eq_attr "type" "store1"))
126 (define_insn_reservation "606te_store2_op" 1
127 (and (eq_attr "tune" "fa606te")
128 (eq_attr "type" "store2"))
131 (define_insn_reservation "606te_store3_op" 2
132 (and (eq_attr "tune" "fa606te")
133 (eq_attr "type" "store3"))
136 (define_insn_reservation "606te_store4_op" 3
137 (and (eq_attr "tune" "fa606te")
138 (eq_attr "type" "store4"))
142 ;;(define_insn_reservation "606te_ldm_op" 9
143 ;; (and (eq_attr "tune" "fa606te")
144 ;; (eq_attr "type" "load2,load3,load4,store2,store3,store4"))
147 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
148 ;; Branch and Call Instructions
149 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
151 ;; Branch instructions are difficult to model accurately. The FA606TE
152 ;; core can predict most branches. If the branch is predicted
153 ;; correctly, and predicted early enough, the branch can be completely
154 ;; eliminated from the instruction stream. Some branches can
155 ;; therefore appear to require zero cycles to execute. We assume that
156 ;; all branches are predicted correctly, and that the latency is
157 ;; therefore the minimum value.
159 (define_insn_reservation "606te_branch_op" 0
160 (and (eq_attr "tune" "fa606te")
161 (eq_attr "type" "branch"))
164 ;; The latency for a call is actually the latency when the result is available.
165 ;; i.e. R0 ready for int return value. For most cases, the return value is set
166 ;; by a mov instruction, which has 1 cycle latency.
167 (define_insn_reservation "606te_call_op" 1
168 (and (eq_attr "tune" "fa606te")
169 (eq_attr "type" "call"))