1 ;; ARM Cortex-M4 FPU pipeline description
2 ;; Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Use an artifial unit to model FPU.
22 (define_cpu_unit "cortex_m4_v" "cortex_m4")
24 (define_reservation "cortex_m4_ex_v" "cortex_m4_ex+cortex_m4_v")
26 ;; Integer instructions following VDIV or VSQRT complete out-of-order.
27 (define_insn_reservation "cortex_m4_fdivs" 15
28 (and (eq_attr "tune" "cortexm4")
29 (eq_attr "type" "fdivs"))
30 "cortex_m4_ex_v,cortex_m4_v*13")
32 (define_insn_reservation "cortex_m4_vmov_1" 1
33 (and (eq_attr "tune" "cortexm4")
34 (eq_attr "type" "fcpys,fconsts"))
37 (define_insn_reservation "cortex_m4_vmov_2" 2
38 (and (eq_attr "tune" "cortexm4")
39 (eq_attr "type" "f_2_r,r_2_f"))
42 (define_insn_reservation "cortex_m4_fmuls" 2
43 (and (eq_attr "tune" "cortexm4")
44 (eq_attr "type" "fmuls"))
47 (define_insn_reservation "cortex_m4_fmacs" 4
48 (and (eq_attr "tune" "cortexm4")
49 (eq_attr "type" "fmacs,ffmas"))
52 (define_insn_reservation "cortex_m4_ffariths" 1
53 (and (eq_attr "tune" "cortexm4")
54 (eq_attr "type" "ffariths"))
57 (define_insn_reservation "cortex_m4_fadds" 2
58 (and (eq_attr "tune" "cortexm4")
59 (eq_attr "type" "fadds"))
62 (define_insn_reservation "cortex_m4_fcmps" 1
63 (and (eq_attr "tune" "cortexm4")
64 (eq_attr "type" "fcmps"))
67 (define_insn_reservation "cortex_m4_f_flag" 1
68 (and (eq_attr "tune" "cortexm4")
69 (eq_attr "type" "f_flag"))
72 (define_insn_reservation "cortex_m4_f_cvt" 2
73 (and (eq_attr "tune" "cortexm4")
74 (eq_attr "type" "f_cvt"))
77 (define_insn_reservation "cortex_m4_f_load" 2
78 (and (eq_attr "tune" "cortexm4")
79 (eq_attr "type" "f_loads"))
82 (define_insn_reservation "cortex_m4_f_store" 2
83 (and (eq_attr "tune" "cortexm4")
84 (eq_attr "type" "f_stores"))
87 (define_insn_reservation "cortex_m4_f_loadd" 3
88 (and (eq_attr "tune" "cortexm4")
89 (eq_attr "type" "f_loadd"))
92 (define_insn_reservation "cortex_m4_f_stored" 3
93 (and (eq_attr "tune" "cortexm4")
94 (eq_attr "type" "f_stored"))
97 ;; MAC instructions consume their addend one cycle later. If the result
98 ;; of an arithmetic instruction is consumed as the addend of the following
99 ;; MAC instruction, the latency can be decreased by one.
101 (define_bypass 1 "cortex_m4_fadds,cortex_m4_fmuls,cortex_m4_f_cvt"
103 "arm_no_early_mul_dep")
105 (define_bypass 3 "cortex_m4_fmacs"
107 "arm_no_early_mul_dep")
109 (define_bypass 14 "cortex_m4_fdivs"
111 "arm_no_early_mul_dep")