1 ;; Constraint definitions for ARM and Thumb
2 ;; Copyright (C) 2006-2013 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The following register constraints have been used:
22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
23 ;; - in Thumb state: h, b
24 ;; - in both states: l, c, k
25 ;; In ARM state, 'l' is an alias for 'r'
26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
28 ;; The following normal constraints have been used:
29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
30 ;; in Thumb-1 state: I, J, K, L, M, N, O
31 ;; 'H' was previously used for FPA.
33 ;; The following multi-letter normal constraints have been used:
34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dz
35 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
36 ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
38 ;; The following memory constraints have been used:
39 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
41 ;; in Thumb state: Uu, Uw
44 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
45 "The VFP registers @code{s0}-@code{s31}.")
47 (define_register_constraint "w"
48 "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
49 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
51 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
52 "The VFP registers @code{d0}-@code{d7}.")
54 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
55 "The Intel iWMMX co-processor registers.")
57 (define_register_constraint "z"
58 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
59 "The Intel iWMMX GR registers.")
61 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
62 "In Thumb state the core registers @code{r0}-@code{r7}.")
64 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
65 "In Thumb state the core registers @code{r8}-@code{r15}.")
67 (define_constraint "j"
68 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
69 (and (match_test "TARGET_32BIT && arm_arch_thumb2")
70 (ior (match_code "high")
71 (and (match_code "const_int")
72 (match_test "(ival & 0xffff0000) == 0")))))
74 (define_constraint "Pj"
75 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
76 (and (match_code "const_int")
77 (and (match_test "TARGET_THUMB2")
78 (match_test "(ival & 0xfffff000) == 0"))))
80 (define_constraint "PJ"
81 "@internal A constant that satisfies the Pj constrant if negated."
82 (and (match_code "const_int")
83 (and (match_test "TARGET_THUMB2")
84 (match_test "((-ival) & 0xfffff000) == 0"))))
86 (define_register_constraint "k" "STACK_REG"
87 "@internal The stack register.")
89 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
91 Thumb only. The union of the low registers and the stack register.")
93 (define_register_constraint "c" "CC_REG"
94 "@internal The condition code register.")
96 (define_constraint "I"
97 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
98 Data Processing instruction. In Thumb-1 state a constant in the range
100 (and (match_code "const_int")
101 (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
102 : ival >= 0 && ival <= 255")))
104 (define_constraint "J"
105 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
106 state a constant in the range @minus{}255-@minus{}1."
107 (and (match_code "const_int")
108 (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
109 : (ival >= -255 && ival <= -1)")))
111 (define_constraint "K"
112 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
113 inverted. In Thumb-1 state a constant that satisfies the @code{I}
114 constraint multiplied by any power of 2."
115 (and (match_code "const_int")
116 (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
117 : thumb_shiftable_const (ival)")))
119 (define_constraint "L"
120 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
121 negated. In Thumb-1 state a constant in the range @minus{}7-7."
122 (and (match_code "const_int")
123 (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
124 : (ival >= -7 && ival <= 7)")))
126 ;; The ARM state version is internal...
127 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
129 (define_constraint "M"
130 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
131 (and (match_code "const_int")
132 (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
133 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
134 : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
136 (define_constraint "N"
137 "Thumb-1 state a constant in the range 0-31."
138 (and (match_code "const_int")
139 (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
141 (define_constraint "O"
142 "In Thumb-1 state a constant that is a multiple of 4 in the range
144 (and (match_code "const_int")
145 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
146 && ((ival & 3) == 0)")))
148 (define_constraint "Pa"
149 "@internal In Thumb-1 state a constant in the range -510 to +510"
150 (and (match_code "const_int")
151 (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
152 && (ival > 255 || ival < -255)")))
154 (define_constraint "Pb"
155 "@internal In Thumb-1 state a constant in the range -262 to +262"
156 (and (match_code "const_int")
157 (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
158 && (ival > 255 || ival < -255)")))
160 (define_constraint "Pc"
161 "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
162 (and (match_code "const_int")
163 (match_test "TARGET_THUMB1
164 && ival > 1020 && ival <= 1275")))
166 (define_constraint "Pd"
167 "@internal In Thumb-1 state a constant in the range 0 to 7"
168 (and (match_code "const_int")
169 (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
171 (define_constraint "Pe"
172 "@internal In Thumb-1 state a constant in the range 256 to +510"
173 (and (match_code "const_int")
174 (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
176 (define_constraint "Ps"
177 "@internal In Thumb-2 state a constant in the range -255 to +255"
178 (and (match_code "const_int")
179 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
181 (define_constraint "Pt"
182 "@internal In Thumb-2 state a constant in the range -7 to +7"
183 (and (match_code "const_int")
184 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
186 (define_constraint "Pu"
187 "@internal In Thumb-2 state a constant in the range +1 to +8"
188 (and (match_code "const_int")
189 (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
191 (define_constraint "Pv"
192 "@internal In Thumb-2 state a constant in the range -255 to 0"
193 (and (match_code "const_int")
194 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
196 (define_constraint "Pw"
197 "@internal In Thumb-2 state a constant in the range -255 to -1"
198 (and (match_code "const_int")
199 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
201 (define_constraint "Px"
202 "@internal In Thumb-2 state a constant in the range -7 to -1"
203 (and (match_code "const_int")
204 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
206 (define_constraint "Py"
207 "@internal In Thumb-2 state a constant in the range 0 to 255"
208 (and (match_code "const_int")
209 (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
211 (define_constraint "G"
212 "In ARM/Thumb-2 state the floating-point constant 0."
213 (and (match_code "const_double")
214 (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
216 (define_constraint "Dz"
218 In ARM/Thumb-2 state a vector of constant zeros."
219 (and (match_code "const_vector")
220 (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
222 (define_constraint "Da"
224 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
225 be generated with two Data Processing insns."
226 (and (match_code "const_double,const_int,const_vector")
227 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
229 (define_constraint "Db"
231 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
232 be generated with three Data Processing insns."
233 (and (match_code "const_double,const_int,const_vector")
234 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
236 (define_constraint "Dc"
238 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
239 be generated with four Data Processing insns. This pattern is disabled
240 if optimizing for space or when we have load-delay slots to fill."
241 (and (match_code "const_double,const_int,const_vector")
242 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
243 && !(optimize_size || arm_ld_sched)")))
245 (define_constraint "Dd"
247 In ARM/Thumb-2 state a const_int that can be used by insn adddi."
248 (and (match_code "const_int")
249 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
251 (define_constraint "Di"
253 In ARM/Thumb-2 state a const_int or const_double where both the high
254 and low SImode words can be generated as immediates in 32-bit instructions."
255 (and (match_code "const_double,const_int")
256 (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
258 (define_constraint "Dn"
260 In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
261 Neon vmov immediate instruction."
262 (and (match_code "const_vector,const_int")
263 (match_test "TARGET_32BIT
264 && imm_for_neon_mov_operand (op, GET_MODE (op))")))
266 (define_constraint "Dl"
268 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
270 (and (match_code "const_vector")
271 (match_test "TARGET_32BIT
272 && imm_for_neon_logic_operand (op, GET_MODE (op))")))
274 (define_constraint "DL"
276 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
278 (and (match_code "const_vector")
279 (match_test "TARGET_32BIT
280 && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
282 (define_constraint "Do"
284 In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
285 (and (match_code "const_int")
286 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
288 (define_constraint "Dv"
290 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
292 (and (match_code "const_double")
293 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
295 (define_constraint "Dy"
297 In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
299 (and (match_code "const_double")
300 (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
302 (define_constraint "Dt"
304 In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
305 (and (match_code "const_double")
306 (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
308 (define_memory_constraint "Ua"
310 An address valid for loading/storing register exclusive"
311 (match_operand 0 "mem_noofs_operand"))
313 (define_memory_constraint "Ut"
315 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
316 types wider than TImode."
317 (and (match_code "mem")
318 (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
320 (define_memory_constraint "Uv"
322 In ARM/Thumb-2 state a valid VFP load/store address."
323 (and (match_code "mem")
324 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
326 (define_memory_constraint "Uy"
328 In ARM/Thumb-2 state a valid iWMMX load/store address."
329 (and (match_code "mem")
330 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
332 (define_memory_constraint "Un"
334 In ARM/Thumb-2 state a valid address for Neon doubleword vector
335 load/store instructions."
336 (and (match_code "mem")
337 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))
339 (define_memory_constraint "Um"
341 In ARM/Thumb-2 state a valid address for Neon element and structure
342 load/store instructions."
343 (and (match_code "mem")
344 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
346 (define_memory_constraint "Us"
348 In ARM/Thumb-2 state a valid address for non-offset loads/stores of
349 quad-word values in four ARM registers."
350 (and (match_code "mem")
351 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))
353 (define_memory_constraint "Uq"
355 In ARM state an address valid in ldrsb instructions."
356 (and (match_code "mem")
357 (match_test "TARGET_ARM
358 && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
361 (define_memory_constraint "Q"
363 In ARM/Thumb-2 state an address that is a single base register."
364 (and (match_code "mem")
365 (match_test "REG_P (XEXP (op, 0))")))
367 (define_memory_constraint "Uu"
369 In Thumb state an address that is valid in 16bit encoding."
370 (and (match_code "mem")
371 (match_test "TARGET_THUMB
372 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
375 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
376 ; are actually LDM/STM instructions, so cannot be used to access unaligned
378 (define_memory_constraint "Uw"
380 In Thumb state an address that is valid in 16bit encoding, and that can be
381 used for unaligned accesses."
382 (and (match_code "mem")
383 (match_test "TARGET_THUMB
384 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
386 && GET_CODE (XEXP (op, 0)) != POST_INC")))
388 ;; We used to have constraint letters for S and R in ARM state, but
389 ;; all uses of these now appear to have been removed.
391 ;; Additionally, we used to have a Q constraint in Thumb state, but
392 ;; this wasn't really a valid memory constraint. Again, all uses of
393 ;; this now seem to have been removed.