1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
27 /* We can't use enum machine_mode inside a generator file because it
28 hasn't been created yet; we shouldn't be using any code that
29 needs the real definition though, so this ought to be safe. */
33 #include "insn-modes.h"
34 #define MACHMODE enum machine_mode
37 #include "config/vxworks-dummy.h"
39 /* The architecture define. */
40 extern char arm_arch_name[];
42 /* Target CPU builtins. */
43 #define TARGET_CPU_CPP_BUILTINS() \
46 if (TARGET_DSP_MULTIPLY) \
47 builtin_define ("__ARM_FEATURE_DSP"); \
48 if (TARGET_ARM_QBIT) \
49 builtin_define ("__ARM_FEATURE_QBIT"); \
51 builtin_define ("__ARM_FEATURE_SAT"); \
52 if (unaligned_access) \
53 builtin_define ("__ARM_FEATURE_UNALIGNED"); \
54 if (TARGET_ARM_FEATURE_LDREX) \
55 builtin_define_with_int_value ( \
56 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \
57 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \
58 || TARGET_ARM_ARCH_ISA_THUMB >=2) \
59 builtin_define ("__ARM_FEATURE_CLZ"); \
60 if (TARGET_INT_SIMD) \
61 builtin_define ("__ARM_FEATURE_SIMD32"); \
63 builtin_define_with_int_value ( \
64 "__ARM_SIZEOF_MINIMAL_ENUM", \
65 flag_short_enums ? 1 : 4); \
66 builtin_define_with_int_value ( \
67 "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \
68 if (TARGET_ARM_ARCH_PROFILE) \
69 builtin_define_with_int_value ( \
70 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \
72 /* Define __arm__ even when in thumb mode, for \
73 consistency with armcc. */ \
74 builtin_define ("__arm__"); \
75 if (TARGET_ARM_ARCH) \
76 builtin_define_with_int_value ( \
77 "__ARM_ARCH", TARGET_ARM_ARCH); \
79 builtin_define ("__ARM_ARCH_ISA_ARM"); \
80 builtin_define ("__APCS_32__"); \
82 builtin_define ("__thumb__"); \
84 builtin_define ("__thumb2__"); \
85 if (TARGET_ARM_ARCH_ISA_THUMB) \
86 builtin_define_with_int_value ( \
87 "__ARM_ARCH_ISA_THUMB", \
88 TARGET_ARM_ARCH_ISA_THUMB); \
92 builtin_define ("__ARMEB__"); \
93 builtin_define ("__ARM_BIG_ENDIAN"); \
95 builtin_define ("__THUMBEB__"); \
96 if (TARGET_LITTLE_WORDS) \
97 builtin_define ("__ARMWEL__"); \
101 builtin_define ("__ARMEL__"); \
103 builtin_define ("__THUMBEL__"); \
106 if (TARGET_SOFT_FLOAT) \
107 builtin_define ("__SOFTFP__"); \
110 builtin_define ("__VFP_FP__"); \
113 builtin_define_with_int_value ( \
114 "__ARM_FP", TARGET_ARM_FP); \
115 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \
116 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \
117 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \
118 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \
120 builtin_define ("__ARM_FEATURE_FMA"); \
124 builtin_define ("__ARM_NEON__"); \
125 builtin_define ("__ARM_NEON"); \
127 if (TARGET_NEON_FP) \
128 builtin_define_with_int_value ( \
129 "__ARM_NEON_FP", TARGET_NEON_FP); \
131 /* Add a define for interworking. \
132 Needed when building libgcc.a. */ \
133 if (arm_cpp_interwork) \
134 builtin_define ("__THUMB_INTERWORK__"); \
136 builtin_assert ("cpu=arm"); \
137 builtin_assert ("machine=arm"); \
139 builtin_define (arm_arch_name); \
140 if (arm_arch_xscale) \
141 builtin_define ("__XSCALE__"); \
142 if (arm_arch_iwmmxt) \
144 builtin_define ("__IWMMXT__"); \
145 builtin_define ("__ARM_WMMX"); \
147 if (arm_arch_iwmmxt2) \
148 builtin_define ("__IWMMXT2__"); \
149 if (TARGET_AAPCS_BASED) \
151 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
152 builtin_define ("__ARM_PCS_VFP"); \
153 else if (arm_pcs_default == ARM_PCS_AAPCS) \
154 builtin_define ("__ARM_PCS"); \
155 builtin_define ("__ARM_EABI__"); \
158 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
161 #include "config/arm/arm-opts.h"
165 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
167 #include "arm-cores.def"
172 /* The processor for which instructions should be scheduled. */
173 extern enum processor_type arm_tune;
175 typedef enum arm_cond_code
177 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
178 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
182 extern arm_cc arm_current_cc;
184 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
186 extern int arm_target_label;
187 extern int arm_ccfsm_state;
188 extern GTY(()) rtx arm_target_insn;
189 /* The label of the current constant pool. */
190 extern rtx pool_vector_label;
191 /* Set to 1 when a return insn is output, this means that the epilogue
193 extern int return_used_this_function;
194 /* Callback to output language specific object attributes. */
195 extern void (*arm_lang_output_object_attributes_hook)(void);
197 /* Just in case configure has failed to define anything. */
198 #ifndef TARGET_CPU_DEFAULT
199 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
204 #define CPP_SPEC "%(subtarget_cpp_spec) \
205 %{mfloat-abi=soft:%{mfloat-abi=hard: \
206 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
207 %{mbig-endian:%{mlittle-endian: \
208 %e-mbig-endian and -mlittle-endian may not be used together}}"
214 /* This macro defines names of additional specifications to put in the specs
215 that can be used in various specifications like CC1_SPEC. Its definition
216 is an initializer with a subgrouping for each command option.
218 Each subgrouping contains a string constant, that defines the
219 specification name, and a string constant that used by the GCC driver
222 Do not define this macro if it does not need to do anything. */
223 #define EXTRA_SPECS \
224 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
225 { "asm_cpu_spec", ASM_CPU_SPEC }, \
226 SUBTARGET_EXTRA_SPECS
228 #ifndef SUBTARGET_EXTRA_SPECS
229 #define SUBTARGET_EXTRA_SPECS
232 #ifndef SUBTARGET_CPP_SPEC
233 #define SUBTARGET_CPP_SPEC ""
236 /* Run-time Target Specification. */
237 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
238 /* Use hardware floating point instructions. */
239 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
240 /* Use hardware floating point calling convention. */
241 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
242 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
243 #define TARGET_IWMMXT (arm_arch_iwmmxt)
244 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
245 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
246 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT)
247 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
248 #define TARGET_ARM (! TARGET_THUMB)
249 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
250 #define TARGET_BACKTRACE (leaf_function_p () \
251 ? TARGET_TPCS_LEAF_FRAME \
253 #define TARGET_AAPCS_BASED \
254 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
256 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
257 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
258 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
260 /* Only 16-bit thumb code. */
261 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
262 /* Arm or Thumb-2 32-bit code. */
263 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
264 /* 32-bit Thumb-2 code. */
265 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
267 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
269 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \
272 /* The following two macros concern the ability to execute coprocessor
273 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
274 only ever tested when we know we are generating for VFP hardware; we need
275 to be more careful with TARGET_NEON as noted below. */
277 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
278 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
280 /* FPU supports VFPv3 instructions. */
281 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
283 /* FPU only supports VFP single-precision instructions. */
284 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
286 /* FPU supports VFP double-precision instructions. */
287 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
289 /* FPU supports half-precision floating-point with NEON element load/store. */
290 #define TARGET_NEON_FP16 \
291 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
293 /* FPU supports VFP half-precision floating-point. */
294 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
296 /* FPU supports fused-multiply-add operations. */
297 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
299 /* FPU is ARMv8 compatible. */
300 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8)
302 /* FPU supports Crypto extensions. */
303 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
305 /* FPU supports Neon instructions. The setting of this macro gets
306 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
307 and TARGET_HARD_FLOAT to ensure that NEON instructions are
309 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
310 && TARGET_VFP && arm_fpu_desc->neon)
312 /* Q-bit is present. */
313 #define TARGET_ARM_QBIT \
314 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
315 /* Saturation operation, e.g. SSAT. */
316 #define TARGET_ARM_SAT \
317 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
318 /* "DSP" multiply instructions, eg. SMULxy. */
319 #define TARGET_DSP_MULTIPLY \
320 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
321 /* Integer SIMD instructions, and extend-accumulate instructions. */
322 #define TARGET_INT_SIMD \
323 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
325 /* Should MOVW/MOVT be used in preference to a constant pool. */
326 #define TARGET_USE_MOVT \
327 (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
329 /* We could use unified syntax for arm mode, but for now we just use it
331 #define TARGET_UNIFIED_ASM TARGET_THUMB2
333 /* Nonzero if this chip provides the DMB instruction. */
334 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
336 /* Nonzero if this chip implements a memory barrier via CP15. */
337 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
340 /* Nonzero if this chip implements a memory barrier instruction. */
341 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
343 /* Nonzero if this chip supports ldrex and strex */
344 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
346 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
347 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
349 /* Nonzero if this chip supports ldrexd and strexd. */
350 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
353 /* Nonzero if integer division instructions supported. */
354 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
355 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
357 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
358 then TARGET_AAPCS_BASED must be true -- but the converse does not
359 hold. TARGET_BPABI implies the use of the BPABI runtime library,
360 etc., in addition to just the AAPCS calling conventions. */
362 #define TARGET_BPABI false
365 /* Support for a compile-time default CPU, et cetera. The rules are:
366 --with-arch is ignored if -march or -mcpu are specified.
367 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
369 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
371 --with-float is ignored if -mfloat-abi is specified.
372 --with-fpu is ignored if -mfpu is specified.
373 --with-abi is ignored if -mabi is specified.
374 --with-tls is ignored if -mtls-dialect is specified. */
375 #define OPTION_DEFAULT_SPECS \
376 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
377 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
378 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
379 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
380 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
381 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
382 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
383 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
385 /* Which floating point model to use. */
388 ARM_FP_MODEL_UNKNOWN,
389 /* VFP floating point model. */
401 extern const struct arm_fpu_desc
404 enum arm_fp_model model;
406 enum vfp_reg_type regs;
412 /* Which floating point hardware to schedule for. */
413 extern int arm_fpu_attr;
415 #ifndef TARGET_DEFAULT_FLOAT_ABI
416 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
419 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
420 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
422 #ifndef ARM_DEFAULT_ABI
423 #define ARM_DEFAULT_ABI ARM_ABI_APCS
426 /* Map each of the micro-architecture variants to their corresponding
427 major architecture revision. */
429 enum base_architecture
457 /* The major revision number of the ARM Architecture implemented by the target. */
458 extern enum base_architecture arm_base_arch;
460 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
461 extern int arm_arch3m;
463 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
464 extern int arm_arch4;
466 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
467 extern int arm_arch4t;
469 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
470 extern int arm_arch5;
472 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
473 extern int arm_arch5e;
475 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
476 extern int arm_arch6;
478 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
479 extern int arm_arch6k;
481 /* Nonzero if instructions present in ARMv6-M can be used. */
482 extern int arm_arch6m;
484 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
485 extern int arm_arch7;
487 /* Nonzero if instructions not present in the 'M' profile can be used. */
488 extern int arm_arch_notm;
490 /* Nonzero if instructions present in ARMv7E-M can be used. */
491 extern int arm_arch7em;
493 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */
494 extern int arm_arch8;
496 /* Nonzero if this chip can benefit from load scheduling. */
497 extern int arm_ld_sched;
499 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
500 extern int thumb_code;
502 /* Nonzero if generating Thumb-1 code. */
503 extern int thumb1_code;
505 /* Nonzero if this chip is a StrongARM. */
506 extern int arm_tune_strongarm;
508 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
509 extern int arm_arch_iwmmxt;
511 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
512 extern int arm_arch_iwmmxt2;
514 /* Nonzero if this chip is an XScale. */
515 extern int arm_arch_xscale;
517 /* Nonzero if tuning for XScale. */
518 extern int arm_tune_xscale;
520 /* Nonzero if tuning for stores via the write buffer. */
521 extern int arm_tune_wbuf;
523 /* Nonzero if tuning for Cortex-A9. */
524 extern int arm_tune_cortex_a9;
526 /* Nonzero if we should define __THUMB_INTERWORK__ in the
528 XXX This is a bit of a hack, it's intended to help work around
529 problems in GLD which doesn't understand that armv5t code is
530 interworking clean. */
531 extern int arm_cpp_interwork;
533 /* Nonzero if chip supports Thumb 2. */
534 extern int arm_arch_thumb2;
536 /* Nonzero if chip supports integer division instruction in ARM mode. */
537 extern int arm_arch_arm_hwdiv;
539 /* Nonzero if chip supports integer division instruction in Thumb mode. */
540 extern int arm_arch_thumb_hwdiv;
542 #ifndef TARGET_DEFAULT
543 #define TARGET_DEFAULT (MASK_APCS_FRAME)
546 /* Nonzero if PIC code requires explicit qualifiers to generate
547 PLT and GOT relocs rather than the assembler doing so implicitly.
548 Subtargets can override these if required. */
549 #ifndef NEED_GOT_RELOC
550 #define NEED_GOT_RELOC 0
552 #ifndef NEED_PLT_RELOC
553 #define NEED_PLT_RELOC 0
556 /* Nonzero if we need to refer to the GOT with a PC-relative
557 offset. In other words, generate
559 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
563 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
565 The default is true, which matches NetBSD. Subtargets can
566 override this if required. */
571 /* Target machine storage Layout. */
574 /* Define this macro if it is advisable to hold scalars in registers
575 in a wider mode than that declared by the program. In such cases,
576 the value is constrained to be within the bounds of the declared
577 type, but kept valid in the wider mode. The signedness of the
578 extension may differ from that of the type. */
580 /* It is far faster to zero extend chars than to sign extend them */
582 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
583 if (GET_MODE_CLASS (MODE) == MODE_INT \
584 && GET_MODE_SIZE (MODE) < 4) \
586 if (MODE == QImode) \
588 else if (MODE == HImode) \
593 /* Define this if most significant bit is lowest numbered
594 in instructions that operate on numbered bit-fields. */
595 #define BITS_BIG_ENDIAN 0
597 /* Define this if most significant byte of a word is the lowest numbered.
598 Most ARM processors are run in little endian mode, so that is the default.
599 If you want to have it run-time selectable, change the definition in a
600 cover file to be TARGET_BIG_ENDIAN. */
601 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
603 /* Define this if most significant word of a multiword number is the lowest
605 This is always false, even when in big-endian mode. */
606 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
608 #define UNITS_PER_WORD 4
610 /* True if natural alignment is used for doubleword types. */
611 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
613 #define DOUBLEWORD_ALIGNMENT 64
615 #define PARM_BOUNDARY 32
617 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
619 #define PREFERRED_STACK_BOUNDARY \
620 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
622 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
624 /* The lowest bit is used to indicate Thumb-mode functions, so the
625 vbit must go into the delta field of pointers to member
627 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
629 #define EMPTY_FIELD_BOUNDARY 32
631 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
633 /* XXX Blah -- this macro is used directly by libobjc. Since it
634 supports no vector modes, cut out the complexity and fall back
635 on BIGGEST_FIELD_ALIGNMENT. */
636 #ifdef IN_TARGET_LIBS
637 #define BIGGEST_FIELD_ALIGNMENT 64
640 /* Make strings word-aligned so strcpy from constants will be faster. */
641 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
643 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
644 ((TREE_CODE (EXP) == STRING_CST \
646 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
647 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
649 /* Align definitions of arrays, unions and structures so that
650 initializations and copies can be made more efficient. This is not
651 ABI-changing, so it only affects places where we can see the
652 definition. Increasing the alignment tends to introduce padding,
653 so don't do this when optimizing for size/conserving stack space. */
654 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
655 (((COND) && ((ALIGN) < BITS_PER_WORD) \
656 && (TREE_CODE (EXP) == ARRAY_TYPE \
657 || TREE_CODE (EXP) == UNION_TYPE \
658 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
660 /* Align global data. */
661 #define DATA_ALIGNMENT(EXP, ALIGN) \
662 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
664 /* Similarly, make sure that objects on the stack are sensibly aligned. */
665 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
666 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
668 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
669 value set in previous versions of this toolchain was 8, which produces more
670 compact structures. The command line option -mstructure_size_boundary=<n>
671 can be used to change this value. For compatibility with the ARM SDK
672 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
673 0020D) page 2-20 says "Structures are aligned on word boundaries".
674 The AAPCS specifies a value of 8. */
675 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
677 /* This is the value used to initialize arm_structure_size_boundary. If a
678 particular arm target wants to change the default value it should change
679 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
680 for an example of this. */
681 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
682 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
685 /* Nonzero if move instructions will actually fail to work
686 when given unaligned data. */
687 #define STRICT_ALIGNMENT 1
689 /* wchar_t is unsigned under the AAPCS. */
691 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
693 #define WCHAR_TYPE_SIZE BITS_PER_WORD
696 /* Sized for fixed-point types. */
698 #define SHORT_FRACT_TYPE_SIZE 8
699 #define FRACT_TYPE_SIZE 16
700 #define LONG_FRACT_TYPE_SIZE 32
701 #define LONG_LONG_FRACT_TYPE_SIZE 64
703 #define SHORT_ACCUM_TYPE_SIZE 16
704 #define ACCUM_TYPE_SIZE 32
705 #define LONG_ACCUM_TYPE_SIZE 64
706 #define LONG_LONG_ACCUM_TYPE_SIZE 64
708 #define MAX_FIXED_MODE_SIZE 64
711 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
715 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
718 /* AAPCS requires that structure alignment is affected by bitfields. */
719 #ifndef PCC_BITFIELD_TYPE_MATTERS
720 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
724 /* Standard register usage. */
726 /* Register allocation in ARM Procedure Call Standard
727 (S - saved over call).
729 r0 * argument word/integer result
732 r4-r8 S register variable
733 r9 S (rfp) register variable (real frame pointer)
735 r10 F S (sl) stack limit (used by -mapcs-stack-check)
736 r11 F S (fp) argument pointer
737 r12 (ip) temp workspace
738 r13 F S (sp) lower end of current stack frame
739 r14 (lr) link address/workspace
740 r15 F (pc) program counter
742 cc This is NOT a real register, but is used internally
743 to represent things that use or set the condition
745 sfp This isn't either. It is used during rtl generation
746 since the offset between the frame pointer and the
747 auto's isn't known until after register allocation.
748 afp Nor this, we only need this because of non-local
749 goto. Without it fp appears to be used and the
750 elimination code won't get rid of sfp. It tracks
751 fp exactly at all times.
753 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
755 /* s0-s15 VFP scratch (aka d0-d7).
756 s16-s31 S VFP variable (aka d8-d15).
757 vfpcc Not a real register. Represents the VFP condition
760 /* The stack backtrace structure is as follows:
761 fp points to here: | save code pointer | [fp]
762 | return link value | [fp, #-4]
763 | return sp value | [fp, #-8]
764 | return fp value | [fp, #-12]
765 [| saved r10 value |]
776 r0-r3 are not normally saved in a C function. */
778 /* 1 for registers that have pervasive standard uses
779 and are not available for the register allocator. */
780 #define FIXED_REGISTERS \
802 /* 1 for registers not available across function calls.
803 These must include the FIXED_REGISTERS and also any
804 registers that can be used without being saved.
805 The latter must include the registers where values are returned
806 and the register where structure-value addresses are passed.
807 Aside from that, you can include as many other registers as you like.
808 The CC is not preserved over function calls on the ARM 6, so it is
809 easier to assume this for all. SFP is preserved, since FP is. */
810 #define CALL_USED_REGISTERS \
832 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
833 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
836 /* These are a couple of extensions to the formats accepted
838 %@ prints out ASM_COMMENT_START
839 %r prints out REGISTER_PREFIX reg_names[arg] */
840 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
842 fputs (ASM_COMMENT_START, FILE); \
846 fputs (REGISTER_PREFIX, FILE); \
847 fputs (reg_names [va_arg (ARGS, int)], FILE); \
850 /* Round X up to the nearest word. */
851 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
853 /* Convert fron bytes to ints. */
854 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
856 /* The number of (integer) registers required to hold a quantity of type MODE.
857 Also used for VFP registers. */
858 #define ARM_NUM_REGS(MODE) \
859 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
861 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
862 #define ARM_NUM_REGS2(MODE, TYPE) \
863 ARM_NUM_INTS ((MODE) == BLKmode ? \
864 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
866 /* The number of (integer) argument register available. */
867 #define NUM_ARG_REGS 4
869 /* And similarly for the VFP. */
870 #define NUM_VFP_ARG_REGS 16
872 /* Return the register number of the N'th (integer) argument. */
873 #define ARG_REGISTER(N) (N - 1)
875 /* Specify the registers used for certain standard purposes.
876 The values of these macros are register numbers. */
878 /* The number of the last argument register. */
879 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
881 /* The numbers of the Thumb register ranges. */
882 #define FIRST_LO_REGNUM 0
883 #define LAST_LO_REGNUM 7
884 #define FIRST_HI_REGNUM 8
885 #define LAST_HI_REGNUM 11
887 /* Overridden by config/arm/bpabi.h. */
888 #ifndef ARM_UNWIND_INFO
889 #define ARM_UNWIND_INFO 0
892 /* Use r0 and r1 to pass exception handling information. */
893 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
895 /* The register that holds the return address in exception handlers. */
896 #define ARM_EH_STACKADJ_REGNUM 2
897 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
899 #ifndef ARM_TARGET2_DWARF_FORMAT
900 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
902 /* ttype entries (the only interesting data references used)
903 use TARGET2 relocations. */
904 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
905 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
909 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
910 as an invisible last argument (possible since varargs don't exist in
911 Pascal), so the following is not true. */
912 #define STATIC_CHAIN_REGNUM 12
914 /* Define this to be where the real frame pointer is if it is not possible to
915 work out the offset between the frame pointer and the automatic variables
916 until after register allocation has taken place. FRAME_POINTER_REGNUM
917 should point to a special register that we will make sure is eliminated.
919 For the Thumb we have another problem. The TPCS defines the frame pointer
920 as r11, and GCC believes that it is always possible to use the frame pointer
921 as base register for addressing purposes. (See comments in
922 find_reloads_address()). But - the Thumb does not allow high registers,
923 including r11, to be used as base address registers. Hence our problem.
925 The solution used here, and in the old thumb port is to use r7 instead of
926 r11 as the hard frame pointer and to have special code to generate
927 backtrace structures on the stack (if required to do so via a command line
928 option) using r11. This is the only 'user visible' use of r11 as a frame
930 #define ARM_HARD_FRAME_POINTER_REGNUM 11
931 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
933 #define HARD_FRAME_POINTER_REGNUM \
935 ? ARM_HARD_FRAME_POINTER_REGNUM \
936 : THUMB_HARD_FRAME_POINTER_REGNUM)
938 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
939 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
941 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
943 /* Register to use for pushing function arguments. */
944 #define STACK_POINTER_REGNUM SP_REGNUM
946 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
947 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
948 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
949 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
951 #define IS_IWMMXT_REGNUM(REGNUM) \
952 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
953 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
954 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
956 /* Base register for access to local variables of the function. */
957 #define FRAME_POINTER_REGNUM 102
959 /* Base register for access to arguments of the function. */
960 #define ARG_POINTER_REGNUM 103
962 #define FIRST_VFP_REGNUM 16
963 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
964 #define LAST_VFP_REGNUM \
965 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
967 #define IS_VFP_REGNUM(REGNUM) \
968 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
970 /* VFP registers are split into two types: those defined by VFP versions < 3
971 have D registers overlaid on consecutive pairs of S registers. VFP version 3
972 defines 16 new D registers (d16-d31) which, for simplicity and correctness
973 in various parts of the backend, we implement as "fake" single-precision
974 registers (which would be S32-S63, but cannot be used in that way). The
975 following macros define these ranges of registers. */
976 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
977 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
978 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
980 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
981 ((REGNUM) <= LAST_LO_VFP_REGNUM)
983 /* DFmode values are only valid in even register pairs. */
984 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
985 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
987 /* Neon Quad values must start at a multiple of four registers. */
988 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
989 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
991 /* Neon structures of vectors must be in even register pairs and there
992 must be enough registers available. Because of various patterns
993 requiring quad registers, we require them to start at a multiple of
995 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
996 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
997 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
999 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
1000 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1001 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
1002 #define FIRST_PSEUDO_REGISTER 104
1004 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1006 /* Value should be nonzero if functions must have frame pointers.
1007 Zero means the frame pointer need not be set up (and parms may be accessed
1008 via the stack pointer) in functions that seem suitable.
1009 If we have to have a frame pointer we might as well make use of it.
1010 APCS says that the frame pointer does not need to be pushed in leaf
1011 functions, or simple tail call functions. */
1013 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1014 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1017 /* Return number of consecutive hard regs needed starting at reg REGNO
1018 to hold something of mode MODE.
1019 This is ordinarily the length in words of a value of mode MODE
1020 but can be less for certain modes in special long registers.
1022 On the ARM core regs are UNITS_PER_WORD bits wide. */
1023 #define HARD_REGNO_NREGS(REGNO, MODE) \
1025 && REGNO > PC_REGNUM \
1026 && REGNO != FRAME_POINTER_REGNUM \
1027 && REGNO != ARG_POINTER_REGNUM) \
1028 && !IS_VFP_REGNUM (REGNO) \
1029 ? 1 : ARM_NUM_REGS (MODE))
1031 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1032 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1033 arm_hard_regno_mode_ok ((REGNO), (MODE))
1035 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
1037 #define VALID_IWMMXT_REG_MODE(MODE) \
1038 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1040 /* Modes valid for Neon D registers. */
1041 #define VALID_NEON_DREG_MODE(MODE) \
1042 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1043 || (MODE) == V2SFmode || (MODE) == DImode)
1045 /* Modes valid for Neon Q registers. */
1046 #define VALID_NEON_QREG_MODE(MODE) \
1047 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1048 || (MODE) == V4SFmode || (MODE) == V2DImode)
1050 /* Structure modes valid for Neon registers. */
1051 #define VALID_NEON_STRUCT_MODE(MODE) \
1052 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1053 || (MODE) == CImode || (MODE) == XImode)
1055 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1056 extern int arm_regs_in_sequence[];
1058 /* The order in which register should be allocated. It is good to use ip
1059 since no saving is required (though calls clobber it) and it never contains
1060 function parameters. It is quite good to use lr since other calls may
1061 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1062 least likely to contain a function parameter; in addition results are
1064 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1065 then D8-D15. The reason for doing this is to attempt to reduce register
1066 pressure when both single- and double-precision registers are used in a
1069 #define VREG(X) (FIRST_VFP_REGNUM + (X))
1070 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1071 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1073 #define REG_ALLOC_ORDER \
1075 /* General registers. */ \
1076 3, 2, 1, 0, 12, 14, 4, 5, \
1077 6, 7, 8, 9, 10, 11, \
1078 /* High VFP registers. */ \
1079 VREG(32), VREG(33), VREG(34), VREG(35), \
1080 VREG(36), VREG(37), VREG(38), VREG(39), \
1081 VREG(40), VREG(41), VREG(42), VREG(43), \
1082 VREG(44), VREG(45), VREG(46), VREG(47), \
1083 VREG(48), VREG(49), VREG(50), VREG(51), \
1084 VREG(52), VREG(53), VREG(54), VREG(55), \
1085 VREG(56), VREG(57), VREG(58), VREG(59), \
1086 VREG(60), VREG(61), VREG(62), VREG(63), \
1087 /* VFP argument registers. */ \
1088 VREG(15), VREG(14), VREG(13), VREG(12), \
1089 VREG(11), VREG(10), VREG(9), VREG(8), \
1090 VREG(7), VREG(6), VREG(5), VREG(4), \
1091 VREG(3), VREG(2), VREG(1), VREG(0), \
1092 /* VFP call-saved registers. */ \
1093 VREG(16), VREG(17), VREG(18), VREG(19), \
1094 VREG(20), VREG(21), VREG(22), VREG(23), \
1095 VREG(24), VREG(25), VREG(26), VREG(27), \
1096 VREG(28), VREG(29), VREG(30), VREG(31), \
1097 /* IWMMX registers. */ \
1098 WREG(0), WREG(1), WREG(2), WREG(3), \
1099 WREG(4), WREG(5), WREG(6), WREG(7), \
1100 WREG(8), WREG(9), WREG(10), WREG(11), \
1101 WREG(12), WREG(13), WREG(14), WREG(15), \
1102 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1103 /* Registers not for general use. */ \
1104 CC_REGNUM, VFPCC_REGNUM, \
1105 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1106 SP_REGNUM, PC_REGNUM \
1109 /* Use different register alloc ordering for Thumb. */
1110 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1112 /* Tell IRA to use the order we define rather than messing it up with its
1113 own cost calculations. */
1114 #define HONOR_REG_ALLOC_ORDER
1116 /* Interrupt functions can only use registers that have already been
1117 saved by the prologue, even if they would normally be
1119 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1120 (! IS_INTERRUPT (cfun->machine->func_type) || \
1121 df_regs_ever_live_p (DST))
1123 /* Register and constant classes. */
1125 /* Register classes. */
1149 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1151 /* Give names of register classes as strings for dump file. */
1152 #define REG_CLASS_NAMES \
1174 /* Define which registers fit in which classes.
1175 This is an initializer for a vector of HARD_REG_SET
1176 of length N_REG_CLASSES. */
1177 #define REG_CLASS_CONTENTS \
1179 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1180 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1181 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1182 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1183 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1184 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1185 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1186 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1187 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1188 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1189 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1190 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1191 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1192 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1193 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1194 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1195 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
1196 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 } /* ALL_REGS */ \
1199 /* Any of the VFP register classes. */
1200 #define IS_VFP_CLASS(X) \
1201 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1202 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1204 /* The same information, inverted:
1205 Return the class number of the smallest class containing
1206 reg number REGNO. This could be a conditional expression
1207 or could index an array. */
1208 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1210 /* In VFPv1, VFP registers could only be accessed in the mode they
1211 were set, so subregs would be invalid there. However, we don't
1212 support VFPv1 at the moment, and the restriction was lifted in
1214 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
1215 VFP registers in little-endian order. We can't describe that accurately to
1216 GCC, so avoid taking subregs of such values. */
1217 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1218 (TARGET_VFP && TARGET_BIG_END \
1219 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
1220 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
1221 && reg_classes_intersect_p (VFP_REGS, (CLASS)))
1223 /* The class value for index registers, and the one for base regs. */
1224 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1225 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1227 /* For the Thumb the high registers cannot be used as base registers
1228 when addressing quantities in QI or HI mode; if we don't know the
1229 mode, then we must be conservative. */
1230 #define MODE_BASE_REG_CLASS(MODE) \
1231 (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
1232 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1234 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1235 instead of BASE_REGS. */
1236 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1238 /* When this hook returns true for MODE, the compiler allows
1239 registers explicitly used in the rtl to be used as spill registers
1240 but prevents the compiler from extending the lifetime of these
1242 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1243 arm_small_register_classes_for_mode_p
1245 /* Must leave BASE_REGS reloads alone */
1246 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1247 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1248 ? ((true_regnum (X) == -1 ? LO_REGS \
1249 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1253 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1254 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1255 ? ((true_regnum (X) == -1 ? LO_REGS \
1256 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1260 /* Return the register class of a scratch register needed to copy IN into
1261 or out of a register in CLASS in MODE. If it can be done directly,
1262 NO_REGS is returned. */
1263 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1264 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1265 ((TARGET_VFP && TARGET_HARD_FLOAT \
1266 && IS_VFP_CLASS (CLASS)) \
1267 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1268 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1269 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1271 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1272 ? GENERAL_REGS : NO_REGS) \
1273 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1275 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1276 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1277 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1278 ((TARGET_VFP && TARGET_HARD_FLOAT \
1279 && IS_VFP_CLASS (CLASS)) \
1280 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1281 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1282 coproc_secondary_reload_class (MODE, X, TRUE) : \
1284 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1285 && CONSTANT_P (X)) \
1287 (((MODE) == HImode && ! arm_arch4 \
1289 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
1290 && true_regnum (X) == -1))) \
1291 ? GENERAL_REGS : NO_REGS) \
1292 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1294 /* Try a machine-dependent way of reloading an illegitimate address
1295 operand. If we find one, push the reload and jump to WIN. This
1296 macro is used in only one place: `find_reloads_address' in reload.c.
1298 For the ARM, we wish to handle large displacements off a base
1299 register by splitting the addend across a MOV and the mem insn.
1300 This can cut the number of reloads needed. */
1301 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1304 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1309 /* XXX If an HImode FP+large_offset address is converted to an HImode
1310 SP+large_offset address, then reload won't know how to fix it. It sees
1311 only that SP isn't valid for HImode, and so reloads the SP into an index
1312 register, but the resulting address is still invalid because the offset
1313 is too big. We fix it here instead by reloading the entire address. */
1314 /* We could probably achieve better results by defining PROMOTE_MODE to help
1315 cope with the variances between the Thumb's signed and unsigned byte and
1316 halfword load instructions. */
1317 /* ??? This should be safe for thumb2, but we may be able to do better. */
1318 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1320 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1328 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1330 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1332 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1334 /* Return the maximum number of consecutive registers
1335 needed to represent mode MODE in a register of class CLASS.
1336 ARM regs are UNITS_PER_WORD bits.
1337 FIXME: Is this true for iWMMX? */
1338 #define CLASS_MAX_NREGS(CLASS, MODE) \
1339 (ARM_NUM_REGS (MODE))
1341 /* If defined, gives a class of registers that cannot be used as the
1342 operand of a SUBREG that changes the mode of the object illegally. */
1344 /* Stack layout; function entry, exit and calling. */
1346 /* Define this if pushing a word on the stack
1347 makes the stack pointer a smaller address. */
1348 #define STACK_GROWS_DOWNWARD 1
1350 /* Define this to nonzero if the nominal address of the stack frame
1351 is at the high-address end of the local variables;
1352 that is, each additional local variable allocated
1353 goes at a more negative offset in the frame. */
1354 #define FRAME_GROWS_DOWNWARD 1
1356 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1357 When present, it is one word in size, and sits at the top of the frame,
1358 between the soft frame pointer and either r7 or r11.
1360 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1361 and only then if some outgoing arguments are passed on the stack. It would
1362 be tempting to also check whether the stack arguments are passed by indirect
1363 calls, but there seems to be no reason in principle why a post-reload pass
1364 couldn't convert a direct call into an indirect one. */
1365 #define CALLER_INTERWORKING_SLOT_SIZE \
1366 (TARGET_CALLER_INTERWORKING \
1367 && crtl->outgoing_args_size != 0 \
1368 ? UNITS_PER_WORD : 0)
1370 /* Offset within stack frame to start allocating local variables at.
1371 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1372 first local allocated. Otherwise, it is the offset to the BEGINNING
1373 of the first local allocated. */
1374 #define STARTING_FRAME_OFFSET 0
1376 /* If we generate an insn to push BYTES bytes,
1377 this says how many the stack pointer really advances by. */
1378 /* The push insns do not do this rounding implicitly.
1379 So don't define this. */
1380 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1382 /* Define this if the maximum size of all the outgoing args is to be
1383 accumulated and pushed during the prologue. The amount can be
1384 found in the variable crtl->outgoing_args_size. */
1385 #define ACCUMULATE_OUTGOING_ARGS 1
1387 /* Offset of first parameter from the argument pointer register value. */
1388 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1390 /* Amount of memory needed for an untyped call to save all possible return
1392 #define APPLY_RESULT_SIZE arm_apply_result_size()
1394 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1395 values must be in memory. On the ARM, they need only do so if larger
1396 than a word, or if they contain elements offset from zero in the struct. */
1397 #define DEFAULT_PCC_STRUCT_RETURN 0
1399 /* These bits describe the different types of function supported
1400 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1401 normal function and an interworked function, for example. Knowing the
1402 type of a function is important for determining its prologue and
1404 Note value 7 is currently unassigned. Also note that the interrupt
1405 function types all have bit 2 set, so that they can be tested for easily.
1406 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1407 machine_function structure is initialized (to zero) func_type will
1408 default to unknown. This will force the first use of arm_current_func_type
1409 to call arm_compute_func_type. */
1410 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1411 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1412 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1413 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1414 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1415 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1417 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1419 /* In addition functions can have several type modifiers,
1420 outlined by these bit masks: */
1421 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1422 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1423 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1424 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1425 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1427 /* Some macros to test these flags. */
1428 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1429 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1430 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1431 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1432 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1433 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1436 /* Structure used to hold the function stack frame layout. Offsets are
1437 relative to the stack pointer on function entry. Positive offsets are
1438 in the direction of stack growth.
1439 Only soft_frame is used in thumb mode. */
1441 typedef struct GTY(()) arm_stack_offsets
1443 int saved_args; /* ARG_POINTER_REGNUM. */
1444 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1446 int soft_frame; /* FRAME_POINTER_REGNUM. */
1447 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1448 int outgoing_args; /* STACK_POINTER_REGNUM. */
1449 unsigned int saved_regs_mask;
1453 #ifndef GENERATOR_FILE
1454 /* A C structure for machine-specific, per-function data.
1455 This is added to the cfun structure. */
1456 typedef struct GTY(()) machine_function
1458 /* Additional stack adjustment in __builtin_eh_throw. */
1459 rtx eh_epilogue_sp_ofs;
1460 /* Records if LR has to be saved for far jumps. */
1462 /* Records if ARG_POINTER was ever live. */
1463 int arg_pointer_live;
1464 /* Records if the save of LR has been eliminated. */
1465 int lr_save_eliminated;
1466 /* The size of the stack frame. Only valid after reload. */
1467 arm_stack_offsets stack_offsets;
1468 /* Records the type of the current function. */
1469 unsigned long func_type;
1470 /* Record if the function has a variable argument list. */
1471 int uses_anonymous_args;
1472 /* Records if sibcalls are blocked because an argument
1473 register is needed to preserve stack alignment. */
1474 int sibcall_blocked;
1475 /* The PIC register for this function. This might be a pseudo. */
1477 /* Labels for per-function Thumb call-via stubs. One per potential calling
1478 register. We can never call via LR or PC. We can call via SP if a
1479 trampoline happens to be on the top of the stack. */
1481 /* Set to 1 when a return insn is output, this means that the epilogue
1483 int return_used_this_function;
1484 /* When outputting Thumb-1 code, record the last insn that provides
1485 information about condition codes, and the comparison operands. */
1489 /* Also record the CC mode that is supported. */
1490 enum machine_mode thumb1_cc_mode;
1495 /* As in the machine_function, a global set of call-via labels, for code
1496 that is in text_section. */
1497 extern GTY(()) rtx thumb_call_via_label[14];
1499 /* The number of potential ways of assigning to a co-processor. */
1500 #define ARM_NUM_COPROC_SLOTS 1
1502 /* Enumeration of procedure calling standard variants. We don't really
1503 support all of these yet. */
1506 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1507 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1508 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1509 /* This must be the last AAPCS variant. */
1510 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1511 ARM_PCS_ATPCS, /* ATPCS. */
1512 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1516 /* Default procedure calling standard of current compilation unit. */
1517 extern enum arm_pcs arm_pcs_default;
1519 /* A C type for declaring a variable that is used as the first argument of
1520 `FUNCTION_ARG' and other related values. */
1523 /* This is the number of registers of arguments scanned so far. */
1525 /* This is the number of iWMMXt register arguments scanned so far. */
1529 /* Which procedure call variant to use for this call. */
1530 enum arm_pcs pcs_variant;
1532 /* AAPCS related state tracking. */
1533 int aapcs_arg_processed; /* No need to lay out this argument again. */
1534 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1535 this argument, or -1 if using core
1538 int aapcs_next_ncrn;
1539 rtx aapcs_reg; /* Register assigned to this argument. */
1540 int aapcs_partial; /* How many bytes are passed in regs (if
1541 split between core regs and stack.
1543 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1544 int can_split; /* Argument can be split between core regs
1546 /* Private data for tracking VFP register allocation */
1547 unsigned aapcs_vfp_regs_free;
1548 unsigned aapcs_vfp_reg_alloc;
1549 int aapcs_vfp_rcount;
1550 MACHMODE aapcs_vfp_rmode;
1553 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1554 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1556 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1557 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1559 /* For AAPCS, padding should never be below the argument. For other ABIs,
1560 * mimic the default. */
1561 #define PAD_VARARGS_DOWN \
1562 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1564 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1565 for a call to a function whose data type is FNTYPE.
1566 For a library call, FNTYPE is 0.
1567 On the ARM, the offset starts at 0. */
1568 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1569 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1571 /* 1 if N is a possible register number for function argument passing.
1572 On the ARM, r0-r3 are used to pass args. */
1573 #define FUNCTION_ARG_REGNO_P(REGNO) \
1574 (IN_RANGE ((REGNO), 0, 3) \
1575 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1576 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1577 || (TARGET_IWMMXT_ABI \
1578 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1581 /* If your target environment doesn't prefix user functions with an
1582 underscore, you may wish to re-define this to prevent any conflicts. */
1583 #ifndef ARM_MCOUNT_NAME
1584 #define ARM_MCOUNT_NAME "*mcount"
1587 /* Call the function profiler with a given profile label. The Acorn
1588 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1589 On the ARM the full profile code will look like:
1598 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1599 will output the .text section.
1601 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1602 ``prof'' doesn't seem to mind about this!
1604 Note - this version of the code is designed to work in both ARM and
1606 #ifndef ARM_FUNCTION_PROFILER
1607 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1612 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1613 IP_REGNUM, LR_REGNUM); \
1614 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1615 fputc ('\n', STREAM); \
1616 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1617 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1618 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1622 #ifdef THUMB_FUNCTION_PROFILER
1623 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1625 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1627 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1629 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1630 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1633 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1634 the stack pointer does not matter. The value is tested only in
1635 functions that have frame pointers.
1636 No definition is equivalent to always zero.
1638 On the ARM, the function epilogue recovers the stack pointer from the
1640 #define EXIT_IGNORE_STACK 1
1642 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1644 /* Determine if the epilogue should be output as RTL.
1645 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1646 #define USE_RETURN_INSN(ISCOND) \
1647 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1649 /* Definitions for register eliminations.
1651 This is an array of structures. Each structure initializes one pair
1652 of eliminable registers. The "from" register number is given first,
1653 followed by "to". Eliminations of the same "from" register are listed
1654 in order of preference.
1656 We have two registers that can be eliminated on the ARM. First, the
1657 arg pointer register can often be eliminated in favor of the stack
1658 pointer register. Secondly, the pseudo frame pointer register can always
1659 be eliminated; it is replaced with either the stack or the real frame
1660 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1661 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1663 #define ELIMINABLE_REGS \
1664 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1665 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1666 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1667 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1668 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1669 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1670 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1672 /* Define the offset between two registers, one to be eliminated, and the
1673 other its replacement, at the start of a routine. */
1674 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1676 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1678 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1680 /* Special case handling of the location of arguments passed on the stack. */
1681 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1683 /* Initialize data used by insn expanders. This is called from insn_emit,
1684 once for every function before code is generated. */
1685 #define INIT_EXPANDERS arm_init_expanders ()
1687 /* Length in units of the trampoline for entering a nested function. */
1688 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1690 /* Alignment required for a trampoline in bits. */
1691 #define TRAMPOLINE_ALIGNMENT 32
1693 /* Addressing modes, and classification of registers for them. */
1694 #define HAVE_POST_INCREMENT 1
1695 #define HAVE_PRE_INCREMENT TARGET_32BIT
1696 #define HAVE_POST_DECREMENT TARGET_32BIT
1697 #define HAVE_PRE_DECREMENT TARGET_32BIT
1698 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1699 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1700 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1701 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1703 enum arm_auto_incmodes
1711 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1712 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1713 #define USE_LOAD_POST_INCREMENT(mode) \
1714 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1715 #define USE_LOAD_PRE_INCREMENT(mode) \
1716 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1717 #define USE_LOAD_POST_DECREMENT(mode) \
1718 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1719 #define USE_LOAD_PRE_DECREMENT(mode) \
1720 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1722 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1723 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1724 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1725 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1727 /* Macros to check register numbers against specific register classes. */
1729 /* These assume that REGNO is a hard or pseudo reg number.
1730 They give nonzero only if REGNO is a hard reg of the suitable class
1731 or a pseudo reg currently allocated to a suitable hard reg.
1732 Since they use reg_renumber, they are safe only once reg_renumber
1733 has been allocated, which happens in reginfo.c during register
1735 #define TEST_REGNO(R, TEST, VALUE) \
1736 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1738 /* Don't allow the pc to be used. */
1739 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1740 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1741 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1742 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1744 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1745 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1746 || (GET_MODE_SIZE (MODE) >= 4 \
1747 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1749 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1751 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1752 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1754 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1755 For Thumb, we can not use SP + reg, so reject SP. */
1756 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1757 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1759 /* For ARM code, we don't care about the mode, but for Thumb, the index
1760 must be suitable for use in a QImode load. */
1761 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1762 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1763 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1765 /* Maximum number of registers that can appear in a valid memory address.
1766 Shifts in addresses can't be by a register. */
1767 #define MAX_REGS_PER_ADDRESS 2
1769 /* Recognize any constant value that is a valid address. */
1770 /* XXX We can address any constant, eventually... */
1771 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1772 #define CONSTANT_ADDRESS_P(X) \
1773 (GET_CODE (X) == SYMBOL_REF \
1774 && (CONSTANT_POOL_ADDRESS_P (X) \
1775 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1777 /* True if SYMBOL + OFFSET constants must refer to something within
1778 SYMBOL's section. */
1779 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1781 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1782 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1783 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1786 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1787 #define SUBTARGET_NAME_ENCODING_LENGTHS
1790 /* This is a C fragment for the inside of a switch statement.
1791 Each case label should return the number of characters to
1792 be stripped from the start of a function's name, if that
1793 name starts with the indicated character. */
1794 #define ARM_NAME_ENCODING_LENGTHS \
1795 case '*': return 1; \
1796 SUBTARGET_NAME_ENCODING_LENGTHS
1798 /* This is how to output a reference to a user-level label named NAME.
1799 `assemble_name' uses this. */
1800 #undef ASM_OUTPUT_LABELREF
1801 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1802 arm_asm_output_labelref (FILE, NAME)
1804 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1805 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1806 if (TARGET_THUMB2) \
1807 thumb2_asm_output_opcode (STREAM);
1809 /* The EABI specifies that constructors should go in .init_array.
1810 Other targets use .ctors for compatibility. */
1811 #ifndef ARM_EABI_CTORS_SECTION_OP
1812 #define ARM_EABI_CTORS_SECTION_OP \
1813 "\t.section\t.init_array,\"aw\",%init_array"
1815 #ifndef ARM_EABI_DTORS_SECTION_OP
1816 #define ARM_EABI_DTORS_SECTION_OP \
1817 "\t.section\t.fini_array,\"aw\",%fini_array"
1819 #define ARM_CTORS_SECTION_OP \
1820 "\t.section\t.ctors,\"aw\",%progbits"
1821 #define ARM_DTORS_SECTION_OP \
1822 "\t.section\t.dtors,\"aw\",%progbits"
1824 /* Define CTORS_SECTION_ASM_OP. */
1825 #undef CTORS_SECTION_ASM_OP
1826 #undef DTORS_SECTION_ASM_OP
1828 # define CTORS_SECTION_ASM_OP \
1829 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1830 # define DTORS_SECTION_ASM_OP \
1831 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1832 #else /* !defined (IN_LIBGCC2) */
1833 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1834 so we cannot use the definition above. */
1835 # ifdef __ARM_EABI__
1836 /* The .ctors section is not part of the EABI, so we do not define
1837 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1838 from trying to use it. We do define it when doing normal
1839 compilation, as .init_array can be used instead of .ctors. */
1840 /* There is no need to emit begin or end markers when using
1841 init_array; the dynamic linker will compute the size of the
1842 array itself based on special symbols created by the static
1843 linker. However, we do need to arrange to set up
1844 exception-handling here. */
1845 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1846 # define CTOR_LIST_END /* empty */
1847 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1848 # define DTOR_LIST_END /* empty */
1849 # else /* !defined (__ARM_EABI__) */
1850 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1851 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1852 # endif /* !defined (__ARM_EABI__) */
1853 #endif /* !defined (IN_LIBCC2) */
1855 /* True if the operating system can merge entities with vague linkage
1856 (e.g., symbols in COMDAT group) during dynamic linking. */
1857 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1858 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1861 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1863 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1864 and check its validity for a certain class.
1865 We have two alternate definitions for each of them.
1866 The usual definition accepts all pseudo regs; the other rejects
1867 them unless they have been allocated suitable hard regs.
1868 The symbol REG_OK_STRICT causes the latter definition to be used.
1869 Thumb-2 has the same restrictions as arm. */
1870 #ifndef REG_OK_STRICT
1872 #define ARM_REG_OK_FOR_BASE_P(X) \
1873 (REGNO (X) <= LAST_ARM_REGNUM \
1874 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1875 || REGNO (X) == FRAME_POINTER_REGNUM \
1876 || REGNO (X) == ARG_POINTER_REGNUM)
1878 #define ARM_REG_OK_FOR_INDEX_P(X) \
1879 ((REGNO (X) <= LAST_ARM_REGNUM \
1880 && REGNO (X) != STACK_POINTER_REGNUM) \
1881 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1882 || REGNO (X) == FRAME_POINTER_REGNUM \
1883 || REGNO (X) == ARG_POINTER_REGNUM)
1885 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1886 (REGNO (X) <= LAST_LO_REGNUM \
1887 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1888 || (GET_MODE_SIZE (MODE) >= 4 \
1889 && (REGNO (X) == STACK_POINTER_REGNUM \
1890 || (X) == hard_frame_pointer_rtx \
1891 || (X) == arg_pointer_rtx)))
1893 #define REG_STRICT_P 0
1895 #else /* REG_OK_STRICT */
1897 #define ARM_REG_OK_FOR_BASE_P(X) \
1898 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1900 #define ARM_REG_OK_FOR_INDEX_P(X) \
1901 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1903 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1904 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1906 #define REG_STRICT_P 1
1908 #endif /* REG_OK_STRICT */
1910 /* Now define some helpers in terms of the above. */
1912 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1914 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1915 : ARM_REG_OK_FOR_BASE_P (X))
1917 /* For 16-bit Thumb, a valid index register is anything that can be used in
1918 a byte load instruction. */
1919 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1920 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1922 /* Nonzero if X is a hard reg that can be used as an index
1923 or if it is a pseudo reg. On the Thumb, the stack pointer
1925 #define REG_OK_FOR_INDEX_P(X) \
1927 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1928 : ARM_REG_OK_FOR_INDEX_P (X))
1930 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1931 For Thumb, we can not use SP + reg, so reject SP. */
1932 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1933 REG_OK_FOR_INDEX_P (X)
1935 #define ARM_BASE_REGISTER_RTX_P(X) \
1936 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
1938 #define ARM_INDEX_REGISTER_RTX_P(X) \
1939 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
1941 /* Specify the machine mode that this machine uses
1942 for the index in the tablejump instruction. */
1943 #define CASE_VECTOR_MODE Pmode
1945 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
1947 && (optimize_size || flag_pic)))
1949 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
1951 ? (min >= 0 && max < 512 \
1952 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
1953 : min >= -256 && max < 256 \
1954 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
1955 : min >= 0 && max < 8192 \
1956 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
1957 : min >= -4096 && max < 4096 \
1958 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
1960 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
1961 : (max >= 0x200) ? HImode \
1964 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1965 unsigned is probably best, but may break some code. */
1966 #ifndef DEFAULT_SIGNED_CHAR
1967 #define DEFAULT_SIGNED_CHAR 0
1970 /* Max number of bytes we can move from memory to memory
1971 in one reasonably fast instruction. */
1975 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
1977 /* Define if operations between registers always perform the operation
1978 on the full register even if a narrower mode is specified. */
1979 #define WORD_REGISTER_OPERATIONS
1981 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1982 will either zero-extend or sign-extend. The value of this macro should
1983 be the code that says which one of the two operations is implicitly
1984 done, UNKNOWN if none. */
1985 #define LOAD_EXTEND_OP(MODE) \
1986 (TARGET_THUMB ? ZERO_EXTEND : \
1987 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1988 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
1990 /* Nonzero if access to memory by bytes is slow and undesirable. */
1991 #define SLOW_BYTE_ACCESS 0
1993 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
1995 /* Immediate shift counts are truncated by the output routines (or was it
1996 the assembler?). Shift counts in a register are truncated by ARM. Note
1997 that the native compiler puts too large (> 32) immediate shift counts
1998 into a register and shifts by the register, letting the ARM decide what
1999 to do instead of doing that itself. */
2000 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2001 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2002 On the arm, Y in a register is used modulo 256 for the shift. Only for
2003 rotates is modulo 32 used. */
2004 /* #define SHIFT_COUNT_TRUNCATED 1 */
2006 /* All integers have the same format so truncation is easy. */
2007 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2009 /* Calling from registers is a massive pain. */
2010 #define NO_FUNCTION_CSE 1
2012 /* The machine modes of pointers and functions */
2013 #define Pmode SImode
2014 #define FUNCTION_MODE Pmode
2016 #define ARM_FRAME_RTX(X) \
2017 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2018 || (X) == arg_pointer_rtx)
2020 /* Try to generate sequences that don't involve branches, we can then use
2021 conditional instructions. */
2022 #define BRANCH_COST(speed_p, predictable_p) \
2023 (current_tune->branch_cost (speed_p, predictable_p))
2025 /* False if short circuit operation is preferred. */
2026 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
2028 ? (TARGET_THUMB ? false : true) \
2029 : (current_tune->logical_op_non_short_circuit[TARGET_ARM]))
2032 /* Position Independent Code. */
2033 /* We decide which register to use based on the compilation options and
2034 the assembler in use; this is more general than the APCS restriction of
2035 using sb (r9) all the time. */
2036 extern unsigned arm_pic_register;
2038 /* The register number of the register used to address a table of static
2039 data addresses in memory. */
2040 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2042 /* We can't directly access anything that contains a symbol,
2043 nor can we indirect via the constant pool. One exception is
2044 UNSPEC_TLS, which is always PIC. */
2045 #define LEGITIMATE_PIC_OPERAND_P(X) \
2046 (!(symbol_mentioned_p (X) \
2047 || label_mentioned_p (X) \
2048 || (GET_CODE (X) == SYMBOL_REF \
2049 && CONSTANT_POOL_ADDRESS_P (X) \
2050 && (symbol_mentioned_p (get_pool_constant (X)) \
2051 || label_mentioned_p (get_pool_constant (X))))) \
2052 || tls_mentioned_p (X))
2054 /* We need to know when we are making a constant pool; this determines
2055 whether data needs to be in the GOT or can be referenced via a GOT
2057 extern int making_const_table;
2059 /* Handle pragmas for compatibility with Intel's compilers. */
2060 /* Also abuse this to register additional C specific EABI attributes. */
2061 #define REGISTER_TARGET_PRAGMAS() do { \
2062 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2063 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2064 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2065 arm_lang_object_attributes_init(); \
2068 /* Condition code information. */
2069 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2070 return the mode to be used for the comparison. */
2072 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2074 #define REVERSIBLE_CC_MODE(MODE) 1
2076 #define REVERSE_CONDITION(CODE,MODE) \
2077 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2078 ? reverse_condition_maybe_unordered (code) \
2079 : reverse_condition (code))
2081 /* The arm5 clz instruction returns 32. */
2082 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2083 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2085 #define CC_STATUS_INIT \
2086 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2089 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2090 TARGET_THUMB2 ? "\t.thumb\n" : "")
2092 /* Output a push or a pop instruction (only used when profiling).
2093 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2094 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2095 that r7 isn't used by the function profiler, so we can use it as a
2096 scratch reg. WARNING: This isn't safe in the general case! It may be
2097 sensitive to future changes in final.c:profile_function. */
2098 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2102 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2103 STACK_POINTER_REGNUM, REGNO); \
2104 else if (TARGET_THUMB1 \
2105 && (REGNO) == STATIC_CHAIN_REGNUM) \
2107 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2108 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2109 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2112 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2116 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2117 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2121 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2122 STACK_POINTER_REGNUM, REGNO); \
2123 else if (TARGET_THUMB1 \
2124 && (REGNO) == STATIC_CHAIN_REGNUM) \
2126 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2127 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2128 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2131 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2134 #define ADDR_VEC_ALIGN(JUMPTABLE) \
2135 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0)
2137 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the
2138 default alignment from elfos.h. */
2139 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2140 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
2142 /* Make sure subsequent insns are aligned after a TBB. */
2143 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2146 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2147 ASM_OUTPUT_ALIGN (FILE, 1); \
2151 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2156 if (is_called_in_ARM_mode (DECL) \
2157 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2158 && cfun->is_thunk)) \
2159 fprintf (STREAM, "\t.code 32\n") ; \
2160 else if (TARGET_THUMB1) \
2161 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2163 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2165 if (TARGET_POKE_FUNCTION_NAME) \
2166 arm_poke_function_name (STREAM, (const char *) NAME); \
2170 /* For aliases of functions we use .thumb_set instead. */
2171 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2174 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2175 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2177 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2179 fprintf (FILE, "\t.thumb_set "); \
2180 assemble_name (FILE, LABEL1); \
2181 fprintf (FILE, ","); \
2182 assemble_name (FILE, LABEL2); \
2183 fprintf (FILE, "\n"); \
2186 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2190 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2191 /* To support -falign-* switches we need to use .p2align so
2192 that alignment directives in code sections will be padded
2193 with no-op instructions, rather than zeroes. */
2194 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2197 if ((MAX_SKIP) == 0) \
2198 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2200 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2201 (int) (LOG), (int) (MAX_SKIP)); \
2205 /* Add two bytes to the length of conditionally executed Thumb-2
2206 instructions for the IT instruction. */
2207 #define ADJUST_INSN_LENGTH(insn, length) \
2208 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2211 /* Only perform branch elimination (by making instructions conditional) if
2212 we're optimizing. For Thumb-2 check if any IT instructions need
2214 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2215 if (TARGET_ARM && optimize) \
2216 arm_final_prescan_insn (INSN); \
2217 else if (TARGET_THUMB2) \
2218 thumb2_final_prescan_insn (INSN); \
2219 else if (TARGET_THUMB1) \
2220 thumb1_final_prescan_insn (INSN)
2222 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2223 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2224 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2225 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2226 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2227 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2230 /* A C expression whose value is RTL representing the value of the return
2231 address for the frame COUNT steps up from the current frame. */
2233 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2234 arm_return_addr (COUNT, FRAME)
2236 /* Mask of the bits in the PC that contain the real return address
2237 when running in 26-bit mode. */
2238 #define RETURN_ADDR_MASK26 (0x03fffffc)
2240 /* Pick up the return address upon entry to a procedure. Used for
2241 dwarf2 unwind information. This also enables the table driven
2243 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2244 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2246 /* Used to mask out junk bits from the return address, such as
2247 processor state, interrupt status, condition codes and the like. */
2248 #define MASK_RETURN_ADDR \
2249 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2250 in 26 bit mode, the condition codes must be masked out of the \
2251 return address. This does not apply to ARM6 and later processors \
2252 when running in 32 bit mode. */ \
2253 ((arm_arch4 || TARGET_THUMB) \
2254 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2255 : arm_gen_return_addr_mask ())
2258 /* Do not emit .note.GNU-stack by default. */
2259 #ifndef NEED_INDICATE_EXEC_STACK
2260 #define NEED_INDICATE_EXEC_STACK 0
2263 #define TARGET_ARM_ARCH \
2266 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
2267 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
2269 /* The highest Thumb instruction set version supported by the chip. */
2270 #define TARGET_ARM_ARCH_ISA_THUMB \
2271 (arm_arch_thumb2 ? 2 \
2272 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
2274 /* Expands to an upper-case char of the target's architectural
2276 #define TARGET_ARM_ARCH_PROFILE \
2280 ? (strlen (arm_arch_name) >=3 \
2281 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \
2285 /* Bit-field indicating what size LDREX/STREX loads/stores are available.
2286 Bit 0 for bytes, up to bit 3 for double-words. */
2287 #define TARGET_ARM_FEATURE_LDREX \
2288 ((TARGET_HAVE_LDREX ? 4 : 0) \
2289 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2290 | (TARGET_HAVE_LDREXD ? 8 : 0))
2292 /* Set as a bit mask indicating the available widths of hardware floating
2293 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2294 32-bit support, bit 3 indicates 64-bit support. */
2295 #define TARGET_ARM_FP \
2296 (TARGET_VFP_SINGLE ? 4 \
2297 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0))
2300 /* Set as a bit mask indicating the available widths of floating point
2301 types for hardware NEON floating point. This is the same as
2302 TARGET_ARM_FP without the 64-bit bit set. */
2304 #define TARGET_NEON_FP \
2305 (TARGET_ARM_FP & (0xff ^ 0x08))
2308 /* The maximum number of parallel loads or stores we support in an ldm/stm
2310 #define MAX_LDM_STM_OPS 4
2312 #define ASM_CPU_SPEC \
2313 " %{mcpu=generic-*:-march=%*;" \
2314 " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
2316 /* -mcpu=native handling only makes sense with compiler running on
2318 #if defined(__arm__)
2319 extern const char *host_detect_local_cpu (int argc, const char **argv);
2320 # define EXTRA_SPEC_FUNCTIONS \
2321 { "local_cpu_detect", host_detect_local_cpu },
2323 # define MCPU_MTUNE_NATIVE_SPECS \
2324 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2325 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2326 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2328 # define MCPU_MTUNE_NATIVE_SPECS ""
2331 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
2333 #endif /* ! GCC_ARM_H */
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