1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 3, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
43 #include "diagnostic-core.h"
48 #include "c-family/c-pragma.h" /* ??? */
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
61 /* Forward definitions of types. */
62 typedef struct minipool_node Mnode;
63 typedef struct minipool_fixup Mfix;
65 void (*arm_lang_output_object_attributes_hook)(void);
72 /* Forward function declarations. */
73 static bool arm_needs_doubleword_align (enum machine_mode, const_tree);
74 static int arm_compute_static_chain_stack_bytes (void);
75 static arm_stack_offsets *arm_get_frame_offsets (void);
76 static void arm_add_gc_roots (void);
77 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
78 HOST_WIDE_INT, rtx, rtx, int, int);
79 static unsigned bit_count (unsigned long);
80 static int arm_address_register_rtx_p (rtx, int);
81 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
82 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
83 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
84 static rtx arm_legitimize_address (rtx, rtx, enum machine_mode);
85 static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode);
86 inline static int thumb1_index_register_rtx_p (rtx, int);
87 static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
88 static int thumb_far_jump_used_p (void);
89 static bool thumb_force_lr_save (void);
90 static rtx emit_sfm (int, int);
91 static unsigned arm_size_return_regs (void);
92 static bool arm_assemble_integer (rtx, unsigned int, int);
93 static void arm_print_operand (FILE *, rtx, int);
94 static void arm_print_operand_address (FILE *, rtx);
95 static bool arm_print_operand_punct_valid_p (unsigned char code);
96 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
97 static arm_cc get_arm_condition_code (rtx);
98 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
99 static rtx is_jump_table (rtx);
100 static const char *output_multi_immediate (rtx *, const char *, const char *,
102 static const char *shift_op (rtx, HOST_WIDE_INT *);
103 static struct machine_function *arm_init_machine_status (void);
104 static void thumb_exit (FILE *, int);
105 static rtx is_jump_table (rtx);
106 static HOST_WIDE_INT get_jump_table_size (rtx);
107 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
108 static Mnode *add_minipool_forward_ref (Mfix *);
109 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
110 static Mnode *add_minipool_backward_ref (Mfix *);
111 static void assign_minipool_offsets (Mfix *);
112 static void arm_print_value (FILE *, rtx);
113 static void dump_minipool (rtx);
114 static int arm_barrier_cost (rtx);
115 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
116 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
117 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
119 static void arm_reorg (void);
120 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
121 static unsigned long arm_compute_save_reg0_reg12_mask (void);
122 static unsigned long arm_compute_save_reg_mask (void);
123 static unsigned long arm_isr_value (tree);
124 static unsigned long arm_compute_func_type (void);
125 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
126 static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *);
127 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
128 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
129 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
131 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
132 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
133 static int arm_comp_type_attributes (const_tree, const_tree);
134 static void arm_set_default_type_attributes (tree);
135 static int arm_adjust_cost (rtx, rtx, rtx, int);
136 static int optimal_immediate_sequence (enum rtx_code code,
137 unsigned HOST_WIDE_INT val,
138 struct four_ints *return_sequence);
139 static int optimal_immediate_sequence_1 (enum rtx_code code,
140 unsigned HOST_WIDE_INT val,
141 struct four_ints *return_sequence,
143 static int arm_get_strip_length (int);
144 static bool arm_function_ok_for_sibcall (tree, tree);
145 static enum machine_mode arm_promote_function_mode (const_tree,
146 enum machine_mode, int *,
148 static bool arm_return_in_memory (const_tree, const_tree);
149 static rtx arm_function_value (const_tree, const_tree, bool);
150 static rtx arm_libcall_value_1 (enum machine_mode);
151 static rtx arm_libcall_value (enum machine_mode, const_rtx);
152 static bool arm_function_value_regno_p (const unsigned int);
153 static void arm_internal_label (FILE *, const char *, unsigned long);
154 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
156 static bool arm_have_conditional_execution (void);
157 static bool arm_cannot_force_const_mem (enum machine_mode, rtx);
158 static bool arm_legitimate_constant_p (enum machine_mode, rtx);
159 static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
160 static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
161 static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
162 static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
163 static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
164 static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
165 static bool arm_rtx_costs (rtx, int, int, int, int *, bool);
166 static int arm_address_cost (rtx, bool);
167 static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
168 static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool);
169 static bool arm_memory_load_p (rtx);
170 static bool arm_cirrus_insn_p (rtx);
171 static void cirrus_reorg (rtx);
172 static void arm_init_builtins (void);
173 static void arm_init_iwmmxt_builtins (void);
174 static rtx safe_vector_operand (rtx, enum machine_mode);
175 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx, bool);
176 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
177 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
178 static tree arm_builtin_decl (unsigned, bool);
179 static void emit_constant_insn (rtx cond, rtx pattern);
180 static rtx emit_set_insn (rtx, rtx);
181 static int arm_arg_partial_bytes (cumulative_args_t, enum machine_mode,
183 static rtx arm_function_arg (cumulative_args_t, enum machine_mode,
185 static void arm_function_arg_advance (cumulative_args_t, enum machine_mode,
187 static unsigned int arm_function_arg_boundary (enum machine_mode, const_tree);
188 static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree,
190 static rtx aapcs_libcall_value (enum machine_mode);
191 static int aapcs_select_return_coproc (const_tree, const_tree);
193 #ifdef OBJECT_FORMAT_ELF
194 static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
195 static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
198 static void arm_encode_section_info (tree, rtx, int);
201 static void arm_file_end (void);
202 static void arm_file_start (void);
204 static void arm_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
206 static bool arm_pass_by_reference (cumulative_args_t,
207 enum machine_mode, const_tree, bool);
208 static bool arm_promote_prototypes (const_tree);
209 static bool arm_default_short_enums (void);
210 static bool arm_align_anon_bitfield (void);
211 static bool arm_return_in_msb (const_tree);
212 static bool arm_must_pass_in_stack (enum machine_mode, const_tree);
213 static bool arm_return_in_memory (const_tree, const_tree);
215 static void arm_unwind_emit (FILE *, rtx);
216 static bool arm_output_ttype (rtx);
217 static void arm_asm_emit_except_personality (rtx);
218 static void arm_asm_init_sections (void);
220 static rtx arm_dwarf_register_span (rtx);
222 static tree arm_cxx_guard_type (void);
223 static bool arm_cxx_guard_mask_bit (void);
224 static tree arm_get_cookie_size (tree);
225 static bool arm_cookie_has_size (void);
226 static bool arm_cxx_cdtor_returns_this (void);
227 static bool arm_cxx_key_method_may_be_inline (void);
228 static void arm_cxx_determine_class_data_visibility (tree);
229 static bool arm_cxx_class_data_always_comdat (void);
230 static bool arm_cxx_use_aeabi_atexit (void);
231 static void arm_init_libfuncs (void);
232 static tree arm_build_builtin_va_list (void);
233 static void arm_expand_builtin_va_start (tree, rtx);
234 static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
235 static void arm_option_override (void);
236 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
237 static bool arm_cannot_copy_insn_p (rtx);
238 static bool arm_tls_symbol_p (rtx x);
239 static int arm_issue_rate (void);
240 static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
241 static bool arm_output_addr_const_extra (FILE *, rtx);
242 static bool arm_allocate_stack_slots_for_args (void);
243 static const char *arm_invalid_parameter_type (const_tree t);
244 static const char *arm_invalid_return_type (const_tree t);
245 static tree arm_promoted_type (const_tree t);
246 static tree arm_convert_to_type (tree type, tree expr);
247 static bool arm_scalar_mode_supported_p (enum machine_mode);
248 static bool arm_frame_pointer_required (void);
249 static bool arm_can_eliminate (const int, const int);
250 static void arm_asm_trampoline_template (FILE *);
251 static void arm_trampoline_init (rtx, tree, rtx);
252 static rtx arm_trampoline_adjust_address (rtx);
253 static rtx arm_pic_static_addr (rtx orig, rtx reg);
254 static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
255 static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
256 static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *);
257 static bool arm_array_mode_supported_p (enum machine_mode,
258 unsigned HOST_WIDE_INT);
259 static enum machine_mode arm_preferred_simd_mode (enum machine_mode);
260 static bool arm_class_likely_spilled_p (reg_class_t);
261 static HOST_WIDE_INT arm_vector_alignment (const_tree type);
262 static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
263 static bool arm_builtin_support_vector_misalignment (enum machine_mode mode,
267 static void arm_conditional_register_usage (void);
268 static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
269 static unsigned int arm_autovectorize_vector_sizes (void);
270 static int arm_default_branch_cost (bool, bool);
271 static int arm_cortex_a5_branch_cost (bool, bool);
273 static bool arm_vectorize_vec_perm_const_ok (enum machine_mode vmode,
274 const unsigned char *sel);
277 /* Table of machine attributes. */
278 static const struct attribute_spec arm_attribute_table[] =
280 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
281 affects_type_identity } */
282 /* Function calls made to this symbol must be done indirectly, because
283 it may lie outside of the 26 bit addressing range of a normal function
285 { "long_call", 0, 0, false, true, true, NULL, false },
286 /* Whereas these functions are always known to reside within the 26 bit
288 { "short_call", 0, 0, false, true, true, NULL, false },
289 /* Specify the procedure call conventions for a function. */
290 { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute,
292 /* Interrupt Service Routines have special prologue and epilogue requirements. */
293 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute,
295 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute,
297 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute,
300 /* ARM/PE has three new attributes:
302 dllexport - for exporting a function/variable that will live in a dll
303 dllimport - for importing a function/variable from a dll
305 Microsoft allows multiple declspecs in one __declspec, separating
306 them with spaces. We do NOT support this. Instead, use __declspec
309 { "dllimport", 0, 0, true, false, false, NULL, false },
310 { "dllexport", 0, 0, true, false, false, NULL, false },
311 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute,
313 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
314 { "dllimport", 0, 0, false, false, false, handle_dll_attribute, false },
315 { "dllexport", 0, 0, false, false, false, handle_dll_attribute, false },
316 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute,
319 { NULL, 0, 0, false, false, false, NULL, false }
322 /* Initialize the GCC target structure. */
323 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
324 #undef TARGET_MERGE_DECL_ATTRIBUTES
325 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
328 #undef TARGET_LEGITIMIZE_ADDRESS
329 #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address
331 #undef TARGET_ATTRIBUTE_TABLE
332 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
334 #undef TARGET_ASM_FILE_START
335 #define TARGET_ASM_FILE_START arm_file_start
336 #undef TARGET_ASM_FILE_END
337 #define TARGET_ASM_FILE_END arm_file_end
339 #undef TARGET_ASM_ALIGNED_SI_OP
340 #define TARGET_ASM_ALIGNED_SI_OP NULL
341 #undef TARGET_ASM_INTEGER
342 #define TARGET_ASM_INTEGER arm_assemble_integer
344 #undef TARGET_PRINT_OPERAND
345 #define TARGET_PRINT_OPERAND arm_print_operand
346 #undef TARGET_PRINT_OPERAND_ADDRESS
347 #define TARGET_PRINT_OPERAND_ADDRESS arm_print_operand_address
348 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
349 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P arm_print_operand_punct_valid_p
351 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
352 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA arm_output_addr_const_extra
354 #undef TARGET_ASM_FUNCTION_PROLOGUE
355 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
357 #undef TARGET_ASM_FUNCTION_EPILOGUE
358 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
360 #undef TARGET_OPTION_OVERRIDE
361 #define TARGET_OPTION_OVERRIDE arm_option_override
363 #undef TARGET_COMP_TYPE_ATTRIBUTES
364 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
366 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
367 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
369 #undef TARGET_SCHED_ADJUST_COST
370 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
372 #undef TARGET_REGISTER_MOVE_COST
373 #define TARGET_REGISTER_MOVE_COST arm_register_move_cost
375 #undef TARGET_MEMORY_MOVE_COST
376 #define TARGET_MEMORY_MOVE_COST arm_memory_move_cost
378 #undef TARGET_ENCODE_SECTION_INFO
380 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
382 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
385 #undef TARGET_STRIP_NAME_ENCODING
386 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
388 #undef TARGET_ASM_INTERNAL_LABEL
389 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
391 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
392 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
394 #undef TARGET_FUNCTION_VALUE
395 #define TARGET_FUNCTION_VALUE arm_function_value
397 #undef TARGET_LIBCALL_VALUE
398 #define TARGET_LIBCALL_VALUE arm_libcall_value
400 #undef TARGET_FUNCTION_VALUE_REGNO_P
401 #define TARGET_FUNCTION_VALUE_REGNO_P arm_function_value_regno_p
403 #undef TARGET_ASM_OUTPUT_MI_THUNK
404 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
405 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
406 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
408 #undef TARGET_RTX_COSTS
409 #define TARGET_RTX_COSTS arm_rtx_costs
410 #undef TARGET_ADDRESS_COST
411 #define TARGET_ADDRESS_COST arm_address_cost
413 #undef TARGET_SHIFT_TRUNCATION_MASK
414 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
415 #undef TARGET_VECTOR_MODE_SUPPORTED_P
416 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
417 #undef TARGET_ARRAY_MODE_SUPPORTED_P
418 #define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
419 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
420 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
421 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
422 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
423 arm_autovectorize_vector_sizes
425 #undef TARGET_MACHINE_DEPENDENT_REORG
426 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
428 #undef TARGET_INIT_BUILTINS
429 #define TARGET_INIT_BUILTINS arm_init_builtins
430 #undef TARGET_EXPAND_BUILTIN
431 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
432 #undef TARGET_BUILTIN_DECL
433 #define TARGET_BUILTIN_DECL arm_builtin_decl
435 #undef TARGET_INIT_LIBFUNCS
436 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
438 #undef TARGET_PROMOTE_FUNCTION_MODE
439 #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode
440 #undef TARGET_PROMOTE_PROTOTYPES
441 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
442 #undef TARGET_PASS_BY_REFERENCE
443 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
444 #undef TARGET_ARG_PARTIAL_BYTES
445 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
446 #undef TARGET_FUNCTION_ARG
447 #define TARGET_FUNCTION_ARG arm_function_arg
448 #undef TARGET_FUNCTION_ARG_ADVANCE
449 #define TARGET_FUNCTION_ARG_ADVANCE arm_function_arg_advance
450 #undef TARGET_FUNCTION_ARG_BOUNDARY
451 #define TARGET_FUNCTION_ARG_BOUNDARY arm_function_arg_boundary
453 #undef TARGET_SETUP_INCOMING_VARARGS
454 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
456 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
457 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
459 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
460 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template
461 #undef TARGET_TRAMPOLINE_INIT
462 #define TARGET_TRAMPOLINE_INIT arm_trampoline_init
463 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
464 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
466 #undef TARGET_DEFAULT_SHORT_ENUMS
467 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
469 #undef TARGET_ALIGN_ANON_BITFIELD
470 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
472 #undef TARGET_NARROW_VOLATILE_BITFIELD
473 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
475 #undef TARGET_CXX_GUARD_TYPE
476 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
478 #undef TARGET_CXX_GUARD_MASK_BIT
479 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
481 #undef TARGET_CXX_GET_COOKIE_SIZE
482 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
484 #undef TARGET_CXX_COOKIE_HAS_SIZE
485 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
487 #undef TARGET_CXX_CDTOR_RETURNS_THIS
488 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
490 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
491 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
493 #undef TARGET_CXX_USE_AEABI_ATEXIT
494 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
496 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
497 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
498 arm_cxx_determine_class_data_visibility
500 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
501 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
503 #undef TARGET_RETURN_IN_MSB
504 #define TARGET_RETURN_IN_MSB arm_return_in_msb
506 #undef TARGET_RETURN_IN_MEMORY
507 #define TARGET_RETURN_IN_MEMORY arm_return_in_memory
509 #undef TARGET_MUST_PASS_IN_STACK
510 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
513 #undef TARGET_ASM_UNWIND_EMIT
514 #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit
516 /* EABI unwinding tables use a different format for the typeinfo tables. */
517 #undef TARGET_ASM_TTYPE
518 #define TARGET_ASM_TTYPE arm_output_ttype
520 #undef TARGET_ARM_EABI_UNWINDER
521 #define TARGET_ARM_EABI_UNWINDER true
523 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
524 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
526 #undef TARGET_ASM_INIT_SECTIONS
527 #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
528 #endif /* ARM_UNWIND_INFO */
530 #undef TARGET_DWARF_REGISTER_SPAN
531 #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
533 #undef TARGET_CANNOT_COPY_INSN_P
534 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
537 #undef TARGET_HAVE_TLS
538 #define TARGET_HAVE_TLS true
541 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
542 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
544 #undef TARGET_LEGITIMATE_CONSTANT_P
545 #define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
547 #undef TARGET_CANNOT_FORCE_CONST_MEM
548 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
550 #undef TARGET_MAX_ANCHOR_OFFSET
551 #define TARGET_MAX_ANCHOR_OFFSET 4095
553 /* The minimum is set such that the total size of the block
554 for a particular anchor is -4088 + 1 + 4095 bytes, which is
555 divisible by eight, ensuring natural spacing of anchors. */
556 #undef TARGET_MIN_ANCHOR_OFFSET
557 #define TARGET_MIN_ANCHOR_OFFSET -4088
559 #undef TARGET_SCHED_ISSUE_RATE
560 #define TARGET_SCHED_ISSUE_RATE arm_issue_rate
562 #undef TARGET_MANGLE_TYPE
563 #define TARGET_MANGLE_TYPE arm_mangle_type
565 #undef TARGET_BUILD_BUILTIN_VA_LIST
566 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
567 #undef TARGET_EXPAND_BUILTIN_VA_START
568 #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start
569 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
570 #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr
573 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
574 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
577 #undef TARGET_LEGITIMATE_ADDRESS_P
578 #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p
580 #undef TARGET_INVALID_PARAMETER_TYPE
581 #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
583 #undef TARGET_INVALID_RETURN_TYPE
584 #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
586 #undef TARGET_PROMOTED_TYPE
587 #define TARGET_PROMOTED_TYPE arm_promoted_type
589 #undef TARGET_CONVERT_TO_TYPE
590 #define TARGET_CONVERT_TO_TYPE arm_convert_to_type
592 #undef TARGET_SCALAR_MODE_SUPPORTED_P
593 #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p
595 #undef TARGET_FRAME_POINTER_REQUIRED
596 #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required
598 #undef TARGET_CAN_ELIMINATE
599 #define TARGET_CAN_ELIMINATE arm_can_eliminate
601 #undef TARGET_CONDITIONAL_REGISTER_USAGE
602 #define TARGET_CONDITIONAL_REGISTER_USAGE arm_conditional_register_usage
604 #undef TARGET_CLASS_LIKELY_SPILLED_P
605 #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p
607 #undef TARGET_VECTOR_ALIGNMENT
608 #define TARGET_VECTOR_ALIGNMENT arm_vector_alignment
610 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
611 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
612 arm_vector_alignment_reachable
614 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
615 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
616 arm_builtin_support_vector_misalignment
618 #undef TARGET_PREFERRED_RENAME_CLASS
619 #define TARGET_PREFERRED_RENAME_CLASS \
620 arm_preferred_rename_class
622 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
623 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
624 arm_vectorize_vec_perm_const_ok
626 struct gcc_target targetm = TARGET_INITIALIZER;
628 /* Obstack for minipool constant handling. */
629 static struct obstack minipool_obstack;
630 static char * minipool_startobj;
632 /* The maximum number of insns skipped which
633 will be conditionalised if possible. */
634 static int max_insns_skipped = 5;
636 extern FILE * asm_out_file;
638 /* True if we are currently building a constant table. */
639 int making_const_table;
641 /* The processor for which instructions should be scheduled. */
642 enum processor_type arm_tune = arm_none;
644 /* The current tuning set. */
645 const struct tune_params *current_tune;
647 /* Which floating point hardware to schedule for. */
650 /* Which floating popint hardware to use. */
651 const struct arm_fpu_desc *arm_fpu_desc;
653 /* Used for Thumb call_via trampolines. */
654 rtx thumb_call_via_label[14];
655 static int thumb_call_reg_needed;
657 /* Bit values used to identify processor capabilities. */
658 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
659 #define FL_ARCH3M (1 << 1) /* Extended multiply */
660 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
661 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
662 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
663 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
664 #define FL_THUMB (1 << 6) /* Thumb aware */
665 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
666 #define FL_STRONG (1 << 8) /* StrongARM */
667 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
668 #define FL_XSCALE (1 << 10) /* XScale */
669 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
670 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
671 media instructions. */
672 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
673 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
674 Note: ARM6 & 7 derivatives only. */
675 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
676 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
677 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
679 #define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
680 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
681 #define FL_NEON (1 << 20) /* Neon instructions. */
682 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
684 #define FL_ARCH7 (1 << 22) /* Architecture 7. */
685 #define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
687 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
689 /* Flags that only effect tuning, not available instructions. */
690 #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
693 #define FL_FOR_ARCH2 FL_NOTM
694 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
695 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
696 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
697 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
698 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
699 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
700 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
701 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
702 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
703 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
704 #define FL_FOR_ARCH6J FL_FOR_ARCH6
705 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
706 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
707 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
708 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
709 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
710 #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
711 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
712 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
713 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
714 #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
716 /* The bits in this mask specify which
717 instructions we are allowed to generate. */
718 static unsigned long insn_flags = 0;
720 /* The bits in this mask specify which instruction scheduling options should
722 static unsigned long tune_flags = 0;
724 /* The following are used in the arm.md file as equivalents to bits
725 in the above two flag variables. */
727 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
730 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
733 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
736 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
739 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
742 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
745 /* Nonzero if this chip supports the ARM 6K extensions. */
748 /* Nonzero if instructions present in ARMv6-M can be used. */
751 /* Nonzero if this chip supports the ARM 7 extensions. */
754 /* Nonzero if instructions not present in the 'M' profile can be used. */
755 int arm_arch_notm = 0;
757 /* Nonzero if instructions present in ARMv7E-M can be used. */
760 /* Nonzero if this chip can benefit from load scheduling. */
761 int arm_ld_sched = 0;
763 /* Nonzero if this chip is a StrongARM. */
764 int arm_tune_strongarm = 0;
766 /* Nonzero if this chip is a Cirrus variant. */
767 int arm_arch_cirrus = 0;
769 /* Nonzero if this chip supports Intel Wireless MMX technology. */
770 int arm_arch_iwmmxt = 0;
772 /* Nonzero if this chip is an XScale. */
773 int arm_arch_xscale = 0;
775 /* Nonzero if tuning for XScale */
776 int arm_tune_xscale = 0;
778 /* Nonzero if we want to tune for stores that access the write-buffer.
779 This typically means an ARM6 or ARM7 with MMU or MPU. */
780 int arm_tune_wbuf = 0;
782 /* Nonzero if tuning for Cortex-A9. */
783 int arm_tune_cortex_a9 = 0;
785 /* Nonzero if generating Thumb instructions. */
788 /* Nonzero if generating Thumb-1 instructions. */
791 /* Nonzero if we should define __THUMB_INTERWORK__ in the
793 XXX This is a bit of a hack, it's intended to help work around
794 problems in GLD which doesn't understand that armv5t code is
795 interworking clean. */
796 int arm_cpp_interwork = 0;
798 /* Nonzero if chip supports Thumb 2. */
801 /* Nonzero if chip supports integer division instruction. */
802 int arm_arch_arm_hwdiv;
803 int arm_arch_thumb_hwdiv;
805 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
806 we must report the mode of the memory reference from
807 TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */
808 enum machine_mode output_memory_reference_mode;
810 /* The register number to be used for the PIC offset register. */
811 unsigned arm_pic_register = INVALID_REGNUM;
813 /* Set to 1 after arm_reorg has started. Reset to start at the start of
814 the next function. */
815 static int after_arm_reorg = 0;
817 enum arm_pcs arm_pcs_default;
819 /* For an explanation of these variables, see final_prescan_insn below. */
821 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
822 enum arm_cond_code arm_current_cc;
825 int arm_target_label;
826 /* The number of conditionally executed insns, including the current insn. */
827 int arm_condexec_count = 0;
828 /* A bitmask specifying the patterns for the IT block.
829 Zero means do not output an IT block before this insn. */
830 int arm_condexec_mask = 0;
831 /* The number of bits used in arm_condexec_mask. */
832 int arm_condexec_masklen = 0;
834 /* The condition codes of the ARM, and the inverse function. */
835 static const char * const arm_condition_codes[] =
837 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
838 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
841 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
842 int arm_regs_in_sequence[] =
844 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
847 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
848 #define streq(string1, string2) (strcmp (string1, string2) == 0)
850 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
851 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
852 | (1 << PIC_OFFSET_TABLE_REGNUM)))
854 /* Initialization code. */
858 const char *const name;
859 enum processor_type core;
861 const unsigned long flags;
862 const struct tune_params *const tune;
866 #define ARM_PREFETCH_NOT_BENEFICIAL 0, -1, -1
867 #define ARM_PREFETCH_BENEFICIAL(prefetch_slots,l1_size,l1_line_size) \
872 const struct tune_params arm_slowmul_tune =
874 arm_slowmul_rtx_costs,
876 3, /* Constant limit. */
877 5, /* Max cond insns. */
878 ARM_PREFETCH_NOT_BENEFICIAL,
879 true, /* Prefer constant pool. */
880 arm_default_branch_cost
883 const struct tune_params arm_fastmul_tune =
885 arm_fastmul_rtx_costs,
887 1, /* Constant limit. */
888 5, /* Max cond insns. */
889 ARM_PREFETCH_NOT_BENEFICIAL,
890 true, /* Prefer constant pool. */
891 arm_default_branch_cost
894 /* StrongARM has early execution of branches, so a sequence that is worth
895 skipping is shorter. Set max_insns_skipped to a lower value. */
897 const struct tune_params arm_strongarm_tune =
899 arm_fastmul_rtx_costs,
901 1, /* Constant limit. */
902 3, /* Max cond insns. */
903 ARM_PREFETCH_NOT_BENEFICIAL,
904 true, /* Prefer constant pool. */
905 arm_default_branch_cost
908 const struct tune_params arm_xscale_tune =
910 arm_xscale_rtx_costs,
911 xscale_sched_adjust_cost,
912 2, /* Constant limit. */
913 3, /* Max cond insns. */
914 ARM_PREFETCH_NOT_BENEFICIAL,
915 true, /* Prefer constant pool. */
916 arm_default_branch_cost
919 const struct tune_params arm_9e_tune =
923 1, /* Constant limit. */
924 5, /* Max cond insns. */
925 ARM_PREFETCH_NOT_BENEFICIAL,
926 true, /* Prefer constant pool. */
927 arm_default_branch_cost
930 const struct tune_params arm_v6t2_tune =
934 1, /* Constant limit. */
935 5, /* Max cond insns. */
936 ARM_PREFETCH_NOT_BENEFICIAL,
937 false, /* Prefer constant pool. */
938 arm_default_branch_cost
941 /* Generic Cortex tuning. Use more specific tunings if appropriate. */
942 const struct tune_params arm_cortex_tune =
946 1, /* Constant limit. */
947 5, /* Max cond insns. */
948 ARM_PREFETCH_NOT_BENEFICIAL,
949 false, /* Prefer constant pool. */
950 arm_default_branch_cost
953 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
954 less appealing. Set max_insns_skipped to a low value. */
956 const struct tune_params arm_cortex_a5_tune =
960 1, /* Constant limit. */
961 1, /* Max cond insns. */
962 ARM_PREFETCH_NOT_BENEFICIAL,
963 false, /* Prefer constant pool. */
964 arm_cortex_a5_branch_cost
967 const struct tune_params arm_cortex_a9_tune =
970 cortex_a9_sched_adjust_cost,
971 1, /* Constant limit. */
972 5, /* Max cond insns. */
973 ARM_PREFETCH_BENEFICIAL(4,32,32),
974 false, /* Prefer constant pool. */
975 arm_default_branch_cost
978 const struct tune_params arm_fa726te_tune =
981 fa726te_sched_adjust_cost,
982 1, /* Constant limit. */
983 5, /* Max cond insns. */
984 ARM_PREFETCH_NOT_BENEFICIAL,
985 true, /* Prefer constant pool. */
986 arm_default_branch_cost
990 /* Not all of these give usefully different compilation alternatives,
991 but there is no simple way of generalizing them. */
992 static const struct processors all_cores[] =
995 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
996 {NAME, IDENT, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
997 #include "arm-cores.def"
999 {NULL, arm_none, NULL, 0, NULL}
1002 static const struct processors all_architectures[] =
1004 /* ARM Architectures */
1005 /* We don't specify tuning costs here as it will be figured out
1008 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
1009 {NAME, CORE, #ARCH, FLAGS, NULL},
1010 #include "arm-arches.def"
1012 {NULL, arm_none, NULL, 0 , NULL}
1016 /* These are populated as commandline arguments are processed, or NULL
1017 if not specified. */
1018 static const struct processors *arm_selected_arch;
1019 static const struct processors *arm_selected_cpu;
1020 static const struct processors *arm_selected_tune;
1022 /* The name of the preprocessor macro to define for this architecture. */
1024 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
1026 /* Available values for -mfpu=. */
1028 static const struct arm_fpu_desc all_fpus[] =
1030 #define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16) \
1031 { NAME, MODEL, REV, VFP_REGS, NEON, FP16 },
1032 #include "arm-fpus.def"
1037 /* Supported TLS relocations. */
1045 TLS_DESCSEQ /* GNU scheme */
1048 /* The maximum number of insns to be used when loading a constant. */
1050 arm_constant_limit (bool size_p)
1052 return size_p ? 1 : current_tune->constant_limit;
1055 /* Emit an insn that's a simple single-set. Both the operands must be known
1058 emit_set_insn (rtx x, rtx y)
1060 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
1063 /* Return the number of bits set in VALUE. */
1065 bit_count (unsigned long value)
1067 unsigned long count = 0;
1072 value &= value - 1; /* Clear the least-significant set bit. */
1080 enum machine_mode mode;
1082 } arm_fixed_mode_set;
1084 /* A small helper for setting fixed-point library libfuncs. */
1087 arm_set_fixed_optab_libfunc (optab optable, enum machine_mode mode,
1088 const char *funcname, const char *modename,
1093 if (num_suffix == 0)
1094 sprintf (buffer, "__gnu_%s%s", funcname, modename);
1096 sprintf (buffer, "__gnu_%s%s%d", funcname, modename, num_suffix);
1098 set_optab_libfunc (optable, mode, buffer);
1102 arm_set_fixed_conv_libfunc (convert_optab optable, enum machine_mode to,
1103 enum machine_mode from, const char *funcname,
1104 const char *toname, const char *fromname)
1107 const char *maybe_suffix_2 = "";
1109 /* Follow the logic for selecting a "2" suffix in fixed-bit.h. */
1110 if (ALL_FIXED_POINT_MODE_P (from) && ALL_FIXED_POINT_MODE_P (to)
1111 && UNSIGNED_FIXED_POINT_MODE_P (from) == UNSIGNED_FIXED_POINT_MODE_P (to)
1112 && ALL_FRACT_MODE_P (from) == ALL_FRACT_MODE_P (to))
1113 maybe_suffix_2 = "2";
1115 sprintf (buffer, "__gnu_%s%s%s%s", funcname, fromname, toname,
1118 set_conv_libfunc (optable, to, from, buffer);
1121 /* Set up library functions unique to ARM. */
1124 arm_init_libfuncs (void)
1126 /* For Linux, we have access to kernel support for atomic operations. */
1127 if (arm_abi == ARM_ABI_AAPCS_LINUX)
1128 init_sync_libfuncs (2 * UNITS_PER_WORD);
1130 /* There are no special library functions unless we are using the
1135 /* The functions below are described in Section 4 of the "Run-Time
1136 ABI for the ARM architecture", Version 1.0. */
1138 /* Double-precision floating-point arithmetic. Table 2. */
1139 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
1140 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
1141 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
1142 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
1143 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
1145 /* Double-precision comparisons. Table 3. */
1146 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
1147 set_optab_libfunc (ne_optab, DFmode, NULL);
1148 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
1149 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
1150 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
1151 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
1152 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
1154 /* Single-precision floating-point arithmetic. Table 4. */
1155 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
1156 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
1157 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
1158 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
1159 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
1161 /* Single-precision comparisons. Table 5. */
1162 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
1163 set_optab_libfunc (ne_optab, SFmode, NULL);
1164 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
1165 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
1166 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
1167 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
1168 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
1170 /* Floating-point to integer conversions. Table 6. */
1171 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
1172 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
1173 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
1174 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
1175 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
1176 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
1177 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
1178 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
1180 /* Conversions between floating types. Table 7. */
1181 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
1182 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
1184 /* Integer to floating-point conversions. Table 8. */
1185 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
1186 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
1187 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
1188 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
1189 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
1190 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
1191 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
1192 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
1194 /* Long long. Table 9. */
1195 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
1196 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
1197 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
1198 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
1199 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
1200 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
1201 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
1202 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
1204 /* Integer (32/32->32) division. \S 4.3.1. */
1205 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
1206 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
1208 /* The divmod functions are designed so that they can be used for
1209 plain division, even though they return both the quotient and the
1210 remainder. The quotient is returned in the usual location (i.e.,
1211 r0 for SImode, {r0, r1} for DImode), just as would be expected
1212 for an ordinary division routine. Because the AAPCS calling
1213 conventions specify that all of { r0, r1, r2, r3 } are
1214 callee-saved registers, there is no need to tell the compiler
1215 explicitly that those registers are clobbered by these
1217 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
1218 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
1220 /* For SImode division the ABI provides div-without-mod routines,
1221 which are faster. */
1222 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
1223 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
1225 /* We don't have mod libcalls. Fortunately gcc knows how to use the
1226 divmod libcalls instead. */
1227 set_optab_libfunc (smod_optab, DImode, NULL);
1228 set_optab_libfunc (umod_optab, DImode, NULL);
1229 set_optab_libfunc (smod_optab, SImode, NULL);
1230 set_optab_libfunc (umod_optab, SImode, NULL);
1232 /* Half-precision float operations. The compiler handles all operations
1233 with NULL libfuncs by converting the SFmode. */
1234 switch (arm_fp16_format)
1236 case ARM_FP16_FORMAT_IEEE:
1237 case ARM_FP16_FORMAT_ALTERNATIVE:
1240 set_conv_libfunc (trunc_optab, HFmode, SFmode,
1241 (arm_fp16_format == ARM_FP16_FORMAT_IEEE
1243 : "__gnu_f2h_alternative"));
1244 set_conv_libfunc (sext_optab, SFmode, HFmode,
1245 (arm_fp16_format == ARM_FP16_FORMAT_IEEE
1247 : "__gnu_h2f_alternative"));
1250 set_optab_libfunc (add_optab, HFmode, NULL);
1251 set_optab_libfunc (sdiv_optab, HFmode, NULL);
1252 set_optab_libfunc (smul_optab, HFmode, NULL);
1253 set_optab_libfunc (neg_optab, HFmode, NULL);
1254 set_optab_libfunc (sub_optab, HFmode, NULL);
1257 set_optab_libfunc (eq_optab, HFmode, NULL);
1258 set_optab_libfunc (ne_optab, HFmode, NULL);
1259 set_optab_libfunc (lt_optab, HFmode, NULL);
1260 set_optab_libfunc (le_optab, HFmode, NULL);
1261 set_optab_libfunc (ge_optab, HFmode, NULL);
1262 set_optab_libfunc (gt_optab, HFmode, NULL);
1263 set_optab_libfunc (unord_optab, HFmode, NULL);
1270 /* Use names prefixed with __gnu_ for fixed-point helper functions. */
1272 const arm_fixed_mode_set fixed_arith_modes[] =
1293 const arm_fixed_mode_set fixed_conv_modes[] =
1323 for (i = 0; i < ARRAY_SIZE (fixed_arith_modes); i++)
1325 arm_set_fixed_optab_libfunc (add_optab, fixed_arith_modes[i].mode,
1326 "add", fixed_arith_modes[i].name, 3);
1327 arm_set_fixed_optab_libfunc (ssadd_optab, fixed_arith_modes[i].mode,
1328 "ssadd", fixed_arith_modes[i].name, 3);
1329 arm_set_fixed_optab_libfunc (usadd_optab, fixed_arith_modes[i].mode,
1330 "usadd", fixed_arith_modes[i].name, 3);
1331 arm_set_fixed_optab_libfunc (sub_optab, fixed_arith_modes[i].mode,
1332 "sub", fixed_arith_modes[i].name, 3);
1333 arm_set_fixed_optab_libfunc (sssub_optab, fixed_arith_modes[i].mode,
1334 "sssub", fixed_arith_modes[i].name, 3);
1335 arm_set_fixed_optab_libfunc (ussub_optab, fixed_arith_modes[i].mode,
1336 "ussub", fixed_arith_modes[i].name, 3);
1337 arm_set_fixed_optab_libfunc (smul_optab, fixed_arith_modes[i].mode,
1338 "mul", fixed_arith_modes[i].name, 3);
1339 arm_set_fixed_optab_libfunc (ssmul_optab, fixed_arith_modes[i].mode,
1340 "ssmul", fixed_arith_modes[i].name, 3);
1341 arm_set_fixed_optab_libfunc (usmul_optab, fixed_arith_modes[i].mode,
1342 "usmul", fixed_arith_modes[i].name, 3);
1343 arm_set_fixed_optab_libfunc (sdiv_optab, fixed_arith_modes[i].mode,
1344 "div", fixed_arith_modes[i].name, 3);
1345 arm_set_fixed_optab_libfunc (udiv_optab, fixed_arith_modes[i].mode,
1346 "udiv", fixed_arith_modes[i].name, 3);
1347 arm_set_fixed_optab_libfunc (ssdiv_optab, fixed_arith_modes[i].mode,
1348 "ssdiv", fixed_arith_modes[i].name, 3);
1349 arm_set_fixed_optab_libfunc (usdiv_optab, fixed_arith_modes[i].mode,
1350 "usdiv", fixed_arith_modes[i].name, 3);
1351 arm_set_fixed_optab_libfunc (neg_optab, fixed_arith_modes[i].mode,
1352 "neg", fixed_arith_modes[i].name, 2);
1353 arm_set_fixed_optab_libfunc (ssneg_optab, fixed_arith_modes[i].mode,
1354 "ssneg", fixed_arith_modes[i].name, 2);
1355 arm_set_fixed_optab_libfunc (usneg_optab, fixed_arith_modes[i].mode,
1356 "usneg", fixed_arith_modes[i].name, 2);
1357 arm_set_fixed_optab_libfunc (ashl_optab, fixed_arith_modes[i].mode,
1358 "ashl", fixed_arith_modes[i].name, 3);
1359 arm_set_fixed_optab_libfunc (ashr_optab, fixed_arith_modes[i].mode,
1360 "ashr", fixed_arith_modes[i].name, 3);
1361 arm_set_fixed_optab_libfunc (lshr_optab, fixed_arith_modes[i].mode,
1362 "lshr", fixed_arith_modes[i].name, 3);
1363 arm_set_fixed_optab_libfunc (ssashl_optab, fixed_arith_modes[i].mode,
1364 "ssashl", fixed_arith_modes[i].name, 3);
1365 arm_set_fixed_optab_libfunc (usashl_optab, fixed_arith_modes[i].mode,
1366 "usashl", fixed_arith_modes[i].name, 3);
1367 arm_set_fixed_optab_libfunc (cmp_optab, fixed_arith_modes[i].mode,
1368 "cmp", fixed_arith_modes[i].name, 2);
1371 for (i = 0; i < ARRAY_SIZE (fixed_conv_modes); i++)
1372 for (j = 0; j < ARRAY_SIZE (fixed_conv_modes); j++)
1375 || (!ALL_FIXED_POINT_MODE_P (fixed_conv_modes[i].mode)
1376 && !ALL_FIXED_POINT_MODE_P (fixed_conv_modes[j].mode)))
1379 arm_set_fixed_conv_libfunc (fract_optab, fixed_conv_modes[i].mode,
1380 fixed_conv_modes[j].mode, "fract",
1381 fixed_conv_modes[i].name,
1382 fixed_conv_modes[j].name);
1383 arm_set_fixed_conv_libfunc (satfract_optab,
1384 fixed_conv_modes[i].mode,
1385 fixed_conv_modes[j].mode, "satfract",
1386 fixed_conv_modes[i].name,
1387 fixed_conv_modes[j].name);
1388 arm_set_fixed_conv_libfunc (fractuns_optab,
1389 fixed_conv_modes[i].mode,
1390 fixed_conv_modes[j].mode, "fractuns",
1391 fixed_conv_modes[i].name,
1392 fixed_conv_modes[j].name);
1393 arm_set_fixed_conv_libfunc (satfractuns_optab,
1394 fixed_conv_modes[i].mode,
1395 fixed_conv_modes[j].mode, "satfractuns",
1396 fixed_conv_modes[i].name,
1397 fixed_conv_modes[j].name);
1401 if (TARGET_AAPCS_BASED)
1402 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
1405 /* On AAPCS systems, this is the "struct __va_list". */
1406 static GTY(()) tree va_list_type;
1408 /* Return the type to use as __builtin_va_list. */
1410 arm_build_builtin_va_list (void)
1415 if (!TARGET_AAPCS_BASED)
1416 return std_build_builtin_va_list ();
1418 /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type
1426 The C Library ABI further reinforces this definition in \S
1429 We must follow this definition exactly. The structure tag
1430 name is visible in C++ mangled names, and thus forms a part
1431 of the ABI. The field name may be used by people who
1432 #include <stdarg.h>. */
1433 /* Create the type. */
1434 va_list_type = lang_hooks.types.make_type (RECORD_TYPE);
1435 /* Give it the required name. */
1436 va_list_name = build_decl (BUILTINS_LOCATION,
1438 get_identifier ("__va_list"),
1440 DECL_ARTIFICIAL (va_list_name) = 1;
1441 TYPE_NAME (va_list_type) = va_list_name;
1442 TYPE_STUB_DECL (va_list_type) = va_list_name;
1443 /* Create the __ap field. */
1444 ap_field = build_decl (BUILTINS_LOCATION,
1446 get_identifier ("__ap"),
1448 DECL_ARTIFICIAL (ap_field) = 1;
1449 DECL_FIELD_CONTEXT (ap_field) = va_list_type;
1450 TYPE_FIELDS (va_list_type) = ap_field;
1451 /* Compute its layout. */
1452 layout_type (va_list_type);
1454 return va_list_type;
1457 /* Return an expression of type "void *" pointing to the next
1458 available argument in a variable-argument list. VALIST is the
1459 user-level va_list object, of type __builtin_va_list. */
1461 arm_extract_valist_ptr (tree valist)
1463 if (TREE_TYPE (valist) == error_mark_node)
1464 return error_mark_node;
1466 /* On an AAPCS target, the pointer is stored within "struct
1468 if (TARGET_AAPCS_BASED)
1470 tree ap_field = TYPE_FIELDS (TREE_TYPE (valist));
1471 valist = build3 (COMPONENT_REF, TREE_TYPE (ap_field),
1472 valist, ap_field, NULL_TREE);
1478 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
1480 arm_expand_builtin_va_start (tree valist, rtx nextarg)
1482 valist = arm_extract_valist_ptr (valist);
1483 std_expand_builtin_va_start (valist, nextarg);
1486 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
1488 arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
1491 valist = arm_extract_valist_ptr (valist);
1492 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
1495 /* Fix up any incompatible options that the user has specified. */
1497 arm_option_override (void)
1499 if (global_options_set.x_arm_arch_option)
1500 arm_selected_arch = &all_architectures[arm_arch_option];
1502 if (global_options_set.x_arm_cpu_option)
1503 arm_selected_cpu = &all_cores[(int) arm_cpu_option];
1505 if (global_options_set.x_arm_tune_option)
1506 arm_selected_tune = &all_cores[(int) arm_tune_option];
1508 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1509 SUBTARGET_OVERRIDE_OPTIONS;
1512 if (arm_selected_arch)
1514 if (arm_selected_cpu)
1516 /* Check for conflict between mcpu and march. */
1517 if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE)
1519 warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
1520 arm_selected_cpu->name, arm_selected_arch->name);
1521 /* -march wins for code generation.
1522 -mcpu wins for default tuning. */
1523 if (!arm_selected_tune)
1524 arm_selected_tune = arm_selected_cpu;
1526 arm_selected_cpu = arm_selected_arch;
1530 arm_selected_arch = NULL;
1533 /* Pick a CPU based on the architecture. */
1534 arm_selected_cpu = arm_selected_arch;
1537 /* If the user did not specify a processor, choose one for them. */
1538 if (!arm_selected_cpu)
1540 const struct processors * sel;
1541 unsigned int sought;
1543 arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT];
1544 if (!arm_selected_cpu->name)
1546 #ifdef SUBTARGET_CPU_DEFAULT
1547 /* Use the subtarget default CPU if none was specified by
1549 arm_selected_cpu = &all_cores[SUBTARGET_CPU_DEFAULT];
1551 /* Default to ARM6. */
1552 if (!arm_selected_cpu->name)
1553 arm_selected_cpu = &all_cores[arm6];
1556 sel = arm_selected_cpu;
1557 insn_flags = sel->flags;
1559 /* Now check to see if the user has specified some command line
1560 switch that require certain abilities from the cpu. */
1563 if (TARGET_INTERWORK || TARGET_THUMB)
1565 sought |= (FL_THUMB | FL_MODE32);
1567 /* There are no ARM processors that support both APCS-26 and
1568 interworking. Therefore we force FL_MODE26 to be removed
1569 from insn_flags here (if it was set), so that the search
1570 below will always be able to find a compatible processor. */
1571 insn_flags &= ~FL_MODE26;
1574 if (sought != 0 && ((sought & insn_flags) != sought))
1576 /* Try to locate a CPU type that supports all of the abilities
1577 of the default CPU, plus the extra abilities requested by
1579 for (sel = all_cores; sel->name != NULL; sel++)
1580 if ((sel->flags & sought) == (sought | insn_flags))
1583 if (sel->name == NULL)
1585 unsigned current_bit_count = 0;
1586 const struct processors * best_fit = NULL;
1588 /* Ideally we would like to issue an error message here
1589 saying that it was not possible to find a CPU compatible
1590 with the default CPU, but which also supports the command
1591 line options specified by the programmer, and so they
1592 ought to use the -mcpu=<name> command line option to
1593 override the default CPU type.
1595 If we cannot find a cpu that has both the
1596 characteristics of the default cpu and the given
1597 command line options we scan the array again looking
1598 for a best match. */
1599 for (sel = all_cores; sel->name != NULL; sel++)
1600 if ((sel->flags & sought) == sought)
1604 count = bit_count (sel->flags & insn_flags);
1606 if (count >= current_bit_count)
1609 current_bit_count = count;
1613 gcc_assert (best_fit);
1617 arm_selected_cpu = sel;
1621 gcc_assert (arm_selected_cpu);
1622 /* The selected cpu may be an architecture, so lookup tuning by core ID. */
1623 if (!arm_selected_tune)
1624 arm_selected_tune = &all_cores[arm_selected_cpu->core];
1626 sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch);
1627 insn_flags = arm_selected_cpu->flags;
1629 arm_tune = arm_selected_tune->core;
1630 tune_flags = arm_selected_tune->flags;
1631 current_tune = arm_selected_tune->tune;
1633 /* Make sure that the processor choice does not conflict with any of the
1634 other command line choices. */
1635 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1636 error ("target CPU does not support ARM mode");
1638 /* BPABI targets use linker tricks to allow interworking on cores
1639 without thumb support. */
1640 if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI))
1642 warning (0, "target CPU does not support interworking" );
1643 target_flags &= ~MASK_INTERWORK;
1646 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1648 warning (0, "target CPU does not support THUMB instructions");
1649 target_flags &= ~MASK_THUMB;
1652 if (TARGET_APCS_FRAME && TARGET_THUMB)
1654 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1655 target_flags &= ~MASK_APCS_FRAME;
1658 /* Callee super interworking implies thumb interworking. Adding
1659 this to the flags here simplifies the logic elsewhere. */
1660 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1661 target_flags |= MASK_INTERWORK;
1663 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1664 from here where no function is being compiled currently. */
1665 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1666 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1668 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1669 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1671 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1673 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1674 target_flags |= MASK_APCS_FRAME;
1677 if (TARGET_POKE_FUNCTION_NAME)
1678 target_flags |= MASK_APCS_FRAME;
1680 if (TARGET_APCS_REENT && flag_pic)
1681 error ("-fpic and -mapcs-reent are incompatible");
1683 if (TARGET_APCS_REENT)
1684 warning (0, "APCS reentrant code not supported. Ignored");
1686 /* If this target is normally configured to use APCS frames, warn if they
1687 are turned off and debugging is turned on. */
1689 && write_symbols != NO_DEBUG
1690 && !TARGET_APCS_FRAME
1691 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1692 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1694 if (TARGET_APCS_FLOAT)
1695 warning (0, "passing floating point arguments in fp regs not yet supported");
1697 if (TARGET_LITTLE_WORDS)
1698 warning (OPT_Wdeprecated, "%<mwords-little-endian%> is deprecated and "
1699 "will be removed in a future release");
1701 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1702 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1703 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1704 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1705 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1706 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1707 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1708 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1709 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1710 arm_arch6m = arm_arch6 && !arm_arch_notm;
1711 arm_arch7 = (insn_flags & FL_ARCH7) != 0;
1712 arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
1713 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1714 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1715 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1717 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1718 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1719 thumb_code = TARGET_ARM == 0;
1720 thumb1_code = TARGET_THUMB1 != 0;
1721 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1722 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1723 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1724 arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
1725 arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
1726 arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
1728 /* If we are not using the default (ARM mode) section anchor offset
1729 ranges, then set the correct ranges now. */
1732 /* Thumb-1 LDR instructions cannot have negative offsets.
1733 Permissible positive offset ranges are 5-bit (for byte loads),
1734 6-bit (for halfword loads), or 7-bit (for word loads).
1735 Empirical results suggest a 7-bit anchor range gives the best
1736 overall code size. */
1737 targetm.min_anchor_offset = 0;
1738 targetm.max_anchor_offset = 127;
1740 else if (TARGET_THUMB2)
1742 /* The minimum is set such that the total size of the block
1743 for a particular anchor is 248 + 1 + 4095 bytes, which is
1744 divisible by eight, ensuring natural spacing of anchors. */
1745 targetm.min_anchor_offset = -248;
1746 targetm.max_anchor_offset = 4095;
1749 /* V5 code we generate is completely interworking capable, so we turn off
1750 TARGET_INTERWORK here to avoid many tests later on. */
1752 /* XXX However, we must pass the right pre-processor defines to CPP
1753 or GLD can get confused. This is a hack. */
1754 if (TARGET_INTERWORK)
1755 arm_cpp_interwork = 1;
1758 target_flags &= ~MASK_INTERWORK;
1760 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1761 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1763 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1764 error ("iwmmxt abi requires an iwmmxt capable cpu");
1766 if (!global_options_set.x_arm_fpu_index)
1768 const char *target_fpu_name;
1771 #ifdef FPUTYPE_DEFAULT
1772 target_fpu_name = FPUTYPE_DEFAULT;
1774 if (arm_arch_cirrus)
1775 target_fpu_name = "maverick";
1777 target_fpu_name = "fpe2";
1780 ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index,
1785 arm_fpu_desc = &all_fpus[arm_fpu_index];
1787 switch (arm_fpu_desc->model)
1789 case ARM_FP_MODEL_FPA:
1790 if (arm_fpu_desc->rev == 2)
1791 arm_fpu_attr = FPU_FPE2;
1792 else if (arm_fpu_desc->rev == 3)
1793 arm_fpu_attr = FPU_FPE3;
1795 arm_fpu_attr = FPU_FPA;
1798 case ARM_FP_MODEL_MAVERICK:
1799 arm_fpu_attr = FPU_MAVERICK;
1802 case ARM_FP_MODEL_VFP:
1803 arm_fpu_attr = FPU_VFP;
1810 if (TARGET_AAPCS_BASED
1811 && (arm_fpu_desc->model == ARM_FP_MODEL_FPA))
1812 error ("FPA is unsupported in the AAPCS");
1814 if (TARGET_AAPCS_BASED)
1816 if (TARGET_CALLER_INTERWORKING)
1817 error ("AAPCS does not support -mcaller-super-interworking");
1819 if (TARGET_CALLEE_INTERWORKING)
1820 error ("AAPCS does not support -mcallee-super-interworking");
1823 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1824 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1825 will ever exist. GCC makes no attempt to support this combination. */
1826 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1827 sorry ("iWMMXt and hardware floating point");
1829 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1830 if (TARGET_THUMB2 && TARGET_IWMMXT)
1831 sorry ("Thumb-2 iWMMXt");
1833 /* __fp16 support currently assumes the core has ldrh. */
1834 if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
1835 sorry ("__fp16 and no ldrh");
1837 /* If soft-float is specified then don't use FPU. */
1838 if (TARGET_SOFT_FLOAT)
1839 arm_fpu_attr = FPU_NONE;
1841 if (TARGET_AAPCS_BASED)
1843 if (arm_abi == ARM_ABI_IWMMXT)
1844 arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
1845 else if (arm_float_abi == ARM_FLOAT_ABI_HARD
1846 && TARGET_HARD_FLOAT
1848 arm_pcs_default = ARM_PCS_AAPCS_VFP;
1850 arm_pcs_default = ARM_PCS_AAPCS;
1854 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1855 sorry ("-mfloat-abi=hard and VFP");
1857 if (arm_abi == ARM_ABI_APCS)
1858 arm_pcs_default = ARM_PCS_APCS;
1860 arm_pcs_default = ARM_PCS_ATPCS;
1863 /* For arm2/3 there is no need to do any scheduling if there is only
1864 a floating point emulator, or we are doing software floating-point. */
1865 if ((TARGET_SOFT_FLOAT
1866 || (TARGET_FPA && arm_fpu_desc->rev))
1867 && (tune_flags & FL_MODE32) == 0)
1868 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1870 /* Use the cp15 method if it is available. */
1871 if (target_thread_pointer == TP_AUTO)
1873 if (arm_arch6k && !TARGET_THUMB1)
1874 target_thread_pointer = TP_CP15;
1876 target_thread_pointer = TP_SOFT;
1879 if (TARGET_HARD_TP && TARGET_THUMB1)
1880 error ("can not use -mtp=cp15 with 16-bit Thumb");
1882 /* Override the default structure alignment for AAPCS ABI. */
1883 if (!global_options_set.x_arm_structure_size_boundary)
1885 if (TARGET_AAPCS_BASED)
1886 arm_structure_size_boundary = 8;
1890 if (arm_structure_size_boundary != 8
1891 && arm_structure_size_boundary != 32
1892 && !(ARM_DOUBLEWORD_ALIGN && arm_structure_size_boundary == 64))
1894 if (ARM_DOUBLEWORD_ALIGN)
1896 "structure size boundary can only be set to 8, 32 or 64");
1898 warning (0, "structure size boundary can only be set to 8 or 32");
1899 arm_structure_size_boundary
1900 = (TARGET_AAPCS_BASED ? 8 : DEFAULT_STRUCTURE_SIZE_BOUNDARY);
1904 if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
1906 error ("RTP PIC is incompatible with Thumb");
1910 /* If stack checking is disabled, we can use r10 as the PIC register,
1911 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1912 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1914 if (TARGET_VXWORKS_RTP)
1915 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1916 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1919 if (flag_pic && TARGET_VXWORKS_RTP)
1920 arm_pic_register = 9;
1922 if (arm_pic_register_string != NULL)
1924 int pic_register = decode_reg_name (arm_pic_register_string);
1927 warning (0, "-mpic-register= is useless without -fpic");
1929 /* Prevent the user from choosing an obviously stupid PIC register. */
1930 else if (pic_register < 0 || call_used_regs[pic_register]
1931 || pic_register == HARD_FRAME_POINTER_REGNUM
1932 || pic_register == STACK_POINTER_REGNUM
1933 || pic_register >= PC_REGNUM
1934 || (TARGET_VXWORKS_RTP
1935 && (unsigned int) pic_register != arm_pic_register))
1936 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1938 arm_pic_register = pic_register;
1941 /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
1942 if (fix_cm3_ldrd == 2)
1944 if (arm_selected_cpu->core == cortexm3)
1950 /* Enable -munaligned-access by default for
1951 - all ARMv6 architecture-based processors
1952 - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
1954 Disable -munaligned-access by default for
1955 - all pre-ARMv6 architecture-based processors
1956 - ARMv6-M architecture-based processors. */
1958 if (unaligned_access == 2)
1960 if (arm_arch6 && (arm_arch_notm || arm_arch7))
1961 unaligned_access = 1;
1963 unaligned_access = 0;
1965 else if (unaligned_access == 1
1966 && !(arm_arch6 && (arm_arch_notm || arm_arch7)))
1968 warning (0, "target CPU does not support unaligned accesses");
1969 unaligned_access = 0;
1972 if (TARGET_THUMB1 && flag_schedule_insns)
1974 /* Don't warn since it's on by default in -O2. */
1975 flag_schedule_insns = 0;
1980 /* If optimizing for size, bump the number of instructions that we
1981 are prepared to conditionally execute (even on a StrongARM). */
1982 max_insns_skipped = 6;
1985 max_insns_skipped = current_tune->max_insns_skipped;
1987 /* Hot/Cold partitioning is not currently supported, since we can't
1988 handle literal pool placement in that case. */
1989 if (flag_reorder_blocks_and_partition)
1991 inform (input_location,
1992 "-freorder-blocks-and-partition not supported on this architecture");
1993 flag_reorder_blocks_and_partition = 0;
1994 flag_reorder_blocks = 1;
1998 /* Hoisting PIC address calculations more aggressively provides a small,
1999 but measurable, size reduction for PIC code. Therefore, we decrease
2000 the bar for unrestricted expression hoisting to the cost of PIC address
2001 calculation, which is 2 instructions. */
2002 maybe_set_param_value (PARAM_GCSE_UNRESTRICTED_COST, 2,
2003 global_options.x_param_values,
2004 global_options_set.x_param_values);
2006 /* ARM EABI defaults to strict volatile bitfields. */
2007 if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0
2008 && abi_version_at_least(2))
2009 flag_strict_volatile_bitfields = 1;
2011 /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed
2012 it beneficial (signified by setting num_prefetch_slots to 1 or more.) */
2013 if (flag_prefetch_loop_arrays < 0
2016 && current_tune->num_prefetch_slots > 0)
2017 flag_prefetch_loop_arrays = 1;
2019 /* Set up parameters to be used in prefetching algorithm. Do not override the
2020 defaults unless we are tuning for a core we have researched values for. */
2021 if (current_tune->num_prefetch_slots > 0)
2022 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
2023 current_tune->num_prefetch_slots,
2024 global_options.x_param_values,
2025 global_options_set.x_param_values);
2026 if (current_tune->l1_cache_line_size >= 0)
2027 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
2028 current_tune->l1_cache_line_size,
2029 global_options.x_param_values,
2030 global_options_set.x_param_values);
2031 if (current_tune->l1_cache_size >= 0)
2032 maybe_set_param_value (PARAM_L1_CACHE_SIZE,
2033 current_tune->l1_cache_size,
2034 global_options.x_param_values,
2035 global_options_set.x_param_values);
2037 /* Register global variables with the garbage collector. */
2038 arm_add_gc_roots ();
2042 arm_add_gc_roots (void)
2044 gcc_obstack_init(&minipool_obstack);
2045 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
2048 /* A table of known ARM exception types.
2049 For use with the interrupt function attribute. */
2053 const char *const arg;
2054 const unsigned long return_value;
2058 static const isr_attribute_arg isr_attribute_args [] =
2060 { "IRQ", ARM_FT_ISR },
2061 { "irq", ARM_FT_ISR },
2062 { "FIQ", ARM_FT_FIQ },
2063 { "fiq", ARM_FT_FIQ },
2064 { "ABORT", ARM_FT_ISR },
2065 { "abort", ARM_FT_ISR },
2066 { "ABORT", ARM_FT_ISR },
2067 { "abort", ARM_FT_ISR },
2068 { "UNDEF", ARM_FT_EXCEPTION },
2069 { "undef", ARM_FT_EXCEPTION },
2070 { "SWI", ARM_FT_EXCEPTION },
2071 { "swi", ARM_FT_EXCEPTION },
2072 { NULL, ARM_FT_NORMAL }
2075 /* Returns the (interrupt) function type of the current
2076 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
2078 static unsigned long
2079 arm_isr_value (tree argument)
2081 const isr_attribute_arg * ptr;
2085 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
2087 /* No argument - default to IRQ. */
2088 if (argument == NULL_TREE)
2091 /* Get the value of the argument. */
2092 if (TREE_VALUE (argument) == NULL_TREE
2093 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
2094 return ARM_FT_UNKNOWN;
2096 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
2098 /* Check it against the list of known arguments. */
2099 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
2100 if (streq (arg, ptr->arg))
2101 return ptr->return_value;
2103 /* An unrecognized interrupt type. */
2104 return ARM_FT_UNKNOWN;
2107 /* Computes the type of the current function. */
2109 static unsigned long
2110 arm_compute_func_type (void)
2112 unsigned long type = ARM_FT_UNKNOWN;
2116 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
2118 /* Decide if the current function is volatile. Such functions
2119 never return, and many memory cycles can be saved by not storing
2120 register values that will never be needed again. This optimization
2121 was added to speed up context switching in a kernel application. */
2123 && (TREE_NOTHROW (current_function_decl)
2124 || !(flag_unwind_tables
2126 && arm_except_unwind_info (&global_options) != UI_SJLJ)))
2127 && TREE_THIS_VOLATILE (current_function_decl))
2128 type |= ARM_FT_VOLATILE;
2130 if (cfun->static_chain_decl != NULL)
2131 type |= ARM_FT_NESTED;
2133 attr = DECL_ATTRIBUTES (current_function_decl);
2135 a = lookup_attribute ("naked", attr);
2137 type |= ARM_FT_NAKED;
2139 a = lookup_attribute ("isr", attr);
2141 a = lookup_attribute ("interrupt", attr);
2144 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
2146 type |= arm_isr_value (TREE_VALUE (a));
2151 /* Returns the type of the current function. */
2154 arm_current_func_type (void)
2156 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
2157 cfun->machine->func_type = arm_compute_func_type ();
2159 return cfun->machine->func_type;
2163 arm_allocate_stack_slots_for_args (void)
2165 /* Naked functions should not allocate stack slots for arguments. */
2166 return !IS_NAKED (arm_current_func_type ());
2170 /* Output assembler code for a block containing the constant parts
2171 of a trampoline, leaving space for the variable parts.
2173 On the ARM, (if r8 is the static chain regnum, and remembering that
2174 referencing pc adds an offset of 8) the trampoline looks like:
2177 .word static chain value
2178 .word function's address
2179 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
2182 arm_asm_trampoline_template (FILE *f)
2186 asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM, PC_REGNUM);
2187 asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", PC_REGNUM, PC_REGNUM);
2189 else if (TARGET_THUMB2)
2191 /* The Thumb-2 trampoline is similar to the arm implementation.
2192 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
2193 asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n",
2194 STATIC_CHAIN_REGNUM, PC_REGNUM);
2195 asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM, PC_REGNUM);
2199 ASM_OUTPUT_ALIGN (f, 2);
2200 fprintf (f, "\t.code\t16\n");
2201 fprintf (f, ".Ltrampoline_start:\n");
2202 asm_fprintf (f, "\tpush\t{r0, r1}\n");
2203 asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM);
2204 asm_fprintf (f, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM);
2205 asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM);
2206 asm_fprintf (f, "\tstr\tr0, [%r, #4]\n", SP_REGNUM);
2207 asm_fprintf (f, "\tpop\t{r0, %r}\n", PC_REGNUM);
2209 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
2210 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
2213 /* Emit RTL insns to initialize the variable parts of a trampoline. */
2216 arm_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2218 rtx fnaddr, mem, a_tramp;
2220 emit_block_move (m_tramp, assemble_trampoline_template (),
2221 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2223 mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 8 : 12);
2224 emit_move_insn (mem, chain_value);
2226 mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 12 : 16);
2227 fnaddr = XEXP (DECL_RTL (fndecl), 0);
2228 emit_move_insn (mem, fnaddr);
2230 a_tramp = XEXP (m_tramp, 0);
2231 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"),
2232 LCT_NORMAL, VOIDmode, 2, a_tramp, Pmode,
2233 plus_constant (a_tramp, TRAMPOLINE_SIZE), Pmode);
2236 /* Thumb trampolines should be entered in thumb mode, so set
2237 the bottom bit of the address. */
2240 arm_trampoline_adjust_address (rtx addr)
2243 addr = expand_simple_binop (Pmode, IOR, addr, const1_rtx,
2244 NULL, 0, OPTAB_LIB_WIDEN);
2248 /* Return 1 if it is possible to return using a single instruction.
2249 If SIBLING is non-null, this is a test for a return before a sibling
2250 call. SIBLING is the call insn, so we can examine its register usage. */
2253 use_return_insn (int iscond, rtx sibling)
2256 unsigned int func_type;
2257 unsigned long saved_int_regs;
2258 unsigned HOST_WIDE_INT stack_adjust;
2259 arm_stack_offsets *offsets;
2261 /* Never use a return instruction before reload has run. */
2262 if (!reload_completed)
2265 func_type = arm_current_func_type ();
2267 /* Naked, volatile and stack alignment functions need special
2269 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
2272 /* So do interrupt functions that use the frame pointer and Thumb
2273 interrupt functions. */
2274 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
2277 offsets = arm_get_frame_offsets ();
2278 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
2280 /* As do variadic functions. */
2281 if (crtl->args.pretend_args_size
2282 || cfun->machine->uses_anonymous_args
2283 /* Or if the function calls __builtin_eh_return () */
2284 || crtl->calls_eh_return
2285 /* Or if the function calls alloca */
2286 || cfun->calls_alloca
2287 /* Or if there is a stack adjustment. However, if the stack pointer
2288 is saved on the stack, we can use a pre-incrementing stack load. */
2289 || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed
2290 && stack_adjust == 4)))
2293 saved_int_regs = offsets->saved_regs_mask;
2295 /* Unfortunately, the insn
2297 ldmib sp, {..., sp, ...}
2299 triggers a bug on most SA-110 based devices, such that the stack
2300 pointer won't be correctly restored if the instruction takes a
2301 page fault. We work around this problem by popping r3 along with
2302 the other registers, since that is never slower than executing
2303 another instruction.
2305 We test for !arm_arch5 here, because code for any architecture
2306 less than this could potentially be run on one of the buggy
2308 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
2310 /* Validate that r3 is a call-clobbered register (always true in
2311 the default abi) ... */
2312 if (!call_used_regs[3])
2315 /* ... that it isn't being used for a return value ... */
2316 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
2319 /* ... or for a tail-call argument ... */
2322 gcc_assert (GET_CODE (sibling) == CALL_INSN);
2324 if (find_regno_fusage (sibling, USE, 3))
2328 /* ... and that there are no call-saved registers in r0-r2
2329 (always true in the default ABI). */
2330 if (saved_int_regs & 0x7)
2334 /* Can't be done if interworking with Thumb, and any registers have been
2336 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
2339 /* On StrongARM, conditional returns are expensive if they aren't
2340 taken and multiple registers have been stacked. */
2341 if (iscond && arm_tune_strongarm)
2343 /* Conditional return when just the LR is stored is a simple
2344 conditional-load instruction, that's not expensive. */
2345 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
2349 && arm_pic_register != INVALID_REGNUM
2350 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
2354 /* If there are saved registers but the LR isn't saved, then we need
2355 two instructions for the return. */
2356 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
2359 /* Can't be done if any of the FPA regs are pushed,
2360 since this also requires an insn. */
2361 if (TARGET_HARD_FLOAT && TARGET_FPA)
2362 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
2363 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
2366 /* Likewise VFP regs. */
2367 if (TARGET_HARD_FLOAT && TARGET_VFP)
2368 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
2369 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
2372 if (TARGET_REALLY_IWMMXT)
2373 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
2374 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2380 /* Return TRUE if int I is a valid immediate ARM constant. */
2383 const_ok_for_arm (HOST_WIDE_INT i)
2387 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
2388 be all zero, or all one. */
2389 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
2390 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
2391 != ((~(unsigned HOST_WIDE_INT) 0)
2392 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
2395 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
2397 /* Fast return for 0 and small values. We must do this for zero, since
2398 the code below can't handle that one case. */
2399 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
2402 /* Get the number of trailing zeros. */
2403 lowbit = ffs((int) i) - 1;
2405 /* Only even shifts are allowed in ARM mode so round down to the
2406 nearest even number. */
2410 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
2415 /* Allow rotated constants in ARM mode. */
2417 && ((i & ~0xc000003f) == 0
2418 || (i & ~0xf000000f) == 0
2419 || (i & ~0xfc000003) == 0))
2426 /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */
2429 if (i == v || i == (v | (v << 8)))
2432 /* Allow repeated pattern 0xXY00XY00. */
2442 /* Return true if I is a valid constant for the operation CODE. */
2444 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
2446 if (const_ok_for_arm (i))
2452 /* See if we can use movw. */
2453 if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
2456 /* Otherwise, try mvn. */
2457 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
2460 /* See if we can use addw or subw. */
2462 && ((i & 0xfffff000) == 0
2463 || ((-i) & 0xfffff000) == 0))
2465 /* else fall through. */
2485 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
2487 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
2493 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
2497 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
2504 /* Emit a sequence of insns to handle a large constant.
2505 CODE is the code of the operation required, it can be any of SET, PLUS,
2506 IOR, AND, XOR, MINUS;
2507 MODE is the mode in which the operation is being performed;
2508 VAL is the integer to operate on;
2509 SOURCE is the other operand (a register, or a null-pointer for SET);
2510 SUBTARGETS means it is safe to create scratch registers if that will
2511 either produce a simpler sequence, or we will want to cse the values.
2512 Return value is the number of insns emitted. */
2514 /* ??? Tweak this for thumb2. */
2516 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
2517 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
2521 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
2522 cond = COND_EXEC_TEST (PATTERN (insn));
2526 if (subtargets || code == SET
2527 || (GET_CODE (target) == REG && GET_CODE (source) == REG
2528 && REGNO (target) != REGNO (source)))
2530 /* After arm_reorg has been called, we can't fix up expensive
2531 constants by pushing them into memory so we must synthesize
2532 them in-line, regardless of the cost. This is only likely to
2533 be more costly on chips that have load delay slots and we are
2534 compiling without running the scheduler (so no splitting
2535 occurred before the final instruction emission).
2537 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
2539 if (!after_arm_reorg
2541 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
2543 > (arm_constant_limit (optimize_function_for_size_p (cfun))
2548 /* Currently SET is the only monadic value for CODE, all
2549 the rest are diadic. */
2550 if (TARGET_USE_MOVT)
2551 arm_emit_movpair (target, GEN_INT (val));
2553 emit_set_insn (target, GEN_INT (val));
2559 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
2561 if (TARGET_USE_MOVT)
2562 arm_emit_movpair (temp, GEN_INT (val));
2564 emit_set_insn (temp, GEN_INT (val));
2566 /* For MINUS, the value is subtracted from, since we never
2567 have subtraction of a constant. */
2569 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
2571 emit_set_insn (target,
2572 gen_rtx_fmt_ee (code, mode, source, temp));
2578 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
2582 /* Return a sequence of integers, in RETURN_SEQUENCE that fit into
2583 ARM/THUMB2 immediates, and add up to VAL.
2584 Thr function return value gives the number of insns required. */
2586 optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
2587 struct four_ints *return_sequence)
2589 int best_consecutive_zeros = 0;
2593 struct four_ints tmp_sequence;
2595 /* If we aren't targetting ARM, the best place to start is always at
2596 the bottom, otherwise look more closely. */
2599 for (i = 0; i < 32; i += 2)
2601 int consecutive_zeros = 0;
2603 if (!(val & (3 << i)))
2605 while ((i < 32) && !(val & (3 << i)))
2607 consecutive_zeros += 2;
2610 if (consecutive_zeros > best_consecutive_zeros)
2612 best_consecutive_zeros = consecutive_zeros;
2613 best_start = i - consecutive_zeros;
2620 /* So long as it won't require any more insns to do so, it's
2621 desirable to emit a small constant (in bits 0...9) in the last
2622 insn. This way there is more chance that it can be combined with
2623 a later addressing insn to form a pre-indexed load or store
2624 operation. Consider:
2626 *((volatile int *)0xe0000100) = 1;
2627 *((volatile int *)0xe0000110) = 2;
2629 We want this to wind up as:
2633 str rB, [rA, #0x100]
2635 str rB, [rA, #0x110]
2637 rather than having to synthesize both large constants from scratch.
2639 Therefore, we calculate how many insns would be required to emit
2640 the constant starting from `best_start', and also starting from
2641 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2642 yield a shorter sequence, we may as well use zero. */
2643 insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
2645 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
2647 insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
2648 if (insns2 <= insns1)
2650 *return_sequence = tmp_sequence;
2658 /* As for optimal_immediate_sequence, but starting at bit-position I. */
2660 optimal_immediate_sequence_1 (enum rtx_code code, unsigned HOST_WIDE_INT val,
2661 struct four_ints *return_sequence, int i)
2663 int remainder = val & 0xffffffff;
2666 /* Try and find a way of doing the job in either two or three
2669 In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
2670 location. We start at position I. This may be the MSB, or
2671 optimial_immediate_sequence may have positioned it at the largest block
2672 of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
2673 wrapping around to the top of the word when we drop off the bottom.
2674 In the worst case this code should produce no more than four insns.
2676 In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
2677 constants, shifted to any arbitrary location. We should always start
2682 unsigned int b1, b2, b3, b4;
2683 unsigned HOST_WIDE_INT result;
2686 gcc_assert (insns < 4);
2691 /* First, find the next normal 12/8-bit shifted/rotated immediate. */
2692 if (remainder & ((TARGET_ARM ? (3 << (i - 2)) : (1 << (i - 1)))))
2695 if (i <= 12 && TARGET_THUMB2 && code == PLUS)
2696 /* We can use addw/subw for the last 12 bits. */
2700 /* Use an 8-bit shifted/rotated immediate. */
2704 result = remainder & ((0x0ff << end)
2705 | ((i < end) ? (0xff >> (32 - end))
2712 /* Arm allows rotates by a multiple of two. Thumb-2 allows
2713 arbitrary shifts. */
2714 i -= TARGET_ARM ? 2 : 1;
2718 /* Next, see if we can do a better job with a thumb2 replicated
2721 We do it this way around to catch the cases like 0x01F001E0 where
2722 two 8-bit immediates would work, but a replicated constant would
2725 TODO: 16-bit constants that don't clear all the bits, but still win.
2726 TODO: Arithmetic splitting for set/add/sub, rather than bitwise. */
2729 b1 = (remainder & 0xff000000) >> 24;
2730 b2 = (remainder & 0x00ff0000) >> 16;
2731 b3 = (remainder & 0x0000ff00) >> 8;
2732 b4 = remainder & 0xff;
2736 /* The 8-bit immediate already found clears b1 (and maybe b2),
2737 but must leave b3 and b4 alone. */
2739 /* First try to find a 32-bit replicated constant that clears
2740 almost everything. We can assume that we can't do it in one,
2741 or else we wouldn't be here. */
2742 unsigned int tmp = b1 & b2 & b3 & b4;
2743 unsigned int tmp2 = tmp + (tmp << 8) + (tmp << 16)
2745 unsigned int matching_bytes = (tmp == b1) + (tmp == b2)
2746 + (tmp == b3) + (tmp == b4);
2748 && (matching_bytes >= 3
2749 || (matching_bytes == 2
2750 && const_ok_for_op (remainder & ~tmp2, code))))
2752 /* At least 3 of the bytes match, and the fourth has at
2753 least as many bits set, or two of the bytes match
2754 and it will only require one more insn to finish. */
2762 /* Second, try to find a 16-bit replicated constant that can
2763 leave three of the bytes clear. If b2 or b4 is already
2764 zero, then we can. If the 8-bit from above would not
2765 clear b2 anyway, then we still win. */
2766 else if (b1 == b3 && (!b2 || !b4
2767 || (remainder & 0x00ff0000 & ~result)))
2769 result = remainder & 0xff00ff00;
2775 /* The 8-bit immediate already found clears b2 (and maybe b3)
2776 and we don't get here unless b1 is alredy clear, but it will
2777 leave b4 unchanged. */
2779 /* If we can clear b2 and b4 at once, then we win, since the
2780 8-bits couldn't possibly reach that far. */
2783 result = remainder & 0x00ff00ff;
2789 return_sequence->i[insns++] = result;
2790 remainder &= ~result;
2792 if (code == SET || code == MINUS)
2800 /* Emit an instruction with the indicated PATTERN. If COND is
2801 non-NULL, conditionalize the execution of the instruction on COND
2805 emit_constant_insn (rtx cond, rtx pattern)
2808 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
2809 emit_insn (pattern);
2812 /* As above, but extra parameter GENERATE which, if clear, suppresses
2816 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
2817 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
2822 int final_invert = 0;
2824 int set_sign_bit_copies = 0;
2825 int clear_sign_bit_copies = 0;
2826 int clear_zero_bit_copies = 0;
2827 int set_zero_bit_copies = 0;
2828 int insns = 0, neg_insns, inv_insns;
2829 unsigned HOST_WIDE_INT temp1, temp2;
2830 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
2831 struct four_ints *immediates;
2832 struct four_ints pos_immediates, neg_immediates, inv_immediates;
2834 /* Find out which operations are safe for a given CODE. Also do a quick
2835 check for degenerate cases; these can occur when DImode operations
2848 if (remainder == 0xffffffff)
2851 emit_constant_insn (cond,
2852 gen_rtx_SET (VOIDmode, target,
2853 GEN_INT (ARM_SIGN_EXTEND (val))));
2859 if (reload_completed && rtx_equal_p (target, source))
2863 emit_constant_insn (cond,
2864 gen_rtx_SET (VOIDmode, target, source));
2873 emit_constant_insn (cond,
2874 gen_rtx_SET (VOIDmode, target, const0_rtx));
2877 if (remainder == 0xffffffff)
2879 if (reload_completed && rtx_equal_p (target, source))
2882 emit_constant_insn (cond,
2883 gen_rtx_SET (VOIDmode, target, source));
2892 if (reload_completed && rtx_equal_p (target, source))
2895 emit_constant_insn (cond,
2896 gen_rtx_SET (VOIDmode, target, source));
2900 if (remainder == 0xffffffff)
2903 emit_constant_insn (cond,
2904 gen_rtx_SET (VOIDmode, target,
2905 gen_rtx_NOT (mode, source)));
2912 /* We treat MINUS as (val - source), since (source - val) is always
2913 passed as (source + (-val)). */
2917 emit_constant_insn (cond,
2918 gen_rtx_SET (VOIDmode, target,
2919 gen_rtx_NEG (mode, source)));
2922 if (const_ok_for_arm (val))
2925 emit_constant_insn (cond,
2926 gen_rtx_SET (VOIDmode, target,
2927 gen_rtx_MINUS (mode, GEN_INT (val),
2938 /* If we can do it in one insn get out quickly. */
2939 if (const_ok_for_op (val, code))
2942 emit_constant_insn (cond,
2943 gen_rtx_SET (VOIDmode, target,
2945 ? gen_rtx_fmt_ee (code, mode, source,
2951 /* Calculate a few attributes that may be useful for specific
2953 /* Count number of leading zeros. */
2954 for (i = 31; i >= 0; i--)
2956 if ((remainder & (1 << i)) == 0)
2957 clear_sign_bit_copies++;
2962 /* Count number of leading 1's. */
2963 for (i = 31; i >= 0; i--)
2965 if ((remainder & (1 << i)) != 0)
2966 set_sign_bit_copies++;
2971 /* Count number of trailing zero's. */
2972 for (i = 0; i <= 31; i++)
2974 if ((remainder & (1 << i)) == 0)
2975 clear_zero_bit_copies++;
2980 /* Count number of trailing 1's. */
2981 for (i = 0; i <= 31; i++)
2983 if ((remainder & (1 << i)) != 0)
2984 set_zero_bit_copies++;
2992 /* See if we can do this by sign_extending a constant that is known
2993 to be negative. This is a good, way of doing it, since the shift
2994 may well merge into a subsequent insn. */
2995 if (set_sign_bit_copies > 1)
2997 if (const_ok_for_arm
2998 (temp1 = ARM_SIGN_EXTEND (remainder
2999 << (set_sign_bit_copies - 1))))
3003 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3004 emit_constant_insn (cond,
3005 gen_rtx_SET (VOIDmode, new_src,
3007 emit_constant_insn (cond,
3008 gen_ashrsi3 (target, new_src,
3009 GEN_INT (set_sign_bit_copies - 1)));
3013 /* For an inverted constant, we will need to set the low bits,
3014 these will be shifted out of harm's way. */
3015 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
3016 if (const_ok_for_arm (~temp1))
3020 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3021 emit_constant_insn (cond,
3022 gen_rtx_SET (VOIDmode, new_src,
3024 emit_constant_insn (cond,
3025 gen_ashrsi3 (target, new_src,
3026 GEN_INT (set_sign_bit_copies - 1)));
3032 /* See if we can calculate the value as the difference between two
3033 valid immediates. */
3034 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
3036 int topshift = clear_sign_bit_copies & ~1;
3038 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
3039 & (0xff000000 >> topshift));
3041 /* If temp1 is zero, then that means the 9 most significant
3042 bits of remainder were 1 and we've caused it to overflow.
3043 When topshift is 0 we don't need to do anything since we
3044 can borrow from 'bit 32'. */
3045 if (temp1 == 0 && topshift != 0)
3046 temp1 = 0x80000000 >> (topshift - 1);
3048 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
3050 if (const_ok_for_arm (temp2))
3054 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3055 emit_constant_insn (cond,
3056 gen_rtx_SET (VOIDmode, new_src,
3058 emit_constant_insn (cond,
3059 gen_addsi3 (target, new_src,
3067 /* See if we can generate this by setting the bottom (or the top)
3068 16 bits, and then shifting these into the other half of the
3069 word. We only look for the simplest cases, to do more would cost
3070 too much. Be careful, however, not to generate this when the
3071 alternative would take fewer insns. */
3072 if (val & 0xffff0000)
3074 temp1 = remainder & 0xffff0000;
3075 temp2 = remainder & 0x0000ffff;
3077 /* Overlaps outside this range are best done using other methods. */
3078 for (i = 9; i < 24; i++)
3080 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
3081 && !const_ok_for_arm (temp2))
3083 rtx new_src = (subtargets
3084 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
3086 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
3087 source, subtargets, generate);
3095 gen_rtx_ASHIFT (mode, source,
3102 /* Don't duplicate cases already considered. */
3103 for (i = 17; i < 24; i++)
3105 if (((temp1 | (temp1 >> i)) == remainder)
3106 && !const_ok_for_arm (temp1))
3108 rtx new_src = (subtargets
3109 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
3111 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
3112 source, subtargets, generate);
3117 gen_rtx_SET (VOIDmode, target,
3120 gen_rtx_LSHIFTRT (mode, source,
3131 /* If we have IOR or XOR, and the constant can be loaded in a
3132 single instruction, and we can find a temporary to put it in,
3133 then this can be done in two instructions instead of 3-4. */
3135 /* TARGET can't be NULL if SUBTARGETS is 0 */
3136 || (reload_completed && !reg_mentioned_p (target, source)))
3138 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
3142 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3144 emit_constant_insn (cond,
3145 gen_rtx_SET (VOIDmode, sub,
3147 emit_constant_insn (cond,
3148 gen_rtx_SET (VOIDmode, target,
3149 gen_rtx_fmt_ee (code, mode,
3160 x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
3161 and the remainder 0s for e.g. 0xfff00000)
3162 x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies)
3164 This can be done in 2 instructions by using shifts with mov or mvn.
3169 mvn r0, r0, lsr #12 */
3170 if (set_sign_bit_copies > 8
3171 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
3175 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3176 rtx shift = GEN_INT (set_sign_bit_copies);
3180 gen_rtx_SET (VOIDmode, sub,
3182 gen_rtx_ASHIFT (mode,
3187 gen_rtx_SET (VOIDmode, target,
3189 gen_rtx_LSHIFTRT (mode, sub,
3196 x = y | constant (which has set_zero_bit_copies number of trailing ones).
3198 x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies).
3200 For eg. r0 = r0 | 0xfff
3205 if (set_zero_bit_copies > 8
3206 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
3210 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3211 rtx shift = GEN_INT (set_zero_bit_copies);
3215 gen_rtx_SET (VOIDmode, sub,
3217 gen_rtx_LSHIFTRT (mode,
3222 gen_rtx_SET (VOIDmode, target,
3224 gen_rtx_ASHIFT (mode, sub,
3230 /* This will never be reached for Thumb2 because orn is a valid
3231 instruction. This is for Thumb1 and the ARM 32 bit cases.
3233 x = y | constant (such that ~constant is a valid constant)
3235 x = ~(~y & ~constant).
3237 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
3241 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3242 emit_constant_insn (cond,
3243 gen_rtx_SET (VOIDmode, sub,
3244 gen_rtx_NOT (mode, source)));
3247 sub = gen_reg_rtx (mode);
3248 emit_constant_insn (cond,
3249 gen_rtx_SET (VOIDmode, sub,
3250 gen_rtx_AND (mode, source,
3252 emit_constant_insn (cond,
3253 gen_rtx_SET (VOIDmode, target,
3254 gen_rtx_NOT (mode, sub)));
3261 /* See if two shifts will do 2 or more insn's worth of work. */
3262 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
3264 HOST_WIDE_INT shift_mask = ((0xffffffff
3265 << (32 - clear_sign_bit_copies))
3268 if ((remainder | shift_mask) != 0xffffffff)
3272 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3273 insns = arm_gen_constant (AND, mode, cond,
3274 remainder | shift_mask,
3275 new_src, source, subtargets, 1);
3280 rtx targ = subtargets ? NULL_RTX : target;
3281 insns = arm_gen_constant (AND, mode, cond,
3282 remainder | shift_mask,
3283 targ, source, subtargets, 0);
3289 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3290 rtx shift = GEN_INT (clear_sign_bit_copies);
3292 emit_insn (gen_ashlsi3 (new_src, source, shift));
3293 emit_insn (gen_lshrsi3 (target, new_src, shift));
3299 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
3301 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
3303 if ((remainder | shift_mask) != 0xffffffff)
3307 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3309 insns = arm_gen_constant (AND, mode, cond,
3310 remainder | shift_mask,
3311 new_src, source, subtargets, 1);
3316 rtx targ = subtargets ? NULL_RTX : target;
3318 insns = arm_gen_constant (AND, mode, cond,
3319 remainder | shift_mask,
3320 targ, source, subtargets, 0);
3326 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3327 rtx shift = GEN_INT (clear_zero_bit_copies);
3329 emit_insn (gen_lshrsi3 (new_src, source, shift));
3330 emit_insn (gen_ashlsi3 (target, new_src, shift));
3342 /* Calculate what the instruction sequences would be if we generated it
3343 normally, negated, or inverted. */
3345 /* AND cannot be split into multiple insns, so invert and use BIC. */
3348 insns = optimal_immediate_sequence (code, remainder, &pos_immediates);
3351 neg_insns = optimal_immediate_sequence (code, (-remainder) & 0xffffffff,
3356 if (can_invert || final_invert)
3357 inv_insns = optimal_immediate_sequence (code, remainder ^ 0xffffffff,
3362 immediates = &pos_immediates;
3364 /* Is the negated immediate sequence more efficient? */
3365 if (neg_insns < insns && neg_insns <= inv_insns)
3368 immediates = &neg_immediates;
3373 /* Is the inverted immediate sequence more efficient?
3374 We must allow for an extra NOT instruction for XOR operations, although
3375 there is some chance that the final 'mvn' will get optimized later. */
3376 if ((inv_insns + 1) < insns || (!final_invert && inv_insns < insns))
3379 immediates = &inv_immediates;
3387 /* Now output the chosen sequence as instructions. */
3390 for (i = 0; i < insns; i++)
3392 rtx new_src, temp1_rtx;
3394 temp1 = immediates->i[i];
3396 if (code == SET || code == MINUS)
3397 new_src = (subtargets ? gen_reg_rtx (mode) : target);
3398 else if ((final_invert || i < (insns - 1)) && subtargets)
3399 new_src = gen_reg_rtx (mode);
3405 else if (can_negate)
3408 temp1 = trunc_int_for_mode (temp1, mode);
3409 temp1_rtx = GEN_INT (temp1);
3413 else if (code == MINUS)
3414 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
3416 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
3418 emit_constant_insn (cond,
3419 gen_rtx_SET (VOIDmode, new_src,
3425 can_negate = can_invert;
3429 else if (code == MINUS)
3437 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
3438 gen_rtx_NOT (mode, source)));
3445 /* Canonicalize a comparison so that we are more likely to recognize it.
3446 This can be done for a few constant compares, where we can make the
3447 immediate value easier to load. */
3450 arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1)
3452 enum machine_mode mode;
3453 unsigned HOST_WIDE_INT i, maxval;
3455 mode = GET_MODE (*op0);
3456 if (mode == VOIDmode)
3457 mode = GET_MODE (*op1);
3459 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
3461 /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode
3462 we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either
3463 reversed or (for constant OP1) adjusted to GE/LT. Similarly
3464 for GTU/LEU in Thumb mode. */
3469 /* To keep things simple, always use the Cirrus cfcmp64 if it is
3471 if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
3474 if (code == GT || code == LE
3475 || (!TARGET_ARM && (code == GTU || code == LEU)))
3477 /* Missing comparison. First try to use an available
3479 if (GET_CODE (*op1) == CONST_INT)
3487 && arm_const_double_by_immediates (GEN_INT (i + 1)))
3489 *op1 = GEN_INT (i + 1);
3490 return code == GT ? GE : LT;
3495 if (i != ~((unsigned HOST_WIDE_INT) 0)
3496 && arm_const_double_by_immediates (GEN_INT (i + 1)))
3498 *op1 = GEN_INT (i + 1);
3499 return code == GTU ? GEU : LTU;
3507 /* If that did not work, reverse the condition. */
3511 return swap_condition (code);
3517 /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing
3518 with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)),
3519 to facilitate possible combining with a cmp into 'ands'. */
3521 && GET_CODE (*op0) == ZERO_EXTEND
3522 && GET_CODE (XEXP (*op0, 0)) == SUBREG
3523 && GET_MODE (XEXP (*op0, 0)) == QImode
3524 && GET_MODE (SUBREG_REG (XEXP (*op0, 0))) == SImode
3525 && subreg_lowpart_p (XEXP (*op0, 0))
3526 && *op1 == const0_rtx)
3527 *op0 = gen_rtx_AND (SImode, SUBREG_REG (XEXP (*op0, 0)),
3530 /* Comparisons smaller than DImode. Only adjust comparisons against
3531 an out-of-range constant. */
3532 if (GET_CODE (*op1) != CONST_INT
3533 || const_ok_for_arm (INTVAL (*op1))
3534 || const_ok_for_arm (- INTVAL (*op1)))
3548 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
3550 *op1 = GEN_INT (i + 1);
3551 return code == GT ? GE : LT;
3558 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
3560 *op1 = GEN_INT (i - 1);
3561 return code == GE ? GT : LE;
3567 if (i != ~((unsigned HOST_WIDE_INT) 0)
3568 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
3570 *op1 = GEN_INT (i + 1);
3571 return code == GTU ? GEU : LTU;
3578 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
3580 *op1 = GEN_INT (i - 1);
3581 return code == GEU ? GTU : LEU;
3593 /* Define how to find the value returned by a function. */
3596 arm_function_value(const_tree type, const_tree func,
3597 bool outgoing ATTRIBUTE_UNUSED)
3599 enum machine_mode mode;
3600 int unsignedp ATTRIBUTE_UNUSED;
3601 rtx r ATTRIBUTE_UNUSED;
3603 mode = TYPE_MODE (type);
3605 if (TARGET_AAPCS_BASED)
3606 return aapcs_allocate_return_reg (mode, type, func);
3608 /* Promote integer types. */
3609 if (INTEGRAL_TYPE_P (type))
3610 mode = arm_promote_function_mode (type, mode, &unsignedp, func, 1);
3612 /* Promotes small structs returned in a register to full-word size
3613 for big-endian AAPCS. */
3614 if (arm_return_in_msb (type))
3616 HOST_WIDE_INT size = int_size_in_bytes (type);
3617 if (size % UNITS_PER_WORD != 0)
3619 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
3620 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
3624 return arm_libcall_value_1 (mode);
3628 libcall_eq (const void *p1, const void *p2)
3630 return rtx_equal_p ((const_rtx) p1, (const_rtx) p2);
3634 libcall_hash (const void *p1)
3636 return hash_rtx ((const_rtx) p1, VOIDmode, NULL, NULL, FALSE);
3640 add_libcall (htab_t htab, rtx libcall)
3642 *htab_find_slot (htab, libcall, INSERT) = libcall;
3646 arm_libcall_uses_aapcs_base (const_rtx libcall)
3648 static bool init_done = false;
3649 static htab_t libcall_htab;
3655 libcall_htab = htab_create (31, libcall_hash, libcall_eq,
3657 add_libcall (libcall_htab,
3658 convert_optab_libfunc (sfloat_optab, SFmode, SImode));
3659 add_libcall (libcall_htab,
3660 convert_optab_libfunc (sfloat_optab, DFmode, SImode));
3661 add_libcall (libcall_htab,
3662 convert_optab_libfunc (sfloat_optab, SFmode, DImode));
3663 add_libcall (libcall_htab,
3664 convert_optab_libfunc (sfloat_optab, DFmode, DImode));
3666 add_libcall (libcall_htab,
3667 convert_optab_libfunc (ufloat_optab, SFmode, SImode));
3668 add_libcall (libcall_htab,
3669 convert_optab_libfunc (ufloat_optab, DFmode, SImode));
3670 add_libcall (libcall_htab,
3671 convert_optab_libfunc (ufloat_optab, SFmode, DImode));
3672 add_libcall (libcall_htab,
3673 convert_optab_libfunc (ufloat_optab, DFmode, DImode));
3675 add_libcall (libcall_htab,
3676 convert_optab_libfunc (sext_optab, SFmode, HFmode));
3677 add_libcall (libcall_htab,
3678 convert_optab_libfunc (trunc_optab, HFmode, SFmode));
3679 add_libcall (libcall_htab,
3680 convert_optab_libfunc (sfix_optab, SImode, DFmode));
3681 add_libcall (libcall_htab,
3682 convert_optab_libfunc (ufix_optab, SImode, DFmode));
3683 add_libcall (libcall_htab,
3684 convert_optab_libfunc (sfix_optab, DImode, DFmode));
3685 add_libcall (libcall_htab,
3686 convert_optab_libfunc (ufix_optab, DImode, DFmode));
3687 add_libcall (libcall_htab,
3688 convert_optab_libfunc (sfix_optab, DImode, SFmode));
3689 add_libcall (libcall_htab,
3690 convert_optab_libfunc (ufix_optab, DImode, SFmode));
3692 /* Values from double-precision helper functions are returned in core
3693 registers if the selected core only supports single-precision
3694 arithmetic, even if we are using the hard-float ABI. The same is
3695 true for single-precision helpers, but we will never be using the
3696 hard-float ABI on a CPU which doesn't support single-precision
3697 operations in hardware. */
3698 add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode));
3699 add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode));
3700 add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode));
3701 add_libcall (libcall_htab, optab_libfunc (neg_optab, DFmode));
3702 add_libcall (libcall_htab, optab_libfunc (sub_optab, DFmode));
3703 add_libcall (libcall_htab, optab_libfunc (eq_optab, DFmode));
3704 add_libcall (libcall_htab, optab_libfunc (lt_optab, DFmode));
3705 add_libcall (libcall_htab, optab_libfunc (le_optab, DFmode));
3706 add_libcall (libcall_htab, optab_libfunc (ge_optab, DFmode));
3707 add_libcall (libcall_htab, optab_libfunc (gt_optab, DFmode));
3708 add_libcall (libcall_htab, optab_libfunc (unord_optab, DFmode));
3709 add_libcall (libcall_htab, convert_optab_libfunc (sext_optab, DFmode,
3711 add_libcall (libcall_htab, convert_optab_libfunc (trunc_optab, SFmode,
3715 return libcall && htab_find (libcall_htab, libcall) != NULL;
3719 arm_libcall_value_1 (enum machine_mode mode)
3721 if (TARGET_AAPCS_BASED)
3722 return aapcs_libcall_value (mode);
3723 else if (TARGET_32BIT
3724 && TARGET_HARD_FLOAT_ABI
3726 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3727 return gen_rtx_REG (mode, FIRST_FPA_REGNUM);
3728 else if (TARGET_32BIT
3729 && TARGET_HARD_FLOAT_ABI
3731 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3732 return gen_rtx_REG (mode, FIRST_CIRRUS_FP_REGNUM);
3733 else if (TARGET_IWMMXT_ABI
3734 && arm_vector_mode_supported_p (mode))
3735 return gen_rtx_REG (mode, FIRST_IWMMXT_REGNUM);
3737 return gen_rtx_REG (mode, ARG_REGISTER (1));
3740 /* Define how to find the value returned by a library function
3741 assuming the value has mode MODE. */
3744 arm_libcall_value (enum machine_mode mode, const_rtx libcall)
3746 if (TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS
3747 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3749 /* The following libcalls return their result in integer registers,
3750 even though they return a floating point value. */
3751 if (arm_libcall_uses_aapcs_base (libcall))
3752 return gen_rtx_REG (mode, ARG_REGISTER(1));
3756 return arm_libcall_value_1 (mode);
3759 /* Implement TARGET_FUNCTION_VALUE_REGNO_P. */
3762 arm_function_value_regno_p (const unsigned int regno)
3764 if (regno == ARG_REGISTER (1)
3766 && TARGET_AAPCS_BASED
3768 && TARGET_HARD_FLOAT
3769 && regno == FIRST_VFP_REGNUM)
3771 && TARGET_HARD_FLOAT_ABI
3773 && regno == FIRST_CIRRUS_FP_REGNUM)
3774 || (TARGET_IWMMXT_ABI
3775 && regno == FIRST_IWMMXT_REGNUM)
3777 && TARGET_HARD_FLOAT_ABI
3779 && regno == FIRST_FPA_REGNUM))
3785 /* Determine the amount of memory needed to store the possible return
3786 registers of an untyped call. */
3788 arm_apply_result_size (void)
3794 if (TARGET_HARD_FLOAT_ABI)
3800 if (TARGET_MAVERICK)
3803 if (TARGET_IWMMXT_ABI)
3810 /* Decide whether TYPE should be returned in memory (true)
3811 or in a register (false). FNTYPE is the type of the function making
3814 arm_return_in_memory (const_tree type, const_tree fntype)
3818 size = int_size_in_bytes (type); /* Negative if not fixed size. */
3820 if (TARGET_AAPCS_BASED)
3822 /* Simple, non-aggregate types (ie not including vectors and
3823 complex) are always returned in a register (or registers).
3824 We don't care about which register here, so we can short-cut
3825 some of the detail. */
3826 if (!AGGREGATE_TYPE_P (type)
3827 && TREE_CODE (type) != VECTOR_TYPE
3828 && TREE_CODE (type) != COMPLEX_TYPE)
3831 /* Any return value that is no larger than one word can be
3833 if (((unsigned HOST_WIDE_INT) size) <= UNITS_PER_WORD)
3836 /* Check any available co-processors to see if they accept the
3837 type as a register candidate (VFP, for example, can return
3838 some aggregates in consecutive registers). These aren't
3839 available if the call is variadic. */
3840 if (aapcs_select_return_coproc (type, fntype) >= 0)
3843 /* Vector values should be returned using ARM registers, not
3844 memory (unless they're over 16 bytes, which will break since
3845 we only have four call-clobbered registers to play with). */
3846 if (TREE_CODE (type) == VECTOR_TYPE)
3847 return (size < 0 || size > (4 * UNITS_PER_WORD));
3849 /* The rest go in memory. */
3853 if (TREE_CODE (type) == VECTOR_TYPE)
3854 return (size < 0 || size > (4 * UNITS_PER_WORD));
3856 if (!AGGREGATE_TYPE_P (type) &&
3857 (TREE_CODE (type) != VECTOR_TYPE))
3858 /* All simple types are returned in registers. */
3861 if (arm_abi != ARM_ABI_APCS)
3863 /* ATPCS and later return aggregate types in memory only if they are
3864 larger than a word (or are variable size). */
3865 return (size < 0 || size > UNITS_PER_WORD);
3868 /* For the arm-wince targets we choose to be compatible with Microsoft's
3869 ARM and Thumb compilers, which always return aggregates in memory. */
3871 /* All structures/unions bigger than one word are returned in memory.
3872 Also catch the case where int_size_in_bytes returns -1. In this case
3873 the aggregate is either huge or of variable size, and in either case
3874 we will want to return it via memory and not in a register. */
3875 if (size < 0 || size > UNITS_PER_WORD)
3878 if (TREE_CODE (type) == RECORD_TYPE)
3882 /* For a struct the APCS says that we only return in a register
3883 if the type is 'integer like' and every addressable element
3884 has an offset of zero. For practical purposes this means
3885 that the structure can have at most one non bit-field element
3886 and that this element must be the first one in the structure. */
3888 /* Find the first field, ignoring non FIELD_DECL things which will
3889 have been created by C++. */
3890 for (field = TYPE_FIELDS (type);
3891 field && TREE_CODE (field) != FIELD_DECL;
3892 field = DECL_CHAIN (field))
3896 return false; /* An empty structure. Allowed by an extension to ANSI C. */
3898 /* Check that the first field is valid for returning in a register. */
3900 /* ... Floats are not allowed */
3901 if (FLOAT_TYPE_P (TREE_TYPE (field)))
3904 /* ... Aggregates that are not themselves valid for returning in
3905 a register are not allowed. */
3906 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
3909 /* Now check the remaining fields, if any. Only bitfields are allowed,
3910 since they are not addressable. */
3911 for (field = DECL_CHAIN (field);
3913 field = DECL_CHAIN (field))
3915 if (TREE_CODE (field) != FIELD_DECL)
3918 if (!DECL_BIT_FIELD_TYPE (field))
3925 if (TREE_CODE (type) == UNION_TYPE)
3929 /* Unions can be returned in registers if every element is
3930 integral, or can be returned in an integer register. */
3931 for (field = TYPE_FIELDS (type);
3933 field = DECL_CHAIN (field))
3935 if (TREE_CODE (field) != FIELD_DECL)
3938 if (FLOAT_TYPE_P (TREE_TYPE (field)))
3941 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
3947 #endif /* not ARM_WINCE */
3949 /* Return all other types in memory. */
3953 /* Indicate whether or not words of a double are in big-endian order. */
3956 arm_float_words_big_endian (void)
3958 if (TARGET_MAVERICK)
3961 /* For FPA, float words are always big-endian. For VFP, floats words
3962 follow the memory system mode. */
3970 return (TARGET_BIG_END ? 1 : 0);
3975 const struct pcs_attribute_arg
3979 } pcs_attribute_args[] =
3981 {"aapcs", ARM_PCS_AAPCS},
3982 {"aapcs-vfp", ARM_PCS_AAPCS_VFP},
3984 /* We could recognize these, but changes would be needed elsewhere
3985 * to implement them. */
3986 {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT},
3987 {"atpcs", ARM_PCS_ATPCS},
3988 {"apcs", ARM_PCS_APCS},
3990 {NULL, ARM_PCS_UNKNOWN}
3994 arm_pcs_from_attribute (tree attr)
3996 const struct pcs_attribute_arg *ptr;
3999 /* Get the value of the argument. */
4000 if (TREE_VALUE (attr) == NULL_TREE
4001 || TREE_CODE (TREE_VALUE (attr)) != STRING_CST)
4002 return ARM_PCS_UNKNOWN;
4004 arg = TREE_STRING_POINTER (TREE_VALUE (attr));
4006 /* Check it against the list of known arguments. */
4007 for (ptr = pcs_attribute_args; ptr->arg != NULL; ptr++)
4008 if (streq (arg, ptr->arg))
4011 /* An unrecognized interrupt type. */
4012 return ARM_PCS_UNKNOWN;
4015 /* Get the PCS variant to use for this call. TYPE is the function's type
4016 specification, DECL is the specific declartion. DECL may be null if
4017 the call could be indirect or if this is a library call. */
4019 arm_get_pcs_model (const_tree type, const_tree decl)
4021 bool user_convention = false;
4022 enum arm_pcs user_pcs = arm_pcs_default;
4027 attr = lookup_attribute ("pcs", TYPE_ATTRIBUTES (type));
4030 user_pcs = arm_pcs_from_attribute (TREE_VALUE (attr));
4031 user_convention = true;
4034 if (TARGET_AAPCS_BASED)
4036 /* Detect varargs functions. These always use the base rules
4037 (no argument is ever a candidate for a co-processor
4039 bool base_rules = stdarg_p (type);
4041 if (user_convention)
4043 if (user_pcs > ARM_PCS_AAPCS_LOCAL)
4044 sorry ("non-AAPCS derived PCS variant");
4045 else if (base_rules && user_pcs != ARM_PCS_AAPCS)
4046 error ("variadic functions must use the base AAPCS variant");
4050 return ARM_PCS_AAPCS;
4051 else if (user_convention)
4053 else if (decl && flag_unit_at_a_time)
4055 /* Local functions never leak outside this compilation unit,
4056 so we are free to use whatever conventions are
4058 /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */
4059 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4061 return ARM_PCS_AAPCS_LOCAL;
4064 else if (user_convention && user_pcs != arm_pcs_default)
4065 sorry ("PCS variant");
4067 /* For everything else we use the target's default. */
4068 return arm_pcs_default;
4073 aapcs_vfp_cum_init (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED,
4074 const_tree fntype ATTRIBUTE_UNUSED,
4075 rtx libcall ATTRIBUTE_UNUSED,
4076 const_tree fndecl ATTRIBUTE_UNUSED)
4078 /* Record the unallocated VFP registers. */
4079 pcum->aapcs_vfp_regs_free = (1 << NUM_VFP_ARG_REGS) - 1;
4080 pcum->aapcs_vfp_reg_alloc = 0;
4083 /* Walk down the type tree of TYPE counting consecutive base elements.
4084 If *MODEP is VOIDmode, then set it to the first valid floating point
4085 type. If a non-floating point type is found, or if a floating point
4086 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
4087 otherwise return the count in the sub-tree. */
4089 aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep)
4091 enum machine_mode mode;
4094 switch (TREE_CODE (type))
4097 mode = TYPE_MODE (type);
4098 if (mode != DFmode && mode != SFmode)
4101 if (*modep == VOIDmode)
4110 mode = TYPE_MODE (TREE_TYPE (type));
4111 if (mode != DFmode && mode != SFmode)
4114 if (*modep == VOIDmode)
4123 /* Use V2SImode and V4SImode as representatives of all 64-bit
4124 and 128-bit vector types, whether or not those modes are
4125 supported with the present options. */
4126 size = int_size_in_bytes (type);
4139 if (*modep == VOIDmode)
4142 /* Vector modes are considered to be opaque: two vectors are
4143 equivalent for the purposes of being homogeneous aggregates
4144 if they are the same size. */
4153 tree index = TYPE_DOMAIN (type);
4155 /* Can't handle incomplete types. */
4156 if (!COMPLETE_TYPE_P(type))
4159 count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep);
4162 || !TYPE_MAX_VALUE (index)
4163 || !host_integerp (TYPE_MAX_VALUE (index), 1)
4164 || !TYPE_MIN_VALUE (index)
4165 || !host_integerp (TYPE_MIN_VALUE (index), 1)
4169 count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1)
4170 - tree_low_cst (TYPE_MIN_VALUE (index), 1));
4172 /* There must be no padding. */
4173 if (!host_integerp (TYPE_SIZE (type), 1)
4174 || (tree_low_cst (TYPE_SIZE (type), 1)
4175 != count * GET_MODE_BITSIZE (*modep)))
4187 /* Can't handle incomplete types. */
4188 if (!COMPLETE_TYPE_P(type))
4191 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4193 if (TREE_CODE (field) != FIELD_DECL)
4196 sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep);
4202 /* There must be no padding. */
4203 if (!host_integerp (TYPE_SIZE (type), 1)
4204 || (tree_low_cst (TYPE_SIZE (type), 1)
4205 != count * GET_MODE_BITSIZE (*modep)))
4212 case QUAL_UNION_TYPE:
4214 /* These aren't very interesting except in a degenerate case. */
4219 /* Can't handle incomplete types. */
4220 if (!COMPLETE_TYPE_P(type))
4223 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4225 if (TREE_CODE (field) != FIELD_DECL)
4228 sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep);
4231 count = count > sub_count ? count : sub_count;
4234 /* There must be no padding. */
4235 if (!host_integerp (TYPE_SIZE (type), 1)
4236 || (tree_low_cst (TYPE_SIZE (type), 1)
4237 != count * GET_MODE_BITSIZE (*modep)))
4250 /* Return true if PCS_VARIANT should use VFP registers. */
4252 use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
4254 if (pcs_variant == ARM_PCS_AAPCS_VFP)
4256 static bool seen_thumb1_vfp = false;
4258 if (TARGET_THUMB1 && !seen_thumb1_vfp)
4260 sorry ("Thumb-1 hard-float VFP ABI");
4261 /* sorry() is not immediately fatal, so only display this once. */
4262 seen_thumb1_vfp = true;
4268 if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
4271 return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT &&
4272 (TARGET_VFP_DOUBLE || !is_double));
4275 /* Return true if an argument whose type is TYPE, or mode is MODE, is
4276 suitable for passing or returning in VFP registers for the PCS
4277 variant selected. If it is, then *BASE_MODE is updated to contain
4278 a machine mode describing each element of the argument's type and
4279 *COUNT to hold the number of such elements. */
4281 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant,
4282 enum machine_mode mode, const_tree type,
4283 enum machine_mode *base_mode, int *count)
4285 enum machine_mode new_mode = VOIDmode;
4287 /* If we have the type information, prefer that to working things
4288 out from the mode. */
4291 int ag_count = aapcs_vfp_sub_candidate (type, &new_mode);
4293 if (ag_count > 0 && ag_count <= 4)
4298 else if (GET_MODE_CLASS (mode) == MODE_FLOAT
4299 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
4300 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4305 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4308 new_mode = (mode == DCmode ? DFmode : SFmode);
4314 if (!use_vfp_abi (pcs_variant, ARM_NUM_REGS (new_mode) > 1))
4317 *base_mode = new_mode;
4322 aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant,
4323 enum machine_mode mode, const_tree type)
4325 int count ATTRIBUTE_UNUSED;
4326 enum machine_mode ag_mode ATTRIBUTE_UNUSED;
4328 if (!use_vfp_abi (pcs_variant, false))
4330 return aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type,
4335 aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4338 if (!use_vfp_abi (pcum->pcs_variant, false))
4341 return aapcs_vfp_is_call_or_return_candidate (pcum->pcs_variant, mode, type,
4342 &pcum->aapcs_vfp_rmode,
4343 &pcum->aapcs_vfp_rcount);
4347 aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4348 const_tree type ATTRIBUTE_UNUSED)
4350 int shift = GET_MODE_SIZE (pcum->aapcs_vfp_rmode) / GET_MODE_SIZE (SFmode);
4351 unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1;
4354 for (regno = 0; regno < NUM_VFP_ARG_REGS; regno += shift)
4355 if (((pcum->aapcs_vfp_regs_free >> regno) & mask) == mask)
4357 pcum->aapcs_vfp_reg_alloc = mask << regno;
4358 if (mode == BLKmode || (mode == TImode && !TARGET_NEON))
4361 int rcount = pcum->aapcs_vfp_rcount;
4363 enum machine_mode rmode = pcum->aapcs_vfp_rmode;
4367 /* Avoid using unsupported vector modes. */
4368 if (rmode == V2SImode)
4370 else if (rmode == V4SImode)
4377 par = gen_rtx_PARALLEL (mode, rtvec_alloc (rcount));
4378 for (i = 0; i < rcount; i++)
4380 rtx tmp = gen_rtx_REG (rmode,
4381 FIRST_VFP_REGNUM + regno + i * rshift);
4382 tmp = gen_rtx_EXPR_LIST
4384 GEN_INT (i * GET_MODE_SIZE (rmode)));
4385 XVECEXP (par, 0, i) = tmp;
4388 pcum->aapcs_reg = par;
4391 pcum->aapcs_reg = gen_rtx_REG (mode, FIRST_VFP_REGNUM + regno);
4398 aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
4399 enum machine_mode mode,
4400 const_tree type ATTRIBUTE_UNUSED)
4402 if (!use_vfp_abi (pcs_variant, false))
4405 if (mode == BLKmode || (mode == TImode && !TARGET_NEON))
4408 enum machine_mode ag_mode;
4413 aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type,
4418 if (ag_mode == V2SImode)
4420 else if (ag_mode == V4SImode)
4426 shift = GET_MODE_SIZE(ag_mode) / GET_MODE_SIZE(SFmode);
4427 par = gen_rtx_PARALLEL (mode, rtvec_alloc (count));
4428 for (i = 0; i < count; i++)
4430 rtx tmp = gen_rtx_REG (ag_mode, FIRST_VFP_REGNUM + i * shift);
4431 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp,
4432 GEN_INT (i * GET_MODE_SIZE (ag_mode)));
4433 XVECEXP (par, 0, i) = tmp;
4439 return gen_rtx_REG (mode, FIRST_VFP_REGNUM);
4443 aapcs_vfp_advance (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED,
4444 enum machine_mode mode ATTRIBUTE_UNUSED,
4445 const_tree type ATTRIBUTE_UNUSED)
4447 pcum->aapcs_vfp_regs_free &= ~pcum->aapcs_vfp_reg_alloc;
4448 pcum->aapcs_vfp_reg_alloc = 0;
4452 #define AAPCS_CP(X) \
4454 aapcs_ ## X ## _cum_init, \
4455 aapcs_ ## X ## _is_call_candidate, \
4456 aapcs_ ## X ## _allocate, \
4457 aapcs_ ## X ## _is_return_candidate, \
4458 aapcs_ ## X ## _allocate_return_reg, \
4459 aapcs_ ## X ## _advance \
4462 /* Table of co-processors that can be used to pass arguments in
4463 registers. Idealy no arugment should be a candidate for more than
4464 one co-processor table entry, but the table is processed in order
4465 and stops after the first match. If that entry then fails to put
4466 the argument into a co-processor register, the argument will go on
4470 /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */
4471 void (*cum_init) (CUMULATIVE_ARGS *, const_tree, rtx, const_tree);
4473 /* Return true if an argument of mode MODE (or type TYPE if MODE is
4474 BLKmode) is a candidate for this co-processor's registers; this
4475 function should ignore any position-dependent state in
4476 CUMULATIVE_ARGS and only use call-type dependent information. */
4477 bool (*is_call_candidate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
4479 /* Return true if the argument does get a co-processor register; it
4480 should set aapcs_reg to an RTX of the register allocated as is
4481 required for a return from FUNCTION_ARG. */
4482 bool (*allocate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
4484 /* Return true if a result of mode MODE (or type TYPE if MODE is
4485 BLKmode) is can be returned in this co-processor's registers. */
4486 bool (*is_return_candidate) (enum arm_pcs, enum machine_mode, const_tree);
4488 /* Allocate and return an RTX element to hold the return type of a
4489 call, this routine must not fail and will only be called if
4490 is_return_candidate returned true with the same parameters. */
4491 rtx (*allocate_return_reg) (enum arm_pcs, enum machine_mode, const_tree);
4493 /* Finish processing this argument and prepare to start processing
4495 void (*advance) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
4496 } aapcs_cp_arg_layout[ARM_NUM_COPROC_SLOTS] =
4504 aapcs_select_call_coproc (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4509 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4510 if (aapcs_cp_arg_layout[i].is_call_candidate (pcum, mode, type))
4517 aapcs_select_return_coproc (const_tree type, const_tree fntype)
4519 /* We aren't passed a decl, so we can't check that a call is local.
4520 However, it isn't clear that that would be a win anyway, since it
4521 might limit some tail-calling opportunities. */
4522 enum arm_pcs pcs_variant;
4526 const_tree fndecl = NULL_TREE;
4528 if (TREE_CODE (fntype) == FUNCTION_DECL)
4531 fntype = TREE_TYPE (fntype);
4534 pcs_variant = arm_get_pcs_model (fntype, fndecl);
4537 pcs_variant = arm_pcs_default;
4539 if (pcs_variant != ARM_PCS_AAPCS)
4543 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4544 if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant,
4553 aapcs_allocate_return_reg (enum machine_mode mode, const_tree type,
4556 /* We aren't passed a decl, so we can't check that a call is local.
4557 However, it isn't clear that that would be a win anyway, since it
4558 might limit some tail-calling opportunities. */
4559 enum arm_pcs pcs_variant;
4560 int unsignedp ATTRIBUTE_UNUSED;
4564 const_tree fndecl = NULL_TREE;
4566 if (TREE_CODE (fntype) == FUNCTION_DECL)
4569 fntype = TREE_TYPE (fntype);
4572 pcs_variant = arm_get_pcs_model (fntype, fndecl);
4575 pcs_variant = arm_pcs_default;
4577 /* Promote integer types. */
4578 if (type && INTEGRAL_TYPE_P (type))
4579 mode = arm_promote_function_mode (type, mode, &unsignedp, fntype, 1);
4581 if (pcs_variant != ARM_PCS_AAPCS)
4585 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4586 if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant, mode,
4588 return aapcs_cp_arg_layout[i].allocate_return_reg (pcs_variant,
4592 /* Promotes small structs returned in a register to full-word size
4593 for big-endian AAPCS. */
4594 if (type && arm_return_in_msb (type))
4596 HOST_WIDE_INT size = int_size_in_bytes (type);
4597 if (size % UNITS_PER_WORD != 0)
4599 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4600 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4604 return gen_rtx_REG (mode, R0_REGNUM);
4608 aapcs_libcall_value (enum machine_mode mode)
4610 if (BYTES_BIG_ENDIAN && ALL_FIXED_POINT_MODE_P (mode)
4611 && GET_MODE_SIZE (mode) <= 4)
4614 return aapcs_allocate_return_reg (mode, NULL_TREE, NULL_TREE);
4617 /* Lay out a function argument using the AAPCS rules. The rule
4618 numbers referred to here are those in the AAPCS. */
4620 aapcs_layout_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4621 const_tree type, bool named)
4626 /* We only need to do this once per argument. */
4627 if (pcum->aapcs_arg_processed)
4630 pcum->aapcs_arg_processed = true;
4632 /* Special case: if named is false then we are handling an incoming
4633 anonymous argument which is on the stack. */
4637 /* Is this a potential co-processor register candidate? */
4638 if (pcum->pcs_variant != ARM_PCS_AAPCS)
4640 int slot = aapcs_select_call_coproc (pcum, mode, type);
4641 pcum->aapcs_cprc_slot = slot;
4643 /* We don't have to apply any of the rules from part B of the
4644 preparation phase, these are handled elsewhere in the
4649 /* A Co-processor register candidate goes either in its own
4650 class of registers or on the stack. */
4651 if (!pcum->aapcs_cprc_failed[slot])
4653 /* C1.cp - Try to allocate the argument to co-processor
4655 if (aapcs_cp_arg_layout[slot].allocate (pcum, mode, type))
4658 /* C2.cp - Put the argument on the stack and note that we
4659 can't assign any more candidates in this slot. We also
4660 need to note that we have allocated stack space, so that
4661 we won't later try to split a non-cprc candidate between
4662 core registers and the stack. */
4663 pcum->aapcs_cprc_failed[slot] = true;
4664 pcum->can_split = false;
4667 /* We didn't get a register, so this argument goes on the
4669 gcc_assert (pcum->can_split == false);
4674 /* C3 - For double-word aligned arguments, round the NCRN up to the
4675 next even number. */
4676 ncrn = pcum->aapcs_ncrn;
4677 if ((ncrn & 1) && arm_needs_doubleword_align (mode, type))
4680 nregs = ARM_NUM_REGS2(mode, type);
4682 /* Sigh, this test should really assert that nregs > 0, but a GCC
4683 extension allows empty structs and then gives them empty size; it
4684 then allows such a structure to be passed by value. For some of
4685 the code below we have to pretend that such an argument has
4686 non-zero size so that we 'locate' it correctly either in
4687 registers or on the stack. */
4688 gcc_assert (nregs >= 0);
4690 nregs2 = nregs ? nregs : 1;
4692 /* C4 - Argument fits entirely in core registers. */
4693 if (ncrn + nregs2 <= NUM_ARG_REGS)
4695 pcum->aapcs_reg = gen_rtx_REG (mode, ncrn);
4696 pcum->aapcs_next_ncrn = ncrn + nregs;
4700 /* C5 - Some core registers left and there are no arguments already
4701 on the stack: split this argument between the remaining core
4702 registers and the stack. */
4703 if (ncrn < NUM_ARG_REGS && pcum->can_split)
4705 pcum->aapcs_reg = gen_rtx_REG (mode, ncrn);
4706 pcum->aapcs_next_ncrn = NUM_ARG_REGS;
4707 pcum->aapcs_partial = (NUM_ARG_REGS - ncrn) * UNITS_PER_WORD;
4711 /* C6 - NCRN is set to 4. */
4712 pcum->aapcs_next_ncrn = NUM_ARG_REGS;
4714 /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
4718 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4719 for a call to a function whose data type is FNTYPE.
4720 For a library call, FNTYPE is NULL. */
4722 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
4724 tree fndecl ATTRIBUTE_UNUSED)
4726 /* Long call handling. */
4728 pcum->pcs_variant = arm_get_pcs_model (fntype, fndecl);
4730 pcum->pcs_variant = arm_pcs_default;
4732 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4734 if (arm_libcall_uses_aapcs_base (libname))
4735 pcum->pcs_variant = ARM_PCS_AAPCS;
4737 pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0;
4738 pcum->aapcs_reg = NULL_RTX;
4739 pcum->aapcs_partial = 0;
4740 pcum->aapcs_arg_processed = false;
4741 pcum->aapcs_cprc_slot = -1;
4742 pcum->can_split = true;
4744 if (pcum->pcs_variant != ARM_PCS_AAPCS)
4748 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4750 pcum->aapcs_cprc_failed[i] = false;
4751 aapcs_cp_arg_layout[i].cum_init (pcum, fntype, libname, fndecl);
4759 /* On the ARM, the offset starts at 0. */
4761 pcum->iwmmxt_nregs = 0;
4762 pcum->can_split = true;
4764 /* Varargs vectors are treated the same as long long.
4765 named_count avoids having to change the way arm handles 'named' */
4766 pcum->named_count = 0;
4769 if (TARGET_REALLY_IWMMXT && fntype)
4773 for (fn_arg = TYPE_ARG_TYPES (fntype);
4775 fn_arg = TREE_CHAIN (fn_arg))
4776 pcum->named_count += 1;
4778 if (! pcum->named_count)
4779 pcum->named_count = INT_MAX;
4784 /* Return true if mode/type need doubleword alignment. */
4786 arm_needs_doubleword_align (enum machine_mode mode, const_tree type)
4788 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
4789 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
4793 /* Determine where to put an argument to a function.
4794 Value is zero to push the argument on the stack,
4795 or a hard register in which to store the argument.
4797 MODE is the argument's machine mode.
4798 TYPE is the data type of the argument (as a tree).
4799 This is null for libcalls where that information may
4801 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4802 the preceding args and about the function being called.
4803 NAMED is nonzero if this argument is a named parameter
4804 (otherwise it is an extra parameter matching an ellipsis).
4806 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
4807 other arguments are passed on the stack. If (NAMED == 0) (which happens
4808 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
4809 defined), say it is passed in the stack (function_prologue will
4810 indeed make it pass in the stack if necessary). */
4813 arm_function_arg (cumulative_args_t pcum_v, enum machine_mode mode,
4814 const_tree type, bool named)
4816 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
4819 /* Handle the special case quickly. Pick an arbitrary value for op2 of
4820 a call insn (op3 of a call_value insn). */
4821 if (mode == VOIDmode)
4824 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4826 aapcs_layout_arg (pcum, mode, type, named);
4827 return pcum->aapcs_reg;
4830 /* Varargs vectors are treated the same as long long.
4831 named_count avoids having to change the way arm handles 'named' */
4832 if (TARGET_IWMMXT_ABI
4833 && arm_vector_mode_supported_p (mode)
4834 && pcum->named_count > pcum->nargs + 1)
4836 if (pcum->iwmmxt_nregs <= 9)
4837 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
4840 pcum->can_split = false;
4845 /* Put doubleword aligned quantities in even register pairs. */
4847 && ARM_DOUBLEWORD_ALIGN
4848 && arm_needs_doubleword_align (mode, type))
4851 /* Only allow splitting an arg between regs and memory if all preceding
4852 args were allocated to regs. For args passed by reference we only count
4853 the reference pointer. */
4854 if (pcum->can_split)
4857 nregs = ARM_NUM_REGS2 (mode, type);
4859 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
4862 return gen_rtx_REG (mode, pcum->nregs);
4866 arm_function_arg_boundary (enum machine_mode mode, const_tree type)
4868 return (ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (mode, type)
4869 ? DOUBLEWORD_ALIGNMENT
4874 arm_arg_partial_bytes (cumulative_args_t pcum_v, enum machine_mode mode,
4875 tree type, bool named)
4877 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
4878 int nregs = pcum->nregs;
4880 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4882 aapcs_layout_arg (pcum, mode, type, named);
4883 return pcum->aapcs_partial;
4886 if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode))
4889 if (NUM_ARG_REGS > nregs
4890 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
4892 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
4897 /* Update the data in PCUM to advance over an argument
4898 of mode MODE and data type TYPE.
4899 (TYPE is null for libcalls where that information may not be available.) */
4902 arm_function_arg_advance (cumulative_args_t pcum_v, enum machine_mode mode,
4903 const_tree type, bool named)
4905 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
4907 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4909 aapcs_layout_arg (pcum, mode, type, named);
4911 if (pcum->aapcs_cprc_slot >= 0)
4913 aapcs_cp_arg_layout[pcum->aapcs_cprc_slot].advance (pcum, mode,
4915 pcum->aapcs_cprc_slot = -1;
4918 /* Generic stuff. */
4919 pcum->aapcs_arg_processed = false;
4920 pcum->aapcs_ncrn = pcum->aapcs_next_ncrn;
4921 pcum->aapcs_reg = NULL_RTX;
4922 pcum->aapcs_partial = 0;
4927 if (arm_vector_mode_supported_p (mode)
4928 && pcum->named_count > pcum->nargs
4929 && TARGET_IWMMXT_ABI)
4930 pcum->iwmmxt_nregs += 1;
4932 pcum->nregs += ARM_NUM_REGS2 (mode, type);
4936 /* Variable sized types are passed by reference. This is a GCC
4937 extension to the ARM ABI. */
4940 arm_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
4941 enum machine_mode mode ATTRIBUTE_UNUSED,
4942 const_tree type, bool named ATTRIBUTE_UNUSED)
4944 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
4947 /* Encode the current state of the #pragma [no_]long_calls. */
4950 OFF, /* No #pragma [no_]long_calls is in effect. */
4951 LONG, /* #pragma long_calls is in effect. */
4952 SHORT /* #pragma no_long_calls is in effect. */
4955 static arm_pragma_enum arm_pragma_long_calls = OFF;
4958 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
4960 arm_pragma_long_calls = LONG;
4964 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
4966 arm_pragma_long_calls = SHORT;
4970 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
4972 arm_pragma_long_calls = OFF;
4975 /* Handle an attribute requiring a FUNCTION_DECL;
4976 arguments as in struct attribute_spec.handler. */
4978 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
4979 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
4981 if (TREE_CODE (*node) != FUNCTION_DECL)
4983 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4985 *no_add_attrs = true;
4991 /* Handle an "interrupt" or "isr" attribute;
4992 arguments as in struct attribute_spec.handler. */
4994 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
4999 if (TREE_CODE (*node) != FUNCTION_DECL)
5001 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5003 *no_add_attrs = true;
5005 /* FIXME: the argument if any is checked for type attributes;
5006 should it be checked for decl ones? */
5010 if (TREE_CODE (*node) == FUNCTION_TYPE
5011 || TREE_CODE (*node) == METHOD_TYPE)
5013 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
5015 warning (OPT_Wattributes, "%qE attribute ignored",
5017 *no_add_attrs = true;
5020 else if (TREE_CODE (*node) == POINTER_TYPE
5021 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
5022 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
5023 && arm_isr_value (args) != ARM_FT_UNKNOWN)
5025 *node = build_variant_type_copy (*node);
5026 TREE_TYPE (*node) = build_type_attribute_variant
5028 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
5029 *no_add_attrs = true;
5033 /* Possibly pass this attribute on from the type to a decl. */
5034 if (flags & ((int) ATTR_FLAG_DECL_NEXT
5035 | (int) ATTR_FLAG_FUNCTION_NEXT
5036 | (int) ATTR_FLAG_ARRAY_NEXT))
5038 *no_add_attrs = true;
5039 return tree_cons (name, args, NULL_TREE);
5043 warning (OPT_Wattributes, "%qE attribute ignored",
5052 /* Handle a "pcs" attribute; arguments as in struct
5053 attribute_spec.handler. */
5055 arm_handle_pcs_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
5056 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
5058 if (arm_pcs_from_attribute (args) == ARM_PCS_UNKNOWN)
5060 warning (OPT_Wattributes, "%qE attribute ignored", name);
5061 *no_add_attrs = true;
5066 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
5067 /* Handle the "notshared" attribute. This attribute is another way of
5068 requesting hidden visibility. ARM's compiler supports
5069 "__declspec(notshared)"; we support the same thing via an
5073 arm_handle_notshared_attribute (tree *node,
5074 tree name ATTRIBUTE_UNUSED,
5075 tree args ATTRIBUTE_UNUSED,
5076 int flags ATTRIBUTE_UNUSED,
5079 tree decl = TYPE_NAME (*node);
5083 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
5084 DECL_VISIBILITY_SPECIFIED (decl) = 1;
5085 *no_add_attrs = false;
5091 /* Return 0 if the attributes for two types are incompatible, 1 if they
5092 are compatible, and 2 if they are nearly compatible (which causes a
5093 warning to be generated). */
5095 arm_comp_type_attributes (const_tree type1, const_tree type2)
5099 /* Check for mismatch of non-default calling convention. */
5100 if (TREE_CODE (type1) != FUNCTION_TYPE)
5103 /* Check for mismatched call attributes. */
5104 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
5105 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
5106 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
5107 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
5109 /* Only bother to check if an attribute is defined. */
5110 if (l1 | l2 | s1 | s2)
5112 /* If one type has an attribute, the other must have the same attribute. */
5113 if ((l1 != l2) || (s1 != s2))
5116 /* Disallow mixed attributes. */
5117 if ((l1 & s2) || (l2 & s1))
5121 /* Check for mismatched ISR attribute. */
5122 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
5124 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
5125 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
5127 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
5134 /* Assigns default attributes to newly defined type. This is used to
5135 set short_call/long_call attributes for function types of
5136 functions defined inside corresponding #pragma scopes. */
5138 arm_set_default_type_attributes (tree type)
5140 /* Add __attribute__ ((long_call)) to all functions, when
5141 inside #pragma long_calls or __attribute__ ((short_call)),
5142 when inside #pragma no_long_calls. */
5143 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
5145 tree type_attr_list, attr_name;
5146 type_attr_list = TYPE_ATTRIBUTES (type);
5148 if (arm_pragma_long_calls == LONG)
5149 attr_name = get_identifier ("long_call");
5150 else if (arm_pragma_long_calls == SHORT)
5151 attr_name = get_identifier ("short_call");
5155 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
5156 TYPE_ATTRIBUTES (type) = type_attr_list;
5160 /* Return true if DECL is known to be linked into section SECTION. */
5163 arm_function_in_section_p (tree decl, section *section)
5165 /* We can only be certain about functions defined in the same
5166 compilation unit. */
5167 if (!TREE_STATIC (decl))
5170 /* Make sure that SYMBOL always binds to the definition in this
5171 compilation unit. */
5172 if (!targetm.binds_local_p (decl))
5175 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
5176 if (!DECL_SECTION_NAME (decl))
5178 /* Make sure that we will not create a unique section for DECL. */
5179 if (flag_function_sections || DECL_ONE_ONLY (decl))
5183 return function_section (decl) == section;
5186 /* Return nonzero if a 32-bit "long_call" should be generated for
5187 a call from the current function to DECL. We generate a long_call
5190 a. has an __attribute__((long call))
5191 or b. is within the scope of a #pragma long_calls
5192 or c. the -mlong-calls command line switch has been specified
5194 However we do not generate a long call if the function:
5196 d. has an __attribute__ ((short_call))
5197 or e. is inside the scope of a #pragma no_long_calls
5198 or f. is defined in the same section as the current function. */
5201 arm_is_long_call_p (tree decl)
5206 return TARGET_LONG_CALLS;
5208 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
5209 if (lookup_attribute ("short_call", attrs))
5212 /* For "f", be conservative, and only cater for cases in which the
5213 whole of the current function is placed in the same section. */
5214 if (!flag_reorder_blocks_and_partition
5215 && TREE_CODE (decl) == FUNCTION_DECL
5216 && arm_function_in_section_p (decl, current_function_section ()))
5219 if (lookup_attribute ("long_call", attrs))
5222 return TARGET_LONG_CALLS;
5225 /* Return nonzero if it is ok to make a tail-call to DECL. */
5227 arm_function_ok_for_sibcall (tree decl, tree exp)
5229 unsigned long func_type;
5231 if (cfun->machine->sibcall_blocked)
5234 /* Never tailcall something for which we have no decl, or if we
5235 are generating code for Thumb-1. */
5236 if (decl == NULL || TARGET_THUMB1)
5239 /* The PIC register is live on entry to VxWorks PLT entries, so we
5240 must make the call before restoring the PIC register. */
5241 if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
5244 /* Cannot tail-call to long calls, since these are out of range of
5245 a branch instruction. */
5246 if (arm_is_long_call_p (decl))
5249 /* If we are interworking and the function is not declared static
5250 then we can't tail-call it unless we know that it exists in this
5251 compilation unit (since it might be a Thumb routine). */
5252 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
5255 func_type = arm_current_func_type ();
5256 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
5257 if (IS_INTERRUPT (func_type))
5260 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
5262 /* Check that the return value locations are the same. For
5263 example that we aren't returning a value from the sibling in
5264 a VFP register but then need to transfer it to a core
5268 a = arm_function_value (TREE_TYPE (exp), decl, false);
5269 b = arm_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
5271 if (!rtx_equal_p (a, b))
5275 /* Never tailcall if function may be called with a misaligned SP. */
5276 if (IS_STACKALIGN (func_type))
5279 /* The AAPCS says that, on bare-metal, calls to unresolved weak
5280 references should become a NOP. Don't convert such calls into
5282 if (TARGET_AAPCS_BASED
5283 && arm_abi == ARM_ABI_AAPCS
5284 && DECL_WEAK (decl))
5287 /* Everything else is ok. */
5292 /* Addressing mode support functions. */
5294 /* Return nonzero if X is a legitimate immediate operand when compiling
5295 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
5297 legitimate_pic_operand_p (rtx x)
5299 if (GET_CODE (x) == SYMBOL_REF
5300 || (GET_CODE (x) == CONST
5301 && GET_CODE (XEXP (x, 0)) == PLUS
5302 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5308 /* Record that the current function needs a PIC register. Initialize
5309 cfun->machine->pic_reg if we have not already done so. */
5312 require_pic_register (void)
5314 /* A lot of the logic here is made obscure by the fact that this
5315 routine gets called as part of the rtx cost estimation process.
5316 We don't want those calls to affect any assumptions about the real
5317 function; and further, we can't call entry_of_function() until we
5318 start the real expansion process. */
5319 if (!crtl->uses_pic_offset_table)
5321 gcc_assert (can_create_pseudo_p ());
5322 if (arm_pic_register != INVALID_REGNUM)
5324 if (!cfun->machine->pic_reg)
5325 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
5327 /* Play games to avoid marking the function as needing pic
5328 if we are being called as part of the cost-estimation
5330 if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl)
5331 crtl->uses_pic_offset_table = 1;
5337 if (!cfun->machine->pic_reg)
5338 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
5340 /* Play games to avoid marking the function as needing pic
5341 if we are being called as part of the cost-estimation
5343 if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl)
5345 crtl->uses_pic_offset_table = 1;
5348 arm_load_pic_register (0UL);
5353 for (insn = seq; insn; insn = NEXT_INSN (insn))
5355 INSN_LOCATOR (insn) = prologue_locator;
5357 /* We can be called during expansion of PHI nodes, where
5358 we can't yet emit instructions directly in the final
5359 insn stream. Queue the insns on the entry edge, they will
5360 be committed after everything else is expanded. */
5361 insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
5368 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
5370 if (GET_CODE (orig) == SYMBOL_REF
5371 || GET_CODE (orig) == LABEL_REF)
5377 gcc_assert (can_create_pseudo_p ());
5378 reg = gen_reg_rtx (Pmode);
5381 /* VxWorks does not impose a fixed gap between segments; the run-time
5382 gap can be different from the object-file gap. We therefore can't
5383 use GOTOFF unless we are absolutely sure that the symbol is in the
5384 same segment as the GOT. Unfortunately, the flexibility of linker
5385 scripts means that we can't be sure of that in general, so assume
5386 that GOTOFF is never valid on VxWorks. */
5387 if ((GET_CODE (orig) == LABEL_REF
5388 || (GET_CODE (orig) == SYMBOL_REF &&
5389 SYMBOL_REF_LOCAL_P (orig)))
5391 && !TARGET_VXWORKS_RTP)
5392 insn = arm_pic_static_addr (orig, reg);
5398 /* If this function doesn't have a pic register, create one now. */
5399 require_pic_register ();
5401 pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig);
5403 /* Make the MEM as close to a constant as possible. */
5404 mem = SET_SRC (pat);
5405 gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem));
5406 MEM_READONLY_P (mem) = 1;
5407 MEM_NOTRAP_P (mem) = 1;
5409 insn = emit_insn (pat);
5412 /* Put a REG_EQUAL note on this insn, so that it can be optimized
5414 set_unique_reg_note (insn, REG_EQUAL, orig);
5418 else if (GET_CODE (orig) == CONST)
5422 if (GET_CODE (XEXP (orig, 0)) == PLUS
5423 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
5426 /* Handle the case where we have: const (UNSPEC_TLS). */
5427 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
5428 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
5431 /* Handle the case where we have:
5432 const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a
5434 if (GET_CODE (XEXP (orig, 0)) == PLUS
5435 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC
5436 && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS)
5438 gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT);
5444 gcc_assert (can_create_pseudo_p ());
5445 reg = gen_reg_rtx (Pmode);
5448 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
5450 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
5451 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
5452 base == reg ? 0 : reg);
5454 if (GET_CODE (offset) == CONST_INT)
5456 /* The base register doesn't really matter, we only want to
5457 test the index for the appropriate mode. */
5458 if (!arm_legitimate_index_p (mode, offset, SET, 0))
5460 gcc_assert (can_create_pseudo_p ());
5461 offset = force_reg (Pmode, offset);
5464 if (GET_CODE (offset) == CONST_INT)
5465 return plus_constant (base, INTVAL (offset));
5468 if (GET_MODE_SIZE (mode) > 4
5469 && (GET_MODE_CLASS (mode) == MODE_INT
5470 || TARGET_SOFT_FLOAT))
5472 emit_insn (gen_addsi3 (reg, base, offset));
5476 return gen_rtx_PLUS (Pmode, base, offset);
5483 /* Find a spare register to use during the prolog of a function. */
5486 thumb_find_work_register (unsigned long pushed_regs_mask)
5490 /* Check the argument registers first as these are call-used. The
5491 register allocation order means that sometimes r3 might be used
5492 but earlier argument registers might not, so check them all. */
5493 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
5494 if (!df_regs_ever_live_p (reg))
5497 /* Before going on to check the call-saved registers we can try a couple
5498 more ways of deducing that r3 is available. The first is when we are
5499 pushing anonymous arguments onto the stack and we have less than 4
5500 registers worth of fixed arguments(*). In this case r3 will be part of
5501 the variable argument list and so we can be sure that it will be
5502 pushed right at the start of the function. Hence it will be available
5503 for the rest of the prologue.
5504 (*): ie crtl->args.pretend_args_size is greater than 0. */
5505 if (cfun->machine->uses_anonymous_args
5506 && crtl->args.pretend_args_size > 0)
5507 return LAST_ARG_REGNUM;
5509 /* The other case is when we have fixed arguments but less than 4 registers
5510 worth. In this case r3 might be used in the body of the function, but
5511 it is not being used to convey an argument into the function. In theory
5512 we could just check crtl->args.size to see how many bytes are
5513 being passed in argument registers, but it seems that it is unreliable.
5514 Sometimes it will have the value 0 when in fact arguments are being
5515 passed. (See testcase execute/20021111-1.c for an example). So we also
5516 check the args_info.nregs field as well. The problem with this field is
5517 that it makes no allowances for arguments that are passed to the
5518 function but which are not used. Hence we could miss an opportunity
5519 when a function has an unused argument in r3. But it is better to be
5520 safe than to be sorry. */
5521 if (! cfun->machine->uses_anonymous_args
5522 && crtl->args.size >= 0
5523 && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
5524 && (TARGET_AAPCS_BASED
5525 ? crtl->args.info.aapcs_ncrn < 4
5526 : crtl->args.info.nregs < 4))
5527 return LAST_ARG_REGNUM;
5529 /* Otherwise look for a call-saved register that is going to be pushed. */
5530 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
5531 if (pushed_regs_mask & (1 << reg))
5536 /* Thumb-2 can use high regs. */
5537 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
5538 if (pushed_regs_mask & (1 << reg))
5541 /* Something went wrong - thumb_compute_save_reg_mask()
5542 should have arranged for a suitable register to be pushed. */
5546 static GTY(()) int pic_labelno;
5548 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
5552 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
5554 rtx l1, labelno, pic_tmp, pic_rtx, pic_reg;
5556 if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
5559 gcc_assert (flag_pic);
5561 pic_reg = cfun->machine->pic_reg;
5562 if (TARGET_VXWORKS_RTP)
5564 pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
5565 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
5566 emit_insn (gen_pic_load_addr_32bit (pic_reg, pic_rtx));
5568 emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg)));
5570 pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5571 emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp));
5575 /* We use an UNSPEC rather than a LABEL_REF because this label
5576 never appears in the code stream. */
5578 labelno = GEN_INT (pic_labelno++);
5579 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
5580 l1 = gen_rtx_CONST (VOIDmode, l1);
5582 /* On the ARM the PC register contains 'dot + 8' at the time of the
5583 addition, on the Thumb it is 'dot + 4'. */
5584 pic_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4);
5585 pic_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, pic_rtx),
5587 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
5591 emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));
5593 else /* TARGET_THUMB1 */
5595 if (arm_pic_register != INVALID_REGNUM
5596 && REGNO (pic_reg) > LAST_LO_REGNUM)
5598 /* We will have pushed the pic register, so we should always be
5599 able to find a work register. */
5600 pic_tmp = gen_rtx_REG (SImode,
5601 thumb_find_work_register (saved_regs));
5602 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
5603 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
5604 emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
5607 emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));
5611 /* Need to emit this whether or not we obey regdecls,
5612 since setjmp/longjmp can cause life info to screw up. */
5616 /* Generate code to load the address of a static var when flag_pic is set. */
5618 arm_pic_static_addr (rtx orig, rtx reg)
5620 rtx l1, labelno, offset_rtx, insn;
5622 gcc_assert (flag_pic);
5624 /* We use an UNSPEC rather than a LABEL_REF because this label
5625 never appears in the code stream. */
5626 labelno = GEN_INT (pic_labelno++);
5627 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
5628 l1 = gen_rtx_CONST (VOIDmode, l1);
5630 /* On the ARM the PC register contains 'dot + 8' at the time of the
5631 addition, on the Thumb it is 'dot + 4'. */
5632 offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4);
5633 offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx),
5634 UNSPEC_SYMBOL_OFFSET);
5635 offset_rtx = gen_rtx_CONST (Pmode, offset_rtx);
5637 insn = emit_insn (gen_pic_load_addr_unified (reg, offset_rtx, labelno));
5641 /* Return nonzero if X is valid as an ARM state addressing register. */
5643 arm_address_register_rtx_p (rtx x, int strict_p)
5647 if (GET_CODE (x) != REG)
5653 return ARM_REGNO_OK_FOR_BASE_P (regno);
5655 return (regno <= LAST_ARM_REGNUM
5656 || regno >= FIRST_PSEUDO_REGISTER
5657 || regno == FRAME_POINTER_REGNUM
5658 || regno == ARG_POINTER_REGNUM);
5661 /* Return TRUE if this rtx is the difference of a symbol and a label,
5662 and will reduce to a PC-relative relocation in the object file.
5663 Expressions like this can be left alone when generating PIC, rather
5664 than forced through the GOT. */
5666 pcrel_constant_p (rtx x)
5668 if (GET_CODE (x) == MINUS)
5669 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
5674 /* Return true if X will surely end up in an index register after next
5677 will_be_in_index_register (const_rtx x)
5679 /* arm.md: calculate_pic_address will split this into a register. */
5680 return GET_CODE (x) == UNSPEC && (XINT (x, 1) == UNSPEC_PIC_SYM);
5683 /* Return nonzero if X is a valid ARM state address operand. */
5685 arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer,
5689 enum rtx_code code = GET_CODE (x);
5691 if (arm_address_register_rtx_p (x, strict_p))
5694 use_ldrd = (TARGET_LDRD
5696 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
5698 if (code == POST_INC || code == PRE_DEC
5699 || ((code == PRE_INC || code == POST_DEC)
5700 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
5701 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
5703 else if ((code == POST_MODIFY || code == PRE_MODIFY)
5704 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
5705 && GET_CODE (XEXP (x, 1)) == PLUS
5706 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5708 rtx addend = XEXP (XEXP (x, 1), 1);
5710 /* Don't allow ldrd post increment by register because it's hard
5711 to fixup invalid register choices. */
5713 && GET_CODE (x) == POST_MODIFY
5714 && GET_CODE (addend) == REG)
5717 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
5718 && arm_legitimate_index_p (mode, addend, outer, strict_p));
5721 /* After reload constants split into minipools will have addresses
5722 from a LABEL_REF. */
5723 else if (reload_completed
5724 && (code == LABEL_REF
5726 && GET_CODE (XEXP (x, 0)) == PLUS
5727 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
5728 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5731 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
5734 else if (code == PLUS)
5736 rtx xop0 = XEXP (x, 0);
5737 rtx xop1 = XEXP (x, 1);
5739 return ((arm_address_register_rtx_p (xop0, strict_p)
5740 && ((GET_CODE(xop1) == CONST_INT
5741 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
5742 || (!strict_p && will_be_in_index_register (xop1))))
5743 || (arm_address_register_rtx_p (xop1, strict_p)
5744 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
5748 /* Reload currently can't handle MINUS, so disable this for now */
5749 else if (GET_CODE (x) == MINUS)
5751 rtx xop0 = XEXP (x, 0);
5752 rtx xop1 = XEXP (x, 1);
5754 return (arm_address_register_rtx_p (xop0, strict_p)
5755 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
5759 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
5760 && code == SYMBOL_REF
5761 && CONSTANT_POOL_ADDRESS_P (x)
5763 && symbol_mentioned_p (get_pool_constant (x))
5764 && ! pcrel_constant_p (get_pool_constant (x))))
5770 /* Return nonzero if X is a valid Thumb-2 address operand. */
5772 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
5775 enum rtx_code code = GET_CODE (x);
5777 if (arm_address_register_rtx_p (x, strict_p))
5780 use_ldrd = (TARGET_LDRD
5782 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
5784 if (code == POST_INC || code == PRE_DEC
5785 || ((code == PRE_INC || code == POST_DEC)
5786 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
5787 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
5789 else if ((code == POST_MODIFY || code == PRE_MODIFY)
5790 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
5791 && GET_CODE (XEXP (x, 1)) == PLUS
5792 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5794 /* Thumb-2 only has autoincrement by constant. */
5795 rtx addend = XEXP (XEXP (x, 1), 1);
5796 HOST_WIDE_INT offset;
5798 if (GET_CODE (addend) != CONST_INT)
5801 offset = INTVAL(addend);
5802 if (GET_MODE_SIZE (mode) <= 4)
5803 return (offset > -256 && offset < 256);
5805 return (use_ldrd && offset > -1024 && offset < 1024
5806 && (offset & 3) == 0);
5809 /* After reload constants split into minipools will have addresses
5810 from a LABEL_REF. */
5811 else if (reload_completed
5812 && (code == LABEL_REF
5814 && GET_CODE (XEXP (x, 0)) == PLUS
5815 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
5816 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5819 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
5822 else if (code == PLUS)
5824 rtx xop0 = XEXP (x, 0);
5825 rtx xop1 = XEXP (x, 1);
5827 return ((arm_address_register_rtx_p (xop0, strict_p)
5828 && (thumb2_legitimate_index_p (mode, xop1, strict_p)
5829 || (!strict_p && will_be_in_index_register (xop1))))
5830 || (arm_address_register_rtx_p (xop1, strict_p)
5831 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
5834 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
5835 && code == SYMBOL_REF
5836 && CONSTANT_POOL_ADDRESS_P (x)
5838 && symbol_mentioned_p (get_pool_constant (x))
5839 && ! pcrel_constant_p (get_pool_constant (x))))
5845 /* Return nonzero if INDEX is valid for an address index operand in
5848 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
5851 HOST_WIDE_INT range;
5852 enum rtx_code code = GET_CODE (index);
5854 /* Standard coprocessor addressing modes. */
5855 if (TARGET_HARD_FLOAT
5856 && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
5857 && (mode == SFmode || mode == DFmode
5858 || (TARGET_MAVERICK && mode == DImode)))
5859 return (code == CONST_INT && INTVAL (index) < 1024
5860 && INTVAL (index) > -1024
5861 && (INTVAL (index) & 3) == 0);
5863 /* For quad modes, we restrict the constant offset to be slightly less
5864 than what the instruction format permits. We do this because for
5865 quad mode moves, we will actually decompose them into two separate
5866 double-mode reads or writes. INDEX must therefore be a valid
5867 (double-mode) offset and so should INDEX+8. */
5868 if (TARGET_NEON && VALID_NEON_QREG_MODE (mode))
5869 return (code == CONST_INT
5870 && INTVAL (index) < 1016
5871 && INTVAL (index) > -1024
5872 && (INTVAL (index) & 3) == 0);
5874 /* We have no such constraint on double mode offsets, so we permit the
5875 full range of the instruction format. */
5876 if (TARGET_NEON && VALID_NEON_DREG_MODE (mode))
5877 return (code == CONST_INT
5878 && INTVAL (index) < 1024
5879 && INTVAL (index) > -1024
5880 && (INTVAL (index) & 3) == 0);
5882 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
5883 return (code == CONST_INT
5884 && INTVAL (index) < 1024
5885 && INTVAL (index) > -1024
5886 && (INTVAL (index) & 3) == 0);
5888 if (arm_address_register_rtx_p (index, strict_p)
5889 && (GET_MODE_SIZE (mode) <= 4))
5892 if (mode == DImode || mode == DFmode)
5894 if (code == CONST_INT)
5896 HOST_WIDE_INT val = INTVAL (index);
5899 return val > -256 && val < 256;
5901 return val > -4096 && val < 4092;
5904 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
5907 if (GET_MODE_SIZE (mode) <= 4
5911 || (mode == QImode && outer == SIGN_EXTEND))))
5915 rtx xiop0 = XEXP (index, 0);
5916 rtx xiop1 = XEXP (index, 1);
5918 return ((arm_address_register_rtx_p (xiop0, strict_p)
5919 && power_of_two_operand (xiop1, SImode))
5920 || (arm_address_register_rtx_p (xiop1, strict_p)
5921 && power_of_two_operand (xiop0, SImode)));
5923 else if (code == LSHIFTRT || code == ASHIFTRT
5924 || code == ASHIFT || code == ROTATERT)
5926 rtx op = XEXP (index, 1);
5928 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
5929 && GET_CODE (op) == CONST_INT
5931 && INTVAL (op) <= 31);
5935 /* For ARM v4 we may be doing a sign-extend operation during the
5941 || (outer == SIGN_EXTEND && mode == QImode))
5947 range = (mode == HImode || mode == HFmode) ? 4095 : 4096;
5949 return (code == CONST_INT
5950 && INTVAL (index) < range
5951 && INTVAL (index) > -range);
5954 /* Return true if OP is a valid index scaling factor for Thumb-2 address
5955 index operand. i.e. 1, 2, 4 or 8. */
5957 thumb2_index_mul_operand (rtx op)
5961 if (GET_CODE(op) != CONST_INT)
5965 return (val == 1 || val == 2 || val == 4 || val == 8);
5968 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
5970 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
5972 enum rtx_code code = GET_CODE (index);
5974 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
5975 /* Standard coprocessor addressing modes. */
5976 if (TARGET_HARD_FLOAT
5977 && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
5978 && (mode == SFmode || mode == DFmode
5979 || (TARGET_MAVERICK && mode == DImode)))
5980 return (code == CONST_INT && INTVAL (index) < 1024
5981 /* Thumb-2 allows only > -256 index range for it's core register
5982 load/stores. Since we allow SF/DF in core registers, we have
5983 to use the intersection between -256~4096 (core) and -1024~1024
5985 && INTVAL (index) > -256
5986 && (INTVAL (index) & 3) == 0);
5988 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
5990 /* For DImode assume values will usually live in core regs
5991 and only allow LDRD addressing modes. */
5992 if (!TARGET_LDRD || mode != DImode)
5993 return (code == CONST_INT
5994 && INTVAL (index) < 1024
5995 && INTVAL (index) > -1024
5996 && (INTVAL (index) & 3) == 0);
5999 /* For quad modes, we restrict the constant offset to be slightly less
6000 than what the instruction format permits. We do this because for
6001 quad mode moves, we will actually decompose them into two separate
6002 double-mode reads or writes. INDEX must therefore be a valid
6003 (double-mode) offset and so should INDEX+8. */
6004 if (TARGET_NEON && VALID_NEON_QREG_MODE (mode))
6005 return (code == CONST_INT
6006 && INTVAL (index) < 1016
6007 && INTVAL (index) > -1024
6008 && (INTVAL (index) & 3) == 0);
6010 /* We have no such constraint on double mode offsets, so we permit the
6011 full range of the instruction format. */
6012 if (TARGET_NEON && VALID_NEON_DREG_MODE (mode))
6013 return (code == CONST_INT
6014 && INTVAL (index) < 1024
6015 && INTVAL (index) > -1024
6016 && (INTVAL (index) & 3) == 0);
6018 if (arm_address_register_rtx_p (index, strict_p)
6019 && (GET_MODE_SIZE (mode) <= 4))
6022 if (mode == DImode || mode == DFmode)
6024 if (code == CONST_INT)
6026 HOST_WIDE_INT val = INTVAL (index);
6027 /* ??? Can we assume ldrd for thumb2? */
6028 /* Thumb-2 ldrd only has reg+const addressing modes. */
6029 /* ldrd supports offsets of +-1020.
6030 However the ldr fallback does not. */
6031 return val > -256 && val < 256 && (val & 3) == 0;
6039 rtx xiop0 = XEXP (index, 0);
6040 rtx xiop1 = XEXP (index, 1);
6042 return ((arm_address_register_rtx_p (xiop0, strict_p)
6043 && thumb2_index_mul_operand (xiop1))
6044 || (arm_address_register_rtx_p (xiop1, strict_p)
6045 && thumb2_index_mul_operand (xiop0)));
6047 else if (code == ASHIFT)
6049 rtx op = XEXP (index, 1);
6051 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
6052 && GET_CODE (op) == CONST_INT
6054 && INTVAL (op) <= 3);
6057 return (code == CONST_INT
6058 && INTVAL (index) < 4096
6059 && INTVAL (index) > -256);
6062 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
6064 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
6068 if (GET_CODE (x) != REG)
6074 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
6076 return (regno <= LAST_LO_REGNUM
6077 || regno > LAST_VIRTUAL_REGISTER
6078 || regno == FRAME_POINTER_REGNUM
6079 || (GET_MODE_SIZE (mode) >= 4
6080 && (regno == STACK_POINTER_REGNUM
6081 || regno >= FIRST_PSEUDO_REGISTER
6082 || x == hard_frame_pointer_rtx
6083 || x == arg_pointer_rtx)));
6086 /* Return nonzero if x is a legitimate index register. This is the case
6087 for any base register that can access a QImode object. */
6089 thumb1_index_register_rtx_p (rtx x, int strict_p)
6091 return thumb1_base_register_rtx_p (x, QImode, strict_p);
6094 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
6096 The AP may be eliminated to either the SP or the FP, so we use the
6097 least common denominator, e.g. SImode, and offsets from 0 to 64.
6099 ??? Verify whether the above is the right approach.
6101 ??? Also, the FP may be eliminated to the SP, so perhaps that
6102 needs special handling also.
6104 ??? Look at how the mips16 port solves this problem. It probably uses
6105 better ways to solve some of these problems.
6107 Although it is not incorrect, we don't accept QImode and HImode
6108 addresses based on the frame pointer or arg pointer until the
6109 reload pass starts. This is so that eliminating such addresses
6110 into stack based ones won't produce impossible code. */
6112 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
6114 /* ??? Not clear if this is right. Experiment. */
6115 if (GET_MODE_SIZE (mode) < 4
6116 && !(reload_in_progress || reload_completed)
6117 && (reg_mentioned_p (frame_pointer_rtx, x)
6118 || reg_mentioned_p (arg_pointer_rtx, x)
6119 || reg_mentioned_p (virtual_incoming_args_rtx, x)
6120 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
6121 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
6122 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
6125 /* Accept any base register. SP only in SImode or larger. */
6126 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
6129 /* This is PC relative data before arm_reorg runs. */
6130 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
6131 && GET_CODE (x) == SYMBOL_REF
6132 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
6135 /* This is PC relative data after arm_reorg runs. */
6136 else if ((GET_MODE_SIZE (mode) >= 4 || mode == HFmode)
6138 && (GET_CODE (x) == LABEL_REF
6139 || (GET_CODE (x) == CONST
6140 && GET_CODE (XEXP (x, 0)) == PLUS
6141 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
6142 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
6145 /* Post-inc indexing only supported for SImode and larger. */
6146 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
6147 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
6150 else if (GET_CODE (x) == PLUS)
6152 /* REG+REG address can be any two index registers. */
6153 /* We disallow FRAME+REG addressing since we know that FRAME
6154 will be replaced with STACK, and SP relative addressing only
6155 permits SP+OFFSET. */
6156 if (GET_MODE_SIZE (mode) <= 4
6157 && XEXP (x, 0) != frame_pointer_rtx
6158 && XEXP (x, 1) != frame_pointer_rtx
6159 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
6160 && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)
6161 || (!strict_p && will_be_in_index_register (XEXP (x, 1)))))
6164 /* REG+const has 5-7 bit offset for non-SP registers. */
6165 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
6166 || XEXP (x, 0) == arg_pointer_rtx)
6167 && GET_CODE (XEXP (x, 1)) == CONST_INT
6168 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
6171 /* REG+const has 10-bit offset for SP, but only SImode and
6172 larger is supported. */
6173 /* ??? Should probably check for DI/DFmode overflow here
6174 just like GO_IF_LEGITIMATE_OFFSET does. */
6175 else if (GET_CODE (XEXP (x, 0)) == REG
6176 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
6177 && GET_MODE_SIZE (mode) >= 4
6178 && GET_CODE (XEXP (x, 1)) == CONST_INT
6179 && INTVAL (XEXP (x, 1)) >= 0
6180 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
6181 && (INTVAL (XEXP (x, 1)) & 3) == 0)
6184 else if (GET_CODE (XEXP (x, 0)) == REG
6185 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
6186 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
6187 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
6188 && REGNO (XEXP (x, 0))
6189 <= LAST_VIRTUAL_POINTER_REGISTER))
6190 && GET_MODE_SIZE (mode) >= 4
6191 && GET_CODE (XEXP (x, 1)) == CONST_INT
6192 && (INTVAL (XEXP (x, 1)) & 3) == 0)
6196 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
6197 && GET_MODE_SIZE (mode) == 4
6198 && GET_CODE (x) == SYMBOL_REF
6199 && CONSTANT_POOL_ADDRESS_P (x)
6201 && symbol_mentioned_p (get_pool_constant (x))
6202 && ! pcrel_constant_p (get_pool_constant (x))))
6208 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
6209 instruction of mode MODE. */
6211 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
6213 switch (GET_MODE_SIZE (mode))
6216 return val >= 0 && val < 32;
6219 return val >= 0 && val < 64 && (val & 1) == 0;
6223 && (val + GET_MODE_SIZE (mode)) <= 128
6229 arm_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
6232 return arm_legitimate_address_outer_p (mode, x, SET, strict_p);
6233 else if (TARGET_THUMB2)
6234 return thumb2_legitimate_address_p (mode, x, strict_p);
6235 else /* if (TARGET_THUMB1) */
6236 return thumb1_legitimate_address_p (mode, x, strict_p);
6239 /* Build the SYMBOL_REF for __tls_get_addr. */
6241 static GTY(()) rtx tls_get_addr_libfunc;
6244 get_tls_get_addr (void)
6246 if (!tls_get_addr_libfunc)
6247 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
6248 return tls_get_addr_libfunc;
6252 arm_load_tp (rtx target)
6255 target = gen_reg_rtx (SImode);
6259 /* Can return in any reg. */
6260 emit_insn (gen_load_tp_hard (target));
6264 /* Always returned in r0. Immediately copy the result into a pseudo,
6265 otherwise other uses of r0 (e.g. setting up function arguments) may
6266 clobber the value. */
6270 emit_insn (gen_load_tp_soft ());
6272 tmp = gen_rtx_REG (SImode, 0);
6273 emit_move_insn (target, tmp);
6279 load_tls_operand (rtx x, rtx reg)
6283 if (reg == NULL_RTX)
6284 reg = gen_reg_rtx (SImode);
6286 tmp = gen_rtx_CONST (SImode, x);
6288 emit_move_insn (reg, tmp);
6294 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
6296 rtx insns, label, labelno, sum;
6298 gcc_assert (reloc != TLS_DESCSEQ);
6301 labelno = GEN_INT (pic_labelno++);
6302 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
6303 label = gen_rtx_CONST (VOIDmode, label);
6305 sum = gen_rtx_UNSPEC (Pmode,
6306 gen_rtvec (4, x, GEN_INT (reloc), label,
6307 GEN_INT (TARGET_ARM ? 8 : 4)),
6309 reg = load_tls_operand (sum, reg);
6312 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
6314 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
6316 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX,
6317 LCT_PURE, /* LCT_CONST? */
6318 Pmode, 1, reg, Pmode);
6320 insns = get_insns ();
6327 arm_tls_descseq_addr (rtx x, rtx reg)
6329 rtx labelno = GEN_INT (pic_labelno++);
6330 rtx label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
6331 rtx sum = gen_rtx_UNSPEC (Pmode,
6332 gen_rtvec (4, x, GEN_INT (TLS_DESCSEQ),
6333 gen_rtx_CONST (VOIDmode, label),
6334 GEN_INT (!TARGET_ARM)),
6336 rtx reg0 = load_tls_operand (sum, gen_rtx_REG (SImode, 0));
6338 emit_insn (gen_tlscall (x, labelno));
6340 reg = gen_reg_rtx (SImode);
6342 gcc_assert (REGNO (reg) != 0);
6344 emit_move_insn (reg, reg0);
6350 legitimize_tls_address (rtx x, rtx reg)
6352 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
6353 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
6357 case TLS_MODEL_GLOBAL_DYNAMIC:
6358 if (TARGET_GNU2_TLS)
6360 reg = arm_tls_descseq_addr (x, reg);
6362 tp = arm_load_tp (NULL_RTX);
6364 dest = gen_rtx_PLUS (Pmode, tp, reg);
6368 /* Original scheme */
6369 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
6370 dest = gen_reg_rtx (Pmode);
6371 emit_libcall_block (insns, dest, ret, x);
6375 case TLS_MODEL_LOCAL_DYNAMIC:
6376 if (TARGET_GNU2_TLS)
6378 reg = arm_tls_descseq_addr (x, reg);
6380 tp = arm_load_tp (NULL_RTX);
6382 dest = gen_rtx_PLUS (Pmode, tp, reg);
6386 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
6388 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
6389 share the LDM result with other LD model accesses. */
6390 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
6392 dest = gen_reg_rtx (Pmode);
6393 emit_libcall_block (insns, dest, ret, eqv);
6395 /* Load the addend. */
6396 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x,
6397 GEN_INT (TLS_LDO32)),
6399 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
6400 dest = gen_rtx_PLUS (Pmode, dest, addend);
6404 case TLS_MODEL_INITIAL_EXEC:
6405 labelno = GEN_INT (pic_labelno++);
6406 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
6407 label = gen_rtx_CONST (VOIDmode, label);
6408 sum = gen_rtx_UNSPEC (Pmode,
6409 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
6410 GEN_INT (TARGET_ARM ? 8 : 4)),
6412 reg = load_tls_operand (sum, reg);
6415 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
6416 else if (TARGET_THUMB2)
6417 emit_insn (gen_tls_load_dot_plus_four (reg, NULL, reg, labelno));
6420 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
6421 emit_move_insn (reg, gen_const_mem (SImode, reg));
6424 tp = arm_load_tp (NULL_RTX);
6426 return gen_rtx_PLUS (Pmode, tp, reg);
6428 case TLS_MODEL_LOCAL_EXEC:
6429 tp = arm_load_tp (NULL_RTX);
6431 reg = gen_rtx_UNSPEC (Pmode,
6432 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
6434 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
6436 return gen_rtx_PLUS (Pmode, tp, reg);
6443 /* Try machine-dependent ways of modifying an illegitimate address
6444 to be legitimate. If we find one, return the new, valid address. */
6446 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
6450 /* TODO: legitimize_address for Thumb2. */
6453 return thumb_legitimize_address (x, orig_x, mode);
6456 if (arm_tls_symbol_p (x))
6457 return legitimize_tls_address (x, NULL_RTX);
6459 if (GET_CODE (x) == PLUS)
6461 rtx xop0 = XEXP (x, 0);
6462 rtx xop1 = XEXP (x, 1);
6464 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
6465 xop0 = force_reg (SImode, xop0);
6467 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
6468 xop1 = force_reg (SImode, xop1);
6470 if (ARM_BASE_REGISTER_RTX_P (xop0)
6471 && GET_CODE (xop1) == CONST_INT)
6473 HOST_WIDE_INT n, low_n;
6477 /* VFP addressing modes actually allow greater offsets, but for
6478 now we just stick with the lowest common denominator. */
6480 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
6492 low_n = ((mode) == TImode ? 0
6493 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
6497 base_reg = gen_reg_rtx (SImode);
6498 val = force_operand (plus_constant (xop0, n), NULL_RTX);
6499 emit_move_insn (base_reg, val);
6500 x = plus_constant (base_reg, low_n);
6502 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
6503 x = gen_rtx_PLUS (SImode, xop0, xop1);
6506 /* XXX We don't allow MINUS any more -- see comment in
6507 arm_legitimate_address_outer_p (). */
6508 else if (GET_CODE (x) == MINUS)
6510 rtx xop0 = XEXP (x, 0);
6511 rtx xop1 = XEXP (x, 1);
6513 if (CONSTANT_P (xop0))
6514 xop0 = force_reg (SImode, xop0);
6516 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
6517 xop1 = force_reg (SImode, xop1);
6519 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
6520 x = gen_rtx_MINUS (SImode, xop0, xop1);
6523 /* Make sure to take full advantage of the pre-indexed addressing mode
6524 with absolute addresses which often allows for the base register to
6525 be factorized for multiple adjacent memory references, and it might
6526 even allows for the mini pool to be avoided entirely. */
6527 else if (GET_CODE (x) == CONST_INT && optimize > 0)
6530 HOST_WIDE_INT mask, base, index;
6533 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
6534 use a 8-bit index. So let's use a 12-bit index for SImode only and
6535 hope that arm_gen_constant will enable ldrb to use more bits. */
6536 bits = (mode == SImode) ? 12 : 8;
6537 mask = (1 << bits) - 1;
6538 base = INTVAL (x) & ~mask;
6539 index = INTVAL (x) & mask;
6540 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
6542 /* It'll most probably be more efficient to generate the base
6543 with more bits set and use a negative index instead. */
6547 base_reg = force_reg (SImode, GEN_INT (base));
6548 x = plus_constant (base_reg, index);
6553 /* We need to find and carefully transform any SYMBOL and LABEL
6554 references; so go back to the original address expression. */
6555 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
6557 if (new_x != orig_x)
6565 /* Try machine-dependent ways of modifying an illegitimate Thumb address
6566 to be legitimate. If we find one, return the new, valid address. */
6568 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
6570 if (arm_tls_symbol_p (x))
6571 return legitimize_tls_address (x, NULL_RTX);
6573 if (GET_CODE (x) == PLUS
6574 && GET_CODE (XEXP (x, 1)) == CONST_INT
6575 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
6576 || INTVAL (XEXP (x, 1)) < 0))
6578 rtx xop0 = XEXP (x, 0);
6579 rtx xop1 = XEXP (x, 1);
6580 HOST_WIDE_INT offset = INTVAL (xop1);
6582 /* Try and fold the offset into a biasing of the base register and
6583 then offsetting that. Don't do this when optimizing for space
6584 since it can cause too many CSEs. */
6585 if (optimize_size && offset >= 0
6586 && offset < 256 + 31 * GET_MODE_SIZE (mode))
6588 HOST_WIDE_INT delta;
6591 delta = offset - (256 - GET_MODE_SIZE (mode));
6592 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
6593 delta = 31 * GET_MODE_SIZE (mode);
6595 delta = offset & (~31 * GET_MODE_SIZE (mode));
6597 xop0 = force_operand (plus_constant (xop0, offset - delta),
6599 x = plus_constant (xop0, delta);
6601 else if (offset < 0 && offset > -256)
6602 /* Small negative offsets are best done with a subtract before the
6603 dereference, forcing these into a register normally takes two
6605 x = force_operand (x, NULL_RTX);
6608 /* For the remaining cases, force the constant into a register. */
6609 xop1 = force_reg (SImode, xop1);
6610 x = gen_rtx_PLUS (SImode, xop0, xop1);
6613 else if (GET_CODE (x) == PLUS
6614 && s_register_operand (XEXP (x, 1), SImode)
6615 && !s_register_operand (XEXP (x, 0), SImode))
6617 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
6619 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
6624 /* We need to find and carefully transform any SYMBOL and LABEL
6625 references; so go back to the original address expression. */
6626 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
6628 if (new_x != orig_x)
6636 arm_legitimize_reload_address (rtx *p,
6637 enum machine_mode mode,
6638 int opnum, int type,
6639 int ind_levels ATTRIBUTE_UNUSED)
6641 /* We must recognize output that we have already generated ourselves. */
6642 if (GET_CODE (*p) == PLUS
6643 && GET_CODE (XEXP (*p, 0)) == PLUS
6644 && GET_CODE (XEXP (XEXP (*p, 0), 0)) == REG
6645 && GET_CODE (XEXP (XEXP (*p, 0), 1)) == CONST_INT
6646 && GET_CODE (XEXP (*p, 1)) == CONST_INT)
6648 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
6649 MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
6650 VOIDmode, 0, 0, opnum, (enum reload_type) type);
6654 if (GET_CODE (*p) == PLUS
6655 && GET_CODE (XEXP (*p, 0)) == REG
6656 && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0)))
6657 /* If the base register is equivalent to a constant, let the generic
6658 code handle it. Otherwise we will run into problems if a future
6659 reload pass decides to rematerialize the constant. */
6660 && !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p, 0)))
6661 && GET_CODE (XEXP (*p, 1)) == CONST_INT)
6663 HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
6664 HOST_WIDE_INT low, high;
6666 /* Detect coprocessor load/stores. */
6667 bool coproc_p = ((TARGET_HARD_FLOAT
6668 && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
6669 && (mode == SFmode || mode == DFmode
6670 || (mode == DImode && TARGET_MAVERICK)))
6671 || (TARGET_REALLY_IWMMXT
6672 && VALID_IWMMXT_REG_MODE (mode))
6674 && (VALID_NEON_DREG_MODE (mode)
6675 || VALID_NEON_QREG_MODE (mode))));
6677 /* For some conditions, bail out when lower two bits are unaligned. */
6678 if ((val & 0x3) != 0
6679 /* Coprocessor load/store indexes are 8-bits + '00' appended. */
6681 /* For DI, and DF under soft-float: */
6682 || ((mode == DImode || mode == DFmode)
6683 /* Without ldrd, we use stm/ldm, which does not
6684 fair well with unaligned bits. */
6686 /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
6687 || TARGET_THUMB2))))
6690 /* When breaking down a [reg+index] reload address into [(reg+high)+low],
6691 of which the (reg+high) gets turned into a reload add insn,
6692 we try to decompose the index into high/low values that can often
6693 also lead to better reload CSE.
6695 ldr r0, [r2, #4100] // Offset too large
6696 ldr r1, [r2, #4104] // Offset too large
6698 is best reloaded as:
6704 which post-reload CSE can simplify in most cases to eliminate the
6705 second add instruction:
6710 The idea here is that we want to split out the bits of the constant
6711 as a mask, rather than as subtracting the maximum offset that the
6712 respective type of load/store used can handle.
6714 When encountering negative offsets, we can still utilize it even if
6715 the overall offset is positive; sometimes this may lead to an immediate
6716 that can be constructed with fewer instructions.
6718 ldr r0, [r2, #0x3FFFFC]
6720 This is best reloaded as:
6721 add t1, r2, #0x400000
6724 The trick for spotting this for a load insn with N bits of offset
6725 (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
6726 negative offset that is going to make bit N and all the bits below
6727 it become zero in the remainder part.
6729 The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
6730 to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
6731 used in most cases of ARM load/store instructions. */
6733 #define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
6734 (((VAL) & ((1 << (N)) - 1)) \
6735 ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
6740 low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
6742 /* NEON quad-word load/stores are made of two double-word accesses,
6743 so the valid index range is reduced by 8. Treat as 9-bit range if
6745 if (TARGET_NEON && VALID_NEON_QREG_MODE (mode) && low >= 1016)
6746 low = SIGN_MAG_LOW_ADDR_BITS (val, 9);
6748 else if (GET_MODE_SIZE (mode) == 8)
6751 low = (TARGET_THUMB2
6752 ? SIGN_MAG_LOW_ADDR_BITS (val, 10)
6753 : SIGN_MAG_LOW_ADDR_BITS (val, 8));
6755 /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
6756 to access doublewords. The supported load/store offsets are
6757 -8, -4, and 4, which we try to produce here. */
6758 low = ((val & 0xf) ^ 0x8) - 0x8;
6760 else if (GET_MODE_SIZE (mode) < 8)
6762 /* NEON element load/stores do not have an offset. */
6763 if (TARGET_NEON_FP16 && mode == HFmode)
6768 /* Thumb-2 has an asymmetrical index range of (-256,4096).
6769 Try the wider 12-bit range first, and re-try if the result
6771 low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
6773 low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
6777 if (mode == HImode || mode == HFmode)
6780 low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
6783 /* The storehi/movhi_bytes fallbacks can use only
6784 [-4094,+4094] of the full ldrb/strb index range. */
6785 low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
6786 if (low == 4095 || low == -4095)
6791 low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
6797 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff)
6798 ^ (unsigned HOST_WIDE_INT) 0x80000000)
6799 - (unsigned HOST_WIDE_INT) 0x80000000);
6800 /* Check for overflow or zero */
6801 if (low == 0 || high == 0 || (high + low != val))
6804 /* Reload the high part into a base reg; leave the low part
6806 *p = gen_rtx_PLUS (GET_MODE (*p),
6807 gen_rtx_PLUS (GET_MODE (*p), XEXP (*p, 0),
6810 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
6811 MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
6812 VOIDmode, 0, 0, opnum, (enum reload_type) type);
6820 thumb_legitimize_reload_address (rtx *x_p,
6821 enum machine_mode mode,
6822 int opnum, int type,
6823 int ind_levels ATTRIBUTE_UNUSED)
6827 if (GET_CODE (x) == PLUS
6828 && GET_MODE_SIZE (mode) < 4
6829 && REG_P (XEXP (x, 0))
6830 && XEXP (x, 0) == stack_pointer_rtx
6831 && GET_CODE (XEXP (x, 1)) == CONST_INT
6832 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
6837 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
6838 Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type);
6842 /* If both registers are hi-regs, then it's better to reload the
6843 entire expression rather than each register individually. That
6844 only requires one reload register rather than two. */
6845 if (GET_CODE (x) == PLUS
6846 && REG_P (XEXP (x, 0))
6847 && REG_P (XEXP (x, 1))
6848 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
6849 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
6854 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
6855 Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type);
6862 /* Test for various thread-local symbols. */
6864 /* Return TRUE if X is a thread-local symbol. */
6867 arm_tls_symbol_p (rtx x)
6869 if (! TARGET_HAVE_TLS)
6872 if (GET_CODE (x) != SYMBOL_REF)
6875 return SYMBOL_REF_TLS_MODEL (x) != 0;
6878 /* Helper for arm_tls_referenced_p. */
6881 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6883 if (GET_CODE (*x) == SYMBOL_REF)
6884 return SYMBOL_REF_TLS_MODEL (*x) != 0;
6886 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
6887 TLS offsets, not real symbol references. */
6888 if (GET_CODE (*x) == UNSPEC
6889 && XINT (*x, 1) == UNSPEC_TLS)
6895 /* Return TRUE if X contains any TLS symbol references. */
6898 arm_tls_referenced_p (rtx x)
6900 if (! TARGET_HAVE_TLS)
6903 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
6906 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
6908 On the ARM, allow any integer (invalid ones are removed later by insn
6909 patterns), nice doubles and symbol_refs which refer to the function's
6912 When generating pic allow anything. */
6915 arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
6917 /* At present, we have no support for Neon structure constants, so forbid
6918 them here. It might be possible to handle simple cases like 0 and -1
6920 if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
6923 return flag_pic || !label_mentioned_p (x);
6927 thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
6929 return (GET_CODE (x) == CONST_INT
6930 || GET_CODE (x) == CONST_DOUBLE
6931 || CONSTANT_ADDRESS_P (x)
6936 arm_legitimate_constant_p (enum machine_mode mode, rtx x)
6938 return (!arm_cannot_force_const_mem (mode, x)
6940 ? arm_legitimate_constant_p_1 (mode, x)
6941 : thumb_legitimate_constant_p (mode, x)));
6944 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6947 arm_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
6951 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
6953 split_const (x, &base, &offset);
6954 if (GET_CODE (base) == SYMBOL_REF
6955 && !offset_within_block_p (base, INTVAL (offset)))
6958 return arm_tls_referenced_p (x);
6961 #define REG_OR_SUBREG_REG(X) \
6962 (GET_CODE (X) == REG \
6963 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
6965 #define REG_OR_SUBREG_RTX(X) \
6966 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
6969 thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
6971 enum machine_mode mode = GET_MODE (x);
6985 return COSTS_N_INSNS (1);
6988 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6991 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
6998 return COSTS_N_INSNS (2) + cycles;
7000 return COSTS_N_INSNS (1) + 16;
7003 return (COSTS_N_INSNS (1)
7004 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
7005 + GET_CODE (SET_DEST (x)) == MEM));
7010 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
7012 if (thumb_shiftable_const (INTVAL (x)))
7013 return COSTS_N_INSNS (2);
7014 return COSTS_N_INSNS (3);
7016 else if ((outer == PLUS || outer == COMPARE)
7017 && INTVAL (x) < 256 && INTVAL (x) > -256)
7019 else if ((outer == IOR || outer == XOR || outer == AND)
7020 && INTVAL (x) < 256 && INTVAL (x) >= -256)
7021 return COSTS_N_INSNS (1);
7022 else if (outer == AND)
7025 /* This duplicates the tests in the andsi3 expander. */
7026 for (i = 9; i <= 31; i++)
7027 if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
7028 || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
7029 return COSTS_N_INSNS (2);
7031 else if (outer == ASHIFT || outer == ASHIFTRT
7032 || outer == LSHIFTRT)
7034 return COSTS_N_INSNS (2);
7040 return COSTS_N_INSNS (3);
7058 /* XXX another guess. */
7059 /* Memory costs quite a lot for the first word, but subsequent words
7060 load at the equivalent of a single insn each. */
7061 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
7062 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
7067 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
7073 total = mode == DImode ? COSTS_N_INSNS (1) : 0;
7074 total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code);
7080 return total + COSTS_N_INSNS (1);
7082 /* Assume a two-shift sequence. Increase the cost slightly so
7083 we prefer actual shifts over an extend operation. */
7084 return total + 1 + COSTS_N_INSNS (2);
7092 arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
7094 enum machine_mode mode = GET_MODE (x);
7095 enum rtx_code subcode;
7097 enum rtx_code code = GET_CODE (x);
7103 /* Memory costs quite a lot for the first word, but subsequent words
7104 load at the equivalent of a single insn each. */
7105 *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
7112 if (TARGET_HARD_FLOAT && mode == SFmode)
7113 *total = COSTS_N_INSNS (2);
7114 else if (TARGET_HARD_FLOAT && mode == DFmode && !TARGET_VFP_SINGLE)
7115 *total = COSTS_N_INSNS (4);
7117 *total = COSTS_N_INSNS (20);
7121 if (GET_CODE (XEXP (x, 1)) == REG)
7122 *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
7123 else if (GET_CODE (XEXP (x, 1)) != CONST_INT)
7124 *total = rtx_cost (XEXP (x, 1), code, 1, speed);
7130 *total += COSTS_N_INSNS (4);
7135 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
7136 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7139 *total += COSTS_N_INSNS (3);
7143 *total += COSTS_N_INSNS (1);
7144 /* Increase the cost of complex shifts because they aren't any faster,
7145 and reduce dual issue opportunities. */
7146 if (arm_tune_cortex_a9
7147 && outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT)
7155 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7156 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7157 && const_ok_for_arm (INTVAL (XEXP (x, 0))))
7159 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7163 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7164 && const_ok_for_arm (INTVAL (XEXP (x, 1))))
7166 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7173 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7175 if (TARGET_HARD_FLOAT
7177 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7179 *total = COSTS_N_INSNS (1);
7180 if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
7181 && arm_const_double_rtx (XEXP (x, 0)))
7183 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7187 if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
7188 && arm_const_double_rtx (XEXP (x, 1)))
7190 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7196 *total = COSTS_N_INSNS (20);
7200 *total = COSTS_N_INSNS (1);
7201 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7202 && const_ok_for_arm (INTVAL (XEXP (x, 0))))
7204 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7208 subcode = GET_CODE (XEXP (x, 1));
7209 if (subcode == ASHIFT || subcode == ASHIFTRT
7210 || subcode == LSHIFTRT
7211 || subcode == ROTATE || subcode == ROTATERT)
7213 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7214 *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, 0, speed);
7218 /* A shift as a part of RSB costs no more than RSB itself. */
7219 if (GET_CODE (XEXP (x, 0)) == MULT
7220 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7222 *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, 0, speed);
7223 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7228 && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode))
7230 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7231 *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, 0, speed);
7235 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE
7236 || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE)
7238 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
7239 if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
7240 && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM)
7241 *total += COSTS_N_INSNS (1);
7249 if (code == PLUS && arm_arch6 && mode == SImode
7250 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
7251 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
7253 *total = COSTS_N_INSNS (1);
7254 *total += rtx_cost (XEXP (XEXP (x, 0), 0), GET_CODE (XEXP (x, 0)),
7256 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7260 /* MLA: All arguments must be registers. We filter out
7261 multiplication by a power of two, so that we fall down into
7263 if (GET_CODE (XEXP (x, 0)) == MULT
7264 && !power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7266 /* The cost comes from the cost of the multiply. */
7270 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7272 if (TARGET_HARD_FLOAT
7274 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7276 *total = COSTS_N_INSNS (1);
7277 if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
7278 && arm_const_double_rtx (XEXP (x, 1)))
7280 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7287 *total = COSTS_N_INSNS (20);
7291 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE
7292 || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE)
7294 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, 1, speed);
7295 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
7296 && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM)
7297 *total += COSTS_N_INSNS (1);
7303 case AND: case XOR: case IOR:
7305 /* Normally the frame registers will be spilt into reg+const during
7306 reload, so it is a bad idea to combine them with other instructions,
7307 since then they might not be moved outside of loops. As a compromise
7308 we allow integration with ops that have a constant as their second
7310 if (REG_OR_SUBREG_REG (XEXP (x, 0))
7311 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
7312 && GET_CODE (XEXP (x, 1)) != CONST_INT)
7313 *total = COSTS_N_INSNS (1);
7317 *total += COSTS_N_INSNS (2);
7318 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7319 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
7321 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7328 *total += COSTS_N_INSNS (1);
7329 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7330 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
7332 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7335 subcode = GET_CODE (XEXP (x, 0));
7336 if (subcode == ASHIFT || subcode == ASHIFTRT
7337 || subcode == LSHIFTRT
7338 || subcode == ROTATE || subcode == ROTATERT)
7340 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7341 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7346 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7348 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7349 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7353 if (subcode == UMIN || subcode == UMAX
7354 || subcode == SMIN || subcode == SMAX)
7356 *total = COSTS_N_INSNS (3);
7363 /* This should have been handled by the CPU specific routines. */
7367 if (arm_arch3m && mode == SImode
7368 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
7369 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
7370 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
7371 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
7372 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
7373 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
7375 *total = rtx_cost (XEXP (XEXP (x, 0), 0), LSHIFTRT, 0, speed);
7378 *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */
7382 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7384 if (TARGET_HARD_FLOAT
7386 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7388 *total = COSTS_N_INSNS (1);
7391 *total = COSTS_N_INSNS (2);
7397 *total = COSTS_N_INSNS (ARM_NUM_REGS(mode));
7398 if (mode == SImode && code == NOT)
7400 subcode = GET_CODE (XEXP (x, 0));
7401 if (subcode == ASHIFT || subcode == ASHIFTRT
7402 || subcode == LSHIFTRT
7403 || subcode == ROTATE || subcode == ROTATERT
7405 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)))
7407 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7408 /* Register shifts cost an extra cycle. */
7409 if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
7410 *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1),
7419 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
7421 *total = COSTS_N_INSNS (4);
7425 operand = XEXP (x, 0);
7427 if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE
7428 || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE)
7429 && GET_CODE (XEXP (operand, 0)) == REG
7430 && REGNO (XEXP (operand, 0)) == CC_REGNUM))
7431 *total += COSTS_N_INSNS (1);
7432 *total += (rtx_cost (XEXP (x, 1), code, 1, speed)
7433 + rtx_cost (XEXP (x, 2), code, 2, speed));
7437 if (mode == SImode && XEXP (x, 1) == const0_rtx)
7439 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
7445 if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM)
7446 && mode == SImode && XEXP (x, 1) == const0_rtx)
7448 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
7454 if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM)
7455 && mode == SImode && XEXP (x, 1) == const0_rtx)
7457 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
7477 /* SCC insns. In the case where the comparison has already been
7478 performed, then they cost 2 instructions. Otherwise they need
7479 an additional comparison before them. */
7480 *total = COSTS_N_INSNS (2);
7481 if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM)
7488 if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM)
7494 *total += COSTS_N_INSNS (1);
7495 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7496 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
7498 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7502 subcode = GET_CODE (XEXP (x, 0));
7503 if (subcode == ASHIFT || subcode == ASHIFTRT
7504 || subcode == LSHIFTRT
7505 || subcode == ROTATE || subcode == ROTATERT)
7507 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7508 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7513 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7515 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7516 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7526 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
7527 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7528 || !const_ok_for_arm (INTVAL (XEXP (x, 1))))
7529 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7533 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7535 if (TARGET_HARD_FLOAT
7537 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7539 *total = COSTS_N_INSNS (1);
7542 *total = COSTS_N_INSNS (20);
7545 *total = COSTS_N_INSNS (1);
7547 *total += COSTS_N_INSNS (3);
7553 if (GET_MODE_CLASS (mode) == MODE_INT)
7555 rtx op = XEXP (x, 0);
7556 enum machine_mode opmode = GET_MODE (op);
7559 *total += COSTS_N_INSNS (1);
7561 if (opmode != SImode)
7565 /* If !arm_arch4, we use one of the extendhisi2_mem
7566 or movhi_bytes patterns for HImode. For a QImode
7567 sign extension, we first zero-extend from memory
7568 and then perform a shift sequence. */
7569 if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND))
7570 *total += COSTS_N_INSNS (2);
7573 *total += COSTS_N_INSNS (1);
7575 /* We don't have the necessary insn, so we need to perform some
7577 else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode)
7578 /* An and with constant 255. */
7579 *total += COSTS_N_INSNS (1);
7581 /* A shift sequence. Increase costs slightly to avoid
7582 combining two shifts into an extend operation. */
7583 *total += COSTS_N_INSNS (2) + 1;
7589 switch (GET_MODE (XEXP (x, 0)))
7596 *total = COSTS_N_INSNS (1);
7606 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
7610 if (const_ok_for_arm (INTVAL (x))
7611 || const_ok_for_arm (~INTVAL (x)))
7612 *total = COSTS_N_INSNS (1);
7614 *total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX,
7615 INTVAL (x), NULL_RTX,
7622 *total = COSTS_N_INSNS (3);
7626 *total = COSTS_N_INSNS (1);
7630 *total = COSTS_N_INSNS (1);
7631 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7635 if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x)
7636 && (mode == SFmode || !TARGET_VFP_SINGLE))
7637 *total = COSTS_N_INSNS (1);
7639 *total = COSTS_N_INSNS (4);
7646 /* We cost this as high as our memory costs to allow this to
7647 be hoisted from loops. */
7648 if (XINT (x, 1) == UNSPEC_PIC_UNIFIED)
7650 *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
7655 *total = COSTS_N_INSNS (4);
7660 /* Estimates the size cost of thumb1 instructions.
7661 For now most of the code is copied from thumb1_rtx_costs. We need more
7662 fine grain tuning when we have more related test cases. */
7664 thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
7666 enum machine_mode mode = GET_MODE (x);
7679 return COSTS_N_INSNS (1);
7682 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7684 /* Thumb1 mul instruction can't operate on const. We must Load it
7685 into a register first. */
7686 int const_size = thumb1_size_rtx_costs (XEXP (x, 1), CONST_INT, SET);
7687 return COSTS_N_INSNS (1) + const_size;
7689 return COSTS_N_INSNS (1);
7692 return (COSTS_N_INSNS (1)
7693 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
7694 + GET_CODE (SET_DEST (x)) == MEM));
7699 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
7700 return COSTS_N_INSNS (1);
7701 /* See split "TARGET_THUMB1 && satisfies_constraint_J". */
7702 if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
7703 return COSTS_N_INSNS (2);
7704 /* See split "TARGET_THUMB1 && satisfies_constraint_K". */
7705 if (thumb_shiftable_const (INTVAL (x)))
7706 return COSTS_N_INSNS (2);
7707 return COSTS_N_INSNS (3);
7709 else if ((outer == PLUS || outer == COMPARE)
7710 && INTVAL (x) < 256 && INTVAL (x) > -256)
7712 else if ((outer == IOR || outer == XOR || outer == AND)
7713 && INTVAL (x) < 256 && INTVAL (x) >= -256)
7714 return COSTS_N_INSNS (1);
7715 else if (outer == AND)
7718 /* This duplicates the tests in the andsi3 expander. */
7719 for (i = 9; i <= 31; i++)
7720 if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
7721 || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
7722 return COSTS_N_INSNS (2);
7724 else if (outer == ASHIFT || outer == ASHIFTRT
7725 || outer == LSHIFTRT)
7727 return COSTS_N_INSNS (2);
7733 return COSTS_N_INSNS (3);
7751 /* XXX another guess. */
7752 /* Memory costs quite a lot for the first word, but subsequent words
7753 load at the equivalent of a single insn each. */
7754 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
7755 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
7760 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
7765 /* XXX still guessing. */
7766 switch (GET_MODE (XEXP (x, 0)))
7769 return (1 + (mode == DImode ? 4 : 0)
7770 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
7773 return (4 + (mode == DImode ? 4 : 0)
7774 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
7777 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
7788 /* RTX costs when optimizing for size. */
7790 arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
7793 enum machine_mode mode = GET_MODE (x);
7796 *total = thumb1_size_rtx_costs (x, code, outer_code);
7800 /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */
7804 /* A memory access costs 1 insn if the mode is small, or the address is
7805 a single register, otherwise it costs one insn per word. */
7806 if (REG_P (XEXP (x, 0)))
7807 *total = COSTS_N_INSNS (1);
7809 && GET_CODE (XEXP (x, 0)) == PLUS
7810 && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))
7811 /* This will be split into two instructions.
7812 See arm.md:calculate_pic_address. */
7813 *total = COSTS_N_INSNS (2);
7815 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7822 /* Needs a libcall, so it costs about this. */
7823 *total = COSTS_N_INSNS (2);
7827 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
7829 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, false);
7837 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
7839 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, 0, false);
7842 else if (mode == SImode)
7844 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, false);
7845 /* Slightly disparage register shifts, but not by much. */
7846 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
7847 *total += 1 + rtx_cost (XEXP (x, 1), code, 1, false);
7851 /* Needs a libcall. */
7852 *total = COSTS_N_INSNS (2);
7856 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
7857 && (mode == SFmode || !TARGET_VFP_SINGLE))
7859 *total = COSTS_N_INSNS (1);
7865 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
7866 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
7868 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
7869 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
7870 || subcode1 == ROTATE || subcode1 == ROTATERT
7871 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
7872 || subcode1 == ASHIFTRT)
7874 /* It's just the cost of the two operands. */
7879 *total = COSTS_N_INSNS (1);
7883 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7887 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
7888 && (mode == SFmode || !TARGET_VFP_SINGLE))
7890 *total = COSTS_N_INSNS (1);
7894 /* A shift as a part of ADD costs nothing. */
7895 if (GET_CODE (XEXP (x, 0)) == MULT
7896 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7898 *total = COSTS_N_INSNS (TARGET_THUMB2 ? 2 : 1);
7899 *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, 0, false);
7900 *total += rtx_cost (XEXP (x, 1), code, 1, false);
7905 case AND: case XOR: case IOR:
7908 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
7910 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
7911 || subcode == LSHIFTRT || subcode == ASHIFTRT
7912 || (code == AND && subcode == NOT))
7914 /* It's just the cost of the two operands. */
7920 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7924 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7928 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
7929 && (mode == SFmode || !TARGET_VFP_SINGLE))
7931 *total = COSTS_N_INSNS (1);
7937 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7946 if (cc_register (XEXP (x, 0), VOIDmode))
7949 *total = COSTS_N_INSNS (1);
7953 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
7954 && (mode == SFmode || !TARGET_VFP_SINGLE))
7955 *total = COSTS_N_INSNS (1);
7957 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
7962 return arm_rtx_costs_1 (x, outer_code, total, 0);
7965 if (const_ok_for_arm (INTVAL (x)))
7966 /* A multiplication by a constant requires another instruction
7967 to load the constant to a register. */
7968 *total = COSTS_N_INSNS ((outer_code == SET || outer_code == MULT)
7970 else if (const_ok_for_arm (~INTVAL (x)))
7971 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
7972 else if (const_ok_for_arm (-INTVAL (x)))
7974 if (outer_code == COMPARE || outer_code == PLUS
7975 || outer_code == MINUS)
7978 *total = COSTS_N_INSNS (1);
7981 *total = COSTS_N_INSNS (2);
7987 *total = COSTS_N_INSNS (2);
7991 *total = COSTS_N_INSNS (4);
7996 /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
7997 cost of these slightly. */
7998 *total = COSTS_N_INSNS (1) + 1;
8005 if (mode != VOIDmode)
8006 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
8008 *total = COSTS_N_INSNS (4); /* How knows? */
8013 /* RTX costs when optimizing for size. */
8015 arm_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
8016 int *total, bool speed)
8019 return arm_size_rtx_costs (x, (enum rtx_code) code,
8020 (enum rtx_code) outer_code, total);
8022 return current_tune->rtx_costs (x, (enum rtx_code) code,
8023 (enum rtx_code) outer_code,
8027 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
8028 supported on any "slowmul" cores, so it can be ignored. */
8031 arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8032 int *total, bool speed)
8034 enum machine_mode mode = GET_MODE (x);
8038 *total = thumb1_rtx_costs (x, code, outer_code);
8045 if (GET_MODE_CLASS (mode) == MODE_FLOAT
8048 *total = COSTS_N_INSNS (20);
8052 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8054 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
8055 & (unsigned HOST_WIDE_INT) 0xffffffff);
8056 int cost, const_ok = const_ok_for_arm (i);
8057 int j, booth_unit_size;
8059 /* Tune as appropriate. */
8060 cost = const_ok ? 4 : 8;
8061 booth_unit_size = 2;
8062 for (j = 0; i && j < 32; j += booth_unit_size)
8064 i >>= booth_unit_size;
8068 *total = COSTS_N_INSNS (cost);
8069 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
8073 *total = COSTS_N_INSNS (20);
8077 return arm_rtx_costs_1 (x, outer_code, total, speed);;
8082 /* RTX cost for cores with a fast multiply unit (M variants). */
8085 arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8086 int *total, bool speed)
8088 enum machine_mode mode = GET_MODE (x);
8092 *total = thumb1_rtx_costs (x, code, outer_code);
8096 /* ??? should thumb2 use different costs? */
8100 /* There is no point basing this on the tuning, since it is always the
8101 fast variant if it exists at all. */
8103 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
8104 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8105 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
8107 *total = COSTS_N_INSNS(2);
8114 *total = COSTS_N_INSNS (5);
8118 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8120 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
8121 & (unsigned HOST_WIDE_INT) 0xffffffff);
8122 int cost, const_ok = const_ok_for_arm (i);
8123 int j, booth_unit_size;
8125 /* Tune as appropriate. */
8126 cost = const_ok ? 4 : 8;
8127 booth_unit_size = 8;
8128 for (j = 0; i && j < 32; j += booth_unit_size)
8130 i >>= booth_unit_size;
8134 *total = COSTS_N_INSNS(cost);
8140 *total = COSTS_N_INSNS (4);
8144 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
8146 if (TARGET_HARD_FLOAT
8148 || (mode == DFmode && !TARGET_VFP_SINGLE)))
8150 *total = COSTS_N_INSNS (1);
8155 /* Requires a lib call */
8156 *total = COSTS_N_INSNS (20);
8160 return arm_rtx_costs_1 (x, outer_code, total, speed);
8165 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
8166 so it can be ignored. */
8169 arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8170 int *total, bool speed)
8172 enum machine_mode mode = GET_MODE (x);
8176 *total = thumb1_rtx_costs (x, code, outer_code);
8183 if (GET_CODE (XEXP (x, 0)) != MULT)
8184 return arm_rtx_costs_1 (x, outer_code, total, speed);
8186 /* A COMPARE of a MULT is slow on XScale; the muls instruction
8187 will stall until the multiplication is complete. */
8188 *total = COSTS_N_INSNS (3);
8192 /* There is no point basing this on the tuning, since it is always the
8193 fast variant if it exists at all. */
8195 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
8196 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8197 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
8199 *total = COSTS_N_INSNS (2);
8206 *total = COSTS_N_INSNS (5);
8210 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8212 /* If operand 1 is a constant we can more accurately
8213 calculate the cost of the multiply. The multiplier can
8214 retire 15 bits on the first cycle and a further 12 on the
8215 second. We do, of course, have to load the constant into
8216 a register first. */
8217 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
8218 /* There's a general overhead of one cycle. */
8220 unsigned HOST_WIDE_INT masked_const;
8225 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
8227 masked_const = i & 0xffff8000;
8228 if (masked_const != 0)
8231 masked_const = i & 0xf8000000;
8232 if (masked_const != 0)
8235 *total = COSTS_N_INSNS (cost);
8241 *total = COSTS_N_INSNS (3);
8245 /* Requires a lib call */
8246 *total = COSTS_N_INSNS (20);
8250 return arm_rtx_costs_1 (x, outer_code, total, speed);
8255 /* RTX costs for 9e (and later) cores. */
8258 arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8259 int *total, bool speed)
8261 enum machine_mode mode = GET_MODE (x);
8268 *total = COSTS_N_INSNS (3);
8272 *total = thumb1_rtx_costs (x, code, outer_code);
8280 /* There is no point basing this on the tuning, since it is always the
8281 fast variant if it exists at all. */
8283 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
8284 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8285 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
8287 *total = COSTS_N_INSNS (2);
8294 *total = COSTS_N_INSNS (5);
8300 *total = COSTS_N_INSNS (2);
8304 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
8306 if (TARGET_HARD_FLOAT
8308 || (mode == DFmode && !TARGET_VFP_SINGLE)))
8310 *total = COSTS_N_INSNS (1);
8315 *total = COSTS_N_INSNS (20);
8319 return arm_rtx_costs_1 (x, outer_code, total, speed);
8322 /* All address computations that can be done are free, but rtx cost returns
8323 the same for practically all of them. So we weight the different types
8324 of address here in the order (most pref first):
8325 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
8327 arm_arm_address_cost (rtx x)
8329 enum rtx_code c = GET_CODE (x);
8331 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
8333 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
8338 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8341 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
8351 arm_thumb_address_cost (rtx x)
8353 enum rtx_code c = GET_CODE (x);
8358 && GET_CODE (XEXP (x, 0)) == REG
8359 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8366 arm_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8368 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
8371 /* Adjust cost hook for XScale. */
8373 xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
8375 /* Some true dependencies can have a higher cost depending
8376 on precisely how certain input operands are used. */
8377 if (REG_NOTE_KIND(link) == 0
8378 && recog_memoized (insn) >= 0
8379 && recog_memoized (dep) >= 0)
8381 int shift_opnum = get_attr_shift (insn);
8382 enum attr_type attr_type = get_attr_type (dep);
8384 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
8385 operand for INSN. If we have a shifted input operand and the
8386 instruction we depend on is another ALU instruction, then we may
8387 have to account for an additional stall. */
8388 if (shift_opnum != 0
8389 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
8391 rtx shifted_operand;
8394 /* Get the shifted operand. */
8395 extract_insn (insn);
8396 shifted_operand = recog_data.operand[shift_opnum];
8398 /* Iterate over all the operands in DEP. If we write an operand
8399 that overlaps with SHIFTED_OPERAND, then we have increase the
8400 cost of this dependency. */
8402 preprocess_constraints ();
8403 for (opno = 0; opno < recog_data.n_operands; opno++)
8405 /* We can ignore strict inputs. */
8406 if (recog_data.operand_type[opno] == OP_IN)
8409 if (reg_overlap_mentioned_p (recog_data.operand[opno],
8421 /* Adjust cost hook for Cortex A9. */
8423 cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
8425 switch (REG_NOTE_KIND (link))
8432 case REG_DEP_OUTPUT:
8433 if (recog_memoized (insn) >= 0
8434 && recog_memoized (dep) >= 0)
8436 if (GET_CODE (PATTERN (insn)) == SET)
8439 (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT
8441 (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
8443 enum attr_type attr_type_insn = get_attr_type (insn);
8444 enum attr_type attr_type_dep = get_attr_type (dep);
8446 /* By default all dependencies of the form
8449 have an extra latency of 1 cycle because
8450 of the input and output dependency in this
8451 case. However this gets modeled as an true
8452 dependency and hence all these checks. */
8453 if (REG_P (SET_DEST (PATTERN (insn)))
8454 && REG_P (SET_DEST (PATTERN (dep)))
8455 && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)),
8456 SET_DEST (PATTERN (dep))))
8458 /* FMACS is a special case where the dependant
8459 instruction can be issued 3 cycles before
8460 the normal latency in case of an output
8462 if ((attr_type_insn == TYPE_FMACS
8463 || attr_type_insn == TYPE_FMACD)
8464 && (attr_type_dep == TYPE_FMACS
8465 || attr_type_dep == TYPE_FMACD))
8467 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
8468 *cost = insn_default_latency (dep) - 3;
8470 *cost = insn_default_latency (dep);
8475 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
8476 *cost = insn_default_latency (dep) + 1;
8478 *cost = insn_default_latency (dep);
8494 /* Adjust cost hook for FA726TE. */
8496 fa726te_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
8498 /* For FA726TE, true dependency on CPSR (i.e. set cond followed by predicated)
8499 have penalty of 3. */
8500 if (REG_NOTE_KIND (link) == REG_DEP_TRUE
8501 && recog_memoized (insn) >= 0
8502 && recog_memoized (dep) >= 0
8503 && get_attr_conds (dep) == CONDS_SET)
8505 /* Use of carry (e.g. 64-bit arithmetic) in ALU: 3-cycle latency. */
8506 if (get_attr_conds (insn) == CONDS_USE
8507 && get_attr_type (insn) != TYPE_BRANCH)
8513 if (GET_CODE (PATTERN (insn)) == COND_EXEC
8514 || get_attr_conds (insn) == CONDS_USE)
8524 /* Implement TARGET_REGISTER_MOVE_COST.
8526 Moves between FPA_REGS and GENERAL_REGS are two memory insns.
8527 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
8528 it is typically more expensive than a single memory access. We set
8529 the cost to less than two memory accesses so that floating
8530 point to integer conversion does not go through memory. */
8533 arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8534 reg_class_t from, reg_class_t to)
8538 if ((from == FPA_REGS && to != FPA_REGS)
8539 || (from != FPA_REGS && to == FPA_REGS))
8541 else if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to))
8542 || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to)))
8544 else if ((from == IWMMXT_REGS && to != IWMMXT_REGS)
8545 || (from != IWMMXT_REGS && to == IWMMXT_REGS))
8547 else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS)
8549 else if ((from == CIRRUS_REGS && to != CIRRUS_REGS)
8550 || (from != CIRRUS_REGS && to == CIRRUS_REGS))
8557 if (from == HI_REGS || to == HI_REGS)
8564 /* Implement TARGET_MEMORY_MOVE_COST. */
8567 arm_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
8568 bool in ATTRIBUTE_UNUSED)
8574 if (GET_MODE_SIZE (mode) < 4)
8577 return ((2 * GET_MODE_SIZE (mode)) * (rclass == LO_REGS ? 1 : 2));
8581 /* This function implements the target macro TARGET_SCHED_ADJUST_COST.
8582 It corrects the value of COST based on the relationship between
8583 INSN and DEP through the dependence LINK. It returns the new
8584 value. There is a per-core adjust_cost hook to adjust scheduler costs
8585 and the per-core hook can choose to completely override the generic
8586 adjust_cost function. Only put bits of code into arm_adjust_cost that
8587 are common across all cores. */
8589 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
8593 /* When generating Thumb-1 code, we want to place flag-setting operations
8594 close to a conditional branch which depends on them, so that we can
8595 omit the comparison. */
8597 && REG_NOTE_KIND (link) == 0
8598 && recog_memoized (insn) == CODE_FOR_cbranchsi4_insn
8599 && recog_memoized (dep) >= 0
8600 && get_attr_conds (dep) == CONDS_SET)
8603 if (current_tune->sched_adjust_cost != NULL)
8605 if (!current_tune->sched_adjust_cost (insn, link, dep, &cost))
8609 /* XXX This is not strictly true for the FPA. */
8610 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8611 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
8614 /* Call insns don't incur a stall, even if they follow a load. */
8615 if (REG_NOTE_KIND (link) == 0
8616 && GET_CODE (insn) == CALL_INSN)
8619 if ((i_pat = single_set (insn)) != NULL
8620 && GET_CODE (SET_SRC (i_pat)) == MEM
8621 && (d_pat = single_set (dep)) != NULL
8622 && GET_CODE (SET_DEST (d_pat)) == MEM)
8624 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
8625 /* This is a load after a store, there is no conflict if the load reads
8626 from a cached area. Assume that loads from the stack, and from the
8627 constant pool are cached, and that others will miss. This is a
8630 if ((GET_CODE (src_mem) == SYMBOL_REF
8631 && CONSTANT_POOL_ADDRESS_P (src_mem))
8632 || reg_mentioned_p (stack_pointer_rtx, src_mem)
8633 || reg_mentioned_p (frame_pointer_rtx, src_mem)
8634 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
8642 arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED)
8645 return (TARGET_THUMB2 && !speed_p) ? 1 : 4;
8647 return (optimize > 0) ? 2 : 0;
8651 arm_cortex_a5_branch_cost (bool speed_p, bool predictable_p)
8653 return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
8656 static int fp_consts_inited = 0;
8658 /* Only zero is valid for VFP. Other values are also valid for FPA. */
8659 static const char * const strings_fp[8] =
8662 "4", "5", "0.5", "10"
8665 static REAL_VALUE_TYPE values_fp[8];
8668 init_fp_table (void)
8674 fp_consts_inited = 1;
8676 fp_consts_inited = 8;
8678 for (i = 0; i < fp_consts_inited; i++)
8680 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
8685 /* Return TRUE if rtx X is a valid immediate FP constant. */
8687 arm_const_double_rtx (rtx x)
8692 if (!fp_consts_inited)
8695 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8696 if (REAL_VALUE_MINUS_ZERO (r))
8699 for (i = 0; i < fp_consts_inited; i++)
8700 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8706 /* Return TRUE if rtx X is a valid immediate FPA constant. */
8708 neg_const_double_rtx_ok_for_fpa (rtx x)
8713 if (!fp_consts_inited)
8716 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8717 r = real_value_negate (&r);
8718 if (REAL_VALUE_MINUS_ZERO (r))
8721 for (i = 0; i < 8; i++)
8722 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8729 /* VFPv3 has a fairly wide range of representable immediates, formed from
8730 "quarter-precision" floating-point values. These can be evaluated using this
8731 formula (with ^ for exponentiation):
8735 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
8736 16 <= n <= 31 and 0 <= r <= 7.
8738 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
8740 - A (most-significant) is the sign bit.
8741 - BCD are the exponent (encoded as r XOR 3).
8742 - EFGH are the mantissa (encoded as n - 16).
8745 /* Return an integer index for a VFPv3 immediate operand X suitable for the
8746 fconst[sd] instruction, or -1 if X isn't suitable. */
8748 vfp3_const_double_index (rtx x)
8750 REAL_VALUE_TYPE r, m;
8752 unsigned HOST_WIDE_INT mantissa, mant_hi;
8753 unsigned HOST_WIDE_INT mask;
8754 HOST_WIDE_INT m1, m2;
8755 int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
8757 if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE)
8760 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8762 /* We can't represent these things, so detect them first. */
8763 if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r))
8766 /* Extract sign, exponent and mantissa. */
8767 sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0;
8768 r = real_value_abs (&r);
8769 exponent = REAL_EXP (&r);
8770 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
8771 highest (sign) bit, with a fixed binary point at bit point_pos.
8772 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
8773 bits for the mantissa, this may fail (low bits would be lost). */
8774 real_ldexp (&m, &r, point_pos - exponent);
8775 REAL_VALUE_TO_INT (&m1, &m2, m);
8779 /* If there are bits set in the low part of the mantissa, we can't
8780 represent this value. */
8784 /* Now make it so that mantissa contains the most-significant bits, and move
8785 the point_pos to indicate that the least-significant bits have been
8787 point_pos -= HOST_BITS_PER_WIDE_INT;
8790 /* We can permit four significant bits of mantissa only, plus a high bit
8791 which is always 1. */
8792 mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
8793 if ((mantissa & mask) != 0)
8796 /* Now we know the mantissa is in range, chop off the unneeded bits. */
8797 mantissa >>= point_pos - 5;
8799 /* The mantissa may be zero. Disallow that case. (It's possible to load the
8800 floating-point immediate zero with Neon using an integer-zero load, but
8801 that case is handled elsewhere.) */
8805 gcc_assert (mantissa >= 16 && mantissa <= 31);
8807 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
8808 normalized significands are in the range [1, 2). (Our mantissa is shifted
8809 left 4 places at this point relative to normalized IEEE754 values). GCC
8810 internally uses [0.5, 1) (see real.c), so the exponent returned from
8811 REAL_EXP must be altered. */
8812 exponent = 5 - exponent;
8814 if (exponent < 0 || exponent > 7)
8817 /* Sign, mantissa and exponent are now in the correct form to plug into the
8818 formula described in the comment above. */
8819 return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16);
8822 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
8824 vfp3_const_double_rtx (rtx x)
8829 return vfp3_const_double_index (x) != -1;
8832 /* Recognize immediates which can be used in various Neon instructions. Legal
8833 immediates are described by the following table (for VMVN variants, the
8834 bitwise inverse of the constant shown is recognized. In either case, VMOV
8835 is output and the correct instruction to use for a given constant is chosen
8836 by the assembler). The constant shown is replicated across all elements of
8837 the destination vector.
8839 insn elems variant constant (binary)
8840 ---- ----- ------- -----------------
8841 vmov i32 0 00000000 00000000 00000000 abcdefgh
8842 vmov i32 1 00000000 00000000 abcdefgh 00000000
8843 vmov i32 2 00000000 abcdefgh 00000000 00000000
8844 vmov i32 3 abcdefgh 00000000 00000000 00000000
8845 vmov i16 4 00000000 abcdefgh
8846 vmov i16 5 abcdefgh 00000000
8847 vmvn i32 6 00000000 00000000 00000000 abcdefgh
8848 vmvn i32 7 00000000 00000000 abcdefgh 00000000
8849 vmvn i32 8 00000000 abcdefgh 00000000 00000000
8850 vmvn i32 9 abcdefgh 00000000 00000000 00000000
8851 vmvn i16 10 00000000 abcdefgh
8852 vmvn i16 11 abcdefgh 00000000
8853 vmov i32 12 00000000 00000000 abcdefgh 11111111
8854 vmvn i32 13 00000000 00000000 abcdefgh 11111111
8855 vmov i32 14 00000000 abcdefgh 11111111 11111111
8856 vmvn i32 15 00000000 abcdefgh 11111111 11111111
8858 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
8859 eeeeeeee ffffffff gggggggg hhhhhhhh
8860 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
8862 For case 18, B = !b. Representable values are exactly those accepted by
8863 vfp3_const_double_index, but are output as floating-point numbers rather
8866 Variants 0-5 (inclusive) may also be used as immediates for the second
8867 operand of VORR/VBIC instructions.
8869 The INVERSE argument causes the bitwise inverse of the given operand to be
8870 recognized instead (used for recognizing legal immediates for the VAND/VORN
8871 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
8872 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
8873 output, rather than the real insns vbic/vorr).
8875 INVERSE makes no difference to the recognition of float vectors.
8877 The return value is the variant of immediate as shown in the above table, or
8878 -1 if the given value doesn't match any of the listed patterns.
8881 neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
8882 rtx *modconst, int *elementwidth)
8884 #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
8886 for (i = 0; i < idx; i += (STRIDE)) \
8891 immtype = (CLASS); \
8892 elsize = (ELSIZE); \
8896 unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op);
8897 unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
8898 unsigned char bytes[16];
8899 int immtype = -1, matches;
8900 unsigned int invmask = inverse ? 0xff : 0;
8902 /* Vectors of float constants. */
8903 if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
8905 rtx el0 = CONST_VECTOR_ELT (op, 0);
8908 if (!vfp3_const_double_rtx (el0))
8911 REAL_VALUE_FROM_CONST_DOUBLE (r0, el0);
8913 for (i = 1; i < n_elts; i++)
8915 rtx elt = CONST_VECTOR_ELT (op, i);
8918 REAL_VALUE_FROM_CONST_DOUBLE (re, elt);
8920 if (!REAL_VALUES_EQUAL (r0, re))
8925 *modconst = CONST_VECTOR_ELT (op, 0);
8933 /* Splat vector constant out into a byte vector. */
8934 for (i = 0; i < n_elts; i++)
8936 rtx el = CONST_VECTOR_ELT (op, i);
8937 unsigned HOST_WIDE_INT elpart;
8938 unsigned int part, parts;
8940 if (GET_CODE (el) == CONST_INT)
8942 elpart = INTVAL (el);
8945 else if (GET_CODE (el) == CONST_DOUBLE)
8947 elpart = CONST_DOUBLE_LOW (el);
8953 for (part = 0; part < parts; part++)
8956 for (byte = 0; byte < innersize; byte++)
8958 bytes[idx++] = (elpart & 0xff) ^ invmask;
8959 elpart >>= BITS_PER_UNIT;
8961 if (GET_CODE (el) == CONST_DOUBLE)
8962 elpart = CONST_DOUBLE_HIGH (el);
8967 gcc_assert (idx == GET_MODE_SIZE (mode));
8971 CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0
8972 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
8974 CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1]
8975 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
8977 CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0
8978 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
8980 CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0
8981 && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]);
8983 CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0);
8985 CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]);
8987 CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff
8988 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
8990 CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
8991 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
8993 CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff
8994 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
8996 CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff
8997 && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]);
8999 CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff);
9001 CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]);
9003 CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
9004 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
9006 CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1]
9007 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
9009 CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff
9010 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
9012 CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0
9013 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
9015 CHECK (1, 8, 16, bytes[i] == bytes[0]);
9017 CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff)
9018 && bytes[i] == bytes[(i + 8) % idx]);
9026 *elementwidth = elsize;
9030 unsigned HOST_WIDE_INT imm = 0;
9032 /* Un-invert bytes of recognized vector, if necessary. */
9034 for (i = 0; i < idx; i++)
9035 bytes[i] ^= invmask;
9039 /* FIXME: Broken on 32-bit H_W_I hosts. */
9040 gcc_assert (sizeof (HOST_WIDE_INT) == 8);
9042 for (i = 0; i < 8; i++)
9043 imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0)
9044 << (i * BITS_PER_UNIT);
9046 *modconst = GEN_INT (imm);
9050 unsigned HOST_WIDE_INT imm = 0;
9052 for (i = 0; i < elsize / BITS_PER_UNIT; i++)
9053 imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT);
9055 *modconst = GEN_INT (imm);
9063 /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly,
9064 VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for
9065 float elements), and a modified constant (whatever should be output for a
9066 VMOV) in *MODCONST. */
9069 neon_immediate_valid_for_move (rtx op, enum machine_mode mode,
9070 rtx *modconst, int *elementwidth)
9074 int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth);
9080 *modconst = tmpconst;
9083 *elementwidth = tmpwidth;
9088 /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
9089 the immediate is valid, write a constant suitable for using as an operand
9090 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
9091 *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */
9094 neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse,
9095 rtx *modconst, int *elementwidth)
9099 int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth);
9101 if (retval < 0 || retval > 5)
9105 *modconst = tmpconst;
9108 *elementwidth = tmpwidth;
9113 /* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction. If
9114 the immediate is valid, write a constant suitable for using as an operand
9115 to VSHR/VSHL to *MODCONST and the corresponding element width to
9116 *ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
9117 because they have different limitations. */
9120 neon_immediate_valid_for_shift (rtx op, enum machine_mode mode,
9121 rtx *modconst, int *elementwidth,
9124 unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
9125 unsigned int n_elts = CONST_VECTOR_NUNITS (op), i;
9126 unsigned HOST_WIDE_INT last_elt = 0;
9127 unsigned HOST_WIDE_INT maxshift;
9129 /* Split vector constant out into a byte vector. */
9130 for (i = 0; i < n_elts; i++)
9132 rtx el = CONST_VECTOR_ELT (op, i);
9133 unsigned HOST_WIDE_INT elpart;
9135 if (GET_CODE (el) == CONST_INT)
9136 elpart = INTVAL (el);
9137 else if (GET_CODE (el) == CONST_DOUBLE)
9142 if (i != 0 && elpart != last_elt)
9148 /* Shift less than element size. */
9149 maxshift = innersize * 8;
9153 /* Left shift immediate value can be from 0 to <size>-1. */
9154 if (last_elt >= maxshift)
9159 /* Right shift immediate value can be from 1 to <size>. */
9160 if (last_elt == 0 || last_elt > maxshift)
9165 *elementwidth = innersize * 8;
9168 *modconst = CONST_VECTOR_ELT (op, 0);
9173 /* Return a string suitable for output of Neon immediate logic operation
9177 neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode,
9178 int inverse, int quad)
9180 int width, is_valid;
9181 static char templ[40];
9183 is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width);
9185 gcc_assert (is_valid != 0);
9188 sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width);
9190 sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width);
9195 /* Return a string suitable for output of Neon immediate shift operation
9196 (VSHR or VSHL) MNEM. */
9199 neon_output_shift_immediate (const char *mnem, char sign, rtx *op2,
9200 enum machine_mode mode, int quad,
9203 int width, is_valid;
9204 static char templ[40];
9206 is_valid = neon_immediate_valid_for_shift (*op2, mode, op2, &width, isleftshift);
9207 gcc_assert (is_valid != 0);
9210 sprintf (templ, "%s.%c%d\t%%q0, %%q1, %%2", mnem, sign, width);
9212 sprintf (templ, "%s.%c%d\t%%P0, %%P1, %%2", mnem, sign, width);
9217 /* Output a sequence of pairwise operations to implement a reduction.
9218 NOTE: We do "too much work" here, because pairwise operations work on two
9219 registers-worth of operands in one go. Unfortunately we can't exploit those
9220 extra calculations to do the full operation in fewer steps, I don't think.
9221 Although all vector elements of the result but the first are ignored, we
9222 actually calculate the same result in each of the elements. An alternative
9223 such as initially loading a vector with zero to use as each of the second
9224 operands would use up an additional register and take an extra instruction,
9225 for no particular gain. */
9228 neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
9229 rtx (*reduc) (rtx, rtx, rtx))
9231 enum machine_mode inner = GET_MODE_INNER (mode);
9232 unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner);
9235 for (i = parts / 2; i >= 1; i /= 2)
9237 rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode);
9238 emit_insn (reduc (dest, tmpsum, tmpsum));
9243 /* If VALS is a vector constant that can be loaded into a register
9244 using VDUP, generate instructions to do so and return an RTX to
9245 assign to the register. Otherwise return NULL_RTX. */
9248 neon_vdup_constant (rtx vals)
9250 enum machine_mode mode = GET_MODE (vals);
9251 enum machine_mode inner_mode = GET_MODE_INNER (mode);
9252 int n_elts = GET_MODE_NUNITS (mode);
9253 bool all_same = true;
9257 if (GET_CODE (vals) != CONST_VECTOR || GET_MODE_SIZE (inner_mode) > 4)
9260 for (i = 0; i < n_elts; ++i)
9262 x = XVECEXP (vals, 0, i);
9263 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
9268 /* The elements are not all the same. We could handle repeating
9269 patterns of a mode larger than INNER_MODE here (e.g. int8x8_t
9270 {0, C, 0, C, 0, C, 0, C} which can be loaded using
9274 /* We can load this constant by using VDUP and a constant in a
9275 single ARM register. This will be cheaper than a vector
9278 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
9279 return gen_rtx_VEC_DUPLICATE (mode, x);
9282 /* Generate code to load VALS, which is a PARALLEL containing only
9283 constants (for vec_init) or CONST_VECTOR, efficiently into a
9284 register. Returns an RTX to copy into the register, or NULL_RTX
9285 for a PARALLEL that can not be converted into a CONST_VECTOR. */
9288 neon_make_constant (rtx vals)
9290 enum machine_mode mode = GET_MODE (vals);
9292 rtx const_vec = NULL_RTX;
9293 int n_elts = GET_MODE_NUNITS (mode);
9297 if (GET_CODE (vals) == CONST_VECTOR)
9299 else if (GET_CODE (vals) == PARALLEL)
9301 /* A CONST_VECTOR must contain only CONST_INTs and
9302 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
9303 Only store valid constants in a CONST_VECTOR. */
9304 for (i = 0; i < n_elts; ++i)
9306 rtx x = XVECEXP (vals, 0, i);
9307 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
9310 if (n_const == n_elts)
9311 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
9316 if (const_vec != NULL
9317 && neon_immediate_valid_for_move (const_vec, mode, NULL, NULL))
9318 /* Load using VMOV. On Cortex-A8 this takes one cycle. */
9320 else if ((target = neon_vdup_constant (vals)) != NULL_RTX)
9321 /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON
9322 pipeline cycle; creating the constant takes one or two ARM
9325 else if (const_vec != NULL_RTX)
9326 /* Load from constant pool. On Cortex-A8 this takes two cycles
9327 (for either double or quad vectors). We can not take advantage
9328 of single-cycle VLD1 because we need a PC-relative addressing
9332 /* A PARALLEL containing something not valid inside CONST_VECTOR.
9333 We can not construct an initializer. */
9337 /* Initialize vector TARGET to VALS. */
9340 neon_expand_vector_init (rtx target, rtx vals)
9342 enum machine_mode mode = GET_MODE (target);
9343 enum machine_mode inner_mode = GET_MODE_INNER (mode);
9344 int n_elts = GET_MODE_NUNITS (mode);
9345 int n_var = 0, one_var = -1;
9346 bool all_same = true;
9350 for (i = 0; i < n_elts; ++i)
9352 x = XVECEXP (vals, 0, i);
9353 if (!CONSTANT_P (x))
9354 ++n_var, one_var = i;
9356 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
9362 rtx constant = neon_make_constant (vals);
9363 if (constant != NULL_RTX)
9365 emit_move_insn (target, constant);
9370 /* Splat a single non-constant element if we can. */
9371 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
9373 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
9374 emit_insn (gen_rtx_SET (VOIDmode, target,
9375 gen_rtx_VEC_DUPLICATE (mode, x)));
9379 /* One field is non-constant. Load constant then overwrite varying
9380 field. This is more efficient than using the stack. */
9383 rtx copy = copy_rtx (vals);
9384 rtx index = GEN_INT (one_var);
9386 /* Load constant part of vector, substitute neighboring value for
9388 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
9389 neon_expand_vector_init (target, copy);
9391 /* Insert variable. */
9392 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
9396 emit_insn (gen_neon_vset_lanev8qi (target, x, target, index));
9399 emit_insn (gen_neon_vset_lanev16qi (target, x, target, index));
9402 emit_insn (gen_neon_vset_lanev4hi (target, x, target, index));
9405 emit_insn (gen_neon_vset_lanev8hi (target, x, target, index));
9408 emit_insn (gen_neon_vset_lanev2si (target, x, target, index));
9411 emit_insn (gen_neon_vset_lanev4si (target, x, target, index));
9414 emit_insn (gen_neon_vset_lanev2sf (target, x, target, index));
9417 emit_insn (gen_neon_vset_lanev4sf (target, x, target, index));
9420 emit_insn (gen_neon_vset_lanev2di (target, x, target, index));
9428 /* Construct the vector in memory one field at a time
9429 and load the whole vector. */
9430 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
9431 for (i = 0; i < n_elts; i++)
9432 emit_move_insn (adjust_address_nv (mem, inner_mode,
9433 i * GET_MODE_SIZE (inner_mode)),
9434 XVECEXP (vals, 0, i));
9435 emit_move_insn (target, mem);
9438 /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise
9439 ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so
9440 reported source locations are bogus. */
9443 bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
9448 gcc_assert (GET_CODE (operand) == CONST_INT);
9450 lane = INTVAL (operand);
9452 if (lane < low || lane >= high)
9456 /* Bounds-check lanes. */
9459 neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
9461 bounds_check (operand, low, high, "lane out of range");
9464 /* Bounds-check constants. */
9467 neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
9469 bounds_check (operand, low, high, "constant out of range");
9473 neon_element_bits (enum machine_mode mode)
9476 return GET_MODE_BITSIZE (mode);
9478 return GET_MODE_BITSIZE (GET_MODE_INNER (mode));
9482 /* Predicates for `match_operand' and `match_operator'. */
9484 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
9486 cirrus_memory_offset (rtx op)
9488 /* Reject eliminable registers. */
9489 if (! (reload_in_progress || reload_completed)
9490 && ( reg_mentioned_p (frame_pointer_rtx, op)
9491 || reg_mentioned_p (arg_pointer_rtx, op)
9492 || reg_mentioned_p (virtual_incoming_args_rtx, op)
9493 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
9494 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
9495 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
9498 if (GET_CODE (op) == MEM)
9504 /* Match: (mem (reg)). */
9505 if (GET_CODE (ind) == REG)
9511 if (GET_CODE (ind) == PLUS
9512 && GET_CODE (XEXP (ind, 0)) == REG
9513 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
9514 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
9521 /* Return TRUE if OP is a valid coprocessor memory address pattern.
9522 WB is true if full writeback address modes are allowed and is false
9523 if limited writeback address modes (POST_INC and PRE_DEC) are
9527 arm_coproc_mem_operand (rtx op, bool wb)
9531 /* Reject eliminable registers. */
9532 if (! (reload_in_progress || reload_completed)
9533 && ( reg_mentioned_p (frame_pointer_rtx, op)
9534 || reg_mentioned_p (arg_pointer_rtx, op)
9535 || reg_mentioned_p (virtual_incoming_args_rtx, op)
9536 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
9537 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
9538 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
9541 /* Constants are converted into offsets from labels. */
9542 if (GET_CODE (op) != MEM)
9547 if (reload_completed
9548 && (GET_CODE (ind) == LABEL_REF
9549 || (GET_CODE (ind) == CONST
9550 && GET_CODE (XEXP (ind, 0)) == PLUS
9551 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
9552 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
9555 /* Match: (mem (reg)). */
9556 if (GET_CODE (ind) == REG)
9557 return arm_address_register_rtx_p (ind, 0);
9559 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
9560 acceptable in any case (subject to verification by
9561 arm_address_register_rtx_p). We need WB to be true to accept
9562 PRE_INC and POST_DEC. */
9563 if (GET_CODE (ind) == POST_INC
9564 || GET_CODE (ind) == PRE_DEC
9566 && (GET_CODE (ind) == PRE_INC
9567 || GET_CODE (ind) == POST_DEC)))
9568 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
9571 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
9572 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
9573 && GET_CODE (XEXP (ind, 1)) == PLUS
9574 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
9575 ind = XEXP (ind, 1);
9580 if (GET_CODE (ind) == PLUS
9581 && GET_CODE (XEXP (ind, 0)) == REG
9582 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
9583 && GET_CODE (XEXP (ind, 1)) == CONST_INT
9584 && INTVAL (XEXP (ind, 1)) > -1024
9585 && INTVAL (XEXP (ind, 1)) < 1024
9586 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
9592 /* Return TRUE if OP is a memory operand which we can load or store a vector
9593 to/from. TYPE is one of the following values:
9594 0 - Vector load/stor (vldr)
9595 1 - Core registers (ldm)
9596 2 - Element/structure loads (vld1)
9599 neon_vector_mem_operand (rtx op, int type)
9603 /* Reject eliminable registers. */
9604 if (! (reload_in_progress || reload_completed)
9605 && ( reg_mentioned_p (frame_pointer_rtx, op)
9606 || reg_mentioned_p (arg_pointer_rtx, op)
9607 || reg_mentioned_p (virtual_incoming_args_rtx, op)
9608 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
9609 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
9610 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
9613 /* Constants are converted into offsets from labels. */
9614 if (GET_CODE (op) != MEM)
9619 if (reload_completed
9620 && (GET_CODE (ind) == LABEL_REF
9621 || (GET_CODE (ind) == CONST
9622 && GET_CODE (XEXP (ind, 0)) == PLUS
9623 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
9624 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
9627 /* Match: (mem (reg)). */
9628 if (GET_CODE (ind) == REG)
9629 return arm_address_register_rtx_p (ind, 0);
9631 /* Allow post-increment with Neon registers. */
9632 if ((type != 1 && GET_CODE (ind) == POST_INC)
9633 || (type == 0 && GET_CODE (ind) == PRE_DEC))
9634 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
9636 /* FIXME: vld1 allows register post-modify. */
9642 && GET_CODE (ind) == PLUS
9643 && GET_CODE (XEXP (ind, 0)) == REG
9644 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
9645 && GET_CODE (XEXP (ind, 1)) == CONST_INT
9646 && INTVAL (XEXP (ind, 1)) > -1024
9647 && INTVAL (XEXP (ind, 1)) < 1016
9648 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
9654 /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
9657 neon_struct_mem_operand (rtx op)
9661 /* Reject eliminable registers. */
9662 if (! (reload_in_progress || reload_completed)
9663 && ( reg_mentioned_p (frame_pointer_rtx, op)
9664 || reg_mentioned_p (arg_pointer_rtx, op)
9665 || reg_mentioned_p (virtual_incoming_args_rtx, op)
9666 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
9667 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
9668 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
9671 /* Constants are converted into offsets from labels. */
9672 if (GET_CODE (op) != MEM)
9677 if (reload_completed
9678 && (GET_CODE (ind) == LABEL_REF
9679 || (GET_CODE (ind) == CONST
9680 && GET_CODE (XEXP (ind, 0)) == PLUS
9681 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
9682 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
9685 /* Match: (mem (reg)). */
9686 if (GET_CODE (ind) == REG)
9687 return arm_address_register_rtx_p (ind, 0);
9689 /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
9690 if (GET_CODE (ind) == POST_INC
9691 || GET_CODE (ind) == PRE_DEC)
9692 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
9697 /* Return true if X is a register that will be eliminated later on. */
9699 arm_eliminable_register (rtx x)
9701 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
9702 || REGNO (x) == ARG_POINTER_REGNUM
9703 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
9704 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
9707 /* Return GENERAL_REGS if a scratch register required to reload x to/from
9708 coprocessor registers. Otherwise return NO_REGS. */
9711 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
9715 if (!TARGET_NEON_FP16)
9716 return GENERAL_REGS;
9717 if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2))
9719 return GENERAL_REGS;
9722 /* The neon move patterns handle all legitimate vector and struct
9725 && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
9726 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
9727 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
9728 || VALID_NEON_STRUCT_MODE (mode)))
9731 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
9734 return GENERAL_REGS;
9737 /* Values which must be returned in the most-significant end of the return
9741 arm_return_in_msb (const_tree valtype)
9743 return (TARGET_AAPCS_BASED
9745 && (AGGREGATE_TYPE_P (valtype)
9746 || TREE_CODE (valtype) == COMPLEX_TYPE
9747 || FIXED_POINT_TYPE_P (valtype)));
9750 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
9751 Use by the Cirrus Maverick code which has to workaround
9752 a hardware bug triggered by such instructions. */
9754 arm_memory_load_p (rtx insn)
9756 rtx body, lhs, rhs;;
9758 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
9761 body = PATTERN (insn);
9763 if (GET_CODE (body) != SET)
9766 lhs = XEXP (body, 0);
9767 rhs = XEXP (body, 1);
9769 lhs = REG_OR_SUBREG_RTX (lhs);
9771 /* If the destination is not a general purpose
9772 register we do not have to worry. */
9773 if (GET_CODE (lhs) != REG
9774 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
9777 /* As well as loads from memory we also have to react
9778 to loads of invalid constants which will be turned
9779 into loads from the minipool. */
9780 return (GET_CODE (rhs) == MEM
9781 || GET_CODE (rhs) == SYMBOL_REF
9782 || note_invalid_constants (insn, -1, false));
9785 /* Return TRUE if INSN is a Cirrus instruction. */
9787 arm_cirrus_insn_p (rtx insn)
9789 enum attr_cirrus attr;
9791 /* get_attr cannot accept USE or CLOBBER. */
9793 || GET_CODE (insn) != INSN
9794 || GET_CODE (PATTERN (insn)) == USE
9795 || GET_CODE (PATTERN (insn)) == CLOBBER)
9798 attr = get_attr_cirrus (insn);
9800 return attr != CIRRUS_NOT;
9803 /* Cirrus reorg for invalid instruction combinations. */
9805 cirrus_reorg (rtx first)
9807 enum attr_cirrus attr;
9808 rtx body = PATTERN (first);
9812 /* Any branch must be followed by 2 non Cirrus instructions. */
9813 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
9816 t = next_nonnote_insn (first);
9818 if (arm_cirrus_insn_p (t))
9821 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
9825 emit_insn_after (gen_nop (), first);
9830 /* (float (blah)) is in parallel with a clobber. */
9831 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
9832 body = XVECEXP (body, 0, 0);
9834 if (GET_CODE (body) == SET)
9836 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
9838 /* cfldrd, cfldr64, cfstrd, cfstr64 must
9839 be followed by a non Cirrus insn. */
9840 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
9842 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
9843 emit_insn_after (gen_nop (), first);
9847 else if (arm_memory_load_p (first))
9849 unsigned int arm_regno;
9851 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
9852 ldr/cfmv64hr combination where the Rd field is the same
9853 in both instructions must be split with a non Cirrus
9860 /* Get Arm register number for ldr insn. */
9861 if (GET_CODE (lhs) == REG)
9862 arm_regno = REGNO (lhs);
9865 gcc_assert (GET_CODE (rhs) == REG);
9866 arm_regno = REGNO (rhs);
9870 first = next_nonnote_insn (first);
9872 if (! arm_cirrus_insn_p (first))
9875 body = PATTERN (first);
9877 /* (float (blah)) is in parallel with a clobber. */
9878 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
9879 body = XVECEXP (body, 0, 0);
9881 if (GET_CODE (body) == FLOAT)
9882 body = XEXP (body, 0);
9884 if (get_attr_cirrus (first) == CIRRUS_MOVE
9885 && GET_CODE (XEXP (body, 1)) == REG
9886 && arm_regno == REGNO (XEXP (body, 1)))
9887 emit_insn_after (gen_nop (), first);
9893 /* get_attr cannot accept USE or CLOBBER. */
9895 || GET_CODE (first) != INSN
9896 || GET_CODE (PATTERN (first)) == USE
9897 || GET_CODE (PATTERN (first)) == CLOBBER)
9900 attr = get_attr_cirrus (first);
9902 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
9903 must be followed by a non-coprocessor instruction. */
9904 if (attr == CIRRUS_COMPARE)
9908 t = next_nonnote_insn (first);
9910 if (arm_cirrus_insn_p (t))
9913 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
9917 emit_insn_after (gen_nop (), first);
9923 /* Return TRUE if X references a SYMBOL_REF. */
9925 symbol_mentioned_p (rtx x)
9930 if (GET_CODE (x) == SYMBOL_REF)
9933 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
9934 are constant offsets, not symbols. */
9935 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
9938 fmt = GET_RTX_FORMAT (GET_CODE (x));
9940 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9946 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9947 if (symbol_mentioned_p (XVECEXP (x, i, j)))
9950 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
9957 /* Return TRUE if X references a LABEL_REF. */
9959 label_mentioned_p (rtx x)
9964 if (GET_CODE (x) == LABEL_REF)
9967 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
9968 instruction, but they are constant offsets, not symbols. */
9969 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
9972 fmt = GET_RTX_FORMAT (GET_CODE (x));
9973 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9979 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9980 if (label_mentioned_p (XVECEXP (x, i, j)))
9983 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
9991 tls_mentioned_p (rtx x)
9993 switch (GET_CODE (x))
9996 return tls_mentioned_p (XEXP (x, 0));
9999 if (XINT (x, 1) == UNSPEC_TLS)
10007 /* Must not copy any rtx that uses a pc-relative address. */
10010 arm_note_pic_base (rtx *x, void *date ATTRIBUTE_UNUSED)
10012 if (GET_CODE (*x) == UNSPEC
10013 && (XINT (*x, 1) == UNSPEC_PIC_BASE
10014 || XINT (*x, 1) == UNSPEC_PIC_UNIFIED))
10020 arm_cannot_copy_insn_p (rtx insn)
10022 /* The tls call insn cannot be copied, as it is paired with a data
10024 if (recog_memoized (insn) == CODE_FOR_tlscall)
10027 return for_each_rtx (&PATTERN (insn), arm_note_pic_base, NULL);
10031 minmax_code (rtx x)
10033 enum rtx_code code = GET_CODE (x);
10046 gcc_unreachable ();
10050 /* Return 1 if memory locations are adjacent. */
10052 adjacent_mem_locations (rtx a, rtx b)
10054 /* We don't guarantee to preserve the order of these memory refs. */
10055 if (volatile_refs_p (a) || volatile_refs_p (b))
10058 if ((GET_CODE (XEXP (a, 0)) == REG
10059 || (GET_CODE (XEXP (a, 0)) == PLUS
10060 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
10061 && (GET_CODE (XEXP (b, 0)) == REG
10062 || (GET_CODE (XEXP (b, 0)) == PLUS
10063 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
10065 HOST_WIDE_INT val0 = 0, val1 = 0;
10069 if (GET_CODE (XEXP (a, 0)) == PLUS)
10071 reg0 = XEXP (XEXP (a, 0), 0);
10072 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
10075 reg0 = XEXP (a, 0);
10077 if (GET_CODE (XEXP (b, 0)) == PLUS)
10079 reg1 = XEXP (XEXP (b, 0), 0);
10080 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
10083 reg1 = XEXP (b, 0);
10085 /* Don't accept any offset that will require multiple
10086 instructions to handle, since this would cause the
10087 arith_adjacentmem pattern to output an overlong sequence. */
10088 if (!const_ok_for_op (val0, PLUS) || !const_ok_for_op (val1, PLUS))
10091 /* Don't allow an eliminable register: register elimination can make
10092 the offset too large. */
10093 if (arm_eliminable_register (reg0))
10096 val_diff = val1 - val0;
10100 /* If the target has load delay slots, then there's no benefit
10101 to using an ldm instruction unless the offset is zero and
10102 we are optimizing for size. */
10103 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
10104 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
10105 && (val_diff == 4 || val_diff == -4));
10108 return ((REGNO (reg0) == REGNO (reg1))
10109 && (val_diff == 4 || val_diff == -4));
10115 /* Return true iff it would be profitable to turn a sequence of NOPS loads
10116 or stores (depending on IS_STORE) into a load-multiple or store-multiple
10117 instruction. ADD_OFFSET is nonzero if the base address register needs
10118 to be modified with an add instruction before we can use it. */
10121 multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED,
10122 int nops, HOST_WIDE_INT add_offset)
10124 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
10125 if the offset isn't small enough. The reason 2 ldrs are faster
10126 is because these ARMs are able to do more than one cache access
10127 in a single cycle. The ARM9 and StrongARM have Harvard caches,
10128 whilst the ARM8 has a double bandwidth cache. This means that
10129 these cores can do both an instruction fetch and a data fetch in
10130 a single cycle, so the trick of calculating the address into a
10131 scratch register (one of the result regs) and then doing a load
10132 multiple actually becomes slower (and no smaller in code size).
10133 That is the transformation
10135 ldr rd1, [rbase + offset]
10136 ldr rd2, [rbase + offset + 4]
10140 add rd1, rbase, offset
10141 ldmia rd1, {rd1, rd2}
10143 produces worse code -- '3 cycles + any stalls on rd2' instead of
10144 '2 cycles + any stalls on rd2'. On ARMs with only one cache
10145 access per cycle, the first sequence could never complete in less
10146 than 6 cycles, whereas the ldm sequence would only take 5 and
10147 would make better use of sequential accesses if not hitting the
10150 We cheat here and test 'arm_ld_sched' which we currently know to
10151 only be true for the ARM8, ARM9 and StrongARM. If this ever
10152 changes, then the test below needs to be reworked. */
10153 if (nops == 2 && arm_ld_sched && add_offset != 0)
10156 /* XScale has load-store double instructions, but they have stricter
10157 alignment requirements than load-store multiple, so we cannot
10160 For XScale ldm requires 2 + NREGS cycles to complete and blocks
10161 the pipeline until completion.
10169 An ldr instruction takes 1-3 cycles, but does not block the
10178 Best case ldr will always win. However, the more ldr instructions
10179 we issue, the less likely we are to be able to schedule them well.
10180 Using ldr instructions also increases code size.
10182 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
10183 for counts of 3 or 4 regs. */
10184 if (nops <= 2 && arm_tune_xscale && !optimize_size)
10189 /* Subroutine of load_multiple_sequence and store_multiple_sequence.
10190 Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
10191 an array ORDER which describes the sequence to use when accessing the
10192 offsets that produces an ascending order. In this sequence, each
10193 offset must be larger by exactly 4 than the previous one. ORDER[0]
10194 must have been filled in with the lowest offset by the caller.
10195 If UNSORTED_REGS is nonnull, it is an array of register numbers that
10196 we use to verify that ORDER produces an ascending order of registers.
10197 Return true if it was possible to construct such an order, false if
10201 compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order,
10202 int *unsorted_regs)
10205 for (i = 1; i < nops; i++)
10209 order[i] = order[i - 1];
10210 for (j = 0; j < nops; j++)
10211 if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4)
10213 /* We must find exactly one offset that is higher than the
10214 previous one by 4. */
10215 if (order[i] != order[i - 1])
10219 if (order[i] == order[i - 1])
10221 /* The register numbers must be ascending. */
10222 if (unsorted_regs != NULL
10223 && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]])
10229 /* Used to determine in a peephole whether a sequence of load
10230 instructions can be changed into a load-multiple instruction.
10231 NOPS is the number of separate load instructions we are examining. The
10232 first NOPS entries in OPERANDS are the destination registers, the
10233 next NOPS entries are memory operands. If this function is
10234 successful, *BASE is set to the common base register of the memory
10235 accesses; *LOAD_OFFSET is set to the first memory location's offset
10236 from that base register.
10237 REGS is an array filled in with the destination register numbers.
10238 SAVED_ORDER (if nonnull), is an array filled in with an order that maps
10239 insn numbers to an ascending order of stores. If CHECK_REGS is true,
10240 the sequence of registers in REGS matches the loads from ascending memory
10241 locations, and the function verifies that the register numbers are
10242 themselves ascending. If CHECK_REGS is false, the register numbers
10243 are stored in the order they are found in the operands. */
10245 load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
10246 int *base, HOST_WIDE_INT *load_offset, bool check_regs)
10248 int unsorted_regs[MAX_LDM_STM_OPS];
10249 HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
10250 int order[MAX_LDM_STM_OPS];
10251 rtx base_reg_rtx = NULL;
10255 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
10256 easily extended if required. */
10257 gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
10259 memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
10261 /* Loop over the operands and check that the memory references are
10262 suitable (i.e. immediate offsets from the same base register). At
10263 the same time, extract the target register, and the memory
10265 for (i = 0; i < nops; i++)
10270 /* Convert a subreg of a mem into the mem itself. */
10271 if (GET_CODE (operands[nops + i]) == SUBREG)
10272 operands[nops + i] = alter_subreg (operands + (nops + i));
10274 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
10276 /* Don't reorder volatile memory references; it doesn't seem worth
10277 looking for the case where the order is ok anyway. */
10278 if (MEM_VOLATILE_P (operands[nops + i]))
10281 offset = const0_rtx;
10283 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
10284 || (GET_CODE (reg) == SUBREG
10285 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
10286 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
10287 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
10289 || (GET_CODE (reg) == SUBREG
10290 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
10291 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
10296 base_reg = REGNO (reg);
10297 base_reg_rtx = reg;
10298 if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
10301 else if (base_reg != (int) REGNO (reg))
10302 /* Not addressed from the same base register. */
10305 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
10306 ? REGNO (operands[i])
10307 : REGNO (SUBREG_REG (operands[i])));
10309 /* If it isn't an integer register, or if it overwrites the
10310 base register but isn't the last insn in the list, then
10311 we can't do this. */
10312 if (unsorted_regs[i] < 0
10313 || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
10314 || unsorted_regs[i] > 14
10315 || (i != nops - 1 && unsorted_regs[i] == base_reg))
10318 unsorted_offsets[i] = INTVAL (offset);
10319 if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
10323 /* Not a suitable memory address. */
10327 /* All the useful information has now been extracted from the
10328 operands into unsorted_regs and unsorted_offsets; additionally,
10329 order[0] has been set to the lowest offset in the list. Sort
10330 the offsets into order, verifying that they are adjacent, and
10331 check that the register numbers are ascending. */
10332 if (!compute_offset_order (nops, unsorted_offsets, order,
10333 check_regs ? unsorted_regs : NULL))
10337 memcpy (saved_order, order, sizeof order);
10343 for (i = 0; i < nops; i++)
10344 regs[i] = unsorted_regs[check_regs ? order[i] : i];
10346 *load_offset = unsorted_offsets[order[0]];
10350 && !peep2_reg_dead_p (nops, base_reg_rtx))
10353 if (unsorted_offsets[order[0]] == 0)
10354 ldm_case = 1; /* ldmia */
10355 else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
10356 ldm_case = 2; /* ldmib */
10357 else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
10358 ldm_case = 3; /* ldmda */
10359 else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
10360 ldm_case = 4; /* ldmdb */
10361 else if (const_ok_for_arm (unsorted_offsets[order[0]])
10362 || const_ok_for_arm (-unsorted_offsets[order[0]]))
10367 if (!multiple_operation_profitable_p (false, nops,
10369 ? unsorted_offsets[order[0]] : 0))
10375 /* Used to determine in a peephole whether a sequence of store instructions can
10376 be changed into a store-multiple instruction.
10377 NOPS is the number of separate store instructions we are examining.
10378 NOPS_TOTAL is the total number of instructions recognized by the peephole
10380 The first NOPS entries in OPERANDS are the source registers, the next
10381 NOPS entries are memory operands. If this function is successful, *BASE is
10382 set to the common base register of the memory accesses; *LOAD_OFFSET is set
10383 to the first memory location's offset from that base register. REGS is an
10384 array filled in with the source register numbers, REG_RTXS (if nonnull) is
10385 likewise filled with the corresponding rtx's.
10386 SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn
10387 numbers to an ascending order of stores.
10388 If CHECK_REGS is true, the sequence of registers in *REGS matches the stores
10389 from ascending memory locations, and the function verifies that the register
10390 numbers are themselves ascending. If CHECK_REGS is false, the register
10391 numbers are stored in the order they are found in the operands. */
10393 store_multiple_sequence (rtx *operands, int nops, int nops_total,
10394 int *regs, rtx *reg_rtxs, int *saved_order, int *base,
10395 HOST_WIDE_INT *load_offset, bool check_regs)
10397 int unsorted_regs[MAX_LDM_STM_OPS];
10398 rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS];
10399 HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
10400 int order[MAX_LDM_STM_OPS];
10402 rtx base_reg_rtx = NULL;
10405 /* Write back of base register is currently only supported for Thumb 1. */
10406 int base_writeback = TARGET_THUMB1;
10408 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
10409 easily extended if required. */
10410 gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
10412 memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
10414 /* Loop over the operands and check that the memory references are
10415 suitable (i.e. immediate offsets from the same base register). At
10416 the same time, extract the target register, and the memory
10418 for (i = 0; i < nops; i++)
10423 /* Convert a subreg of a mem into the mem itself. */
10424 if (GET_CODE (operands[nops + i]) == SUBREG)
10425 operands[nops + i] = alter_subreg (operands + (nops + i));
10427 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
10429 /* Don't reorder volatile memory references; it doesn't seem worth
10430 looking for the case where the order is ok anyway. */
10431 if (MEM_VOLATILE_P (operands[nops + i]))
10434 offset = const0_rtx;
10436 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
10437 || (GET_CODE (reg) == SUBREG
10438 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
10439 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
10440 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
10442 || (GET_CODE (reg) == SUBREG
10443 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
10444 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
10447 unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG
10448 ? operands[i] : SUBREG_REG (operands[i]));
10449 unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]);
10453 base_reg = REGNO (reg);
10454 base_reg_rtx = reg;
10455 if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
10458 else if (base_reg != (int) REGNO (reg))
10459 /* Not addressed from the same base register. */
10462 /* If it isn't an integer register, then we can't do this. */
10463 if (unsorted_regs[i] < 0
10464 || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
10465 /* The effects are unpredictable if the base register is
10466 both updated and stored. */
10467 || (base_writeback && unsorted_regs[i] == base_reg)
10468 || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM)
10469 || unsorted_regs[i] > 14)
10472 unsorted_offsets[i] = INTVAL (offset);
10473 if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
10477 /* Not a suitable memory address. */
10481 /* All the useful information has now been extracted from the
10482 operands into unsorted_regs and unsorted_offsets; additionally,
10483 order[0] has been set to the lowest offset in the list. Sort
10484 the offsets into order, verifying that they are adjacent, and
10485 check that the register numbers are ascending. */
10486 if (!compute_offset_order (nops, unsorted_offsets, order,
10487 check_regs ? unsorted_regs : NULL))
10491 memcpy (saved_order, order, sizeof order);
10497 for (i = 0; i < nops; i++)
10499 regs[i] = unsorted_regs[check_regs ? order[i] : i];
10501 reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i];
10504 *load_offset = unsorted_offsets[order[0]];
10508 && !peep2_reg_dead_p (nops_total, base_reg_rtx))
10511 if (unsorted_offsets[order[0]] == 0)
10512 stm_case = 1; /* stmia */
10513 else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
10514 stm_case = 2; /* stmib */
10515 else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
10516 stm_case = 3; /* stmda */
10517 else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
10518 stm_case = 4; /* stmdb */
10522 if (!multiple_operation_profitable_p (false, nops, 0))
10528 /* Routines for use in generating RTL. */
10530 /* Generate a load-multiple instruction. COUNT is the number of loads in
10531 the instruction; REGS and MEMS are arrays containing the operands.
10532 BASEREG is the base register to be used in addressing the memory operands.
10533 WBACK_OFFSET is nonzero if the instruction should update the base
10537 arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
10538 HOST_WIDE_INT wback_offset)
10543 if (!multiple_operation_profitable_p (false, count, 0))
10549 for (i = 0; i < count; i++)
10550 emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]);
10552 if (wback_offset != 0)
10553 emit_move_insn (basereg, plus_constant (basereg, wback_offset));
10555 seq = get_insns ();
10561 result = gen_rtx_PARALLEL (VOIDmode,
10562 rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
10563 if (wback_offset != 0)
10565 XVECEXP (result, 0, 0)
10566 = gen_rtx_SET (VOIDmode, basereg,
10567 plus_constant (basereg, wback_offset));
10572 for (j = 0; i < count; i++, j++)
10573 XVECEXP (result, 0, i)
10574 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]);
10579 /* Generate a store-multiple instruction. COUNT is the number of stores in
10580 the instruction; REGS and MEMS are arrays containing the operands.
10581 BASEREG is the base register to be used in addressing the memory operands.
10582 WBACK_OFFSET is nonzero if the instruction should update the base
10586 arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
10587 HOST_WIDE_INT wback_offset)
10592 if (GET_CODE (basereg) == PLUS)
10593 basereg = XEXP (basereg, 0);
10595 if (!multiple_operation_profitable_p (false, count, 0))
10601 for (i = 0; i < count; i++)
10602 emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i]));
10604 if (wback_offset != 0)
10605 emit_move_insn (basereg, plus_constant (basereg, wback_offset));
10607 seq = get_insns ();
10613 result = gen_rtx_PARALLEL (VOIDmode,
10614 rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
10615 if (wback_offset != 0)
10617 XVECEXP (result, 0, 0)
10618 = gen_rtx_SET (VOIDmode, basereg,
10619 plus_constant (basereg, wback_offset));
10624 for (j = 0; i < count; i++, j++)
10625 XVECEXP (result, 0, i)
10626 = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j]));
10631 /* Generate either a load-multiple or a store-multiple instruction. This
10632 function can be used in situations where we can start with a single MEM
10633 rtx and adjust its address upwards.
10634 COUNT is the number of operations in the instruction, not counting a
10635 possible update of the base register. REGS is an array containing the
10637 BASEREG is the base register to be used in addressing the memory operands,
10638 which are constructed from BASEMEM.
10639 WRITE_BACK specifies whether the generated instruction should include an
10640 update of the base register.
10641 OFFSETP is used to pass an offset to and from this function; this offset
10642 is not used when constructing the address (instead BASEMEM should have an
10643 appropriate offset in its address), it is used only for setting
10644 MEM_OFFSET. It is updated only if WRITE_BACK is true.*/
10647 arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg,
10648 bool write_back, rtx basemem, HOST_WIDE_INT *offsetp)
10650 rtx mems[MAX_LDM_STM_OPS];
10651 HOST_WIDE_INT offset = *offsetp;
10654 gcc_assert (count <= MAX_LDM_STM_OPS);
10656 if (GET_CODE (basereg) == PLUS)
10657 basereg = XEXP (basereg, 0);
10659 for (i = 0; i < count; i++)
10661 rtx addr = plus_constant (basereg, i * 4);
10662 mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset);
10670 return arm_gen_load_multiple_1 (count, regs, mems, basereg,
10671 write_back ? 4 * count : 0);
10673 return arm_gen_store_multiple_1 (count, regs, mems, basereg,
10674 write_back ? 4 * count : 0);
10678 arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back,
10679 rtx basemem, HOST_WIDE_INT *offsetp)
10681 return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem,
10686 arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back,
10687 rtx basemem, HOST_WIDE_INT *offsetp)
10689 return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem,
10693 /* Called from a peephole2 expander to turn a sequence of loads into an
10694 LDM instruction. OPERANDS are the operands found by the peephole matcher;
10695 NOPS indicates how many separate loads we are trying to combine. SORT_REGS
10696 is true if we can reorder the registers because they are used commutatively
10698 Returns true iff we could generate a new instruction. */
10701 gen_ldm_seq (rtx *operands, int nops, bool sort_regs)
10703 int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
10704 rtx mems[MAX_LDM_STM_OPS];
10705 int i, j, base_reg;
10707 HOST_WIDE_INT offset;
10708 int write_back = FALSE;
10712 ldm_case = load_multiple_sequence (operands, nops, regs, mem_order,
10713 &base_reg, &offset, !sort_regs);
10719 for (i = 0; i < nops - 1; i++)
10720 for (j = i + 1; j < nops; j++)
10721 if (regs[i] > regs[j])
10727 base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
10731 gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx));
10732 gcc_assert (ldm_case == 1 || ldm_case == 5);
10738 rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]);
10739 emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset)));
10741 if (!TARGET_THUMB1)
10743 base_reg = regs[0];
10744 base_reg_rtx = newbase;
10748 for (i = 0; i < nops; i++)
10750 addr = plus_constant (base_reg_rtx, offset + i * 4);
10751 mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
10754 emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx,
10755 write_back ? offset + i * 4 : 0));
10759 /* Called from a peephole2 expander to turn a sequence of stores into an
10760 STM instruction. OPERANDS are the operands found by the peephole matcher;
10761 NOPS indicates how many separate stores we are trying to combine.
10762 Returns true iff we could generate a new instruction. */
10765 gen_stm_seq (rtx *operands, int nops)
10768 int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
10769 rtx mems[MAX_LDM_STM_OPS];
10772 HOST_WIDE_INT offset;
10773 int write_back = FALSE;
10776 bool base_reg_dies;
10778 stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL,
10779 mem_order, &base_reg, &offset, true);
10784 base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
10786 base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx);
10789 gcc_assert (base_reg_dies);
10795 gcc_assert (base_reg_dies);
10796 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
10800 addr = plus_constant (base_reg_rtx, offset);
10802 for (i = 0; i < nops; i++)
10804 addr = plus_constant (base_reg_rtx, offset + i * 4);
10805 mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
10808 emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx,
10809 write_back ? offset + i * 4 : 0));
10813 /* Called from a peephole2 expander to turn a sequence of stores that are
10814 preceded by constant loads into an STM instruction. OPERANDS are the
10815 operands found by the peephole matcher; NOPS indicates how many
10816 separate stores we are trying to combine; there are 2 * NOPS
10817 instructions in the peephole.
10818 Returns true iff we could generate a new instruction. */
10821 gen_const_stm_seq (rtx *operands, int nops)
10823 int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS];
10824 int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
10825 rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS];
10826 rtx mems[MAX_LDM_STM_OPS];
10829 HOST_WIDE_INT offset;
10830 int write_back = FALSE;
10833 bool base_reg_dies;
10835 HARD_REG_SET allocated;
10837 stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs,
10838 mem_order, &base_reg, &offset, false);
10843 memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs);
10845 /* If the same register is used more than once, try to find a free
10847 CLEAR_HARD_REG_SET (allocated);
10848 for (i = 0; i < nops; i++)
10850 for (j = i + 1; j < nops; j++)
10851 if (regs[i] == regs[j])
10853 rtx t = peep2_find_free_register (0, nops * 2,
10854 TARGET_THUMB1 ? "l" : "r",
10855 SImode, &allocated);
10859 regs[i] = REGNO (t);
10863 /* Compute an ordering that maps the register numbers to an ascending
10866 for (i = 0; i < nops; i++)
10867 if (regs[i] < regs[reg_order[0]])
10870 for (i = 1; i < nops; i++)
10872 int this_order = reg_order[i - 1];
10873 for (j = 0; j < nops; j++)
10874 if (regs[j] > regs[reg_order[i - 1]]
10875 && (this_order == reg_order[i - 1]
10876 || regs[j] < regs[this_order]))
10878 reg_order[i] = this_order;
10881 /* Ensure that registers that must be live after the instruction end
10882 up with the correct value. */
10883 for (i = 0; i < nops; i++)
10885 int this_order = reg_order[i];
10886 if ((this_order != mem_order[i]
10887 || orig_reg_rtxs[this_order] != reg_rtxs[this_order])
10888 && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order]))
10892 /* Load the constants. */
10893 for (i = 0; i < nops; i++)
10895 rtx op = operands[2 * nops + mem_order[i]];
10896 sorted_regs[i] = regs[reg_order[i]];
10897 emit_move_insn (reg_rtxs[reg_order[i]], op);
10900 base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
10902 base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx);
10905 gcc_assert (base_reg_dies);
10911 gcc_assert (base_reg_dies);
10912 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
10916 addr = plus_constant (base_reg_rtx, offset);
10918 for (i = 0; i < nops; i++)
10920 addr = plus_constant (base_reg_rtx, offset + i * 4);
10921 mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
10924 emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx,
10925 write_back ? offset + i * 4 : 0));
10929 /* Copy a block of memory using plain ldr/str/ldrh/strh instructions, to permit
10930 unaligned copies on processors which support unaligned semantics for those
10931 instructions. INTERLEAVE_FACTOR can be used to attempt to hide load latency
10932 (using more registers) by doing e.g. load/load/store/store for a factor of 2.
10933 An interleave factor of 1 (the minimum) will perform no interleaving.
10934 Load/store multiple are used for aligned addresses where possible. */
10937 arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
10938 HOST_WIDE_INT length,
10939 unsigned int interleave_factor)
10941 rtx *regs = XALLOCAVEC (rtx, interleave_factor);
10942 int *regnos = XALLOCAVEC (int, interleave_factor);
10943 HOST_WIDE_INT block_size_bytes = interleave_factor * UNITS_PER_WORD;
10944 HOST_WIDE_INT i, j;
10945 HOST_WIDE_INT remaining = length, words;
10946 rtx halfword_tmp = NULL, byte_tmp = NULL;
10948 bool src_aligned = MEM_ALIGN (srcbase) >= BITS_PER_WORD;
10949 bool dst_aligned = MEM_ALIGN (dstbase) >= BITS_PER_WORD;
10950 HOST_WIDE_INT srcoffset, dstoffset;
10951 HOST_WIDE_INT src_autoinc, dst_autoinc;
10954 gcc_assert (1 <= interleave_factor && interleave_factor <= 4);
10956 /* Use hard registers if we have aligned source or destination so we can use
10957 load/store multiple with contiguous registers. */
10958 if (dst_aligned || src_aligned)
10959 for (i = 0; i < interleave_factor; i++)
10960 regs[i] = gen_rtx_REG (SImode, i);
10962 for (i = 0; i < interleave_factor; i++)
10963 regs[i] = gen_reg_rtx (SImode);
10965 dst = copy_addr_to_reg (XEXP (dstbase, 0));
10966 src = copy_addr_to_reg (XEXP (srcbase, 0));
10968 srcoffset = dstoffset = 0;
10970 /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST.
10971 For copying the last bytes we want to subtract this offset again. */
10972 src_autoinc = dst_autoinc = 0;
10974 for (i = 0; i < interleave_factor; i++)
10977 /* Copy BLOCK_SIZE_BYTES chunks. */
10979 for (i = 0; i + block_size_bytes <= length; i += block_size_bytes)
10982 if (src_aligned && interleave_factor > 1)
10984 emit_insn (arm_gen_load_multiple (regnos, interleave_factor, src,
10985 TRUE, srcbase, &srcoffset));
10986 src_autoinc += UNITS_PER_WORD * interleave_factor;
10990 for (j = 0; j < interleave_factor; j++)
10992 addr = plus_constant (src, srcoffset + j * UNITS_PER_WORD
10994 mem = adjust_automodify_address (srcbase, SImode, addr,
10995 srcoffset + j * UNITS_PER_WORD);
10996 emit_insn (gen_unaligned_loadsi (regs[j], mem));
10998 srcoffset += block_size_bytes;
11002 if (dst_aligned && interleave_factor > 1)
11004 emit_insn (arm_gen_store_multiple (regnos, interleave_factor, dst,
11005 TRUE, dstbase, &dstoffset));
11006 dst_autoinc += UNITS_PER_WORD * interleave_factor;
11010 for (j = 0; j < interleave_factor; j++)
11012 addr = plus_constant (dst, dstoffset + j * UNITS_PER_WORD
11014 mem = adjust_automodify_address (dstbase, SImode, addr,
11015 dstoffset + j * UNITS_PER_WORD);
11016 emit_insn (gen_unaligned_storesi (mem, regs[j]));
11018 dstoffset += block_size_bytes;
11021 remaining -= block_size_bytes;
11024 /* Copy any whole words left (note these aren't interleaved with any
11025 subsequent halfword/byte load/stores in the interests of simplicity). */
11027 words = remaining / UNITS_PER_WORD;
11029 gcc_assert (words < interleave_factor);
11031 if (src_aligned && words > 1)
11033 emit_insn (arm_gen_load_multiple (regnos, words, src, TRUE, srcbase,
11035 src_autoinc += UNITS_PER_WORD * words;
11039 for (j = 0; j < words; j++)
11041 addr = plus_constant (src,
11042 srcoffset + j * UNITS_PER_WORD - src_autoinc);
11043 mem = adjust_automodify_address (srcbase, SImode, addr,
11044 srcoffset + j * UNITS_PER_WORD);
11045 emit_insn (gen_unaligned_loadsi (regs[j], mem));
11047 srcoffset += words * UNITS_PER_WORD;
11050 if (dst_aligned && words > 1)
11052 emit_insn (arm_gen_store_multiple (regnos, words, dst, TRUE, dstbase,
11054 dst_autoinc += words * UNITS_PER_WORD;
11058 for (j = 0; j < words; j++)
11060 addr = plus_constant (dst,
11061 dstoffset + j * UNITS_PER_WORD - dst_autoinc);
11062 mem = adjust_automodify_address (dstbase, SImode, addr,
11063 dstoffset + j * UNITS_PER_WORD);
11064 emit_insn (gen_unaligned_storesi (mem, regs[j]));
11066 dstoffset += words * UNITS_PER_WORD;
11069 remaining -= words * UNITS_PER_WORD;
11071 gcc_assert (remaining < 4);
11073 /* Copy a halfword if necessary. */
11075 if (remaining >= 2)
11077 halfword_tmp = gen_reg_rtx (SImode);
11079 addr = plus_constant (src, srcoffset - src_autoinc);
11080 mem = adjust_automodify_address (srcbase, HImode, addr, srcoffset);
11081 emit_insn (gen_unaligned_loadhiu (halfword_tmp, mem));
11083 /* Either write out immediately, or delay until we've loaded the last
11084 byte, depending on interleave factor. */
11085 if (interleave_factor == 1)
11087 addr = plus_constant (dst, dstoffset - dst_autoinc);
11088 mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
11089 emit_insn (gen_unaligned_storehi (mem,
11090 gen_lowpart (HImode, halfword_tmp)));
11091 halfword_tmp = NULL;
11099 gcc_assert (remaining < 2);
11101 /* Copy last byte. */
11103 if ((remaining & 1) != 0)
11105 byte_tmp = gen_reg_rtx (SImode);
11107 addr = plus_constant (src, srcoffset - src_autoinc);
11108 mem = adjust_automodify_address (srcbase, QImode, addr, srcoffset);
11109 emit_move_insn (gen_lowpart (QImode, byte_tmp), mem);
11111 if (interleave_factor == 1)
11113 addr = plus_constant (dst, dstoffset - dst_autoinc);
11114 mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
11115 emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
11124 /* Store last halfword if we haven't done so already. */
11128 addr = plus_constant (dst, dstoffset - dst_autoinc);
11129 mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
11130 emit_insn (gen_unaligned_storehi (mem,
11131 gen_lowpart (HImode, halfword_tmp)));
11135 /* Likewise for last byte. */
11139 addr = plus_constant (dst, dstoffset - dst_autoinc);
11140 mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
11141 emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
11145 gcc_assert (remaining == 0 && srcoffset == dstoffset);
11148 /* From mips_adjust_block_mem:
11150 Helper function for doing a loop-based block operation on memory
11151 reference MEM. Each iteration of the loop will operate on LENGTH
11154 Create a new base register for use within the loop and point it to
11155 the start of MEM. Create a new memory reference that uses this
11156 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
11159 arm_adjust_block_mem (rtx mem, HOST_WIDE_INT length, rtx *loop_reg,
11162 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
11164 /* Although the new mem does not refer to a known location,
11165 it does keep up to LENGTH bytes of alignment. */
11166 *loop_mem = change_address (mem, BLKmode, *loop_reg);
11167 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
11170 /* From mips_block_move_loop:
11172 Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
11173 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
11174 the memory regions do not overlap. */
11177 arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length,
11178 unsigned int interleave_factor,
11179 HOST_WIDE_INT bytes_per_iter)
11181 rtx label, src_reg, dest_reg, final_src, test;
11182 HOST_WIDE_INT leftover;
11184 leftover = length % bytes_per_iter;
11185 length -= leftover;
11187 /* Create registers and memory references for use within the loop. */
11188 arm_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
11189 arm_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
11191 /* Calculate the value that SRC_REG should have after the last iteration of
11193 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
11194 0, 0, OPTAB_WIDEN);
11196 /* Emit the start of the loop. */
11197 label = gen_label_rtx ();
11198 emit_label (label);
11200 /* Emit the loop body. */
11201 arm_block_move_unaligned_straight (dest, src, bytes_per_iter,
11202 interleave_factor);
11204 /* Move on to the next block. */
11205 emit_move_insn (src_reg, plus_constant (src_reg, bytes_per_iter));
11206 emit_move_insn (dest_reg, plus_constant (dest_reg, bytes_per_iter));
11208 /* Emit the loop condition. */
11209 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
11210 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
11212 /* Mop up any left-over bytes. */
11214 arm_block_move_unaligned_straight (dest, src, leftover, interleave_factor);
11217 /* Emit a block move when either the source or destination is unaligned (not
11218 aligned to a four-byte boundary). This may need further tuning depending on
11219 core type, optimize_size setting, etc. */
11222 arm_movmemqi_unaligned (rtx *operands)
11224 HOST_WIDE_INT length = INTVAL (operands[2]);
11228 bool src_aligned = MEM_ALIGN (operands[1]) >= BITS_PER_WORD;
11229 bool dst_aligned = MEM_ALIGN (operands[0]) >= BITS_PER_WORD;
11230 /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
11231 size of code if optimizing for size. We'll use ldm/stm if src_aligned
11232 or dst_aligned though: allow more interleaving in those cases since the
11233 resulting code can be smaller. */
11234 unsigned int interleave_factor = (src_aligned || dst_aligned) ? 2 : 1;
11235 HOST_WIDE_INT bytes_per_iter = (src_aligned || dst_aligned) ? 8 : 4;
11238 arm_block_move_unaligned_loop (operands[0], operands[1], length,
11239 interleave_factor, bytes_per_iter);
11241 arm_block_move_unaligned_straight (operands[0], operands[1], length,
11242 interleave_factor);
11246 /* Note that the loop created by arm_block_move_unaligned_loop may be
11247 subject to loop unrolling, which makes tuning this condition a little
11250 arm_block_move_unaligned_loop (operands[0], operands[1], length, 4, 16);
11252 arm_block_move_unaligned_straight (operands[0], operands[1], length, 4);
11259 arm_gen_movmemqi (rtx *operands)
11261 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
11262 HOST_WIDE_INT srcoffset, dstoffset;
11264 rtx src, dst, srcbase, dstbase;
11265 rtx part_bytes_reg = NULL;
11268 if (GET_CODE (operands[2]) != CONST_INT
11269 || GET_CODE (operands[3]) != CONST_INT
11270 || INTVAL (operands[2]) > 64)
11273 if (unaligned_access && (INTVAL (operands[3]) & 3) != 0)
11274 return arm_movmemqi_unaligned (operands);
11276 if (INTVAL (operands[3]) & 3)
11279 dstbase = operands[0];
11280 srcbase = operands[1];
11282 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
11283 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
11285 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
11286 out_words_to_go = INTVAL (operands[2]) / 4;
11287 last_bytes = INTVAL (operands[2]) & 3;
11288 dstoffset = srcoffset = 0;
11290 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
11291 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
11293 for (i = 0; in_words_to_go >= 2; i+=4)
11295 if (in_words_to_go > 4)
11296 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src,
11297 TRUE, srcbase, &srcoffset));
11299 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go,
11300 src, FALSE, srcbase,
11303 if (out_words_to_go)
11305 if (out_words_to_go > 4)
11306 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst,
11307 TRUE, dstbase, &dstoffset));
11308 else if (out_words_to_go != 1)
11309 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence,
11310 out_words_to_go, dst,
11313 dstbase, &dstoffset));
11316 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
11317 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
11318 if (last_bytes != 0)
11320 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
11326 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
11327 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
11330 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
11331 if (out_words_to_go)
11335 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
11336 sreg = copy_to_reg (mem);
11338 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
11339 emit_move_insn (mem, sreg);
11342 gcc_assert (!in_words_to_go); /* Sanity check */
11345 if (in_words_to_go)
11347 gcc_assert (in_words_to_go > 0);
11349 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
11350 part_bytes_reg = copy_to_mode_reg (SImode, mem);
11353 gcc_assert (!last_bytes || part_bytes_reg);
11355 if (BYTES_BIG_ENDIAN && last_bytes)
11357 rtx tmp = gen_reg_rtx (SImode);
11359 /* The bytes we want are in the top end of the word. */
11360 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
11361 GEN_INT (8 * (4 - last_bytes))));
11362 part_bytes_reg = tmp;
11366 mem = adjust_automodify_address (dstbase, QImode,
11367 plus_constant (dst, last_bytes - 1),
11368 dstoffset + last_bytes - 1);
11369 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
11373 tmp = gen_reg_rtx (SImode);
11374 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
11375 part_bytes_reg = tmp;
11382 if (last_bytes > 1)
11384 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
11385 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
11389 rtx tmp = gen_reg_rtx (SImode);
11390 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
11391 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
11392 part_bytes_reg = tmp;
11399 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
11400 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
11407 /* Select a dominance comparison mode if possible for a test of the general
11408 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
11409 COND_OR == DOM_CC_X_AND_Y => (X && Y)
11410 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
11411 COND_OR == DOM_CC_X_OR_Y => (X || Y)
11412 In all cases OP will be either EQ or NE, but we don't need to know which
11413 here. If we are unable to support a dominance comparison we return
11414 CC mode. This will then fail to match for the RTL expressions that
11415 generate this call. */
11417 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
11419 enum rtx_code cond1, cond2;
11422 /* Currently we will probably get the wrong result if the individual
11423 comparisons are not simple. This also ensures that it is safe to
11424 reverse a comparison if necessary. */
11425 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
11427 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
11431 /* The if_then_else variant of this tests the second condition if the
11432 first passes, but is true if the first fails. Reverse the first
11433 condition to get a true "inclusive-or" expression. */
11434 if (cond_or == DOM_CC_NX_OR_Y)
11435 cond1 = reverse_condition (cond1);
11437 /* If the comparisons are not equal, and one doesn't dominate the other,
11438 then we can't do this. */
11440 && !comparison_dominates_p (cond1, cond2)
11441 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
11446 enum rtx_code temp = cond1;
11454 if (cond_or == DOM_CC_X_AND_Y)
11459 case EQ: return CC_DEQmode;
11460 case LE: return CC_DLEmode;
11461 case LEU: return CC_DLEUmode;
11462 case GE: return CC_DGEmode;
11463 case GEU: return CC_DGEUmode;
11464 default: gcc_unreachable ();
11468 if (cond_or == DOM_CC_X_AND_Y)
11480 gcc_unreachable ();
11484 if (cond_or == DOM_CC_X_AND_Y)
11496 gcc_unreachable ();
11500 if (cond_or == DOM_CC_X_AND_Y)
11501 return CC_DLTUmode;
11506 return CC_DLTUmode;
11508 return CC_DLEUmode;
11512 gcc_unreachable ();
11516 if (cond_or == DOM_CC_X_AND_Y)
11517 return CC_DGTUmode;
11522 return CC_DGTUmode;
11524 return CC_DGEUmode;
11528 gcc_unreachable ();
11531 /* The remaining cases only occur when both comparisons are the
11534 gcc_assert (cond1 == cond2);
11538 gcc_assert (cond1 == cond2);
11542 gcc_assert (cond1 == cond2);
11546 gcc_assert (cond1 == cond2);
11547 return CC_DLEUmode;
11550 gcc_assert (cond1 == cond2);
11551 return CC_DGEUmode;
11554 gcc_unreachable ();
11559 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
11561 /* All floating point compares return CCFP if it is an equality
11562 comparison, and CCFPE otherwise. */
11563 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11583 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
11588 gcc_unreachable ();
11592 /* A compare with a shifted operand. Because of canonicalization, the
11593 comparison will have to be swapped when we emit the assembler. */
11594 if (GET_MODE (y) == SImode
11595 && (REG_P (y) || (GET_CODE (y) == SUBREG))
11596 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
11597 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
11598 || GET_CODE (x) == ROTATERT))
11601 /* This operation is performed swapped, but since we only rely on the Z
11602 flag we don't need an additional mode. */
11603 if (GET_MODE (y) == SImode
11604 && (REG_P (y) || (GET_CODE (y) == SUBREG))
11605 && GET_CODE (x) == NEG
11606 && (op == EQ || op == NE))
11609 /* This is a special case that is used by combine to allow a
11610 comparison of a shifted byte load to be split into a zero-extend
11611 followed by a comparison of the shifted integer (only valid for
11612 equalities and unsigned inequalities). */
11613 if (GET_MODE (x) == SImode
11614 && GET_CODE (x) == ASHIFT
11615 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
11616 && GET_CODE (XEXP (x, 0)) == SUBREG
11617 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
11618 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
11619 && (op == EQ || op == NE
11620 || op == GEU || op == GTU || op == LTU || op == LEU)
11621 && GET_CODE (y) == CONST_INT)
11624 /* A construct for a conditional compare, if the false arm contains
11625 0, then both conditions must be true, otherwise either condition
11626 must be true. Not all conditions are possible, so CCmode is
11627 returned if it can't be done. */
11628 if (GET_CODE (x) == IF_THEN_ELSE
11629 && (XEXP (x, 2) == const0_rtx
11630 || XEXP (x, 2) == const1_rtx)
11631 && COMPARISON_P (XEXP (x, 0))
11632 && COMPARISON_P (XEXP (x, 1)))
11633 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
11634 INTVAL (XEXP (x, 2)));
11636 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
11637 if (GET_CODE (x) == AND
11638 && (op == EQ || op == NE)
11639 && COMPARISON_P (XEXP (x, 0))
11640 && COMPARISON_P (XEXP (x, 1)))
11641 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
11644 if (GET_CODE (x) == IOR
11645 && (op == EQ || op == NE)
11646 && COMPARISON_P (XEXP (x, 0))
11647 && COMPARISON_P (XEXP (x, 1)))
11648 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
11651 /* An operation (on Thumb) where we want to test for a single bit.
11652 This is done by shifting that bit up into the top bit of a
11653 scratch register; we can then branch on the sign bit. */
11655 && GET_MODE (x) == SImode
11656 && (op == EQ || op == NE)
11657 && GET_CODE (x) == ZERO_EXTRACT
11658 && XEXP (x, 1) == const1_rtx)
11661 /* An operation that sets the condition codes as a side-effect, the
11662 V flag is not set correctly, so we can only use comparisons where
11663 this doesn't matter. (For LT and GE we can use "mi" and "pl"
11665 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
11666 if (GET_MODE (x) == SImode
11668 && (op == EQ || op == NE || op == LT || op == GE)
11669 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
11670 || GET_CODE (x) == AND || GET_CODE (x) == IOR
11671 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
11672 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
11673 || GET_CODE (x) == LSHIFTRT
11674 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
11675 || GET_CODE (x) == ROTATERT
11676 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
11677 return CC_NOOVmode;
11679 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
11682 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
11683 && GET_CODE (x) == PLUS
11684 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
11687 if (GET_MODE (x) == DImode || GET_MODE (y) == DImode)
11689 /* To keep things simple, always use the Cirrus cfcmp64 if it is
11691 if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
11698 /* A DImode comparison against zero can be implemented by
11699 or'ing the two halves together. */
11700 if (y == const0_rtx)
11703 /* We can do an equality test in three Thumb instructions. */
11713 /* DImode unsigned comparisons can be implemented by cmp +
11714 cmpeq without a scratch register. Not worth doing in
11725 /* DImode signed and unsigned comparisons can be implemented
11726 by cmp + sbcs with a scratch register, but that does not
11727 set the Z flag - we must reverse GT/LE/GTU/LEU. */
11728 gcc_assert (op != EQ && op != NE);
11732 gcc_unreachable ();
11736 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
11737 return GET_MODE (x);
11742 /* X and Y are two things to compare using CODE. Emit the compare insn and
11743 return the rtx for register 0 in the proper mode. FP means this is a
11744 floating point compare: I don't think that it is needed on the arm. */
11746 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y, rtx scratch)
11748 enum machine_mode mode;
11750 int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode;
11752 /* We might have X as a constant, Y as a register because of the predicates
11753 used for cmpdi. If so, force X to a register here. */
11754 if (dimode_comparison && !REG_P (x))
11755 x = force_reg (DImode, x);
11757 mode = SELECT_CC_MODE (code, x, y);
11758 cc_reg = gen_rtx_REG (mode, CC_REGNUM);
11760 if (dimode_comparison
11761 && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
11762 && mode != CC_CZmode)
11766 /* To compare two non-zero values for equality, XOR them and
11767 then compare against zero. Not used for ARM mode; there
11768 CC_CZmode is cheaper. */
11769 if (mode == CC_Zmode && y != const0_rtx)
11771 gcc_assert (!reload_completed);
11772 x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN);
11776 /* A scratch register is required. */
11777 if (reload_completed)
11778 gcc_assert (scratch != NULL && GET_MODE (scratch) == SImode);
11780 scratch = gen_rtx_SCRATCH (SImode);
11782 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
11783 set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y));
11784 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
11787 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
11792 /* Generate a sequence of insns that will generate the correct return
11793 address mask depending on the physical architecture that the program
11796 arm_gen_return_addr_mask (void)
11798 rtx reg = gen_reg_rtx (Pmode);
11800 emit_insn (gen_return_addr_mask (reg));
11805 arm_reload_in_hi (rtx *operands)
11807 rtx ref = operands[1];
11809 HOST_WIDE_INT offset = 0;
11811 if (GET_CODE (ref) == SUBREG)
11813 offset = SUBREG_BYTE (ref);
11814 ref = SUBREG_REG (ref);
11817 if (GET_CODE (ref) == REG)
11819 /* We have a pseudo which has been spilt onto the stack; there
11820 are two cases here: the first where there is a simple
11821 stack-slot replacement and a second where the stack-slot is
11822 out of range, or is used as a subreg. */
11823 if (reg_equiv_mem (REGNO (ref)))
11825 ref = reg_equiv_mem (REGNO (ref));
11826 base = find_replacement (&XEXP (ref, 0));
11829 /* The slot is out of range, or was dressed up in a SUBREG. */
11830 base = reg_equiv_address (REGNO (ref));
11833 base = find_replacement (&XEXP (ref, 0));
11835 /* Handle the case where the address is too complex to be offset by 1. */
11836 if (GET_CODE (base) == MINUS
11837 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
11839 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
11841 emit_set_insn (base_plus, base);
11844 else if (GET_CODE (base) == PLUS)
11846 /* The addend must be CONST_INT, or we would have dealt with it above. */
11847 HOST_WIDE_INT hi, lo;
11849 offset += INTVAL (XEXP (base, 1));
11850 base = XEXP (base, 0);
11852 /* Rework the address into a legal sequence of insns. */
11853 /* Valid range for lo is -4095 -> 4095 */
11856 : -((-offset) & 0xfff));
11858 /* Corner case, if lo is the max offset then we would be out of range
11859 once we have added the additional 1 below, so bump the msb into the
11860 pre-loading insn(s). */
11864 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
11865 ^ (HOST_WIDE_INT) 0x80000000)
11866 - (HOST_WIDE_INT) 0x80000000);
11868 gcc_assert (hi + lo == offset);
11872 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
11874 /* Get the base address; addsi3 knows how to handle constants
11875 that require more than one insn. */
11876 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
11882 /* Operands[2] may overlap operands[0] (though it won't overlap
11883 operands[1]), that's why we asked for a DImode reg -- so we can
11884 use the bit that does not overlap. */
11885 if (REGNO (operands[2]) == REGNO (operands[0]))
11886 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
11888 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
11890 emit_insn (gen_zero_extendqisi2 (scratch,
11891 gen_rtx_MEM (QImode,
11892 plus_constant (base,
11894 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
11895 gen_rtx_MEM (QImode,
11896 plus_constant (base,
11898 if (!BYTES_BIG_ENDIAN)
11899 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
11900 gen_rtx_IOR (SImode,
11903 gen_rtx_SUBREG (SImode, operands[0], 0),
11907 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
11908 gen_rtx_IOR (SImode,
11909 gen_rtx_ASHIFT (SImode, scratch,
11911 gen_rtx_SUBREG (SImode, operands[0], 0)));
11914 /* Handle storing a half-word to memory during reload by synthesizing as two
11915 byte stores. Take care not to clobber the input values until after we
11916 have moved them somewhere safe. This code assumes that if the DImode
11917 scratch in operands[2] overlaps either the input value or output address
11918 in some way, then that value must die in this insn (we absolutely need
11919 two scratch registers for some corner cases). */
11921 arm_reload_out_hi (rtx *operands)
11923 rtx ref = operands[0];
11924 rtx outval = operands[1];
11926 HOST_WIDE_INT offset = 0;
11928 if (GET_CODE (ref) == SUBREG)
11930 offset = SUBREG_BYTE (ref);
11931 ref = SUBREG_REG (ref);
11934 if (GET_CODE (ref) == REG)
11936 /* We have a pseudo which has been spilt onto the stack; there
11937 are two cases here: the first where there is a simple
11938 stack-slot replacement and a second where the stack-slot is
11939 out of range, or is used as a subreg. */
11940 if (reg_equiv_mem (REGNO (ref)))
11942 ref = reg_equiv_mem (REGNO (ref));
11943 base = find_replacement (&XEXP (ref, 0));
11946 /* The slot is out of range, or was dressed up in a SUBREG. */
11947 base = reg_equiv_address (REGNO (ref));
11950 base = find_replacement (&XEXP (ref, 0));
11952 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
11954 /* Handle the case where the address is too complex to be offset by 1. */
11955 if (GET_CODE (base) == MINUS
11956 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
11958 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
11960 /* Be careful not to destroy OUTVAL. */
11961 if (reg_overlap_mentioned_p (base_plus, outval))
11963 /* Updating base_plus might destroy outval, see if we can
11964 swap the scratch and base_plus. */
11965 if (!reg_overlap_mentioned_p (scratch, outval))
11968 scratch = base_plus;
11973 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
11975 /* Be conservative and copy OUTVAL into the scratch now,
11976 this should only be necessary if outval is a subreg
11977 of something larger than a word. */
11978 /* XXX Might this clobber base? I can't see how it can,
11979 since scratch is known to overlap with OUTVAL, and
11980 must be wider than a word. */
11981 emit_insn (gen_movhi (scratch_hi, outval));
11982 outval = scratch_hi;
11986 emit_set_insn (base_plus, base);
11989 else if (GET_CODE (base) == PLUS)
11991 /* The addend must be CONST_INT, or we would have dealt with it above. */
11992 HOST_WIDE_INT hi, lo;
11994 offset += INTVAL (XEXP (base, 1));
11995 base = XEXP (base, 0);
11997 /* Rework the address into a legal sequence of insns. */
11998 /* Valid range for lo is -4095 -> 4095 */
12001 : -((-offset) & 0xfff));
12003 /* Corner case, if lo is the max offset then we would be out of range
12004 once we have added the additional 1 below, so bump the msb into the
12005 pre-loading insn(s). */
12009 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
12010 ^ (HOST_WIDE_INT) 0x80000000)
12011 - (HOST_WIDE_INT) 0x80000000);
12013 gcc_assert (hi + lo == offset);
12017 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
12019 /* Be careful not to destroy OUTVAL. */
12020 if (reg_overlap_mentioned_p (base_plus, outval))
12022 /* Updating base_plus might destroy outval, see if we
12023 can swap the scratch and base_plus. */
12024 if (!reg_overlap_mentioned_p (scratch, outval))
12027 scratch = base_plus;
12032 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
12034 /* Be conservative and copy outval into scratch now,
12035 this should only be necessary if outval is a
12036 subreg of something larger than a word. */
12037 /* XXX Might this clobber base? I can't see how it
12038 can, since scratch is known to overlap with
12040 emit_insn (gen_movhi (scratch_hi, outval));
12041 outval = scratch_hi;
12045 /* Get the base address; addsi3 knows how to handle constants
12046 that require more than one insn. */
12047 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
12053 if (BYTES_BIG_ENDIAN)
12055 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
12056 plus_constant (base, offset + 1)),
12057 gen_lowpart (QImode, outval)));
12058 emit_insn (gen_lshrsi3 (scratch,
12059 gen_rtx_SUBREG (SImode, outval, 0),
12061 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
12062 gen_lowpart (QImode, scratch)));
12066 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
12067 gen_lowpart (QImode, outval)));
12068 emit_insn (gen_lshrsi3 (scratch,
12069 gen_rtx_SUBREG (SImode, outval, 0),
12071 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
12072 plus_constant (base, offset + 1)),
12073 gen_lowpart (QImode, scratch)));
12077 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
12078 (padded to the size of a word) should be passed in a register. */
12081 arm_must_pass_in_stack (enum machine_mode mode, const_tree type)
12083 if (TARGET_AAPCS_BASED)
12084 return must_pass_in_stack_var_size (mode, type);
12086 return must_pass_in_stack_var_size_or_pad (mode, type);
12090 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
12091 Return true if an argument passed on the stack should be padded upwards,
12092 i.e. if the least-significant byte has useful data.
12093 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
12094 aggregate types are placed in the lowest memory address. */
12097 arm_pad_arg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, const_tree type)
12099 if (!TARGET_AAPCS_BASED)
12100 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
12102 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
12109 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
12110 Return !BYTES_BIG_ENDIAN if the least significant byte of the
12111 register has useful data, and return the opposite if the most
12112 significant byte does. */
12115 arm_pad_reg_upward (enum machine_mode mode,
12116 tree type, int first ATTRIBUTE_UNUSED)
12118 if (TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN)
12120 /* For AAPCS, small aggregates, small fixed-point types,
12121 and small complex types are always padded upwards. */
12124 if ((AGGREGATE_TYPE_P (type)
12125 || TREE_CODE (type) == COMPLEX_TYPE
12126 || FIXED_POINT_TYPE_P (type))
12127 && int_size_in_bytes (type) <= 4)
12132 if ((COMPLEX_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))
12133 && GET_MODE_SIZE (mode) <= 4)
12138 /* Otherwise, use default padding. */
12139 return !BYTES_BIG_ENDIAN;
12143 /* Print a symbolic form of X to the debug file, F. */
12145 arm_print_value (FILE *f, rtx x)
12147 switch (GET_CODE (x))
12150 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
12154 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
12162 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
12164 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
12165 if (i < (CONST_VECTOR_NUNITS (x) - 1))
12173 fprintf (f, "\"%s\"", XSTR (x, 0));
12177 fprintf (f, "`%s'", XSTR (x, 0));
12181 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
12185 arm_print_value (f, XEXP (x, 0));
12189 arm_print_value (f, XEXP (x, 0));
12191 arm_print_value (f, XEXP (x, 1));
12199 fprintf (f, "????");
12204 /* Routines for manipulation of the constant pool. */
12206 /* Arm instructions cannot load a large constant directly into a
12207 register; they have to come from a pc relative load. The constant
12208 must therefore be placed in the addressable range of the pc
12209 relative load. Depending on the precise pc relative load
12210 instruction the range is somewhere between 256 bytes and 4k. This
12211 means that we often have to dump a constant inside a function, and
12212 generate code to branch around it.
12214 It is important to minimize this, since the branches will slow
12215 things down and make the code larger.
12217 Normally we can hide the table after an existing unconditional
12218 branch so that there is no interruption of the flow, but in the
12219 worst case the code looks like this:
12237 We fix this by performing a scan after scheduling, which notices
12238 which instructions need to have their operands fetched from the
12239 constant table and builds the table.
12241 The algorithm starts by building a table of all the constants that
12242 need fixing up and all the natural barriers in the function (places
12243 where a constant table can be dropped without breaking the flow).
12244 For each fixup we note how far the pc-relative replacement will be
12245 able to reach and the offset of the instruction into the function.
12247 Having built the table we then group the fixes together to form
12248 tables that are as large as possible (subject to addressing
12249 constraints) and emit each table of constants after the last
12250 barrier that is within range of all the instructions in the group.
12251 If a group does not contain a barrier, then we forcibly create one
12252 by inserting a jump instruction into the flow. Once the table has
12253 been inserted, the insns are then modified to reference the
12254 relevant entry in the pool.
12256 Possible enhancements to the algorithm (not implemented) are:
12258 1) For some processors and object formats, there may be benefit in
12259 aligning the pools to the start of cache lines; this alignment
12260 would need to be taken into account when calculating addressability
12263 /* These typedefs are located at the start of this file, so that
12264 they can be used in the prototypes there. This comment is to
12265 remind readers of that fact so that the following structures
12266 can be understood more easily.
12268 typedef struct minipool_node Mnode;
12269 typedef struct minipool_fixup Mfix; */
12271 struct minipool_node
12273 /* Doubly linked chain of entries. */
12276 /* The maximum offset into the code that this entry can be placed. While
12277 pushing fixes for forward references, all entries are sorted in order
12278 of increasing max_address. */
12279 HOST_WIDE_INT max_address;
12280 /* Similarly for an entry inserted for a backwards ref. */
12281 HOST_WIDE_INT min_address;
12282 /* The number of fixes referencing this entry. This can become zero
12283 if we "unpush" an entry. In this case we ignore the entry when we
12284 come to emit the code. */
12286 /* The offset from the start of the minipool. */
12287 HOST_WIDE_INT offset;
12288 /* The value in table. */
12290 /* The mode of value. */
12291 enum machine_mode mode;
12292 /* The size of the value. With iWMMXt enabled
12293 sizes > 4 also imply an alignment of 8-bytes. */
12297 struct minipool_fixup
12301 HOST_WIDE_INT address;
12303 enum machine_mode mode;
12307 HOST_WIDE_INT forwards;
12308 HOST_WIDE_INT backwards;
12311 /* Fixes less than a word need padding out to a word boundary. */
12312 #define MINIPOOL_FIX_SIZE(mode) \
12313 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
12315 static Mnode * minipool_vector_head;
12316 static Mnode * minipool_vector_tail;
12317 static rtx minipool_vector_label;
12318 static int minipool_pad;
12320 /* The linked list of all minipool fixes required for this function. */
12321 Mfix * minipool_fix_head;
12322 Mfix * minipool_fix_tail;
12323 /* The fix entry for the current minipool, once it has been placed. */
12324 Mfix * minipool_barrier;
12326 /* Determines if INSN is the start of a jump table. Returns the end
12327 of the TABLE or NULL_RTX. */
12329 is_jump_table (rtx insn)
12333 if (jump_to_label_p (insn)
12334 && ((table = next_real_insn (JUMP_LABEL (insn)))
12335 == next_real_insn (insn))
12337 && GET_CODE (table) == JUMP_INSN
12338 && (GET_CODE (PATTERN (table)) == ADDR_VEC
12339 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
12345 #ifndef JUMP_TABLES_IN_TEXT_SECTION
12346 #define JUMP_TABLES_IN_TEXT_SECTION 0
12349 static HOST_WIDE_INT
12350 get_jump_table_size (rtx insn)
12352 /* ADDR_VECs only take room if read-only data does into the text
12354 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
12356 rtx body = PATTERN (insn);
12357 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
12358 HOST_WIDE_INT size;
12359 HOST_WIDE_INT modesize;
12361 modesize = GET_MODE_SIZE (GET_MODE (body));
12362 size = modesize * XVECLEN (body, elt);
12366 /* Round up size of TBB table to a halfword boundary. */
12367 size = (size + 1) & ~(HOST_WIDE_INT)1;
12370 /* No padding necessary for TBH. */
12373 /* Add two bytes for alignment on Thumb. */
12378 gcc_unreachable ();
12386 /* Return the maximum amount of padding that will be inserted before
12389 static HOST_WIDE_INT
12390 get_label_padding (rtx label)
12392 HOST_WIDE_INT align, min_insn_size;
12394 align = 1 << label_to_alignment (label);
12395 min_insn_size = TARGET_THUMB ? 2 : 4;
12396 return align > min_insn_size ? align - min_insn_size : 0;
12399 /* Move a minipool fix MP from its current location to before MAX_MP.
12400 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
12401 constraints may need updating. */
12403 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
12404 HOST_WIDE_INT max_address)
12406 /* The code below assumes these are different. */
12407 gcc_assert (mp != max_mp);
12409 if (max_mp == NULL)
12411 if (max_address < mp->max_address)
12412 mp->max_address = max_address;
12416 if (max_address > max_mp->max_address - mp->fix_size)
12417 mp->max_address = max_mp->max_address - mp->fix_size;
12419 mp->max_address = max_address;
12421 /* Unlink MP from its current position. Since max_mp is non-null,
12422 mp->prev must be non-null. */
12423 mp->prev->next = mp->next;
12424 if (mp->next != NULL)
12425 mp->next->prev = mp->prev;
12427 minipool_vector_tail = mp->prev;
12429 /* Re-insert it before MAX_MP. */
12431 mp->prev = max_mp->prev;
12434 if (mp->prev != NULL)
12435 mp->prev->next = mp;
12437 minipool_vector_head = mp;
12440 /* Save the new entry. */
12443 /* Scan over the preceding entries and adjust their addresses as
12445 while (mp->prev != NULL
12446 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
12448 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
12455 /* Add a constant to the minipool for a forward reference. Returns the
12456 node added or NULL if the constant will not fit in this pool. */
12458 add_minipool_forward_ref (Mfix *fix)
12460 /* If set, max_mp is the first pool_entry that has a lower
12461 constraint than the one we are trying to add. */
12462 Mnode * max_mp = NULL;
12463 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
12466 /* If the minipool starts before the end of FIX->INSN then this FIX
12467 can not be placed into the current pool. Furthermore, adding the
12468 new constant pool entry may cause the pool to start FIX_SIZE bytes
12470 if (minipool_vector_head &&
12471 (fix->address + get_attr_length (fix->insn)
12472 >= minipool_vector_head->max_address - fix->fix_size))
12475 /* Scan the pool to see if a constant with the same value has
12476 already been added. While we are doing this, also note the
12477 location where we must insert the constant if it doesn't already
12479 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
12481 if (GET_CODE (fix->value) == GET_CODE (mp->value)
12482 && fix->mode == mp->mode
12483 && (GET_CODE (fix->value) != CODE_LABEL
12484 || (CODE_LABEL_NUMBER (fix->value)
12485 == CODE_LABEL_NUMBER (mp->value)))
12486 && rtx_equal_p (fix->value, mp->value))
12488 /* More than one fix references this entry. */
12490 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
12493 /* Note the insertion point if necessary. */
12495 && mp->max_address > max_address)
12498 /* If we are inserting an 8-bytes aligned quantity and
12499 we have not already found an insertion point, then
12500 make sure that all such 8-byte aligned quantities are
12501 placed at the start of the pool. */
12502 if (ARM_DOUBLEWORD_ALIGN
12504 && fix->fix_size >= 8
12505 && mp->fix_size < 8)
12508 max_address = mp->max_address;
12512 /* The value is not currently in the minipool, so we need to create
12513 a new entry for it. If MAX_MP is NULL, the entry will be put on
12514 the end of the list since the placement is less constrained than
12515 any existing entry. Otherwise, we insert the new fix before
12516 MAX_MP and, if necessary, adjust the constraints on the other
12519 mp->fix_size = fix->fix_size;
12520 mp->mode = fix->mode;
12521 mp->value = fix->value;
12523 /* Not yet required for a backwards ref. */
12524 mp->min_address = -65536;
12526 if (max_mp == NULL)
12528 mp->max_address = max_address;
12530 mp->prev = minipool_vector_tail;
12532 if (mp->prev == NULL)
12534 minipool_vector_head = mp;
12535 minipool_vector_label = gen_label_rtx ();
12538 mp->prev->next = mp;
12540 minipool_vector_tail = mp;
12544 if (max_address > max_mp->max_address - mp->fix_size)
12545 mp->max_address = max_mp->max_address - mp->fix_size;
12547 mp->max_address = max_address;
12550 mp->prev = max_mp->prev;
12552 if (mp->prev != NULL)
12553 mp->prev->next = mp;
12555 minipool_vector_head = mp;
12558 /* Save the new entry. */
12561 /* Scan over the preceding entries and adjust their addresses as
12563 while (mp->prev != NULL
12564 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
12566 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
12574 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
12575 HOST_WIDE_INT min_address)
12577 HOST_WIDE_INT offset;
12579 /* The code below assumes these are different. */
12580 gcc_assert (mp != min_mp);
12582 if (min_mp == NULL)
12584 if (min_address > mp->min_address)
12585 mp->min_address = min_address;
12589 /* We will adjust this below if it is too loose. */
12590 mp->min_address = min_address;
12592 /* Unlink MP from its current position. Since min_mp is non-null,
12593 mp->next must be non-null. */
12594 mp->next->prev = mp->prev;
12595 if (mp->prev != NULL)
12596 mp->prev->next = mp->next;
12598 minipool_vector_head = mp->next;
12600 /* Reinsert it after MIN_MP. */
12602 mp->next = min_mp->next;
12604 if (mp->next != NULL)
12605 mp->next->prev = mp;
12607 minipool_vector_tail = mp;
12613 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
12615 mp->offset = offset;
12616 if (mp->refcount > 0)
12617 offset += mp->fix_size;
12619 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
12620 mp->next->min_address = mp->min_address + mp->fix_size;
12626 /* Add a constant to the minipool for a backward reference. Returns the
12627 node added or NULL if the constant will not fit in this pool.
12629 Note that the code for insertion for a backwards reference can be
12630 somewhat confusing because the calculated offsets for each fix do
12631 not take into account the size of the pool (which is still under
12634 add_minipool_backward_ref (Mfix *fix)
12636 /* If set, min_mp is the last pool_entry that has a lower constraint
12637 than the one we are trying to add. */
12638 Mnode *min_mp = NULL;
12639 /* This can be negative, since it is only a constraint. */
12640 HOST_WIDE_INT min_address = fix->address - fix->backwards;
12643 /* If we can't reach the current pool from this insn, or if we can't
12644 insert this entry at the end of the pool without pushing other
12645 fixes out of range, then we don't try. This ensures that we
12646 can't fail later on. */
12647 if (min_address >= minipool_barrier->address
12648 || (minipool_vector_tail->min_address + fix->fix_size
12649 >= minipool_barrier->address))
12652 /* Scan the pool to see if a constant with the same value has
12653 already been added. While we are doing this, also note the
12654 location where we must insert the constant if it doesn't already
12656 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
12658 if (GET_CODE (fix->value) == GET_CODE (mp->value)
12659 && fix->mode == mp->mode
12660 && (GET_CODE (fix->value) != CODE_LABEL
12661 || (CODE_LABEL_NUMBER (fix->value)
12662 == CODE_LABEL_NUMBER (mp->value)))
12663 && rtx_equal_p (fix->value, mp->value)
12664 /* Check that there is enough slack to move this entry to the
12665 end of the table (this is conservative). */
12666 && (mp->max_address
12667 > (minipool_barrier->address
12668 + minipool_vector_tail->offset
12669 + minipool_vector_tail->fix_size)))
12672 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
12675 if (min_mp != NULL)
12676 mp->min_address += fix->fix_size;
12679 /* Note the insertion point if necessary. */
12680 if (mp->min_address < min_address)
12682 /* For now, we do not allow the insertion of 8-byte alignment
12683 requiring nodes anywhere but at the start of the pool. */
12684 if (ARM_DOUBLEWORD_ALIGN
12685 && fix->fix_size >= 8 && mp->fix_size < 8)
12690 else if (mp->max_address
12691 < minipool_barrier->address + mp->offset + fix->fix_size)
12693 /* Inserting before this entry would push the fix beyond
12694 its maximum address (which can happen if we have
12695 re-located a forwards fix); force the new fix to come
12697 if (ARM_DOUBLEWORD_ALIGN
12698 && fix->fix_size >= 8 && mp->fix_size < 8)
12703 min_address = mp->min_address + fix->fix_size;
12706 /* Do not insert a non-8-byte aligned quantity before 8-byte
12707 aligned quantities. */
12708 else if (ARM_DOUBLEWORD_ALIGN
12709 && fix->fix_size < 8
12710 && mp->fix_size >= 8)
12713 min_address = mp->min_address + fix->fix_size;
12718 /* We need to create a new entry. */
12720 mp->fix_size = fix->fix_size;
12721 mp->mode = fix->mode;
12722 mp->value = fix->value;
12724 mp->max_address = minipool_barrier->address + 65536;
12726 mp->min_address = min_address;
12728 if (min_mp == NULL)
12731 mp->next = minipool_vector_head;
12733 if (mp->next == NULL)
12735 minipool_vector_tail = mp;
12736 minipool_vector_label = gen_label_rtx ();
12739 mp->next->prev = mp;
12741 minipool_vector_head = mp;
12745 mp->next = min_mp->next;
12749 if (mp->next != NULL)
12750 mp->next->prev = mp;
12752 minipool_vector_tail = mp;
12755 /* Save the new entry. */
12763 /* Scan over the following entries and adjust their offsets. */
12764 while (mp->next != NULL)
12766 if (mp->next->min_address < mp->min_address + mp->fix_size)
12767 mp->next->min_address = mp->min_address + mp->fix_size;
12770 mp->next->offset = mp->offset + mp->fix_size;
12772 mp->next->offset = mp->offset;
12781 assign_minipool_offsets (Mfix *barrier)
12783 HOST_WIDE_INT offset = 0;
12786 minipool_barrier = barrier;
12788 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
12790 mp->offset = offset;
12792 if (mp->refcount > 0)
12793 offset += mp->fix_size;
12797 /* Output the literal table */
12799 dump_minipool (rtx scan)
12805 if (ARM_DOUBLEWORD_ALIGN)
12806 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
12807 if (mp->refcount > 0 && mp->fix_size >= 8)
12814 fprintf (dump_file,
12815 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
12816 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
12818 scan = emit_label_after (gen_label_rtx (), scan);
12819 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
12820 scan = emit_label_after (minipool_vector_label, scan);
12822 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
12824 if (mp->refcount > 0)
12828 fprintf (dump_file,
12829 ";; Offset %u, min %ld, max %ld ",
12830 (unsigned) mp->offset, (unsigned long) mp->min_address,
12831 (unsigned long) mp->max_address);
12832 arm_print_value (dump_file, mp->value);
12833 fputc ('\n', dump_file);
12836 switch (mp->fix_size)
12838 #ifdef HAVE_consttable_1
12840 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
12844 #ifdef HAVE_consttable_2
12846 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
12850 #ifdef HAVE_consttable_4
12852 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
12856 #ifdef HAVE_consttable_8
12858 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
12862 #ifdef HAVE_consttable_16
12864 scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
12869 gcc_unreachable ();
12877 minipool_vector_head = minipool_vector_tail = NULL;
12878 scan = emit_insn_after (gen_consttable_end (), scan);
12879 scan = emit_barrier_after (scan);
12882 /* Return the cost of forcibly inserting a barrier after INSN. */
12884 arm_barrier_cost (rtx insn)
12886 /* Basing the location of the pool on the loop depth is preferable,
12887 but at the moment, the basic block information seems to be
12888 corrupt by this stage of the compilation. */
12889 int base_cost = 50;
12890 rtx next = next_nonnote_insn (insn);
12892 if (next != NULL && GET_CODE (next) == CODE_LABEL)
12895 switch (GET_CODE (insn))
12898 /* It will always be better to place the table before the label, rather
12907 return base_cost - 10;
12910 return base_cost + 10;
12914 /* Find the best place in the insn stream in the range
12915 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
12916 Create the barrier by inserting a jump and add a new fix entry for
12919 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
12921 HOST_WIDE_INT count = 0;
12923 rtx from = fix->insn;
12924 /* The instruction after which we will insert the jump. */
12925 rtx selected = NULL;
12927 /* The address at which the jump instruction will be placed. */
12928 HOST_WIDE_INT selected_address;
12930 HOST_WIDE_INT max_count = max_address - fix->address;
12931 rtx label = gen_label_rtx ();
12933 selected_cost = arm_barrier_cost (from);
12934 selected_address = fix->address;
12936 while (from && count < max_count)
12941 /* This code shouldn't have been called if there was a natural barrier
12943 gcc_assert (GET_CODE (from) != BARRIER);
12945 /* Count the length of this insn. This must stay in sync with the
12946 code that pushes minipool fixes. */
12947 if (LABEL_P (from))
12948 count += get_label_padding (from);
12950 count += get_attr_length (from);
12952 /* If there is a jump table, add its length. */
12953 tmp = is_jump_table (from);
12956 count += get_jump_table_size (tmp);
12958 /* Jump tables aren't in a basic block, so base the cost on
12959 the dispatch insn. If we select this location, we will
12960 still put the pool after the table. */
12961 new_cost = arm_barrier_cost (from);
12963 if (count < max_count
12964 && (!selected || new_cost <= selected_cost))
12967 selected_cost = new_cost;
12968 selected_address = fix->address + count;
12971 /* Continue after the dispatch table. */
12972 from = NEXT_INSN (tmp);
12976 new_cost = arm_barrier_cost (from);
12978 if (count < max_count
12979 && (!selected || new_cost <= selected_cost))
12982 selected_cost = new_cost;
12983 selected_address = fix->address + count;
12986 from = NEXT_INSN (from);
12989 /* Make sure that we found a place to insert the jump. */
12990 gcc_assert (selected);
12992 /* Make sure we do not split a call and its corresponding
12993 CALL_ARG_LOCATION note. */
12994 if (CALL_P (selected))
12996 rtx next = NEXT_INSN (selected);
12997 if (next && NOTE_P (next)
12998 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
13002 /* Create a new JUMP_INSN that branches around a barrier. */
13003 from = emit_jump_insn_after (gen_jump (label), selected);
13004 JUMP_LABEL (from) = label;
13005 barrier = emit_barrier_after (from);
13006 emit_label_after (label, barrier);
13008 /* Create a minipool barrier entry for the new barrier. */
13009 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
13010 new_fix->insn = barrier;
13011 new_fix->address = selected_address;
13012 new_fix->next = fix->next;
13013 fix->next = new_fix;
13018 /* Record that there is a natural barrier in the insn stream at
13021 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
13023 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
13026 fix->address = address;
13029 if (minipool_fix_head != NULL)
13030 minipool_fix_tail->next = fix;
13032 minipool_fix_head = fix;
13034 minipool_fix_tail = fix;
13037 /* Record INSN, which will need fixing up to load a value from the
13038 minipool. ADDRESS is the offset of the insn since the start of the
13039 function; LOC is a pointer to the part of the insn which requires
13040 fixing; VALUE is the constant that must be loaded, which is of type
13043 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
13044 enum machine_mode mode, rtx value)
13046 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
13049 fix->address = address;
13052 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
13053 fix->value = value;
13054 fix->forwards = get_attr_pool_range (insn);
13055 fix->backwards = get_attr_neg_pool_range (insn);
13056 fix->minipool = NULL;
13058 /* If an insn doesn't have a range defined for it, then it isn't
13059 expecting to be reworked by this code. Better to stop now than
13060 to generate duff assembly code. */
13061 gcc_assert (fix->forwards || fix->backwards);
13063 /* If an entry requires 8-byte alignment then assume all constant pools
13064 require 4 bytes of padding. Trying to do this later on a per-pool
13065 basis is awkward because existing pool entries have to be modified. */
13066 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8)
13071 fprintf (dump_file,
13072 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
13073 GET_MODE_NAME (mode),
13074 INSN_UID (insn), (unsigned long) address,
13075 -1 * (long)fix->backwards, (long)fix->forwards);
13076 arm_print_value (dump_file, fix->value);
13077 fprintf (dump_file, "\n");
13080 /* Add it to the chain of fixes. */
13083 if (minipool_fix_head != NULL)
13084 minipool_fix_tail->next = fix;
13086 minipool_fix_head = fix;
13088 minipool_fix_tail = fix;
13091 /* Return the cost of synthesizing a 64-bit constant VAL inline.
13092 Returns the number of insns needed, or 99 if we don't know how to
13095 arm_const_double_inline_cost (rtx val)
13097 rtx lowpart, highpart;
13098 enum machine_mode mode;
13100 mode = GET_MODE (val);
13102 if (mode == VOIDmode)
13105 gcc_assert (GET_MODE_SIZE (mode) == 8);
13107 lowpart = gen_lowpart (SImode, val);
13108 highpart = gen_highpart_mode (SImode, mode, val);
13110 gcc_assert (GET_CODE (lowpart) == CONST_INT);
13111 gcc_assert (GET_CODE (highpart) == CONST_INT);
13113 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
13114 NULL_RTX, NULL_RTX, 0, 0)
13115 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
13116 NULL_RTX, NULL_RTX, 0, 0));
13119 /* Return true if it is worthwhile to split a 64-bit constant into two
13120 32-bit operations. This is the case if optimizing for size, or
13121 if we have load delay slots, or if one 32-bit part can be done with
13122 a single data operation. */
13124 arm_const_double_by_parts (rtx val)
13126 enum machine_mode mode = GET_MODE (val);
13129 if (optimize_size || arm_ld_sched)
13132 if (mode == VOIDmode)
13135 part = gen_highpart_mode (SImode, mode, val);
13137 gcc_assert (GET_CODE (part) == CONST_INT);
13139 if (const_ok_for_arm (INTVAL (part))
13140 || const_ok_for_arm (~INTVAL (part)))
13143 part = gen_lowpart (SImode, val);
13145 gcc_assert (GET_CODE (part) == CONST_INT);
13147 if (const_ok_for_arm (INTVAL (part))
13148 || const_ok_for_arm (~INTVAL (part)))
13154 /* Return true if it is possible to inline both the high and low parts
13155 of a 64-bit constant into 32-bit data processing instructions. */
13157 arm_const_double_by_immediates (rtx val)
13159 enum machine_mode mode = GET_MODE (val);
13162 if (mode == VOIDmode)
13165 part = gen_highpart_mode (SImode, mode, val);
13167 gcc_assert (GET_CODE (part) == CONST_INT);
13169 if (!const_ok_for_arm (INTVAL (part)))
13172 part = gen_lowpart (SImode, val);
13174 gcc_assert (GET_CODE (part) == CONST_INT);
13176 if (!const_ok_for_arm (INTVAL (part)))
13182 /* Scan INSN and note any of its operands that need fixing.
13183 If DO_PUSHES is false we do not actually push any of the fixups
13184 needed. The function returns TRUE if any fixups were needed/pushed.
13185 This is used by arm_memory_load_p() which needs to know about loads
13186 of constants that will be converted into minipool loads. */
13188 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
13190 bool result = false;
13193 extract_insn (insn);
13195 if (!constrain_operands (1))
13196 fatal_insn_not_found (insn);
13198 if (recog_data.n_alternatives == 0)
13201 /* Fill in recog_op_alt with information about the constraints of
13203 preprocess_constraints ();
13205 for (opno = 0; opno < recog_data.n_operands; opno++)
13207 /* Things we need to fix can only occur in inputs. */
13208 if (recog_data.operand_type[opno] != OP_IN)
13211 /* If this alternative is a memory reference, then any mention
13212 of constants in this alternative is really to fool reload
13213 into allowing us to accept one there. We need to fix them up
13214 now so that we output the right code. */
13215 if (recog_op_alt[opno][which_alternative].memory_ok)
13217 rtx op = recog_data.operand[opno];
13219 if (CONSTANT_P (op))
13222 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
13223 recog_data.operand_mode[opno], op);
13226 else if (GET_CODE (op) == MEM
13227 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
13228 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
13232 rtx cop = avoid_constant_pool_reference (op);
13234 /* Casting the address of something to a mode narrower
13235 than a word can cause avoid_constant_pool_reference()
13236 to return the pool reference itself. That's no good to
13237 us here. Lets just hope that we can use the
13238 constant pool value directly. */
13240 cop = get_pool_constant (XEXP (op, 0));
13242 push_minipool_fix (insn, address,
13243 recog_data.operand_loc[opno],
13244 recog_data.operand_mode[opno], cop);
13255 /* Convert instructions to their cc-clobbering variant if possible, since
13256 that allows us to use smaller encodings. */
13259 thumb2_reorg (void)
13264 INIT_REG_SET (&live);
13266 /* We are freeing block_for_insn in the toplev to keep compatibility
13267 with old MDEP_REORGS that are not CFG based. Recompute it now. */
13268 compute_bb_for_insn ();
13275 COPY_REG_SET (&live, DF_LR_OUT (bb));
13276 df_simulate_initialize_backwards (bb, &live);
13277 FOR_BB_INSNS_REVERSE (bb, insn)
13279 if (NONJUMP_INSN_P (insn)
13280 && !REGNO_REG_SET_P (&live, CC_REGNUM))
13282 rtx pat = PATTERN (insn);
13283 if (GET_CODE (pat) == SET
13284 && low_register_operand (XEXP (pat, 0), SImode)
13285 && thumb_16bit_operator (XEXP (pat, 1), SImode)
13286 && low_register_operand (XEXP (XEXP (pat, 1), 0), SImode)
13287 && low_register_operand (XEXP (XEXP (pat, 1), 1), SImode))
13289 rtx dst = XEXP (pat, 0);
13290 rtx src = XEXP (pat, 1);
13291 rtx op0 = XEXP (src, 0);
13292 rtx op1 = (GET_RTX_CLASS (GET_CODE (src)) == RTX_COMM_ARITH
13293 ? XEXP (src, 1) : NULL);
13295 if (rtx_equal_p (dst, op0)
13296 || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
13298 rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM);
13299 rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg);
13300 rtvec vec = gen_rtvec (2, pat, clobber);
13302 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
13303 INSN_CODE (insn) = -1;
13305 /* We can also handle a commutative operation where the
13306 second operand matches the destination. */
13307 else if (op1 && rtx_equal_p (dst, op1))
13309 rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM);
13310 rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg);
13313 src = copy_rtx (src);
13314 XEXP (src, 0) = op1;
13315 XEXP (src, 1) = op0;
13316 pat = gen_rtx_SET (VOIDmode, dst, src);
13317 vec = gen_rtvec (2, pat, clobber);
13318 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
13319 INSN_CODE (insn) = -1;
13324 if (NONDEBUG_INSN_P (insn))
13325 df_simulate_one_insn_backwards (bb, insn, &live);
13329 CLEAR_REG_SET (&live);
13332 /* Gcc puts the pool in the wrong place for ARM, since we can only
13333 load addresses a limited distance around the pc. We do some
13334 special munging to move the constant pool values to the correct
13335 point in the code. */
13340 HOST_WIDE_INT address = 0;
13346 /* Ensure all insns that must be split have been split at this point.
13347 Otherwise, the pool placement code below may compute incorrect
13348 insn lengths. Note that when optimizing, all insns have already
13349 been split at this point. */
13351 split_all_insns_noflow ();
13353 minipool_fix_head = minipool_fix_tail = NULL;
13355 /* The first insn must always be a note, or the code below won't
13356 scan it properly. */
13357 insn = get_insns ();
13358 gcc_assert (GET_CODE (insn) == NOTE);
13361 /* Scan all the insns and record the operands that will need fixing. */
13362 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
13364 if (TARGET_CIRRUS_FIX_INVALID_INSNS
13365 && (arm_cirrus_insn_p (insn)
13366 || GET_CODE (insn) == JUMP_INSN
13367 || arm_memory_load_p (insn)))
13368 cirrus_reorg (insn);
13370 if (GET_CODE (insn) == BARRIER)
13371 push_minipool_barrier (insn, address);
13372 else if (INSN_P (insn))
13376 note_invalid_constants (insn, address, true);
13377 address += get_attr_length (insn);
13379 /* If the insn is a vector jump, add the size of the table
13380 and skip the table. */
13381 if ((table = is_jump_table (insn)) != NULL)
13383 address += get_jump_table_size (table);
13387 else if (LABEL_P (insn))
13388 /* Add the worst-case padding due to alignment. We don't add
13389 the _current_ padding because the minipool insertions
13390 themselves might change it. */
13391 address += get_label_padding (insn);
13394 fix = minipool_fix_head;
13396 /* Now scan the fixups and perform the required changes. */
13401 Mfix * last_added_fix;
13402 Mfix * last_barrier = NULL;
13405 /* Skip any further barriers before the next fix. */
13406 while (fix && GET_CODE (fix->insn) == BARRIER)
13409 /* No more fixes. */
13413 last_added_fix = NULL;
13415 for (ftmp = fix; ftmp; ftmp = ftmp->next)
13417 if (GET_CODE (ftmp->insn) == BARRIER)
13419 if (ftmp->address >= minipool_vector_head->max_address)
13422 last_barrier = ftmp;
13424 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
13427 last_added_fix = ftmp; /* Keep track of the last fix added. */
13430 /* If we found a barrier, drop back to that; any fixes that we
13431 could have reached but come after the barrier will now go in
13432 the next mini-pool. */
13433 if (last_barrier != NULL)
13435 /* Reduce the refcount for those fixes that won't go into this
13437 for (fdel = last_barrier->next;
13438 fdel && fdel != ftmp;
13441 fdel->minipool->refcount--;
13442 fdel->minipool = NULL;
13445 ftmp = last_barrier;
13449 /* ftmp is first fix that we can't fit into this pool and
13450 there no natural barriers that we could use. Insert a
13451 new barrier in the code somewhere between the previous
13452 fix and this one, and arrange to jump around it. */
13453 HOST_WIDE_INT max_address;
13455 /* The last item on the list of fixes must be a barrier, so
13456 we can never run off the end of the list of fixes without
13457 last_barrier being set. */
13460 max_address = minipool_vector_head->max_address;
13461 /* Check that there isn't another fix that is in range that
13462 we couldn't fit into this pool because the pool was
13463 already too large: we need to put the pool before such an
13464 instruction. The pool itself may come just after the
13465 fix because create_fix_barrier also allows space for a
13466 jump instruction. */
13467 if (ftmp->address < max_address)
13468 max_address = ftmp->address + 1;
13470 last_barrier = create_fix_barrier (last_added_fix, max_address);
13473 assign_minipool_offsets (last_barrier);
13477 if (GET_CODE (ftmp->insn) != BARRIER
13478 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
13485 /* Scan over the fixes we have identified for this pool, fixing them
13486 up and adding the constants to the pool itself. */
13487 for (this_fix = fix; this_fix && ftmp != this_fix;
13488 this_fix = this_fix->next)
13489 if (GET_CODE (this_fix->insn) != BARRIER)
13492 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
13493 minipool_vector_label),
13494 this_fix->minipool->offset);
13495 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
13498 dump_minipool (last_barrier->insn);
13502 /* From now on we must synthesize any constants that we can't handle
13503 directly. This can happen if the RTL gets split during final
13504 instruction generation. */
13505 after_arm_reorg = 1;
13507 /* Free the minipool memory. */
13508 obstack_free (&minipool_obstack, minipool_startobj);
13511 /* Routines to output assembly language. */
13513 /* If the rtx is the correct value then return the string of the number.
13514 In this way we can ensure that valid double constants are generated even
13515 when cross compiling. */
13517 fp_immediate_constant (rtx x)
13522 if (!fp_consts_inited)
13525 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
13526 for (i = 0; i < 8; i++)
13527 if (REAL_VALUES_EQUAL (r, values_fp[i]))
13528 return strings_fp[i];
13530 gcc_unreachable ();
13533 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
13534 static const char *
13535 fp_const_from_val (REAL_VALUE_TYPE *r)
13539 if (!fp_consts_inited)
13542 for (i = 0; i < 8; i++)
13543 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
13544 return strings_fp[i];
13546 gcc_unreachable ();
13549 /* Output the operands of a LDM/STM instruction to STREAM.
13550 MASK is the ARM register set mask of which only bits 0-15 are important.
13551 REG is the base register, either the frame pointer or the stack pointer,
13552 INSTR is the possibly suffixed load or store instruction.
13553 RFE is nonzero if the instruction should also copy spsr to cpsr. */
13556 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
13557 unsigned long mask, int rfe)
13560 bool not_first = FALSE;
13562 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
13563 fputc ('\t', stream);
13564 asm_fprintf (stream, instr, reg);
13565 fputc ('{', stream);
13567 for (i = 0; i <= LAST_ARM_REGNUM; i++)
13568 if (mask & (1 << i))
13571 fprintf (stream, ", ");
13573 asm_fprintf (stream, "%r", i);
13578 fprintf (stream, "}^\n");
13580 fprintf (stream, "}\n");
13584 /* Output a FLDMD instruction to STREAM.
13585 BASE if the register containing the address.
13586 REG and COUNT specify the register range.
13587 Extra registers may be added to avoid hardware bugs.
13589 We output FLDMD even for ARMv5 VFP implementations. Although
13590 FLDMD is technically not supported until ARMv6, it is believed
13591 that all VFP implementations support its use in this context. */
13594 vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
13598 /* Workaround ARM10 VFPr1 bug. */
13599 if (count == 2 && !arm_arch6)
13606 /* FLDMD may not load more than 16 doubleword registers at a time. Split the
13607 load into multiple parts if we have to handle more than 16 registers. */
13610 vfp_output_fldmd (stream, base, reg, 16);
13611 vfp_output_fldmd (stream, base, reg + 16, count - 16);
13615 fputc ('\t', stream);
13616 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
13618 for (i = reg; i < reg + count; i++)
13621 fputs (", ", stream);
13622 asm_fprintf (stream, "d%d", i);
13624 fputs ("}\n", stream);
13629 /* Output the assembly for a store multiple. */
13632 vfp_output_fstmd (rtx * operands)
13639 strcpy (pattern, "fstmfdd%?\t%m0!, {%P1");
13640 p = strlen (pattern);
13642 gcc_assert (GET_CODE (operands[1]) == REG);
13644 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
13645 for (i = 1; i < XVECLEN (operands[2], 0); i++)
13647 p += sprintf (&pattern[p], ", d%d", base + i);
13649 strcpy (&pattern[p], "}");
13651 output_asm_insn (pattern, operands);
13656 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
13657 number of bytes pushed. */
13660 vfp_emit_fstmd (int base_reg, int count)
13667 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
13668 register pairs are stored by a store multiple insn. We avoid this
13669 by pushing an extra pair. */
13670 if (count == 2 && !arm_arch6)
13672 if (base_reg == LAST_VFP_REGNUM - 3)
13677 /* FSTMD may not store more than 16 doubleword registers at once. Split
13678 larger stores into multiple parts (up to a maximum of two, in
13683 /* NOTE: base_reg is an internal register number, so each D register
13685 saved = vfp_emit_fstmd (base_reg + 32, count - 16);
13686 saved += vfp_emit_fstmd (base_reg, 16);
13690 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
13691 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
13693 reg = gen_rtx_REG (DFmode, base_reg);
13696 XVECEXP (par, 0, 0)
13697 = gen_rtx_SET (VOIDmode,
13700 gen_rtx_PRE_MODIFY (Pmode,
13703 (stack_pointer_rtx,
13706 gen_rtx_UNSPEC (BLKmode,
13707 gen_rtvec (1, reg),
13708 UNSPEC_PUSH_MULT));
13710 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
13711 plus_constant (stack_pointer_rtx, -(count * 8)));
13712 RTX_FRAME_RELATED_P (tmp) = 1;
13713 XVECEXP (dwarf, 0, 0) = tmp;
13715 tmp = gen_rtx_SET (VOIDmode,
13716 gen_frame_mem (DFmode, stack_pointer_rtx),
13718 RTX_FRAME_RELATED_P (tmp) = 1;
13719 XVECEXP (dwarf, 0, 1) = tmp;
13721 for (i = 1; i < count; i++)
13723 reg = gen_rtx_REG (DFmode, base_reg);
13725 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
13727 tmp = gen_rtx_SET (VOIDmode,
13728 gen_frame_mem (DFmode,
13729 plus_constant (stack_pointer_rtx,
13732 RTX_FRAME_RELATED_P (tmp) = 1;
13733 XVECEXP (dwarf, 0, i + 1) = tmp;
13736 par = emit_insn (par);
13737 add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf);
13738 RTX_FRAME_RELATED_P (par) = 1;
13743 /* Emit a call instruction with pattern PAT. ADDR is the address of
13744 the call target. */
13747 arm_emit_call_insn (rtx pat, rtx addr)
13751 insn = emit_call_insn (pat);
13753 /* The PIC register is live on entry to VxWorks PIC PLT entries.
13754 If the call might use such an entry, add a use of the PIC register
13755 to the instruction's CALL_INSN_FUNCTION_USAGE. */
13756 if (TARGET_VXWORKS_RTP
13758 && GET_CODE (addr) == SYMBOL_REF
13759 && (SYMBOL_REF_DECL (addr)
13760 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
13761 : !SYMBOL_REF_LOCAL_P (addr)))
13763 require_pic_register ();
13764 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
13768 /* Output a 'call' insn. */
13770 output_call (rtx *operands)
13772 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
13774 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
13775 if (REGNO (operands[0]) == LR_REGNUM)
13777 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
13778 output_asm_insn ("mov%?\t%0, %|lr", operands);
13781 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
13783 if (TARGET_INTERWORK || arm_arch4t)
13784 output_asm_insn ("bx%?\t%0", operands);
13786 output_asm_insn ("mov%?\t%|pc, %0", operands);
13791 /* Output a 'call' insn that is a reference in memory. This is
13792 disabled for ARMv5 and we prefer a blx instead because otherwise
13793 there's a significant performance overhead. */
13795 output_call_mem (rtx *operands)
13797 gcc_assert (!arm_arch5);
13798 if (TARGET_INTERWORK)
13800 output_asm_insn ("ldr%?\t%|ip, %0", operands);
13801 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
13802 output_asm_insn ("bx%?\t%|ip", operands);
13804 else if (regno_use_in (LR_REGNUM, operands[0]))
13806 /* LR is used in the memory address. We load the address in the
13807 first instruction. It's safe to use IP as the target of the
13808 load since the call will kill it anyway. */
13809 output_asm_insn ("ldr%?\t%|ip, %0", operands);
13810 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
13812 output_asm_insn ("bx%?\t%|ip", operands);
13814 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
13818 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
13819 output_asm_insn ("ldr%?\t%|pc, %0", operands);
13826 /* Output a move from arm registers to an fpa registers.
13827 OPERANDS[0] is an fpa register.
13828 OPERANDS[1] is the first registers of an arm register pair. */
13830 output_mov_long_double_fpa_from_arm (rtx *operands)
13832 int arm_reg0 = REGNO (operands[1]);
13835 gcc_assert (arm_reg0 != IP_REGNUM);
13837 ops[0] = gen_rtx_REG (SImode, arm_reg0);
13838 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
13839 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
13841 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
13842 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
13847 /* Output a move from an fpa register to arm registers.
13848 OPERANDS[0] is the first registers of an arm register pair.
13849 OPERANDS[1] is an fpa register. */
13851 output_mov_long_double_arm_from_fpa (rtx *operands)
13853 int arm_reg0 = REGNO (operands[0]);
13856 gcc_assert (arm_reg0 != IP_REGNUM);
13858 ops[0] = gen_rtx_REG (SImode, arm_reg0);
13859 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
13860 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
13862 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
13863 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
13867 /* Output a move from arm registers to arm registers of a long double
13868 OPERANDS[0] is the destination.
13869 OPERANDS[1] is the source. */
13871 output_mov_long_double_arm_from_arm (rtx *operands)
13873 /* We have to be careful here because the two might overlap. */
13874 int dest_start = REGNO (operands[0]);
13875 int src_start = REGNO (operands[1]);
13879 if (dest_start < src_start)
13881 for (i = 0; i < 3; i++)
13883 ops[0] = gen_rtx_REG (SImode, dest_start + i);
13884 ops[1] = gen_rtx_REG (SImode, src_start + i);
13885 output_asm_insn ("mov%?\t%0, %1", ops);
13890 for (i = 2; i >= 0; i--)
13892 ops[0] = gen_rtx_REG (SImode, dest_start + i);
13893 ops[1] = gen_rtx_REG (SImode, src_start + i);
13894 output_asm_insn ("mov%?\t%0, %1", ops);
13902 arm_emit_movpair (rtx dest, rtx src)
13904 /* If the src is an immediate, simplify it. */
13905 if (CONST_INT_P (src))
13907 HOST_WIDE_INT val = INTVAL (src);
13908 emit_set_insn (dest, GEN_INT (val & 0x0000ffff));
13909 if ((val >> 16) & 0x0000ffff)
13910 emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode, dest, GEN_INT (16),
13912 GEN_INT ((val >> 16) & 0x0000ffff));
13915 emit_set_insn (dest, gen_rtx_HIGH (SImode, src));
13916 emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src));
13919 /* Output a move from arm registers to an fpa registers.
13920 OPERANDS[0] is an fpa register.
13921 OPERANDS[1] is the first registers of an arm register pair. */
13923 output_mov_double_fpa_from_arm (rtx *operands)
13925 int arm_reg0 = REGNO (operands[1]);
13928 gcc_assert (arm_reg0 != IP_REGNUM);
13930 ops[0] = gen_rtx_REG (SImode, arm_reg0);
13931 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
13932 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
13933 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
13937 /* Output a move from an fpa register to arm registers.
13938 OPERANDS[0] is the first registers of an arm register pair.
13939 OPERANDS[1] is an fpa register. */
13941 output_mov_double_arm_from_fpa (rtx *operands)
13943 int arm_reg0 = REGNO (operands[0]);
13946 gcc_assert (arm_reg0 != IP_REGNUM);
13948 ops[0] = gen_rtx_REG (SImode, arm_reg0);
13949 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
13950 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
13951 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
13955 /* Output a move between double words. It must be REG<-MEM
13958 output_move_double (rtx *operands, bool emit, int *count)
13960 enum rtx_code code0 = GET_CODE (operands[0]);
13961 enum rtx_code code1 = GET_CODE (operands[1]);
13966 /* The only case when this might happen is when
13967 you are looking at the length of a DImode instruction
13968 that has an invalid constant in it. */
13969 if (code0 == REG && code1 != MEM)
13971 gcc_assert (!emit);
13978 unsigned int reg0 = REGNO (operands[0]);
13980 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
13982 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
13984 switch (GET_CODE (XEXP (operands[1], 0)))
13991 && !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0))))
13992 output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands);
13994 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
13999 gcc_assert (TARGET_LDRD);
14001 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
14008 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
14010 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
14018 output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands);
14020 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
14025 gcc_assert (TARGET_LDRD);
14027 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
14032 /* Autoicrement addressing modes should never have overlapping
14033 base and destination registers, and overlapping index registers
14034 are already prohibited, so this doesn't need to worry about
14036 otherops[0] = operands[0];
14037 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
14038 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
14040 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
14042 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
14044 /* Registers overlap so split out the increment. */
14047 output_asm_insn ("add%?\t%1, %1, %2", otherops);
14048 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
14055 /* Use a single insn if we can.
14056 FIXME: IWMMXT allows offsets larger than ldrd can
14057 handle, fix these up with a pair of ldr. */
14059 || GET_CODE (otherops[2]) != CONST_INT
14060 || (INTVAL (otherops[2]) > -256
14061 && INTVAL (otherops[2]) < 256))
14064 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
14070 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
14071 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
14081 /* Use a single insn if we can.
14082 FIXME: IWMMXT allows offsets larger than ldrd can handle,
14083 fix these up with a pair of ldr. */
14085 || GET_CODE (otherops[2]) != CONST_INT
14086 || (INTVAL (otherops[2]) > -256
14087 && INTVAL (otherops[2]) < 256))
14090 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
14096 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
14097 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
14107 /* We might be able to use ldrd %0, %1 here. However the range is
14108 different to ldr/adr, and it is broken on some ARMv7-M
14109 implementations. */
14110 /* Use the second register of the pair to avoid problematic
14112 otherops[1] = operands[1];
14114 output_asm_insn ("adr%?\t%0, %1", otherops);
14115 operands[1] = otherops[0];
14119 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands);
14121 output_asm_insn ("ldm%(ia%)\t%1, %M0", operands);
14128 /* ??? This needs checking for thumb2. */
14130 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
14131 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
14133 otherops[0] = operands[0];
14134 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
14135 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
14137 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
14139 if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
14141 switch ((int) INTVAL (otherops[2]))
14145 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
14151 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
14157 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
14161 otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1);
14162 operands[1] = otherops[0];
14164 && (GET_CODE (otherops[2]) == REG
14166 || (GET_CODE (otherops[2]) == CONST_INT
14167 && INTVAL (otherops[2]) > -256
14168 && INTVAL (otherops[2]) < 256)))
14170 if (reg_overlap_mentioned_p (operands[0],
14174 /* Swap base and index registers over to
14175 avoid a conflict. */
14177 otherops[1] = otherops[2];
14180 /* If both registers conflict, it will usually
14181 have been fixed by a splitter. */
14182 if (reg_overlap_mentioned_p (operands[0], otherops[2])
14183 || (fix_cm3_ldrd && reg0 == REGNO (otherops[1])))
14187 output_asm_insn ("add%?\t%0, %1, %2", otherops);
14188 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands);
14195 otherops[0] = operands[0];
14197 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
14202 if (GET_CODE (otherops[2]) == CONST_INT)
14206 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
14207 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
14209 output_asm_insn ("add%?\t%0, %1, %2", otherops);
14215 output_asm_insn ("add%?\t%0, %1, %2", otherops);
14221 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
14228 return "ldr%(d%)\t%0, [%1]";
14230 return "ldm%(ia%)\t%1, %M0";
14234 otherops[1] = adjust_address (operands[1], SImode, 4);
14235 /* Take care of overlapping base/data reg. */
14236 if (reg_mentioned_p (operands[0], operands[1]))
14240 output_asm_insn ("ldr%?\t%0, %1", otherops);
14241 output_asm_insn ("ldr%?\t%0, %1", operands);
14251 output_asm_insn ("ldr%?\t%0, %1", operands);
14252 output_asm_insn ("ldr%?\t%0, %1", otherops);
14262 /* Constraints should ensure this. */
14263 gcc_assert (code0 == MEM && code1 == REG);
14264 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
14266 switch (GET_CODE (XEXP (operands[0], 0)))
14272 output_asm_insn ("str%(d%)\t%1, [%m0]", operands);
14274 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
14279 gcc_assert (TARGET_LDRD);
14281 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
14288 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
14290 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
14298 output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands);
14300 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
14305 gcc_assert (TARGET_LDRD);
14307 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
14312 otherops[0] = operands[1];
14313 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
14314 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
14316 /* IWMMXT allows offsets larger than ldrd can handle,
14317 fix these up with a pair of ldr. */
14319 && GET_CODE (otherops[2]) == CONST_INT
14320 && (INTVAL(otherops[2]) <= -256
14321 || INTVAL(otherops[2]) >= 256))
14323 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
14327 output_asm_insn ("str%?\t%0, [%1, %2]!", otherops);
14328 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
14337 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
14338 output_asm_insn ("str%?\t%0, [%1], %2", otherops);
14344 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
14347 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
14352 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
14357 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
14358 if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
14360 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
14364 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
14371 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
14378 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
14383 && (GET_CODE (otherops[2]) == REG
14385 || (GET_CODE (otherops[2]) == CONST_INT
14386 && INTVAL (otherops[2]) > -256
14387 && INTVAL (otherops[2]) < 256)))
14389 otherops[0] = operands[1];
14390 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
14392 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
14398 otherops[0] = adjust_address (operands[0], SImode, 4);
14399 otherops[1] = operands[1];
14402 output_asm_insn ("str%?\t%1, %0", operands);
14403 output_asm_insn ("str%?\t%H1, %0", otherops);
14413 /* Output a move, load or store for quad-word vectors in ARM registers. Only
14414 handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
14417 output_move_quad (rtx *operands)
14419 if (REG_P (operands[0]))
14421 /* Load, or reg->reg move. */
14423 if (MEM_P (operands[1]))
14425 switch (GET_CODE (XEXP (operands[1], 0)))
14428 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
14433 output_asm_insn ("adr%?\t%0, %1", operands);
14434 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
14438 gcc_unreachable ();
14446 gcc_assert (REG_P (operands[1]));
14448 dest = REGNO (operands[0]);
14449 src = REGNO (operands[1]);
14451 /* This seems pretty dumb, but hopefully GCC won't try to do it
14454 for (i = 0; i < 4; i++)
14456 ops[0] = gen_rtx_REG (SImode, dest + i);
14457 ops[1] = gen_rtx_REG (SImode, src + i);
14458 output_asm_insn ("mov%?\t%0, %1", ops);
14461 for (i = 3; i >= 0; i--)
14463 ops[0] = gen_rtx_REG (SImode, dest + i);
14464 ops[1] = gen_rtx_REG (SImode, src + i);
14465 output_asm_insn ("mov%?\t%0, %1", ops);
14471 gcc_assert (MEM_P (operands[0]));
14472 gcc_assert (REG_P (operands[1]));
14473 gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0]));
14475 switch (GET_CODE (XEXP (operands[0], 0)))
14478 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
14482 gcc_unreachable ();
14489 /* Output a VFP load or store instruction. */
14492 output_move_vfp (rtx *operands)
14494 rtx reg, mem, addr, ops[2];
14495 int load = REG_P (operands[0]);
14496 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
14497 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
14500 enum machine_mode mode;
14502 reg = operands[!load];
14503 mem = operands[load];
14505 mode = GET_MODE (reg);
14507 gcc_assert (REG_P (reg));
14508 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
14509 gcc_assert (mode == SFmode
14513 || (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
14514 gcc_assert (MEM_P (mem));
14516 addr = XEXP (mem, 0);
14518 switch (GET_CODE (addr))
14521 templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
14522 ops[0] = XEXP (addr, 0);
14527 templ = "f%smia%c%%?\t%%0!, {%%%s1}%s";
14528 ops[0] = XEXP (addr, 0);
14533 templ = "f%s%c%%?\t%%%s0, %%1%s";
14539 sprintf (buff, templ,
14540 load ? "ld" : "st",
14543 integer_p ? "\t%@ int" : "");
14544 output_asm_insn (buff, ops);
14549 /* Output a Neon quad-word load or store, or a load or store for
14550 larger structure modes.
14552 WARNING: The ordering of elements is weird in big-endian mode,
14553 because we use VSTM, as required by the EABI. GCC RTL defines
14554 element ordering based on in-memory order. This can be differ
14555 from the architectural ordering of elements within a NEON register.
14556 The intrinsics defined in arm_neon.h use the NEON register element
14557 ordering, not the GCC RTL element ordering.
14559 For example, the in-memory ordering of a big-endian a quadword
14560 vector with 16-bit elements when stored from register pair {d0,d1}
14561 will be (lowest address first, d0[N] is NEON register element N):
14563 [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]]
14565 When necessary, quadword registers (dN, dN+1) are moved to ARM
14566 registers from rN in the order:
14568 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
14570 So that STM/LDM can be used on vectors in ARM registers, and the
14571 same memory layout will result as if VSTM/VLDM were used. */
14574 output_move_neon (rtx *operands)
14576 rtx reg, mem, addr, ops[2];
14577 int regno, load = REG_P (operands[0]);
14580 enum machine_mode mode;
14582 reg = operands[!load];
14583 mem = operands[load];
14585 mode = GET_MODE (reg);
14587 gcc_assert (REG_P (reg));
14588 regno = REGNO (reg);
14589 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno)
14590 || NEON_REGNO_OK_FOR_QUAD (regno));
14591 gcc_assert (VALID_NEON_DREG_MODE (mode)
14592 || VALID_NEON_QREG_MODE (mode)
14593 || VALID_NEON_STRUCT_MODE (mode));
14594 gcc_assert (MEM_P (mem));
14596 addr = XEXP (mem, 0);
14598 /* Strip off const from addresses like (const (plus (...))). */
14599 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS)
14600 addr = XEXP (addr, 0);
14602 switch (GET_CODE (addr))
14605 templ = "v%smia%%?\t%%0!, %%h1";
14606 ops[0] = XEXP (addr, 0);
14611 /* FIXME: We should be using vld1/vst1 here in BE mode? */
14612 templ = "v%smdb%%?\t%%0!, %%h1";
14613 ops[0] = XEXP (addr, 0);
14618 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
14619 gcc_unreachable ();
14624 int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2;
14627 for (i = 0; i < nregs; i++)
14629 /* We're only using DImode here because it's a convenient size. */
14630 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i);
14631 ops[1] = adjust_address (mem, DImode, 8 * i);
14632 if (reg_overlap_mentioned_p (ops[0], mem))
14634 gcc_assert (overlap == -1);
14639 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
14640 output_asm_insn (buff, ops);
14645 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap);
14646 ops[1] = adjust_address (mem, SImode, 8 * overlap);
14647 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
14648 output_asm_insn (buff, ops);
14655 templ = "v%smia%%?\t%%m0, %%h1";
14660 sprintf (buff, templ, load ? "ld" : "st");
14661 output_asm_insn (buff, ops);
14666 /* Compute and return the length of neon_mov<mode>, where <mode> is
14667 one of VSTRUCT modes: EI, OI, CI or XI. */
14669 arm_attr_length_move_neon (rtx insn)
14671 rtx reg, mem, addr;
14673 enum machine_mode mode;
14675 extract_insn_cached (insn);
14677 if (REG_P (recog_data.operand[0]) && REG_P (recog_data.operand[1]))
14679 mode = GET_MODE (recog_data.operand[0]);
14690 gcc_unreachable ();
14694 load = REG_P (recog_data.operand[0]);
14695 reg = recog_data.operand[!load];
14696 mem = recog_data.operand[load];
14698 gcc_assert (MEM_P (mem));
14700 mode = GET_MODE (reg);
14701 addr = XEXP (mem, 0);
14703 /* Strip off const from addresses like (const (plus (...))). */
14704 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS)
14705 addr = XEXP (addr, 0);
14707 if (GET_CODE (addr) == LABEL_REF || GET_CODE (addr) == PLUS)
14709 int insns = HARD_REGNO_NREGS (REGNO (reg), mode) / 2;
14716 /* Return nonzero if the offset in the address is an immediate. Otherwise,
14720 arm_address_offset_is_imm (rtx insn)
14724 extract_insn_cached (insn);
14726 if (REG_P (recog_data.operand[0]))
14729 mem = recog_data.operand[0];
14731 gcc_assert (MEM_P (mem));
14733 addr = XEXP (mem, 0);
14735 if (GET_CODE (addr) == REG
14736 || (GET_CODE (addr) == PLUS
14737 && GET_CODE (XEXP (addr, 0)) == REG
14738 && GET_CODE (XEXP (addr, 1)) == CONST_INT))
14744 /* Output an ADD r, s, #n where n may be too big for one instruction.
14745 If adding zero to one register, output nothing. */
14747 output_add_immediate (rtx *operands)
14749 HOST_WIDE_INT n = INTVAL (operands[2]);
14751 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
14754 output_multi_immediate (operands,
14755 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
14758 output_multi_immediate (operands,
14759 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
14766 /* Output a multiple immediate operation.
14767 OPERANDS is the vector of operands referred to in the output patterns.
14768 INSTR1 is the output pattern to use for the first constant.
14769 INSTR2 is the output pattern to use for subsequent constants.
14770 IMMED_OP is the index of the constant slot in OPERANDS.
14771 N is the constant value. */
14772 static const char *
14773 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
14774 int immed_op, HOST_WIDE_INT n)
14776 #if HOST_BITS_PER_WIDE_INT > 32
14782 /* Quick and easy output. */
14783 operands[immed_op] = const0_rtx;
14784 output_asm_insn (instr1, operands);
14789 const char * instr = instr1;
14791 /* Note that n is never zero here (which would give no output). */
14792 for (i = 0; i < 32; i += 2)
14796 operands[immed_op] = GEN_INT (n & (255 << i));
14797 output_asm_insn (instr, operands);
14807 /* Return the name of a shifter operation. */
14808 static const char *
14809 arm_shift_nmem(enum rtx_code code)
14814 return ARM_LSL_NAME;
14830 /* Return the appropriate ARM instruction for the operation code.
14831 The returned result should not be overwritten. OP is the rtx of the
14832 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
14835 arithmetic_instr (rtx op, int shift_first_arg)
14837 switch (GET_CODE (op))
14843 return shift_first_arg ? "rsb" : "sub";
14858 return arm_shift_nmem(GET_CODE(op));
14861 gcc_unreachable ();
14865 /* Ensure valid constant shifts and return the appropriate shift mnemonic
14866 for the operation code. The returned result should not be overwritten.
14867 OP is the rtx code of the shift.
14868 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
14870 static const char *
14871 shift_op (rtx op, HOST_WIDE_INT *amountp)
14874 enum rtx_code code = GET_CODE (op);
14879 if (!CONST_INT_P (XEXP (op, 1)))
14881 output_operand_lossage ("invalid shift operand");
14886 *amountp = 32 - INTVAL (XEXP (op, 1));
14894 mnem = arm_shift_nmem(code);
14895 if (CONST_INT_P (XEXP (op, 1)))
14897 *amountp = INTVAL (XEXP (op, 1));
14899 else if (REG_P (XEXP (op, 1)))
14906 output_operand_lossage ("invalid shift operand");
14912 /* We never have to worry about the amount being other than a
14913 power of 2, since this case can never be reloaded from a reg. */
14914 if (!CONST_INT_P (XEXP (op, 1)))
14916 output_operand_lossage ("invalid shift operand");
14920 *amountp = INTVAL (XEXP (op, 1)) & 0xFFFFFFFF;
14922 /* Amount must be a power of two. */
14923 if (*amountp & (*amountp - 1))
14925 output_operand_lossage ("invalid shift operand");
14929 *amountp = int_log2 (*amountp);
14930 return ARM_LSL_NAME;
14933 output_operand_lossage ("invalid shift operand");
14937 /* This is not 100% correct, but follows from the desire to merge
14938 multiplication by a power of 2 with the recognizer for a
14939 shift. >=32 is not a valid shift for "lsl", so we must try and
14940 output a shift that produces the correct arithmetical result.
14941 Using lsr #32 is identical except for the fact that the carry bit
14942 is not set correctly if we set the flags; but we never use the
14943 carry bit from such an operation, so we can ignore that. */
14944 if (code == ROTATERT)
14945 /* Rotate is just modulo 32. */
14947 else if (*amountp != (*amountp & 31))
14949 if (code == ASHIFT)
14954 /* Shifts of 0 are no-ops. */
14961 /* Obtain the shift from the POWER of two. */
14963 static HOST_WIDE_INT
14964 int_log2 (HOST_WIDE_INT power)
14966 HOST_WIDE_INT shift = 0;
14968 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
14970 gcc_assert (shift <= 31);
14977 /* Output a .ascii pseudo-op, keeping track of lengths. This is
14978 because /bin/as is horribly restrictive. The judgement about
14979 whether or not each character is 'printable' (and can be output as
14980 is) or not (and must be printed with an octal escape) must be made
14981 with reference to the *host* character set -- the situation is
14982 similar to that discussed in the comments above pp_c_char in
14983 c-pretty-print.c. */
14985 #define MAX_ASCII_LEN 51
14988 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
14991 int len_so_far = 0;
14993 fputs ("\t.ascii\t\"", stream);
14995 for (i = 0; i < len; i++)
14999 if (len_so_far >= MAX_ASCII_LEN)
15001 fputs ("\"\n\t.ascii\t\"", stream);
15007 if (c == '\\' || c == '\"')
15009 putc ('\\', stream);
15017 fprintf (stream, "\\%03o", c);
15022 fputs ("\"\n", stream);
15025 /* Compute the register save mask for registers 0 through 12
15026 inclusive. This code is used by arm_compute_save_reg_mask. */
15028 static unsigned long
15029 arm_compute_save_reg0_reg12_mask (void)
15031 unsigned long func_type = arm_current_func_type ();
15032 unsigned long save_reg_mask = 0;
15035 if (IS_INTERRUPT (func_type))
15037 unsigned int max_reg;
15038 /* Interrupt functions must not corrupt any registers,
15039 even call clobbered ones. If this is a leaf function
15040 we can just examine the registers used by the RTL, but
15041 otherwise we have to assume that whatever function is
15042 called might clobber anything, and so we have to save
15043 all the call-clobbered registers as well. */
15044 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
15045 /* FIQ handlers have registers r8 - r12 banked, so
15046 we only need to check r0 - r7, Normal ISRs only
15047 bank r14 and r15, so we must check up to r12.
15048 r13 is the stack pointer which is always preserved,
15049 so we do not need to consider it here. */
15054 for (reg = 0; reg <= max_reg; reg++)
15055 if (df_regs_ever_live_p (reg)
15056 || (! current_function_is_leaf && call_used_regs[reg]))
15057 save_reg_mask |= (1 << reg);
15059 /* Also save the pic base register if necessary. */
15061 && !TARGET_SINGLE_PIC_BASE
15062 && arm_pic_register != INVALID_REGNUM
15063 && crtl->uses_pic_offset_table)
15064 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
15066 else if (IS_VOLATILE(func_type))
15068 /* For noreturn functions we historically omitted register saves
15069 altogether. However this really messes up debugging. As a
15070 compromise save just the frame pointers. Combined with the link
15071 register saved elsewhere this should be sufficient to get
15073 if (frame_pointer_needed)
15074 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
15075 if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM))
15076 save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
15077 if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM))
15078 save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM;
15082 /* In the normal case we only need to save those registers
15083 which are call saved and which are used by this function. */
15084 for (reg = 0; reg <= 11; reg++)
15085 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
15086 save_reg_mask |= (1 << reg);
15088 /* Handle the frame pointer as a special case. */
15089 if (frame_pointer_needed)
15090 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
15092 /* If we aren't loading the PIC register,
15093 don't stack it even though it may be live. */
15095 && !TARGET_SINGLE_PIC_BASE
15096 && arm_pic_register != INVALID_REGNUM
15097 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)
15098 || crtl->uses_pic_offset_table))
15099 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
15101 /* The prologue will copy SP into R0, so save it. */
15102 if (IS_STACKALIGN (func_type))
15103 save_reg_mask |= 1;
15106 /* Save registers so the exception handler can modify them. */
15107 if (crtl->calls_eh_return)
15113 reg = EH_RETURN_DATA_REGNO (i);
15114 if (reg == INVALID_REGNUM)
15116 save_reg_mask |= 1 << reg;
15120 return save_reg_mask;
15124 /* Compute the number of bytes used to store the static chain register on the
15125 stack, above the stack frame. We need to know this accurately to get the
15126 alignment of the rest of the stack frame correct. */
15128 static int arm_compute_static_chain_stack_bytes (void)
15130 unsigned long func_type = arm_current_func_type ();
15131 int static_chain_stack_bytes = 0;
15133 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM &&
15134 IS_NESTED (func_type) &&
15135 df_regs_ever_live_p (3) && crtl->args.pretend_args_size == 0)
15136 static_chain_stack_bytes = 4;
15138 return static_chain_stack_bytes;
15142 /* Compute a bit mask of which registers need to be
15143 saved on the stack for the current function.
15144 This is used by arm_get_frame_offsets, which may add extra registers. */
15146 static unsigned long
15147 arm_compute_save_reg_mask (void)
15149 unsigned int save_reg_mask = 0;
15150 unsigned long func_type = arm_current_func_type ();
15153 if (IS_NAKED (func_type))
15154 /* This should never really happen. */
15157 /* If we are creating a stack frame, then we must save the frame pointer,
15158 IP (which will hold the old stack pointer), LR and the PC. */
15159 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
15161 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
15164 | (1 << PC_REGNUM);
15166 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
15168 /* Decide if we need to save the link register.
15169 Interrupt routines have their own banked link register,
15170 so they never need to save it.
15171 Otherwise if we do not use the link register we do not need to save
15172 it. If we are pushing other registers onto the stack however, we
15173 can save an instruction in the epilogue by pushing the link register
15174 now and then popping it back into the PC. This incurs extra memory
15175 accesses though, so we only do it when optimizing for size, and only
15176 if we know that we will not need a fancy return sequence. */
15177 if (df_regs_ever_live_p (LR_REGNUM)
15180 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
15181 && !crtl->calls_eh_return))
15182 save_reg_mask |= 1 << LR_REGNUM;
15184 if (cfun->machine->lr_save_eliminated)
15185 save_reg_mask &= ~ (1 << LR_REGNUM);
15187 if (TARGET_REALLY_IWMMXT
15188 && ((bit_count (save_reg_mask)
15189 + ARM_NUM_INTS (crtl->args.pretend_args_size +
15190 arm_compute_static_chain_stack_bytes())
15193 /* The total number of registers that are going to be pushed
15194 onto the stack is odd. We need to ensure that the stack
15195 is 64-bit aligned before we start to save iWMMXt registers,
15196 and also before we start to create locals. (A local variable
15197 might be a double or long long which we will load/store using
15198 an iWMMXt instruction). Therefore we need to push another
15199 ARM register, so that the stack will be 64-bit aligned. We
15200 try to avoid using the arg registers (r0 -r3) as they might be
15201 used to pass values in a tail call. */
15202 for (reg = 4; reg <= 12; reg++)
15203 if ((save_reg_mask & (1 << reg)) == 0)
15207 save_reg_mask |= (1 << reg);
15210 cfun->machine->sibcall_blocked = 1;
15211 save_reg_mask |= (1 << 3);
15215 /* We may need to push an additional register for use initializing the
15216 PIC base register. */
15217 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
15218 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
15220 reg = thumb_find_work_register (1 << 4);
15221 if (!call_used_regs[reg])
15222 save_reg_mask |= (1 << reg);
15225 return save_reg_mask;
15229 /* Compute a bit mask of which registers need to be
15230 saved on the stack for the current function. */
15231 static unsigned long
15232 thumb1_compute_save_reg_mask (void)
15234 unsigned long mask;
15238 for (reg = 0; reg < 12; reg ++)
15239 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
15243 && !TARGET_SINGLE_PIC_BASE
15244 && arm_pic_register != INVALID_REGNUM
15245 && crtl->uses_pic_offset_table)
15246 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
15248 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
15249 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
15250 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
15252 /* LR will also be pushed if any lo regs are pushed. */
15253 if (mask & 0xff || thumb_force_lr_save ())
15254 mask |= (1 << LR_REGNUM);
15256 /* Make sure we have a low work register if we need one.
15257 We will need one if we are going to push a high register,
15258 but we are not currently intending to push a low register. */
15259 if ((mask & 0xff) == 0
15260 && ((mask & 0x0f00) || TARGET_BACKTRACE))
15262 /* Use thumb_find_work_register to choose which register
15263 we will use. If the register is live then we will
15264 have to push it. Use LAST_LO_REGNUM as our fallback
15265 choice for the register to select. */
15266 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
15267 /* Make sure the register returned by thumb_find_work_register is
15268 not part of the return value. */
15269 if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ())
15270 reg = LAST_LO_REGNUM;
15272 if (! call_used_regs[reg])
15276 /* The 504 below is 8 bytes less than 512 because there are two possible
15277 alignment words. We can't tell here if they will be present or not so we
15278 have to play it safe and assume that they are. */
15279 if ((CALLER_INTERWORKING_SLOT_SIZE +
15280 ROUND_UP_WORD (get_frame_size ()) +
15281 crtl->outgoing_args_size) >= 504)
15283 /* This is the same as the code in thumb1_expand_prologue() which
15284 determines which register to use for stack decrement. */
15285 for (reg = LAST_ARG_REGNUM + 1; reg <= LAST_LO_REGNUM; reg++)
15286 if (mask & (1 << reg))
15289 if (reg > LAST_LO_REGNUM)
15291 /* Make sure we have a register available for stack decrement. */
15292 mask |= 1 << LAST_LO_REGNUM;
15300 /* Return the number of bytes required to save VFP registers. */
15302 arm_get_vfp_saved_size (void)
15304 unsigned int regno;
15309 /* Space for saved VFP registers. */
15310 if (TARGET_HARD_FLOAT && TARGET_VFP)
15313 for (regno = FIRST_VFP_REGNUM;
15314 regno < LAST_VFP_REGNUM;
15317 if ((!df_regs_ever_live_p (regno) || call_used_regs[regno])
15318 && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1]))
15322 /* Workaround ARM10 VFPr1 bug. */
15323 if (count == 2 && !arm_arch6)
15325 saved += count * 8;
15334 if (count == 2 && !arm_arch6)
15336 saved += count * 8;
15343 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
15344 everything bar the final return instruction. */
15346 output_return_instruction (rtx operand, int really_return, int reverse)
15348 char conditional[10];
15351 unsigned long live_regs_mask;
15352 unsigned long func_type;
15353 arm_stack_offsets *offsets;
15355 func_type = arm_current_func_type ();
15357 if (IS_NAKED (func_type))
15360 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
15362 /* If this function was declared non-returning, and we have
15363 found a tail call, then we have to trust that the called
15364 function won't return. */
15369 /* Otherwise, trap an attempted return by aborting. */
15371 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
15373 assemble_external_libcall (ops[1]);
15374 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
15380 gcc_assert (!cfun->calls_alloca || really_return);
15382 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
15384 cfun->machine->return_used_this_function = 1;
15386 offsets = arm_get_frame_offsets ();
15387 live_regs_mask = offsets->saved_regs_mask;
15389 if (live_regs_mask)
15391 const char * return_reg;
15393 /* If we do not have any special requirements for function exit
15394 (e.g. interworking) then we can load the return address
15395 directly into the PC. Otherwise we must load it into LR. */
15397 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
15398 return_reg = reg_names[PC_REGNUM];
15400 return_reg = reg_names[LR_REGNUM];
15402 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
15404 /* There are three possible reasons for the IP register
15405 being saved. 1) a stack frame was created, in which case
15406 IP contains the old stack pointer, or 2) an ISR routine
15407 corrupted it, or 3) it was saved to align the stack on
15408 iWMMXt. In case 1, restore IP into SP, otherwise just
15410 if (frame_pointer_needed)
15412 live_regs_mask &= ~ (1 << IP_REGNUM);
15413 live_regs_mask |= (1 << SP_REGNUM);
15416 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
15419 /* On some ARM architectures it is faster to use LDR rather than
15420 LDM to load a single register. On other architectures, the
15421 cost is the same. In 26 bit mode, or for exception handlers,
15422 we have to use LDM to load the PC so that the CPSR is also
15424 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
15425 if (live_regs_mask == (1U << reg))
15428 if (reg <= LAST_ARM_REGNUM
15429 && (reg != LR_REGNUM
15431 || ! IS_INTERRUPT (func_type)))
15433 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
15434 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
15441 /* Generate the load multiple instruction to restore the
15442 registers. Note we can get here, even if
15443 frame_pointer_needed is true, but only if sp already
15444 points to the base of the saved core registers. */
15445 if (live_regs_mask & (1 << SP_REGNUM))
15447 unsigned HOST_WIDE_INT stack_adjust;
15449 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
15450 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
15452 if (stack_adjust && arm_arch5 && TARGET_ARM)
15453 if (TARGET_UNIFIED_ASM)
15454 sprintf (instr, "ldmib%s\t%%|sp, {", conditional);
15456 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
15459 /* If we can't use ldmib (SA110 bug),
15460 then try to pop r3 instead. */
15462 live_regs_mask |= 1 << 3;
15464 if (TARGET_UNIFIED_ASM)
15465 sprintf (instr, "ldmfd%s\t%%|sp, {", conditional);
15467 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
15471 if (TARGET_UNIFIED_ASM)
15472 sprintf (instr, "pop%s\t{", conditional);
15474 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
15476 p = instr + strlen (instr);
15478 for (reg = 0; reg <= SP_REGNUM; reg++)
15479 if (live_regs_mask & (1 << reg))
15481 int l = strlen (reg_names[reg]);
15487 memcpy (p, ", ", 2);
15491 memcpy (p, "%|", 2);
15492 memcpy (p + 2, reg_names[reg], l);
15496 if (live_regs_mask & (1 << LR_REGNUM))
15498 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
15499 /* If returning from an interrupt, restore the CPSR. */
15500 if (IS_INTERRUPT (func_type))
15507 output_asm_insn (instr, & operand);
15509 /* See if we need to generate an extra instruction to
15510 perform the actual function return. */
15512 && func_type != ARM_FT_INTERWORKED
15513 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
15515 /* The return has already been handled
15516 by loading the LR into the PC. */
15523 switch ((int) ARM_FUNC_TYPE (func_type))
15527 /* ??? This is wrong for unified assembly syntax. */
15528 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
15531 case ARM_FT_INTERWORKED:
15532 sprintf (instr, "bx%s\t%%|lr", conditional);
15535 case ARM_FT_EXCEPTION:
15536 /* ??? This is wrong for unified assembly syntax. */
15537 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
15541 /* Use bx if it's available. */
15542 if (arm_arch5 || arm_arch4t)
15543 sprintf (instr, "bx%s\t%%|lr", conditional);
15545 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
15549 output_asm_insn (instr, & operand);
15555 /* Write the function name into the code section, directly preceding
15556 the function prologue.
15558 Code will be output similar to this:
15560 .ascii "arm_poke_function_name", 0
15563 .word 0xff000000 + (t1 - t0)
15564 arm_poke_function_name
15566 stmfd sp!, {fp, ip, lr, pc}
15569 When performing a stack backtrace, code can inspect the value
15570 of 'pc' stored at 'fp' + 0. If the trace function then looks
15571 at location pc - 12 and the top 8 bits are set, then we know
15572 that there is a function name embedded immediately preceding this
15573 location and has length ((pc[-3]) & 0xff000000).
15575 We assume that pc is declared as a pointer to an unsigned long.
15577 It is of no benefit to output the function name if we are assembling
15578 a leaf function. These function types will not contain a stack
15579 backtrace structure, therefore it is not possible to determine the
15582 arm_poke_function_name (FILE *stream, const char *name)
15584 unsigned long alignlength;
15585 unsigned long length;
15588 length = strlen (name) + 1;
15589 alignlength = ROUND_UP_WORD (length);
15591 ASM_OUTPUT_ASCII (stream, name, length);
15592 ASM_OUTPUT_ALIGN (stream, 2);
15593 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
15594 assemble_aligned_integer (UNITS_PER_WORD, x);
15597 /* Place some comments into the assembler stream
15598 describing the current function. */
15600 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
15602 unsigned long func_type;
15604 /* ??? Do we want to print some of the below anyway? */
15608 /* Sanity check. */
15609 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
15611 func_type = arm_current_func_type ();
15613 switch ((int) ARM_FUNC_TYPE (func_type))
15616 case ARM_FT_NORMAL:
15618 case ARM_FT_INTERWORKED:
15619 asm_fprintf (f, "\t%@ Function supports interworking.\n");
15622 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
15625 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
15627 case ARM_FT_EXCEPTION:
15628 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
15632 if (IS_NAKED (func_type))
15633 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
15635 if (IS_VOLATILE (func_type))
15636 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
15638 if (IS_NESTED (func_type))
15639 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
15640 if (IS_STACKALIGN (func_type))
15641 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
15643 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
15645 crtl->args.pretend_args_size, frame_size);
15647 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
15648 frame_pointer_needed,
15649 cfun->machine->uses_anonymous_args);
15651 if (cfun->machine->lr_save_eliminated)
15652 asm_fprintf (f, "\t%@ link register save eliminated.\n");
15654 if (crtl->calls_eh_return)
15655 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
15660 arm_output_epilogue (rtx sibling)
15663 unsigned long saved_regs_mask;
15664 unsigned long func_type;
15665 /* Floats_offset is the offset from the "virtual" frame. In an APCS
15666 frame that is $fp + 4 for a non-variadic function. */
15667 int floats_offset = 0;
15669 FILE * f = asm_out_file;
15670 unsigned int lrm_count = 0;
15671 int really_return = (sibling == NULL);
15673 arm_stack_offsets *offsets;
15675 /* If we have already generated the return instruction
15676 then it is futile to generate anything else. */
15677 if (use_return_insn (FALSE, sibling) &&
15678 (cfun->machine->return_used_this_function != 0))
15681 func_type = arm_current_func_type ();
15683 if (IS_NAKED (func_type))
15684 /* Naked functions don't have epilogues. */
15687 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
15691 /* A volatile function should never return. Call abort. */
15692 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
15693 assemble_external_libcall (op);
15694 output_asm_insn ("bl\t%a0", &op);
15699 /* If we are throwing an exception, then we really must be doing a
15700 return, so we can't tail-call. */
15701 gcc_assert (!crtl->calls_eh_return || really_return);
15703 offsets = arm_get_frame_offsets ();
15704 saved_regs_mask = offsets->saved_regs_mask;
15707 lrm_count = bit_count (saved_regs_mask);
15709 floats_offset = offsets->saved_args;
15710 /* Compute how far away the floats will be. */
15711 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
15712 if (saved_regs_mask & (1 << reg))
15713 floats_offset += 4;
15715 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
15717 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
15718 int vfp_offset = offsets->frame;
15720 if (TARGET_FPA_EMU2)
15722 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
15723 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
15725 floats_offset += 12;
15726 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
15727 reg, FP_REGNUM, floats_offset - vfp_offset);
15732 start_reg = LAST_FPA_REGNUM;
15734 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
15736 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
15738 floats_offset += 12;
15740 /* We can't unstack more than four registers at once. */
15741 if (start_reg - reg == 3)
15743 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
15744 reg, FP_REGNUM, floats_offset - vfp_offset);
15745 start_reg = reg - 1;
15750 if (reg != start_reg)
15751 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
15752 reg + 1, start_reg - reg,
15753 FP_REGNUM, floats_offset - vfp_offset);
15754 start_reg = reg - 1;
15758 /* Just in case the last register checked also needs unstacking. */
15759 if (reg != start_reg)
15760 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
15761 reg + 1, start_reg - reg,
15762 FP_REGNUM, floats_offset - vfp_offset);
15765 if (TARGET_HARD_FLOAT && TARGET_VFP)
15769 /* The fldmd insns do not have base+offset addressing
15770 modes, so we use IP to hold the address. */
15771 saved_size = arm_get_vfp_saved_size ();
15773 if (saved_size > 0)
15775 floats_offset += saved_size;
15776 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
15777 FP_REGNUM, floats_offset - vfp_offset);
15779 start_reg = FIRST_VFP_REGNUM;
15780 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
15782 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
15783 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
15785 if (start_reg != reg)
15786 vfp_output_fldmd (f, IP_REGNUM,
15787 (start_reg - FIRST_VFP_REGNUM) / 2,
15788 (reg - start_reg) / 2);
15789 start_reg = reg + 2;
15792 if (start_reg != reg)
15793 vfp_output_fldmd (f, IP_REGNUM,
15794 (start_reg - FIRST_VFP_REGNUM) / 2,
15795 (reg - start_reg) / 2);
15800 /* The frame pointer is guaranteed to be non-double-word aligned.
15801 This is because it is set to (old_stack_pointer - 4) and the
15802 old_stack_pointer was double word aligned. Thus the offset to
15803 the iWMMXt registers to be loaded must also be non-double-word
15804 sized, so that the resultant address *is* double-word aligned.
15805 We can ignore floats_offset since that was already included in
15806 the live_regs_mask. */
15807 lrm_count += (lrm_count % 2 ? 2 : 1);
15809 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
15810 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
15812 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
15813 reg, FP_REGNUM, lrm_count * 4);
15818 /* saved_regs_mask should contain the IP, which at the time of stack
15819 frame generation actually contains the old stack pointer. So a
15820 quick way to unwind the stack is just pop the IP register directly
15821 into the stack pointer. */
15822 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
15823 saved_regs_mask &= ~ (1 << IP_REGNUM);
15824 saved_regs_mask |= (1 << SP_REGNUM);
15826 /* There are two registers left in saved_regs_mask - LR and PC. We
15827 only need to restore the LR register (the return address), but to
15828 save time we can load it directly into the PC, unless we need a
15829 special function exit sequence, or we are not really returning. */
15831 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
15832 && !crtl->calls_eh_return)
15833 /* Delete the LR from the register mask, so that the LR on
15834 the stack is loaded into the PC in the register mask. */
15835 saved_regs_mask &= ~ (1 << LR_REGNUM);
15837 saved_regs_mask &= ~ (1 << PC_REGNUM);
15839 /* We must use SP as the base register, because SP is one of the
15840 registers being restored. If an interrupt or page fault
15841 happens in the ldm instruction, the SP might or might not
15842 have been restored. That would be bad, as then SP will no
15843 longer indicate the safe area of stack, and we can get stack
15844 corruption. Using SP as the base register means that it will
15845 be reset correctly to the original value, should an interrupt
15846 occur. If the stack pointer already points at the right
15847 place, then omit the subtraction. */
15848 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
15849 || cfun->calls_alloca)
15850 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
15851 4 * bit_count (saved_regs_mask));
15852 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
15854 if (IS_INTERRUPT (func_type))
15855 /* Interrupt handlers will have pushed the
15856 IP onto the stack, so restore it now. */
15857 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
15861 /* This branch is executed for ARM mode (non-apcs frames) and
15862 Thumb-2 mode. Frame layout is essentially the same for those
15863 cases, except that in ARM mode frame pointer points to the
15864 first saved register, while in Thumb-2 mode the frame pointer points
15865 to the last saved register.
15867 It is possible to make frame pointer point to last saved
15868 register in both cases, and remove some conditionals below.
15869 That means that fp setup in prologue would be just "mov fp, sp"
15870 and sp restore in epilogue would be just "mov sp, fp", whereas
15871 now we have to use add/sub in those cases. However, the value
15872 of that would be marginal, as both mov and add/sub are 32-bit
15873 in ARM mode, and it would require extra conditionals
15874 in arm_expand_prologue to distingish ARM-apcs-frame case
15875 (where frame pointer is required to point at first register)
15876 and ARM-non-apcs-frame. Therefore, such change is postponed
15877 until real need arise. */
15878 unsigned HOST_WIDE_INT amount;
15880 /* Restore stack pointer if necessary. */
15881 if (TARGET_ARM && frame_pointer_needed)
15883 operands[0] = stack_pointer_rtx;
15884 operands[1] = hard_frame_pointer_rtx;
15886 operands[2] = GEN_INT (offsets->frame - offsets->saved_regs);
15887 output_add_immediate (operands);
15891 if (frame_pointer_needed)
15893 /* For Thumb-2 restore sp from the frame pointer.
15894 Operand restrictions mean we have to incrememnt FP, then copy
15896 amount = offsets->locals_base - offsets->saved_regs;
15897 operands[0] = hard_frame_pointer_rtx;
15901 unsigned long count;
15902 operands[0] = stack_pointer_rtx;
15903 amount = offsets->outgoing_args - offsets->saved_regs;
15904 /* pop call clobbered registers if it avoids a
15905 separate stack adjustment. */
15906 count = offsets->saved_regs - offsets->saved_args;
15909 && !crtl->calls_eh_return
15910 && bit_count(saved_regs_mask) * 4 == count
15911 && !IS_INTERRUPT (func_type)
15912 && !IS_STACKALIGN (func_type)
15913 && !crtl->tail_call_emit)
15915 unsigned long mask;
15916 /* Preserve return values, of any size. */
15917 mask = (1 << ((arm_size_return_regs() + 3) / 4)) - 1;
15919 mask &= ~saved_regs_mask;
15921 while (bit_count (mask) * 4 > amount)
15923 while ((mask & (1 << reg)) == 0)
15925 mask &= ~(1 << reg);
15927 if (bit_count (mask) * 4 == amount) {
15929 saved_regs_mask |= mask;
15936 operands[1] = operands[0];
15937 operands[2] = GEN_INT (amount);
15938 output_add_immediate (operands);
15940 if (frame_pointer_needed)
15941 asm_fprintf (f, "\tmov\t%r, %r\n",
15942 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
15945 if (TARGET_FPA_EMU2)
15947 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
15948 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
15949 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
15954 start_reg = FIRST_FPA_REGNUM;
15956 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
15958 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
15960 if (reg - start_reg == 3)
15962 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
15963 start_reg, SP_REGNUM);
15964 start_reg = reg + 1;
15969 if (reg != start_reg)
15970 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
15971 start_reg, reg - start_reg,
15974 start_reg = reg + 1;
15978 /* Just in case the last register checked also needs unstacking. */
15979 if (reg != start_reg)
15980 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
15981 start_reg, reg - start_reg, SP_REGNUM);
15984 if (TARGET_HARD_FLOAT && TARGET_VFP)
15986 int end_reg = LAST_VFP_REGNUM + 1;
15988 /* Scan the registers in reverse order. We need to match
15989 any groupings made in the prologue and generate matching
15991 for (reg = LAST_VFP_REGNUM - 1; reg >= FIRST_VFP_REGNUM; reg -= 2)
15993 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
15994 && (!df_regs_ever_live_p (reg + 1)
15995 || call_used_regs[reg + 1]))
15997 if (end_reg > reg + 2)
15998 vfp_output_fldmd (f, SP_REGNUM,
15999 (reg + 2 - FIRST_VFP_REGNUM) / 2,
16000 (end_reg - (reg + 2)) / 2);
16004 if (end_reg > reg + 2)
16005 vfp_output_fldmd (f, SP_REGNUM, 0,
16006 (end_reg - (reg + 2)) / 2);
16010 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
16011 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
16012 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
16014 /* If we can, restore the LR into the PC. */
16015 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
16016 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
16017 && !IS_STACKALIGN (func_type)
16019 && crtl->args.pretend_args_size == 0
16020 && saved_regs_mask & (1 << LR_REGNUM)
16021 && !crtl->calls_eh_return)
16023 saved_regs_mask &= ~ (1 << LR_REGNUM);
16024 saved_regs_mask |= (1 << PC_REGNUM);
16025 rfe = IS_INTERRUPT (func_type);
16030 /* Load the registers off the stack. If we only have one register
16031 to load use the LDR instruction - it is faster. For Thumb-2
16032 always use pop and the assembler will pick the best instruction.*/
16033 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
16034 && !IS_INTERRUPT(func_type))
16036 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
16038 else if (saved_regs_mask)
16040 if (saved_regs_mask & (1 << SP_REGNUM))
16041 /* Note - write back to the stack register is not enabled
16042 (i.e. "ldmfd sp!..."). We know that the stack pointer is
16043 in the list of registers and if we add writeback the
16044 instruction becomes UNPREDICTABLE. */
16045 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
16047 else if (TARGET_ARM)
16048 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
16051 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
16054 if (crtl->args.pretend_args_size)
16056 /* Unwind the pre-pushed regs. */
16057 operands[0] = operands[1] = stack_pointer_rtx;
16058 operands[2] = GEN_INT (crtl->args.pretend_args_size);
16059 output_add_immediate (operands);
16063 /* We may have already restored PC directly from the stack. */
16064 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
16067 /* Stack adjustment for exception handler. */
16068 if (crtl->calls_eh_return)
16069 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
16070 ARM_EH_STACKADJ_REGNUM);
16072 /* Generate the return instruction. */
16073 switch ((int) ARM_FUNC_TYPE (func_type))
16077 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
16080 case ARM_FT_EXCEPTION:
16081 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
16084 case ARM_FT_INTERWORKED:
16085 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
16089 if (IS_STACKALIGN (func_type))
16091 /* See comment in arm_expand_prologue. */
16092 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
16094 if (arm_arch5 || arm_arch4t)
16095 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
16097 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
16105 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
16106 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
16108 arm_stack_offsets *offsets;
16114 /* Emit any call-via-reg trampolines that are needed for v4t support
16115 of call_reg and call_value_reg type insns. */
16116 for (regno = 0; regno < LR_REGNUM; regno++)
16118 rtx label = cfun->machine->call_via[regno];
16122 switch_to_section (function_section (current_function_decl));
16123 targetm.asm_out.internal_label (asm_out_file, "L",
16124 CODE_LABEL_NUMBER (label));
16125 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
16129 /* ??? Probably not safe to set this here, since it assumes that a
16130 function will be emitted as assembly immediately after we generate
16131 RTL for it. This does not happen for inline functions. */
16132 cfun->machine->return_used_this_function = 0;
16134 else /* TARGET_32BIT */
16136 /* We need to take into account any stack-frame rounding. */
16137 offsets = arm_get_frame_offsets ();
16139 gcc_assert (!use_return_insn (FALSE, NULL)
16140 || (cfun->machine->return_used_this_function != 0)
16141 || offsets->saved_regs == offsets->outgoing_args
16142 || frame_pointer_needed);
16144 /* Reset the ARM-specific per-function variables. */
16145 after_arm_reorg = 0;
16149 /* Generate and emit an insn that we will recognize as a push_multi.
16150 Unfortunately, since this insn does not reflect very well the actual
16151 semantics of the operation, we need to annotate the insn for the benefit
16152 of DWARF2 frame unwind information. */
16154 emit_multi_reg_push (unsigned long mask)
16157 int num_dwarf_regs;
16161 int dwarf_par_index;
16164 for (i = 0; i <= LAST_ARM_REGNUM; i++)
16165 if (mask & (1 << i))
16168 gcc_assert (num_regs && num_regs <= 16);
16170 /* We don't record the PC in the dwarf frame information. */
16171 num_dwarf_regs = num_regs;
16172 if (mask & (1 << PC_REGNUM))
16175 /* For the body of the insn we are going to generate an UNSPEC in
16176 parallel with several USEs. This allows the insn to be recognized
16177 by the push_multi pattern in the arm.md file.
16179 The body of the insn looks something like this:
16182 (set (mem:BLK (pre_modify:SI (reg:SI sp)
16183 (const_int:SI <num>)))
16184 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
16190 For the frame note however, we try to be more explicit and actually
16191 show each register being stored into the stack frame, plus a (single)
16192 decrement of the stack pointer. We do it this way in order to be
16193 friendly to the stack unwinding code, which only wants to see a single
16194 stack decrement per instruction. The RTL we generate for the note looks
16195 something like this:
16198 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
16199 (set (mem:SI (reg:SI sp)) (reg:SI r4))
16200 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX))
16201 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY))
16205 FIXME:: In an ideal world the PRE_MODIFY would not exist and
16206 instead we'd have a parallel expression detailing all
16207 the stores to the various memory addresses so that debug
16208 information is more up-to-date. Remember however while writing
16209 this to take care of the constraints with the push instruction.
16211 Note also that this has to be taken care of for the VFP registers.
16213 For more see PR43399. */
16215 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
16216 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
16217 dwarf_par_index = 1;
16219 for (i = 0; i <= LAST_ARM_REGNUM; i++)
16221 if (mask & (1 << i))
16223 reg = gen_rtx_REG (SImode, i);
16225 XVECEXP (par, 0, 0)
16226 = gen_rtx_SET (VOIDmode,
16229 gen_rtx_PRE_MODIFY (Pmode,
16232 (stack_pointer_rtx,
16235 gen_rtx_UNSPEC (BLKmode,
16236 gen_rtvec (1, reg),
16237 UNSPEC_PUSH_MULT));
16239 if (i != PC_REGNUM)
16241 tmp = gen_rtx_SET (VOIDmode,
16242 gen_frame_mem (SImode, stack_pointer_rtx),
16244 RTX_FRAME_RELATED_P (tmp) = 1;
16245 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
16253 for (j = 1, i++; j < num_regs; i++)
16255 if (mask & (1 << i))
16257 reg = gen_rtx_REG (SImode, i);
16259 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
16261 if (i != PC_REGNUM)
16264 = gen_rtx_SET (VOIDmode,
16267 plus_constant (stack_pointer_rtx,
16270 RTX_FRAME_RELATED_P (tmp) = 1;
16271 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
16278 par = emit_insn (par);
16280 tmp = gen_rtx_SET (VOIDmode,
16282 plus_constant (stack_pointer_rtx, -4 * num_regs));
16283 RTX_FRAME_RELATED_P (tmp) = 1;
16284 XVECEXP (dwarf, 0, 0) = tmp;
16286 add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf);
16291 /* Calculate the size of the return value that is passed in registers. */
16293 arm_size_return_regs (void)
16295 enum machine_mode mode;
16297 if (crtl->return_rtx != 0)
16298 mode = GET_MODE (crtl->return_rtx);
16300 mode = DECL_MODE (DECL_RESULT (current_function_decl));
16302 return GET_MODE_SIZE (mode);
16306 emit_sfm (int base_reg, int count)
16313 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
16314 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
16316 reg = gen_rtx_REG (XFmode, base_reg++);
16318 XVECEXP (par, 0, 0)
16319 = gen_rtx_SET (VOIDmode,
16322 gen_rtx_PRE_MODIFY (Pmode,
16325 (stack_pointer_rtx,
16328 gen_rtx_UNSPEC (BLKmode,
16329 gen_rtvec (1, reg),
16330 UNSPEC_PUSH_MULT));
16331 tmp = gen_rtx_SET (VOIDmode,
16332 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
16333 RTX_FRAME_RELATED_P (tmp) = 1;
16334 XVECEXP (dwarf, 0, 1) = tmp;
16336 for (i = 1; i < count; i++)
16338 reg = gen_rtx_REG (XFmode, base_reg++);
16339 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
16341 tmp = gen_rtx_SET (VOIDmode,
16342 gen_frame_mem (XFmode,
16343 plus_constant (stack_pointer_rtx,
16346 RTX_FRAME_RELATED_P (tmp) = 1;
16347 XVECEXP (dwarf, 0, i + 1) = tmp;
16350 tmp = gen_rtx_SET (VOIDmode,
16352 plus_constant (stack_pointer_rtx, -12 * count));
16354 RTX_FRAME_RELATED_P (tmp) = 1;
16355 XVECEXP (dwarf, 0, 0) = tmp;
16357 par = emit_insn (par);
16358 add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf);
16364 /* Return true if the current function needs to save/restore LR. */
16367 thumb_force_lr_save (void)
16369 return !cfun->machine->lr_save_eliminated
16370 && (!leaf_function_p ()
16371 || thumb_far_jump_used_p ()
16372 || df_regs_ever_live_p (LR_REGNUM));
16376 /* Return true if r3 is used by any of the tail call insns in the
16377 current function. */
16380 any_sibcall_uses_r3 (void)
16385 if (!crtl->tail_call_emit)
16387 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
16388 if (e->flags & EDGE_SIBCALL)
16390 rtx call = BB_END (e->src);
16391 if (!CALL_P (call))
16392 call = prev_nonnote_nondebug_insn (call);
16393 gcc_assert (CALL_P (call) && SIBLING_CALL_P (call));
16394 if (find_regno_fusage (call, USE, 3))
16401 /* Compute the distance from register FROM to register TO.
16402 These can be the arg pointer (26), the soft frame pointer (25),
16403 the stack pointer (13) or the hard frame pointer (11).
16404 In thumb mode r7 is used as the soft frame pointer, if needed.
16405 Typical stack layout looks like this:
16407 old stack pointer -> | |
16410 | | saved arguments for
16411 | | vararg functions
16414 hard FP & arg pointer -> | | \
16422 soft frame pointer -> | | /
16427 locals base pointer -> | | /
16432 current stack pointer -> | | /
16435 For a given function some or all of these stack components
16436 may not be needed, giving rise to the possibility of
16437 eliminating some of the registers.
16439 The values returned by this function must reflect the behavior
16440 of arm_expand_prologue() and arm_compute_save_reg_mask().
16442 The sign of the number returned reflects the direction of stack
16443 growth, so the values are positive for all eliminations except
16444 from the soft frame pointer to the hard frame pointer.
16446 SFP may point just inside the local variables block to ensure correct
16450 /* Calculate stack offsets. These are used to calculate register elimination
16451 offsets and in prologue/epilogue code. Also calculates which registers
16452 should be saved. */
16454 static arm_stack_offsets *
16455 arm_get_frame_offsets (void)
16457 struct arm_stack_offsets *offsets;
16458 unsigned long func_type;
16462 HOST_WIDE_INT frame_size;
16465 offsets = &cfun->machine->stack_offsets;
16467 /* We need to know if we are a leaf function. Unfortunately, it
16468 is possible to be called after start_sequence has been called,
16469 which causes get_insns to return the insns for the sequence,
16470 not the function, which will cause leaf_function_p to return
16471 the incorrect result.
16473 to know about leaf functions once reload has completed, and the
16474 frame size cannot be changed after that time, so we can safely
16475 use the cached value. */
16477 if (reload_completed)
16480 /* Initially this is the size of the local variables. It will translated
16481 into an offset once we have determined the size of preceding data. */
16482 frame_size = ROUND_UP_WORD (get_frame_size ());
16484 leaf = leaf_function_p ();
16486 /* Space for variadic functions. */
16487 offsets->saved_args = crtl->args.pretend_args_size;
16489 /* In Thumb mode this is incorrect, but never used. */
16490 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0) +
16491 arm_compute_static_chain_stack_bytes();
16495 unsigned int regno;
16497 offsets->saved_regs_mask = arm_compute_save_reg_mask ();
16498 core_saved = bit_count (offsets->saved_regs_mask) * 4;
16499 saved = core_saved;
16501 /* We know that SP will be doubleword aligned on entry, and we must
16502 preserve that condition at any subroutine call. We also require the
16503 soft frame pointer to be doubleword aligned. */
16505 if (TARGET_REALLY_IWMMXT)
16507 /* Check for the call-saved iWMMXt registers. */
16508 for (regno = FIRST_IWMMXT_REGNUM;
16509 regno <= LAST_IWMMXT_REGNUM;
16511 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
16515 func_type = arm_current_func_type ();
16516 if (! IS_VOLATILE (func_type))
16518 /* Space for saved FPA registers. */
16519 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
16520 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
16523 /* Space for saved VFP registers. */
16524 if (TARGET_HARD_FLOAT && TARGET_VFP)
16525 saved += arm_get_vfp_saved_size ();
16528 else /* TARGET_THUMB1 */
16530 offsets->saved_regs_mask = thumb1_compute_save_reg_mask ();
16531 core_saved = bit_count (offsets->saved_regs_mask) * 4;
16532 saved = core_saved;
16533 if (TARGET_BACKTRACE)
16537 /* Saved registers include the stack frame. */
16538 offsets->saved_regs = offsets->saved_args + saved +
16539 arm_compute_static_chain_stack_bytes();
16540 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
16541 /* A leaf function does not need any stack alignment if it has nothing
16543 if (leaf && frame_size == 0
16544 /* However if it calls alloca(), we have a dynamically allocated
16545 block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
16546 && ! cfun->calls_alloca)
16548 offsets->outgoing_args = offsets->soft_frame;
16549 offsets->locals_base = offsets->soft_frame;
16553 /* Ensure SFP has the correct alignment. */
16554 if (ARM_DOUBLEWORD_ALIGN
16555 && (offsets->soft_frame & 7))
16557 offsets->soft_frame += 4;
16558 /* Try to align stack by pushing an extra reg. Don't bother doing this
16559 when there is a stack frame as the alignment will be rolled into
16560 the normal stack adjustment. */
16561 if (frame_size + crtl->outgoing_args_size == 0)
16565 /* If it is safe to use r3, then do so. This sometimes
16566 generates better code on Thumb-2 by avoiding the need to
16567 use 32-bit push/pop instructions. */
16568 if (! any_sibcall_uses_r3 ()
16569 && arm_size_return_regs () <= 12
16570 && (offsets->saved_regs_mask & (1 << 3)) == 0)
16575 for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
16577 if ((offsets->saved_regs_mask & (1 << i)) == 0)
16586 offsets->saved_regs += 4;
16587 offsets->saved_regs_mask |= (1 << reg);
16592 offsets->locals_base = offsets->soft_frame + frame_size;
16593 offsets->outgoing_args = (offsets->locals_base
16594 + crtl->outgoing_args_size);
16596 if (ARM_DOUBLEWORD_ALIGN)
16598 /* Ensure SP remains doubleword aligned. */
16599 if (offsets->outgoing_args & 7)
16600 offsets->outgoing_args += 4;
16601 gcc_assert (!(offsets->outgoing_args & 7));
16608 /* Calculate the relative offsets for the different stack pointers. Positive
16609 offsets are in the direction of stack growth. */
16612 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
16614 arm_stack_offsets *offsets;
16616 offsets = arm_get_frame_offsets ();
16618 /* OK, now we have enough information to compute the distances.
16619 There must be an entry in these switch tables for each pair
16620 of registers in ELIMINABLE_REGS, even if some of the entries
16621 seem to be redundant or useless. */
16624 case ARG_POINTER_REGNUM:
16627 case THUMB_HARD_FRAME_POINTER_REGNUM:
16630 case FRAME_POINTER_REGNUM:
16631 /* This is the reverse of the soft frame pointer
16632 to hard frame pointer elimination below. */
16633 return offsets->soft_frame - offsets->saved_args;
16635 case ARM_HARD_FRAME_POINTER_REGNUM:
16636 /* This is only non-zero in the case where the static chain register
16637 is stored above the frame. */
16638 return offsets->frame - offsets->saved_args - 4;
16640 case STACK_POINTER_REGNUM:
16641 /* If nothing has been pushed on the stack at all
16642 then this will return -4. This *is* correct! */
16643 return offsets->outgoing_args - (offsets->saved_args + 4);
16646 gcc_unreachable ();
16648 gcc_unreachable ();
16650 case FRAME_POINTER_REGNUM:
16653 case THUMB_HARD_FRAME_POINTER_REGNUM:
16656 case ARM_HARD_FRAME_POINTER_REGNUM:
16657 /* The hard frame pointer points to the top entry in the
16658 stack frame. The soft frame pointer to the bottom entry
16659 in the stack frame. If there is no stack frame at all,
16660 then they are identical. */
16662 return offsets->frame - offsets->soft_frame;
16664 case STACK_POINTER_REGNUM:
16665 return offsets->outgoing_args - offsets->soft_frame;
16668 gcc_unreachable ();
16670 gcc_unreachable ();
16673 /* You cannot eliminate from the stack pointer.
16674 In theory you could eliminate from the hard frame
16675 pointer to the stack pointer, but this will never
16676 happen, since if a stack frame is not needed the
16677 hard frame pointer will never be used. */
16678 gcc_unreachable ();
16682 /* Given FROM and TO register numbers, say whether this elimination is
16683 allowed. Frame pointer elimination is automatically handled.
16685 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
16686 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
16687 pointer, we must eliminate FRAME_POINTER_REGNUM into
16688 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
16689 ARG_POINTER_REGNUM. */
16692 arm_can_eliminate (const int from, const int to)
16694 return ((to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) ? false :
16695 (to == STACK_POINTER_REGNUM && frame_pointer_needed) ? false :
16696 (to == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? false :
16697 (to == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? false :
16701 /* Emit RTL to save coprocessor registers on function entry. Returns the
16702 number of bytes pushed. */
16705 arm_save_coproc_regs(void)
16707 int saved_size = 0;
16709 unsigned start_reg;
16712 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
16713 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
16715 insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
16716 insn = gen_rtx_MEM (V2SImode, insn);
16717 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
16718 RTX_FRAME_RELATED_P (insn) = 1;
16722 /* Save any floating point call-saved registers used by this
16724 if (TARGET_FPA_EMU2)
16726 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
16727 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
16729 insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
16730 insn = gen_rtx_MEM (XFmode, insn);
16731 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
16732 RTX_FRAME_RELATED_P (insn) = 1;
16738 start_reg = LAST_FPA_REGNUM;
16740 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
16742 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
16744 if (start_reg - reg == 3)
16746 insn = emit_sfm (reg, 4);
16747 RTX_FRAME_RELATED_P (insn) = 1;
16749 start_reg = reg - 1;
16754 if (start_reg != reg)
16756 insn = emit_sfm (reg + 1, start_reg - reg);
16757 RTX_FRAME_RELATED_P (insn) = 1;
16758 saved_size += (start_reg - reg) * 12;
16760 start_reg = reg - 1;
16764 if (start_reg != reg)
16766 insn = emit_sfm (reg + 1, start_reg - reg);
16767 saved_size += (start_reg - reg) * 12;
16768 RTX_FRAME_RELATED_P (insn) = 1;
16771 if (TARGET_HARD_FLOAT && TARGET_VFP)
16773 start_reg = FIRST_VFP_REGNUM;
16775 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
16777 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
16778 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
16780 if (start_reg != reg)
16781 saved_size += vfp_emit_fstmd (start_reg,
16782 (reg - start_reg) / 2);
16783 start_reg = reg + 2;
16786 if (start_reg != reg)
16787 saved_size += vfp_emit_fstmd (start_reg,
16788 (reg - start_reg) / 2);
16794 /* Set the Thumb frame pointer from the stack pointer. */
16797 thumb_set_frame_pointer (arm_stack_offsets *offsets)
16799 HOST_WIDE_INT amount;
16802 amount = offsets->outgoing_args - offsets->locals_base;
16804 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
16805 stack_pointer_rtx, GEN_INT (amount)));
16808 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
16809 /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1
16810 expects the first two operands to be the same. */
16813 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
16815 hard_frame_pointer_rtx));
16819 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
16820 hard_frame_pointer_rtx,
16821 stack_pointer_rtx));
16823 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
16824 plus_constant (stack_pointer_rtx, amount));
16825 RTX_FRAME_RELATED_P (dwarf) = 1;
16826 add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
16829 RTX_FRAME_RELATED_P (insn) = 1;
16832 /* Generate the prologue instructions for entry into an ARM or Thumb-2
16835 arm_expand_prologue (void)
16840 unsigned long live_regs_mask;
16841 unsigned long func_type;
16843 int saved_pretend_args = 0;
16844 int saved_regs = 0;
16845 unsigned HOST_WIDE_INT args_to_push;
16846 arm_stack_offsets *offsets;
16848 func_type = arm_current_func_type ();
16850 /* Naked functions don't have prologues. */
16851 if (IS_NAKED (func_type))
16854 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
16855 args_to_push = crtl->args.pretend_args_size;
16857 /* Compute which register we will have to save onto the stack. */
16858 offsets = arm_get_frame_offsets ();
16859 live_regs_mask = offsets->saved_regs_mask;
16861 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
16863 if (IS_STACKALIGN (func_type))
16867 /* Handle a word-aligned stack pointer. We generate the following:
16872 <save and restore r0 in normal prologue/epilogue>
16876 The unwinder doesn't need to know about the stack realignment.
16877 Just tell it we saved SP in r0. */
16878 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
16880 r0 = gen_rtx_REG (SImode, 0);
16881 r1 = gen_rtx_REG (SImode, 1);
16883 insn = emit_insn (gen_movsi (r0, stack_pointer_rtx));
16884 RTX_FRAME_RELATED_P (insn) = 1;
16885 add_reg_note (insn, REG_CFA_REGISTER, NULL);
16887 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
16889 /* ??? The CFA changes here, which may cause GDB to conclude that it
16890 has entered a different function. That said, the unwind info is
16891 correct, individually, before and after this instruction because
16892 we've described the save of SP, which will override the default
16893 handling of SP as restoring from the CFA. */
16894 emit_insn (gen_movsi (stack_pointer_rtx, r1));
16897 /* For APCS frames, if IP register is clobbered
16898 when creating frame, save that register in a special
16900 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
16902 if (IS_INTERRUPT (func_type))
16904 /* Interrupt functions must not corrupt any registers.
16905 Creating a frame pointer however, corrupts the IP
16906 register, so we must push it first. */
16907 emit_multi_reg_push (1 << IP_REGNUM);
16909 /* Do not set RTX_FRAME_RELATED_P on this insn.
16910 The dwarf stack unwinding code only wants to see one
16911 stack decrement per function, and this is not it. If
16912 this instruction is labeled as being part of the frame
16913 creation sequence then dwarf2out_frame_debug_expr will
16914 die when it encounters the assignment of IP to FP
16915 later on, since the use of SP here establishes SP as
16916 the CFA register and not IP.
16918 Anyway this instruction is not really part of the stack
16919 frame creation although it is part of the prologue. */
16921 else if (IS_NESTED (func_type))
16923 /* The Static chain register is the same as the IP register
16924 used as a scratch register during stack frame creation.
16925 To get around this need to find somewhere to store IP
16926 whilst the frame is being created. We try the following
16929 1. The last argument register.
16930 2. A slot on the stack above the frame. (This only
16931 works if the function is not a varargs function).
16932 3. Register r3, after pushing the argument registers
16935 Note - we only need to tell the dwarf2 backend about the SP
16936 adjustment in the second variant; the static chain register
16937 doesn't need to be unwound, as it doesn't contain a value
16938 inherited from the caller. */
16940 if (df_regs_ever_live_p (3) == false)
16941 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
16942 else if (args_to_push == 0)
16946 gcc_assert(arm_compute_static_chain_stack_bytes() == 4);
16949 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
16950 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
16953 /* Just tell the dwarf backend that we adjusted SP. */
16954 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
16955 plus_constant (stack_pointer_rtx,
16957 RTX_FRAME_RELATED_P (insn) = 1;
16958 add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
16962 /* Store the args on the stack. */
16963 if (cfun->machine->uses_anonymous_args)
16964 insn = emit_multi_reg_push
16965 ((0xf0 >> (args_to_push / 4)) & 0xf);
16968 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
16969 GEN_INT (- args_to_push)));
16971 RTX_FRAME_RELATED_P (insn) = 1;
16973 saved_pretend_args = 1;
16974 fp_offset = args_to_push;
16977 /* Now reuse r3 to preserve IP. */
16978 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
16982 insn = emit_set_insn (ip_rtx,
16983 plus_constant (stack_pointer_rtx, fp_offset));
16984 RTX_FRAME_RELATED_P (insn) = 1;
16989 /* Push the argument registers, or reserve space for them. */
16990 if (cfun->machine->uses_anonymous_args)
16991 insn = emit_multi_reg_push
16992 ((0xf0 >> (args_to_push / 4)) & 0xf);
16995 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
16996 GEN_INT (- args_to_push)));
16997 RTX_FRAME_RELATED_P (insn) = 1;
17000 /* If this is an interrupt service routine, and the link register
17001 is going to be pushed, and we're not generating extra
17002 push of IP (needed when frame is needed and frame layout if apcs),
17003 subtracting four from LR now will mean that the function return
17004 can be done with a single instruction. */
17005 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
17006 && (live_regs_mask & (1 << LR_REGNUM)) != 0
17007 && !(frame_pointer_needed && TARGET_APCS_FRAME)
17010 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
17012 emit_set_insn (lr, plus_constant (lr, -4));
17015 if (live_regs_mask)
17017 saved_regs += bit_count (live_regs_mask) * 4;
17018 if (optimize_size && !frame_pointer_needed
17019 && saved_regs == offsets->saved_regs - offsets->saved_args)
17021 /* If no coprocessor registers are being pushed and we don't have
17022 to worry about a frame pointer then push extra registers to
17023 create the stack frame. This is done is a way that does not
17024 alter the frame layout, so is independent of the epilogue. */
17028 while (n < 8 && (live_regs_mask & (1 << n)) == 0)
17030 frame = offsets->outgoing_args - (offsets->saved_args + saved_regs);
17031 if (frame && n * 4 >= frame)
17034 live_regs_mask |= (1 << n) - 1;
17035 saved_regs += frame;
17038 insn = emit_multi_reg_push (live_regs_mask);
17039 RTX_FRAME_RELATED_P (insn) = 1;
17042 if (! IS_VOLATILE (func_type))
17043 saved_regs += arm_save_coproc_regs ();
17045 if (frame_pointer_needed && TARGET_ARM)
17047 /* Create the new frame pointer. */
17048 if (TARGET_APCS_FRAME)
17050 insn = GEN_INT (-(4 + args_to_push + fp_offset));
17051 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
17052 RTX_FRAME_RELATED_P (insn) = 1;
17054 if (IS_NESTED (func_type))
17056 /* Recover the static chain register. */
17057 if (!df_regs_ever_live_p (3)
17058 || saved_pretend_args)
17059 insn = gen_rtx_REG (SImode, 3);
17060 else /* if (crtl->args.pretend_args_size == 0) */
17062 insn = plus_constant (hard_frame_pointer_rtx, 4);
17063 insn = gen_frame_mem (SImode, insn);
17065 emit_set_insn (ip_rtx, insn);
17066 /* Add a USE to stop propagate_one_insn() from barfing. */
17067 emit_insn (gen_prologue_use (ip_rtx));
17072 insn = GEN_INT (saved_regs - 4);
17073 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
17074 stack_pointer_rtx, insn));
17075 RTX_FRAME_RELATED_P (insn) = 1;
17079 if (flag_stack_usage_info)
17080 current_function_static_stack_size
17081 = offsets->outgoing_args - offsets->saved_args;
17083 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
17085 /* This add can produce multiple insns for a large constant, so we
17086 need to get tricky. */
17087 rtx last = get_last_insn ();
17089 amount = GEN_INT (offsets->saved_args + saved_regs
17090 - offsets->outgoing_args);
17092 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
17096 last = last ? NEXT_INSN (last) : get_insns ();
17097 RTX_FRAME_RELATED_P (last) = 1;
17099 while (last != insn);
17101 /* If the frame pointer is needed, emit a special barrier that
17102 will prevent the scheduler from moving stores to the frame
17103 before the stack adjustment. */
17104 if (frame_pointer_needed)
17105 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
17106 hard_frame_pointer_rtx));
17110 if (frame_pointer_needed && TARGET_THUMB2)
17111 thumb_set_frame_pointer (offsets);
17113 if (flag_pic && arm_pic_register != INVALID_REGNUM)
17115 unsigned long mask;
17117 mask = live_regs_mask;
17118 mask &= THUMB2_WORK_REGS;
17119 if (!IS_NESTED (func_type))
17120 mask |= (1 << IP_REGNUM);
17121 arm_load_pic_register (mask);
17124 /* If we are profiling, make sure no instructions are scheduled before
17125 the call to mcount. Similarly if the user has requested no
17126 scheduling in the prolog. Similarly if we want non-call exceptions
17127 using the EABI unwinder, to prevent faulting instructions from being
17128 swapped with a stack adjustment. */
17129 if (crtl->profile || !TARGET_SCHED_PROLOG
17130 || (arm_except_unwind_info (&global_options) == UI_TARGET
17131 && cfun->can_throw_non_call_exceptions))
17132 emit_insn (gen_blockage ());
17134 /* If the link register is being kept alive, with the return address in it,
17135 then make sure that it does not get reused by the ce2 pass. */
17136 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
17137 cfun->machine->lr_save_eliminated = 1;
17140 /* Print condition code to STREAM. Helper function for arm_print_operand. */
17142 arm_print_condition (FILE *stream)
17144 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
17146 /* Branch conversion is not implemented for Thumb-2. */
17149 output_operand_lossage ("predicated Thumb instruction");
17152 if (current_insn_predicate != NULL)
17154 output_operand_lossage
17155 ("predicated instruction in conditional sequence");
17159 fputs (arm_condition_codes[arm_current_cc], stream);
17161 else if (current_insn_predicate)
17163 enum arm_cond_code code;
17167 output_operand_lossage ("predicated Thumb instruction");
17171 code = get_arm_condition_code (current_insn_predicate);
17172 fputs (arm_condition_codes[code], stream);
17177 /* If CODE is 'd', then the X is a condition operand and the instruction
17178 should only be executed if the condition is true.
17179 if CODE is 'D', then the X is a condition operand and the instruction
17180 should only be executed if the condition is false: however, if the mode
17181 of the comparison is CCFPEmode, then always execute the instruction -- we
17182 do this because in these circumstances !GE does not necessarily imply LT;
17183 in these cases the instruction pattern will take care to make sure that
17184 an instruction containing %d will follow, thereby undoing the effects of
17185 doing this instruction unconditionally.
17186 If CODE is 'N' then X is a floating point operand that must be negated
17188 If CODE is 'B' then output a bitwise inverted value of X (a const int).
17189 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
17191 arm_print_operand (FILE *stream, rtx x, int code)
17196 fputs (ASM_COMMENT_START, stream);
17200 fputs (user_label_prefix, stream);
17204 fputs (REGISTER_PREFIX, stream);
17208 arm_print_condition (stream);
17212 /* Nothing in unified syntax, otherwise the current condition code. */
17213 if (!TARGET_UNIFIED_ASM)
17214 arm_print_condition (stream);
17218 /* The current condition code in unified syntax, otherwise nothing. */
17219 if (TARGET_UNIFIED_ASM)
17220 arm_print_condition (stream);
17224 /* The current condition code for a condition code setting instruction.
17225 Preceded by 's' in unified syntax, otherwise followed by 's'. */
17226 if (TARGET_UNIFIED_ASM)
17228 fputc('s', stream);
17229 arm_print_condition (stream);
17233 arm_print_condition (stream);
17234 fputc('s', stream);
17239 /* If the instruction is conditionally executed then print
17240 the current condition code, otherwise print 's'. */
17241 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
17242 if (current_insn_predicate)
17243 arm_print_condition (stream);
17245 fputc('s', stream);
17248 /* %# is a "break" sequence. It doesn't output anything, but is used to
17249 separate e.g. operand numbers from following text, if that text consists
17250 of further digits which we don't want to be part of the operand
17258 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
17259 r = real_value_negate (&r);
17260 fprintf (stream, "%s", fp_const_from_val (&r));
17264 /* An integer or symbol address without a preceding # sign. */
17266 switch (GET_CODE (x))
17269 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
17273 output_addr_const (stream, x);
17277 if (GET_CODE (XEXP (x, 0)) == PLUS
17278 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
17280 output_addr_const (stream, x);
17283 /* Fall through. */
17286 output_operand_lossage ("Unsupported operand for code '%c'", code);
17291 if (GET_CODE (x) == CONST_INT)
17294 val = ARM_SIGN_EXTEND (~INTVAL (x));
17295 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
17299 putc ('~', stream);
17300 output_addr_const (stream, x);
17305 /* The low 16 bits of an immediate constant. */
17306 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
17310 fprintf (stream, "%s", arithmetic_instr (x, 1));
17313 /* Truncate Cirrus shift counts. */
17315 if (GET_CODE (x) == CONST_INT)
17317 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
17320 arm_print_operand (stream, x, 0);
17324 fprintf (stream, "%s", arithmetic_instr (x, 0));
17332 shift = shift_op (x, &val);
17336 fprintf (stream, ", %s ", shift);
17338 arm_print_operand (stream, XEXP (x, 1), 0);
17340 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
17345 /* An explanation of the 'Q', 'R' and 'H' register operands:
17347 In a pair of registers containing a DI or DF value the 'Q'
17348 operand returns the register number of the register containing
17349 the least significant part of the value. The 'R' operand returns
17350 the register number of the register containing the most
17351 significant part of the value.
17353 The 'H' operand returns the higher of the two register numbers.
17354 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
17355 same as the 'Q' operand, since the most significant part of the
17356 value is held in the lower number register. The reverse is true
17357 on systems where WORDS_BIG_ENDIAN is false.
17359 The purpose of these operands is to distinguish between cases
17360 where the endian-ness of the values is important (for example
17361 when they are added together), and cases where the endian-ness
17362 is irrelevant, but the order of register operations is important.
17363 For example when loading a value from memory into a register
17364 pair, the endian-ness does not matter. Provided that the value
17365 from the lower memory address is put into the lower numbered
17366 register, and the value from the higher address is put into the
17367 higher numbered register, the load will work regardless of whether
17368 the value being loaded is big-wordian or little-wordian. The
17369 order of the two register loads can matter however, if the address
17370 of the memory location is actually held in one of the registers
17371 being overwritten by the load.
17373 The 'Q' and 'R' constraints are also available for 64-bit
17376 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
17378 rtx part = gen_lowpart (SImode, x);
17379 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
17383 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
17385 output_operand_lossage ("invalid operand for code '%c'", code);
17389 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
17393 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
17395 enum machine_mode mode = GET_MODE (x);
17398 if (mode == VOIDmode)
17400 part = gen_highpart_mode (SImode, mode, x);
17401 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
17405 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
17407 output_operand_lossage ("invalid operand for code '%c'", code);
17411 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
17415 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
17417 output_operand_lossage ("invalid operand for code '%c'", code);
17421 asm_fprintf (stream, "%r", REGNO (x) + 1);
17425 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
17427 output_operand_lossage ("invalid operand for code '%c'", code);
17431 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2));
17435 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
17437 output_operand_lossage ("invalid operand for code '%c'", code);
17441 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3));
17445 asm_fprintf (stream, "%r",
17446 GET_CODE (XEXP (x, 0)) == REG
17447 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
17451 asm_fprintf (stream, "{%r-%r}",
17453 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
17456 /* Like 'M', but writing doubleword vector registers, for use by Neon
17460 int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2;
17461 int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2;
17463 asm_fprintf (stream, "{d%d}", regno);
17465 asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1);
17470 /* CONST_TRUE_RTX means always -- that's the default. */
17471 if (x == const_true_rtx)
17474 if (!COMPARISON_P (x))
17476 output_operand_lossage ("invalid operand for code '%c'", code);
17480 fputs (arm_condition_codes[get_arm_condition_code (x)],
17485 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
17486 want to do that. */
17487 if (x == const_true_rtx)
17489 output_operand_lossage ("instruction never executed");
17492 if (!COMPARISON_P (x))
17494 output_operand_lossage ("invalid operand for code '%c'", code);
17498 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
17499 (get_arm_condition_code (x))],
17503 /* Cirrus registers can be accessed in a variety of ways:
17504 single floating point (f)
17505 double floating point (d)
17507 64bit integer (dx). */
17508 case 'W': /* Cirrus register in F mode. */
17509 case 'X': /* Cirrus register in D mode. */
17510 case 'Y': /* Cirrus register in FX mode. */
17511 case 'Z': /* Cirrus register in DX mode. */
17512 gcc_assert (GET_CODE (x) == REG
17513 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
17515 fprintf (stream, "mv%s%s",
17517 : code == 'X' ? "d"
17518 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
17522 /* Print cirrus register in the mode specified by the register's mode. */
17525 int mode = GET_MODE (x);
17527 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
17529 output_operand_lossage ("invalid operand for code '%c'", code);
17533 fprintf (stream, "mv%s%s",
17534 mode == DFmode ? "d"
17535 : mode == SImode ? "fx"
17536 : mode == DImode ? "dx"
17537 : "f", reg_names[REGNO (x)] + 2);
17543 if (GET_CODE (x) != REG
17544 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
17545 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
17546 /* Bad value for wCG register number. */
17548 output_operand_lossage ("invalid operand for code '%c'", code);
17553 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
17556 /* Print an iWMMXt control register name. */
17558 if (GET_CODE (x) != CONST_INT
17560 || INTVAL (x) >= 16)
17561 /* Bad value for wC register number. */
17563 output_operand_lossage ("invalid operand for code '%c'", code);
17569 static const char * wc_reg_names [16] =
17571 "wCID", "wCon", "wCSSF", "wCASF",
17572 "wC4", "wC5", "wC6", "wC7",
17573 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
17574 "wC12", "wC13", "wC14", "wC15"
17577 fprintf (stream, wc_reg_names [INTVAL (x)]);
17581 /* Print the high single-precision register of a VFP double-precision
17585 int mode = GET_MODE (x);
17588 if (GET_MODE_SIZE (mode) != 8 || GET_CODE (x) != REG)
17590 output_operand_lossage ("invalid operand for code '%c'", code);
17595 if (!VFP_REGNO_OK_FOR_DOUBLE (regno))
17597 output_operand_lossage ("invalid operand for code '%c'", code);
17601 fprintf (stream, "s%d", regno - FIRST_VFP_REGNUM + 1);
17605 /* Print a VFP/Neon double precision or quad precision register name. */
17609 int mode = GET_MODE (x);
17610 int is_quad = (code == 'q');
17613 if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8))
17615 output_operand_lossage ("invalid operand for code '%c'", code);
17619 if (GET_CODE (x) != REG
17620 || !IS_VFP_REGNUM (REGNO (x)))
17622 output_operand_lossage ("invalid operand for code '%c'", code);
17627 if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno))
17628 || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno)))
17630 output_operand_lossage ("invalid operand for code '%c'", code);
17634 fprintf (stream, "%c%d", is_quad ? 'q' : 'd',
17635 (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1));
17639 /* These two codes print the low/high doubleword register of a Neon quad
17640 register, respectively. For pair-structure types, can also print
17641 low/high quadword registers. */
17645 int mode = GET_MODE (x);
17648 if ((GET_MODE_SIZE (mode) != 16
17649 && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG)
17651 output_operand_lossage ("invalid operand for code '%c'", code);
17656 if (!NEON_REGNO_OK_FOR_QUAD (regno))
17658 output_operand_lossage ("invalid operand for code '%c'", code);
17662 if (GET_MODE_SIZE (mode) == 16)
17663 fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1)
17664 + (code == 'f' ? 1 : 0));
17666 fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2)
17667 + (code == 'f' ? 1 : 0));
17671 /* Print a VFPv3 floating-point constant, represented as an integer
17675 int index = vfp3_const_double_index (x);
17676 gcc_assert (index != -1);
17677 fprintf (stream, "%d", index);
17681 /* Print bits representing opcode features for Neon.
17683 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
17684 and polynomials as unsigned.
17686 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
17688 Bit 2 is 1 for rounding functions, 0 otherwise. */
17690 /* Identify the type as 's', 'u', 'p' or 'f'. */
17693 HOST_WIDE_INT bits = INTVAL (x);
17694 fputc ("uspf"[bits & 3], stream);
17698 /* Likewise, but signed and unsigned integers are both 'i'. */
17701 HOST_WIDE_INT bits = INTVAL (x);
17702 fputc ("iipf"[bits & 3], stream);
17706 /* As for 'T', but emit 'u' instead of 'p'. */
17709 HOST_WIDE_INT bits = INTVAL (x);
17710 fputc ("usuf"[bits & 3], stream);
17714 /* Bit 2: rounding (vs none). */
17717 HOST_WIDE_INT bits = INTVAL (x);
17718 fputs ((bits & 4) != 0 ? "r" : "", stream);
17722 /* Memory operand for vld1/vst1 instruction. */
17726 bool postinc = FALSE;
17727 unsigned align, memsize, align_bits;
17729 gcc_assert (GET_CODE (x) == MEM);
17730 addr = XEXP (x, 0);
17731 if (GET_CODE (addr) == POST_INC)
17734 addr = XEXP (addr, 0);
17736 asm_fprintf (stream, "[%r", REGNO (addr));
17738 /* We know the alignment of this access, so we can emit a hint in the
17739 instruction (for some alignments) as an aid to the memory subsystem
17741 align = MEM_ALIGN (x) >> 3;
17742 memsize = MEM_SIZE (x);
17744 /* Only certain alignment specifiers are supported by the hardware. */
17745 if (memsize == 32 && (align % 32) == 0)
17747 else if ((memsize == 16 || memsize == 32) && (align % 16) == 0)
17749 else if (memsize >= 8 && (align % 8) == 0)
17754 if (align_bits != 0)
17755 asm_fprintf (stream, ":%d", align_bits);
17757 asm_fprintf (stream, "]");
17760 fputs("!", stream);
17768 gcc_assert (GET_CODE (x) == MEM);
17769 addr = XEXP (x, 0);
17770 gcc_assert (GET_CODE (addr) == REG);
17771 asm_fprintf (stream, "[%r]", REGNO (addr));
17775 /* Translate an S register number into a D register number and element index. */
17778 int mode = GET_MODE (x);
17781 if (GET_MODE_SIZE (mode) != 4 || GET_CODE (x) != REG)
17783 output_operand_lossage ("invalid operand for code '%c'", code);
17788 if (!VFP_REGNO_OK_FOR_SINGLE (regno))
17790 output_operand_lossage ("invalid operand for code '%c'", code);
17794 regno = regno - FIRST_VFP_REGNUM;
17795 fprintf (stream, "d%d[%d]", regno / 2, regno % 2);
17800 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
17801 fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x));
17804 /* Register specifier for vld1.16/vst1.16. Translate the S register
17805 number into a D register number and element index. */
17808 int mode = GET_MODE (x);
17811 if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG)
17813 output_operand_lossage ("invalid operand for code '%c'", code);
17818 if (!VFP_REGNO_OK_FOR_SINGLE (regno))
17820 output_operand_lossage ("invalid operand for code '%c'", code);
17824 regno = regno - FIRST_VFP_REGNUM;
17825 fprintf (stream, "d%d[%d]", regno/2, ((regno % 2) ? 2 : 0));
17832 output_operand_lossage ("missing operand");
17836 switch (GET_CODE (x))
17839 asm_fprintf (stream, "%r", REGNO (x));
17843 output_memory_reference_mode = GET_MODE (x);
17844 output_address (XEXP (x, 0));
17851 real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
17852 sizeof (fpstr), 0, 1);
17853 fprintf (stream, "#%s", fpstr);
17856 fprintf (stream, "#%s", fp_immediate_constant (x));
17860 gcc_assert (GET_CODE (x) != NEG);
17861 fputc ('#', stream);
17862 if (GET_CODE (x) == HIGH)
17864 fputs (":lower16:", stream);
17868 output_addr_const (stream, x);
17874 /* Target hook for printing a memory address. */
17876 arm_print_operand_address (FILE *stream, rtx x)
17880 int is_minus = GET_CODE (x) == MINUS;
17882 if (GET_CODE (x) == REG)
17883 asm_fprintf (stream, "[%r, #0]", REGNO (x));
17884 else if (GET_CODE (x) == PLUS || is_minus)
17886 rtx base = XEXP (x, 0);
17887 rtx index = XEXP (x, 1);
17888 HOST_WIDE_INT offset = 0;
17889 if (GET_CODE (base) != REG
17890 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM))
17892 /* Ensure that BASE is a register. */
17893 /* (one of them must be). */
17894 /* Also ensure the SP is not used as in index register. */
17899 switch (GET_CODE (index))
17902 offset = INTVAL (index);
17905 asm_fprintf (stream, "[%r, #%wd]",
17906 REGNO (base), offset);
17910 asm_fprintf (stream, "[%r, %s%r]",
17911 REGNO (base), is_minus ? "-" : "",
17921 asm_fprintf (stream, "[%r, %s%r",
17922 REGNO (base), is_minus ? "-" : "",
17923 REGNO (XEXP (index, 0)));
17924 arm_print_operand (stream, index, 'S');
17925 fputs ("]", stream);
17930 gcc_unreachable ();
17933 else if (GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_INC
17934 || GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_DEC)
17936 extern enum machine_mode output_memory_reference_mode;
17938 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
17940 if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC)
17941 asm_fprintf (stream, "[%r, #%s%d]!",
17942 REGNO (XEXP (x, 0)),
17943 GET_CODE (x) == PRE_DEC ? "-" : "",
17944 GET_MODE_SIZE (output_memory_reference_mode));
17946 asm_fprintf (stream, "[%r], #%s%d",
17947 REGNO (XEXP (x, 0)),
17948 GET_CODE (x) == POST_DEC ? "-" : "",
17949 GET_MODE_SIZE (output_memory_reference_mode));
17951 else if (GET_CODE (x) == PRE_MODIFY)
17953 asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0)));
17954 if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
17955 asm_fprintf (stream, "#%wd]!",
17956 INTVAL (XEXP (XEXP (x, 1), 1)));
17958 asm_fprintf (stream, "%r]!",
17959 REGNO (XEXP (XEXP (x, 1), 1)));
17961 else if (GET_CODE (x) == POST_MODIFY)
17963 asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0)));
17964 if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
17965 asm_fprintf (stream, "#%wd",
17966 INTVAL (XEXP (XEXP (x, 1), 1)));
17968 asm_fprintf (stream, "%r",
17969 REGNO (XEXP (XEXP (x, 1), 1)));
17971 else output_addr_const (stream, x);
17975 if (GET_CODE (x) == REG)
17976 asm_fprintf (stream, "[%r]", REGNO (x));
17977 else if (GET_CODE (x) == POST_INC)
17978 asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0)));
17979 else if (GET_CODE (x) == PLUS)
17981 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
17982 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
17983 asm_fprintf (stream, "[%r, #%wd]",
17984 REGNO (XEXP (x, 0)),
17985 INTVAL (XEXP (x, 1)));
17987 asm_fprintf (stream, "[%r, %r]",
17988 REGNO (XEXP (x, 0)),
17989 REGNO (XEXP (x, 1)));
17992 output_addr_const (stream, x);
17996 /* Target hook for indicating whether a punctuation character for
17997 TARGET_PRINT_OPERAND is valid. */
17999 arm_print_operand_punct_valid_p (unsigned char code)
18001 return (code == '@' || code == '|' || code == '.'
18002 || code == '(' || code == ')' || code == '#'
18003 || (TARGET_32BIT && (code == '?'))
18004 || (TARGET_THUMB2 && (code == '!'))
18005 || (TARGET_THUMB && (code == '_')));
18008 /* Target hook for assembling integer objects. The ARM version needs to
18009 handle word-sized values specially. */
18011 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
18013 enum machine_mode mode;
18015 if (size == UNITS_PER_WORD && aligned_p)
18017 fputs ("\t.word\t", asm_out_file);
18018 output_addr_const (asm_out_file, x);
18020 /* Mark symbols as position independent. We only do this in the
18021 .text segment, not in the .data segment. */
18022 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
18023 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
18025 /* See legitimize_pic_address for an explanation of the
18026 TARGET_VXWORKS_RTP check. */
18027 if (TARGET_VXWORKS_RTP
18028 || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
18029 fputs ("(GOT)", asm_out_file);
18031 fputs ("(GOTOFF)", asm_out_file);
18033 fputc ('\n', asm_out_file);
18037 mode = GET_MODE (x);
18039 if (arm_vector_mode_supported_p (mode))
18043 gcc_assert (GET_CODE (x) == CONST_VECTOR);
18045 units = CONST_VECTOR_NUNITS (x);
18046 size = GET_MODE_SIZE (GET_MODE_INNER (mode));
18048 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
18049 for (i = 0; i < units; i++)
18051 rtx elt = CONST_VECTOR_ELT (x, i);
18053 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
18056 for (i = 0; i < units; i++)
18058 rtx elt = CONST_VECTOR_ELT (x, i);
18059 REAL_VALUE_TYPE rval;
18061 REAL_VALUE_FROM_CONST_DOUBLE (rval, elt);
18064 (rval, GET_MODE_INNER (mode),
18065 i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT);
18071 return default_assemble_integer (x, size, aligned_p);
18075 arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
18079 if (!TARGET_AAPCS_BASED)
18082 default_named_section_asm_out_constructor
18083 : default_named_section_asm_out_destructor) (symbol, priority);
18087 /* Put these in the .init_array section, using a special relocation. */
18088 if (priority != DEFAULT_INIT_PRIORITY)
18091 sprintf (buf, "%s.%.5u",
18092 is_ctor ? ".init_array" : ".fini_array",
18094 s = get_section (buf, SECTION_WRITE, NULL_TREE);
18101 switch_to_section (s);
18102 assemble_align (POINTER_SIZE);
18103 fputs ("\t.word\t", asm_out_file);
18104 output_addr_const (asm_out_file, symbol);
18105 fputs ("(target1)\n", asm_out_file);
18108 /* Add a function to the list of static constructors. */
18111 arm_elf_asm_constructor (rtx symbol, int priority)
18113 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
18116 /* Add a function to the list of static destructors. */
18119 arm_elf_asm_destructor (rtx symbol, int priority)
18121 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
18124 /* A finite state machine takes care of noticing whether or not instructions
18125 can be conditionally executed, and thus decrease execution time and code
18126 size by deleting branch instructions. The fsm is controlled by
18127 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
18129 /* The state of the fsm controlling condition codes are:
18130 0: normal, do nothing special
18131 1: make ASM_OUTPUT_OPCODE not output this instruction
18132 2: make ASM_OUTPUT_OPCODE not output this instruction
18133 3: make instructions conditional
18134 4: make instructions conditional
18136 State transitions (state->state by whom under condition):
18137 0 -> 1 final_prescan_insn if the `target' is a label
18138 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
18139 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
18140 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
18141 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
18142 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
18143 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
18144 (the target insn is arm_target_insn).
18146 If the jump clobbers the conditions then we use states 2 and 4.
18148 A similar thing can be done with conditional return insns.
18150 XXX In case the `target' is an unconditional branch, this conditionalising
18151 of the instructions always reduces code size, but not always execution
18152 time. But then, I want to reduce the code size to somewhere near what
18153 /bin/cc produces. */
18155 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
18156 instructions. When a COND_EXEC instruction is seen the subsequent
18157 instructions are scanned so that multiple conditional instructions can be
18158 combined into a single IT block. arm_condexec_count and arm_condexec_mask
18159 specify the length and true/false mask for the IT block. These will be
18160 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
18162 /* Returns the index of the ARM condition code string in
18163 `arm_condition_codes', or ARM_NV if the comparison is invalid.
18164 COMPARISON should be an rtx like `(eq (...) (...))'. */
18167 maybe_get_arm_condition_code (rtx comparison)
18169 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
18170 enum arm_cond_code code;
18171 enum rtx_code comp_code = GET_CODE (comparison);
18173 if (GET_MODE_CLASS (mode) != MODE_CC)
18174 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
18175 XEXP (comparison, 1));
18179 case CC_DNEmode: code = ARM_NE; goto dominance;
18180 case CC_DEQmode: code = ARM_EQ; goto dominance;
18181 case CC_DGEmode: code = ARM_GE; goto dominance;
18182 case CC_DGTmode: code = ARM_GT; goto dominance;
18183 case CC_DLEmode: code = ARM_LE; goto dominance;
18184 case CC_DLTmode: code = ARM_LT; goto dominance;
18185 case CC_DGEUmode: code = ARM_CS; goto dominance;
18186 case CC_DGTUmode: code = ARM_HI; goto dominance;
18187 case CC_DLEUmode: code = ARM_LS; goto dominance;
18188 case CC_DLTUmode: code = ARM_CC;
18191 if (comp_code == EQ)
18192 return ARM_INVERSE_CONDITION_CODE (code);
18193 if (comp_code == NE)
18200 case NE: return ARM_NE;
18201 case EQ: return ARM_EQ;
18202 case GE: return ARM_PL;
18203 case LT: return ARM_MI;
18204 default: return ARM_NV;
18210 case NE: return ARM_NE;
18211 case EQ: return ARM_EQ;
18212 default: return ARM_NV;
18218 case NE: return ARM_MI;
18219 case EQ: return ARM_PL;
18220 default: return ARM_NV;
18225 /* These encodings assume that AC=1 in the FPA system control
18226 byte. This allows us to handle all cases except UNEQ and
18230 case GE: return ARM_GE;
18231 case GT: return ARM_GT;
18232 case LE: return ARM_LS;
18233 case LT: return ARM_MI;
18234 case NE: return ARM_NE;
18235 case EQ: return ARM_EQ;
18236 case ORDERED: return ARM_VC;
18237 case UNORDERED: return ARM_VS;
18238 case UNLT: return ARM_LT;
18239 case UNLE: return ARM_LE;
18240 case UNGT: return ARM_HI;
18241 case UNGE: return ARM_PL;
18242 /* UNEQ and LTGT do not have a representation. */
18243 case UNEQ: /* Fall through. */
18244 case LTGT: /* Fall through. */
18245 default: return ARM_NV;
18251 case NE: return ARM_NE;
18252 case EQ: return ARM_EQ;
18253 case GE: return ARM_LE;
18254 case GT: return ARM_LT;
18255 case LE: return ARM_GE;
18256 case LT: return ARM_GT;
18257 case GEU: return ARM_LS;
18258 case GTU: return ARM_CC;
18259 case LEU: return ARM_CS;
18260 case LTU: return ARM_HI;
18261 default: return ARM_NV;
18267 case LTU: return ARM_CS;
18268 case GEU: return ARM_CC;
18269 default: return ARM_NV;
18275 case NE: return ARM_NE;
18276 case EQ: return ARM_EQ;
18277 case GEU: return ARM_CS;
18278 case GTU: return ARM_HI;
18279 case LEU: return ARM_LS;
18280 case LTU: return ARM_CC;
18281 default: return ARM_NV;
18287 case GE: return ARM_GE;
18288 case LT: return ARM_LT;
18289 case GEU: return ARM_CS;
18290 case LTU: return ARM_CC;
18291 default: return ARM_NV;
18297 case NE: return ARM_NE;
18298 case EQ: return ARM_EQ;
18299 case GE: return ARM_GE;
18300 case GT: return ARM_GT;
18301 case LE: return ARM_LE;
18302 case LT: return ARM_LT;
18303 case GEU: return ARM_CS;
18304 case GTU: return ARM_HI;
18305 case LEU: return ARM_LS;
18306 case LTU: return ARM_CC;
18307 default: return ARM_NV;
18310 default: gcc_unreachable ();
18314 /* Like maybe_get_arm_condition_code, but never return ARM_NV. */
18315 static enum arm_cond_code
18316 get_arm_condition_code (rtx comparison)
18318 enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
18319 gcc_assert (code != ARM_NV);
18323 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
18326 thumb2_final_prescan_insn (rtx insn)
18328 rtx first_insn = insn;
18329 rtx body = PATTERN (insn);
18331 enum arm_cond_code code;
18335 /* Remove the previous insn from the count of insns to be output. */
18336 if (arm_condexec_count)
18337 arm_condexec_count--;
18339 /* Nothing to do if we are already inside a conditional block. */
18340 if (arm_condexec_count)
18343 if (GET_CODE (body) != COND_EXEC)
18346 /* Conditional jumps are implemented directly. */
18347 if (GET_CODE (insn) == JUMP_INSN)
18350 predicate = COND_EXEC_TEST (body);
18351 arm_current_cc = get_arm_condition_code (predicate);
18353 n = get_attr_ce_count (insn);
18354 arm_condexec_count = 1;
18355 arm_condexec_mask = (1 << n) - 1;
18356 arm_condexec_masklen = n;
18357 /* See if subsequent instructions can be combined into the same block. */
18360 insn = next_nonnote_insn (insn);
18362 /* Jumping into the middle of an IT block is illegal, so a label or
18363 barrier terminates the block. */
18364 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
18367 body = PATTERN (insn);
18368 /* USE and CLOBBER aren't really insns, so just skip them. */
18369 if (GET_CODE (body) == USE
18370 || GET_CODE (body) == CLOBBER)
18373 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
18374 if (GET_CODE (body) != COND_EXEC)
18376 /* Allow up to 4 conditionally executed instructions in a block. */
18377 n = get_attr_ce_count (insn);
18378 if (arm_condexec_masklen + n > 4)
18381 predicate = COND_EXEC_TEST (body);
18382 code = get_arm_condition_code (predicate);
18383 mask = (1 << n) - 1;
18384 if (arm_current_cc == code)
18385 arm_condexec_mask |= (mask << arm_condexec_masklen);
18386 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
18389 arm_condexec_count++;
18390 arm_condexec_masklen += n;
18392 /* A jump must be the last instruction in a conditional block. */
18393 if (GET_CODE(insn) == JUMP_INSN)
18396 /* Restore recog_data (getting the attributes of other insns can
18397 destroy this array, but final.c assumes that it remains intact
18398 across this call). */
18399 extract_constrain_insn_cached (first_insn);
18403 arm_final_prescan_insn (rtx insn)
18405 /* BODY will hold the body of INSN. */
18406 rtx body = PATTERN (insn);
18408 /* This will be 1 if trying to repeat the trick, and things need to be
18409 reversed if it appears to fail. */
18412 /* If we start with a return insn, we only succeed if we find another one. */
18413 int seeking_return = 0;
18414 enum rtx_code return_code = UNKNOWN;
18416 /* START_INSN will hold the insn from where we start looking. This is the
18417 first insn after the following code_label if REVERSE is true. */
18418 rtx start_insn = insn;
18420 /* If in state 4, check if the target branch is reached, in order to
18421 change back to state 0. */
18422 if (arm_ccfsm_state == 4)
18424 if (insn == arm_target_insn)
18426 arm_target_insn = NULL;
18427 arm_ccfsm_state = 0;
18432 /* If in state 3, it is possible to repeat the trick, if this insn is an
18433 unconditional branch to a label, and immediately following this branch
18434 is the previous target label which is only used once, and the label this
18435 branch jumps to is not too far off. */
18436 if (arm_ccfsm_state == 3)
18438 if (simplejump_p (insn))
18440 start_insn = next_nonnote_insn (start_insn);
18441 if (GET_CODE (start_insn) == BARRIER)
18443 /* XXX Isn't this always a barrier? */
18444 start_insn = next_nonnote_insn (start_insn);
18446 if (GET_CODE (start_insn) == CODE_LABEL
18447 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
18448 && LABEL_NUSES (start_insn) == 1)
18453 else if (ANY_RETURN_P (body))
18455 start_insn = next_nonnote_insn (start_insn);
18456 if (GET_CODE (start_insn) == BARRIER)
18457 start_insn = next_nonnote_insn (start_insn);
18458 if (GET_CODE (start_insn) == CODE_LABEL
18459 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
18460 && LABEL_NUSES (start_insn) == 1)
18463 seeking_return = 1;
18464 return_code = GET_CODE (body);
18473 gcc_assert (!arm_ccfsm_state || reverse);
18474 if (GET_CODE (insn) != JUMP_INSN)
18477 /* This jump might be paralleled with a clobber of the condition codes
18478 the jump should always come first */
18479 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
18480 body = XVECEXP (body, 0, 0);
18483 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
18484 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
18487 int fail = FALSE, succeed = FALSE;
18488 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
18489 int then_not_else = TRUE;
18490 rtx this_insn = start_insn, label = 0;
18492 /* Register the insn jumped to. */
18495 if (!seeking_return)
18496 label = XEXP (SET_SRC (body), 0);
18498 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
18499 label = XEXP (XEXP (SET_SRC (body), 1), 0);
18500 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
18502 label = XEXP (XEXP (SET_SRC (body), 2), 0);
18503 then_not_else = FALSE;
18505 else if (ANY_RETURN_P (XEXP (SET_SRC (body), 1)))
18507 seeking_return = 1;
18508 return_code = GET_CODE (XEXP (SET_SRC (body), 1));
18510 else if (ANY_RETURN_P (XEXP (SET_SRC (body), 2)))
18512 seeking_return = 1;
18513 return_code = GET_CODE (XEXP (SET_SRC (body), 2));
18514 then_not_else = FALSE;
18517 gcc_unreachable ();
18519 /* See how many insns this branch skips, and what kind of insns. If all
18520 insns are okay, and the label or unconditional branch to the same
18521 label is not too far away, succeed. */
18522 for (insns_skipped = 0;
18523 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
18527 this_insn = next_nonnote_insn (this_insn);
18531 switch (GET_CODE (this_insn))
18534 /* Succeed if it is the target label, otherwise fail since
18535 control falls in from somewhere else. */
18536 if (this_insn == label)
18538 arm_ccfsm_state = 1;
18546 /* Succeed if the following insn is the target label.
18548 If return insns are used then the last insn in a function
18549 will be a barrier. */
18550 this_insn = next_nonnote_insn (this_insn);
18551 if (this_insn && this_insn == label)
18553 arm_ccfsm_state = 1;
18561 /* The AAPCS says that conditional calls should not be
18562 used since they make interworking inefficient (the
18563 linker can't transform BL<cond> into BLX). That's
18564 only a problem if the machine has BLX. */
18571 /* Succeed if the following insn is the target label, or
18572 if the following two insns are a barrier and the
18574 this_insn = next_nonnote_insn (this_insn);
18575 if (this_insn && GET_CODE (this_insn) == BARRIER)
18576 this_insn = next_nonnote_insn (this_insn);
18578 if (this_insn && this_insn == label
18579 && insns_skipped < max_insns_skipped)
18581 arm_ccfsm_state = 1;
18589 /* If this is an unconditional branch to the same label, succeed.
18590 If it is to another label, do nothing. If it is conditional,
18592 /* XXX Probably, the tests for SET and the PC are
18595 scanbody = PATTERN (this_insn);
18596 if (GET_CODE (scanbody) == SET
18597 && GET_CODE (SET_DEST (scanbody)) == PC)
18599 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
18600 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
18602 arm_ccfsm_state = 2;
18605 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
18608 /* Fail if a conditional return is undesirable (e.g. on a
18609 StrongARM), but still allow this if optimizing for size. */
18610 else if (GET_CODE (scanbody) == return_code
18611 && !use_return_insn (TRUE, NULL)
18614 else if (GET_CODE (scanbody) == return_code)
18616 arm_ccfsm_state = 2;
18619 else if (GET_CODE (scanbody) == PARALLEL)
18621 switch (get_attr_conds (this_insn))
18631 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
18636 /* Instructions using or affecting the condition codes make it
18638 scanbody = PATTERN (this_insn);
18639 if (!(GET_CODE (scanbody) == SET
18640 || GET_CODE (scanbody) == PARALLEL)
18641 || get_attr_conds (this_insn) != CONDS_NOCOND)
18644 /* A conditional cirrus instruction must be followed by
18645 a non Cirrus instruction. However, since we
18646 conditionalize instructions in this function and by
18647 the time we get here we can't add instructions
18648 (nops), because shorten_branches() has already been
18649 called, we will disable conditionalizing Cirrus
18650 instructions to be safe. */
18651 if (GET_CODE (scanbody) != USE
18652 && GET_CODE (scanbody) != CLOBBER
18653 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
18663 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
18664 arm_target_label = CODE_LABEL_NUMBER (label);
18667 gcc_assert (seeking_return || arm_ccfsm_state == 2);
18669 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
18671 this_insn = next_nonnote_insn (this_insn);
18672 gcc_assert (!this_insn
18673 || (GET_CODE (this_insn) != BARRIER
18674 && GET_CODE (this_insn) != CODE_LABEL));
18678 /* Oh, dear! we ran off the end.. give up. */
18679 extract_constrain_insn_cached (insn);
18680 arm_ccfsm_state = 0;
18681 arm_target_insn = NULL;
18684 arm_target_insn = this_insn;
18687 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
18690 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 0));
18692 if (reverse || then_not_else)
18693 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
18696 /* Restore recog_data (getting the attributes of other insns can
18697 destroy this array, but final.c assumes that it remains intact
18698 across this call. */
18699 extract_constrain_insn_cached (insn);
18703 /* Output IT instructions. */
18705 thumb2_asm_output_opcode (FILE * stream)
18710 if (arm_condexec_mask)
18712 for (n = 0; n < arm_condexec_masklen; n++)
18713 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
18715 asm_fprintf(stream, "i%s\t%s\n\t", buff,
18716 arm_condition_codes[arm_current_cc]);
18717 arm_condexec_mask = 0;
18721 /* Returns true if REGNO is a valid register
18722 for holding a quantity of type MODE. */
18724 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
18726 if (GET_MODE_CLASS (mode) == MODE_CC)
18727 return (regno == CC_REGNUM
18728 || (TARGET_HARD_FLOAT && TARGET_VFP
18729 && regno == VFPCC_REGNUM));
18732 /* For the Thumb we only allow values bigger than SImode in
18733 registers 0 - 6, so that there is always a second low
18734 register available to hold the upper part of the value.
18735 We probably we ought to ensure that the register is the
18736 start of an even numbered register pair. */
18737 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
18739 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
18740 && IS_CIRRUS_REGNUM (regno))
18741 /* We have outlawed SI values in Cirrus registers because they
18742 reside in the lower 32 bits, but SF values reside in the
18743 upper 32 bits. This causes gcc all sorts of grief. We can't
18744 even split the registers into pairs because Cirrus SI values
18745 get sign extended to 64bits-- aldyh. */
18746 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
18748 if (TARGET_HARD_FLOAT && TARGET_VFP
18749 && IS_VFP_REGNUM (regno))
18751 if (mode == SFmode || mode == SImode)
18752 return VFP_REGNO_OK_FOR_SINGLE (regno);
18754 if (mode == DFmode)
18755 return VFP_REGNO_OK_FOR_DOUBLE (regno);
18757 /* VFP registers can hold HFmode values, but there is no point in
18758 putting them there unless we have hardware conversion insns. */
18759 if (mode == HFmode)
18760 return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno);
18763 return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
18764 || (VALID_NEON_QREG_MODE (mode)
18765 && NEON_REGNO_OK_FOR_QUAD (regno))
18766 || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2))
18767 || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3))
18768 || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4))
18769 || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6))
18770 || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8));
18775 if (TARGET_REALLY_IWMMXT)
18777 if (IS_IWMMXT_GR_REGNUM (regno))
18778 return mode == SImode;
18780 if (IS_IWMMXT_REGNUM (regno))
18781 return VALID_IWMMXT_REG_MODE (mode);
18784 /* We allow almost any value to be stored in the general registers.
18785 Restrict doubleword quantities to even register pairs so that we can
18786 use ldrd. Do not allow very large Neon structure opaque modes in
18787 general registers; they would use too many. */
18788 if (regno <= LAST_ARM_REGNUM)
18789 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0)
18790 && ARM_NUM_REGS (mode) <= 4;
18792 if (regno == FRAME_POINTER_REGNUM
18793 || regno == ARG_POINTER_REGNUM)
18794 /* We only allow integers in the fake hard registers. */
18795 return GET_MODE_CLASS (mode) == MODE_INT;
18797 /* The only registers left are the FPA registers
18798 which we only allow to hold FP values. */
18799 return (TARGET_HARD_FLOAT && TARGET_FPA
18800 && GET_MODE_CLASS (mode) == MODE_FLOAT
18801 && regno >= FIRST_FPA_REGNUM
18802 && regno <= LAST_FPA_REGNUM);
18805 /* Implement MODES_TIEABLE_P. */
18808 arm_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
18810 if (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2))
18813 /* We specifically want to allow elements of "structure" modes to
18814 be tieable to the structure. This more general condition allows
18815 other rarer situations too. */
18817 && (VALID_NEON_DREG_MODE (mode1)
18818 || VALID_NEON_QREG_MODE (mode1)
18819 || VALID_NEON_STRUCT_MODE (mode1))
18820 && (VALID_NEON_DREG_MODE (mode2)
18821 || VALID_NEON_QREG_MODE (mode2)
18822 || VALID_NEON_STRUCT_MODE (mode2)))
18828 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
18829 not used in arm mode. */
18832 arm_regno_class (int regno)
18836 if (regno == STACK_POINTER_REGNUM)
18838 if (regno == CC_REGNUM)
18845 if (TARGET_THUMB2 && regno < 8)
18848 if ( regno <= LAST_ARM_REGNUM
18849 || regno == FRAME_POINTER_REGNUM
18850 || regno == ARG_POINTER_REGNUM)
18851 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
18853 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
18854 return TARGET_THUMB2 ? CC_REG : NO_REGS;
18856 if (IS_CIRRUS_REGNUM (regno))
18857 return CIRRUS_REGS;
18859 if (IS_VFP_REGNUM (regno))
18861 if (regno <= D7_VFP_REGNUM)
18862 return VFP_D0_D7_REGS;
18863 else if (regno <= LAST_LO_VFP_REGNUM)
18864 return VFP_LO_REGS;
18866 return VFP_HI_REGS;
18869 if (IS_IWMMXT_REGNUM (regno))
18870 return IWMMXT_REGS;
18872 if (IS_IWMMXT_GR_REGNUM (regno))
18873 return IWMMXT_GR_REGS;
18878 /* Handle a special case when computing the offset
18879 of an argument from the frame pointer. */
18881 arm_debugger_arg_offset (int value, rtx addr)
18885 /* We are only interested if dbxout_parms() failed to compute the offset. */
18889 /* We can only cope with the case where the address is held in a register. */
18890 if (GET_CODE (addr) != REG)
18893 /* If we are using the frame pointer to point at the argument, then
18894 an offset of 0 is correct. */
18895 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
18898 /* If we are using the stack pointer to point at the
18899 argument, then an offset of 0 is correct. */
18900 /* ??? Check this is consistent with thumb2 frame layout. */
18901 if ((TARGET_THUMB || !frame_pointer_needed)
18902 && REGNO (addr) == SP_REGNUM)
18905 /* Oh dear. The argument is pointed to by a register rather
18906 than being held in a register, or being stored at a known
18907 offset from the frame pointer. Since GDB only understands
18908 those two kinds of argument we must translate the address
18909 held in the register into an offset from the frame pointer.
18910 We do this by searching through the insns for the function
18911 looking to see where this register gets its value. If the
18912 register is initialized from the frame pointer plus an offset
18913 then we are in luck and we can continue, otherwise we give up.
18915 This code is exercised by producing debugging information
18916 for a function with arguments like this:
18918 double func (double a, double b, int c, double d) {return d;}
18920 Without this code the stab for parameter 'd' will be set to
18921 an offset of 0 from the frame pointer, rather than 8. */
18923 /* The if() statement says:
18925 If the insn is a normal instruction
18926 and if the insn is setting the value in a register
18927 and if the register being set is the register holding the address of the argument
18928 and if the address is computing by an addition
18929 that involves adding to a register
18930 which is the frame pointer
18935 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18937 if ( GET_CODE (insn) == INSN
18938 && GET_CODE (PATTERN (insn)) == SET
18939 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
18940 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
18941 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
18942 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
18943 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
18946 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
18955 warning (0, "unable to compute real location of stacked parameter");
18956 value = 8; /* XXX magic hack */
18976 T_MAX /* Size of enum. Keep last. */
18977 } neon_builtin_type_mode;
18979 #define TYPE_MODE_BIT(X) (1 << (X))
18981 #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \
18982 | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF) \
18983 | TYPE_MODE_BIT (T_DI))
18984 #define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \
18985 | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \
18986 | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
18988 #define v8qi_UP T_V8QI
18989 #define v4hi_UP T_V4HI
18990 #define v2si_UP T_V2SI
18991 #define v2sf_UP T_V2SF
18993 #define v16qi_UP T_V16QI
18994 #define v8hi_UP T_V8HI
18995 #define v4si_UP T_V4SI
18996 #define v4sf_UP T_V4SF
18997 #define v2di_UP T_V2DI
19002 #define UP(X) X##_UP
19035 NEON_LOADSTRUCTLANE,
19037 NEON_STORESTRUCTLANE,
19046 const neon_itype itype;
19047 const neon_builtin_type_mode mode;
19048 const enum insn_code code;
19049 unsigned int fcode;
19050 } neon_builtin_datum;
19052 #define CF(N,X) CODE_FOR_neon_##N##X
19054 #define VAR1(T, N, A) \
19055 {#N, NEON_##T, UP (A), CF (N, A), 0}
19056 #define VAR2(T, N, A, B) \
19058 {#N, NEON_##T, UP (B), CF (N, B), 0}
19059 #define VAR3(T, N, A, B, C) \
19060 VAR2 (T, N, A, B), \
19061 {#N, NEON_##T, UP (C), CF (N, C), 0}
19062 #define VAR4(T, N, A, B, C, D) \
19063 VAR3 (T, N, A, B, C), \
19064 {#N, NEON_##T, UP (D), CF (N, D), 0}
19065 #define VAR5(T, N, A, B, C, D, E) \
19066 VAR4 (T, N, A, B, C, D), \
19067 {#N, NEON_##T, UP (E), CF (N, E), 0}
19068 #define VAR6(T, N, A, B, C, D, E, F) \
19069 VAR5 (T, N, A, B, C, D, E), \
19070 {#N, NEON_##T, UP (F), CF (N, F), 0}
19071 #define VAR7(T, N, A, B, C, D, E, F, G) \
19072 VAR6 (T, N, A, B, C, D, E, F), \
19073 {#N, NEON_##T, UP (G), CF (N, G), 0}
19074 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
19075 VAR7 (T, N, A, B, C, D, E, F, G), \
19076 {#N, NEON_##T, UP (H), CF (N, H), 0}
19077 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
19078 VAR8 (T, N, A, B, C, D, E, F, G, H), \
19079 {#N, NEON_##T, UP (I), CF (N, I), 0}
19080 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
19081 VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
19082 {#N, NEON_##T, UP (J), CF (N, J), 0}
19084 /* The mode entries in the following table correspond to the "key" type of the
19085 instruction variant, i.e. equivalent to that which would be specified after
19086 the assembler mnemonic, which usually refers to the last vector operand.
19087 (Signed/unsigned/polynomial types are not differentiated between though, and
19088 are all mapped onto the same mode for a given element size.) The modes
19089 listed per instruction should be the same as those defined for that
19090 instruction's pattern in neon.md. */
19092 static neon_builtin_datum neon_builtin_data[] =
19094 VAR10 (BINOP, vadd,
19095 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19096 VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
19097 VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
19098 VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19099 VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19100 VAR3 (BINOP, vaddhn, v8hi, v4si, v2di),
19101 VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19102 VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19103 VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si),
19104 VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19105 VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si),
19106 VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si),
19107 VAR2 (TERNOP, vqdmlal, v4hi, v2si),
19108 VAR2 (TERNOP, vqdmlsl, v4hi, v2si),
19109 VAR3 (BINOP, vmull, v8qi, v4hi, v2si),
19110 VAR2 (SCALARMULL, vmull_n, v4hi, v2si),
19111 VAR2 (LANEMULL, vmull_lane, v4hi, v2si),
19112 VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si),
19113 VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si),
19114 VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si),
19115 VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si),
19116 VAR2 (BINOP, vqdmull, v4hi, v2si),
19117 VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19118 VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19119 VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19120 VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di),
19121 VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di),
19122 VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di),
19123 VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19124 VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19125 VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19126 VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
19127 VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19128 VAR10 (BINOP, vsub,
19129 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19130 VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
19131 VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
19132 VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19133 VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19134 VAR3 (BINOP, vsubhn, v8hi, v4si, v2di),
19135 VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19136 VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19137 VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19138 VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19139 VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19140 VAR2 (BINOP, vcage, v2sf, v4sf),
19141 VAR2 (BINOP, vcagt, v2sf, v4sf),
19142 VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19143 VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19144 VAR3 (BINOP, vabdl, v8qi, v4hi, v2si),
19145 VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19146 VAR3 (TERNOP, vabal, v8qi, v4hi, v2si),
19147 VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19148 VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19149 VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf),
19150 VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19151 VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19152 VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf),
19153 VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf),
19154 VAR2 (BINOP, vrecps, v2sf, v4sf),
19155 VAR2 (BINOP, vrsqrts, v2sf, v4sf),
19156 VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19157 VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19158 VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19159 VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19160 VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19161 VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19162 VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19163 VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19164 VAR2 (UNOP, vcnt, v8qi, v16qi),
19165 VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf),
19166 VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf),
19167 VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19168 /* FIXME: vget_lane supports more variants than this! */
19169 VAR10 (GETLANE, vget_lane,
19170 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19171 VAR10 (SETLANE, vset_lane,
19172 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19173 VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di),
19174 VAR10 (DUP, vdup_n,
19175 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19176 VAR10 (DUPLANE, vdup_lane,
19177 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19178 VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di),
19179 VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di),
19180 VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di),
19181 VAR3 (UNOP, vmovn, v8hi, v4si, v2di),
19182 VAR3 (UNOP, vqmovn, v8hi, v4si, v2di),
19183 VAR3 (UNOP, vqmovun, v8hi, v4si, v2di),
19184 VAR3 (UNOP, vmovl, v8qi, v4hi, v2si),
19185 VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19186 VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19187 VAR2 (LANEMAC, vmlal_lane, v4hi, v2si),
19188 VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si),
19189 VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19190 VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si),
19191 VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si),
19192 VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19193 VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19194 VAR2 (SCALARMAC, vmlal_n, v4hi, v2si),
19195 VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si),
19196 VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19197 VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si),
19198 VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si),
19199 VAR10 (BINOP, vext,
19200 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19201 VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19202 VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi),
19203 VAR2 (UNOP, vrev16, v8qi, v16qi),
19204 VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf),
19205 VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf),
19206 VAR10 (SELECT, vbsl,
19207 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19208 VAR1 (VTBL, vtbl1, v8qi),
19209 VAR1 (VTBL, vtbl2, v8qi),
19210 VAR1 (VTBL, vtbl3, v8qi),
19211 VAR1 (VTBL, vtbl4, v8qi),
19212 VAR1 (VTBX, vtbx1, v8qi),
19213 VAR1 (VTBX, vtbx2, v8qi),
19214 VAR1 (VTBX, vtbx3, v8qi),
19215 VAR1 (VTBX, vtbx4, v8qi),
19216 VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19217 VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19218 VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19219 VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di),
19220 VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
19221 VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
19222 VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di),
19223 VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di),
19224 VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di),
19225 VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di),
19226 VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di),
19227 VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di),
19228 VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di),
19229 VAR10 (LOAD1, vld1,
19230 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19231 VAR10 (LOAD1LANE, vld1_lane,
19232 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19233 VAR10 (LOAD1, vld1_dup,
19234 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19235 VAR10 (STORE1, vst1,
19236 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19237 VAR10 (STORE1LANE, vst1_lane,
19238 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19240 vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19241 VAR7 (LOADSTRUCTLANE, vld2_lane,
19242 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19243 VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di),
19244 VAR9 (STORESTRUCT, vst2,
19245 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19246 VAR7 (STORESTRUCTLANE, vst2_lane,
19247 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19249 vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19250 VAR7 (LOADSTRUCTLANE, vld3_lane,
19251 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19252 VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di),
19253 VAR9 (STORESTRUCT, vst3,
19254 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19255 VAR7 (STORESTRUCTLANE, vst3_lane,
19256 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19257 VAR9 (LOADSTRUCT, vld4,
19258 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19259 VAR7 (LOADSTRUCTLANE, vld4_lane,
19260 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19261 VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
19262 VAR9 (STORESTRUCT, vst4,
19263 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19264 VAR7 (STORESTRUCTLANE, vst4_lane,
19265 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19266 VAR10 (LOGICBINOP, vand,
19267 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19268 VAR10 (LOGICBINOP, vorr,
19269 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19270 VAR10 (BINOP, veor,
19271 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19272 VAR10 (LOGICBINOP, vbic,
19273 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19274 VAR10 (LOGICBINOP, vorn,
19275 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
19290 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
19291 symbolic names defined here (which would require too much duplication).
19295 ARM_BUILTIN_GETWCX,
19296 ARM_BUILTIN_SETWCX,
19300 ARM_BUILTIN_WAVG2BR,
19301 ARM_BUILTIN_WAVG2HR,
19302 ARM_BUILTIN_WAVG2B,
19303 ARM_BUILTIN_WAVG2H,
19310 ARM_BUILTIN_WMACSZ,
19312 ARM_BUILTIN_WMACUZ,
19315 ARM_BUILTIN_WSADBZ,
19317 ARM_BUILTIN_WSADHZ,
19319 ARM_BUILTIN_WALIGN,
19322 ARM_BUILTIN_TMIAPH,
19323 ARM_BUILTIN_TMIABB,
19324 ARM_BUILTIN_TMIABT,
19325 ARM_BUILTIN_TMIATB,
19326 ARM_BUILTIN_TMIATT,
19328 ARM_BUILTIN_TMOVMSKB,
19329 ARM_BUILTIN_TMOVMSKH,
19330 ARM_BUILTIN_TMOVMSKW,
19332 ARM_BUILTIN_TBCSTB,
19333 ARM_BUILTIN_TBCSTH,
19334 ARM_BUILTIN_TBCSTW,
19336 ARM_BUILTIN_WMADDS,
19337 ARM_BUILTIN_WMADDU,
19339 ARM_BUILTIN_WPACKHSS,
19340 ARM_BUILTIN_WPACKWSS,
19341 ARM_BUILTIN_WPACKDSS,
19342 ARM_BUILTIN_WPACKHUS,
19343 ARM_BUILTIN_WPACKWUS,
19344 ARM_BUILTIN_WPACKDUS,
19349 ARM_BUILTIN_WADDSSB,
19350 ARM_BUILTIN_WADDSSH,
19351 ARM_BUILTIN_WADDSSW,
19352 ARM_BUILTIN_WADDUSB,
19353 ARM_BUILTIN_WADDUSH,
19354 ARM_BUILTIN_WADDUSW,
19358 ARM_BUILTIN_WSUBSSB,
19359 ARM_BUILTIN_WSUBSSH,
19360 ARM_BUILTIN_WSUBSSW,
19361 ARM_BUILTIN_WSUBUSB,
19362 ARM_BUILTIN_WSUBUSH,
19363 ARM_BUILTIN_WSUBUSW,
19370 ARM_BUILTIN_WCMPEQB,
19371 ARM_BUILTIN_WCMPEQH,
19372 ARM_BUILTIN_WCMPEQW,
19373 ARM_BUILTIN_WCMPGTUB,
19374 ARM_BUILTIN_WCMPGTUH,
19375 ARM_BUILTIN_WCMPGTUW,
19376 ARM_BUILTIN_WCMPGTSB,
19377 ARM_BUILTIN_WCMPGTSH,
19378 ARM_BUILTIN_WCMPGTSW,
19380 ARM_BUILTIN_TEXTRMSB,
19381 ARM_BUILTIN_TEXTRMSH,
19382 ARM_BUILTIN_TEXTRMSW,
19383 ARM_BUILTIN_TEXTRMUB,
19384 ARM_BUILTIN_TEXTRMUH,
19385 ARM_BUILTIN_TEXTRMUW,
19386 ARM_BUILTIN_TINSRB,
19387 ARM_BUILTIN_TINSRH,
19388 ARM_BUILTIN_TINSRW,
19390 ARM_BUILTIN_WMAXSW,
19391 ARM_BUILTIN_WMAXSH,
19392 ARM_BUILTIN_WMAXSB,
19393 ARM_BUILTIN_WMAXUW,
19394 ARM_BUILTIN_WMAXUH,
19395 ARM_BUILTIN_WMAXUB,
19396 ARM_BUILTIN_WMINSW,
19397 ARM_BUILTIN_WMINSH,
19398 ARM_BUILTIN_WMINSB,
19399 ARM_BUILTIN_WMINUW,
19400 ARM_BUILTIN_WMINUH,
19401 ARM_BUILTIN_WMINUB,
19403 ARM_BUILTIN_WMULUM,
19404 ARM_BUILTIN_WMULSM,
19405 ARM_BUILTIN_WMULUL,
19407 ARM_BUILTIN_PSADBH,
19408 ARM_BUILTIN_WSHUFH,
19422 ARM_BUILTIN_WSLLHI,
19423 ARM_BUILTIN_WSLLWI,
19424 ARM_BUILTIN_WSLLDI,
19425 ARM_BUILTIN_WSRAHI,
19426 ARM_BUILTIN_WSRAWI,
19427 ARM_BUILTIN_WSRADI,
19428 ARM_BUILTIN_WSRLHI,
19429 ARM_BUILTIN_WSRLWI,
19430 ARM_BUILTIN_WSRLDI,
19431 ARM_BUILTIN_WRORHI,
19432 ARM_BUILTIN_WRORWI,
19433 ARM_BUILTIN_WRORDI,
19435 ARM_BUILTIN_WUNPCKIHB,
19436 ARM_BUILTIN_WUNPCKIHH,
19437 ARM_BUILTIN_WUNPCKIHW,
19438 ARM_BUILTIN_WUNPCKILB,
19439 ARM_BUILTIN_WUNPCKILH,
19440 ARM_BUILTIN_WUNPCKILW,
19442 ARM_BUILTIN_WUNPCKEHSB,
19443 ARM_BUILTIN_WUNPCKEHSH,
19444 ARM_BUILTIN_WUNPCKEHSW,
19445 ARM_BUILTIN_WUNPCKEHUB,
19446 ARM_BUILTIN_WUNPCKEHUH,
19447 ARM_BUILTIN_WUNPCKEHUW,
19448 ARM_BUILTIN_WUNPCKELSB,
19449 ARM_BUILTIN_WUNPCKELSH,
19450 ARM_BUILTIN_WUNPCKELSW,
19451 ARM_BUILTIN_WUNPCKELUB,
19452 ARM_BUILTIN_WUNPCKELUH,
19453 ARM_BUILTIN_WUNPCKELUW,
19455 ARM_BUILTIN_THREAD_POINTER,
19457 ARM_BUILTIN_NEON_BASE,
19459 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE + ARRAY_SIZE (neon_builtin_data)
19462 static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX];
19465 arm_init_neon_builtins (void)
19467 unsigned int i, fcode;
19470 tree neon_intQI_type_node;
19471 tree neon_intHI_type_node;
19472 tree neon_polyQI_type_node;
19473 tree neon_polyHI_type_node;
19474 tree neon_intSI_type_node;
19475 tree neon_intDI_type_node;
19476 tree neon_float_type_node;
19478 tree intQI_pointer_node;
19479 tree intHI_pointer_node;
19480 tree intSI_pointer_node;
19481 tree intDI_pointer_node;
19482 tree float_pointer_node;
19484 tree const_intQI_node;
19485 tree const_intHI_node;
19486 tree const_intSI_node;
19487 tree const_intDI_node;
19488 tree const_float_node;
19490 tree const_intQI_pointer_node;
19491 tree const_intHI_pointer_node;
19492 tree const_intSI_pointer_node;
19493 tree const_intDI_pointer_node;
19494 tree const_float_pointer_node;
19496 tree V8QI_type_node;
19497 tree V4HI_type_node;
19498 tree V2SI_type_node;
19499 tree V2SF_type_node;
19500 tree V16QI_type_node;
19501 tree V8HI_type_node;
19502 tree V4SI_type_node;
19503 tree V4SF_type_node;
19504 tree V2DI_type_node;
19506 tree intUQI_type_node;
19507 tree intUHI_type_node;
19508 tree intUSI_type_node;
19509 tree intUDI_type_node;
19511 tree intEI_type_node;
19512 tree intOI_type_node;
19513 tree intCI_type_node;
19514 tree intXI_type_node;
19516 tree V8QI_pointer_node;
19517 tree V4HI_pointer_node;
19518 tree V2SI_pointer_node;
19519 tree V2SF_pointer_node;
19520 tree V16QI_pointer_node;
19521 tree V8HI_pointer_node;
19522 tree V4SI_pointer_node;
19523 tree V4SF_pointer_node;
19524 tree V2DI_pointer_node;
19526 tree void_ftype_pv8qi_v8qi_v8qi;
19527 tree void_ftype_pv4hi_v4hi_v4hi;
19528 tree void_ftype_pv2si_v2si_v2si;
19529 tree void_ftype_pv2sf_v2sf_v2sf;
19530 tree void_ftype_pdi_di_di;
19531 tree void_ftype_pv16qi_v16qi_v16qi;
19532 tree void_ftype_pv8hi_v8hi_v8hi;
19533 tree void_ftype_pv4si_v4si_v4si;
19534 tree void_ftype_pv4sf_v4sf_v4sf;
19535 tree void_ftype_pv2di_v2di_v2di;
19537 tree reinterp_ftype_dreg[5][5];
19538 tree reinterp_ftype_qreg[5][5];
19539 tree dreg_types[5], qreg_types[5];
19541 /* Create distinguished type nodes for NEON vector element types,
19542 and pointers to values of such types, so we can detect them later. */
19543 neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
19544 neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
19545 neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
19546 neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
19547 neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode));
19548 neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode));
19549 neon_float_type_node = make_node (REAL_TYPE);
19550 TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE;
19551 layout_type (neon_float_type_node);
19553 /* Define typedefs which exactly correspond to the modes we are basing vector
19554 types on. If you change these names you'll need to change
19555 the table used by arm_mangle_type too. */
19556 (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node,
19557 "__builtin_neon_qi");
19558 (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node,
19559 "__builtin_neon_hi");
19560 (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node,
19561 "__builtin_neon_si");
19562 (*lang_hooks.types.register_builtin_type) (neon_float_type_node,
19563 "__builtin_neon_sf");
19564 (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node,
19565 "__builtin_neon_di");
19566 (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node,
19567 "__builtin_neon_poly8");
19568 (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node,
19569 "__builtin_neon_poly16");
19571 intQI_pointer_node = build_pointer_type (neon_intQI_type_node);
19572 intHI_pointer_node = build_pointer_type (neon_intHI_type_node);
19573 intSI_pointer_node = build_pointer_type (neon_intSI_type_node);
19574 intDI_pointer_node = build_pointer_type (neon_intDI_type_node);
19575 float_pointer_node = build_pointer_type (neon_float_type_node);
19577 /* Next create constant-qualified versions of the above types. */
19578 const_intQI_node = build_qualified_type (neon_intQI_type_node,
19580 const_intHI_node = build_qualified_type (neon_intHI_type_node,
19582 const_intSI_node = build_qualified_type (neon_intSI_type_node,
19584 const_intDI_node = build_qualified_type (neon_intDI_type_node,
19586 const_float_node = build_qualified_type (neon_float_type_node,
19589 const_intQI_pointer_node = build_pointer_type (const_intQI_node);
19590 const_intHI_pointer_node = build_pointer_type (const_intHI_node);
19591 const_intSI_pointer_node = build_pointer_type (const_intSI_node);
19592 const_intDI_pointer_node = build_pointer_type (const_intDI_node);
19593 const_float_pointer_node = build_pointer_type (const_float_node);
19595 /* Now create vector types based on our NEON element types. */
19596 /* 64-bit vectors. */
19598 build_vector_type_for_mode (neon_intQI_type_node, V8QImode);
19600 build_vector_type_for_mode (neon_intHI_type_node, V4HImode);
19602 build_vector_type_for_mode (neon_intSI_type_node, V2SImode);
19604 build_vector_type_for_mode (neon_float_type_node, V2SFmode);
19605 /* 128-bit vectors. */
19607 build_vector_type_for_mode (neon_intQI_type_node, V16QImode);
19609 build_vector_type_for_mode (neon_intHI_type_node, V8HImode);
19611 build_vector_type_for_mode (neon_intSI_type_node, V4SImode);
19613 build_vector_type_for_mode (neon_float_type_node, V4SFmode);
19615 build_vector_type_for_mode (neon_intDI_type_node, V2DImode);
19617 /* Unsigned integer types for various mode sizes. */
19618 intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode));
19619 intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode));
19620 intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode));
19621 intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode));
19623 (*lang_hooks.types.register_builtin_type) (intUQI_type_node,
19624 "__builtin_neon_uqi");
19625 (*lang_hooks.types.register_builtin_type) (intUHI_type_node,
19626 "__builtin_neon_uhi");
19627 (*lang_hooks.types.register_builtin_type) (intUSI_type_node,
19628 "__builtin_neon_usi");
19629 (*lang_hooks.types.register_builtin_type) (intUDI_type_node,
19630 "__builtin_neon_udi");
19632 /* Opaque integer types for structures of vectors. */
19633 intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode));
19634 intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode));
19635 intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode));
19636 intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode));
19638 (*lang_hooks.types.register_builtin_type) (intTI_type_node,
19639 "__builtin_neon_ti");
19640 (*lang_hooks.types.register_builtin_type) (intEI_type_node,
19641 "__builtin_neon_ei");
19642 (*lang_hooks.types.register_builtin_type) (intOI_type_node,
19643 "__builtin_neon_oi");
19644 (*lang_hooks.types.register_builtin_type) (intCI_type_node,
19645 "__builtin_neon_ci");
19646 (*lang_hooks.types.register_builtin_type) (intXI_type_node,
19647 "__builtin_neon_xi");
19649 /* Pointers to vector types. */
19650 V8QI_pointer_node = build_pointer_type (V8QI_type_node);
19651 V4HI_pointer_node = build_pointer_type (V4HI_type_node);
19652 V2SI_pointer_node = build_pointer_type (V2SI_type_node);
19653 V2SF_pointer_node = build_pointer_type (V2SF_type_node);
19654 V16QI_pointer_node = build_pointer_type (V16QI_type_node);
19655 V8HI_pointer_node = build_pointer_type (V8HI_type_node);
19656 V4SI_pointer_node = build_pointer_type (V4SI_type_node);
19657 V4SF_pointer_node = build_pointer_type (V4SF_type_node);
19658 V2DI_pointer_node = build_pointer_type (V2DI_type_node);
19660 /* Operations which return results as pairs. */
19661 void_ftype_pv8qi_v8qi_v8qi =
19662 build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node,
19663 V8QI_type_node, NULL);
19664 void_ftype_pv4hi_v4hi_v4hi =
19665 build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node,
19666 V4HI_type_node, NULL);
19667 void_ftype_pv2si_v2si_v2si =
19668 build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node,
19669 V2SI_type_node, NULL);
19670 void_ftype_pv2sf_v2sf_v2sf =
19671 build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node,
19672 V2SF_type_node, NULL);
19673 void_ftype_pdi_di_di =
19674 build_function_type_list (void_type_node, intDI_pointer_node,
19675 neon_intDI_type_node, neon_intDI_type_node, NULL);
19676 void_ftype_pv16qi_v16qi_v16qi =
19677 build_function_type_list (void_type_node, V16QI_pointer_node,
19678 V16QI_type_node, V16QI_type_node, NULL);
19679 void_ftype_pv8hi_v8hi_v8hi =
19680 build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node,
19681 V8HI_type_node, NULL);
19682 void_ftype_pv4si_v4si_v4si =
19683 build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node,
19684 V4SI_type_node, NULL);
19685 void_ftype_pv4sf_v4sf_v4sf =
19686 build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node,
19687 V4SF_type_node, NULL);
19688 void_ftype_pv2di_v2di_v2di =
19689 build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node,
19690 V2DI_type_node, NULL);
19692 dreg_types[0] = V8QI_type_node;
19693 dreg_types[1] = V4HI_type_node;
19694 dreg_types[2] = V2SI_type_node;
19695 dreg_types[3] = V2SF_type_node;
19696 dreg_types[4] = neon_intDI_type_node;
19698 qreg_types[0] = V16QI_type_node;
19699 qreg_types[1] = V8HI_type_node;
19700 qreg_types[2] = V4SI_type_node;
19701 qreg_types[3] = V4SF_type_node;
19702 qreg_types[4] = V2DI_type_node;
19704 for (i = 0; i < 5; i++)
19707 for (j = 0; j < 5; j++)
19709 reinterp_ftype_dreg[i][j]
19710 = build_function_type_list (dreg_types[i], dreg_types[j], NULL);
19711 reinterp_ftype_qreg[i][j]
19712 = build_function_type_list (qreg_types[i], qreg_types[j], NULL);
19716 for (i = 0, fcode = ARM_BUILTIN_NEON_BASE;
19717 i < ARRAY_SIZE (neon_builtin_data);
19720 neon_builtin_datum *d = &neon_builtin_data[i];
19722 const char* const modenames[] = {
19723 "v8qi", "v4hi", "v2si", "v2sf", "di",
19724 "v16qi", "v8hi", "v4si", "v4sf", "v2di",
19729 int is_load = 0, is_store = 0;
19731 gcc_assert (ARRAY_SIZE (modenames) == T_MAX);
19738 case NEON_LOAD1LANE:
19739 case NEON_LOADSTRUCT:
19740 case NEON_LOADSTRUCTLANE:
19742 /* Fall through. */
19744 case NEON_STORE1LANE:
19745 case NEON_STORESTRUCT:
19746 case NEON_STORESTRUCTLANE:
19749 /* Fall through. */
19752 case NEON_LOGICBINOP:
19753 case NEON_SHIFTINSERT:
19760 case NEON_SHIFTIMM:
19761 case NEON_SHIFTACC:
19767 case NEON_LANEMULL:
19768 case NEON_LANEMULH:
19770 case NEON_SCALARMUL:
19771 case NEON_SCALARMULL:
19772 case NEON_SCALARMULH:
19773 case NEON_SCALARMAC:
19779 tree return_type = void_type_node, args = void_list_node;
19781 /* Build a function type directly from the insn_data for
19782 this builtin. The build_function_type() function takes
19783 care of removing duplicates for us. */
19784 for (k = insn_data[d->code].n_generator_args - 1; k >= 0; k--)
19788 if (is_load && k == 1)
19790 /* Neon load patterns always have the memory
19791 operand in the operand 1 position. */
19792 gcc_assert (insn_data[d->code].operand[k].predicate
19793 == neon_struct_operand);
19799 eltype = const_intQI_pointer_node;
19804 eltype = const_intHI_pointer_node;
19809 eltype = const_intSI_pointer_node;
19814 eltype = const_float_pointer_node;
19819 eltype = const_intDI_pointer_node;
19822 default: gcc_unreachable ();
19825 else if (is_store && k == 0)
19827 /* Similarly, Neon store patterns use operand 0 as
19828 the memory location to store to. */
19829 gcc_assert (insn_data[d->code].operand[k].predicate
19830 == neon_struct_operand);
19836 eltype = intQI_pointer_node;
19841 eltype = intHI_pointer_node;
19846 eltype = intSI_pointer_node;
19851 eltype = float_pointer_node;
19856 eltype = intDI_pointer_node;
19859 default: gcc_unreachable ();
19864 switch (insn_data[d->code].operand[k].mode)
19866 case VOIDmode: eltype = void_type_node; break;
19868 case QImode: eltype = neon_intQI_type_node; break;
19869 case HImode: eltype = neon_intHI_type_node; break;
19870 case SImode: eltype = neon_intSI_type_node; break;
19871 case SFmode: eltype = neon_float_type_node; break;
19872 case DImode: eltype = neon_intDI_type_node; break;
19873 case TImode: eltype = intTI_type_node; break;
19874 case EImode: eltype = intEI_type_node; break;
19875 case OImode: eltype = intOI_type_node; break;
19876 case CImode: eltype = intCI_type_node; break;
19877 case XImode: eltype = intXI_type_node; break;
19878 /* 64-bit vectors. */
19879 case V8QImode: eltype = V8QI_type_node; break;
19880 case V4HImode: eltype = V4HI_type_node; break;
19881 case V2SImode: eltype = V2SI_type_node; break;
19882 case V2SFmode: eltype = V2SF_type_node; break;
19883 /* 128-bit vectors. */
19884 case V16QImode: eltype = V16QI_type_node; break;
19885 case V8HImode: eltype = V8HI_type_node; break;
19886 case V4SImode: eltype = V4SI_type_node; break;
19887 case V4SFmode: eltype = V4SF_type_node; break;
19888 case V2DImode: eltype = V2DI_type_node; break;
19889 default: gcc_unreachable ();
19893 if (k == 0 && !is_store)
19894 return_type = eltype;
19896 args = tree_cons (NULL_TREE, eltype, args);
19899 ftype = build_function_type (return_type, args);
19903 case NEON_RESULTPAIR:
19905 switch (insn_data[d->code].operand[1].mode)
19907 case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
19908 case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
19909 case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
19910 case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
19911 case DImode: ftype = void_ftype_pdi_di_di; break;
19912 case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
19913 case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
19914 case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
19915 case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
19916 case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
19917 default: gcc_unreachable ();
19922 case NEON_REINTERP:
19924 /* We iterate over 5 doubleword types, then 5 quadword
19926 int rhs = d->mode % 5;
19927 switch (insn_data[d->code].operand[0].mode)
19929 case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
19930 case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
19931 case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
19932 case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
19933 case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
19934 case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
19935 case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
19936 case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
19937 case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
19938 case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
19939 default: gcc_unreachable ();
19945 gcc_unreachable ();
19948 gcc_assert (ftype != NULL);
19950 sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[d->mode]);
19952 decl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, NULL,
19954 arm_builtin_decls[fcode] = decl;
19958 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
19961 if ((MASK) & insn_flags) \
19964 bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \
19965 BUILT_IN_MD, NULL, NULL_TREE); \
19966 arm_builtin_decls[CODE] = bdecl; \
19971 struct builtin_description
19973 const unsigned int mask;
19974 const enum insn_code icode;
19975 const char * const name;
19976 const enum arm_builtins code;
19977 const enum rtx_code comparison;
19978 const unsigned int flag;
19981 static const struct builtin_description bdesc_2arg[] =
19983 #define IWMMXT_BUILTIN(code, string, builtin) \
19984 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
19985 ARM_BUILTIN_##builtin, UNKNOWN, 0 },
19987 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
19988 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
19989 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
19990 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
19991 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
19992 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
19993 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
19994 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
19995 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
19996 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
19997 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
19998 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
19999 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
20000 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
20001 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
20002 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
20003 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
20004 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
20005 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
20006 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
20007 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
20008 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
20009 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
20010 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
20011 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
20012 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
20013 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
20014 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
20015 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
20016 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
20017 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
20018 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
20019 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
20020 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
20021 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
20022 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
20023 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
20024 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
20025 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
20026 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
20027 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
20028 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
20029 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
20030 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
20031 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
20032 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
20033 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
20034 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
20035 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
20036 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
20037 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
20038 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
20039 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
20040 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
20041 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
20042 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
20043 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
20044 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
20046 #define IWMMXT_BUILTIN2(code, builtin) \
20047 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
20049 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
20050 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
20051 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
20052 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
20053 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
20054 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
20055 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
20056 IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
20057 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
20058 IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
20059 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
20060 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
20061 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
20062 IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
20063 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
20064 IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
20065 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
20066 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
20067 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
20068 IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
20069 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
20070 IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
20071 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
20072 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
20073 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
20074 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
20075 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
20076 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
20077 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
20078 IWMMXT_BUILTIN2 (rordi3, WRORDI)
20079 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
20080 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
20083 static const struct builtin_description bdesc_1arg[] =
20085 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
20086 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
20087 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
20088 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
20089 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
20090 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
20091 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
20092 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
20093 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
20094 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
20095 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
20096 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
20097 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
20098 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
20099 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
20100 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
20101 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
20102 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
20105 /* Set up all the iWMMXt builtins. This is not called if
20106 TARGET_IWMMXT is zero. */
20109 arm_init_iwmmxt_builtins (void)
20111 const struct builtin_description * d;
20114 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
20115 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
20116 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
20119 = build_function_type_list (integer_type_node,
20120 integer_type_node, NULL_TREE);
20121 tree v8qi_ftype_v8qi_v8qi_int
20122 = build_function_type_list (V8QI_type_node,
20123 V8QI_type_node, V8QI_type_node,
20124 integer_type_node, NULL_TREE);
20125 tree v4hi_ftype_v4hi_int
20126 = build_function_type_list (V4HI_type_node,
20127 V4HI_type_node, integer_type_node, NULL_TREE);
20128 tree v2si_ftype_v2si_int
20129 = build_function_type_list (V2SI_type_node,
20130 V2SI_type_node, integer_type_node, NULL_TREE);
20131 tree v2si_ftype_di_di
20132 = build_function_type_list (V2SI_type_node,
20133 long_long_integer_type_node,
20134 long_long_integer_type_node,
20136 tree di_ftype_di_int
20137 = build_function_type_list (long_long_integer_type_node,
20138 long_long_integer_type_node,
20139 integer_type_node, NULL_TREE);
20140 tree di_ftype_di_int_int
20141 = build_function_type_list (long_long_integer_type_node,
20142 long_long_integer_type_node,
20144 integer_type_node, NULL_TREE);
20145 tree int_ftype_v8qi
20146 = build_function_type_list (integer_type_node,
20147 V8QI_type_node, NULL_TREE);
20148 tree int_ftype_v4hi
20149 = build_function_type_list (integer_type_node,
20150 V4HI_type_node, NULL_TREE);
20151 tree int_ftype_v2si
20152 = build_function_type_list (integer_type_node,
20153 V2SI_type_node, NULL_TREE);
20154 tree int_ftype_v8qi_int
20155 = build_function_type_list (integer_type_node,
20156 V8QI_type_node, integer_type_node, NULL_TREE);
20157 tree int_ftype_v4hi_int
20158 = build_function_type_list (integer_type_node,
20159 V4HI_type_node, integer_type_node, NULL_TREE);
20160 tree int_ftype_v2si_int
20161 = build_function_type_list (integer_type_node,
20162 V2SI_type_node, integer_type_node, NULL_TREE);
20163 tree v8qi_ftype_v8qi_int_int
20164 = build_function_type_list (V8QI_type_node,
20165 V8QI_type_node, integer_type_node,
20166 integer_type_node, NULL_TREE);
20167 tree v4hi_ftype_v4hi_int_int
20168 = build_function_type_list (V4HI_type_node,
20169 V4HI_type_node, integer_type_node,
20170 integer_type_node, NULL_TREE);
20171 tree v2si_ftype_v2si_int_int
20172 = build_function_type_list (V2SI_type_node,
20173 V2SI_type_node, integer_type_node,
20174 integer_type_node, NULL_TREE);
20175 /* Miscellaneous. */
20176 tree v8qi_ftype_v4hi_v4hi
20177 = build_function_type_list (V8QI_type_node,
20178 V4HI_type_node, V4HI_type_node, NULL_TREE);
20179 tree v4hi_ftype_v2si_v2si
20180 = build_function_type_list (V4HI_type_node,
20181 V2SI_type_node, V2SI_type_node, NULL_TREE);
20182 tree v2si_ftype_v4hi_v4hi
20183 = build_function_type_list (V2SI_type_node,
20184 V4HI_type_node, V4HI_type_node, NULL_TREE);
20185 tree v2si_ftype_v8qi_v8qi
20186 = build_function_type_list (V2SI_type_node,
20187 V8QI_type_node, V8QI_type_node, NULL_TREE);
20188 tree v4hi_ftype_v4hi_di
20189 = build_function_type_list (V4HI_type_node,
20190 V4HI_type_node, long_long_integer_type_node,
20192 tree v2si_ftype_v2si_di
20193 = build_function_type_list (V2SI_type_node,
20194 V2SI_type_node, long_long_integer_type_node,
20196 tree void_ftype_int_int
20197 = build_function_type_list (void_type_node,
20198 integer_type_node, integer_type_node,
20201 = build_function_type_list (long_long_unsigned_type_node, NULL_TREE);
20203 = build_function_type_list (long_long_integer_type_node,
20204 V8QI_type_node, NULL_TREE);
20206 = build_function_type_list (long_long_integer_type_node,
20207 V4HI_type_node, NULL_TREE);
20209 = build_function_type_list (long_long_integer_type_node,
20210 V2SI_type_node, NULL_TREE);
20211 tree v2si_ftype_v4hi
20212 = build_function_type_list (V2SI_type_node,
20213 V4HI_type_node, NULL_TREE);
20214 tree v4hi_ftype_v8qi
20215 = build_function_type_list (V4HI_type_node,
20216 V8QI_type_node, NULL_TREE);
20218 tree di_ftype_di_v4hi_v4hi
20219 = build_function_type_list (long_long_unsigned_type_node,
20220 long_long_unsigned_type_node,
20221 V4HI_type_node, V4HI_type_node,
20224 tree di_ftype_v4hi_v4hi
20225 = build_function_type_list (long_long_unsigned_type_node,
20226 V4HI_type_node,V4HI_type_node,
20229 /* Normal vector binops. */
20230 tree v8qi_ftype_v8qi_v8qi
20231 = build_function_type_list (V8QI_type_node,
20232 V8QI_type_node, V8QI_type_node, NULL_TREE);
20233 tree v4hi_ftype_v4hi_v4hi
20234 = build_function_type_list (V4HI_type_node,
20235 V4HI_type_node,V4HI_type_node, NULL_TREE);
20236 tree v2si_ftype_v2si_v2si
20237 = build_function_type_list (V2SI_type_node,
20238 V2SI_type_node, V2SI_type_node, NULL_TREE);
20239 tree di_ftype_di_di
20240 = build_function_type_list (long_long_unsigned_type_node,
20241 long_long_unsigned_type_node,
20242 long_long_unsigned_type_node,
20245 /* Add all builtins that are more or less simple operations on two
20247 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
20249 /* Use one of the operands; the target can have a different mode for
20250 mask-generating compares. */
20251 enum machine_mode mode;
20257 mode = insn_data[d->icode].operand[1].mode;
20262 type = v8qi_ftype_v8qi_v8qi;
20265 type = v4hi_ftype_v4hi_v4hi;
20268 type = v2si_ftype_v2si_v2si;
20271 type = di_ftype_di_di;
20275 gcc_unreachable ();
20278 def_mbuiltin (d->mask, d->name, type, d->code);
20281 /* Add the remaining MMX insns with somewhat more complicated types. */
20282 #define iwmmx_mbuiltin(NAME, TYPE, CODE) \
20283 def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \
20284 ARM_BUILTIN_ ## CODE)
20286 iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);
20287 iwmmx_mbuiltin ("setwcx", void_ftype_int_int, SETWCX);
20288 iwmmx_mbuiltin ("getwcx", int_ftype_int, GETWCX);
20290 iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH);
20291 iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW);
20292 iwmmx_mbuiltin ("wslld", di_ftype_di_di, WSLLD);
20293 iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int, WSLLHI);
20294 iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int, WSLLWI);
20295 iwmmx_mbuiltin ("wslldi", di_ftype_di_int, WSLLDI);
20297 iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di, WSRLH);
20298 iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di, WSRLW);
20299 iwmmx_mbuiltin ("wsrld", di_ftype_di_di, WSRLD);
20300 iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int, WSRLHI);
20301 iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int, WSRLWI);
20302 iwmmx_mbuiltin ("wsrldi", di_ftype_di_int, WSRLDI);
20304 iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di, WSRAH);
20305 iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di, WSRAW);
20306 iwmmx_mbuiltin ("wsrad", di_ftype_di_di, WSRAD);
20307 iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int, WSRAHI);
20308 iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int, WSRAWI);
20309 iwmmx_mbuiltin ("wsradi", di_ftype_di_int, WSRADI);
20311 iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di, WRORH);
20312 iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di, WRORW);
20313 iwmmx_mbuiltin ("wrord", di_ftype_di_di, WRORD);
20314 iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int, WRORHI);
20315 iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int, WRORWI);
20316 iwmmx_mbuiltin ("wrordi", di_ftype_di_int, WRORDI);
20318 iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH);
20320 iwmmx_mbuiltin ("wsadb", v2si_ftype_v8qi_v8qi, WSADB);
20321 iwmmx_mbuiltin ("wsadh", v2si_ftype_v4hi_v4hi, WSADH);
20322 iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ);
20323 iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ);
20325 iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int, TEXTRMSB);
20326 iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int, TEXTRMSH);
20327 iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int, TEXTRMSW);
20328 iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int, TEXTRMUB);
20329 iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int, TEXTRMUH);
20330 iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int, TEXTRMUW);
20331 iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int, TINSRB);
20332 iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int, TINSRH);
20333 iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int, TINSRW);
20335 iwmmx_mbuiltin ("waccb", di_ftype_v8qi, WACCB);
20336 iwmmx_mbuiltin ("wacch", di_ftype_v4hi, WACCH);
20337 iwmmx_mbuiltin ("waccw", di_ftype_v2si, WACCW);
20339 iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi, TMOVMSKB);
20340 iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH);
20341 iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW);
20343 iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS);
20344 iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS);
20345 iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS);
20346 iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si, WPACKWSS);
20347 iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di, WPACKDUS);
20348 iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di, WPACKDSS);
20350 iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi, WUNPCKEHUB);
20351 iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi, WUNPCKEHUH);
20352 iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si, WUNPCKEHUW);
20353 iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi, WUNPCKEHSB);
20354 iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi, WUNPCKEHSH);
20355 iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si, WUNPCKEHSW);
20356 iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi, WUNPCKELUB);
20357 iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi, WUNPCKELUH);
20358 iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si, WUNPCKELUW);
20359 iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi, WUNPCKELSB);
20360 iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi, WUNPCKELSH);
20361 iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si, WUNPCKELSW);
20363 iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi, WMACS);
20364 iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi, WMACSZ);
20365 iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU);
20366 iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ);
20368 iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGN);
20369 iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA);
20370 iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH);
20371 iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB);
20372 iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int, TMIABT);
20373 iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB);
20374 iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT);
20376 #undef iwmmx_mbuiltin
20380 arm_init_tls_builtins (void)
20384 ftype = build_function_type (ptr_type_node, void_list_node);
20385 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
20386 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
20388 TREE_NOTHROW (decl) = 1;
20389 TREE_READONLY (decl) = 1;
20390 arm_builtin_decls[ARM_BUILTIN_THREAD_POINTER] = decl;
20394 arm_init_fp16_builtins (void)
20396 tree fp16_type = make_node (REAL_TYPE);
20397 TYPE_PRECISION (fp16_type) = 16;
20398 layout_type (fp16_type);
20399 (*lang_hooks.types.register_builtin_type) (fp16_type, "__fp16");
20403 arm_init_builtins (void)
20405 arm_init_tls_builtins ();
20407 if (TARGET_REALLY_IWMMXT)
20408 arm_init_iwmmxt_builtins ();
20411 arm_init_neon_builtins ();
20413 if (arm_fp16_format)
20414 arm_init_fp16_builtins ();
20417 /* Return the ARM builtin for CODE. */
20420 arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
20422 if (code >= ARM_BUILTIN_MAX)
20423 return error_mark_node;
20425 return arm_builtin_decls[code];
20428 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
20430 static const char *
20431 arm_invalid_parameter_type (const_tree t)
20433 if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
20434 return N_("function parameters cannot have __fp16 type");
20438 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
20440 static const char *
20441 arm_invalid_return_type (const_tree t)
20443 if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
20444 return N_("functions cannot return __fp16 type");
20448 /* Implement TARGET_PROMOTED_TYPE. */
20451 arm_promoted_type (const_tree t)
20453 if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
20454 return float_type_node;
20458 /* Implement TARGET_CONVERT_TO_TYPE.
20459 Specifically, this hook implements the peculiarity of the ARM
20460 half-precision floating-point C semantics that requires conversions between
20461 __fp16 to or from double to do an intermediate conversion to float. */
20464 arm_convert_to_type (tree type, tree expr)
20466 tree fromtype = TREE_TYPE (expr);
20467 if (!SCALAR_FLOAT_TYPE_P (fromtype) || !SCALAR_FLOAT_TYPE_P (type))
20469 if ((TYPE_PRECISION (fromtype) == 16 && TYPE_PRECISION (type) > 32)
20470 || (TYPE_PRECISION (type) == 16 && TYPE_PRECISION (fromtype) > 32))
20471 return convert (type, convert (float_type_node, expr));
20475 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P.
20476 This simply adds HFmode as a supported mode; even though we don't
20477 implement arithmetic on this type directly, it's supported by
20478 optabs conversions, much the way the double-word arithmetic is
20479 special-cased in the default hook. */
20482 arm_scalar_mode_supported_p (enum machine_mode mode)
20484 if (mode == HFmode)
20485 return (arm_fp16_format != ARM_FP16_FORMAT_NONE);
20486 else if (ALL_FIXED_POINT_MODE_P (mode))
20489 return default_scalar_mode_supported_p (mode);
20492 /* Errors in the source file can cause expand_expr to return const0_rtx
20493 where we expect a vector. To avoid crashing, use one of the vector
20494 clear instructions. */
20497 safe_vector_operand (rtx x, enum machine_mode mode)
20499 if (x != const0_rtx)
20501 x = gen_reg_rtx (mode);
20503 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
20504 : gen_rtx_SUBREG (DImode, x, 0)));
20508 /* Subroutine of arm_expand_builtin to take care of binop insns. */
20511 arm_expand_binop_builtin (enum insn_code icode,
20512 tree exp, rtx target, bool allow_void)
20515 tree arg0 = CALL_EXPR_ARG (exp, 0);
20516 tree arg1 = CALL_EXPR_ARG (exp, 1);
20517 rtx op0 = expand_normal (arg0);
20518 rtx op1 = expand_normal (arg1);
20519 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20520 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20521 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20523 if (VECTOR_MODE_P (mode0))
20524 op0 = safe_vector_operand (op0, mode0);
20525 if (VECTOR_MODE_P (mode1))
20526 op1 = safe_vector_operand (op1, mode1);
20529 || GET_MODE (target) != tmode
20530 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20531 target = gen_reg_rtx (tmode);
20533 if (GET_MODE (op0) != mode0)
20535 error ("the first argument to the builtin has mode %s, expecting %s",
20536 mode_name[GET_MODE (op0)], mode_name[mode0]);
20537 /* Do not return a NULL_RTX - it causes an ICE in store_expr()
20538 which does not expect builtin expansion to fail. */
20542 if (GET_MODE (op1) != mode1)
20544 if (GET_MODE (op1) == VOIDmode)
20546 /* We are being passed a constant as our second parameter.
20547 If allow_void is true, assume that the pattern allows
20548 immediates. Otherwise, copy the value into a register. */
20550 op1 = copy_to_mode_reg (mode1, op1);
20554 error ("the second argument to the builtin has mode %s, expecting %s",
20555 mode_name[GET_MODE (op1)], mode_name[mode1]);
20560 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20561 op0 = copy_to_mode_reg (mode0, op0);
20562 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
20563 op1 = copy_to_mode_reg (mode1, op1);
20565 pat = GEN_FCN (icode) (target, op0, op1);
20572 /* Subroutine of arm_expand_builtin to take care of unop insns. */
20575 arm_expand_unop_builtin (enum insn_code icode,
20576 tree exp, rtx target, int do_load)
20579 tree arg0 = CALL_EXPR_ARG (exp, 0);
20580 rtx op0 = expand_normal (arg0);
20581 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20582 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20585 || GET_MODE (target) != tmode
20586 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20587 target = gen_reg_rtx (tmode);
20589 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20592 if (VECTOR_MODE_P (mode0))
20593 op0 = safe_vector_operand (op0, mode0);
20595 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20596 op0 = copy_to_mode_reg (mode0, op0);
20599 pat = GEN_FCN (icode) (target, op0);
20607 NEON_ARG_COPY_TO_REG,
20613 #define NEON_MAX_BUILTIN_ARGS 5
20615 /* EXP is a pointer argument to a Neon load or store intrinsic. Derive
20616 and return an expression for the accessed memory.
20618 The intrinsic function operates on a block of registers that has
20619 mode REG_MODE. This block contains vectors of type TYPE_MODE. The
20620 function references the memory at EXP of type TYPE and in mode
20621 MEM_MODE; this mode may be BLKmode if no more suitable mode is
20625 neon_dereference_pointer (tree exp, tree type, enum machine_mode mem_mode,
20626 enum machine_mode reg_mode,
20627 neon_builtin_type_mode type_mode)
20629 HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
20630 tree elem_type, upper_bound, array_type;
20632 /* Work out the size of the register block in bytes. */
20633 reg_size = GET_MODE_SIZE (reg_mode);
20635 /* Work out the size of each vector in bytes. */
20636 gcc_assert (TYPE_MODE_BIT (type_mode) & (TB_DREG | TB_QREG));
20637 vector_size = (TYPE_MODE_BIT (type_mode) & TB_QREG ? 16 : 8);
20639 /* Work out how many vectors there are. */
20640 gcc_assert (reg_size % vector_size == 0);
20641 nvectors = reg_size / vector_size;
20643 /* Work out the type of each element. */
20644 gcc_assert (POINTER_TYPE_P (type));
20645 elem_type = TREE_TYPE (type);
20647 /* Work out how many elements are being loaded or stored.
20648 MEM_MODE == REG_MODE implies a one-to-one mapping between register
20649 and memory elements; anything else implies a lane load or store. */
20650 if (mem_mode == reg_mode)
20651 nelems = vector_size * nvectors / int_size_in_bytes (elem_type);
20655 /* Create a type that describes the full access. */
20656 upper_bound = build_int_cst (size_type_node, nelems - 1);
20657 array_type = build_array_type (elem_type, build_index_type (upper_bound));
20659 /* Dereference EXP using that type. */
20660 return fold_build2 (MEM_REF, array_type, exp,
20661 build_int_cst (build_pointer_type (array_type), 0));
20664 /* Expand a Neon builtin. */
20666 arm_expand_neon_args (rtx target, int icode, int have_retval,
20667 neon_builtin_type_mode type_mode,
20668 tree exp, int fcode, ...)
20672 tree arg[NEON_MAX_BUILTIN_ARGS];
20673 rtx op[NEON_MAX_BUILTIN_ARGS];
20676 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20677 enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
20678 enum machine_mode other_mode;
20684 || GET_MODE (target) != tmode
20685 || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
20686 target = gen_reg_rtx (tmode);
20688 va_start (ap, fcode);
20690 formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode]));
20694 builtin_arg thisarg = (builtin_arg) va_arg (ap, int);
20696 if (thisarg == NEON_ARG_STOP)
20700 opno = argc + have_retval;
20701 mode[argc] = insn_data[icode].operand[opno].mode;
20702 arg[argc] = CALL_EXPR_ARG (exp, argc);
20703 arg_type = TREE_VALUE (formals);
20704 if (thisarg == NEON_ARG_MEMORY)
20706 other_mode = insn_data[icode].operand[1 - opno].mode;
20707 arg[argc] = neon_dereference_pointer (arg[argc], arg_type,
20708 mode[argc], other_mode,
20712 op[argc] = expand_normal (arg[argc]);
20716 case NEON_ARG_COPY_TO_REG:
20717 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
20718 if (!(*insn_data[icode].operand[opno].predicate)
20719 (op[argc], mode[argc]))
20720 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
20723 case NEON_ARG_CONSTANT:
20724 /* FIXME: This error message is somewhat unhelpful. */
20725 if (!(*insn_data[icode].operand[opno].predicate)
20726 (op[argc], mode[argc]))
20727 error ("argument must be a constant");
20730 case NEON_ARG_MEMORY:
20731 gcc_assert (MEM_P (op[argc]));
20732 PUT_MODE (op[argc], mode[argc]);
20733 /* ??? arm_neon.h uses the same built-in functions for signed
20734 and unsigned accesses, casting where necessary. This isn't
20736 set_mem_alias_set (op[argc], 0);
20737 if (!(*insn_data[icode].operand[opno].predicate)
20738 (op[argc], mode[argc]))
20739 op[argc] = (replace_equiv_address
20740 (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
20743 case NEON_ARG_STOP:
20744 gcc_unreachable ();
20748 formals = TREE_CHAIN (formals);
20758 pat = GEN_FCN (icode) (target, op[0]);
20762 pat = GEN_FCN (icode) (target, op[0], op[1]);
20766 pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
20770 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
20774 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
20778 gcc_unreachable ();
20784 pat = GEN_FCN (icode) (op[0]);
20788 pat = GEN_FCN (icode) (op[0], op[1]);
20792 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
20796 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
20800 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
20804 gcc_unreachable ();
20815 /* Expand a Neon builtin. These are "special" because they don't have symbolic
20816 constants defined per-instruction or per instruction-variant. Instead, the
20817 required info is looked up in the table neon_builtin_data. */
20819 arm_expand_neon_builtin (int fcode, tree exp, rtx target)
20821 neon_builtin_datum *d = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE];
20822 neon_itype itype = d->itype;
20823 enum insn_code icode = d->code;
20824 neon_builtin_type_mode type_mode = d->mode;
20831 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20832 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
20836 case NEON_SCALARMUL:
20837 case NEON_SCALARMULL:
20838 case NEON_SCALARMULH:
20839 case NEON_SHIFTINSERT:
20840 case NEON_LOGICBINOP:
20841 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20842 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
20846 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20847 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
20848 NEON_ARG_CONSTANT, NEON_ARG_STOP);
20852 case NEON_SHIFTIMM:
20853 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20854 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
20858 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20859 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
20863 case NEON_REINTERP:
20864 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20865 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
20869 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20870 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
20872 case NEON_RESULTPAIR:
20873 return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
20874 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
20878 case NEON_LANEMULL:
20879 case NEON_LANEMULH:
20880 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20881 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
20882 NEON_ARG_CONSTANT, NEON_ARG_STOP);
20885 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20886 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
20887 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
20889 case NEON_SHIFTACC:
20890 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20891 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
20892 NEON_ARG_CONSTANT, NEON_ARG_STOP);
20894 case NEON_SCALARMAC:
20895 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20896 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
20897 NEON_ARG_CONSTANT, NEON_ARG_STOP);
20901 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20902 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
20906 case NEON_LOADSTRUCT:
20907 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20908 NEON_ARG_MEMORY, NEON_ARG_STOP);
20910 case NEON_LOAD1LANE:
20911 case NEON_LOADSTRUCTLANE:
20912 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
20913 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
20917 case NEON_STORESTRUCT:
20918 return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
20919 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
20921 case NEON_STORE1LANE:
20922 case NEON_STORESTRUCTLANE:
20923 return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
20924 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
20928 gcc_unreachable ();
20931 /* Emit code to reinterpret one Neon type as another, without altering bits. */
20933 neon_reinterpret (rtx dest, rtx src)
20935 emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src));
20938 /* Emit code to place a Neon pair result in memory locations (with equal
20941 neon_emit_pair_result_insn (enum machine_mode mode,
20942 rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr,
20945 rtx mem = gen_rtx_MEM (mode, destaddr);
20946 rtx tmp1 = gen_reg_rtx (mode);
20947 rtx tmp2 = gen_reg_rtx (mode);
20949 emit_insn (intfn (tmp1, op1, op2, tmp2));
20951 emit_move_insn (mem, tmp1);
20952 mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
20953 emit_move_insn (mem, tmp2);
20956 /* Set up OPERANDS for a register copy from SRC to DEST, taking care
20957 not to early-clobber SRC registers in the process.
20959 We assume that the operands described by SRC and DEST represent a
20960 decomposed copy of OPERANDS[1] into OPERANDS[0]. COUNT is the
20961 number of components into which the copy has been decomposed. */
20963 neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count)
20967 if (!reg_overlap_mentioned_p (operands[0], operands[1])
20968 || REGNO (operands[0]) < REGNO (operands[1]))
20970 for (i = 0; i < count; i++)
20972 operands[2 * i] = dest[i];
20973 operands[2 * i + 1] = src[i];
20978 for (i = 0; i < count; i++)
20980 operands[2 * i] = dest[count - i - 1];
20981 operands[2 * i + 1] = src[count - i - 1];
20986 /* Split operands into moves from op[1] + op[2] into op[0]. */
20989 neon_split_vcombine (rtx operands[3])
20991 unsigned int dest = REGNO (operands[0]);
20992 unsigned int src1 = REGNO (operands[1]);
20993 unsigned int src2 = REGNO (operands[2]);
20994 enum machine_mode halfmode = GET_MODE (operands[1]);
20995 unsigned int halfregs = HARD_REGNO_NREGS (src1, halfmode);
20996 rtx destlo, desthi;
20998 if (src1 == dest && src2 == dest + halfregs)
21000 /* No-op move. Can't split to nothing; emit something. */
21001 emit_note (NOTE_INSN_DELETED);
21005 /* Preserve register attributes for variable tracking. */
21006 destlo = gen_rtx_REG_offset (operands[0], halfmode, dest, 0);
21007 desthi = gen_rtx_REG_offset (operands[0], halfmode, dest + halfregs,
21008 GET_MODE_SIZE (halfmode));
21010 /* Special case of reversed high/low parts. Use VSWP. */
21011 if (src2 == dest && src1 == dest + halfregs)
21013 rtx x = gen_rtx_SET (VOIDmode, destlo, operands[1]);
21014 rtx y = gen_rtx_SET (VOIDmode, desthi, operands[2]);
21015 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y)));
21019 if (!reg_overlap_mentioned_p (operands[2], destlo))
21021 /* Try to avoid unnecessary moves if part of the result
21022 is in the right place already. */
21024 emit_move_insn (destlo, operands[1]);
21025 if (src2 != dest + halfregs)
21026 emit_move_insn (desthi, operands[2]);
21030 if (src2 != dest + halfregs)
21031 emit_move_insn (desthi, operands[2]);
21033 emit_move_insn (destlo, operands[1]);
21037 /* Expand an expression EXP that calls a built-in function,
21038 with result going to TARGET if that's convenient
21039 (and in mode MODE if that's convenient).
21040 SUBTARGET may be used as the target for computing one of EXP's operands.
21041 IGNORE is nonzero if the value is to be ignored. */
21044 arm_expand_builtin (tree exp,
21046 rtx subtarget ATTRIBUTE_UNUSED,
21047 enum machine_mode mode ATTRIBUTE_UNUSED,
21048 int ignore ATTRIBUTE_UNUSED)
21050 const struct builtin_description * d;
21051 enum insn_code icode;
21052 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
21060 int fcode = DECL_FUNCTION_CODE (fndecl);
21062 enum machine_mode tmode;
21063 enum machine_mode mode0;
21064 enum machine_mode mode1;
21065 enum machine_mode mode2;
21067 if (fcode >= ARM_BUILTIN_NEON_BASE)
21068 return arm_expand_neon_builtin (fcode, exp, target);
21072 case ARM_BUILTIN_TEXTRMSB:
21073 case ARM_BUILTIN_TEXTRMUB:
21074 case ARM_BUILTIN_TEXTRMSH:
21075 case ARM_BUILTIN_TEXTRMUH:
21076 case ARM_BUILTIN_TEXTRMSW:
21077 case ARM_BUILTIN_TEXTRMUW:
21078 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
21079 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
21080 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
21081 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
21082 : CODE_FOR_iwmmxt_textrmw);
21084 arg0 = CALL_EXPR_ARG (exp, 0);
21085 arg1 = CALL_EXPR_ARG (exp, 1);
21086 op0 = expand_normal (arg0);
21087 op1 = expand_normal (arg1);
21088 tmode = insn_data[icode].operand[0].mode;
21089 mode0 = insn_data[icode].operand[1].mode;
21090 mode1 = insn_data[icode].operand[2].mode;
21092 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21093 op0 = copy_to_mode_reg (mode0, op0);
21094 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
21096 /* @@@ better error message */
21097 error ("selector must be an immediate");
21098 return gen_reg_rtx (tmode);
21101 || GET_MODE (target) != tmode
21102 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21103 target = gen_reg_rtx (tmode);
21104 pat = GEN_FCN (icode) (target, op0, op1);
21110 case ARM_BUILTIN_TINSRB:
21111 case ARM_BUILTIN_TINSRH:
21112 case ARM_BUILTIN_TINSRW:
21113 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
21114 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
21115 : CODE_FOR_iwmmxt_tinsrw);
21116 arg0 = CALL_EXPR_ARG (exp, 0);
21117 arg1 = CALL_EXPR_ARG (exp, 1);
21118 arg2 = CALL_EXPR_ARG (exp, 2);
21119 op0 = expand_normal (arg0);
21120 op1 = expand_normal (arg1);
21121 op2 = expand_normal (arg2);
21122 tmode = insn_data[icode].operand[0].mode;
21123 mode0 = insn_data[icode].operand[1].mode;
21124 mode1 = insn_data[icode].operand[2].mode;
21125 mode2 = insn_data[icode].operand[3].mode;
21127 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21128 op0 = copy_to_mode_reg (mode0, op0);
21129 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
21130 op1 = copy_to_mode_reg (mode1, op1);
21131 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
21133 /* @@@ better error message */
21134 error ("selector must be an immediate");
21138 || GET_MODE (target) != tmode
21139 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21140 target = gen_reg_rtx (tmode);
21141 pat = GEN_FCN (icode) (target, op0, op1, op2);
21147 case ARM_BUILTIN_SETWCX:
21148 arg0 = CALL_EXPR_ARG (exp, 0);
21149 arg1 = CALL_EXPR_ARG (exp, 1);
21150 op0 = force_reg (SImode, expand_normal (arg0));
21151 op1 = expand_normal (arg1);
21152 emit_insn (gen_iwmmxt_tmcr (op1, op0));
21155 case ARM_BUILTIN_GETWCX:
21156 arg0 = CALL_EXPR_ARG (exp, 0);
21157 op0 = expand_normal (arg0);
21158 target = gen_reg_rtx (SImode);
21159 emit_insn (gen_iwmmxt_tmrc (target, op0));
21162 case ARM_BUILTIN_WSHUFH:
21163 icode = CODE_FOR_iwmmxt_wshufh;
21164 arg0 = CALL_EXPR_ARG (exp, 0);
21165 arg1 = CALL_EXPR_ARG (exp, 1);
21166 op0 = expand_normal (arg0);
21167 op1 = expand_normal (arg1);
21168 tmode = insn_data[icode].operand[0].mode;
21169 mode1 = insn_data[icode].operand[1].mode;
21170 mode2 = insn_data[icode].operand[2].mode;
21172 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21173 op0 = copy_to_mode_reg (mode1, op0);
21174 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21176 /* @@@ better error message */
21177 error ("mask must be an immediate");
21181 || GET_MODE (target) != tmode
21182 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21183 target = gen_reg_rtx (tmode);
21184 pat = GEN_FCN (icode) (target, op0, op1);
21190 case ARM_BUILTIN_WSADB:
21191 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target, false);
21192 case ARM_BUILTIN_WSADH:
21193 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target, false);
21194 case ARM_BUILTIN_WSADBZ:
21195 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target, false);
21196 case ARM_BUILTIN_WSADHZ:
21197 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target, false);
21199 /* Several three-argument builtins. */
21200 case ARM_BUILTIN_WMACS:
21201 case ARM_BUILTIN_WMACU:
21202 case ARM_BUILTIN_WALIGN:
21203 case ARM_BUILTIN_TMIA:
21204 case ARM_BUILTIN_TMIAPH:
21205 case ARM_BUILTIN_TMIATT:
21206 case ARM_BUILTIN_TMIATB:
21207 case ARM_BUILTIN_TMIABT:
21208 case ARM_BUILTIN_TMIABB:
21209 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
21210 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
21211 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
21212 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
21213 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
21214 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
21215 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
21216 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
21217 : CODE_FOR_iwmmxt_walign);
21218 arg0 = CALL_EXPR_ARG (exp, 0);
21219 arg1 = CALL_EXPR_ARG (exp, 1);
21220 arg2 = CALL_EXPR_ARG (exp, 2);
21221 op0 = expand_normal (arg0);
21222 op1 = expand_normal (arg1);
21223 op2 = expand_normal (arg2);
21224 tmode = insn_data[icode].operand[0].mode;
21225 mode0 = insn_data[icode].operand[1].mode;
21226 mode1 = insn_data[icode].operand[2].mode;
21227 mode2 = insn_data[icode].operand[3].mode;
21229 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21230 op0 = copy_to_mode_reg (mode0, op0);
21231 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
21232 op1 = copy_to_mode_reg (mode1, op1);
21233 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
21234 op2 = copy_to_mode_reg (mode2, op2);
21236 || GET_MODE (target) != tmode
21237 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21238 target = gen_reg_rtx (tmode);
21239 pat = GEN_FCN (icode) (target, op0, op1, op2);
21245 case ARM_BUILTIN_WSLLHI:
21246 case ARM_BUILTIN_WSLLWI:
21247 case ARM_BUILTIN_WSLLDI:
21248 case ARM_BUILTIN_WSRAHI:
21249 case ARM_BUILTIN_WSRAWI:
21250 case ARM_BUILTIN_WSRADI:
21251 case ARM_BUILTIN_WSRLHI:
21252 case ARM_BUILTIN_WSRLWI:
21253 case ARM_BUILTIN_WSRLDI:
21254 case ARM_BUILTIN_WRORHI:
21255 case ARM_BUILTIN_WRORWI:
21256 case ARM_BUILTIN_WRORDI:
21257 icode = ( fcode == ARM_BUILTIN_WSLLHI ? CODE_FOR_ashlv4hi3_iwmmxt
21258 : fcode == ARM_BUILTIN_WSLLWI ? CODE_FOR_ashlv2si3_iwmmxt
21259 : fcode == ARM_BUILTIN_WSLLDI ? CODE_FOR_ashldi3_iwmmxt
21260 : fcode == ARM_BUILTIN_WSRAHI ? CODE_FOR_ashrv4hi3_iwmmxt
21261 : fcode == ARM_BUILTIN_WSRAWI ? CODE_FOR_ashrv2si3_iwmmxt
21262 : fcode == ARM_BUILTIN_WSRADI ? CODE_FOR_ashrdi3_iwmmxt
21263 : fcode == ARM_BUILTIN_WSRLHI ? CODE_FOR_lshrv4hi3_iwmmxt
21264 : fcode == ARM_BUILTIN_WSRLWI ? CODE_FOR_lshrv2si3_iwmmxt
21265 : fcode == ARM_BUILTIN_WSRLDI ? CODE_FOR_lshrdi3_iwmmxt
21266 : fcode == ARM_BUILTIN_WRORHI ? CODE_FOR_rorv4hi3
21267 : fcode == ARM_BUILTIN_WRORWI ? CODE_FOR_rorv2si3
21268 : /* ARM_BUILTIN_WRORDI */CODE_FOR_rordi3);
21269 return arm_expand_binop_builtin (icode, exp, target, true);
21271 case ARM_BUILTIN_WZERO:
21272 target = gen_reg_rtx (DImode);
21273 emit_insn (gen_iwmmxt_clrdi (target));
21276 case ARM_BUILTIN_THREAD_POINTER:
21277 return arm_load_tp (target);
21283 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
21284 if (d->code == (const enum arm_builtins) fcode)
21285 return arm_expand_binop_builtin (d->icode, exp, target, false);
21287 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
21288 if (d->code == (const enum arm_builtins) fcode)
21289 return arm_expand_unop_builtin (d->icode, exp, target, 0);
21291 /* @@@ Should really do something sensible here. */
21295 /* Return the number (counting from 0) of
21296 the least significant set bit in MASK. */
21299 number_of_first_bit_set (unsigned mask)
21301 return ctz_hwi (mask);
21304 /* Like emit_multi_reg_push, but allowing for a different set of
21305 registers to be described as saved. MASK is the set of registers
21306 to be saved; REAL_REGS is the set of registers to be described as
21307 saved. If REAL_REGS is 0, only describe the stack adjustment. */
21310 thumb1_emit_multi_reg_push (unsigned long mask, unsigned long real_regs)
21312 unsigned long regno;
21313 rtx par[10], tmp, reg, insn;
21316 /* Build the parallel of the registers actually being stored. */
21317 for (i = 0; mask; ++i, mask &= mask - 1)
21319 regno = ctz_hwi (mask);
21320 reg = gen_rtx_REG (SImode, regno);
21323 tmp = gen_rtx_UNSPEC (BLKmode, gen_rtvec (1, reg), UNSPEC_PUSH_MULT);
21325 tmp = gen_rtx_USE (VOIDmode, reg);
21330 tmp = plus_constant (stack_pointer_rtx, -4 * i);
21331 tmp = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, tmp);
21332 tmp = gen_frame_mem (BLKmode, tmp);
21333 tmp = gen_rtx_SET (VOIDmode, tmp, par[0]);
21336 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (i, par));
21337 insn = emit_insn (tmp);
21339 /* Always build the stack adjustment note for unwind info. */
21340 tmp = plus_constant (stack_pointer_rtx, -4 * i);
21341 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp);
21344 /* Build the parallel of the registers recorded as saved for unwind. */
21345 for (j = 0; real_regs; ++j, real_regs &= real_regs - 1)
21347 regno = ctz_hwi (real_regs);
21348 reg = gen_rtx_REG (SImode, regno);
21350 tmp = plus_constant (stack_pointer_rtx, j * 4);
21351 tmp = gen_frame_mem (SImode, tmp);
21352 tmp = gen_rtx_SET (VOIDmode, tmp, reg);
21353 RTX_FRAME_RELATED_P (tmp) = 1;
21361 RTX_FRAME_RELATED_P (par[0]) = 1;
21362 tmp = gen_rtx_SEQUENCE (VOIDmode, gen_rtvec_v (j + 1, par));
21365 add_reg_note (insn, REG_FRAME_RELATED_EXPR, tmp);
21370 /* Emit code to push or pop registers to or from the stack. F is the
21371 assembly file. MASK is the registers to pop. */
21373 thumb_pop (FILE *f, unsigned long mask)
21376 int lo_mask = mask & 0xFF;
21377 int pushed_words = 0;
21381 if (lo_mask == 0 && (mask & (1 << PC_REGNUM)))
21383 /* Special case. Do not generate a POP PC statement here, do it in
21385 thumb_exit (f, -1);
21389 fprintf (f, "\tpop\t{");
21391 /* Look at the low registers first. */
21392 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
21396 asm_fprintf (f, "%r", regno);
21398 if ((lo_mask & ~1) != 0)
21405 if (mask & (1 << PC_REGNUM))
21407 /* Catch popping the PC. */
21408 if (TARGET_INTERWORK || TARGET_BACKTRACE
21409 || crtl->calls_eh_return)
21411 /* The PC is never poped directly, instead
21412 it is popped into r3 and then BX is used. */
21413 fprintf (f, "}\n");
21415 thumb_exit (f, -1);
21424 asm_fprintf (f, "%r", PC_REGNUM);
21428 fprintf (f, "}\n");
21431 /* Generate code to return from a thumb function.
21432 If 'reg_containing_return_addr' is -1, then the return address is
21433 actually on the stack, at the stack pointer. */
21435 thumb_exit (FILE *f, int reg_containing_return_addr)
21437 unsigned regs_available_for_popping;
21438 unsigned regs_to_pop;
21440 unsigned available;
21444 int restore_a4 = FALSE;
21446 /* Compute the registers we need to pop. */
21450 if (reg_containing_return_addr == -1)
21452 regs_to_pop |= 1 << LR_REGNUM;
21456 if (TARGET_BACKTRACE)
21458 /* Restore the (ARM) frame pointer and stack pointer. */
21459 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
21463 /* If there is nothing to pop then just emit the BX instruction and
21465 if (pops_needed == 0)
21467 if (crtl->calls_eh_return)
21468 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
21470 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
21473 /* Otherwise if we are not supporting interworking and we have not created
21474 a backtrace structure and the function was not entered in ARM mode then
21475 just pop the return address straight into the PC. */
21476 else if (!TARGET_INTERWORK
21477 && !TARGET_BACKTRACE
21478 && !is_called_in_ARM_mode (current_function_decl)
21479 && !crtl->calls_eh_return)
21481 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
21485 /* Find out how many of the (return) argument registers we can corrupt. */
21486 regs_available_for_popping = 0;
21488 /* If returning via __builtin_eh_return, the bottom three registers
21489 all contain information needed for the return. */
21490 if (crtl->calls_eh_return)
21494 /* If we can deduce the registers used from the function's
21495 return value. This is more reliable that examining
21496 df_regs_ever_live_p () because that will be set if the register is
21497 ever used in the function, not just if the register is used
21498 to hold a return value. */
21500 if (crtl->return_rtx != 0)
21501 mode = GET_MODE (crtl->return_rtx);
21503 mode = DECL_MODE (DECL_RESULT (current_function_decl));
21505 size = GET_MODE_SIZE (mode);
21509 /* In a void function we can use any argument register.
21510 In a function that returns a structure on the stack
21511 we can use the second and third argument registers. */
21512 if (mode == VOIDmode)
21513 regs_available_for_popping =
21514 (1 << ARG_REGISTER (1))
21515 | (1 << ARG_REGISTER (2))
21516 | (1 << ARG_REGISTER (3));
21518 regs_available_for_popping =
21519 (1 << ARG_REGISTER (2))
21520 | (1 << ARG_REGISTER (3));
21522 else if (size <= 4)
21523 regs_available_for_popping =
21524 (1 << ARG_REGISTER (2))
21525 | (1 << ARG_REGISTER (3));
21526 else if (size <= 8)
21527 regs_available_for_popping =
21528 (1 << ARG_REGISTER (3));
21531 /* Match registers to be popped with registers into which we pop them. */
21532 for (available = regs_available_for_popping,
21533 required = regs_to_pop;
21534 required != 0 && available != 0;
21535 available &= ~(available & - available),
21536 required &= ~(required & - required))
21539 /* If we have any popping registers left over, remove them. */
21541 regs_available_for_popping &= ~available;
21543 /* Otherwise if we need another popping register we can use
21544 the fourth argument register. */
21545 else if (pops_needed)
21547 /* If we have not found any free argument registers and
21548 reg a4 contains the return address, we must move it. */
21549 if (regs_available_for_popping == 0
21550 && reg_containing_return_addr == LAST_ARG_REGNUM)
21552 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
21553 reg_containing_return_addr = LR_REGNUM;
21555 else if (size > 12)
21557 /* Register a4 is being used to hold part of the return value,
21558 but we have dire need of a free, low register. */
21561 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
21564 if (reg_containing_return_addr != LAST_ARG_REGNUM)
21566 /* The fourth argument register is available. */
21567 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
21573 /* Pop as many registers as we can. */
21574 thumb_pop (f, regs_available_for_popping);
21576 /* Process the registers we popped. */
21577 if (reg_containing_return_addr == -1)
21579 /* The return address was popped into the lowest numbered register. */
21580 regs_to_pop &= ~(1 << LR_REGNUM);
21582 reg_containing_return_addr =
21583 number_of_first_bit_set (regs_available_for_popping);
21585 /* Remove this register for the mask of available registers, so that
21586 the return address will not be corrupted by further pops. */
21587 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
21590 /* If we popped other registers then handle them here. */
21591 if (regs_available_for_popping)
21595 /* Work out which register currently contains the frame pointer. */
21596 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
21598 /* Move it into the correct place. */
21599 asm_fprintf (f, "\tmov\t%r, %r\n",
21600 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
21602 /* (Temporarily) remove it from the mask of popped registers. */
21603 regs_available_for_popping &= ~(1 << frame_pointer);
21604 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
21606 if (regs_available_for_popping)
21610 /* We popped the stack pointer as well,
21611 find the register that contains it. */
21612 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
21614 /* Move it into the stack register. */
21615 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
21617 /* At this point we have popped all necessary registers, so
21618 do not worry about restoring regs_available_for_popping
21619 to its correct value:
21621 assert (pops_needed == 0)
21622 assert (regs_available_for_popping == (1 << frame_pointer))
21623 assert (regs_to_pop == (1 << STACK_POINTER)) */
21627 /* Since we have just move the popped value into the frame
21628 pointer, the popping register is available for reuse, and
21629 we know that we still have the stack pointer left to pop. */
21630 regs_available_for_popping |= (1 << frame_pointer);
21634 /* If we still have registers left on the stack, but we no longer have
21635 any registers into which we can pop them, then we must move the return
21636 address into the link register and make available the register that
21638 if (regs_available_for_popping == 0 && pops_needed > 0)
21640 regs_available_for_popping |= 1 << reg_containing_return_addr;
21642 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
21643 reg_containing_return_addr);
21645 reg_containing_return_addr = LR_REGNUM;
21648 /* If we have registers left on the stack then pop some more.
21649 We know that at most we will want to pop FP and SP. */
21650 if (pops_needed > 0)
21655 thumb_pop (f, regs_available_for_popping);
21657 /* We have popped either FP or SP.
21658 Move whichever one it is into the correct register. */
21659 popped_into = number_of_first_bit_set (regs_available_for_popping);
21660 move_to = number_of_first_bit_set (regs_to_pop);
21662 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
21664 regs_to_pop &= ~(1 << move_to);
21669 /* If we still have not popped everything then we must have only
21670 had one register available to us and we are now popping the SP. */
21671 if (pops_needed > 0)
21675 thumb_pop (f, regs_available_for_popping);
21677 popped_into = number_of_first_bit_set (regs_available_for_popping);
21679 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
21681 assert (regs_to_pop == (1 << STACK_POINTER))
21682 assert (pops_needed == 1)
21686 /* If necessary restore the a4 register. */
21689 if (reg_containing_return_addr != LR_REGNUM)
21691 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
21692 reg_containing_return_addr = LR_REGNUM;
21695 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
21698 if (crtl->calls_eh_return)
21699 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
21701 /* Return to caller. */
21702 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
21705 /* Scan INSN just before assembler is output for it.
21706 For Thumb-1, we track the status of the condition codes; this
21707 information is used in the cbranchsi4_insn pattern. */
21709 thumb1_final_prescan_insn (rtx insn)
21711 if (flag_print_asm_name)
21712 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
21713 INSN_ADDRESSES (INSN_UID (insn)));
21714 /* Don't overwrite the previous setter when we get to a cbranch. */
21715 if (INSN_CODE (insn) != CODE_FOR_cbranchsi4_insn)
21717 enum attr_conds conds;
21719 if (cfun->machine->thumb1_cc_insn)
21721 if (modified_in_p (cfun->machine->thumb1_cc_op0, insn)
21722 || modified_in_p (cfun->machine->thumb1_cc_op1, insn))
21725 conds = get_attr_conds (insn);
21726 if (conds == CONDS_SET)
21728 rtx set = single_set (insn);
21729 cfun->machine->thumb1_cc_insn = insn;
21730 cfun->machine->thumb1_cc_op0 = SET_DEST (set);
21731 cfun->machine->thumb1_cc_op1 = const0_rtx;
21732 cfun->machine->thumb1_cc_mode = CC_NOOVmode;
21733 if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn)
21735 rtx src1 = XEXP (SET_SRC (set), 1);
21736 if (src1 == const0_rtx)
21737 cfun->machine->thumb1_cc_mode = CCmode;
21740 else if (conds != CONDS_NOCOND)
21741 cfun->machine->thumb1_cc_insn = NULL_RTX;
21746 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
21748 unsigned HOST_WIDE_INT mask = 0xff;
21751 val = val & (unsigned HOST_WIDE_INT)0xffffffffu;
21752 if (val == 0) /* XXX */
21755 for (i = 0; i < 25; i++)
21756 if ((val & (mask << i)) == val)
21762 /* Returns nonzero if the current function contains,
21763 or might contain a far jump. */
21765 thumb_far_jump_used_p (void)
21769 /* This test is only important for leaf functions. */
21770 /* assert (!leaf_function_p ()); */
21772 /* If we have already decided that far jumps may be used,
21773 do not bother checking again, and always return true even if
21774 it turns out that they are not being used. Once we have made
21775 the decision that far jumps are present (and that hence the link
21776 register will be pushed onto the stack) we cannot go back on it. */
21777 if (cfun->machine->far_jump_used)
21780 /* If this function is not being called from the prologue/epilogue
21781 generation code then it must be being called from the
21782 INITIAL_ELIMINATION_OFFSET macro. */
21783 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
21785 /* In this case we know that we are being asked about the elimination
21786 of the arg pointer register. If that register is not being used,
21787 then there are no arguments on the stack, and we do not have to
21788 worry that a far jump might force the prologue to push the link
21789 register, changing the stack offsets. In this case we can just
21790 return false, since the presence of far jumps in the function will
21791 not affect stack offsets.
21793 If the arg pointer is live (or if it was live, but has now been
21794 eliminated and so set to dead) then we do have to test to see if
21795 the function might contain a far jump. This test can lead to some
21796 false negatives, since before reload is completed, then length of
21797 branch instructions is not known, so gcc defaults to returning their
21798 longest length, which in turn sets the far jump attribute to true.
21800 A false negative will not result in bad code being generated, but it
21801 will result in a needless push and pop of the link register. We
21802 hope that this does not occur too often.
21804 If we need doubleword stack alignment this could affect the other
21805 elimination offsets so we can't risk getting it wrong. */
21806 if (df_regs_ever_live_p (ARG_POINTER_REGNUM))
21807 cfun->machine->arg_pointer_live = 1;
21808 else if (!cfun->machine->arg_pointer_live)
21812 /* Check to see if the function contains a branch
21813 insn with the far jump attribute set. */
21814 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
21816 if (GET_CODE (insn) == JUMP_INSN
21817 /* Ignore tablejump patterns. */
21818 && GET_CODE (PATTERN (insn)) != ADDR_VEC
21819 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
21820 && get_attr_far_jump (insn) == FAR_JUMP_YES
21823 /* Record the fact that we have decided that
21824 the function does use far jumps. */
21825 cfun->machine->far_jump_used = 1;
21833 /* Return nonzero if FUNC must be entered in ARM mode. */
21835 is_called_in_ARM_mode (tree func)
21837 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
21839 /* Ignore the problem about functions whose address is taken. */
21840 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
21844 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
21850 /* Given the stack offsets and register mask in OFFSETS, decide how
21851 many additional registers to push instead of subtracting a constant
21852 from SP. For epilogues the principle is the same except we use pop.
21853 FOR_PROLOGUE indicates which we're generating. */
21855 thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue)
21857 HOST_WIDE_INT amount;
21858 unsigned long live_regs_mask = offsets->saved_regs_mask;
21859 /* Extract a mask of the ones we can give to the Thumb's push/pop
21861 unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff);
21862 /* Then count how many other high registers will need to be pushed. */
21863 unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
21864 int n_free, reg_base, size;
21866 if (!for_prologue && frame_pointer_needed)
21867 amount = offsets->locals_base - offsets->saved_regs;
21869 amount = offsets->outgoing_args - offsets->saved_regs;
21871 /* If the stack frame size is 512 exactly, we can save one load
21872 instruction, which should make this a win even when optimizing
21874 if (!optimize_size && amount != 512)
21877 /* Can't do this if there are high registers to push. */
21878 if (high_regs_pushed != 0)
21881 /* Shouldn't do it in the prologue if no registers would normally
21882 be pushed at all. In the epilogue, also allow it if we'll have
21883 a pop insn for the PC. */
21886 || TARGET_BACKTRACE
21887 || (live_regs_mask & 1 << LR_REGNUM) == 0
21888 || TARGET_INTERWORK
21889 || crtl->args.pretend_args_size != 0))
21892 /* Don't do this if thumb_expand_prologue wants to emit instructions
21893 between the push and the stack frame allocation. */
21895 && ((flag_pic && arm_pic_register != INVALID_REGNUM)
21896 || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)))
21903 size = arm_size_return_regs ();
21904 reg_base = ARM_NUM_INTS (size);
21905 live_regs_mask >>= reg_base;
21908 while (reg_base + n_free < 8 && !(live_regs_mask & 1)
21909 && (for_prologue || call_used_regs[reg_base + n_free]))
21911 live_regs_mask >>= 1;
21917 gcc_assert (amount / 4 * 4 == amount);
21919 if (amount >= 512 && (amount - n_free * 4) < 512)
21920 return (amount - 508) / 4;
21921 if (amount <= n_free * 4)
21926 /* The bits which aren't usefully expanded as rtl. */
21928 thumb_unexpanded_epilogue (void)
21930 arm_stack_offsets *offsets;
21932 unsigned long live_regs_mask = 0;
21933 int high_regs_pushed = 0;
21935 int had_to_push_lr;
21938 if (cfun->machine->return_used_this_function != 0)
21941 if (IS_NAKED (arm_current_func_type ()))
21944 offsets = arm_get_frame_offsets ();
21945 live_regs_mask = offsets->saved_regs_mask;
21946 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
21948 /* If we can deduce the registers used from the function's return value.
21949 This is more reliable that examining df_regs_ever_live_p () because that
21950 will be set if the register is ever used in the function, not just if
21951 the register is used to hold a return value. */
21952 size = arm_size_return_regs ();
21954 extra_pop = thumb1_extra_regs_pushed (offsets, false);
21957 unsigned long extra_mask = (1 << extra_pop) - 1;
21958 live_regs_mask |= extra_mask << ARM_NUM_INTS (size);
21961 /* The prolog may have pushed some high registers to use as
21962 work registers. e.g. the testsuite file:
21963 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
21964 compiles to produce:
21965 push {r4, r5, r6, r7, lr}
21969 as part of the prolog. We have to undo that pushing here. */
21971 if (high_regs_pushed)
21973 unsigned long mask = live_regs_mask & 0xff;
21976 /* The available low registers depend on the size of the value we are
21984 /* Oh dear! We have no low registers into which we can pop
21987 ("no low registers available for popping high registers");
21989 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
21990 if (live_regs_mask & (1 << next_hi_reg))
21993 while (high_regs_pushed)
21995 /* Find lo register(s) into which the high register(s) can
21997 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
21999 if (mask & (1 << regno))
22000 high_regs_pushed--;
22001 if (high_regs_pushed == 0)
22005 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
22007 /* Pop the values into the low register(s). */
22008 thumb_pop (asm_out_file, mask);
22010 /* Move the value(s) into the high registers. */
22011 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
22013 if (mask & (1 << regno))
22015 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
22018 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
22019 if (live_regs_mask & (1 << next_hi_reg))
22024 live_regs_mask &= ~0x0f00;
22027 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
22028 live_regs_mask &= 0xff;
22030 if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE)
22032 /* Pop the return address into the PC. */
22033 if (had_to_push_lr)
22034 live_regs_mask |= 1 << PC_REGNUM;
22036 /* Either no argument registers were pushed or a backtrace
22037 structure was created which includes an adjusted stack
22038 pointer, so just pop everything. */
22039 if (live_regs_mask)
22040 thumb_pop (asm_out_file, live_regs_mask);
22042 /* We have either just popped the return address into the
22043 PC or it is was kept in LR for the entire function.
22044 Note that thumb_pop has already called thumb_exit if the
22045 PC was in the list. */
22046 if (!had_to_push_lr)
22047 thumb_exit (asm_out_file, LR_REGNUM);
22051 /* Pop everything but the return address. */
22052 if (live_regs_mask)
22053 thumb_pop (asm_out_file, live_regs_mask);
22055 if (had_to_push_lr)
22059 /* We have no free low regs, so save one. */
22060 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
22064 /* Get the return address into a temporary register. */
22065 thumb_pop (asm_out_file, 1 << LAST_ARG_REGNUM);
22069 /* Move the return address to lr. */
22070 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
22072 /* Restore the low register. */
22073 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
22078 regno = LAST_ARG_REGNUM;
22083 /* Remove the argument registers that were pushed onto the stack. */
22084 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
22085 SP_REGNUM, SP_REGNUM,
22086 crtl->args.pretend_args_size);
22088 thumb_exit (asm_out_file, regno);
22094 /* Functions to save and restore machine-specific function data. */
22095 static struct machine_function *
22096 arm_init_machine_status (void)
22098 struct machine_function *machine;
22099 machine = ggc_alloc_cleared_machine_function ();
22101 #if ARM_FT_UNKNOWN != 0
22102 machine->func_type = ARM_FT_UNKNOWN;
22107 /* Return an RTX indicating where the return address to the
22108 calling function can be found. */
22110 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
22115 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
22118 /* Do anything needed before RTL is emitted for each function. */
22120 arm_init_expanders (void)
22122 /* Arrange to initialize and mark the machine per-function status. */
22123 init_machine_status = arm_init_machine_status;
22125 /* This is to stop the combine pass optimizing away the alignment
22126 adjustment of va_arg. */
22127 /* ??? It is claimed that this should not be necessary. */
22129 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
22133 /* Like arm_compute_initial_elimination offset. Simpler because there
22134 isn't an ABI specified frame pointer for Thumb. Instead, we set it
22135 to point at the base of the local variables after static stack
22136 space for a function has been allocated. */
22139 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
22141 arm_stack_offsets *offsets;
22143 offsets = arm_get_frame_offsets ();
22147 case ARG_POINTER_REGNUM:
22150 case STACK_POINTER_REGNUM:
22151 return offsets->outgoing_args - offsets->saved_args;
22153 case FRAME_POINTER_REGNUM:
22154 return offsets->soft_frame - offsets->saved_args;
22156 case ARM_HARD_FRAME_POINTER_REGNUM:
22157 return offsets->saved_regs - offsets->saved_args;
22159 case THUMB_HARD_FRAME_POINTER_REGNUM:
22160 return offsets->locals_base - offsets->saved_args;
22163 gcc_unreachable ();
22167 case FRAME_POINTER_REGNUM:
22170 case STACK_POINTER_REGNUM:
22171 return offsets->outgoing_args - offsets->soft_frame;
22173 case ARM_HARD_FRAME_POINTER_REGNUM:
22174 return offsets->saved_regs - offsets->soft_frame;
22176 case THUMB_HARD_FRAME_POINTER_REGNUM:
22177 return offsets->locals_base - offsets->soft_frame;
22180 gcc_unreachable ();
22185 gcc_unreachable ();
22189 /* Generate the function's prologue. */
22192 thumb1_expand_prologue (void)
22196 HOST_WIDE_INT amount;
22197 arm_stack_offsets *offsets;
22198 unsigned long func_type;
22200 unsigned long live_regs_mask;
22201 unsigned long l_mask;
22202 unsigned high_regs_pushed = 0;
22204 func_type = arm_current_func_type ();
22206 /* Naked functions don't have prologues. */
22207 if (IS_NAKED (func_type))
22210 if (IS_INTERRUPT (func_type))
22212 error ("interrupt Service Routines cannot be coded in Thumb mode");
22216 if (is_called_in_ARM_mode (current_function_decl))
22217 emit_insn (gen_prologue_thumb1_interwork ());
22219 offsets = arm_get_frame_offsets ();
22220 live_regs_mask = offsets->saved_regs_mask;
22222 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
22223 l_mask = live_regs_mask & 0x40ff;
22224 /* Then count how many other high registers will need to be pushed. */
22225 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
22227 if (crtl->args.pretend_args_size)
22229 rtx x = GEN_INT (-crtl->args.pretend_args_size);
22231 if (cfun->machine->uses_anonymous_args)
22233 int num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size);
22234 unsigned long mask;
22236 mask = 1ul << (LAST_ARG_REGNUM + 1);
22237 mask -= 1ul << (LAST_ARG_REGNUM + 1 - num_pushes);
22239 insn = thumb1_emit_multi_reg_push (mask, 0);
22243 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
22244 stack_pointer_rtx, x));
22246 RTX_FRAME_RELATED_P (insn) = 1;
22249 if (TARGET_BACKTRACE)
22251 HOST_WIDE_INT offset = 0;
22252 unsigned work_register;
22253 rtx work_reg, x, arm_hfp_rtx;
22255 /* We have been asked to create a stack backtrace structure.
22256 The code looks like this:
22260 0 sub SP, #16 Reserve space for 4 registers.
22261 2 push {R7} Push low registers.
22262 4 add R7, SP, #20 Get the stack pointer before the push.
22263 6 str R7, [SP, #8] Store the stack pointer
22264 (before reserving the space).
22265 8 mov R7, PC Get hold of the start of this code + 12.
22266 10 str R7, [SP, #16] Store it.
22267 12 mov R7, FP Get hold of the current frame pointer.
22268 14 str R7, [SP, #4] Store it.
22269 16 mov R7, LR Get hold of the current return address.
22270 18 str R7, [SP, #12] Store it.
22271 20 add R7, SP, #16 Point at the start of the
22272 backtrace structure.
22273 22 mov FP, R7 Put this value into the frame pointer. */
22275 work_register = thumb_find_work_register (live_regs_mask);
22276 work_reg = gen_rtx_REG (SImode, work_register);
22277 arm_hfp_rtx = gen_rtx_REG (SImode, ARM_HARD_FRAME_POINTER_REGNUM);
22279 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
22280 stack_pointer_rtx, GEN_INT (-16)));
22281 RTX_FRAME_RELATED_P (insn) = 1;
22285 insn = thumb1_emit_multi_reg_push (l_mask, l_mask);
22286 RTX_FRAME_RELATED_P (insn) = 1;
22288 offset = bit_count (l_mask) * UNITS_PER_WORD;
22291 x = GEN_INT (offset + 16 + crtl->args.pretend_args_size);
22292 emit_insn (gen_addsi3 (work_reg, stack_pointer_rtx, x));
22294 x = plus_constant (stack_pointer_rtx, offset + 4);
22295 x = gen_frame_mem (SImode, x);
22296 emit_move_insn (x, work_reg);
22298 /* Make sure that the instruction fetching the PC is in the right place
22299 to calculate "start of backtrace creation code + 12". */
22300 /* ??? The stores using the common WORK_REG ought to be enough to
22301 prevent the scheduler from doing anything weird. Failing that
22302 we could always move all of the following into an UNSPEC_VOLATILE. */
22305 x = gen_rtx_REG (SImode, PC_REGNUM);
22306 emit_move_insn (work_reg, x);
22308 x = plus_constant (stack_pointer_rtx, offset + 12);
22309 x = gen_frame_mem (SImode, x);
22310 emit_move_insn (x, work_reg);
22312 emit_move_insn (work_reg, arm_hfp_rtx);
22314 x = plus_constant (stack_pointer_rtx, offset);
22315 x = gen_frame_mem (SImode, x);
22316 emit_move_insn (x, work_reg);
22320 emit_move_insn (work_reg, arm_hfp_rtx);
22322 x = plus_constant (stack_pointer_rtx, offset);
22323 x = gen_frame_mem (SImode, x);
22324 emit_move_insn (x, work_reg);
22326 x = gen_rtx_REG (SImode, PC_REGNUM);
22327 emit_move_insn (work_reg, x);
22329 x = plus_constant (stack_pointer_rtx, offset + 12);
22330 x = gen_frame_mem (SImode, x);
22331 emit_move_insn (x, work_reg);
22334 x = gen_rtx_REG (SImode, LR_REGNUM);
22335 emit_move_insn (work_reg, x);
22337 x = plus_constant (stack_pointer_rtx, offset + 8);
22338 x = gen_frame_mem (SImode, x);
22339 emit_move_insn (x, work_reg);
22341 x = GEN_INT (offset + 12);
22342 emit_insn (gen_addsi3 (work_reg, stack_pointer_rtx, x));
22344 emit_move_insn (arm_hfp_rtx, work_reg);
22346 /* Optimization: If we are not pushing any low registers but we are going
22347 to push some high registers then delay our first push. This will just
22348 be a push of LR and we can combine it with the push of the first high
22350 else if ((l_mask & 0xff) != 0
22351 || (high_regs_pushed == 0 && l_mask))
22353 unsigned long mask = l_mask;
22354 mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1;
22355 insn = thumb1_emit_multi_reg_push (mask, mask);
22356 RTX_FRAME_RELATED_P (insn) = 1;
22359 if (high_regs_pushed)
22361 unsigned pushable_regs;
22362 unsigned next_hi_reg;
22363 unsigned arg_regs_num = TARGET_AAPCS_BASED ? crtl->args.info.aapcs_ncrn
22364 : crtl->args.info.nregs;
22365 unsigned arg_regs_mask = (1 << arg_regs_num) - 1;
22367 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
22368 if (live_regs_mask & (1 << next_hi_reg))
22371 /* Here we need to mask out registers used for passing arguments
22372 even if they can be pushed. This is to avoid using them to stash the high
22373 registers. Such kind of stash may clobber the use of arguments. */
22374 pushable_regs = l_mask & (~arg_regs_mask) & 0xff;
22376 if (pushable_regs == 0)
22377 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
22379 while (high_regs_pushed > 0)
22381 unsigned long real_regs_mask = 0;
22383 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
22385 if (pushable_regs & (1 << regno))
22387 emit_move_insn (gen_rtx_REG (SImode, regno),
22388 gen_rtx_REG (SImode, next_hi_reg));
22390 high_regs_pushed --;
22391 real_regs_mask |= (1 << next_hi_reg);
22393 if (high_regs_pushed)
22395 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
22397 if (live_regs_mask & (1 << next_hi_reg))
22402 pushable_regs &= ~((1 << regno) - 1);
22408 /* If we had to find a work register and we have not yet
22409 saved the LR then add it to the list of regs to push. */
22410 if (l_mask == (1 << LR_REGNUM))
22412 pushable_regs |= l_mask;
22413 real_regs_mask |= l_mask;
22417 insn = thumb1_emit_multi_reg_push (pushable_regs, real_regs_mask);
22418 RTX_FRAME_RELATED_P (insn) = 1;
22422 /* Load the pic register before setting the frame pointer,
22423 so we can use r7 as a temporary work register. */
22424 if (flag_pic && arm_pic_register != INVALID_REGNUM)
22425 arm_load_pic_register (live_regs_mask);
22427 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
22428 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
22429 stack_pointer_rtx);
22431 if (flag_stack_usage_info)
22432 current_function_static_stack_size
22433 = offsets->outgoing_args - offsets->saved_args;
22435 amount = offsets->outgoing_args - offsets->saved_regs;
22436 amount -= 4 * thumb1_extra_regs_pushed (offsets, true);
22441 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
22442 GEN_INT (- amount)));
22443 RTX_FRAME_RELATED_P (insn) = 1;
22449 /* The stack decrement is too big for an immediate value in a single
22450 insn. In theory we could issue multiple subtracts, but after
22451 three of them it becomes more space efficient to place the full
22452 value in the constant pool and load into a register. (Also the
22453 ARM debugger really likes to see only one stack decrement per
22454 function). So instead we look for a scratch register into which
22455 we can load the decrement, and then we subtract this from the
22456 stack pointer. Unfortunately on the thumb the only available
22457 scratch registers are the argument registers, and we cannot use
22458 these as they may hold arguments to the function. Instead we
22459 attempt to locate a call preserved register which is used by this
22460 function. If we can find one, then we know that it will have
22461 been pushed at the start of the prologue and so we can corrupt
22463 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
22464 if (live_regs_mask & (1 << regno))
22467 gcc_assert(regno <= LAST_LO_REGNUM);
22469 reg = gen_rtx_REG (SImode, regno);
22471 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
22473 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
22474 stack_pointer_rtx, reg));
22476 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
22477 plus_constant (stack_pointer_rtx,
22479 add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
22480 RTX_FRAME_RELATED_P (insn) = 1;
22484 if (frame_pointer_needed)
22485 thumb_set_frame_pointer (offsets);
22487 /* If we are profiling, make sure no instructions are scheduled before
22488 the call to mcount. Similarly if the user has requested no
22489 scheduling in the prolog. Similarly if we want non-call exceptions
22490 using the EABI unwinder, to prevent faulting instructions from being
22491 swapped with a stack adjustment. */
22492 if (crtl->profile || !TARGET_SCHED_PROLOG
22493 || (arm_except_unwind_info (&global_options) == UI_TARGET
22494 && cfun->can_throw_non_call_exceptions))
22495 emit_insn (gen_blockage ());
22497 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
22498 if (live_regs_mask & 0xff)
22499 cfun->machine->lr_save_eliminated = 0;
22504 thumb1_expand_epilogue (void)
22506 HOST_WIDE_INT amount;
22507 arm_stack_offsets *offsets;
22510 /* Naked functions don't have prologues. */
22511 if (IS_NAKED (arm_current_func_type ()))
22514 offsets = arm_get_frame_offsets ();
22515 amount = offsets->outgoing_args - offsets->saved_regs;
22517 if (frame_pointer_needed)
22519 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
22520 amount = offsets->locals_base - offsets->saved_regs;
22522 amount -= 4 * thumb1_extra_regs_pushed (offsets, false);
22524 gcc_assert (amount >= 0);
22527 emit_insn (gen_blockage ());
22530 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
22531 GEN_INT (amount)));
22534 /* r3 is always free in the epilogue. */
22535 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
22537 emit_insn (gen_movsi (reg, GEN_INT (amount)));
22538 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
22542 /* Emit a USE (stack_pointer_rtx), so that
22543 the stack adjustment will not be deleted. */
22544 emit_insn (gen_prologue_use (stack_pointer_rtx));
22546 if (crtl->profile || !TARGET_SCHED_PROLOG)
22547 emit_insn (gen_blockage ());
22549 /* Emit a clobber for each insn that will be restored in the epilogue,
22550 so that flow2 will get register lifetimes correct. */
22551 for (regno = 0; regno < 13; regno++)
22552 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
22553 emit_clobber (gen_rtx_REG (SImode, regno));
22555 if (! df_regs_ever_live_p (LR_REGNUM))
22556 emit_use (gen_rtx_REG (SImode, LR_REGNUM));
22559 /* Implementation of insn prologue_thumb1_interwork. This is the first
22560 "instruction" of a function called in ARM mode. Swap to thumb mode. */
22563 thumb1_output_interwork (void)
22566 FILE *f = asm_out_file;
22568 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
22569 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
22571 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
22573 /* Generate code sequence to switch us into Thumb mode. */
22574 /* The .code 32 directive has already been emitted by
22575 ASM_DECLARE_FUNCTION_NAME. */
22576 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
22577 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
22579 /* Generate a label, so that the debugger will notice the
22580 change in instruction sets. This label is also used by
22581 the assembler to bypass the ARM code when this function
22582 is called from a Thumb encoded function elsewhere in the
22583 same file. Hence the definition of STUB_NAME here must
22584 agree with the definition in gas/config/tc-arm.c. */
22586 #define STUB_NAME ".real_start_of"
22588 fprintf (f, "\t.code\t16\n");
22590 if (arm_dllexport_name_p (name))
22591 name = arm_strip_name_encoding (name);
22593 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
22594 fprintf (f, "\t.thumb_func\n");
22595 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
22600 /* Handle the case of a double word load into a low register from
22601 a computed memory address. The computed address may involve a
22602 register which is overwritten by the load. */
22604 thumb_load_double_from_address (rtx *operands)
22612 gcc_assert (GET_CODE (operands[0]) == REG);
22613 gcc_assert (GET_CODE (operands[1]) == MEM);
22615 /* Get the memory address. */
22616 addr = XEXP (operands[1], 0);
22618 /* Work out how the memory address is computed. */
22619 switch (GET_CODE (addr))
22622 operands[2] = adjust_address (operands[1], SImode, 4);
22624 if (REGNO (operands[0]) == REGNO (addr))
22626 output_asm_insn ("ldr\t%H0, %2", operands);
22627 output_asm_insn ("ldr\t%0, %1", operands);
22631 output_asm_insn ("ldr\t%0, %1", operands);
22632 output_asm_insn ("ldr\t%H0, %2", operands);
22637 /* Compute <address> + 4 for the high order load. */
22638 operands[2] = adjust_address (operands[1], SImode, 4);
22640 output_asm_insn ("ldr\t%0, %1", operands);
22641 output_asm_insn ("ldr\t%H0, %2", operands);
22645 arg1 = XEXP (addr, 0);
22646 arg2 = XEXP (addr, 1);
22648 if (CONSTANT_P (arg1))
22649 base = arg2, offset = arg1;
22651 base = arg1, offset = arg2;
22653 gcc_assert (GET_CODE (base) == REG);
22655 /* Catch the case of <address> = <reg> + <reg> */
22656 if (GET_CODE (offset) == REG)
22658 int reg_offset = REGNO (offset);
22659 int reg_base = REGNO (base);
22660 int reg_dest = REGNO (operands[0]);
22662 /* Add the base and offset registers together into the
22663 higher destination register. */
22664 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
22665 reg_dest + 1, reg_base, reg_offset);
22667 /* Load the lower destination register from the address in
22668 the higher destination register. */
22669 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
22670 reg_dest, reg_dest + 1);
22672 /* Load the higher destination register from its own address
22674 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
22675 reg_dest + 1, reg_dest + 1);
22679 /* Compute <address> + 4 for the high order load. */
22680 operands[2] = adjust_address (operands[1], SImode, 4);
22682 /* If the computed address is held in the low order register
22683 then load the high order register first, otherwise always
22684 load the low order register first. */
22685 if (REGNO (operands[0]) == REGNO (base))
22687 output_asm_insn ("ldr\t%H0, %2", operands);
22688 output_asm_insn ("ldr\t%0, %1", operands);
22692 output_asm_insn ("ldr\t%0, %1", operands);
22693 output_asm_insn ("ldr\t%H0, %2", operands);
22699 /* With no registers to worry about we can just load the value
22701 operands[2] = adjust_address (operands[1], SImode, 4);
22703 output_asm_insn ("ldr\t%H0, %2", operands);
22704 output_asm_insn ("ldr\t%0, %1", operands);
22708 gcc_unreachable ();
22715 thumb_output_move_mem_multiple (int n, rtx *operands)
22722 if (REGNO (operands[4]) > REGNO (operands[5]))
22725 operands[4] = operands[5];
22728 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
22729 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
22733 if (REGNO (operands[4]) > REGNO (operands[5]))
22736 operands[4] = operands[5];
22739 if (REGNO (operands[5]) > REGNO (operands[6]))
22742 operands[5] = operands[6];
22745 if (REGNO (operands[4]) > REGNO (operands[5]))
22748 operands[4] = operands[5];
22752 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
22753 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
22757 gcc_unreachable ();
22763 /* Output a call-via instruction for thumb state. */
22765 thumb_call_via_reg (rtx reg)
22767 int regno = REGNO (reg);
22770 gcc_assert (regno < LR_REGNUM);
22772 /* If we are in the normal text section we can use a single instance
22773 per compilation unit. If we are doing function sections, then we need
22774 an entry per section, since we can't rely on reachability. */
22775 if (in_section == text_section)
22777 thumb_call_reg_needed = 1;
22779 if (thumb_call_via_label[regno] == NULL)
22780 thumb_call_via_label[regno] = gen_label_rtx ();
22781 labelp = thumb_call_via_label + regno;
22785 if (cfun->machine->call_via[regno] == NULL)
22786 cfun->machine->call_via[regno] = gen_label_rtx ();
22787 labelp = cfun->machine->call_via + regno;
22790 output_asm_insn ("bl\t%a0", labelp);
22794 /* Routines for generating rtl. */
22796 thumb_expand_movmemqi (rtx *operands)
22798 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
22799 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
22800 HOST_WIDE_INT len = INTVAL (operands[2]);
22801 HOST_WIDE_INT offset = 0;
22805 emit_insn (gen_movmem12b (out, in, out, in));
22811 emit_insn (gen_movmem8b (out, in, out, in));
22817 rtx reg = gen_reg_rtx (SImode);
22818 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
22819 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
22826 rtx reg = gen_reg_rtx (HImode);
22827 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
22828 plus_constant (in, offset))));
22829 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
22837 rtx reg = gen_reg_rtx (QImode);
22838 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
22839 plus_constant (in, offset))));
22840 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
22846 thumb_reload_out_hi (rtx *operands)
22848 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
22851 /* Handle reading a half-word from memory during reload. */
22853 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
22855 gcc_unreachable ();
22858 /* Return the length of a function name prefix
22859 that starts with the character 'c'. */
22861 arm_get_strip_length (int c)
22865 ARM_NAME_ENCODING_LENGTHS
22870 /* Return a pointer to a function's name with any
22871 and all prefix encodings stripped from it. */
22873 arm_strip_name_encoding (const char *name)
22877 while ((skip = arm_get_strip_length (* name)))
22883 /* If there is a '*' anywhere in the name's prefix, then
22884 emit the stripped name verbatim, otherwise prepend an
22885 underscore if leading underscores are being used. */
22887 arm_asm_output_labelref (FILE *stream, const char *name)
22892 while ((skip = arm_get_strip_length (* name)))
22894 verbatim |= (*name == '*');
22899 fputs (name, stream);
22901 asm_fprintf (stream, "%U%s", name);
22905 arm_file_start (void)
22909 if (TARGET_UNIFIED_ASM)
22910 asm_fprintf (asm_out_file, "\t.syntax unified\n");
22914 const char *fpu_name;
22915 if (arm_selected_arch)
22916 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name);
22917 else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
22918 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8);
22920 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name);
22922 if (TARGET_SOFT_FLOAT)
22925 fpu_name = "softvfp";
22927 fpu_name = "softfpa";
22931 fpu_name = arm_fpu_desc->name;
22932 if (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
22934 if (TARGET_HARD_FLOAT)
22935 EMIT_EABI_ATTRIBUTE (Tag_ABI_HardFP_use, 27, 3);
22936 if (TARGET_HARD_FLOAT_ABI)
22937 EMIT_EABI_ATTRIBUTE (Tag_ABI_VFP_args, 28, 1);
22940 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
22942 /* Some of these attributes only apply when the corresponding features
22943 are used. However we don't have any easy way of figuring this out.
22944 Conservatively record the setting that would have been used. */
22946 if (flag_rounding_math)
22947 EMIT_EABI_ATTRIBUTE (Tag_ABI_FP_rounding, 19, 1);
22949 if (!flag_unsafe_math_optimizations)
22951 EMIT_EABI_ATTRIBUTE (Tag_ABI_FP_denormal, 20, 1);
22952 EMIT_EABI_ATTRIBUTE (Tag_ABI_FP_exceptions, 21, 1);
22954 if (flag_signaling_nans)
22955 EMIT_EABI_ATTRIBUTE (Tag_ABI_FP_user_exceptions, 22, 1);
22957 EMIT_EABI_ATTRIBUTE (Tag_ABI_FP_number_model, 23,
22958 flag_finite_math_only ? 1 : 3);
22960 EMIT_EABI_ATTRIBUTE (Tag_ABI_align8_needed, 24, 1);
22961 EMIT_EABI_ATTRIBUTE (Tag_ABI_align8_preserved, 25, 1);
22962 EMIT_EABI_ATTRIBUTE (Tag_ABI_enum_size, 26, flag_short_enums ? 1 : 2);
22964 /* Tag_ABI_optimization_goals. */
22967 else if (optimize >= 2)
22973 EMIT_EABI_ATTRIBUTE (Tag_ABI_optimization_goals, 30, val);
22975 EMIT_EABI_ATTRIBUTE (Tag_CPU_unaligned_access, 34, unaligned_access);
22977 if (arm_fp16_format)
22978 EMIT_EABI_ATTRIBUTE (Tag_ABI_FP_16bit_format, 38, (int) arm_fp16_format);
22980 if (arm_lang_output_object_attributes_hook)
22981 arm_lang_output_object_attributes_hook();
22984 default_file_start ();
22988 arm_file_end (void)
22992 if (NEED_INDICATE_EXEC_STACK)
22993 /* Add .note.GNU-stack. */
22994 file_end_indicate_exec_stack ();
22996 if (! thumb_call_reg_needed)
22999 switch_to_section (text_section);
23000 asm_fprintf (asm_out_file, "\t.code 16\n");
23001 ASM_OUTPUT_ALIGN (asm_out_file, 1);
23003 for (regno = 0; regno < LR_REGNUM; regno++)
23005 rtx label = thumb_call_via_label[regno];
23009 targetm.asm_out.internal_label (asm_out_file, "L",
23010 CODE_LABEL_NUMBER (label));
23011 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
23017 /* Symbols in the text segment can be accessed without indirecting via the
23018 constant pool; it may take an extra binary operation, but this is still
23019 faster than indirecting via memory. Don't do this when not optimizing,
23020 since we won't be calculating al of the offsets necessary to do this
23024 arm_encode_section_info (tree decl, rtx rtl, int first)
23026 if (optimize > 0 && TREE_CONSTANT (decl))
23027 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
23029 default_encode_section_info (decl, rtl, first);
23031 #endif /* !ARM_PE */
23034 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
23036 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
23037 && !strcmp (prefix, "L"))
23039 arm_ccfsm_state = 0;
23040 arm_target_insn = NULL;
23042 default_internal_label (stream, prefix, labelno);
23045 /* Output code to add DELTA to the first argument, and then jump
23046 to FUNCTION. Used for C++ multiple inheritance. */
23048 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
23049 HOST_WIDE_INT delta,
23050 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
23053 static int thunk_label = 0;
23056 int mi_delta = delta;
23057 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
23059 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
23062 mi_delta = - mi_delta;
23066 int labelno = thunk_label++;
23067 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
23068 /* Thunks are entered in arm mode when avaiable. */
23069 if (TARGET_THUMB1_ONLY)
23071 /* push r3 so we can use it as a temporary. */
23072 /* TODO: Omit this save if r3 is not used. */
23073 fputs ("\tpush {r3}\n", file);
23074 fputs ("\tldr\tr3, ", file);
23078 fputs ("\tldr\tr12, ", file);
23080 assemble_name (file, label);
23081 fputc ('\n', file);
23084 /* If we are generating PIC, the ldr instruction below loads
23085 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
23086 the address of the add + 8, so we have:
23088 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
23091 Note that we have "+ 1" because some versions of GNU ld
23092 don't set the low bit of the result for R_ARM_REL32
23093 relocations against thumb function symbols.
23094 On ARMv6M this is +4, not +8. */
23095 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
23096 assemble_name (file, labelpc);
23097 fputs (":\n", file);
23098 if (TARGET_THUMB1_ONLY)
23100 /* This is 2 insns after the start of the thunk, so we know it
23101 is 4-byte aligned. */
23102 fputs ("\tadd\tr3, pc, r3\n", file);
23103 fputs ("\tmov r12, r3\n", file);
23106 fputs ("\tadd\tr12, pc, r12\n", file);
23108 else if (TARGET_THUMB1_ONLY)
23109 fputs ("\tmov r12, r3\n", file);
23111 if (TARGET_THUMB1_ONLY)
23113 if (mi_delta > 255)
23115 fputs ("\tldr\tr3, ", file);
23116 assemble_name (file, label);
23117 fputs ("+4\n", file);
23118 asm_fprintf (file, "\t%s\t%r, %r, r3\n",
23119 mi_op, this_regno, this_regno);
23121 else if (mi_delta != 0)
23123 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
23124 mi_op, this_regno, this_regno,
23130 /* TODO: Use movw/movt for large constants when available. */
23131 while (mi_delta != 0)
23133 if ((mi_delta & (3 << shift)) == 0)
23137 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
23138 mi_op, this_regno, this_regno,
23139 mi_delta & (0xff << shift));
23140 mi_delta &= ~(0xff << shift);
23147 if (TARGET_THUMB1_ONLY)
23148 fputs ("\tpop\t{r3}\n", file);
23150 fprintf (file, "\tbx\tr12\n");
23151 ASM_OUTPUT_ALIGN (file, 2);
23152 assemble_name (file, label);
23153 fputs (":\n", file);
23156 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
23157 rtx tem = XEXP (DECL_RTL (function), 0);
23158 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
23159 tem = gen_rtx_MINUS (GET_MODE (tem),
23161 gen_rtx_SYMBOL_REF (Pmode,
23162 ggc_strdup (labelpc)));
23163 assemble_integer (tem, 4, BITS_PER_WORD, 1);
23166 /* Output ".word .LTHUNKn". */
23167 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
23169 if (TARGET_THUMB1_ONLY && mi_delta > 255)
23170 assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1);
23174 fputs ("\tb\t", file);
23175 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
23176 if (NEED_PLT_RELOC)
23177 fputs ("(PLT)", file);
23178 fputc ('\n', file);
23183 arm_emit_vector_const (FILE *file, rtx x)
23186 const char * pattern;
23188 gcc_assert (GET_CODE (x) == CONST_VECTOR);
23190 switch (GET_MODE (x))
23192 case V2SImode: pattern = "%08x"; break;
23193 case V4HImode: pattern = "%04x"; break;
23194 case V8QImode: pattern = "%02x"; break;
23195 default: gcc_unreachable ();
23198 fprintf (file, "0x");
23199 for (i = CONST_VECTOR_NUNITS (x); i--;)
23203 element = CONST_VECTOR_ELT (x, i);
23204 fprintf (file, pattern, INTVAL (element));
23210 /* Emit a fp16 constant appropriately padded to occupy a 4-byte word.
23211 HFmode constant pool entries are actually loaded with ldr. */
23213 arm_emit_fp16_const (rtx c)
23218 REAL_VALUE_FROM_CONST_DOUBLE (r, c);
23219 bits = real_to_target (NULL, &r, HFmode);
23220 if (WORDS_BIG_ENDIAN)
23221 assemble_zeros (2);
23222 assemble_integer (GEN_INT (bits), 2, BITS_PER_WORD, 1);
23223 if (!WORDS_BIG_ENDIAN)
23224 assemble_zeros (2);
23228 arm_output_load_gr (rtx *operands)
23235 if (GET_CODE (operands [1]) != MEM
23236 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
23237 || GET_CODE (reg = XEXP (sum, 0)) != REG
23238 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
23239 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
23240 return "wldrw%?\t%0, %1";
23242 /* Fix up an out-of-range load of a GR register. */
23243 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
23244 wcgr = operands[0];
23246 output_asm_insn ("ldr%?\t%0, %1", operands);
23248 operands[0] = wcgr;
23250 output_asm_insn ("tmcr%?\t%0, %1", operands);
23251 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
23256 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
23258 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
23259 named arg and all anonymous args onto the stack.
23260 XXX I know the prologue shouldn't be pushing registers, but it is faster
23264 arm_setup_incoming_varargs (cumulative_args_t pcum_v,
23265 enum machine_mode mode,
23268 int second_time ATTRIBUTE_UNUSED)
23270 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
23273 cfun->machine->uses_anonymous_args = 1;
23274 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
23276 nregs = pcum->aapcs_ncrn;
23277 if ((nregs & 1) && arm_needs_doubleword_align (mode, type))
23281 nregs = pcum->nregs;
23283 if (nregs < NUM_ARG_REGS)
23284 *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
23287 /* Return nonzero if the CONSUMER instruction (a store) does not need
23288 PRODUCER's value to calculate the address. */
23291 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
23293 rtx value = PATTERN (producer);
23294 rtx addr = PATTERN (consumer);
23296 if (GET_CODE (value) == COND_EXEC)
23297 value = COND_EXEC_CODE (value);
23298 if (GET_CODE (value) == PARALLEL)
23299 value = XVECEXP (value, 0, 0);
23300 value = XEXP (value, 0);
23301 if (GET_CODE (addr) == COND_EXEC)
23302 addr = COND_EXEC_CODE (addr);
23303 if (GET_CODE (addr) == PARALLEL)
23304 addr = XVECEXP (addr, 0, 0);
23305 addr = XEXP (addr, 0);
23307 return !reg_overlap_mentioned_p (value, addr);
23310 /* Return nonzero if the CONSUMER instruction (a store) does need
23311 PRODUCER's value to calculate the address. */
23314 arm_early_store_addr_dep (rtx producer, rtx consumer)
23316 return !arm_no_early_store_addr_dep (producer, consumer);
23319 /* Return nonzero if the CONSUMER instruction (a load) does need
23320 PRODUCER's value to calculate the address. */
23323 arm_early_load_addr_dep (rtx producer, rtx consumer)
23325 rtx value = PATTERN (producer);
23326 rtx addr = PATTERN (consumer);
23328 if (GET_CODE (value) == COND_EXEC)
23329 value = COND_EXEC_CODE (value);
23330 if (GET_CODE (value) == PARALLEL)
23331 value = XVECEXP (value, 0, 0);
23332 value = XEXP (value, 0);
23333 if (GET_CODE (addr) == COND_EXEC)
23334 addr = COND_EXEC_CODE (addr);
23335 if (GET_CODE (addr) == PARALLEL)
23336 addr = XVECEXP (addr, 0, 0);
23337 addr = XEXP (addr, 1);
23339 return reg_overlap_mentioned_p (value, addr);
23342 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
23343 have an early register shift value or amount dependency on the
23344 result of PRODUCER. */
23347 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
23349 rtx value = PATTERN (producer);
23350 rtx op = PATTERN (consumer);
23353 if (GET_CODE (value) == COND_EXEC)
23354 value = COND_EXEC_CODE (value);
23355 if (GET_CODE (value) == PARALLEL)
23356 value = XVECEXP (value, 0, 0);
23357 value = XEXP (value, 0);
23358 if (GET_CODE (op) == COND_EXEC)
23359 op = COND_EXEC_CODE (op);
23360 if (GET_CODE (op) == PARALLEL)
23361 op = XVECEXP (op, 0, 0);
23364 early_op = XEXP (op, 0);
23365 /* This is either an actual independent shift, or a shift applied to
23366 the first operand of another operation. We want the whole shift
23368 if (GET_CODE (early_op) == REG)
23371 return !reg_overlap_mentioned_p (value, early_op);
23374 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
23375 have an early register shift value dependency on the result of
23379 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
23381 rtx value = PATTERN (producer);
23382 rtx op = PATTERN (consumer);
23385 if (GET_CODE (value) == COND_EXEC)
23386 value = COND_EXEC_CODE (value);
23387 if (GET_CODE (value) == PARALLEL)
23388 value = XVECEXP (value, 0, 0);
23389 value = XEXP (value, 0);
23390 if (GET_CODE (op) == COND_EXEC)
23391 op = COND_EXEC_CODE (op);
23392 if (GET_CODE (op) == PARALLEL)
23393 op = XVECEXP (op, 0, 0);
23396 early_op = XEXP (op, 0);
23398 /* This is either an actual independent shift, or a shift applied to
23399 the first operand of another operation. We want the value being
23400 shifted, in either case. */
23401 if (GET_CODE (early_op) != REG)
23402 early_op = XEXP (early_op, 0);
23404 return !reg_overlap_mentioned_p (value, early_op);
23407 /* Return nonzero if the CONSUMER (a mul or mac op) does not
23408 have an early register mult dependency on the result of
23412 arm_no_early_mul_dep (rtx producer, rtx consumer)
23414 rtx value = PATTERN (producer);
23415 rtx op = PATTERN (consumer);
23417 if (GET_CODE (value) == COND_EXEC)
23418 value = COND_EXEC_CODE (value);
23419 if (GET_CODE (value) == PARALLEL)
23420 value = XVECEXP (value, 0, 0);
23421 value = XEXP (value, 0);
23422 if (GET_CODE (op) == COND_EXEC)
23423 op = COND_EXEC_CODE (op);
23424 if (GET_CODE (op) == PARALLEL)
23425 op = XVECEXP (op, 0, 0);
23428 if (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
23430 if (GET_CODE (XEXP (op, 0)) == MULT)
23431 return !reg_overlap_mentioned_p (value, XEXP (op, 0));
23433 return !reg_overlap_mentioned_p (value, XEXP (op, 1));
23439 /* We can't rely on the caller doing the proper promotion when
23440 using APCS or ATPCS. */
23443 arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED)
23445 return !TARGET_AAPCS_BASED;
23448 static enum machine_mode
23449 arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
23450 enum machine_mode mode,
23451 int *punsignedp ATTRIBUTE_UNUSED,
23452 const_tree fntype ATTRIBUTE_UNUSED,
23453 int for_return ATTRIBUTE_UNUSED)
23455 if (GET_MODE_CLASS (mode) == MODE_INT
23456 && GET_MODE_SIZE (mode) < 4)
23462 /* AAPCS based ABIs use short enums by default. */
23465 arm_default_short_enums (void)
23467 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
23471 /* AAPCS requires that anonymous bitfields affect structure alignment. */
23474 arm_align_anon_bitfield (void)
23476 return TARGET_AAPCS_BASED;
23480 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
23483 arm_cxx_guard_type (void)
23485 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
23488 /* Return non-zero if the consumer (a multiply-accumulate instruction)
23489 has an accumulator dependency on the result of the producer (a
23490 multiplication instruction) and no other dependency on that result. */
23492 arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer)
23494 rtx mul = PATTERN (producer);
23495 rtx mac = PATTERN (consumer);
23497 rtx mac_op0, mac_op1, mac_acc;
23499 if (GET_CODE (mul) == COND_EXEC)
23500 mul = COND_EXEC_CODE (mul);
23501 if (GET_CODE (mac) == COND_EXEC)
23502 mac = COND_EXEC_CODE (mac);
23504 /* Check that mul is of the form (set (...) (mult ...))
23505 and mla is of the form (set (...) (plus (mult ...) (...))). */
23506 if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT)
23507 || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS
23508 || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT))
23511 mul_result = XEXP (mul, 0);
23512 mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0);
23513 mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1);
23514 mac_acc = XEXP (XEXP (mac, 1), 1);
23516 return (reg_overlap_mentioned_p (mul_result, mac_acc)
23517 && !reg_overlap_mentioned_p (mul_result, mac_op0)
23518 && !reg_overlap_mentioned_p (mul_result, mac_op1));
23522 /* The EABI says test the least significant bit of a guard variable. */
23525 arm_cxx_guard_mask_bit (void)
23527 return TARGET_AAPCS_BASED;
23531 /* The EABI specifies that all array cookies are 8 bytes long. */
23534 arm_get_cookie_size (tree type)
23538 if (!TARGET_AAPCS_BASED)
23539 return default_cxx_get_cookie_size (type);
23541 size = build_int_cst (sizetype, 8);
23546 /* The EABI says that array cookies should also contain the element size. */
23549 arm_cookie_has_size (void)
23551 return TARGET_AAPCS_BASED;
23555 /* The EABI says constructors and destructors should return a pointer to
23556 the object constructed/destroyed. */
23559 arm_cxx_cdtor_returns_this (void)
23561 return TARGET_AAPCS_BASED;
23564 /* The EABI says that an inline function may never be the key
23568 arm_cxx_key_method_may_be_inline (void)
23570 return !TARGET_AAPCS_BASED;
23574 arm_cxx_determine_class_data_visibility (tree decl)
23576 if (!TARGET_AAPCS_BASED
23577 || !TARGET_DLLIMPORT_DECL_ATTRIBUTES)
23580 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
23581 is exported. However, on systems without dynamic vague linkage,
23582 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
23583 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
23584 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
23586 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
23587 DECL_VISIBILITY_SPECIFIED (decl) = 1;
23591 arm_cxx_class_data_always_comdat (void)
23593 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
23594 vague linkage if the class has no key function. */
23595 return !TARGET_AAPCS_BASED;
23599 /* The EABI says __aeabi_atexit should be used to register static
23603 arm_cxx_use_aeabi_atexit (void)
23605 return TARGET_AAPCS_BASED;
23610 arm_set_return_address (rtx source, rtx scratch)
23612 arm_stack_offsets *offsets;
23613 HOST_WIDE_INT delta;
23615 unsigned long saved_regs;
23617 offsets = arm_get_frame_offsets ();
23618 saved_regs = offsets->saved_regs_mask;
23620 if ((saved_regs & (1 << LR_REGNUM)) == 0)
23621 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
23624 if (frame_pointer_needed)
23625 addr = plus_constant(hard_frame_pointer_rtx, -4);
23628 /* LR will be the first saved register. */
23629 delta = offsets->outgoing_args - (offsets->frame + 4);
23634 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
23635 GEN_INT (delta & ~4095)));
23640 addr = stack_pointer_rtx;
23642 addr = plus_constant (addr, delta);
23644 emit_move_insn (gen_frame_mem (Pmode, addr), source);
23650 thumb_set_return_address (rtx source, rtx scratch)
23652 arm_stack_offsets *offsets;
23653 HOST_WIDE_INT delta;
23654 HOST_WIDE_INT limit;
23657 unsigned long mask;
23661 offsets = arm_get_frame_offsets ();
23662 mask = offsets->saved_regs_mask;
23663 if (mask & (1 << LR_REGNUM))
23666 /* Find the saved regs. */
23667 if (frame_pointer_needed)
23669 delta = offsets->soft_frame - offsets->saved_args;
23670 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
23676 delta = offsets->outgoing_args - offsets->saved_args;
23679 /* Allow for the stack frame. */
23680 if (TARGET_THUMB1 && TARGET_BACKTRACE)
23682 /* The link register is always the first saved register. */
23685 /* Construct the address. */
23686 addr = gen_rtx_REG (SImode, reg);
23689 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
23690 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
23694 addr = plus_constant (addr, delta);
23696 emit_move_insn (gen_frame_mem (Pmode, addr), source);
23699 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
23702 /* Implements target hook vector_mode_supported_p. */
23704 arm_vector_mode_supported_p (enum machine_mode mode)
23706 /* Neon also supports V2SImode, etc. listed in the clause below. */
23707 if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode
23708 || mode == V16QImode || mode == V4SFmode || mode == V2DImode))
23711 if ((TARGET_NEON || TARGET_IWMMXT)
23712 && ((mode == V2SImode)
23713 || (mode == V4HImode)
23714 || (mode == V8QImode)))
23717 if (TARGET_INT_SIMD && (mode == V4UQQmode || mode == V4QQmode
23718 || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode
23719 || mode == V2HAmode))
23725 /* Implements target hook array_mode_supported_p. */
23728 arm_array_mode_supported_p (enum machine_mode mode,
23729 unsigned HOST_WIDE_INT nelems)
23732 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
23733 && (nelems >= 2 && nelems <= 4))
23739 /* Use the option -mvectorize-with-neon-double to override the use of quardword
23740 registers when autovectorizing for Neon, at least until multiple vector
23741 widths are supported properly by the middle-end. */
23743 static enum machine_mode
23744 arm_preferred_simd_mode (enum machine_mode mode)
23750 return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode;
23752 return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode;
23754 return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode;
23756 return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode;
23758 if (!TARGET_NEON_VECTORIZE_DOUBLE)
23765 if (TARGET_REALLY_IWMMXT)
23781 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
23783 We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
23784 using r0-r4 for function arguments, r7 for the stack frame and don't have
23785 enough left over to do doubleword arithmetic. For Thumb-2 all the
23786 potentially problematic instructions accept high registers so this is not
23787 necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
23788 that require many low registers. */
23790 arm_class_likely_spilled_p (reg_class_t rclass)
23792 if ((TARGET_THUMB1 && rclass == LO_REGS)
23793 || rclass == CC_REG)
23799 /* Implements target hook small_register_classes_for_mode_p. */
23801 arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
23803 return TARGET_THUMB1;
23806 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
23807 ARM insns and therefore guarantee that the shift count is modulo 256.
23808 DImode shifts (those implemented by lib1funcs.S or by optabs.c)
23809 guarantee no particular behavior for out-of-range counts. */
23811 static unsigned HOST_WIDE_INT
23812 arm_shift_truncation_mask (enum machine_mode mode)
23814 return mode == SImode ? 255 : 0;
23818 /* Map internal gcc register numbers to DWARF2 register numbers. */
23821 arm_dbx_register_number (unsigned int regno)
23826 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
23827 compatibility. The EABI defines them as registers 96-103. */
23828 if (IS_FPA_REGNUM (regno))
23829 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
23831 if (IS_VFP_REGNUM (regno))
23833 /* See comment in arm_dwarf_register_span. */
23834 if (VFP_REGNO_OK_FOR_SINGLE (regno))
23835 return 64 + regno - FIRST_VFP_REGNUM;
23837 return 256 + (regno - FIRST_VFP_REGNUM) / 2;
23840 if (IS_IWMMXT_GR_REGNUM (regno))
23841 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
23843 if (IS_IWMMXT_REGNUM (regno))
23844 return 112 + regno - FIRST_IWMMXT_REGNUM;
23846 gcc_unreachable ();
23849 /* Dwarf models VFPv3 registers as 32 64-bit registers.
23850 GCC models tham as 64 32-bit registers, so we need to describe this to
23851 the DWARF generation code. Other registers can use the default. */
23853 arm_dwarf_register_span (rtx rtl)
23860 regno = REGNO (rtl);
23861 if (!IS_VFP_REGNUM (regno))
23864 /* XXX FIXME: The EABI defines two VFP register ranges:
23865 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
23867 The recommended encoding for S0-S31 is a DW_OP_bit_piece of the
23868 corresponding D register. Until GDB supports this, we shall use the
23869 legacy encodings. We also use these encodings for D0-D15 for
23870 compatibility with older debuggers. */
23871 if (VFP_REGNO_OK_FOR_SINGLE (regno))
23874 nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8;
23875 p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
23876 regno = (regno - FIRST_VFP_REGNUM) / 2;
23877 for (i = 0; i < nregs; i++)
23878 XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i);
23883 #if ARM_UNWIND_INFO
23884 /* Emit unwind directives for a store-multiple instruction or stack pointer
23885 push during alignment.
23886 These should only ever be generated by the function prologue code, so
23887 expect them to have a particular form. */
23890 arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
23893 HOST_WIDE_INT offset;
23894 HOST_WIDE_INT nregs;
23900 e = XVECEXP (p, 0, 0);
23901 if (GET_CODE (e) != SET)
23904 /* First insn will adjust the stack pointer. */
23905 if (GET_CODE (e) != SET
23906 || GET_CODE (XEXP (e, 0)) != REG
23907 || REGNO (XEXP (e, 0)) != SP_REGNUM
23908 || GET_CODE (XEXP (e, 1)) != PLUS)
23911 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
23912 nregs = XVECLEN (p, 0) - 1;
23914 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
23917 /* The function prologue may also push pc, but not annotate it as it is
23918 never restored. We turn this into a stack pointer adjustment. */
23919 if (nregs * 4 == offset - 4)
23921 fprintf (asm_out_file, "\t.pad #4\n");
23925 fprintf (asm_out_file, "\t.save {");
23927 else if (IS_VFP_REGNUM (reg))
23930 fprintf (asm_out_file, "\t.vsave {");
23932 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
23934 /* FPA registers are done differently. */
23935 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
23939 /* Unknown register type. */
23942 /* If the stack increment doesn't match the size of the saved registers,
23943 something has gone horribly wrong. */
23944 if (offset != nregs * reg_size)
23949 /* The remaining insns will describe the stores. */
23950 for (i = 1; i <= nregs; i++)
23952 /* Expect (set (mem <addr>) (reg)).
23953 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
23954 e = XVECEXP (p, 0, i);
23955 if (GET_CODE (e) != SET
23956 || GET_CODE (XEXP (e, 0)) != MEM
23957 || GET_CODE (XEXP (e, 1)) != REG)
23960 reg = REGNO (XEXP (e, 1));
23965 fprintf (asm_out_file, ", ");
23966 /* We can't use %r for vfp because we need to use the
23967 double precision register names. */
23968 if (IS_VFP_REGNUM (reg))
23969 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
23971 asm_fprintf (asm_out_file, "%r", reg);
23973 #ifdef ENABLE_CHECKING
23974 /* Check that the addresses are consecutive. */
23975 e = XEXP (XEXP (e, 0), 0);
23976 if (GET_CODE (e) == PLUS)
23978 offset += reg_size;
23979 if (GET_CODE (XEXP (e, 0)) != REG
23980 || REGNO (XEXP (e, 0)) != SP_REGNUM
23981 || GET_CODE (XEXP (e, 1)) != CONST_INT
23982 || offset != INTVAL (XEXP (e, 1)))
23986 || GET_CODE (e) != REG
23987 || REGNO (e) != SP_REGNUM)
23991 fprintf (asm_out_file, "}\n");
23994 /* Emit unwind directives for a SET. */
23997 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
24005 switch (GET_CODE (e0))
24008 /* Pushing a single register. */
24009 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
24010 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
24011 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
24014 asm_fprintf (asm_out_file, "\t.save ");
24015 if (IS_VFP_REGNUM (REGNO (e1)))
24016 asm_fprintf(asm_out_file, "{d%d}\n",
24017 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
24019 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
24023 if (REGNO (e0) == SP_REGNUM)
24025 /* A stack increment. */
24026 if (GET_CODE (e1) != PLUS
24027 || GET_CODE (XEXP (e1, 0)) != REG
24028 || REGNO (XEXP (e1, 0)) != SP_REGNUM
24029 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
24032 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
24033 -INTVAL (XEXP (e1, 1)));
24035 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
24037 HOST_WIDE_INT offset;
24039 if (GET_CODE (e1) == PLUS)
24041 if (GET_CODE (XEXP (e1, 0)) != REG
24042 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
24044 reg = REGNO (XEXP (e1, 0));
24045 offset = INTVAL (XEXP (e1, 1));
24046 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
24047 HARD_FRAME_POINTER_REGNUM, reg,
24050 else if (GET_CODE (e1) == REG)
24053 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
24054 HARD_FRAME_POINTER_REGNUM, reg);
24059 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
24061 /* Move from sp to reg. */
24062 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
24064 else if (GET_CODE (e1) == PLUS
24065 && GET_CODE (XEXP (e1, 0)) == REG
24066 && REGNO (XEXP (e1, 0)) == SP_REGNUM
24067 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
24069 /* Set reg to offset from sp. */
24070 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
24071 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
24083 /* Emit unwind directives for the given insn. */
24086 arm_unwind_emit (FILE * asm_out_file, rtx insn)
24089 bool handled_one = false;
24091 if (arm_except_unwind_info (&global_options) != UI_TARGET)
24094 if (!(flag_unwind_tables || crtl->uses_eh_lsda)
24095 && (TREE_NOTHROW (current_function_decl)
24096 || crtl->all_throwers_are_sibcalls))
24099 if (NOTE_P (insn) || !RTX_FRAME_RELATED_P (insn))
24102 for (note = REG_NOTES (insn); note ; note = XEXP (note, 1))
24104 pat = XEXP (note, 0);
24105 switch (REG_NOTE_KIND (note))
24107 case REG_FRAME_RELATED_EXPR:
24110 case REG_CFA_REGISTER:
24113 pat = PATTERN (insn);
24114 if (GET_CODE (pat) == PARALLEL)
24115 pat = XVECEXP (pat, 0, 0);
24118 /* Only emitted for IS_STACKALIGN re-alignment. */
24123 src = SET_SRC (pat);
24124 dest = SET_DEST (pat);
24126 gcc_assert (src == stack_pointer_rtx);
24127 reg = REGNO (dest);
24128 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
24131 handled_one = true;
24134 case REG_CFA_DEF_CFA:
24135 case REG_CFA_EXPRESSION:
24136 case REG_CFA_ADJUST_CFA:
24137 case REG_CFA_OFFSET:
24138 /* ??? Only handling here what we actually emit. */
24139 gcc_unreachable ();
24147 pat = PATTERN (insn);
24150 switch (GET_CODE (pat))
24153 arm_unwind_emit_set (asm_out_file, pat);
24157 /* Store multiple. */
24158 arm_unwind_emit_sequence (asm_out_file, pat);
24167 /* Output a reference from a function exception table to the type_info
24168 object X. The EABI specifies that the symbol should be relocated by
24169 an R_ARM_TARGET2 relocation. */
24172 arm_output_ttype (rtx x)
24174 fputs ("\t.word\t", asm_out_file);
24175 output_addr_const (asm_out_file, x);
24176 /* Use special relocations for symbol references. */
24177 if (GET_CODE (x) != CONST_INT)
24178 fputs ("(TARGET2)", asm_out_file);
24179 fputc ('\n', asm_out_file);
24184 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
24187 arm_asm_emit_except_personality (rtx personality)
24189 fputs ("\t.personality\t", asm_out_file);
24190 output_addr_const (asm_out_file, personality);
24191 fputc ('\n', asm_out_file);
24194 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
24197 arm_asm_init_sections (void)
24199 exception_section = get_unnamed_section (0, output_section_asm_op,
24202 #endif /* ARM_UNWIND_INFO */
24204 /* Output unwind directives for the start/end of a function. */
24207 arm_output_fn_unwind (FILE * f, bool prologue)
24209 if (arm_except_unwind_info (&global_options) != UI_TARGET)
24213 fputs ("\t.fnstart\n", f);
24216 /* If this function will never be unwound, then mark it as such.
24217 The came condition is used in arm_unwind_emit to suppress
24218 the frame annotations. */
24219 if (!(flag_unwind_tables || crtl->uses_eh_lsda)
24220 && (TREE_NOTHROW (current_function_decl)
24221 || crtl->all_throwers_are_sibcalls))
24222 fputs("\t.cantunwind\n", f);
24224 fputs ("\t.fnend\n", f);
24229 arm_emit_tls_decoration (FILE *fp, rtx x)
24231 enum tls_reloc reloc;
24234 val = XVECEXP (x, 0, 0);
24235 reloc = (enum tls_reloc) INTVAL (XVECEXP (x, 0, 1));
24237 output_addr_const (fp, val);
24242 fputs ("(tlsgd)", fp);
24245 fputs ("(tlsldm)", fp);
24248 fputs ("(tlsldo)", fp);
24251 fputs ("(gottpoff)", fp);
24254 fputs ("(tpoff)", fp);
24257 fputs ("(tlsdesc)", fp);
24260 gcc_unreachable ();
24269 fputs (" + (. - ", fp);
24270 output_addr_const (fp, XVECEXP (x, 0, 2));
24271 /* For DESCSEQ the 3rd operand encodes thumbness, and is added */
24272 fputs (reloc == TLS_DESCSEQ ? " + " : " - ", fp);
24273 output_addr_const (fp, XVECEXP (x, 0, 3));
24283 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
24286 arm_output_dwarf_dtprel (FILE *file, int size, rtx x)
24288 gcc_assert (size == 4);
24289 fputs ("\t.word\t", file);
24290 output_addr_const (file, x);
24291 fputs ("(tlsldo)", file);
24294 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
24297 arm_output_addr_const_extra (FILE *fp, rtx x)
24299 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
24300 return arm_emit_tls_decoration (fp, x);
24301 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
24304 int labelno = INTVAL (XVECEXP (x, 0, 0));
24306 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
24307 assemble_name_raw (fp, label);
24311 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOTSYM_OFF)
24313 assemble_name (fp, "_GLOBAL_OFFSET_TABLE_");
24317 output_addr_const (fp, XVECEXP (x, 0, 0));
24321 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET)
24323 output_addr_const (fp, XVECEXP (x, 0, 0));
24327 output_addr_const (fp, XVECEXP (x, 0, 1));
24331 else if (GET_CODE (x) == CONST_VECTOR)
24332 return arm_emit_vector_const (fp, x);
24337 /* Output assembly for a shift instruction.
24338 SET_FLAGS determines how the instruction modifies the condition codes.
24339 0 - Do not set condition codes.
24340 1 - Set condition codes.
24341 2 - Use smallest instruction. */
24343 arm_output_shift(rtx * operands, int set_flags)
24346 static const char flag_chars[3] = {'?', '.', '!'};
24351 c = flag_chars[set_flags];
24352 if (TARGET_UNIFIED_ASM)
24354 shift = shift_op(operands[3], &val);
24358 operands[2] = GEN_INT(val);
24359 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
24362 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
24365 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
24366 output_asm_insn (pattern, operands);
24370 /* Output a Thumb-1 casesi dispatch sequence. */
24372 thumb1_output_casesi (rtx *operands)
24374 rtx diff_vec = PATTERN (next_real_insn (operands[0]));
24376 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
24378 switch (GET_MODE(diff_vec))
24381 return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ?
24382 "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi");
24384 return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ?
24385 "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi");
24387 return "bl\t%___gnu_thumb1_case_si";
24389 gcc_unreachable ();
24393 /* Output a Thumb-2 casesi instruction. */
24395 thumb2_output_casesi (rtx *operands)
24397 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
24399 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
24401 output_asm_insn ("cmp\t%0, %1", operands);
24402 output_asm_insn ("bhi\t%l3", operands);
24403 switch (GET_MODE(diff_vec))
24406 return "tbb\t[%|pc, %0]";
24408 return "tbh\t[%|pc, %0, lsl #1]";
24412 output_asm_insn ("adr\t%4, %l2", operands);
24413 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
24414 output_asm_insn ("add\t%4, %4, %5", operands);
24419 output_asm_insn ("adr\t%4, %l2", operands);
24420 return "ldr\t%|pc, [%4, %0, lsl #2]";
24423 gcc_unreachable ();
24427 /* Most ARM cores are single issue, but some newer ones can dual issue.
24428 The scheduler descriptions rely on this being correct. */
24430 arm_issue_rate (void)
24452 /* A table and a function to perform ARM-specific name mangling for
24453 NEON vector types in order to conform to the AAPCS (see "Procedure
24454 Call Standard for the ARM Architecture", Appendix A). To qualify
24455 for emission with the mangled names defined in that document, a
24456 vector type must not only be of the correct mode but also be
24457 composed of NEON vector element types (e.g. __builtin_neon_qi). */
24460 enum machine_mode mode;
24461 const char *element_type_name;
24462 const char *aapcs_name;
24463 } arm_mangle_map_entry;
24465 static arm_mangle_map_entry arm_mangle_map[] = {
24466 /* 64-bit containerized types. */
24467 { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" },
24468 { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" },
24469 { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" },
24470 { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" },
24471 { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" },
24472 { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" },
24473 { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" },
24474 { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" },
24475 { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" },
24476 /* 128-bit containerized types. */
24477 { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" },
24478 { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" },
24479 { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" },
24480 { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" },
24481 { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" },
24482 { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" },
24483 { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" },
24484 { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" },
24485 { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" },
24486 { VOIDmode, NULL, NULL }
24490 arm_mangle_type (const_tree type)
24492 arm_mangle_map_entry *pos = arm_mangle_map;
24494 /* The ARM ABI documents (10th October 2008) say that "__va_list"
24495 has to be managled as if it is in the "std" namespace. */
24496 if (TARGET_AAPCS_BASED
24497 && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type))
24499 static bool warned;
24500 if (!warned && warn_psabi && !in_system_header)
24503 inform (input_location,
24504 "the mangling of %<va_list%> has changed in GCC 4.4");
24506 return "St9__va_list";
24509 /* Half-precision float. */
24510 if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16)
24513 if (TREE_CODE (type) != VECTOR_TYPE)
24516 /* Check the mode of the vector type, and the name of the vector
24517 element type, against the table. */
24518 while (pos->mode != VOIDmode)
24520 tree elt_type = TREE_TYPE (type);
24522 if (pos->mode == TYPE_MODE (type)
24523 && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL
24524 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))),
24525 pos->element_type_name))
24526 return pos->aapcs_name;
24531 /* Use the default mangling for unrecognized (possibly user-defined)
24536 /* Order of allocation of core registers for Thumb: this allocation is
24537 written over the corresponding initial entries of the array
24538 initialized with REG_ALLOC_ORDER. We allocate all low registers
24539 first. Saving and restoring a low register is usually cheaper than
24540 using a call-clobbered high register. */
24542 static const int thumb_core_reg_alloc_order[] =
24544 3, 2, 1, 0, 4, 5, 6, 7,
24545 14, 12, 8, 9, 10, 11, 13, 15
24548 /* Adjust register allocation order when compiling for Thumb. */
24551 arm_order_regs_for_local_alloc (void)
24553 const int arm_reg_alloc_order[] = REG_ALLOC_ORDER;
24554 memcpy(reg_alloc_order, arm_reg_alloc_order, sizeof (reg_alloc_order));
24556 memcpy (reg_alloc_order, thumb_core_reg_alloc_order,
24557 sizeof (thumb_core_reg_alloc_order));
24560 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
24563 arm_frame_pointer_required (void)
24565 return (cfun->has_nonlocal_label
24566 || SUBTARGET_FRAME_POINTER_REQUIRED
24567 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()));
24570 /* Only thumb1 can't support conditional execution, so return true if
24571 the target is not thumb1. */
24573 arm_have_conditional_execution (void)
24575 return !TARGET_THUMB1;
24578 /* The AAPCS sets the maximum alignment of a vector to 64 bits. */
24579 static HOST_WIDE_INT
24580 arm_vector_alignment (const_tree type)
24582 HOST_WIDE_INT align = tree_low_cst (TYPE_SIZE (type), 0);
24584 if (TARGET_AAPCS_BASED)
24585 align = MIN (align, 64);
24590 static unsigned int
24591 arm_autovectorize_vector_sizes (void)
24593 return TARGET_NEON_VECTORIZE_DOUBLE ? 0 : (16 | 8);
24597 arm_vector_alignment_reachable (const_tree type, bool is_packed)
24599 /* Vectors which aren't in packed structures will not be less aligned than
24600 the natural alignment of their element type, so this is safe. */
24601 if (TARGET_NEON && !BYTES_BIG_ENDIAN)
24604 return default_builtin_vector_alignment_reachable (type, is_packed);
24608 arm_builtin_support_vector_misalignment (enum machine_mode mode,
24609 const_tree type, int misalignment,
24612 if (TARGET_NEON && !BYTES_BIG_ENDIAN)
24614 HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type);
24619 /* If the misalignment is unknown, we should be able to handle the access
24620 so long as it is not to a member of a packed data structure. */
24621 if (misalignment == -1)
24624 /* Return true if the misalignment is a multiple of the natural alignment
24625 of the vector's element type. This is probably always going to be
24626 true in practice, since we've already established that this isn't a
24628 return ((misalignment % align) == 0);
24631 return default_builtin_support_vector_misalignment (mode, type, misalignment,
24636 arm_conditional_register_usage (void)
24640 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA)
24642 for (regno = FIRST_FPA_REGNUM;
24643 regno <= LAST_FPA_REGNUM; ++regno)
24644 fixed_regs[regno] = call_used_regs[regno] = 1;
24647 if (TARGET_THUMB1 && optimize_size)
24649 /* When optimizing for size on Thumb-1, it's better not
24650 to use the HI regs, because of the overhead of
24652 for (regno = FIRST_HI_REGNUM;
24653 regno <= LAST_HI_REGNUM; ++regno)
24654 fixed_regs[regno] = call_used_regs[regno] = 1;
24657 /* The link register can be clobbered by any branch insn,
24658 but we have no way to track that at present, so mark
24659 it as unavailable. */
24661 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
24663 if (TARGET_32BIT && TARGET_HARD_FLOAT)
24665 if (TARGET_MAVERICK)
24667 for (regno = FIRST_FPA_REGNUM;
24668 regno <= LAST_FPA_REGNUM; ++ regno)
24669 fixed_regs[regno] = call_used_regs[regno] = 1;
24670 for (regno = FIRST_CIRRUS_FP_REGNUM;
24671 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno)
24673 fixed_regs[regno] = 0;
24674 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4;
24679 /* VFPv3 registers are disabled when earlier VFP
24680 versions are selected due to the definition of
24681 LAST_VFP_REGNUM. */
24682 for (regno = FIRST_VFP_REGNUM;
24683 regno <= LAST_VFP_REGNUM; ++ regno)
24685 fixed_regs[regno] = 0;
24686 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16
24687 || regno >= FIRST_VFP_REGNUM + 32;
24692 if (TARGET_REALLY_IWMMXT)
24694 regno = FIRST_IWMMXT_GR_REGNUM;
24695 /* The 2002/10/09 revision of the XScale ABI has wCG0
24696 and wCG1 as call-preserved registers. The 2002/11/21
24697 revision changed this so that all wCG registers are
24698 scratch registers. */
24699 for (regno = FIRST_IWMMXT_GR_REGNUM;
24700 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno)
24701 fixed_regs[regno] = 0;
24702 /* The XScale ABI has wR0 - wR9 as scratch registers,
24703 the rest as call-preserved registers. */
24704 for (regno = FIRST_IWMMXT_REGNUM;
24705 regno <= LAST_IWMMXT_REGNUM; ++ regno)
24707 fixed_regs[regno] = 0;
24708 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10;
24712 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
24714 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
24715 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
24717 else if (TARGET_APCS_STACK)
24719 fixed_regs[10] = 1;
24720 call_used_regs[10] = 1;
24722 /* -mcaller-super-interworking reserves r11 for calls to
24723 _interwork_r11_call_via_rN(). Making the register global
24724 is an easy way of ensuring that it remains valid for all
24726 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING
24727 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME)
24729 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;
24730 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;
24731 if (TARGET_CALLER_INTERWORKING)
24732 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;
24734 SUBTARGET_CONDITIONAL_REGISTER_USAGE
24738 arm_preferred_rename_class (reg_class_t rclass)
24740 /* Thumb-2 instructions using LO_REGS may be smaller than instructions
24741 using GENERIC_REGS. During register rename pass, we prefer LO_REGS,
24742 and code size can be reduced. */
24743 if (TARGET_THUMB2 && rclass == GENERAL_REGS)
24749 /* Compute the atrribute "length" of insn "*push_multi".
24750 So this function MUST be kept in sync with that insn pattern. */
24752 arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
24754 int i, regno, hi_reg;
24755 int num_saves = XVECLEN (parallel_op, 0);
24765 regno = REGNO (first_op);
24766 hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
24767 for (i = 1; i < num_saves && !hi_reg; i++)
24769 regno = REGNO (XEXP (XVECEXP (parallel_op, 0, i), 0));
24770 hi_reg |= (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
24778 /* Compute the number of instructions emitted by output_move_double. */
24780 arm_count_output_move_double_insns (rtx *operands)
24784 /* output_move_double may modify the operands array, so call it
24785 here on a copy of the array. */
24786 ops[0] = operands[0];
24787 ops[1] = operands[1];
24788 output_move_double (ops, false, &count);
24793 vfp3_const_double_for_fract_bits (rtx operand)
24795 REAL_VALUE_TYPE r0;
24797 if (GET_CODE (operand) != CONST_DOUBLE)
24800 REAL_VALUE_FROM_CONST_DOUBLE (r0, operand);
24801 if (exact_real_inverse (DFmode, &r0))
24803 if (exact_real_truncate (DFmode, &r0))
24805 HOST_WIDE_INT value = real_to_integer (&r0);
24806 value = value & 0xffffffff;
24807 if ((value != 0) && ( (value & (value - 1)) == 0))
24808 return int_log2 (value);
24814 /* Emit a memory barrier around an atomic sequence according to MODEL. */
24817 arm_pre_atomic_barrier (enum memmodel model)
24821 case MEMMODEL_RELAXED:
24822 case MEMMODEL_CONSUME:
24823 case MEMMODEL_ACQUIRE:
24825 case MEMMODEL_RELEASE:
24826 case MEMMODEL_ACQ_REL:
24827 case MEMMODEL_SEQ_CST:
24828 emit_insn (gen_memory_barrier ());
24831 gcc_unreachable ();
24836 arm_post_atomic_barrier (enum memmodel model)
24840 case MEMMODEL_RELAXED:
24841 case MEMMODEL_CONSUME:
24842 case MEMMODEL_RELEASE:
24844 case MEMMODEL_ACQUIRE:
24845 case MEMMODEL_ACQ_REL:
24846 case MEMMODEL_SEQ_CST:
24847 emit_insn (gen_memory_barrier ());
24850 gcc_unreachable ();
24854 /* Emit the load-exclusive and store-exclusive instructions. */
24857 arm_emit_load_exclusive (enum machine_mode mode, rtx rval, rtx mem)
24859 rtx (*gen) (rtx, rtx);
24863 case QImode: gen = gen_arm_load_exclusiveqi; break;
24864 case HImode: gen = gen_arm_load_exclusivehi; break;
24865 case SImode: gen = gen_arm_load_exclusivesi; break;
24866 case DImode: gen = gen_arm_load_exclusivedi; break;
24868 gcc_unreachable ();
24871 emit_insn (gen (rval, mem));
24875 arm_emit_store_exclusive (enum machine_mode mode, rtx bval, rtx rval, rtx mem)
24877 rtx (*gen) (rtx, rtx, rtx);
24881 case QImode: gen = gen_arm_store_exclusiveqi; break;
24882 case HImode: gen = gen_arm_store_exclusivehi; break;
24883 case SImode: gen = gen_arm_store_exclusivesi; break;
24884 case DImode: gen = gen_arm_store_exclusivedi; break;
24886 gcc_unreachable ();
24889 emit_insn (gen (bval, rval, mem));
24892 /* Mark the previous jump instruction as unlikely. */
24895 emit_unlikely_jump (rtx insn)
24897 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
24899 insn = emit_jump_insn (insn);
24900 add_reg_note (insn, REG_BR_PROB, very_unlikely);
24903 /* Expand a compare and swap pattern. */
24906 arm_expand_compare_and_swap (rtx operands[])
24908 rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
24909 enum machine_mode mode;
24910 rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
24912 bval = operands[0];
24913 rval = operands[1];
24915 oldval = operands[3];
24916 newval = operands[4];
24917 is_weak = operands[5];
24918 mod_s = operands[6];
24919 mod_f = operands[7];
24920 mode = GET_MODE (mem);
24926 /* For narrow modes, we're going to perform the comparison in SImode,
24927 so do the zero-extension now. */
24928 rval = gen_reg_rtx (SImode);
24929 oldval = convert_modes (SImode, mode, oldval, true);
24933 /* Force the value into a register if needed. We waited until after
24934 the zero-extension above to do this properly. */
24935 if (!arm_add_operand (oldval, SImode))
24936 oldval = force_reg (SImode, oldval);
24940 if (!cmpdi_operand (oldval, mode))
24941 oldval = force_reg (mode, oldval);
24945 gcc_unreachable ();
24950 case QImode: gen = gen_atomic_compare_and_swapqi_1; break;
24951 case HImode: gen = gen_atomic_compare_and_swaphi_1; break;
24952 case SImode: gen = gen_atomic_compare_and_swapsi_1; break;
24953 case DImode: gen = gen_atomic_compare_and_swapdi_1; break;
24955 gcc_unreachable ();
24958 emit_insn (gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
24960 if (mode == QImode || mode == HImode)
24961 emit_move_insn (operands[1], gen_lowpart (mode, rval));
24963 /* In all cases, we arrange for success to be signaled by Z set.
24964 This arrangement allows for the boolean result to be used directly
24965 in a subsequent branch, post optimization. */
24966 x = gen_rtx_REG (CCmode, CC_REGNUM);
24967 x = gen_rtx_EQ (SImode, x, const0_rtx);
24968 emit_insn (gen_rtx_SET (VOIDmode, bval, x));
24971 /* Split a compare and swap pattern. It is IMPLEMENTATION DEFINED whether
24972 another memory store between the load-exclusive and store-exclusive can
24973 reset the monitor from Exclusive to Open state. This means we must wait
24974 until after reload to split the pattern, lest we get a register spill in
24975 the middle of the atomic sequence. */
24978 arm_split_compare_and_swap (rtx operands[])
24980 rtx rval, mem, oldval, newval, scratch;
24981 enum machine_mode mode;
24982 enum memmodel mod_s, mod_f;
24984 rtx label1, label2, x, cond;
24986 rval = operands[0];
24988 oldval = operands[2];
24989 newval = operands[3];
24990 is_weak = (operands[4] != const0_rtx);
24991 mod_s = (enum memmodel) INTVAL (operands[5]);
24992 mod_f = (enum memmodel) INTVAL (operands[6]);
24993 scratch = operands[7];
24994 mode = GET_MODE (mem);
24996 arm_pre_atomic_barrier (mod_s);
25001 label1 = gen_label_rtx ();
25002 emit_label (label1);
25004 label2 = gen_label_rtx ();
25006 arm_emit_load_exclusive (mode, rval, mem);
25008 cond = arm_gen_compare_reg (NE, rval, oldval, scratch);
25009 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
25010 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
25011 gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
25012 emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x));
25014 arm_emit_store_exclusive (mode, scratch, mem, newval);
25016 /* Weak or strong, we want EQ to be true for success, so that we
25017 match the flags that we got from the compare above. */
25018 cond = gen_rtx_REG (CCmode, CC_REGNUM);
25019 x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx);
25020 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
25024 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
25025 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
25026 gen_rtx_LABEL_REF (Pmode, label1), pc_rtx);
25027 emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x));
25030 if (mod_f != MEMMODEL_RELAXED)
25031 emit_label (label2);
25033 arm_post_atomic_barrier (mod_s);
25035 if (mod_f == MEMMODEL_RELAXED)
25036 emit_label (label2);
25040 arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
25041 rtx value, rtx model_rtx, rtx cond)
25043 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
25044 enum machine_mode mode = GET_MODE (mem);
25045 enum machine_mode wmode = (mode == DImode ? DImode : SImode);
25048 arm_pre_atomic_barrier (model);
25050 label = gen_label_rtx ();
25051 emit_label (label);
25054 new_out = gen_lowpart (wmode, new_out);
25056 old_out = gen_lowpart (wmode, old_out);
25059 value = simplify_gen_subreg (wmode, value, mode, 0);
25061 arm_emit_load_exclusive (mode, old_out, mem);
25070 x = gen_rtx_AND (wmode, old_out, value);
25071 emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
25072 x = gen_rtx_NOT (wmode, new_out);
25073 emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
25077 if (CONST_INT_P (value))
25079 value = GEN_INT (-INTVAL (value));
25085 if (mode == DImode)
25087 /* DImode plus/minus need to clobber flags. */
25088 /* The adddi3 and subdi3 patterns are incorrectly written so that
25089 they require matching operands, even when we could easily support
25090 three operands. Thankfully, this can be fixed up post-splitting,
25091 as the individual add+adc patterns do accept three operands and
25092 post-reload cprop can make these moves go away. */
25093 emit_move_insn (new_out, old_out);
25095 x = gen_adddi3 (new_out, new_out, value);
25097 x = gen_subdi3 (new_out, new_out, value);
25104 x = gen_rtx_fmt_ee (code, wmode, old_out, value);
25105 emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
25109 arm_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out));
25111 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
25112 emit_unlikely_jump (gen_cbranchsi4 (x, cond, const0_rtx, label));
25114 arm_post_atomic_barrier (model);
25117 #define MAX_VECT_LEN 16
25119 struct expand_vec_perm_d
25121 rtx target, op0, op1;
25122 unsigned char perm[MAX_VECT_LEN];
25123 enum machine_mode vmode;
25124 unsigned char nelt;
25129 /* Generate a variable permutation. */
25132 arm_expand_vec_perm_1 (rtx target, rtx op0, rtx op1, rtx sel)
25134 enum machine_mode vmode = GET_MODE (target);
25135 bool one_vector_p = rtx_equal_p (op0, op1);
25137 gcc_checking_assert (vmode == V8QImode || vmode == V16QImode);
25138 gcc_checking_assert (GET_MODE (op0) == vmode);
25139 gcc_checking_assert (GET_MODE (op1) == vmode);
25140 gcc_checking_assert (GET_MODE (sel) == vmode);
25141 gcc_checking_assert (TARGET_NEON);
25145 if (vmode == V8QImode)
25146 emit_insn (gen_neon_vtbl1v8qi (target, op0, sel));
25148 emit_insn (gen_neon_vtbl1v16qi (target, op0, sel));
25154 if (vmode == V8QImode)
25156 pair = gen_reg_rtx (V16QImode);
25157 emit_insn (gen_neon_vcombinev8qi (pair, op0, op1));
25158 pair = gen_lowpart (TImode, pair);
25159 emit_insn (gen_neon_vtbl2v8qi (target, pair, sel));
25163 pair = gen_reg_rtx (OImode);
25164 emit_insn (gen_neon_vcombinev16qi (pair, op0, op1));
25165 emit_insn (gen_neon_vtbl2v16qi (target, pair, sel));
25171 arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
25173 enum machine_mode vmode = GET_MODE (target);
25174 unsigned int i, nelt = GET_MODE_NUNITS (vmode);
25175 bool one_vector_p = rtx_equal_p (op0, op1);
25176 rtx rmask[MAX_VECT_LEN], mask;
25178 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
25179 numbering of elements for big-endian, we must reverse the order. */
25180 gcc_checking_assert (!BYTES_BIG_ENDIAN);
25182 /* The VTBL instruction does not use a modulo index, so we must take care
25183 of that ourselves. */
25184 mask = GEN_INT (one_vector_p ? nelt - 1 : 2 * nelt - 1);
25185 for (i = 0; i < nelt; ++i)
25187 mask = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rmask));
25188 sel = expand_simple_binop (vmode, AND, sel, mask, NULL, 0, OPTAB_LIB_WIDEN);
25190 arm_expand_vec_perm_1 (target, op0, op1, sel);
25193 /* Generate or test for an insn that supports a constant permutation. */
25195 /* Recognize patterns for the VUZP insns. */
25198 arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
25200 unsigned int i, odd, mask, nelt = d->nelt;
25201 rtx out0, out1, in0, in1, x;
25202 rtx (*gen)(rtx, rtx, rtx, rtx);
25204 if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
25207 /* Note that these are little-endian tests. Adjust for big-endian later. */
25208 if (d->perm[0] == 0)
25210 else if (d->perm[0] == 1)
25214 mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
25216 for (i = 0; i < nelt; i++)
25218 unsigned elt = (i * 2 + odd) & mask;
25219 if (d->perm[i] != elt)
25229 case V16QImode: gen = gen_neon_vuzpv16qi_internal; break;
25230 case V8QImode: gen = gen_neon_vuzpv8qi_internal; break;
25231 case V8HImode: gen = gen_neon_vuzpv8hi_internal; break;
25232 case V4HImode: gen = gen_neon_vuzpv4hi_internal; break;
25233 case V4SImode: gen = gen_neon_vuzpv4si_internal; break;
25234 case V2SImode: gen = gen_neon_vuzpv2si_internal; break;
25235 case V2SFmode: gen = gen_neon_vuzpv2sf_internal; break;
25236 case V4SFmode: gen = gen_neon_vuzpv4sf_internal; break;
25238 gcc_unreachable ();
25243 if (BYTES_BIG_ENDIAN)
25245 x = in0, in0 = in1, in1 = x;
25250 out1 = gen_reg_rtx (d->vmode);
25252 x = out0, out0 = out1, out1 = x;
25254 emit_insn (gen (out0, in0, in1, out1));
25258 /* Recognize patterns for the VZIP insns. */
25261 arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
25263 unsigned int i, high, mask, nelt = d->nelt;
25264 rtx out0, out1, in0, in1, x;
25265 rtx (*gen)(rtx, rtx, rtx, rtx);
25267 if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
25270 /* Note that these are little-endian tests. Adjust for big-endian later. */
25272 if (d->perm[0] == high)
25274 else if (d->perm[0] == 0)
25278 mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
25280 for (i = 0; i < nelt / 2; i++)
25282 unsigned elt = (i + high) & mask;
25283 if (d->perm[i * 2] != elt)
25285 elt = (elt + nelt) & mask;
25286 if (d->perm[i * 2 + 1] != elt)
25296 case V16QImode: gen = gen_neon_vzipv16qi_internal; break;
25297 case V8QImode: gen = gen_neon_vzipv8qi_internal; break;
25298 case V8HImode: gen = gen_neon_vzipv8hi_internal; break;
25299 case V4HImode: gen = gen_neon_vzipv4hi_internal; break;
25300 case V4SImode: gen = gen_neon_vzipv4si_internal; break;
25301 case V2SImode: gen = gen_neon_vzipv2si_internal; break;
25302 case V2SFmode: gen = gen_neon_vzipv2sf_internal; break;
25303 case V4SFmode: gen = gen_neon_vzipv4sf_internal; break;
25305 gcc_unreachable ();
25310 if (BYTES_BIG_ENDIAN)
25312 x = in0, in0 = in1, in1 = x;
25317 out1 = gen_reg_rtx (d->vmode);
25319 x = out0, out0 = out1, out1 = x;
25321 emit_insn (gen (out0, in0, in1, out1));
25325 /* Recognize patterns for the VREV insns. */
25328 arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
25330 unsigned int i, j, diff, nelt = d->nelt;
25331 rtx (*gen)(rtx, rtx, rtx);
25333 if (!d->one_vector_p)
25342 case V16QImode: gen = gen_neon_vrev64v16qi; break;
25343 case V8QImode: gen = gen_neon_vrev64v8qi; break;
25351 case V16QImode: gen = gen_neon_vrev32v16qi; break;
25352 case V8QImode: gen = gen_neon_vrev32v8qi; break;
25353 case V8HImode: gen = gen_neon_vrev64v8hi; break;
25354 case V4HImode: gen = gen_neon_vrev64v4hi; break;
25362 case V16QImode: gen = gen_neon_vrev16v16qi; break;
25363 case V8QImode: gen = gen_neon_vrev16v8qi; break;
25364 case V8HImode: gen = gen_neon_vrev32v8hi; break;
25365 case V4HImode: gen = gen_neon_vrev32v4hi; break;
25366 case V4SImode: gen = gen_neon_vrev64v4si; break;
25367 case V2SImode: gen = gen_neon_vrev64v2si; break;
25368 case V4SFmode: gen = gen_neon_vrev64v4sf; break;
25369 case V2SFmode: gen = gen_neon_vrev64v2sf; break;
25378 for (i = 0; i < nelt ; i += diff + 1)
25379 for (j = 0; j <= diff; j += 1)
25381 /* This is guaranteed to be true as the value of diff
25382 is 7, 3, 1 and we should have enough elements in the
25383 queue to generate this. Getting a vector mask with a
25384 value of diff other than these values implies that
25385 something is wrong by the time we get here. */
25386 gcc_assert (i + j < nelt);
25387 if (d->perm[i + j] != i + diff - j)
25395 /* ??? The third operand is an artifact of the builtin infrastructure
25396 and is ignored by the actual instruction. */
25397 emit_insn (gen (d->target, d->op0, const0_rtx));
25401 /* Recognize patterns for the VTRN insns. */
25404 arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
25406 unsigned int i, odd, mask, nelt = d->nelt;
25407 rtx out0, out1, in0, in1, x;
25408 rtx (*gen)(rtx, rtx, rtx, rtx);
25410 if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
25413 /* Note that these are little-endian tests. Adjust for big-endian later. */
25414 if (d->perm[0] == 0)
25416 else if (d->perm[0] == 1)
25420 mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
25422 for (i = 0; i < nelt; i += 2)
25424 if (d->perm[i] != i + odd)
25426 if (d->perm[i + 1] != ((i + nelt + odd) & mask))
25436 case V16QImode: gen = gen_neon_vtrnv16qi_internal; break;
25437 case V8QImode: gen = gen_neon_vtrnv8qi_internal; break;
25438 case V8HImode: gen = gen_neon_vtrnv8hi_internal; break;
25439 case V4HImode: gen = gen_neon_vtrnv4hi_internal; break;
25440 case V4SImode: gen = gen_neon_vtrnv4si_internal; break;
25441 case V2SImode: gen = gen_neon_vtrnv2si_internal; break;
25442 case V2SFmode: gen = gen_neon_vtrnv2sf_internal; break;
25443 case V4SFmode: gen = gen_neon_vtrnv4sf_internal; break;
25445 gcc_unreachable ();
25450 if (BYTES_BIG_ENDIAN)
25452 x = in0, in0 = in1, in1 = x;
25457 out1 = gen_reg_rtx (d->vmode);
25459 x = out0, out0 = out1, out1 = x;
25461 emit_insn (gen (out0, in0, in1, out1));
25465 /* The NEON VTBL instruction is a fully variable permuation that's even
25466 stronger than what we expose via VEC_PERM_EXPR. What it doesn't do
25467 is mask the index operand as VEC_PERM_EXPR requires. Therefore we
25468 can do slightly better by expanding this as a constant where we don't
25469 have to apply a mask. */
25472 arm_evpc_neon_vtbl (struct expand_vec_perm_d *d)
25474 rtx rperm[MAX_VECT_LEN], sel;
25475 enum machine_mode vmode = d->vmode;
25476 unsigned int i, nelt = d->nelt;
25478 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
25479 numbering of elements for big-endian, we must reverse the order. */
25480 if (BYTES_BIG_ENDIAN)
25486 /* Generic code will try constant permutation twice. Once with the
25487 original mode and again with the elements lowered to QImode.
25488 So wait and don't do the selector expansion ourselves. */
25489 if (vmode != V8QImode && vmode != V16QImode)
25492 for (i = 0; i < nelt; ++i)
25493 rperm[i] = GEN_INT (d->perm[i]);
25494 sel = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rperm));
25495 sel = force_reg (vmode, sel);
25497 arm_expand_vec_perm_1 (d->target, d->op0, d->op1, sel);
25502 arm_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
25504 /* The pattern matching functions above are written to look for a small
25505 number to begin the sequence (0, 1, N/2). If we begin with an index
25506 from the second operand, we can swap the operands. */
25507 if (d->perm[0] >= d->nelt)
25509 unsigned i, nelt = d->nelt;
25512 for (i = 0; i < nelt; ++i)
25513 d->perm[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
25522 if (arm_evpc_neon_vuzp (d))
25524 if (arm_evpc_neon_vzip (d))
25526 if (arm_evpc_neon_vrev (d))
25528 if (arm_evpc_neon_vtrn (d))
25530 return arm_evpc_neon_vtbl (d);
25535 /* Expand a vec_perm_const pattern. */
25538 arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel)
25540 struct expand_vec_perm_d d;
25541 int i, nelt, which;
25547 d.vmode = GET_MODE (target);
25548 gcc_assert (VECTOR_MODE_P (d.vmode));
25549 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
25550 d.testing_p = false;
25552 for (i = which = 0; i < nelt; ++i)
25554 rtx e = XVECEXP (sel, 0, i);
25555 int ei = INTVAL (e) & (2 * nelt - 1);
25556 which |= (ei < nelt ? 1 : 2);
25566 d.one_vector_p = false;
25567 if (!rtx_equal_p (op0, op1))
25570 /* The elements of PERM do not suggest that only the first operand
25571 is used, but both operands are identical. Allow easier matching
25572 of the permutation by folding the permutation into the single
25576 for (i = 0; i < nelt; ++i)
25577 d.perm[i] &= nelt - 1;
25579 d.one_vector_p = true;
25584 d.one_vector_p = true;
25588 return arm_expand_vec_perm_const_1 (&d);
25591 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
25594 arm_vectorize_vec_perm_const_ok (enum machine_mode vmode,
25595 const unsigned char *sel)
25597 struct expand_vec_perm_d d;
25598 unsigned int i, nelt, which;
25602 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
25603 d.testing_p = true;
25604 memcpy (d.perm, sel, nelt);
25606 /* Categorize the set of elements in the selector. */
25607 for (i = which = 0; i < nelt; ++i)
25609 unsigned char e = d.perm[i];
25610 gcc_assert (e < 2 * nelt);
25611 which |= (e < nelt ? 1 : 2);
25614 /* For all elements from second vector, fold the elements to first. */
25616 for (i = 0; i < nelt; ++i)
25619 /* Check whether the mask can be applied to the vector type. */
25620 d.one_vector_p = (which != 3);
25622 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
25623 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
25624 if (!d.one_vector_p)
25625 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
25628 ret = arm_expand_vec_perm_const_1 (&d);
25635 #include "gt-arm.h"