1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
41 #include "diagnostic-core.h"
48 #include "target-def.h"
50 #include "langhooks.h"
58 /* Forward definitions of types. */
59 typedef struct minipool_node Mnode;
60 typedef struct minipool_fixup Mfix;
62 void (*arm_lang_output_object_attributes_hook)(void);
69 /* Forward function declarations. */
70 static bool arm_needs_doubleword_align (enum machine_mode, const_tree);
71 static int arm_compute_static_chain_stack_bytes (void);
72 static arm_stack_offsets *arm_get_frame_offsets (void);
73 static void arm_add_gc_roots (void);
74 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
75 HOST_WIDE_INT, rtx, rtx, int, int);
76 static unsigned bit_count (unsigned long);
77 static int arm_address_register_rtx_p (rtx, int);
78 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
79 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
80 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
81 static rtx arm_legitimize_address (rtx, rtx, enum machine_mode);
82 static reg_class_t arm_preferred_reload_class (rtx, reg_class_t);
83 static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode);
84 inline static int thumb1_index_register_rtx_p (rtx, int);
85 static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
86 static int thumb_far_jump_used_p (void);
87 static bool thumb_force_lr_save (void);
88 static unsigned arm_size_return_regs (void);
89 static bool arm_assemble_integer (rtx, unsigned int, int);
90 static void arm_print_operand (FILE *, rtx, int);
91 static void arm_print_operand_address (FILE *, rtx);
92 static bool arm_print_operand_punct_valid_p (unsigned char code);
93 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
94 static arm_cc get_arm_condition_code (rtx);
95 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
96 static rtx is_jump_table (rtx);
97 static const char *output_multi_immediate (rtx *, const char *, const char *,
99 static const char *shift_op (rtx, HOST_WIDE_INT *);
100 static struct machine_function *arm_init_machine_status (void);
101 static void thumb_exit (FILE *, int);
102 static rtx is_jump_table (rtx);
103 static HOST_WIDE_INT get_jump_table_size (rtx);
104 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
105 static Mnode *add_minipool_forward_ref (Mfix *);
106 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
107 static Mnode *add_minipool_backward_ref (Mfix *);
108 static void assign_minipool_offsets (Mfix *);
109 static void arm_print_value (FILE *, rtx);
110 static void dump_minipool (rtx);
111 static int arm_barrier_cost (rtx);
112 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
113 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
114 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
116 static void arm_reorg (void);
117 static void note_invalid_constants (rtx, HOST_WIDE_INT, int);
118 static unsigned long arm_compute_save_reg0_reg12_mask (void);
119 static unsigned long arm_compute_save_reg_mask (void);
120 static unsigned long arm_isr_value (tree);
121 static unsigned long arm_compute_func_type (void);
122 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
123 static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *);
124 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
125 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
126 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
128 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
129 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
130 static int arm_comp_type_attributes (const_tree, const_tree);
131 static void arm_set_default_type_attributes (tree);
132 static int arm_adjust_cost (rtx, rtx, rtx, int);
133 static int arm_sched_reorder (FILE *, int, rtx *, int *, int);
134 static int optimal_immediate_sequence (enum rtx_code code,
135 unsigned HOST_WIDE_INT val,
136 struct four_ints *return_sequence);
137 static int optimal_immediate_sequence_1 (enum rtx_code code,
138 unsigned HOST_WIDE_INT val,
139 struct four_ints *return_sequence,
141 static int arm_get_strip_length (int);
142 static bool arm_function_ok_for_sibcall (tree, tree);
143 static enum machine_mode arm_promote_function_mode (const_tree,
144 enum machine_mode, int *,
146 static bool arm_return_in_memory (const_tree, const_tree);
147 static rtx arm_function_value (const_tree, const_tree, bool);
148 static rtx arm_libcall_value_1 (enum machine_mode);
149 static rtx arm_libcall_value (enum machine_mode, const_rtx);
150 static bool arm_function_value_regno_p (const unsigned int);
151 static void arm_internal_label (FILE *, const char *, unsigned long);
152 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
154 static bool arm_have_conditional_execution (void);
155 static bool arm_cannot_force_const_mem (enum machine_mode, rtx);
156 static bool arm_legitimate_constant_p (enum machine_mode, rtx);
157 static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
158 static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
159 static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
160 static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
161 static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
162 static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
163 static bool arm_rtx_costs (rtx, int, int, int, int *, bool);
164 static int arm_address_cost (rtx, enum machine_mode, addr_space_t, bool);
165 static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
166 static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool);
167 static void arm_init_builtins (void);
168 static void arm_init_iwmmxt_builtins (void);
169 static rtx safe_vector_operand (rtx, enum machine_mode);
170 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
171 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
172 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
173 static tree arm_builtin_decl (unsigned, bool);
174 static void emit_constant_insn (rtx cond, rtx pattern);
175 static rtx emit_set_insn (rtx, rtx);
176 static int arm_arg_partial_bytes (cumulative_args_t, enum machine_mode,
178 static rtx arm_function_arg (cumulative_args_t, enum machine_mode,
180 static void arm_function_arg_advance (cumulative_args_t, enum machine_mode,
182 static unsigned int arm_function_arg_boundary (enum machine_mode, const_tree);
183 static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree,
185 static rtx aapcs_libcall_value (enum machine_mode);
186 static int aapcs_select_return_coproc (const_tree, const_tree);
188 #ifdef OBJECT_FORMAT_ELF
189 static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
190 static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
193 static void arm_encode_section_info (tree, rtx, int);
196 static void arm_file_end (void);
197 static void arm_file_start (void);
199 static void arm_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
201 static bool arm_pass_by_reference (cumulative_args_t,
202 enum machine_mode, const_tree, bool);
203 static bool arm_promote_prototypes (const_tree);
204 static bool arm_default_short_enums (void);
205 static bool arm_align_anon_bitfield (void);
206 static bool arm_return_in_msb (const_tree);
207 static bool arm_must_pass_in_stack (enum machine_mode, const_tree);
208 static bool arm_return_in_memory (const_tree, const_tree);
210 static void arm_unwind_emit (FILE *, rtx);
211 static bool arm_output_ttype (rtx);
212 static void arm_asm_emit_except_personality (rtx);
213 static void arm_asm_init_sections (void);
215 static rtx arm_dwarf_register_span (rtx);
217 static tree arm_cxx_guard_type (void);
218 static bool arm_cxx_guard_mask_bit (void);
219 static tree arm_get_cookie_size (tree);
220 static bool arm_cookie_has_size (void);
221 static bool arm_cxx_cdtor_returns_this (void);
222 static bool arm_cxx_key_method_may_be_inline (void);
223 static void arm_cxx_determine_class_data_visibility (tree);
224 static bool arm_cxx_class_data_always_comdat (void);
225 static bool arm_cxx_use_aeabi_atexit (void);
226 static void arm_init_libfuncs (void);
227 static tree arm_build_builtin_va_list (void);
228 static void arm_expand_builtin_va_start (tree, rtx);
229 static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
230 static void arm_option_override (void);
231 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
232 static bool arm_cannot_copy_insn_p (rtx);
233 static bool arm_tls_symbol_p (rtx x);
234 static int arm_issue_rate (void);
235 static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
236 static bool arm_output_addr_const_extra (FILE *, rtx);
237 static bool arm_allocate_stack_slots_for_args (void);
238 static bool arm_warn_func_return (tree);
239 static const char *arm_invalid_parameter_type (const_tree t);
240 static const char *arm_invalid_return_type (const_tree t);
241 static tree arm_promoted_type (const_tree t);
242 static tree arm_convert_to_type (tree type, tree expr);
243 static bool arm_scalar_mode_supported_p (enum machine_mode);
244 static bool arm_frame_pointer_required (void);
245 static bool arm_can_eliminate (const int, const int);
246 static void arm_asm_trampoline_template (FILE *);
247 static void arm_trampoline_init (rtx, tree, rtx);
248 static rtx arm_trampoline_adjust_address (rtx);
249 static rtx arm_pic_static_addr (rtx orig, rtx reg);
250 static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
251 static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
252 static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *);
253 static bool arm_array_mode_supported_p (enum machine_mode,
254 unsigned HOST_WIDE_INT);
255 static enum machine_mode arm_preferred_simd_mode (enum machine_mode);
256 static bool arm_class_likely_spilled_p (reg_class_t);
257 static HOST_WIDE_INT arm_vector_alignment (const_tree type);
258 static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
259 static bool arm_builtin_support_vector_misalignment (enum machine_mode mode,
263 static void arm_conditional_register_usage (void);
264 static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
265 static unsigned int arm_autovectorize_vector_sizes (void);
266 static int arm_default_branch_cost (bool, bool);
267 static int arm_cortex_a5_branch_cost (bool, bool);
269 static bool arm_vectorize_vec_perm_const_ok (enum machine_mode vmode,
270 const unsigned char *sel);
272 static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
274 int misalign ATTRIBUTE_UNUSED);
275 static unsigned arm_add_stmt_cost (void *data, int count,
276 enum vect_cost_for_stmt kind,
277 struct _stmt_vec_info *stmt_info,
279 enum vect_cost_model_location where);
281 static void arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
282 bool op0_preserve_value);
283 static unsigned HOST_WIDE_INT arm_asan_shadow_offset (void);
285 /* Table of machine attributes. */
286 static const struct attribute_spec arm_attribute_table[] =
288 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
289 affects_type_identity } */
290 /* Function calls made to this symbol must be done indirectly, because
291 it may lie outside of the 26 bit addressing range of a normal function
293 { "long_call", 0, 0, false, true, true, NULL, false },
294 /* Whereas these functions are always known to reside within the 26 bit
296 { "short_call", 0, 0, false, true, true, NULL, false },
297 /* Specify the procedure call conventions for a function. */
298 { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute,
300 /* Interrupt Service Routines have special prologue and epilogue requirements. */
301 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute,
303 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute,
305 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute,
308 /* ARM/PE has three new attributes:
310 dllexport - for exporting a function/variable that will live in a dll
311 dllimport - for importing a function/variable from a dll
313 Microsoft allows multiple declspecs in one __declspec, separating
314 them with spaces. We do NOT support this. Instead, use __declspec
317 { "dllimport", 0, 0, true, false, false, NULL, false },
318 { "dllexport", 0, 0, true, false, false, NULL, false },
319 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute,
321 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
322 { "dllimport", 0, 0, false, false, false, handle_dll_attribute, false },
323 { "dllexport", 0, 0, false, false, false, handle_dll_attribute, false },
324 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute,
327 { NULL, 0, 0, false, false, false, NULL, false }
330 /* Initialize the GCC target structure. */
331 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
332 #undef TARGET_MERGE_DECL_ATTRIBUTES
333 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
336 #undef TARGET_LEGITIMIZE_ADDRESS
337 #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address
339 #undef TARGET_ATTRIBUTE_TABLE
340 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
342 #undef TARGET_ASM_FILE_START
343 #define TARGET_ASM_FILE_START arm_file_start
344 #undef TARGET_ASM_FILE_END
345 #define TARGET_ASM_FILE_END arm_file_end
347 #undef TARGET_ASM_ALIGNED_SI_OP
348 #define TARGET_ASM_ALIGNED_SI_OP NULL
349 #undef TARGET_ASM_INTEGER
350 #define TARGET_ASM_INTEGER arm_assemble_integer
352 #undef TARGET_PRINT_OPERAND
353 #define TARGET_PRINT_OPERAND arm_print_operand
354 #undef TARGET_PRINT_OPERAND_ADDRESS
355 #define TARGET_PRINT_OPERAND_ADDRESS arm_print_operand_address
356 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
357 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P arm_print_operand_punct_valid_p
359 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
360 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA arm_output_addr_const_extra
362 #undef TARGET_ASM_FUNCTION_PROLOGUE
363 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
365 #undef TARGET_ASM_FUNCTION_EPILOGUE
366 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
368 #undef TARGET_OPTION_OVERRIDE
369 #define TARGET_OPTION_OVERRIDE arm_option_override
371 #undef TARGET_COMP_TYPE_ATTRIBUTES
372 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
374 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
375 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
377 #undef TARGET_SCHED_ADJUST_COST
378 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
380 #undef TARGET_SCHED_REORDER
381 #define TARGET_SCHED_REORDER arm_sched_reorder
383 #undef TARGET_REGISTER_MOVE_COST
384 #define TARGET_REGISTER_MOVE_COST arm_register_move_cost
386 #undef TARGET_MEMORY_MOVE_COST
387 #define TARGET_MEMORY_MOVE_COST arm_memory_move_cost
389 #undef TARGET_ENCODE_SECTION_INFO
391 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
393 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
396 #undef TARGET_STRIP_NAME_ENCODING
397 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
399 #undef TARGET_ASM_INTERNAL_LABEL
400 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
402 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
403 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
405 #undef TARGET_FUNCTION_VALUE
406 #define TARGET_FUNCTION_VALUE arm_function_value
408 #undef TARGET_LIBCALL_VALUE
409 #define TARGET_LIBCALL_VALUE arm_libcall_value
411 #undef TARGET_FUNCTION_VALUE_REGNO_P
412 #define TARGET_FUNCTION_VALUE_REGNO_P arm_function_value_regno_p
414 #undef TARGET_ASM_OUTPUT_MI_THUNK
415 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
416 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
417 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
419 #undef TARGET_RTX_COSTS
420 #define TARGET_RTX_COSTS arm_rtx_costs
421 #undef TARGET_ADDRESS_COST
422 #define TARGET_ADDRESS_COST arm_address_cost
424 #undef TARGET_SHIFT_TRUNCATION_MASK
425 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
426 #undef TARGET_VECTOR_MODE_SUPPORTED_P
427 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
428 #undef TARGET_ARRAY_MODE_SUPPORTED_P
429 #define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
430 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
431 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
432 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
433 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
434 arm_autovectorize_vector_sizes
436 #undef TARGET_MACHINE_DEPENDENT_REORG
437 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
439 #undef TARGET_INIT_BUILTINS
440 #define TARGET_INIT_BUILTINS arm_init_builtins
441 #undef TARGET_EXPAND_BUILTIN
442 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
443 #undef TARGET_BUILTIN_DECL
444 #define TARGET_BUILTIN_DECL arm_builtin_decl
446 #undef TARGET_INIT_LIBFUNCS
447 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
449 #undef TARGET_PROMOTE_FUNCTION_MODE
450 #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode
451 #undef TARGET_PROMOTE_PROTOTYPES
452 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
453 #undef TARGET_PASS_BY_REFERENCE
454 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
455 #undef TARGET_ARG_PARTIAL_BYTES
456 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
457 #undef TARGET_FUNCTION_ARG
458 #define TARGET_FUNCTION_ARG arm_function_arg
459 #undef TARGET_FUNCTION_ARG_ADVANCE
460 #define TARGET_FUNCTION_ARG_ADVANCE arm_function_arg_advance
461 #undef TARGET_FUNCTION_ARG_BOUNDARY
462 #define TARGET_FUNCTION_ARG_BOUNDARY arm_function_arg_boundary
464 #undef TARGET_SETUP_INCOMING_VARARGS
465 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
467 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
468 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
470 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
471 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template
472 #undef TARGET_TRAMPOLINE_INIT
473 #define TARGET_TRAMPOLINE_INIT arm_trampoline_init
474 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
475 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
477 #undef TARGET_WARN_FUNC_RETURN
478 #define TARGET_WARN_FUNC_RETURN arm_warn_func_return
480 #undef TARGET_DEFAULT_SHORT_ENUMS
481 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
483 #undef TARGET_ALIGN_ANON_BITFIELD
484 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
486 #undef TARGET_NARROW_VOLATILE_BITFIELD
487 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
489 #undef TARGET_CXX_GUARD_TYPE
490 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
492 #undef TARGET_CXX_GUARD_MASK_BIT
493 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
495 #undef TARGET_CXX_GET_COOKIE_SIZE
496 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
498 #undef TARGET_CXX_COOKIE_HAS_SIZE
499 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
501 #undef TARGET_CXX_CDTOR_RETURNS_THIS
502 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
504 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
505 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
507 #undef TARGET_CXX_USE_AEABI_ATEXIT
508 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
510 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
511 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
512 arm_cxx_determine_class_data_visibility
514 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
515 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
517 #undef TARGET_RETURN_IN_MSB
518 #define TARGET_RETURN_IN_MSB arm_return_in_msb
520 #undef TARGET_RETURN_IN_MEMORY
521 #define TARGET_RETURN_IN_MEMORY arm_return_in_memory
523 #undef TARGET_MUST_PASS_IN_STACK
524 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
527 #undef TARGET_ASM_UNWIND_EMIT
528 #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit
530 /* EABI unwinding tables use a different format for the typeinfo tables. */
531 #undef TARGET_ASM_TTYPE
532 #define TARGET_ASM_TTYPE arm_output_ttype
534 #undef TARGET_ARM_EABI_UNWINDER
535 #define TARGET_ARM_EABI_UNWINDER true
537 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
538 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
540 #undef TARGET_ASM_INIT_SECTIONS
541 #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
542 #endif /* ARM_UNWIND_INFO */
544 #undef TARGET_DWARF_REGISTER_SPAN
545 #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
547 #undef TARGET_CANNOT_COPY_INSN_P
548 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
551 #undef TARGET_HAVE_TLS
552 #define TARGET_HAVE_TLS true
555 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
556 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
558 #undef TARGET_LEGITIMATE_CONSTANT_P
559 #define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
561 #undef TARGET_CANNOT_FORCE_CONST_MEM
562 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
564 #undef TARGET_MAX_ANCHOR_OFFSET
565 #define TARGET_MAX_ANCHOR_OFFSET 4095
567 /* The minimum is set such that the total size of the block
568 for a particular anchor is -4088 + 1 + 4095 bytes, which is
569 divisible by eight, ensuring natural spacing of anchors. */
570 #undef TARGET_MIN_ANCHOR_OFFSET
571 #define TARGET_MIN_ANCHOR_OFFSET -4088
573 #undef TARGET_SCHED_ISSUE_RATE
574 #define TARGET_SCHED_ISSUE_RATE arm_issue_rate
576 #undef TARGET_MANGLE_TYPE
577 #define TARGET_MANGLE_TYPE arm_mangle_type
579 #undef TARGET_BUILD_BUILTIN_VA_LIST
580 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
581 #undef TARGET_EXPAND_BUILTIN_VA_START
582 #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start
583 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
584 #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr
587 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
588 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
591 #undef TARGET_LEGITIMATE_ADDRESS_P
592 #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p
594 #undef TARGET_PREFERRED_RELOAD_CLASS
595 #define TARGET_PREFERRED_RELOAD_CLASS arm_preferred_reload_class
597 #undef TARGET_INVALID_PARAMETER_TYPE
598 #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
600 #undef TARGET_INVALID_RETURN_TYPE
601 #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
603 #undef TARGET_PROMOTED_TYPE
604 #define TARGET_PROMOTED_TYPE arm_promoted_type
606 #undef TARGET_CONVERT_TO_TYPE
607 #define TARGET_CONVERT_TO_TYPE arm_convert_to_type
609 #undef TARGET_SCALAR_MODE_SUPPORTED_P
610 #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p
612 #undef TARGET_FRAME_POINTER_REQUIRED
613 #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required
615 #undef TARGET_CAN_ELIMINATE
616 #define TARGET_CAN_ELIMINATE arm_can_eliminate
618 #undef TARGET_CONDITIONAL_REGISTER_USAGE
619 #define TARGET_CONDITIONAL_REGISTER_USAGE arm_conditional_register_usage
621 #undef TARGET_CLASS_LIKELY_SPILLED_P
622 #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p
624 #undef TARGET_VECTOR_ALIGNMENT
625 #define TARGET_VECTOR_ALIGNMENT arm_vector_alignment
627 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
628 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
629 arm_vector_alignment_reachable
631 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
632 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
633 arm_builtin_support_vector_misalignment
635 #undef TARGET_PREFERRED_RENAME_CLASS
636 #define TARGET_PREFERRED_RENAME_CLASS \
637 arm_preferred_rename_class
639 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
640 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
641 arm_vectorize_vec_perm_const_ok
643 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
644 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
645 arm_builtin_vectorization_cost
646 #undef TARGET_VECTORIZE_ADD_STMT_COST
647 #define TARGET_VECTORIZE_ADD_STMT_COST arm_add_stmt_cost
649 #undef TARGET_CANONICALIZE_COMPARISON
650 #define TARGET_CANONICALIZE_COMPARISON \
651 arm_canonicalize_comparison
653 #undef TARGET_ASAN_SHADOW_OFFSET
654 #define TARGET_ASAN_SHADOW_OFFSET arm_asan_shadow_offset
656 struct gcc_target targetm = TARGET_INITIALIZER;
658 /* Obstack for minipool constant handling. */
659 static struct obstack minipool_obstack;
660 static char * minipool_startobj;
662 /* The maximum number of insns skipped which
663 will be conditionalised if possible. */
664 static int max_insns_skipped = 5;
666 extern FILE * asm_out_file;
668 /* True if we are currently building a constant table. */
669 int making_const_table;
671 /* The processor for which instructions should be scheduled. */
672 enum processor_type arm_tune = arm_none;
674 /* The current tuning set. */
675 const struct tune_params *current_tune;
677 /* Which floating point hardware to schedule for. */
680 /* Which floating popint hardware to use. */
681 const struct arm_fpu_desc *arm_fpu_desc;
683 /* Used for Thumb call_via trampolines. */
684 rtx thumb_call_via_label[14];
685 static int thumb_call_reg_needed;
687 /* Bit values used to identify processor capabilities. */
688 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
689 #define FL_ARCH3M (1 << 1) /* Extended multiply */
690 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
691 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
692 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
693 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
694 #define FL_THUMB (1 << 6) /* Thumb aware */
695 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
696 #define FL_STRONG (1 << 8) /* StrongARM */
697 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
698 #define FL_XSCALE (1 << 10) /* XScale */
699 /* spare (1 << 11) */
700 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
701 media instructions. */
702 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
703 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
704 Note: ARM6 & 7 derivatives only. */
705 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
706 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
707 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
709 #define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
710 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
711 #define FL_NEON (1 << 20) /* Neon instructions. */
712 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
714 #define FL_ARCH7 (1 << 22) /* Architecture 7. */
715 #define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
716 #define FL_ARCH8 (1 << 24) /* Architecture 8. */
718 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
719 #define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
721 /* Flags that only effect tuning, not available instructions. */
722 #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
725 #define FL_FOR_ARCH2 FL_NOTM
726 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
727 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
728 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
729 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
730 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
731 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
732 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
733 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
734 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
735 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
736 #define FL_FOR_ARCH6J FL_FOR_ARCH6
737 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
738 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
739 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
740 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
741 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
742 #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
743 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
744 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
745 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
746 #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
747 #define FL_FOR_ARCH8A (FL_FOR_ARCH7 | FL_ARCH6K | FL_ARCH8 | FL_THUMB_DIV \
748 | FL_ARM_DIV | FL_NOTM)
750 /* The bits in this mask specify which
751 instructions we are allowed to generate. */
752 static unsigned long insn_flags = 0;
754 /* The bits in this mask specify which instruction scheduling options should
756 static unsigned long tune_flags = 0;
758 /* The highest ARM architecture version supported by the
760 enum base_architecture arm_base_arch = BASE_ARCH_0;
762 /* The following are used in the arm.md file as equivalents to bits
763 in the above two flag variables. */
765 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
768 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
771 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
774 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
777 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
780 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
783 /* Nonzero if this chip supports the ARM 6K extensions. */
786 /* Nonzero if instructions present in ARMv6-M can be used. */
789 /* Nonzero if this chip supports the ARM 7 extensions. */
792 /* Nonzero if instructions not present in the 'M' profile can be used. */
793 int arm_arch_notm = 0;
795 /* Nonzero if instructions present in ARMv7E-M can be used. */
798 /* Nonzero if instructions present in ARMv8 can be used. */
801 /* Nonzero if this chip can benefit from load scheduling. */
802 int arm_ld_sched = 0;
804 /* Nonzero if this chip is a StrongARM. */
805 int arm_tune_strongarm = 0;
807 /* Nonzero if this chip supports Intel Wireless MMX technology. */
808 int arm_arch_iwmmxt = 0;
810 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
811 int arm_arch_iwmmxt2 = 0;
813 /* Nonzero if this chip is an XScale. */
814 int arm_arch_xscale = 0;
816 /* Nonzero if tuning for XScale */
817 int arm_tune_xscale = 0;
819 /* Nonzero if we want to tune for stores that access the write-buffer.
820 This typically means an ARM6 or ARM7 with MMU or MPU. */
821 int arm_tune_wbuf = 0;
823 /* Nonzero if tuning for Cortex-A9. */
824 int arm_tune_cortex_a9 = 0;
826 /* Nonzero if generating Thumb instructions. */
829 /* Nonzero if generating Thumb-1 instructions. */
832 /* Nonzero if we should define __THUMB_INTERWORK__ in the
834 XXX This is a bit of a hack, it's intended to help work around
835 problems in GLD which doesn't understand that armv5t code is
836 interworking clean. */
837 int arm_cpp_interwork = 0;
839 /* Nonzero if chip supports Thumb 2. */
842 /* Nonzero if chip supports integer division instruction. */
843 int arm_arch_arm_hwdiv;
844 int arm_arch_thumb_hwdiv;
846 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
847 we must report the mode of the memory reference from
848 TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */
849 enum machine_mode output_memory_reference_mode;
851 /* The register number to be used for the PIC offset register. */
852 unsigned arm_pic_register = INVALID_REGNUM;
854 /* Set to 1 after arm_reorg has started. Reset to start at the start of
855 the next function. */
856 static int after_arm_reorg = 0;
858 enum arm_pcs arm_pcs_default;
860 /* For an explanation of these variables, see final_prescan_insn below. */
862 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
863 enum arm_cond_code arm_current_cc;
866 int arm_target_label;
867 /* The number of conditionally executed insns, including the current insn. */
868 int arm_condexec_count = 0;
869 /* A bitmask specifying the patterns for the IT block.
870 Zero means do not output an IT block before this insn. */
871 int arm_condexec_mask = 0;
872 /* The number of bits used in arm_condexec_mask. */
873 int arm_condexec_masklen = 0;
875 /* The condition codes of the ARM, and the inverse function. */
876 static const char * const arm_condition_codes[] =
878 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
879 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
882 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
883 int arm_regs_in_sequence[] =
885 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
888 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
889 #define streq(string1, string2) (strcmp (string1, string2) == 0)
891 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
892 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
893 | (1 << PIC_OFFSET_TABLE_REGNUM)))
895 /* Initialization code. */
899 const char *const name;
900 enum processor_type core;
902 enum base_architecture base_arch;
903 const unsigned long flags;
904 const struct tune_params *const tune;
908 #define ARM_PREFETCH_NOT_BENEFICIAL 0, -1, -1
909 #define ARM_PREFETCH_BENEFICIAL(prefetch_slots,l1_size,l1_line_size) \
914 /* arm generic vectorizer costs. */
916 struct cpu_vec_costs arm_default_vec_cost = {
917 1, /* scalar_stmt_cost. */
918 1, /* scalar load_cost. */
919 1, /* scalar_store_cost. */
920 1, /* vec_stmt_cost. */
921 1, /* vec_to_scalar_cost. */
922 1, /* scalar_to_vec_cost. */
923 1, /* vec_align_load_cost. */
924 1, /* vec_unalign_load_cost. */
925 1, /* vec_unalign_store_cost. */
926 1, /* vec_store_cost. */
927 3, /* cond_taken_branch_cost. */
928 1, /* cond_not_taken_branch_cost. */
931 const struct tune_params arm_slowmul_tune =
933 arm_slowmul_rtx_costs,
935 3, /* Constant limit. */
936 5, /* Max cond insns. */
937 ARM_PREFETCH_NOT_BENEFICIAL,
938 true, /* Prefer constant pool. */
939 arm_default_branch_cost,
940 false, /* Prefer LDRD/STRD. */
941 {true, true}, /* Prefer non short circuit. */
942 &arm_default_vec_cost, /* Vectorizer costs. */
945 const struct tune_params arm_fastmul_tune =
947 arm_fastmul_rtx_costs,
949 1, /* Constant limit. */
950 5, /* Max cond insns. */
951 ARM_PREFETCH_NOT_BENEFICIAL,
952 true, /* Prefer constant pool. */
953 arm_default_branch_cost,
954 false, /* Prefer LDRD/STRD. */
955 {true, true}, /* Prefer non short circuit. */
956 &arm_default_vec_cost, /* Vectorizer costs. */
959 /* StrongARM has early execution of branches, so a sequence that is worth
960 skipping is shorter. Set max_insns_skipped to a lower value. */
962 const struct tune_params arm_strongarm_tune =
964 arm_fastmul_rtx_costs,
966 1, /* Constant limit. */
967 3, /* Max cond insns. */
968 ARM_PREFETCH_NOT_BENEFICIAL,
969 true, /* Prefer constant pool. */
970 arm_default_branch_cost,
971 false, /* Prefer LDRD/STRD. */
972 {true, true}, /* Prefer non short circuit. */
973 &arm_default_vec_cost, /* Vectorizer costs. */
976 const struct tune_params arm_xscale_tune =
978 arm_xscale_rtx_costs,
979 xscale_sched_adjust_cost,
980 2, /* Constant limit. */
981 3, /* Max cond insns. */
982 ARM_PREFETCH_NOT_BENEFICIAL,
983 true, /* Prefer constant pool. */
984 arm_default_branch_cost,
985 false, /* Prefer LDRD/STRD. */
986 {true, true}, /* Prefer non short circuit. */
987 &arm_default_vec_cost, /* Vectorizer costs. */
990 const struct tune_params arm_9e_tune =
994 1, /* Constant limit. */
995 5, /* Max cond insns. */
996 ARM_PREFETCH_NOT_BENEFICIAL,
997 true, /* Prefer constant pool. */
998 arm_default_branch_cost,
999 false, /* Prefer LDRD/STRD. */
1000 {true, true}, /* Prefer non short circuit. */
1001 &arm_default_vec_cost, /* Vectorizer costs. */
1004 const struct tune_params arm_v6t2_tune =
1008 1, /* Constant limit. */
1009 5, /* Max cond insns. */
1010 ARM_PREFETCH_NOT_BENEFICIAL,
1011 false, /* Prefer constant pool. */
1012 arm_default_branch_cost,
1013 false, /* Prefer LDRD/STRD. */
1014 {true, true}, /* Prefer non short circuit. */
1015 &arm_default_vec_cost, /* Vectorizer costs. */
1018 /* Generic Cortex tuning. Use more specific tunings if appropriate. */
1019 const struct tune_params arm_cortex_tune =
1023 1, /* Constant limit. */
1024 5, /* Max cond insns. */
1025 ARM_PREFETCH_NOT_BENEFICIAL,
1026 false, /* Prefer constant pool. */
1027 arm_default_branch_cost,
1028 false, /* Prefer LDRD/STRD. */
1029 {true, true}, /* Prefer non short circuit. */
1030 &arm_default_vec_cost, /* Vectorizer costs. */
1033 const struct tune_params arm_cortex_a15_tune =
1037 1, /* Constant limit. */
1038 5, /* Max cond insns. */
1039 ARM_PREFETCH_NOT_BENEFICIAL,
1040 false, /* Prefer constant pool. */
1041 arm_default_branch_cost,
1042 true, /* Prefer LDRD/STRD. */
1043 {true, true}, /* Prefer non short circuit. */
1044 &arm_default_vec_cost, /* Vectorizer costs. */
1047 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
1048 less appealing. Set max_insns_skipped to a low value. */
1050 const struct tune_params arm_cortex_a5_tune =
1054 1, /* Constant limit. */
1055 1, /* Max cond insns. */
1056 ARM_PREFETCH_NOT_BENEFICIAL,
1057 false, /* Prefer constant pool. */
1058 arm_cortex_a5_branch_cost,
1059 false, /* Prefer LDRD/STRD. */
1060 {false, false}, /* Prefer non short circuit. */
1061 &arm_default_vec_cost, /* Vectorizer costs. */
1064 const struct tune_params arm_cortex_a9_tune =
1067 cortex_a9_sched_adjust_cost,
1068 1, /* Constant limit. */
1069 5, /* Max cond insns. */
1070 ARM_PREFETCH_BENEFICIAL(4,32,32),
1071 false, /* Prefer constant pool. */
1072 arm_default_branch_cost,
1073 false, /* Prefer LDRD/STRD. */
1074 {true, true}, /* Prefer non short circuit. */
1075 &arm_default_vec_cost, /* Vectorizer costs. */
1078 /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
1079 arm_v6t2_tune. It is used for cortex-m0, cortex-m1 and cortex-m0plus. */
1080 const struct tune_params arm_v6m_tune =
1084 1, /* Constant limit. */
1085 5, /* Max cond insns. */
1086 ARM_PREFETCH_NOT_BENEFICIAL,
1087 false, /* Prefer constant pool. */
1088 arm_default_branch_cost,
1089 false, /* Prefer LDRD/STRD. */
1090 {false, false}, /* Prefer non short circuit. */
1091 &arm_default_vec_cost, /* Vectorizer costs. */
1094 const struct tune_params arm_fa726te_tune =
1097 fa726te_sched_adjust_cost,
1098 1, /* Constant limit. */
1099 5, /* Max cond insns. */
1100 ARM_PREFETCH_NOT_BENEFICIAL,
1101 true, /* Prefer constant pool. */
1102 arm_default_branch_cost,
1103 false, /* Prefer LDRD/STRD. */
1104 {true, true}, /* Prefer non short circuit. */
1105 &arm_default_vec_cost, /* Vectorizer costs. */
1109 /* Not all of these give usefully different compilation alternatives,
1110 but there is no simple way of generalizing them. */
1111 static const struct processors all_cores[] =
1114 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
1115 {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH, \
1116 FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
1117 #include "arm-cores.def"
1119 {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
1122 static const struct processors all_architectures[] =
1124 /* ARM Architectures */
1125 /* We don't specify tuning costs here as it will be figured out
1128 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
1129 {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
1130 #include "arm-arches.def"
1132 {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
1136 /* These are populated as commandline arguments are processed, or NULL
1137 if not specified. */
1138 static const struct processors *arm_selected_arch;
1139 static const struct processors *arm_selected_cpu;
1140 static const struct processors *arm_selected_tune;
1142 /* The name of the preprocessor macro to define for this architecture. */
1144 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
1146 /* Available values for -mfpu=. */
1148 static const struct arm_fpu_desc all_fpus[] =
1150 #define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO) \
1151 { NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO },
1152 #include "arm-fpus.def"
1157 /* Supported TLS relocations. */
1165 TLS_DESCSEQ /* GNU scheme */
1168 /* The maximum number of insns to be used when loading a constant. */
1170 arm_constant_limit (bool size_p)
1172 return size_p ? 1 : current_tune->constant_limit;
1175 /* Emit an insn that's a simple single-set. Both the operands must be known
1178 emit_set_insn (rtx x, rtx y)
1180 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
1183 /* Return the number of bits set in VALUE. */
1185 bit_count (unsigned long value)
1187 unsigned long count = 0;
1192 value &= value - 1; /* Clear the least-significant set bit. */
1200 enum machine_mode mode;
1202 } arm_fixed_mode_set;
1204 /* A small helper for setting fixed-point library libfuncs. */
1207 arm_set_fixed_optab_libfunc (optab optable, enum machine_mode mode,
1208 const char *funcname, const char *modename,
1213 if (num_suffix == 0)
1214 sprintf (buffer, "__gnu_%s%s", funcname, modename);
1216 sprintf (buffer, "__gnu_%s%s%d", funcname, modename, num_suffix);
1218 set_optab_libfunc (optable, mode, buffer);
1222 arm_set_fixed_conv_libfunc (convert_optab optable, enum machine_mode to,
1223 enum machine_mode from, const char *funcname,
1224 const char *toname, const char *fromname)
1227 const char *maybe_suffix_2 = "";
1229 /* Follow the logic for selecting a "2" suffix in fixed-bit.h. */
1230 if (ALL_FIXED_POINT_MODE_P (from) && ALL_FIXED_POINT_MODE_P (to)
1231 && UNSIGNED_FIXED_POINT_MODE_P (from) == UNSIGNED_FIXED_POINT_MODE_P (to)
1232 && ALL_FRACT_MODE_P (from) == ALL_FRACT_MODE_P (to))
1233 maybe_suffix_2 = "2";
1235 sprintf (buffer, "__gnu_%s%s%s%s", funcname, fromname, toname,
1238 set_conv_libfunc (optable, to, from, buffer);
1241 /* Set up library functions unique to ARM. */
1244 arm_init_libfuncs (void)
1246 /* For Linux, we have access to kernel support for atomic operations. */
1247 if (arm_abi == ARM_ABI_AAPCS_LINUX)
1248 init_sync_libfuncs (2 * UNITS_PER_WORD);
1250 /* There are no special library functions unless we are using the
1255 /* The functions below are described in Section 4 of the "Run-Time
1256 ABI for the ARM architecture", Version 1.0. */
1258 /* Double-precision floating-point arithmetic. Table 2. */
1259 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
1260 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
1261 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
1262 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
1263 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
1265 /* Double-precision comparisons. Table 3. */
1266 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
1267 set_optab_libfunc (ne_optab, DFmode, NULL);
1268 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
1269 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
1270 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
1271 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
1272 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
1274 /* Single-precision floating-point arithmetic. Table 4. */
1275 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
1276 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
1277 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
1278 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
1279 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
1281 /* Single-precision comparisons. Table 5. */
1282 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
1283 set_optab_libfunc (ne_optab, SFmode, NULL);
1284 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
1285 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
1286 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
1287 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
1288 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
1290 /* Floating-point to integer conversions. Table 6. */
1291 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
1292 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
1293 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
1294 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
1295 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
1296 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
1297 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
1298 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
1300 /* Conversions between floating types. Table 7. */
1301 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
1302 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
1304 /* Integer to floating-point conversions. Table 8. */
1305 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
1306 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
1307 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
1308 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
1309 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
1310 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
1311 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
1312 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
1314 /* Long long. Table 9. */
1315 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
1316 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
1317 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
1318 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
1319 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
1320 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
1321 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
1322 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
1324 /* Integer (32/32->32) division. \S 4.3.1. */
1325 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
1326 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
1328 /* The divmod functions are designed so that they can be used for
1329 plain division, even though they return both the quotient and the
1330 remainder. The quotient is returned in the usual location (i.e.,
1331 r0 for SImode, {r0, r1} for DImode), just as would be expected
1332 for an ordinary division routine. Because the AAPCS calling
1333 conventions specify that all of { r0, r1, r2, r3 } are
1334 callee-saved registers, there is no need to tell the compiler
1335 explicitly that those registers are clobbered by these
1337 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
1338 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
1340 /* For SImode division the ABI provides div-without-mod routines,
1341 which are faster. */
1342 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
1343 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
1345 /* We don't have mod libcalls. Fortunately gcc knows how to use the
1346 divmod libcalls instead. */
1347 set_optab_libfunc (smod_optab, DImode, NULL);
1348 set_optab_libfunc (umod_optab, DImode, NULL);
1349 set_optab_libfunc (smod_optab, SImode, NULL);
1350 set_optab_libfunc (umod_optab, SImode, NULL);
1352 /* Half-precision float operations. The compiler handles all operations
1353 with NULL libfuncs by converting the SFmode. */
1354 switch (arm_fp16_format)
1356 case ARM_FP16_FORMAT_IEEE:
1357 case ARM_FP16_FORMAT_ALTERNATIVE:
1360 set_conv_libfunc (trunc_optab, HFmode, SFmode,
1361 (arm_fp16_format == ARM_FP16_FORMAT_IEEE
1363 : "__gnu_f2h_alternative"));
1364 set_conv_libfunc (sext_optab, SFmode, HFmode,
1365 (arm_fp16_format == ARM_FP16_FORMAT_IEEE
1367 : "__gnu_h2f_alternative"));
1370 set_optab_libfunc (add_optab, HFmode, NULL);
1371 set_optab_libfunc (sdiv_optab, HFmode, NULL);
1372 set_optab_libfunc (smul_optab, HFmode, NULL);
1373 set_optab_libfunc (neg_optab, HFmode, NULL);
1374 set_optab_libfunc (sub_optab, HFmode, NULL);
1377 set_optab_libfunc (eq_optab, HFmode, NULL);
1378 set_optab_libfunc (ne_optab, HFmode, NULL);
1379 set_optab_libfunc (lt_optab, HFmode, NULL);
1380 set_optab_libfunc (le_optab, HFmode, NULL);
1381 set_optab_libfunc (ge_optab, HFmode, NULL);
1382 set_optab_libfunc (gt_optab, HFmode, NULL);
1383 set_optab_libfunc (unord_optab, HFmode, NULL);
1390 /* Use names prefixed with __gnu_ for fixed-point helper functions. */
1392 const arm_fixed_mode_set fixed_arith_modes[] =
1413 const arm_fixed_mode_set fixed_conv_modes[] =
1443 for (i = 0; i < ARRAY_SIZE (fixed_arith_modes); i++)
1445 arm_set_fixed_optab_libfunc (add_optab, fixed_arith_modes[i].mode,
1446 "add", fixed_arith_modes[i].name, 3);
1447 arm_set_fixed_optab_libfunc (ssadd_optab, fixed_arith_modes[i].mode,
1448 "ssadd", fixed_arith_modes[i].name, 3);
1449 arm_set_fixed_optab_libfunc (usadd_optab, fixed_arith_modes[i].mode,
1450 "usadd", fixed_arith_modes[i].name, 3);
1451 arm_set_fixed_optab_libfunc (sub_optab, fixed_arith_modes[i].mode,
1452 "sub", fixed_arith_modes[i].name, 3);
1453 arm_set_fixed_optab_libfunc (sssub_optab, fixed_arith_modes[i].mode,
1454 "sssub", fixed_arith_modes[i].name, 3);
1455 arm_set_fixed_optab_libfunc (ussub_optab, fixed_arith_modes[i].mode,
1456 "ussub", fixed_arith_modes[i].name, 3);
1457 arm_set_fixed_optab_libfunc (smul_optab, fixed_arith_modes[i].mode,
1458 "mul", fixed_arith_modes[i].name, 3);
1459 arm_set_fixed_optab_libfunc (ssmul_optab, fixed_arith_modes[i].mode,
1460 "ssmul", fixed_arith_modes[i].name, 3);
1461 arm_set_fixed_optab_libfunc (usmul_optab, fixed_arith_modes[i].mode,
1462 "usmul", fixed_arith_modes[i].name, 3);
1463 arm_set_fixed_optab_libfunc (sdiv_optab, fixed_arith_modes[i].mode,
1464 "div", fixed_arith_modes[i].name, 3);
1465 arm_set_fixed_optab_libfunc (udiv_optab, fixed_arith_modes[i].mode,
1466 "udiv", fixed_arith_modes[i].name, 3);
1467 arm_set_fixed_optab_libfunc (ssdiv_optab, fixed_arith_modes[i].mode,
1468 "ssdiv", fixed_arith_modes[i].name, 3);
1469 arm_set_fixed_optab_libfunc (usdiv_optab, fixed_arith_modes[i].mode,
1470 "usdiv", fixed_arith_modes[i].name, 3);
1471 arm_set_fixed_optab_libfunc (neg_optab, fixed_arith_modes[i].mode,
1472 "neg", fixed_arith_modes[i].name, 2);
1473 arm_set_fixed_optab_libfunc (ssneg_optab, fixed_arith_modes[i].mode,
1474 "ssneg", fixed_arith_modes[i].name, 2);
1475 arm_set_fixed_optab_libfunc (usneg_optab, fixed_arith_modes[i].mode,
1476 "usneg", fixed_arith_modes[i].name, 2);
1477 arm_set_fixed_optab_libfunc (ashl_optab, fixed_arith_modes[i].mode,
1478 "ashl", fixed_arith_modes[i].name, 3);
1479 arm_set_fixed_optab_libfunc (ashr_optab, fixed_arith_modes[i].mode,
1480 "ashr", fixed_arith_modes[i].name, 3);
1481 arm_set_fixed_optab_libfunc (lshr_optab, fixed_arith_modes[i].mode,
1482 "lshr", fixed_arith_modes[i].name, 3);
1483 arm_set_fixed_optab_libfunc (ssashl_optab, fixed_arith_modes[i].mode,
1484 "ssashl", fixed_arith_modes[i].name, 3);
1485 arm_set_fixed_optab_libfunc (usashl_optab, fixed_arith_modes[i].mode,
1486 "usashl", fixed_arith_modes[i].name, 3);
1487 arm_set_fixed_optab_libfunc (cmp_optab, fixed_arith_modes[i].mode,
1488 "cmp", fixed_arith_modes[i].name, 2);
1491 for (i = 0; i < ARRAY_SIZE (fixed_conv_modes); i++)
1492 for (j = 0; j < ARRAY_SIZE (fixed_conv_modes); j++)
1495 || (!ALL_FIXED_POINT_MODE_P (fixed_conv_modes[i].mode)
1496 && !ALL_FIXED_POINT_MODE_P (fixed_conv_modes[j].mode)))
1499 arm_set_fixed_conv_libfunc (fract_optab, fixed_conv_modes[i].mode,
1500 fixed_conv_modes[j].mode, "fract",
1501 fixed_conv_modes[i].name,
1502 fixed_conv_modes[j].name);
1503 arm_set_fixed_conv_libfunc (satfract_optab,
1504 fixed_conv_modes[i].mode,
1505 fixed_conv_modes[j].mode, "satfract",
1506 fixed_conv_modes[i].name,
1507 fixed_conv_modes[j].name);
1508 arm_set_fixed_conv_libfunc (fractuns_optab,
1509 fixed_conv_modes[i].mode,
1510 fixed_conv_modes[j].mode, "fractuns",
1511 fixed_conv_modes[i].name,
1512 fixed_conv_modes[j].name);
1513 arm_set_fixed_conv_libfunc (satfractuns_optab,
1514 fixed_conv_modes[i].mode,
1515 fixed_conv_modes[j].mode, "satfractuns",
1516 fixed_conv_modes[i].name,
1517 fixed_conv_modes[j].name);
1521 if (TARGET_AAPCS_BASED)
1522 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
1525 /* On AAPCS systems, this is the "struct __va_list". */
1526 static GTY(()) tree va_list_type;
1528 /* Return the type to use as __builtin_va_list. */
1530 arm_build_builtin_va_list (void)
1535 if (!TARGET_AAPCS_BASED)
1536 return std_build_builtin_va_list ();
1538 /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type
1546 The C Library ABI further reinforces this definition in \S
1549 We must follow this definition exactly. The structure tag
1550 name is visible in C++ mangled names, and thus forms a part
1551 of the ABI. The field name may be used by people who
1552 #include <stdarg.h>. */
1553 /* Create the type. */
1554 va_list_type = lang_hooks.types.make_type (RECORD_TYPE);
1555 /* Give it the required name. */
1556 va_list_name = build_decl (BUILTINS_LOCATION,
1558 get_identifier ("__va_list"),
1560 DECL_ARTIFICIAL (va_list_name) = 1;
1561 TYPE_NAME (va_list_type) = va_list_name;
1562 TYPE_STUB_DECL (va_list_type) = va_list_name;
1563 /* Create the __ap field. */
1564 ap_field = build_decl (BUILTINS_LOCATION,
1566 get_identifier ("__ap"),
1568 DECL_ARTIFICIAL (ap_field) = 1;
1569 DECL_FIELD_CONTEXT (ap_field) = va_list_type;
1570 TYPE_FIELDS (va_list_type) = ap_field;
1571 /* Compute its layout. */
1572 layout_type (va_list_type);
1574 return va_list_type;
1577 /* Return an expression of type "void *" pointing to the next
1578 available argument in a variable-argument list. VALIST is the
1579 user-level va_list object, of type __builtin_va_list. */
1581 arm_extract_valist_ptr (tree valist)
1583 if (TREE_TYPE (valist) == error_mark_node)
1584 return error_mark_node;
1586 /* On an AAPCS target, the pointer is stored within "struct
1588 if (TARGET_AAPCS_BASED)
1590 tree ap_field = TYPE_FIELDS (TREE_TYPE (valist));
1591 valist = build3 (COMPONENT_REF, TREE_TYPE (ap_field),
1592 valist, ap_field, NULL_TREE);
1598 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
1600 arm_expand_builtin_va_start (tree valist, rtx nextarg)
1602 valist = arm_extract_valist_ptr (valist);
1603 std_expand_builtin_va_start (valist, nextarg);
1606 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
1608 arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
1611 valist = arm_extract_valist_ptr (valist);
1612 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
1615 /* Fix up any incompatible options that the user has specified. */
1617 arm_option_override (void)
1619 if (global_options_set.x_arm_arch_option)
1620 arm_selected_arch = &all_architectures[arm_arch_option];
1622 if (global_options_set.x_arm_cpu_option)
1623 arm_selected_cpu = &all_cores[(int) arm_cpu_option];
1625 if (global_options_set.x_arm_tune_option)
1626 arm_selected_tune = &all_cores[(int) arm_tune_option];
1628 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1629 SUBTARGET_OVERRIDE_OPTIONS;
1632 if (arm_selected_arch)
1634 if (arm_selected_cpu)
1636 /* Check for conflict between mcpu and march. */
1637 if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE)
1639 warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
1640 arm_selected_cpu->name, arm_selected_arch->name);
1641 /* -march wins for code generation.
1642 -mcpu wins for default tuning. */
1643 if (!arm_selected_tune)
1644 arm_selected_tune = arm_selected_cpu;
1646 arm_selected_cpu = arm_selected_arch;
1650 arm_selected_arch = NULL;
1653 /* Pick a CPU based on the architecture. */
1654 arm_selected_cpu = arm_selected_arch;
1657 /* If the user did not specify a processor, choose one for them. */
1658 if (!arm_selected_cpu)
1660 const struct processors * sel;
1661 unsigned int sought;
1663 arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT];
1664 if (!arm_selected_cpu->name)
1666 #ifdef SUBTARGET_CPU_DEFAULT
1667 /* Use the subtarget default CPU if none was specified by
1669 arm_selected_cpu = &all_cores[SUBTARGET_CPU_DEFAULT];
1671 /* Default to ARM6. */
1672 if (!arm_selected_cpu->name)
1673 arm_selected_cpu = &all_cores[arm6];
1676 sel = arm_selected_cpu;
1677 insn_flags = sel->flags;
1679 /* Now check to see if the user has specified some command line
1680 switch that require certain abilities from the cpu. */
1683 if (TARGET_INTERWORK || TARGET_THUMB)
1685 sought |= (FL_THUMB | FL_MODE32);
1687 /* There are no ARM processors that support both APCS-26 and
1688 interworking. Therefore we force FL_MODE26 to be removed
1689 from insn_flags here (if it was set), so that the search
1690 below will always be able to find a compatible processor. */
1691 insn_flags &= ~FL_MODE26;
1694 if (sought != 0 && ((sought & insn_flags) != sought))
1696 /* Try to locate a CPU type that supports all of the abilities
1697 of the default CPU, plus the extra abilities requested by
1699 for (sel = all_cores; sel->name != NULL; sel++)
1700 if ((sel->flags & sought) == (sought | insn_flags))
1703 if (sel->name == NULL)
1705 unsigned current_bit_count = 0;
1706 const struct processors * best_fit = NULL;
1708 /* Ideally we would like to issue an error message here
1709 saying that it was not possible to find a CPU compatible
1710 with the default CPU, but which also supports the command
1711 line options specified by the programmer, and so they
1712 ought to use the -mcpu=<name> command line option to
1713 override the default CPU type.
1715 If we cannot find a cpu that has both the
1716 characteristics of the default cpu and the given
1717 command line options we scan the array again looking
1718 for a best match. */
1719 for (sel = all_cores; sel->name != NULL; sel++)
1720 if ((sel->flags & sought) == sought)
1724 count = bit_count (sel->flags & insn_flags);
1726 if (count >= current_bit_count)
1729 current_bit_count = count;
1733 gcc_assert (best_fit);
1737 arm_selected_cpu = sel;
1741 gcc_assert (arm_selected_cpu);
1742 /* The selected cpu may be an architecture, so lookup tuning by core ID. */
1743 if (!arm_selected_tune)
1744 arm_selected_tune = &all_cores[arm_selected_cpu->core];
1746 sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch);
1747 insn_flags = arm_selected_cpu->flags;
1748 arm_base_arch = arm_selected_cpu->base_arch;
1750 arm_tune = arm_selected_tune->core;
1751 tune_flags = arm_selected_tune->flags;
1752 current_tune = arm_selected_tune->tune;
1754 /* Make sure that the processor choice does not conflict with any of the
1755 other command line choices. */
1756 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1757 error ("target CPU does not support ARM mode");
1759 /* BPABI targets use linker tricks to allow interworking on cores
1760 without thumb support. */
1761 if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI))
1763 warning (0, "target CPU does not support interworking" );
1764 target_flags &= ~MASK_INTERWORK;
1767 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1769 warning (0, "target CPU does not support THUMB instructions");
1770 target_flags &= ~MASK_THUMB;
1773 if (TARGET_APCS_FRAME && TARGET_THUMB)
1775 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1776 target_flags &= ~MASK_APCS_FRAME;
1779 /* Callee super interworking implies thumb interworking. Adding
1780 this to the flags here simplifies the logic elsewhere. */
1781 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1782 target_flags |= MASK_INTERWORK;
1784 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1785 from here where no function is being compiled currently. */
1786 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1787 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1789 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1790 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1792 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1794 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1795 target_flags |= MASK_APCS_FRAME;
1798 if (TARGET_POKE_FUNCTION_NAME)
1799 target_flags |= MASK_APCS_FRAME;
1801 if (TARGET_APCS_REENT && flag_pic)
1802 error ("-fpic and -mapcs-reent are incompatible");
1804 if (TARGET_APCS_REENT)
1805 warning (0, "APCS reentrant code not supported. Ignored");
1807 /* If this target is normally configured to use APCS frames, warn if they
1808 are turned off and debugging is turned on. */
1810 && write_symbols != NO_DEBUG
1811 && !TARGET_APCS_FRAME
1812 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1813 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1815 if (TARGET_APCS_FLOAT)
1816 warning (0, "passing floating point arguments in fp regs not yet supported");
1818 if (TARGET_LITTLE_WORDS)
1819 warning (OPT_Wdeprecated, "%<mwords-little-endian%> is deprecated and "
1820 "will be removed in a future release");
1822 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1823 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1824 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1825 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1826 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1827 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1828 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1829 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1830 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1831 arm_arch6m = arm_arch6 && !arm_arch_notm;
1832 arm_arch7 = (insn_flags & FL_ARCH7) != 0;
1833 arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
1834 arm_arch8 = (insn_flags & FL_ARCH8) != 0;
1835 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1836 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1838 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1839 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1840 thumb_code = TARGET_ARM == 0;
1841 thumb1_code = TARGET_THUMB1 != 0;
1842 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1843 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1844 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1845 arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0;
1846 arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
1847 arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
1848 arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
1850 /* If we are not using the default (ARM mode) section anchor offset
1851 ranges, then set the correct ranges now. */
1854 /* Thumb-1 LDR instructions cannot have negative offsets.
1855 Permissible positive offset ranges are 5-bit (for byte loads),
1856 6-bit (for halfword loads), or 7-bit (for word loads).
1857 Empirical results suggest a 7-bit anchor range gives the best
1858 overall code size. */
1859 targetm.min_anchor_offset = 0;
1860 targetm.max_anchor_offset = 127;
1862 else if (TARGET_THUMB2)
1864 /* The minimum is set such that the total size of the block
1865 for a particular anchor is 248 + 1 + 4095 bytes, which is
1866 divisible by eight, ensuring natural spacing of anchors. */
1867 targetm.min_anchor_offset = -248;
1868 targetm.max_anchor_offset = 4095;
1871 /* V5 code we generate is completely interworking capable, so we turn off
1872 TARGET_INTERWORK here to avoid many tests later on. */
1874 /* XXX However, we must pass the right pre-processor defines to CPP
1875 or GLD can get confused. This is a hack. */
1876 if (TARGET_INTERWORK)
1877 arm_cpp_interwork = 1;
1880 target_flags &= ~MASK_INTERWORK;
1882 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1883 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1885 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1886 error ("iwmmxt abi requires an iwmmxt capable cpu");
1888 if (!global_options_set.x_arm_fpu_index)
1890 const char *target_fpu_name;
1893 #ifdef FPUTYPE_DEFAULT
1894 target_fpu_name = FPUTYPE_DEFAULT;
1896 target_fpu_name = "vfp";
1899 ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index,
1904 arm_fpu_desc = &all_fpus[arm_fpu_index];
1906 switch (arm_fpu_desc->model)
1908 case ARM_FP_MODEL_VFP:
1909 arm_fpu_attr = FPU_VFP;
1916 if (TARGET_AAPCS_BASED)
1918 if (TARGET_CALLER_INTERWORKING)
1919 error ("AAPCS does not support -mcaller-super-interworking");
1921 if (TARGET_CALLEE_INTERWORKING)
1922 error ("AAPCS does not support -mcallee-super-interworking");
1925 /* iWMMXt and NEON are incompatible. */
1926 if (TARGET_IWMMXT && TARGET_NEON)
1927 error ("iWMMXt and NEON are incompatible");
1929 /* iWMMXt unsupported under Thumb mode. */
1930 if (TARGET_THUMB && TARGET_IWMMXT)
1931 error ("iWMMXt unsupported under Thumb mode");
1933 /* __fp16 support currently assumes the core has ldrh. */
1934 if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
1935 sorry ("__fp16 and no ldrh");
1937 /* If soft-float is specified then don't use FPU. */
1938 if (TARGET_SOFT_FLOAT)
1939 arm_fpu_attr = FPU_NONE;
1941 if (TARGET_AAPCS_BASED)
1943 if (arm_abi == ARM_ABI_IWMMXT)
1944 arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
1945 else if (arm_float_abi == ARM_FLOAT_ABI_HARD
1946 && TARGET_HARD_FLOAT
1948 arm_pcs_default = ARM_PCS_AAPCS_VFP;
1950 arm_pcs_default = ARM_PCS_AAPCS;
1954 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1955 sorry ("-mfloat-abi=hard and VFP");
1957 if (arm_abi == ARM_ABI_APCS)
1958 arm_pcs_default = ARM_PCS_APCS;
1960 arm_pcs_default = ARM_PCS_ATPCS;
1963 /* For arm2/3 there is no need to do any scheduling if we are doing
1964 software floating-point. */
1965 if (TARGET_SOFT_FLOAT && (tune_flags & FL_MODE32) == 0)
1966 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1968 /* Use the cp15 method if it is available. */
1969 if (target_thread_pointer == TP_AUTO)
1971 if (arm_arch6k && !TARGET_THUMB1)
1972 target_thread_pointer = TP_CP15;
1974 target_thread_pointer = TP_SOFT;
1977 if (TARGET_HARD_TP && TARGET_THUMB1)
1978 error ("can not use -mtp=cp15 with 16-bit Thumb");
1980 /* Override the default structure alignment for AAPCS ABI. */
1981 if (!global_options_set.x_arm_structure_size_boundary)
1983 if (TARGET_AAPCS_BASED)
1984 arm_structure_size_boundary = 8;
1988 if (arm_structure_size_boundary != 8
1989 && arm_structure_size_boundary != 32
1990 && !(ARM_DOUBLEWORD_ALIGN && arm_structure_size_boundary == 64))
1992 if (ARM_DOUBLEWORD_ALIGN)
1994 "structure size boundary can only be set to 8, 32 or 64");
1996 warning (0, "structure size boundary can only be set to 8 or 32");
1997 arm_structure_size_boundary
1998 = (TARGET_AAPCS_BASED ? 8 : DEFAULT_STRUCTURE_SIZE_BOUNDARY);
2002 if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
2004 error ("RTP PIC is incompatible with Thumb");
2008 /* If stack checking is disabled, we can use r10 as the PIC register,
2009 which keeps r9 available. The EABI specifies r9 as the PIC register. */
2010 if (flag_pic && TARGET_SINGLE_PIC_BASE)
2012 if (TARGET_VXWORKS_RTP)
2013 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
2014 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
2017 if (flag_pic && TARGET_VXWORKS_RTP)
2018 arm_pic_register = 9;
2020 if (arm_pic_register_string != NULL)
2022 int pic_register = decode_reg_name (arm_pic_register_string);
2025 warning (0, "-mpic-register= is useless without -fpic");
2027 /* Prevent the user from choosing an obviously stupid PIC register. */
2028 else if (pic_register < 0 || call_used_regs[pic_register]
2029 || pic_register == HARD_FRAME_POINTER_REGNUM
2030 || pic_register == STACK_POINTER_REGNUM
2031 || pic_register >= PC_REGNUM
2032 || (TARGET_VXWORKS_RTP
2033 && (unsigned int) pic_register != arm_pic_register))
2034 error ("unable to use '%s' for PIC register", arm_pic_register_string);
2036 arm_pic_register = pic_register;
2039 /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
2040 if (fix_cm3_ldrd == 2)
2042 if (arm_selected_cpu->core == cortexm3)
2048 /* Enable -munaligned-access by default for
2049 - all ARMv6 architecture-based processors
2050 - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
2051 - ARMv8 architecture-base processors.
2053 Disable -munaligned-access by default for
2054 - all pre-ARMv6 architecture-based processors
2055 - ARMv6-M architecture-based processors. */
2057 if (unaligned_access == 2)
2059 if (arm_arch6 && (arm_arch_notm || arm_arch7))
2060 unaligned_access = 1;
2062 unaligned_access = 0;
2064 else if (unaligned_access == 1
2065 && !(arm_arch6 && (arm_arch_notm || arm_arch7)))
2067 warning (0, "target CPU does not support unaligned accesses");
2068 unaligned_access = 0;
2071 if (TARGET_THUMB1 && flag_schedule_insns)
2073 /* Don't warn since it's on by default in -O2. */
2074 flag_schedule_insns = 0;
2079 /* If optimizing for size, bump the number of instructions that we
2080 are prepared to conditionally execute (even on a StrongARM). */
2081 max_insns_skipped = 6;
2084 max_insns_skipped = current_tune->max_insns_skipped;
2086 /* Hot/Cold partitioning is not currently supported, since we can't
2087 handle literal pool placement in that case. */
2088 if (flag_reorder_blocks_and_partition)
2090 inform (input_location,
2091 "-freorder-blocks-and-partition not supported on this architecture");
2092 flag_reorder_blocks_and_partition = 0;
2093 flag_reorder_blocks = 1;
2097 /* Hoisting PIC address calculations more aggressively provides a small,
2098 but measurable, size reduction for PIC code. Therefore, we decrease
2099 the bar for unrestricted expression hoisting to the cost of PIC address
2100 calculation, which is 2 instructions. */
2101 maybe_set_param_value (PARAM_GCSE_UNRESTRICTED_COST, 2,
2102 global_options.x_param_values,
2103 global_options_set.x_param_values);
2105 /* ARM EABI defaults to strict volatile bitfields. */
2106 if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0
2107 && abi_version_at_least(2))
2108 flag_strict_volatile_bitfields = 1;
2110 /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed
2111 it beneficial (signified by setting num_prefetch_slots to 1 or more.) */
2112 if (flag_prefetch_loop_arrays < 0
2115 && current_tune->num_prefetch_slots > 0)
2116 flag_prefetch_loop_arrays = 1;
2118 /* Set up parameters to be used in prefetching algorithm. Do not override the
2119 defaults unless we are tuning for a core we have researched values for. */
2120 if (current_tune->num_prefetch_slots > 0)
2121 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
2122 current_tune->num_prefetch_slots,
2123 global_options.x_param_values,
2124 global_options_set.x_param_values);
2125 if (current_tune->l1_cache_line_size >= 0)
2126 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
2127 current_tune->l1_cache_line_size,
2128 global_options.x_param_values,
2129 global_options_set.x_param_values);
2130 if (current_tune->l1_cache_size >= 0)
2131 maybe_set_param_value (PARAM_L1_CACHE_SIZE,
2132 current_tune->l1_cache_size,
2133 global_options.x_param_values,
2134 global_options_set.x_param_values);
2136 /* Use the alternative scheduling-pressure algorithm by default. */
2137 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
2138 global_options.x_param_values,
2139 global_options_set.x_param_values);
2141 /* Register global variables with the garbage collector. */
2142 arm_add_gc_roots ();
2146 arm_add_gc_roots (void)
2148 gcc_obstack_init(&minipool_obstack);
2149 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
2152 /* A table of known ARM exception types.
2153 For use with the interrupt function attribute. */
2157 const char *const arg;
2158 const unsigned long return_value;
2162 static const isr_attribute_arg isr_attribute_args [] =
2164 { "IRQ", ARM_FT_ISR },
2165 { "irq", ARM_FT_ISR },
2166 { "FIQ", ARM_FT_FIQ },
2167 { "fiq", ARM_FT_FIQ },
2168 { "ABORT", ARM_FT_ISR },
2169 { "abort", ARM_FT_ISR },
2170 { "ABORT", ARM_FT_ISR },
2171 { "abort", ARM_FT_ISR },
2172 { "UNDEF", ARM_FT_EXCEPTION },
2173 { "undef", ARM_FT_EXCEPTION },
2174 { "SWI", ARM_FT_EXCEPTION },
2175 { "swi", ARM_FT_EXCEPTION },
2176 { NULL, ARM_FT_NORMAL }
2179 /* Returns the (interrupt) function type of the current
2180 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
2182 static unsigned long
2183 arm_isr_value (tree argument)
2185 const isr_attribute_arg * ptr;
2189 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
2191 /* No argument - default to IRQ. */
2192 if (argument == NULL_TREE)
2195 /* Get the value of the argument. */
2196 if (TREE_VALUE (argument) == NULL_TREE
2197 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
2198 return ARM_FT_UNKNOWN;
2200 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
2202 /* Check it against the list of known arguments. */
2203 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
2204 if (streq (arg, ptr->arg))
2205 return ptr->return_value;
2207 /* An unrecognized interrupt type. */
2208 return ARM_FT_UNKNOWN;
2211 /* Computes the type of the current function. */
2213 static unsigned long
2214 arm_compute_func_type (void)
2216 unsigned long type = ARM_FT_UNKNOWN;
2220 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
2222 /* Decide if the current function is volatile. Such functions
2223 never return, and many memory cycles can be saved by not storing
2224 register values that will never be needed again. This optimization
2225 was added to speed up context switching in a kernel application. */
2227 && (TREE_NOTHROW (current_function_decl)
2228 || !(flag_unwind_tables
2230 && arm_except_unwind_info (&global_options) != UI_SJLJ)))
2231 && TREE_THIS_VOLATILE (current_function_decl))
2232 type |= ARM_FT_VOLATILE;
2234 if (cfun->static_chain_decl != NULL)
2235 type |= ARM_FT_NESTED;
2237 attr = DECL_ATTRIBUTES (current_function_decl);
2239 a = lookup_attribute ("naked", attr);
2241 type |= ARM_FT_NAKED;
2243 a = lookup_attribute ("isr", attr);
2245 a = lookup_attribute ("interrupt", attr);
2248 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
2250 type |= arm_isr_value (TREE_VALUE (a));
2255 /* Returns the type of the current function. */
2258 arm_current_func_type (void)
2260 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
2261 cfun->machine->func_type = arm_compute_func_type ();
2263 return cfun->machine->func_type;
2267 arm_allocate_stack_slots_for_args (void)
2269 /* Naked functions should not allocate stack slots for arguments. */
2270 return !IS_NAKED (arm_current_func_type ());
2274 arm_warn_func_return (tree decl)
2276 /* Naked functions are implemented entirely in assembly, including the
2277 return sequence, so suppress warnings about this. */
2278 return lookup_attribute ("naked", DECL_ATTRIBUTES (decl)) == NULL_TREE;
2282 /* Output assembler code for a block containing the constant parts
2283 of a trampoline, leaving space for the variable parts.
2285 On the ARM, (if r8 is the static chain regnum, and remembering that
2286 referencing pc adds an offset of 8) the trampoline looks like:
2289 .word static chain value
2290 .word function's address
2291 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
2294 arm_asm_trampoline_template (FILE *f)
2298 asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM, PC_REGNUM);
2299 asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", PC_REGNUM, PC_REGNUM);
2301 else if (TARGET_THUMB2)
2303 /* The Thumb-2 trampoline is similar to the arm implementation.
2304 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
2305 asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n",
2306 STATIC_CHAIN_REGNUM, PC_REGNUM);
2307 asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM, PC_REGNUM);
2311 ASM_OUTPUT_ALIGN (f, 2);
2312 fprintf (f, "\t.code\t16\n");
2313 fprintf (f, ".Ltrampoline_start:\n");
2314 asm_fprintf (f, "\tpush\t{r0, r1}\n");
2315 asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM);
2316 asm_fprintf (f, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM);
2317 asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM);
2318 asm_fprintf (f, "\tstr\tr0, [%r, #4]\n", SP_REGNUM);
2319 asm_fprintf (f, "\tpop\t{r0, %r}\n", PC_REGNUM);
2321 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
2322 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
2325 /* Emit RTL insns to initialize the variable parts of a trampoline. */
2328 arm_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2330 rtx fnaddr, mem, a_tramp;
2332 emit_block_move (m_tramp, assemble_trampoline_template (),
2333 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2335 mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 8 : 12);
2336 emit_move_insn (mem, chain_value);
2338 mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 12 : 16);
2339 fnaddr = XEXP (DECL_RTL (fndecl), 0);
2340 emit_move_insn (mem, fnaddr);
2342 a_tramp = XEXP (m_tramp, 0);
2343 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"),
2344 LCT_NORMAL, VOIDmode, 2, a_tramp, Pmode,
2345 plus_constant (Pmode, a_tramp, TRAMPOLINE_SIZE), Pmode);
2348 /* Thumb trampolines should be entered in thumb mode, so set
2349 the bottom bit of the address. */
2352 arm_trampoline_adjust_address (rtx addr)
2355 addr = expand_simple_binop (Pmode, IOR, addr, const1_rtx,
2356 NULL, 0, OPTAB_LIB_WIDEN);
2360 /* Return 1 if it is possible to return using a single instruction.
2361 If SIBLING is non-null, this is a test for a return before a sibling
2362 call. SIBLING is the call insn, so we can examine its register usage. */
2365 use_return_insn (int iscond, rtx sibling)
2368 unsigned int func_type;
2369 unsigned long saved_int_regs;
2370 unsigned HOST_WIDE_INT stack_adjust;
2371 arm_stack_offsets *offsets;
2373 /* Never use a return instruction before reload has run. */
2374 if (!reload_completed)
2377 func_type = arm_current_func_type ();
2379 /* Naked, volatile and stack alignment functions need special
2381 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
2384 /* So do interrupt functions that use the frame pointer and Thumb
2385 interrupt functions. */
2386 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
2389 offsets = arm_get_frame_offsets ();
2390 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
2392 /* As do variadic functions. */
2393 if (crtl->args.pretend_args_size
2394 || cfun->machine->uses_anonymous_args
2395 /* Or if the function calls __builtin_eh_return () */
2396 || crtl->calls_eh_return
2397 /* Or if the function calls alloca */
2398 || cfun->calls_alloca
2399 /* Or if there is a stack adjustment. However, if the stack pointer
2400 is saved on the stack, we can use a pre-incrementing stack load. */
2401 || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed
2402 && stack_adjust == 4)))
2405 saved_int_regs = offsets->saved_regs_mask;
2407 /* Unfortunately, the insn
2409 ldmib sp, {..., sp, ...}
2411 triggers a bug on most SA-110 based devices, such that the stack
2412 pointer won't be correctly restored if the instruction takes a
2413 page fault. We work around this problem by popping r3 along with
2414 the other registers, since that is never slower than executing
2415 another instruction.
2417 We test for !arm_arch5 here, because code for any architecture
2418 less than this could potentially be run on one of the buggy
2420 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
2422 /* Validate that r3 is a call-clobbered register (always true in
2423 the default abi) ... */
2424 if (!call_used_regs[3])
2427 /* ... that it isn't being used for a return value ... */
2428 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
2431 /* ... or for a tail-call argument ... */
2434 gcc_assert (CALL_P (sibling));
2436 if (find_regno_fusage (sibling, USE, 3))
2440 /* ... and that there are no call-saved registers in r0-r2
2441 (always true in the default ABI). */
2442 if (saved_int_regs & 0x7)
2446 /* Can't be done if interworking with Thumb, and any registers have been
2448 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
2451 /* On StrongARM, conditional returns are expensive if they aren't
2452 taken and multiple registers have been stacked. */
2453 if (iscond && arm_tune_strongarm)
2455 /* Conditional return when just the LR is stored is a simple
2456 conditional-load instruction, that's not expensive. */
2457 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
2461 && arm_pic_register != INVALID_REGNUM
2462 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
2466 /* If there are saved registers but the LR isn't saved, then we need
2467 two instructions for the return. */
2468 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
2471 /* Can't be done if any of the VFP regs are pushed,
2472 since this also requires an insn. */
2473 if (TARGET_HARD_FLOAT && TARGET_VFP)
2474 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
2475 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
2478 if (TARGET_REALLY_IWMMXT)
2479 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
2480 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2486 /* Return TRUE if int I is a valid immediate ARM constant. */
2489 const_ok_for_arm (HOST_WIDE_INT i)
2493 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
2494 be all zero, or all one. */
2495 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
2496 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
2497 != ((~(unsigned HOST_WIDE_INT) 0)
2498 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
2501 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
2503 /* Fast return for 0 and small values. We must do this for zero, since
2504 the code below can't handle that one case. */
2505 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
2508 /* Get the number of trailing zeros. */
2509 lowbit = ffs((int) i) - 1;
2511 /* Only even shifts are allowed in ARM mode so round down to the
2512 nearest even number. */
2516 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
2521 /* Allow rotated constants in ARM mode. */
2523 && ((i & ~0xc000003f) == 0
2524 || (i & ~0xf000000f) == 0
2525 || (i & ~0xfc000003) == 0))
2532 /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */
2535 if (i == v || i == (v | (v << 8)))
2538 /* Allow repeated pattern 0xXY00XY00. */
2548 /* Return true if I is a valid constant for the operation CODE. */
2550 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
2552 if (const_ok_for_arm (i))
2558 /* See if we can use movw. */
2559 if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
2562 /* Otherwise, try mvn. */
2563 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
2566 /* See if we can use addw or subw. */
2568 && ((i & 0xfffff000) == 0
2569 || ((-i) & 0xfffff000) == 0))
2571 /* else fall through. */
2591 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
2593 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
2599 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
2603 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
2610 /* Return true if I is a valid di mode constant for the operation CODE. */
2612 const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code)
2614 HOST_WIDE_INT hi_val = (i >> 32) & 0xFFFFFFFF;
2615 HOST_WIDE_INT lo_val = i & 0xFFFFFFFF;
2616 rtx hi = GEN_INT (hi_val);
2617 rtx lo = GEN_INT (lo_val);
2625 return arm_not_operand (hi, SImode) && arm_add_operand (lo, SImode);
2632 /* Emit a sequence of insns to handle a large constant.
2633 CODE is the code of the operation required, it can be any of SET, PLUS,
2634 IOR, AND, XOR, MINUS;
2635 MODE is the mode in which the operation is being performed;
2636 VAL is the integer to operate on;
2637 SOURCE is the other operand (a register, or a null-pointer for SET);
2638 SUBTARGETS means it is safe to create scratch registers if that will
2639 either produce a simpler sequence, or we will want to cse the values.
2640 Return value is the number of insns emitted. */
2642 /* ??? Tweak this for thumb2. */
2644 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
2645 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
2649 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
2650 cond = COND_EXEC_TEST (PATTERN (insn));
2654 if (subtargets || code == SET
2655 || (REG_P (target) && REG_P (source)
2656 && REGNO (target) != REGNO (source)))
2658 /* After arm_reorg has been called, we can't fix up expensive
2659 constants by pushing them into memory so we must synthesize
2660 them in-line, regardless of the cost. This is only likely to
2661 be more costly on chips that have load delay slots and we are
2662 compiling without running the scheduler (so no splitting
2663 occurred before the final instruction emission).
2665 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
2667 if (!after_arm_reorg
2669 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
2671 > (arm_constant_limit (optimize_function_for_size_p (cfun))
2676 /* Currently SET is the only monadic value for CODE, all
2677 the rest are diadic. */
2678 if (TARGET_USE_MOVT)
2679 arm_emit_movpair (target, GEN_INT (val));
2681 emit_set_insn (target, GEN_INT (val));
2687 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
2689 if (TARGET_USE_MOVT)
2690 arm_emit_movpair (temp, GEN_INT (val));
2692 emit_set_insn (temp, GEN_INT (val));
2694 /* For MINUS, the value is subtracted from, since we never
2695 have subtraction of a constant. */
2697 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
2699 emit_set_insn (target,
2700 gen_rtx_fmt_ee (code, mode, source, temp));
2706 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
2710 /* Return a sequence of integers, in RETURN_SEQUENCE that fit into
2711 ARM/THUMB2 immediates, and add up to VAL.
2712 Thr function return value gives the number of insns required. */
2714 optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
2715 struct four_ints *return_sequence)
2717 int best_consecutive_zeros = 0;
2721 struct four_ints tmp_sequence;
2723 /* If we aren't targeting ARM, the best place to start is always at
2724 the bottom, otherwise look more closely. */
2727 for (i = 0; i < 32; i += 2)
2729 int consecutive_zeros = 0;
2731 if (!(val & (3 << i)))
2733 while ((i < 32) && !(val & (3 << i)))
2735 consecutive_zeros += 2;
2738 if (consecutive_zeros > best_consecutive_zeros)
2740 best_consecutive_zeros = consecutive_zeros;
2741 best_start = i - consecutive_zeros;
2748 /* So long as it won't require any more insns to do so, it's
2749 desirable to emit a small constant (in bits 0...9) in the last
2750 insn. This way there is more chance that it can be combined with
2751 a later addressing insn to form a pre-indexed load or store
2752 operation. Consider:
2754 *((volatile int *)0xe0000100) = 1;
2755 *((volatile int *)0xe0000110) = 2;
2757 We want this to wind up as:
2761 str rB, [rA, #0x100]
2763 str rB, [rA, #0x110]
2765 rather than having to synthesize both large constants from scratch.
2767 Therefore, we calculate how many insns would be required to emit
2768 the constant starting from `best_start', and also starting from
2769 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2770 yield a shorter sequence, we may as well use zero. */
2771 insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
2773 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
2775 insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
2776 if (insns2 <= insns1)
2778 *return_sequence = tmp_sequence;
2786 /* As for optimal_immediate_sequence, but starting at bit-position I. */
2788 optimal_immediate_sequence_1 (enum rtx_code code, unsigned HOST_WIDE_INT val,
2789 struct four_ints *return_sequence, int i)
2791 int remainder = val & 0xffffffff;
2794 /* Try and find a way of doing the job in either two or three
2797 In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
2798 location. We start at position I. This may be the MSB, or
2799 optimial_immediate_sequence may have positioned it at the largest block
2800 of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
2801 wrapping around to the top of the word when we drop off the bottom.
2802 In the worst case this code should produce no more than four insns.
2804 In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
2805 constants, shifted to any arbitrary location. We should always start
2810 unsigned int b1, b2, b3, b4;
2811 unsigned HOST_WIDE_INT result;
2814 gcc_assert (insns < 4);
2819 /* First, find the next normal 12/8-bit shifted/rotated immediate. */
2820 if (remainder & ((TARGET_ARM ? (3 << (i - 2)) : (1 << (i - 1)))))
2823 if (i <= 12 && TARGET_THUMB2 && code == PLUS)
2824 /* We can use addw/subw for the last 12 bits. */
2828 /* Use an 8-bit shifted/rotated immediate. */
2832 result = remainder & ((0x0ff << end)
2833 | ((i < end) ? (0xff >> (32 - end))
2840 /* Arm allows rotates by a multiple of two. Thumb-2 allows
2841 arbitrary shifts. */
2842 i -= TARGET_ARM ? 2 : 1;
2846 /* Next, see if we can do a better job with a thumb2 replicated
2849 We do it this way around to catch the cases like 0x01F001E0 where
2850 two 8-bit immediates would work, but a replicated constant would
2853 TODO: 16-bit constants that don't clear all the bits, but still win.
2854 TODO: Arithmetic splitting for set/add/sub, rather than bitwise. */
2857 b1 = (remainder & 0xff000000) >> 24;
2858 b2 = (remainder & 0x00ff0000) >> 16;
2859 b3 = (remainder & 0x0000ff00) >> 8;
2860 b4 = remainder & 0xff;
2864 /* The 8-bit immediate already found clears b1 (and maybe b2),
2865 but must leave b3 and b4 alone. */
2867 /* First try to find a 32-bit replicated constant that clears
2868 almost everything. We can assume that we can't do it in one,
2869 or else we wouldn't be here. */
2870 unsigned int tmp = b1 & b2 & b3 & b4;
2871 unsigned int tmp2 = tmp + (tmp << 8) + (tmp << 16)
2873 unsigned int matching_bytes = (tmp == b1) + (tmp == b2)
2874 + (tmp == b3) + (tmp == b4);
2876 && (matching_bytes >= 3
2877 || (matching_bytes == 2
2878 && const_ok_for_op (remainder & ~tmp2, code))))
2880 /* At least 3 of the bytes match, and the fourth has at
2881 least as many bits set, or two of the bytes match
2882 and it will only require one more insn to finish. */
2890 /* Second, try to find a 16-bit replicated constant that can
2891 leave three of the bytes clear. If b2 or b4 is already
2892 zero, then we can. If the 8-bit from above would not
2893 clear b2 anyway, then we still win. */
2894 else if (b1 == b3 && (!b2 || !b4
2895 || (remainder & 0x00ff0000 & ~result)))
2897 result = remainder & 0xff00ff00;
2903 /* The 8-bit immediate already found clears b2 (and maybe b3)
2904 and we don't get here unless b1 is alredy clear, but it will
2905 leave b4 unchanged. */
2907 /* If we can clear b2 and b4 at once, then we win, since the
2908 8-bits couldn't possibly reach that far. */
2911 result = remainder & 0x00ff00ff;
2917 return_sequence->i[insns++] = result;
2918 remainder &= ~result;
2920 if (code == SET || code == MINUS)
2928 /* Emit an instruction with the indicated PATTERN. If COND is
2929 non-NULL, conditionalize the execution of the instruction on COND
2933 emit_constant_insn (rtx cond, rtx pattern)
2936 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
2937 emit_insn (pattern);
2940 /* As above, but extra parameter GENERATE which, if clear, suppresses
2944 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
2945 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
2950 int final_invert = 0;
2952 int set_sign_bit_copies = 0;
2953 int clear_sign_bit_copies = 0;
2954 int clear_zero_bit_copies = 0;
2955 int set_zero_bit_copies = 0;
2956 int insns = 0, neg_insns, inv_insns;
2957 unsigned HOST_WIDE_INT temp1, temp2;
2958 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
2959 struct four_ints *immediates;
2960 struct four_ints pos_immediates, neg_immediates, inv_immediates;
2962 /* Find out which operations are safe for a given CODE. Also do a quick
2963 check for degenerate cases; these can occur when DImode operations
2976 if (remainder == 0xffffffff)
2979 emit_constant_insn (cond,
2980 gen_rtx_SET (VOIDmode, target,
2981 GEN_INT (ARM_SIGN_EXTEND (val))));
2987 if (reload_completed && rtx_equal_p (target, source))
2991 emit_constant_insn (cond,
2992 gen_rtx_SET (VOIDmode, target, source));
3001 emit_constant_insn (cond,
3002 gen_rtx_SET (VOIDmode, target, const0_rtx));
3005 if (remainder == 0xffffffff)
3007 if (reload_completed && rtx_equal_p (target, source))
3010 emit_constant_insn (cond,
3011 gen_rtx_SET (VOIDmode, target, source));
3020 if (reload_completed && rtx_equal_p (target, source))
3023 emit_constant_insn (cond,
3024 gen_rtx_SET (VOIDmode, target, source));
3028 if (remainder == 0xffffffff)
3031 emit_constant_insn (cond,
3032 gen_rtx_SET (VOIDmode, target,
3033 gen_rtx_NOT (mode, source)));
3040 /* We treat MINUS as (val - source), since (source - val) is always
3041 passed as (source + (-val)). */
3045 emit_constant_insn (cond,
3046 gen_rtx_SET (VOIDmode, target,
3047 gen_rtx_NEG (mode, source)));
3050 if (const_ok_for_arm (val))
3053 emit_constant_insn (cond,
3054 gen_rtx_SET (VOIDmode, target,
3055 gen_rtx_MINUS (mode, GEN_INT (val),
3066 /* If we can do it in one insn get out quickly. */
3067 if (const_ok_for_op (val, code))
3070 emit_constant_insn (cond,
3071 gen_rtx_SET (VOIDmode, target,
3073 ? gen_rtx_fmt_ee (code, mode, source,
3079 /* On targets with UXTH/UBFX, we can deal with AND (2^N)-1 in a single
3081 if (code == AND && (i = exact_log2 (remainder + 1)) > 0
3082 && (arm_arch_thumb2 || (i == 16 && arm_arch6 && mode == SImode)))
3086 if (mode == SImode && i == 16)
3087 /* Use UXTH in preference to UBFX, since on Thumb2 it's a
3089 emit_constant_insn (cond,
3090 gen_zero_extendhisi2
3091 (target, gen_lowpart (HImode, source)));
3093 /* Extz only supports SImode, but we can coerce the operands
3095 emit_constant_insn (cond,
3096 gen_extzv_t2 (gen_lowpart (SImode, target),
3097 gen_lowpart (SImode, source),
3098 GEN_INT (i), const0_rtx));
3104 /* Calculate a few attributes that may be useful for specific
3106 /* Count number of leading zeros. */
3107 for (i = 31; i >= 0; i--)
3109 if ((remainder & (1 << i)) == 0)
3110 clear_sign_bit_copies++;
3115 /* Count number of leading 1's. */
3116 for (i = 31; i >= 0; i--)
3118 if ((remainder & (1 << i)) != 0)
3119 set_sign_bit_copies++;
3124 /* Count number of trailing zero's. */
3125 for (i = 0; i <= 31; i++)
3127 if ((remainder & (1 << i)) == 0)
3128 clear_zero_bit_copies++;
3133 /* Count number of trailing 1's. */
3134 for (i = 0; i <= 31; i++)
3136 if ((remainder & (1 << i)) != 0)
3137 set_zero_bit_copies++;
3145 /* See if we can do this by sign_extending a constant that is known
3146 to be negative. This is a good, way of doing it, since the shift
3147 may well merge into a subsequent insn. */
3148 if (set_sign_bit_copies > 1)
3150 if (const_ok_for_arm
3151 (temp1 = ARM_SIGN_EXTEND (remainder
3152 << (set_sign_bit_copies - 1))))
3156 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3157 emit_constant_insn (cond,
3158 gen_rtx_SET (VOIDmode, new_src,
3160 emit_constant_insn (cond,
3161 gen_ashrsi3 (target, new_src,
3162 GEN_INT (set_sign_bit_copies - 1)));
3166 /* For an inverted constant, we will need to set the low bits,
3167 these will be shifted out of harm's way. */
3168 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
3169 if (const_ok_for_arm (~temp1))
3173 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3174 emit_constant_insn (cond,
3175 gen_rtx_SET (VOIDmode, new_src,
3177 emit_constant_insn (cond,
3178 gen_ashrsi3 (target, new_src,
3179 GEN_INT (set_sign_bit_copies - 1)));
3185 /* See if we can calculate the value as the difference between two
3186 valid immediates. */
3187 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
3189 int topshift = clear_sign_bit_copies & ~1;
3191 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
3192 & (0xff000000 >> topshift));
3194 /* If temp1 is zero, then that means the 9 most significant
3195 bits of remainder were 1 and we've caused it to overflow.
3196 When topshift is 0 we don't need to do anything since we
3197 can borrow from 'bit 32'. */
3198 if (temp1 == 0 && topshift != 0)
3199 temp1 = 0x80000000 >> (topshift - 1);
3201 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
3203 if (const_ok_for_arm (temp2))
3207 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3208 emit_constant_insn (cond,
3209 gen_rtx_SET (VOIDmode, new_src,
3211 emit_constant_insn (cond,
3212 gen_addsi3 (target, new_src,
3220 /* See if we can generate this by setting the bottom (or the top)
3221 16 bits, and then shifting these into the other half of the
3222 word. We only look for the simplest cases, to do more would cost
3223 too much. Be careful, however, not to generate this when the
3224 alternative would take fewer insns. */
3225 if (val & 0xffff0000)
3227 temp1 = remainder & 0xffff0000;
3228 temp2 = remainder & 0x0000ffff;
3230 /* Overlaps outside this range are best done using other methods. */
3231 for (i = 9; i < 24; i++)
3233 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
3234 && !const_ok_for_arm (temp2))
3236 rtx new_src = (subtargets
3237 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
3239 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
3240 source, subtargets, generate);
3248 gen_rtx_ASHIFT (mode, source,
3255 /* Don't duplicate cases already considered. */
3256 for (i = 17; i < 24; i++)
3258 if (((temp1 | (temp1 >> i)) == remainder)
3259 && !const_ok_for_arm (temp1))
3261 rtx new_src = (subtargets
3262 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
3264 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
3265 source, subtargets, generate);
3270 gen_rtx_SET (VOIDmode, target,
3273 gen_rtx_LSHIFTRT (mode, source,
3284 /* If we have IOR or XOR, and the constant can be loaded in a
3285 single instruction, and we can find a temporary to put it in,
3286 then this can be done in two instructions instead of 3-4. */
3288 /* TARGET can't be NULL if SUBTARGETS is 0 */
3289 || (reload_completed && !reg_mentioned_p (target, source)))
3291 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
3295 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3297 emit_constant_insn (cond,
3298 gen_rtx_SET (VOIDmode, sub,
3300 emit_constant_insn (cond,
3301 gen_rtx_SET (VOIDmode, target,
3302 gen_rtx_fmt_ee (code, mode,
3313 x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
3314 and the remainder 0s for e.g. 0xfff00000)
3315 x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies)
3317 This can be done in 2 instructions by using shifts with mov or mvn.
3322 mvn r0, r0, lsr #12 */
3323 if (set_sign_bit_copies > 8
3324 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
3328 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3329 rtx shift = GEN_INT (set_sign_bit_copies);
3333 gen_rtx_SET (VOIDmode, sub,
3335 gen_rtx_ASHIFT (mode,
3340 gen_rtx_SET (VOIDmode, target,
3342 gen_rtx_LSHIFTRT (mode, sub,
3349 x = y | constant (which has set_zero_bit_copies number of trailing ones).
3351 x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies).
3353 For eg. r0 = r0 | 0xfff
3358 if (set_zero_bit_copies > 8
3359 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
3363 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3364 rtx shift = GEN_INT (set_zero_bit_copies);
3368 gen_rtx_SET (VOIDmode, sub,
3370 gen_rtx_LSHIFTRT (mode,
3375 gen_rtx_SET (VOIDmode, target,
3377 gen_rtx_ASHIFT (mode, sub,
3383 /* This will never be reached for Thumb2 because orn is a valid
3384 instruction. This is for Thumb1 and the ARM 32 bit cases.
3386 x = y | constant (such that ~constant is a valid constant)
3388 x = ~(~y & ~constant).
3390 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
3394 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
3395 emit_constant_insn (cond,
3396 gen_rtx_SET (VOIDmode, sub,
3397 gen_rtx_NOT (mode, source)));
3400 sub = gen_reg_rtx (mode);
3401 emit_constant_insn (cond,
3402 gen_rtx_SET (VOIDmode, sub,
3403 gen_rtx_AND (mode, source,
3405 emit_constant_insn (cond,
3406 gen_rtx_SET (VOIDmode, target,
3407 gen_rtx_NOT (mode, sub)));
3414 /* See if two shifts will do 2 or more insn's worth of work. */
3415 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
3417 HOST_WIDE_INT shift_mask = ((0xffffffff
3418 << (32 - clear_sign_bit_copies))
3421 if ((remainder | shift_mask) != 0xffffffff)
3425 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3426 insns = arm_gen_constant (AND, mode, cond,
3427 remainder | shift_mask,
3428 new_src, source, subtargets, 1);
3433 rtx targ = subtargets ? NULL_RTX : target;
3434 insns = arm_gen_constant (AND, mode, cond,
3435 remainder | shift_mask,
3436 targ, source, subtargets, 0);
3442 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3443 rtx shift = GEN_INT (clear_sign_bit_copies);
3445 emit_insn (gen_ashlsi3 (new_src, source, shift));
3446 emit_insn (gen_lshrsi3 (target, new_src, shift));
3452 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
3454 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
3456 if ((remainder | shift_mask) != 0xffffffff)
3460 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3462 insns = arm_gen_constant (AND, mode, cond,
3463 remainder | shift_mask,
3464 new_src, source, subtargets, 1);
3469 rtx targ = subtargets ? NULL_RTX : target;
3471 insns = arm_gen_constant (AND, mode, cond,
3472 remainder | shift_mask,
3473 targ, source, subtargets, 0);
3479 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
3480 rtx shift = GEN_INT (clear_zero_bit_copies);
3482 emit_insn (gen_lshrsi3 (new_src, source, shift));
3483 emit_insn (gen_ashlsi3 (target, new_src, shift));
3495 /* Calculate what the instruction sequences would be if we generated it
3496 normally, negated, or inverted. */
3498 /* AND cannot be split into multiple insns, so invert and use BIC. */
3501 insns = optimal_immediate_sequence (code, remainder, &pos_immediates);
3504 neg_insns = optimal_immediate_sequence (code, (-remainder) & 0xffffffff,
3509 if (can_invert || final_invert)
3510 inv_insns = optimal_immediate_sequence (code, remainder ^ 0xffffffff,
3515 immediates = &pos_immediates;
3517 /* Is the negated immediate sequence more efficient? */
3518 if (neg_insns < insns && neg_insns <= inv_insns)
3521 immediates = &neg_immediates;
3526 /* Is the inverted immediate sequence more efficient?
3527 We must allow for an extra NOT instruction for XOR operations, although
3528 there is some chance that the final 'mvn' will get optimized later. */
3529 if ((inv_insns + 1) < insns || (!final_invert && inv_insns < insns))
3532 immediates = &inv_immediates;
3540 /* Now output the chosen sequence as instructions. */
3543 for (i = 0; i < insns; i++)
3545 rtx new_src, temp1_rtx;
3547 temp1 = immediates->i[i];
3549 if (code == SET || code == MINUS)
3550 new_src = (subtargets ? gen_reg_rtx (mode) : target);
3551 else if ((final_invert || i < (insns - 1)) && subtargets)
3552 new_src = gen_reg_rtx (mode);
3558 else if (can_negate)
3561 temp1 = trunc_int_for_mode (temp1, mode);
3562 temp1_rtx = GEN_INT (temp1);
3566 else if (code == MINUS)
3567 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
3569 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
3571 emit_constant_insn (cond,
3572 gen_rtx_SET (VOIDmode, new_src,
3578 can_negate = can_invert;
3582 else if (code == MINUS)
3590 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
3591 gen_rtx_NOT (mode, source)));
3598 /* Canonicalize a comparison so that we are more likely to recognize it.
3599 This can be done for a few constant compares, where we can make the
3600 immediate value easier to load. */
3603 arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
3604 bool op0_preserve_value)
3606 enum machine_mode mode;
3607 unsigned HOST_WIDE_INT i, maxval;
3609 mode = GET_MODE (*op0);
3610 if (mode == VOIDmode)
3611 mode = GET_MODE (*op1);
3613 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
3615 /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode
3616 we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either
3617 reversed or (for constant OP1) adjusted to GE/LT. Similarly
3618 for GTU/LEU in Thumb mode. */
3623 if (*code == GT || *code == LE
3624 || (!TARGET_ARM && (*code == GTU || *code == LEU)))
3626 /* Missing comparison. First try to use an available
3628 if (CONST_INT_P (*op1))
3636 && arm_const_double_by_immediates (GEN_INT (i + 1)))
3638 *op1 = GEN_INT (i + 1);
3639 *code = *code == GT ? GE : LT;
3645 if (i != ~((unsigned HOST_WIDE_INT) 0)
3646 && arm_const_double_by_immediates (GEN_INT (i + 1)))
3648 *op1 = GEN_INT (i + 1);
3649 *code = *code == GTU ? GEU : LTU;
3658 /* If that did not work, reverse the condition. */
3659 if (!op0_preserve_value)
3664 *code = (int)swap_condition ((enum rtx_code)*code);
3670 /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing
3671 with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)),
3672 to facilitate possible combining with a cmp into 'ands'. */
3674 && GET_CODE (*op0) == ZERO_EXTEND
3675 && GET_CODE (XEXP (*op0, 0)) == SUBREG
3676 && GET_MODE (XEXP (*op0, 0)) == QImode
3677 && GET_MODE (SUBREG_REG (XEXP (*op0, 0))) == SImode
3678 && subreg_lowpart_p (XEXP (*op0, 0))
3679 && *op1 == const0_rtx)
3680 *op0 = gen_rtx_AND (SImode, SUBREG_REG (XEXP (*op0, 0)),
3683 /* Comparisons smaller than DImode. Only adjust comparisons against
3684 an out-of-range constant. */
3685 if (!CONST_INT_P (*op1)
3686 || const_ok_for_arm (INTVAL (*op1))
3687 || const_ok_for_arm (- INTVAL (*op1)))
3701 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
3703 *op1 = GEN_INT (i + 1);
3704 *code = *code == GT ? GE : LT;
3712 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
3714 *op1 = GEN_INT (i - 1);
3715 *code = *code == GE ? GT : LE;
3722 if (i != ~((unsigned HOST_WIDE_INT) 0)
3723 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
3725 *op1 = GEN_INT (i + 1);
3726 *code = *code == GTU ? GEU : LTU;
3734 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
3736 *op1 = GEN_INT (i - 1);
3737 *code = *code == GEU ? GTU : LEU;
3748 /* Define how to find the value returned by a function. */
3751 arm_function_value(const_tree type, const_tree func,
3752 bool outgoing ATTRIBUTE_UNUSED)
3754 enum machine_mode mode;
3755 int unsignedp ATTRIBUTE_UNUSED;
3756 rtx r ATTRIBUTE_UNUSED;
3758 mode = TYPE_MODE (type);
3760 if (TARGET_AAPCS_BASED)
3761 return aapcs_allocate_return_reg (mode, type, func);
3763 /* Promote integer types. */
3764 if (INTEGRAL_TYPE_P (type))
3765 mode = arm_promote_function_mode (type, mode, &unsignedp, func, 1);
3767 /* Promotes small structs returned in a register to full-word size
3768 for big-endian AAPCS. */
3769 if (arm_return_in_msb (type))
3771 HOST_WIDE_INT size = int_size_in_bytes (type);
3772 if (size % UNITS_PER_WORD != 0)
3774 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
3775 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
3779 return arm_libcall_value_1 (mode);
3783 libcall_eq (const void *p1, const void *p2)
3785 return rtx_equal_p ((const_rtx) p1, (const_rtx) p2);
3789 libcall_hash (const void *p1)
3791 return hash_rtx ((const_rtx) p1, VOIDmode, NULL, NULL, FALSE);
3795 add_libcall (htab_t htab, rtx libcall)
3797 *htab_find_slot (htab, libcall, INSERT) = libcall;
3801 arm_libcall_uses_aapcs_base (const_rtx libcall)
3803 static bool init_done = false;
3804 static htab_t libcall_htab;
3810 libcall_htab = htab_create (31, libcall_hash, libcall_eq,
3812 add_libcall (libcall_htab,
3813 convert_optab_libfunc (sfloat_optab, SFmode, SImode));
3814 add_libcall (libcall_htab,
3815 convert_optab_libfunc (sfloat_optab, DFmode, SImode));
3816 add_libcall (libcall_htab,
3817 convert_optab_libfunc (sfloat_optab, SFmode, DImode));
3818 add_libcall (libcall_htab,
3819 convert_optab_libfunc (sfloat_optab, DFmode, DImode));
3821 add_libcall (libcall_htab,
3822 convert_optab_libfunc (ufloat_optab, SFmode, SImode));
3823 add_libcall (libcall_htab,
3824 convert_optab_libfunc (ufloat_optab, DFmode, SImode));
3825 add_libcall (libcall_htab,
3826 convert_optab_libfunc (ufloat_optab, SFmode, DImode));
3827 add_libcall (libcall_htab,
3828 convert_optab_libfunc (ufloat_optab, DFmode, DImode));
3830 add_libcall (libcall_htab,
3831 convert_optab_libfunc (sext_optab, SFmode, HFmode));
3832 add_libcall (libcall_htab,
3833 convert_optab_libfunc (trunc_optab, HFmode, SFmode));
3834 add_libcall (libcall_htab,
3835 convert_optab_libfunc (sfix_optab, SImode, DFmode));
3836 add_libcall (libcall_htab,
3837 convert_optab_libfunc (ufix_optab, SImode, DFmode));
3838 add_libcall (libcall_htab,
3839 convert_optab_libfunc (sfix_optab, DImode, DFmode));
3840 add_libcall (libcall_htab,
3841 convert_optab_libfunc (ufix_optab, DImode, DFmode));
3842 add_libcall (libcall_htab,
3843 convert_optab_libfunc (sfix_optab, DImode, SFmode));
3844 add_libcall (libcall_htab,
3845 convert_optab_libfunc (ufix_optab, DImode, SFmode));
3847 /* Values from double-precision helper functions are returned in core
3848 registers if the selected core only supports single-precision
3849 arithmetic, even if we are using the hard-float ABI. The same is
3850 true for single-precision helpers, but we will never be using the
3851 hard-float ABI on a CPU which doesn't support single-precision
3852 operations in hardware. */
3853 add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode));
3854 add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode));
3855 add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode));
3856 add_libcall (libcall_htab, optab_libfunc (neg_optab, DFmode));
3857 add_libcall (libcall_htab, optab_libfunc (sub_optab, DFmode));
3858 add_libcall (libcall_htab, optab_libfunc (eq_optab, DFmode));
3859 add_libcall (libcall_htab, optab_libfunc (lt_optab, DFmode));
3860 add_libcall (libcall_htab, optab_libfunc (le_optab, DFmode));
3861 add_libcall (libcall_htab, optab_libfunc (ge_optab, DFmode));
3862 add_libcall (libcall_htab, optab_libfunc (gt_optab, DFmode));
3863 add_libcall (libcall_htab, optab_libfunc (unord_optab, DFmode));
3864 add_libcall (libcall_htab, convert_optab_libfunc (sext_optab, DFmode,
3866 add_libcall (libcall_htab, convert_optab_libfunc (trunc_optab, SFmode,
3870 return libcall && htab_find (libcall_htab, libcall) != NULL;
3874 arm_libcall_value_1 (enum machine_mode mode)
3876 if (TARGET_AAPCS_BASED)
3877 return aapcs_libcall_value (mode);
3878 else if (TARGET_IWMMXT_ABI
3879 && arm_vector_mode_supported_p (mode))
3880 return gen_rtx_REG (mode, FIRST_IWMMXT_REGNUM);
3882 return gen_rtx_REG (mode, ARG_REGISTER (1));
3885 /* Define how to find the value returned by a library function
3886 assuming the value has mode MODE. */
3889 arm_libcall_value (enum machine_mode mode, const_rtx libcall)
3891 if (TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS
3892 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3894 /* The following libcalls return their result in integer registers,
3895 even though they return a floating point value. */
3896 if (arm_libcall_uses_aapcs_base (libcall))
3897 return gen_rtx_REG (mode, ARG_REGISTER(1));
3901 return arm_libcall_value_1 (mode);
3904 /* Implement TARGET_FUNCTION_VALUE_REGNO_P. */
3907 arm_function_value_regno_p (const unsigned int regno)
3909 if (regno == ARG_REGISTER (1)
3911 && TARGET_AAPCS_BASED
3913 && TARGET_HARD_FLOAT
3914 && regno == FIRST_VFP_REGNUM)
3915 || (TARGET_IWMMXT_ABI
3916 && regno == FIRST_IWMMXT_REGNUM))
3922 /* Determine the amount of memory needed to store the possible return
3923 registers of an untyped call. */
3925 arm_apply_result_size (void)
3931 if (TARGET_HARD_FLOAT_ABI && TARGET_VFP)
3933 if (TARGET_IWMMXT_ABI)
3940 /* Decide whether TYPE should be returned in memory (true)
3941 or in a register (false). FNTYPE is the type of the function making
3944 arm_return_in_memory (const_tree type, const_tree fntype)
3948 size = int_size_in_bytes (type); /* Negative if not fixed size. */
3950 if (TARGET_AAPCS_BASED)
3952 /* Simple, non-aggregate types (ie not including vectors and
3953 complex) are always returned in a register (or registers).
3954 We don't care about which register here, so we can short-cut
3955 some of the detail. */
3956 if (!AGGREGATE_TYPE_P (type)
3957 && TREE_CODE (type) != VECTOR_TYPE
3958 && TREE_CODE (type) != COMPLEX_TYPE)
3961 /* Any return value that is no larger than one word can be
3963 if (((unsigned HOST_WIDE_INT) size) <= UNITS_PER_WORD)
3966 /* Check any available co-processors to see if they accept the
3967 type as a register candidate (VFP, for example, can return
3968 some aggregates in consecutive registers). These aren't
3969 available if the call is variadic. */
3970 if (aapcs_select_return_coproc (type, fntype) >= 0)
3973 /* Vector values should be returned using ARM registers, not
3974 memory (unless they're over 16 bytes, which will break since
3975 we only have four call-clobbered registers to play with). */
3976 if (TREE_CODE (type) == VECTOR_TYPE)
3977 return (size < 0 || size > (4 * UNITS_PER_WORD));
3979 /* The rest go in memory. */
3983 if (TREE_CODE (type) == VECTOR_TYPE)
3984 return (size < 0 || size > (4 * UNITS_PER_WORD));
3986 if (!AGGREGATE_TYPE_P (type) &&
3987 (TREE_CODE (type) != VECTOR_TYPE))
3988 /* All simple types are returned in registers. */
3991 if (arm_abi != ARM_ABI_APCS)
3993 /* ATPCS and later return aggregate types in memory only if they are
3994 larger than a word (or are variable size). */
3995 return (size < 0 || size > UNITS_PER_WORD);
3998 /* For the arm-wince targets we choose to be compatible with Microsoft's
3999 ARM and Thumb compilers, which always return aggregates in memory. */
4001 /* All structures/unions bigger than one word are returned in memory.
4002 Also catch the case where int_size_in_bytes returns -1. In this case
4003 the aggregate is either huge or of variable size, and in either case
4004 we will want to return it via memory and not in a register. */
4005 if (size < 0 || size > UNITS_PER_WORD)
4008 if (TREE_CODE (type) == RECORD_TYPE)
4012 /* For a struct the APCS says that we only return in a register
4013 if the type is 'integer like' and every addressable element
4014 has an offset of zero. For practical purposes this means
4015 that the structure can have at most one non bit-field element
4016 and that this element must be the first one in the structure. */
4018 /* Find the first field, ignoring non FIELD_DECL things which will
4019 have been created by C++. */
4020 for (field = TYPE_FIELDS (type);
4021 field && TREE_CODE (field) != FIELD_DECL;
4022 field = DECL_CHAIN (field))
4026 return false; /* An empty structure. Allowed by an extension to ANSI C. */
4028 /* Check that the first field is valid for returning in a register. */
4030 /* ... Floats are not allowed */
4031 if (FLOAT_TYPE_P (TREE_TYPE (field)))
4034 /* ... Aggregates that are not themselves valid for returning in
4035 a register are not allowed. */
4036 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
4039 /* Now check the remaining fields, if any. Only bitfields are allowed,
4040 since they are not addressable. */
4041 for (field = DECL_CHAIN (field);
4043 field = DECL_CHAIN (field))
4045 if (TREE_CODE (field) != FIELD_DECL)
4048 if (!DECL_BIT_FIELD_TYPE (field))
4055 if (TREE_CODE (type) == UNION_TYPE)
4059 /* Unions can be returned in registers if every element is
4060 integral, or can be returned in an integer register. */
4061 for (field = TYPE_FIELDS (type);
4063 field = DECL_CHAIN (field))
4065 if (TREE_CODE (field) != FIELD_DECL)
4068 if (FLOAT_TYPE_P (TREE_TYPE (field)))
4071 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
4077 #endif /* not ARM_WINCE */
4079 /* Return all other types in memory. */
4083 const struct pcs_attribute_arg
4087 } pcs_attribute_args[] =
4089 {"aapcs", ARM_PCS_AAPCS},
4090 {"aapcs-vfp", ARM_PCS_AAPCS_VFP},
4092 /* We could recognize these, but changes would be needed elsewhere
4093 * to implement them. */
4094 {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT},
4095 {"atpcs", ARM_PCS_ATPCS},
4096 {"apcs", ARM_PCS_APCS},
4098 {NULL, ARM_PCS_UNKNOWN}
4102 arm_pcs_from_attribute (tree attr)
4104 const struct pcs_attribute_arg *ptr;
4107 /* Get the value of the argument. */
4108 if (TREE_VALUE (attr) == NULL_TREE
4109 || TREE_CODE (TREE_VALUE (attr)) != STRING_CST)
4110 return ARM_PCS_UNKNOWN;
4112 arg = TREE_STRING_POINTER (TREE_VALUE (attr));
4114 /* Check it against the list of known arguments. */
4115 for (ptr = pcs_attribute_args; ptr->arg != NULL; ptr++)
4116 if (streq (arg, ptr->arg))
4119 /* An unrecognized interrupt type. */
4120 return ARM_PCS_UNKNOWN;
4123 /* Get the PCS variant to use for this call. TYPE is the function's type
4124 specification, DECL is the specific declartion. DECL may be null if
4125 the call could be indirect or if this is a library call. */
4127 arm_get_pcs_model (const_tree type, const_tree decl)
4129 bool user_convention = false;
4130 enum arm_pcs user_pcs = arm_pcs_default;
4135 attr = lookup_attribute ("pcs", TYPE_ATTRIBUTES (type));
4138 user_pcs = arm_pcs_from_attribute (TREE_VALUE (attr));
4139 user_convention = true;
4142 if (TARGET_AAPCS_BASED)
4144 /* Detect varargs functions. These always use the base rules
4145 (no argument is ever a candidate for a co-processor
4147 bool base_rules = stdarg_p (type);
4149 if (user_convention)
4151 if (user_pcs > ARM_PCS_AAPCS_LOCAL)
4152 sorry ("non-AAPCS derived PCS variant");
4153 else if (base_rules && user_pcs != ARM_PCS_AAPCS)
4154 error ("variadic functions must use the base AAPCS variant");
4158 return ARM_PCS_AAPCS;
4159 else if (user_convention)
4161 else if (decl && flag_unit_at_a_time)
4163 /* Local functions never leak outside this compilation unit,
4164 so we are free to use whatever conventions are
4166 /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */
4167 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4169 return ARM_PCS_AAPCS_LOCAL;
4172 else if (user_convention && user_pcs != arm_pcs_default)
4173 sorry ("PCS variant");
4175 /* For everything else we use the target's default. */
4176 return arm_pcs_default;
4181 aapcs_vfp_cum_init (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED,
4182 const_tree fntype ATTRIBUTE_UNUSED,
4183 rtx libcall ATTRIBUTE_UNUSED,
4184 const_tree fndecl ATTRIBUTE_UNUSED)
4186 /* Record the unallocated VFP registers. */
4187 pcum->aapcs_vfp_regs_free = (1 << NUM_VFP_ARG_REGS) - 1;
4188 pcum->aapcs_vfp_reg_alloc = 0;
4191 /* Walk down the type tree of TYPE counting consecutive base elements.
4192 If *MODEP is VOIDmode, then set it to the first valid floating point
4193 type. If a non-floating point type is found, or if a floating point
4194 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
4195 otherwise return the count in the sub-tree. */
4197 aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep)
4199 enum machine_mode mode;
4202 switch (TREE_CODE (type))
4205 mode = TYPE_MODE (type);
4206 if (mode != DFmode && mode != SFmode)
4209 if (*modep == VOIDmode)
4218 mode = TYPE_MODE (TREE_TYPE (type));
4219 if (mode != DFmode && mode != SFmode)
4222 if (*modep == VOIDmode)
4231 /* Use V2SImode and V4SImode as representatives of all 64-bit
4232 and 128-bit vector types, whether or not those modes are
4233 supported with the present options. */
4234 size = int_size_in_bytes (type);
4247 if (*modep == VOIDmode)
4250 /* Vector modes are considered to be opaque: two vectors are
4251 equivalent for the purposes of being homogeneous aggregates
4252 if they are the same size. */
4261 tree index = TYPE_DOMAIN (type);
4263 /* Can't handle incomplete types. */
4264 if (!COMPLETE_TYPE_P (type))
4267 count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep);
4270 || !TYPE_MAX_VALUE (index)
4271 || !host_integerp (TYPE_MAX_VALUE (index), 1)
4272 || !TYPE_MIN_VALUE (index)
4273 || !host_integerp (TYPE_MIN_VALUE (index), 1)
4277 count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1)
4278 - tree_low_cst (TYPE_MIN_VALUE (index), 1));
4280 /* There must be no padding. */
4281 if (!host_integerp (TYPE_SIZE (type), 1)
4282 || (tree_low_cst (TYPE_SIZE (type), 1)
4283 != count * GET_MODE_BITSIZE (*modep)))
4295 /* Can't handle incomplete types. */
4296 if (!COMPLETE_TYPE_P (type))
4299 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4301 if (TREE_CODE (field) != FIELD_DECL)
4304 sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep);
4310 /* There must be no padding. */
4311 if (!host_integerp (TYPE_SIZE (type), 1)
4312 || (tree_low_cst (TYPE_SIZE (type), 1)
4313 != count * GET_MODE_BITSIZE (*modep)))
4320 case QUAL_UNION_TYPE:
4322 /* These aren't very interesting except in a degenerate case. */
4327 /* Can't handle incomplete types. */
4328 if (!COMPLETE_TYPE_P (type))
4331 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4333 if (TREE_CODE (field) != FIELD_DECL)
4336 sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep);
4339 count = count > sub_count ? count : sub_count;
4342 /* There must be no padding. */
4343 if (!host_integerp (TYPE_SIZE (type), 1)
4344 || (tree_low_cst (TYPE_SIZE (type), 1)
4345 != count * GET_MODE_BITSIZE (*modep)))
4358 /* Return true if PCS_VARIANT should use VFP registers. */
4360 use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
4362 if (pcs_variant == ARM_PCS_AAPCS_VFP)
4364 static bool seen_thumb1_vfp = false;
4366 if (TARGET_THUMB1 && !seen_thumb1_vfp)
4368 sorry ("Thumb-1 hard-float VFP ABI");
4369 /* sorry() is not immediately fatal, so only display this once. */
4370 seen_thumb1_vfp = true;
4376 if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
4379 return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT &&
4380 (TARGET_VFP_DOUBLE || !is_double));
4383 /* Return true if an argument whose type is TYPE, or mode is MODE, is
4384 suitable for passing or returning in VFP registers for the PCS
4385 variant selected. If it is, then *BASE_MODE is updated to contain
4386 a machine mode describing each element of the argument's type and
4387 *COUNT to hold the number of such elements. */
4389 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant,
4390 enum machine_mode mode, const_tree type,
4391 enum machine_mode *base_mode, int *count)
4393 enum machine_mode new_mode = VOIDmode;
4395 /* If we have the type information, prefer that to working things
4396 out from the mode. */
4399 int ag_count = aapcs_vfp_sub_candidate (type, &new_mode);
4401 if (ag_count > 0 && ag_count <= 4)
4406 else if (GET_MODE_CLASS (mode) == MODE_FLOAT
4407 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
4408 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4413 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4416 new_mode = (mode == DCmode ? DFmode : SFmode);
4422 if (!use_vfp_abi (pcs_variant, ARM_NUM_REGS (new_mode) > 1))
4425 *base_mode = new_mode;
4430 aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant,
4431 enum machine_mode mode, const_tree type)
4433 int count ATTRIBUTE_UNUSED;
4434 enum machine_mode ag_mode ATTRIBUTE_UNUSED;
4436 if (!use_vfp_abi (pcs_variant, false))
4438 return aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type,
4443 aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4446 if (!use_vfp_abi (pcum->pcs_variant, false))
4449 return aapcs_vfp_is_call_or_return_candidate (pcum->pcs_variant, mode, type,
4450 &pcum->aapcs_vfp_rmode,
4451 &pcum->aapcs_vfp_rcount);
4455 aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4456 const_tree type ATTRIBUTE_UNUSED)
4458 int shift = GET_MODE_SIZE (pcum->aapcs_vfp_rmode) / GET_MODE_SIZE (SFmode);
4459 unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1;
4462 for (regno = 0; regno < NUM_VFP_ARG_REGS; regno += shift)
4463 if (((pcum->aapcs_vfp_regs_free >> regno) & mask) == mask)
4465 pcum->aapcs_vfp_reg_alloc = mask << regno;
4466 if (mode == BLKmode || (mode == TImode && !TARGET_NEON))
4469 int rcount = pcum->aapcs_vfp_rcount;
4471 enum machine_mode rmode = pcum->aapcs_vfp_rmode;
4475 /* Avoid using unsupported vector modes. */
4476 if (rmode == V2SImode)
4478 else if (rmode == V4SImode)
4485 par = gen_rtx_PARALLEL (mode, rtvec_alloc (rcount));
4486 for (i = 0; i < rcount; i++)
4488 rtx tmp = gen_rtx_REG (rmode,
4489 FIRST_VFP_REGNUM + regno + i * rshift);
4490 tmp = gen_rtx_EXPR_LIST
4492 GEN_INT (i * GET_MODE_SIZE (rmode)));
4493 XVECEXP (par, 0, i) = tmp;
4496 pcum->aapcs_reg = par;
4499 pcum->aapcs_reg = gen_rtx_REG (mode, FIRST_VFP_REGNUM + regno);
4506 aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
4507 enum machine_mode mode,
4508 const_tree type ATTRIBUTE_UNUSED)
4510 if (!use_vfp_abi (pcs_variant, false))
4513 if (mode == BLKmode || (mode == TImode && !TARGET_NEON))
4516 enum machine_mode ag_mode;
4521 aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type,
4526 if (ag_mode == V2SImode)
4528 else if (ag_mode == V4SImode)
4534 shift = GET_MODE_SIZE(ag_mode) / GET_MODE_SIZE(SFmode);
4535 par = gen_rtx_PARALLEL (mode, rtvec_alloc (count));
4536 for (i = 0; i < count; i++)
4538 rtx tmp = gen_rtx_REG (ag_mode, FIRST_VFP_REGNUM + i * shift);
4539 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp,
4540 GEN_INT (i * GET_MODE_SIZE (ag_mode)));
4541 XVECEXP (par, 0, i) = tmp;
4547 return gen_rtx_REG (mode, FIRST_VFP_REGNUM);
4551 aapcs_vfp_advance (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED,
4552 enum machine_mode mode ATTRIBUTE_UNUSED,
4553 const_tree type ATTRIBUTE_UNUSED)
4555 pcum->aapcs_vfp_regs_free &= ~pcum->aapcs_vfp_reg_alloc;
4556 pcum->aapcs_vfp_reg_alloc = 0;
4560 #define AAPCS_CP(X) \
4562 aapcs_ ## X ## _cum_init, \
4563 aapcs_ ## X ## _is_call_candidate, \
4564 aapcs_ ## X ## _allocate, \
4565 aapcs_ ## X ## _is_return_candidate, \
4566 aapcs_ ## X ## _allocate_return_reg, \
4567 aapcs_ ## X ## _advance \
4570 /* Table of co-processors that can be used to pass arguments in
4571 registers. Idealy no arugment should be a candidate for more than
4572 one co-processor table entry, but the table is processed in order
4573 and stops after the first match. If that entry then fails to put
4574 the argument into a co-processor register, the argument will go on
4578 /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */
4579 void (*cum_init) (CUMULATIVE_ARGS *, const_tree, rtx, const_tree);
4581 /* Return true if an argument of mode MODE (or type TYPE if MODE is
4582 BLKmode) is a candidate for this co-processor's registers; this
4583 function should ignore any position-dependent state in
4584 CUMULATIVE_ARGS and only use call-type dependent information. */
4585 bool (*is_call_candidate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
4587 /* Return true if the argument does get a co-processor register; it
4588 should set aapcs_reg to an RTX of the register allocated as is
4589 required for a return from FUNCTION_ARG. */
4590 bool (*allocate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
4592 /* Return true if a result of mode MODE (or type TYPE if MODE is
4593 BLKmode) is can be returned in this co-processor's registers. */
4594 bool (*is_return_candidate) (enum arm_pcs, enum machine_mode, const_tree);
4596 /* Allocate and return an RTX element to hold the return type of a
4597 call, this routine must not fail and will only be called if
4598 is_return_candidate returned true with the same parameters. */
4599 rtx (*allocate_return_reg) (enum arm_pcs, enum machine_mode, const_tree);
4601 /* Finish processing this argument and prepare to start processing
4603 void (*advance) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
4604 } aapcs_cp_arg_layout[ARM_NUM_COPROC_SLOTS] =
4612 aapcs_select_call_coproc (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4617 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4618 if (aapcs_cp_arg_layout[i].is_call_candidate (pcum, mode, type))
4625 aapcs_select_return_coproc (const_tree type, const_tree fntype)
4627 /* We aren't passed a decl, so we can't check that a call is local.
4628 However, it isn't clear that that would be a win anyway, since it
4629 might limit some tail-calling opportunities. */
4630 enum arm_pcs pcs_variant;
4634 const_tree fndecl = NULL_TREE;
4636 if (TREE_CODE (fntype) == FUNCTION_DECL)
4639 fntype = TREE_TYPE (fntype);
4642 pcs_variant = arm_get_pcs_model (fntype, fndecl);
4645 pcs_variant = arm_pcs_default;
4647 if (pcs_variant != ARM_PCS_AAPCS)
4651 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4652 if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant,
4661 aapcs_allocate_return_reg (enum machine_mode mode, const_tree type,
4664 /* We aren't passed a decl, so we can't check that a call is local.
4665 However, it isn't clear that that would be a win anyway, since it
4666 might limit some tail-calling opportunities. */
4667 enum arm_pcs pcs_variant;
4668 int unsignedp ATTRIBUTE_UNUSED;
4672 const_tree fndecl = NULL_TREE;
4674 if (TREE_CODE (fntype) == FUNCTION_DECL)
4677 fntype = TREE_TYPE (fntype);
4680 pcs_variant = arm_get_pcs_model (fntype, fndecl);
4683 pcs_variant = arm_pcs_default;
4685 /* Promote integer types. */
4686 if (type && INTEGRAL_TYPE_P (type))
4687 mode = arm_promote_function_mode (type, mode, &unsignedp, fntype, 1);
4689 if (pcs_variant != ARM_PCS_AAPCS)
4693 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4694 if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant, mode,
4696 return aapcs_cp_arg_layout[i].allocate_return_reg (pcs_variant,
4700 /* Promotes small structs returned in a register to full-word size
4701 for big-endian AAPCS. */
4702 if (type && arm_return_in_msb (type))
4704 HOST_WIDE_INT size = int_size_in_bytes (type);
4705 if (size % UNITS_PER_WORD != 0)
4707 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4708 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4712 return gen_rtx_REG (mode, R0_REGNUM);
4716 aapcs_libcall_value (enum machine_mode mode)
4718 if (BYTES_BIG_ENDIAN && ALL_FIXED_POINT_MODE_P (mode)
4719 && GET_MODE_SIZE (mode) <= 4)
4722 return aapcs_allocate_return_reg (mode, NULL_TREE, NULL_TREE);
4725 /* Lay out a function argument using the AAPCS rules. The rule
4726 numbers referred to here are those in the AAPCS. */
4728 aapcs_layout_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
4729 const_tree type, bool named)
4734 /* We only need to do this once per argument. */
4735 if (pcum->aapcs_arg_processed)
4738 pcum->aapcs_arg_processed = true;
4740 /* Special case: if named is false then we are handling an incoming
4741 anonymous argument which is on the stack. */
4745 /* Is this a potential co-processor register candidate? */
4746 if (pcum->pcs_variant != ARM_PCS_AAPCS)
4748 int slot = aapcs_select_call_coproc (pcum, mode, type);
4749 pcum->aapcs_cprc_slot = slot;
4751 /* We don't have to apply any of the rules from part B of the
4752 preparation phase, these are handled elsewhere in the
4757 /* A Co-processor register candidate goes either in its own
4758 class of registers or on the stack. */
4759 if (!pcum->aapcs_cprc_failed[slot])
4761 /* C1.cp - Try to allocate the argument to co-processor
4763 if (aapcs_cp_arg_layout[slot].allocate (pcum, mode, type))
4766 /* C2.cp - Put the argument on the stack and note that we
4767 can't assign any more candidates in this slot. We also
4768 need to note that we have allocated stack space, so that
4769 we won't later try to split a non-cprc candidate between
4770 core registers and the stack. */
4771 pcum->aapcs_cprc_failed[slot] = true;
4772 pcum->can_split = false;
4775 /* We didn't get a register, so this argument goes on the
4777 gcc_assert (pcum->can_split == false);
4782 /* C3 - For double-word aligned arguments, round the NCRN up to the
4783 next even number. */
4784 ncrn = pcum->aapcs_ncrn;
4785 if ((ncrn & 1) && arm_needs_doubleword_align (mode, type))
4788 nregs = ARM_NUM_REGS2(mode, type);
4790 /* Sigh, this test should really assert that nregs > 0, but a GCC
4791 extension allows empty structs and then gives them empty size; it
4792 then allows such a structure to be passed by value. For some of
4793 the code below we have to pretend that such an argument has
4794 non-zero size so that we 'locate' it correctly either in
4795 registers or on the stack. */
4796 gcc_assert (nregs >= 0);
4798 nregs2 = nregs ? nregs : 1;
4800 /* C4 - Argument fits entirely in core registers. */
4801 if (ncrn + nregs2 <= NUM_ARG_REGS)
4803 pcum->aapcs_reg = gen_rtx_REG (mode, ncrn);
4804 pcum->aapcs_next_ncrn = ncrn + nregs;
4808 /* C5 - Some core registers left and there are no arguments already
4809 on the stack: split this argument between the remaining core
4810 registers and the stack. */
4811 if (ncrn < NUM_ARG_REGS && pcum->can_split)
4813 pcum->aapcs_reg = gen_rtx_REG (mode, ncrn);
4814 pcum->aapcs_next_ncrn = NUM_ARG_REGS;
4815 pcum->aapcs_partial = (NUM_ARG_REGS - ncrn) * UNITS_PER_WORD;
4819 /* C6 - NCRN is set to 4. */
4820 pcum->aapcs_next_ncrn = NUM_ARG_REGS;
4822 /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
4826 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4827 for a call to a function whose data type is FNTYPE.
4828 For a library call, FNTYPE is NULL. */
4830 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
4832 tree fndecl ATTRIBUTE_UNUSED)
4834 /* Long call handling. */
4836 pcum->pcs_variant = arm_get_pcs_model (fntype, fndecl);
4838 pcum->pcs_variant = arm_pcs_default;
4840 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4842 if (arm_libcall_uses_aapcs_base (libname))
4843 pcum->pcs_variant = ARM_PCS_AAPCS;
4845 pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0;
4846 pcum->aapcs_reg = NULL_RTX;
4847 pcum->aapcs_partial = 0;
4848 pcum->aapcs_arg_processed = false;
4849 pcum->aapcs_cprc_slot = -1;
4850 pcum->can_split = true;
4852 if (pcum->pcs_variant != ARM_PCS_AAPCS)
4856 for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
4858 pcum->aapcs_cprc_failed[i] = false;
4859 aapcs_cp_arg_layout[i].cum_init (pcum, fntype, libname, fndecl);
4867 /* On the ARM, the offset starts at 0. */
4869 pcum->iwmmxt_nregs = 0;
4870 pcum->can_split = true;
4872 /* Varargs vectors are treated the same as long long.
4873 named_count avoids having to change the way arm handles 'named' */
4874 pcum->named_count = 0;
4877 if (TARGET_REALLY_IWMMXT && fntype)
4881 for (fn_arg = TYPE_ARG_TYPES (fntype);
4883 fn_arg = TREE_CHAIN (fn_arg))
4884 pcum->named_count += 1;
4886 if (! pcum->named_count)
4887 pcum->named_count = INT_MAX;
4892 /* Return true if mode/type need doubleword alignment. */
4894 arm_needs_doubleword_align (enum machine_mode mode, const_tree type)
4896 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
4897 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
4901 /* Determine where to put an argument to a function.
4902 Value is zero to push the argument on the stack,
4903 or a hard register in which to store the argument.
4905 MODE is the argument's machine mode.
4906 TYPE is the data type of the argument (as a tree).
4907 This is null for libcalls where that information may
4909 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4910 the preceding args and about the function being called.
4911 NAMED is nonzero if this argument is a named parameter
4912 (otherwise it is an extra parameter matching an ellipsis).
4914 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
4915 other arguments are passed on the stack. If (NAMED == 0) (which happens
4916 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
4917 defined), say it is passed in the stack (function_prologue will
4918 indeed make it pass in the stack if necessary). */
4921 arm_function_arg (cumulative_args_t pcum_v, enum machine_mode mode,
4922 const_tree type, bool named)
4924 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
4927 /* Handle the special case quickly. Pick an arbitrary value for op2 of
4928 a call insn (op3 of a call_value insn). */
4929 if (mode == VOIDmode)
4932 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4934 aapcs_layout_arg (pcum, mode, type, named);
4935 return pcum->aapcs_reg;
4938 /* Varargs vectors are treated the same as long long.
4939 named_count avoids having to change the way arm handles 'named' */
4940 if (TARGET_IWMMXT_ABI
4941 && arm_vector_mode_supported_p (mode)
4942 && pcum->named_count > pcum->nargs + 1)
4944 if (pcum->iwmmxt_nregs <= 9)
4945 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
4948 pcum->can_split = false;
4953 /* Put doubleword aligned quantities in even register pairs. */
4955 && ARM_DOUBLEWORD_ALIGN
4956 && arm_needs_doubleword_align (mode, type))
4959 /* Only allow splitting an arg between regs and memory if all preceding
4960 args were allocated to regs. For args passed by reference we only count
4961 the reference pointer. */
4962 if (pcum->can_split)
4965 nregs = ARM_NUM_REGS2 (mode, type);
4967 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
4970 return gen_rtx_REG (mode, pcum->nregs);
4974 arm_function_arg_boundary (enum machine_mode mode, const_tree type)
4976 return (ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (mode, type)
4977 ? DOUBLEWORD_ALIGNMENT
4982 arm_arg_partial_bytes (cumulative_args_t pcum_v, enum machine_mode mode,
4983 tree type, bool named)
4985 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
4986 int nregs = pcum->nregs;
4988 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4990 aapcs_layout_arg (pcum, mode, type, named);
4991 return pcum->aapcs_partial;
4994 if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode))
4997 if (NUM_ARG_REGS > nregs
4998 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
5000 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
5005 /* Update the data in PCUM to advance over an argument
5006 of mode MODE and data type TYPE.
5007 (TYPE is null for libcalls where that information may not be available.) */
5010 arm_function_arg_advance (cumulative_args_t pcum_v, enum machine_mode mode,
5011 const_tree type, bool named)
5013 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
5015 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
5017 aapcs_layout_arg (pcum, mode, type, named);
5019 if (pcum->aapcs_cprc_slot >= 0)
5021 aapcs_cp_arg_layout[pcum->aapcs_cprc_slot].advance (pcum, mode,
5023 pcum->aapcs_cprc_slot = -1;
5026 /* Generic stuff. */
5027 pcum->aapcs_arg_processed = false;
5028 pcum->aapcs_ncrn = pcum->aapcs_next_ncrn;
5029 pcum->aapcs_reg = NULL_RTX;
5030 pcum->aapcs_partial = 0;
5035 if (arm_vector_mode_supported_p (mode)
5036 && pcum->named_count > pcum->nargs
5037 && TARGET_IWMMXT_ABI)
5038 pcum->iwmmxt_nregs += 1;
5040 pcum->nregs += ARM_NUM_REGS2 (mode, type);
5044 /* Variable sized types are passed by reference. This is a GCC
5045 extension to the ARM ABI. */
5048 arm_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5049 enum machine_mode mode ATTRIBUTE_UNUSED,
5050 const_tree type, bool named ATTRIBUTE_UNUSED)
5052 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
5055 /* Encode the current state of the #pragma [no_]long_calls. */
5058 OFF, /* No #pragma [no_]long_calls is in effect. */
5059 LONG, /* #pragma long_calls is in effect. */
5060 SHORT /* #pragma no_long_calls is in effect. */
5063 static arm_pragma_enum arm_pragma_long_calls = OFF;
5066 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
5068 arm_pragma_long_calls = LONG;
5072 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
5074 arm_pragma_long_calls = SHORT;
5078 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
5080 arm_pragma_long_calls = OFF;
5083 /* Handle an attribute requiring a FUNCTION_DECL;
5084 arguments as in struct attribute_spec.handler. */
5086 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
5087 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
5089 if (TREE_CODE (*node) != FUNCTION_DECL)
5091 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5093 *no_add_attrs = true;
5099 /* Handle an "interrupt" or "isr" attribute;
5100 arguments as in struct attribute_spec.handler. */
5102 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
5107 if (TREE_CODE (*node) != FUNCTION_DECL)
5109 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5111 *no_add_attrs = true;
5113 /* FIXME: the argument if any is checked for type attributes;
5114 should it be checked for decl ones? */
5118 if (TREE_CODE (*node) == FUNCTION_TYPE
5119 || TREE_CODE (*node) == METHOD_TYPE)
5121 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
5123 warning (OPT_Wattributes, "%qE attribute ignored",
5125 *no_add_attrs = true;
5128 else if (TREE_CODE (*node) == POINTER_TYPE
5129 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
5130 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
5131 && arm_isr_value (args) != ARM_FT_UNKNOWN)
5133 *node = build_variant_type_copy (*node);
5134 TREE_TYPE (*node) = build_type_attribute_variant
5136 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
5137 *no_add_attrs = true;
5141 /* Possibly pass this attribute on from the type to a decl. */
5142 if (flags & ((int) ATTR_FLAG_DECL_NEXT
5143 | (int) ATTR_FLAG_FUNCTION_NEXT
5144 | (int) ATTR_FLAG_ARRAY_NEXT))
5146 *no_add_attrs = true;
5147 return tree_cons (name, args, NULL_TREE);
5151 warning (OPT_Wattributes, "%qE attribute ignored",
5160 /* Handle a "pcs" attribute; arguments as in struct
5161 attribute_spec.handler. */
5163 arm_handle_pcs_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
5164 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
5166 if (arm_pcs_from_attribute (args) == ARM_PCS_UNKNOWN)
5168 warning (OPT_Wattributes, "%qE attribute ignored", name);
5169 *no_add_attrs = true;
5174 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
5175 /* Handle the "notshared" attribute. This attribute is another way of
5176 requesting hidden visibility. ARM's compiler supports
5177 "__declspec(notshared)"; we support the same thing via an
5181 arm_handle_notshared_attribute (tree *node,
5182 tree name ATTRIBUTE_UNUSED,
5183 tree args ATTRIBUTE_UNUSED,
5184 int flags ATTRIBUTE_UNUSED,
5187 tree decl = TYPE_NAME (*node);
5191 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
5192 DECL_VISIBILITY_SPECIFIED (decl) = 1;
5193 *no_add_attrs = false;
5199 /* Return 0 if the attributes for two types are incompatible, 1 if they
5200 are compatible, and 2 if they are nearly compatible (which causes a
5201 warning to be generated). */
5203 arm_comp_type_attributes (const_tree type1, const_tree type2)
5207 /* Check for mismatch of non-default calling convention. */
5208 if (TREE_CODE (type1) != FUNCTION_TYPE)
5211 /* Check for mismatched call attributes. */
5212 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
5213 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
5214 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
5215 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
5217 /* Only bother to check if an attribute is defined. */
5218 if (l1 | l2 | s1 | s2)
5220 /* If one type has an attribute, the other must have the same attribute. */
5221 if ((l1 != l2) || (s1 != s2))
5224 /* Disallow mixed attributes. */
5225 if ((l1 & s2) || (l2 & s1))
5229 /* Check for mismatched ISR attribute. */
5230 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
5232 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
5233 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
5235 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
5242 /* Assigns default attributes to newly defined type. This is used to
5243 set short_call/long_call attributes for function types of
5244 functions defined inside corresponding #pragma scopes. */
5246 arm_set_default_type_attributes (tree type)
5248 /* Add __attribute__ ((long_call)) to all functions, when
5249 inside #pragma long_calls or __attribute__ ((short_call)),
5250 when inside #pragma no_long_calls. */
5251 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
5253 tree type_attr_list, attr_name;
5254 type_attr_list = TYPE_ATTRIBUTES (type);
5256 if (arm_pragma_long_calls == LONG)
5257 attr_name = get_identifier ("long_call");
5258 else if (arm_pragma_long_calls == SHORT)
5259 attr_name = get_identifier ("short_call");
5263 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
5264 TYPE_ATTRIBUTES (type) = type_attr_list;
5268 /* Return true if DECL is known to be linked into section SECTION. */
5271 arm_function_in_section_p (tree decl, section *section)
5273 /* We can only be certain about functions defined in the same
5274 compilation unit. */
5275 if (!TREE_STATIC (decl))
5278 /* Make sure that SYMBOL always binds to the definition in this
5279 compilation unit. */
5280 if (!targetm.binds_local_p (decl))
5283 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
5284 if (!DECL_SECTION_NAME (decl))
5286 /* Make sure that we will not create a unique section for DECL. */
5287 if (flag_function_sections || DECL_ONE_ONLY (decl))
5291 return function_section (decl) == section;
5294 /* Return nonzero if a 32-bit "long_call" should be generated for
5295 a call from the current function to DECL. We generate a long_call
5298 a. has an __attribute__((long call))
5299 or b. is within the scope of a #pragma long_calls
5300 or c. the -mlong-calls command line switch has been specified
5302 However we do not generate a long call if the function:
5304 d. has an __attribute__ ((short_call))
5305 or e. is inside the scope of a #pragma no_long_calls
5306 or f. is defined in the same section as the current function. */
5309 arm_is_long_call_p (tree decl)
5314 return TARGET_LONG_CALLS;
5316 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
5317 if (lookup_attribute ("short_call", attrs))
5320 /* For "f", be conservative, and only cater for cases in which the
5321 whole of the current function is placed in the same section. */
5322 if (!flag_reorder_blocks_and_partition
5323 && TREE_CODE (decl) == FUNCTION_DECL
5324 && arm_function_in_section_p (decl, current_function_section ()))
5327 if (lookup_attribute ("long_call", attrs))
5330 return TARGET_LONG_CALLS;
5333 /* Return nonzero if it is ok to make a tail-call to DECL. */
5335 arm_function_ok_for_sibcall (tree decl, tree exp)
5337 unsigned long func_type;
5339 if (cfun->machine->sibcall_blocked)
5342 /* Never tailcall something for which we have no decl, or if we
5343 are generating code for Thumb-1. */
5344 if (decl == NULL || TARGET_THUMB1)
5347 /* The PIC register is live on entry to VxWorks PLT entries, so we
5348 must make the call before restoring the PIC register. */
5349 if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
5352 /* Cannot tail-call to long calls, since these are out of range of
5353 a branch instruction. */
5354 if (arm_is_long_call_p (decl))
5357 /* If we are interworking and the function is not declared static
5358 then we can't tail-call it unless we know that it exists in this
5359 compilation unit (since it might be a Thumb routine). */
5360 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
5363 func_type = arm_current_func_type ();
5364 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
5365 if (IS_INTERRUPT (func_type))
5368 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
5370 /* Check that the return value locations are the same. For
5371 example that we aren't returning a value from the sibling in
5372 a VFP register but then need to transfer it to a core
5376 a = arm_function_value (TREE_TYPE (exp), decl, false);
5377 b = arm_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
5379 if (!rtx_equal_p (a, b))
5383 /* Never tailcall if function may be called with a misaligned SP. */
5384 if (IS_STACKALIGN (func_type))
5387 /* The AAPCS says that, on bare-metal, calls to unresolved weak
5388 references should become a NOP. Don't convert such calls into
5390 if (TARGET_AAPCS_BASED
5391 && arm_abi == ARM_ABI_AAPCS
5392 && DECL_WEAK (decl))
5395 /* Everything else is ok. */
5400 /* Addressing mode support functions. */
5402 /* Return nonzero if X is a legitimate immediate operand when compiling
5403 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
5405 legitimate_pic_operand_p (rtx x)
5407 if (GET_CODE (x) == SYMBOL_REF
5408 || (GET_CODE (x) == CONST
5409 && GET_CODE (XEXP (x, 0)) == PLUS
5410 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5416 /* Record that the current function needs a PIC register. Initialize
5417 cfun->machine->pic_reg if we have not already done so. */
5420 require_pic_register (void)
5422 /* A lot of the logic here is made obscure by the fact that this
5423 routine gets called as part of the rtx cost estimation process.
5424 We don't want those calls to affect any assumptions about the real
5425 function; and further, we can't call entry_of_function() until we
5426 start the real expansion process. */
5427 if (!crtl->uses_pic_offset_table)
5429 gcc_assert (can_create_pseudo_p ());
5430 if (arm_pic_register != INVALID_REGNUM)
5432 if (!cfun->machine->pic_reg)
5433 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
5435 /* Play games to avoid marking the function as needing pic
5436 if we are being called as part of the cost-estimation
5438 if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl)
5439 crtl->uses_pic_offset_table = 1;
5445 if (!cfun->machine->pic_reg)
5446 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
5448 /* Play games to avoid marking the function as needing pic
5449 if we are being called as part of the cost-estimation
5451 if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl)
5453 crtl->uses_pic_offset_table = 1;
5456 arm_load_pic_register (0UL);
5461 for (insn = seq; insn; insn = NEXT_INSN (insn))
5463 INSN_LOCATION (insn) = prologue_location;
5465 /* We can be called during expansion of PHI nodes, where
5466 we can't yet emit instructions directly in the final
5467 insn stream. Queue the insns on the entry edge, they will
5468 be committed after everything else is expanded. */
5469 insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
5476 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
5478 if (GET_CODE (orig) == SYMBOL_REF
5479 || GET_CODE (orig) == LABEL_REF)
5485 gcc_assert (can_create_pseudo_p ());
5486 reg = gen_reg_rtx (Pmode);
5489 /* VxWorks does not impose a fixed gap between segments; the run-time
5490 gap can be different from the object-file gap. We therefore can't
5491 use GOTOFF unless we are absolutely sure that the symbol is in the
5492 same segment as the GOT. Unfortunately, the flexibility of linker
5493 scripts means that we can't be sure of that in general, so assume
5494 that GOTOFF is never valid on VxWorks. */
5495 if ((GET_CODE (orig) == LABEL_REF
5496 || (GET_CODE (orig) == SYMBOL_REF &&
5497 SYMBOL_REF_LOCAL_P (orig)))
5499 && !TARGET_VXWORKS_RTP)
5500 insn = arm_pic_static_addr (orig, reg);
5506 /* If this function doesn't have a pic register, create one now. */
5507 require_pic_register ();
5509 pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig);
5511 /* Make the MEM as close to a constant as possible. */
5512 mem = SET_SRC (pat);
5513 gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem));
5514 MEM_READONLY_P (mem) = 1;
5515 MEM_NOTRAP_P (mem) = 1;
5517 insn = emit_insn (pat);
5520 /* Put a REG_EQUAL note on this insn, so that it can be optimized
5522 set_unique_reg_note (insn, REG_EQUAL, orig);
5526 else if (GET_CODE (orig) == CONST)
5530 if (GET_CODE (XEXP (orig, 0)) == PLUS
5531 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
5534 /* Handle the case where we have: const (UNSPEC_TLS). */
5535 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
5536 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
5539 /* Handle the case where we have:
5540 const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a
5542 if (GET_CODE (XEXP (orig, 0)) == PLUS
5543 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC
5544 && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS)
5546 gcc_assert (CONST_INT_P (XEXP (XEXP (orig, 0), 1)));
5552 gcc_assert (can_create_pseudo_p ());
5553 reg = gen_reg_rtx (Pmode);
5556 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
5558 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
5559 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
5560 base == reg ? 0 : reg);
5562 if (CONST_INT_P (offset))
5564 /* The base register doesn't really matter, we only want to
5565 test the index for the appropriate mode. */
5566 if (!arm_legitimate_index_p (mode, offset, SET, 0))
5568 gcc_assert (can_create_pseudo_p ());
5569 offset = force_reg (Pmode, offset);
5572 if (CONST_INT_P (offset))
5573 return plus_constant (Pmode, base, INTVAL (offset));
5576 if (GET_MODE_SIZE (mode) > 4
5577 && (GET_MODE_CLASS (mode) == MODE_INT
5578 || TARGET_SOFT_FLOAT))
5580 emit_insn (gen_addsi3 (reg, base, offset));
5584 return gen_rtx_PLUS (Pmode, base, offset);
5591 /* Find a spare register to use during the prolog of a function. */
5594 thumb_find_work_register (unsigned long pushed_regs_mask)
5598 /* Check the argument registers first as these are call-used. The
5599 register allocation order means that sometimes r3 might be used
5600 but earlier argument registers might not, so check them all. */
5601 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
5602 if (!df_regs_ever_live_p (reg))
5605 /* Before going on to check the call-saved registers we can try a couple
5606 more ways of deducing that r3 is available. The first is when we are
5607 pushing anonymous arguments onto the stack and we have less than 4
5608 registers worth of fixed arguments(*). In this case r3 will be part of
5609 the variable argument list and so we can be sure that it will be
5610 pushed right at the start of the function. Hence it will be available
5611 for the rest of the prologue.
5612 (*): ie crtl->args.pretend_args_size is greater than 0. */
5613 if (cfun->machine->uses_anonymous_args
5614 && crtl->args.pretend_args_size > 0)
5615 return LAST_ARG_REGNUM;
5617 /* The other case is when we have fixed arguments but less than 4 registers
5618 worth. In this case r3 might be used in the body of the function, but
5619 it is not being used to convey an argument into the function. In theory
5620 we could just check crtl->args.size to see how many bytes are
5621 being passed in argument registers, but it seems that it is unreliable.
5622 Sometimes it will have the value 0 when in fact arguments are being
5623 passed. (See testcase execute/20021111-1.c for an example). So we also
5624 check the args_info.nregs field as well. The problem with this field is
5625 that it makes no allowances for arguments that are passed to the
5626 function but which are not used. Hence we could miss an opportunity
5627 when a function has an unused argument in r3. But it is better to be
5628 safe than to be sorry. */
5629 if (! cfun->machine->uses_anonymous_args
5630 && crtl->args.size >= 0
5631 && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
5632 && (TARGET_AAPCS_BASED
5633 ? crtl->args.info.aapcs_ncrn < 4
5634 : crtl->args.info.nregs < 4))
5635 return LAST_ARG_REGNUM;
5637 /* Otherwise look for a call-saved register that is going to be pushed. */
5638 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
5639 if (pushed_regs_mask & (1 << reg))
5644 /* Thumb-2 can use high regs. */
5645 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
5646 if (pushed_regs_mask & (1 << reg))
5649 /* Something went wrong - thumb_compute_save_reg_mask()
5650 should have arranged for a suitable register to be pushed. */
5654 static GTY(()) int pic_labelno;
5656 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
5660 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
5662 rtx l1, labelno, pic_tmp, pic_rtx, pic_reg;
5664 if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
5667 gcc_assert (flag_pic);
5669 pic_reg = cfun->machine->pic_reg;
5670 if (TARGET_VXWORKS_RTP)
5672 pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
5673 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
5674 emit_insn (gen_pic_load_addr_32bit (pic_reg, pic_rtx));
5676 emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg)));
5678 pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5679 emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp));
5683 /* We use an UNSPEC rather than a LABEL_REF because this label
5684 never appears in the code stream. */
5686 labelno = GEN_INT (pic_labelno++);
5687 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
5688 l1 = gen_rtx_CONST (VOIDmode, l1);
5690 /* On the ARM the PC register contains 'dot + 8' at the time of the
5691 addition, on the Thumb it is 'dot + 4'. */
5692 pic_rtx = plus_constant (Pmode, l1, TARGET_ARM ? 8 : 4);
5693 pic_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, pic_rtx),
5695 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
5699 emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));
5701 else /* TARGET_THUMB1 */
5703 if (arm_pic_register != INVALID_REGNUM
5704 && REGNO (pic_reg) > LAST_LO_REGNUM)
5706 /* We will have pushed the pic register, so we should always be
5707 able to find a work register. */
5708 pic_tmp = gen_rtx_REG (SImode,
5709 thumb_find_work_register (saved_regs));
5710 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
5711 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
5712 emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
5715 emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno));
5719 /* Need to emit this whether or not we obey regdecls,
5720 since setjmp/longjmp can cause life info to screw up. */
5724 /* Generate code to load the address of a static var when flag_pic is set. */
5726 arm_pic_static_addr (rtx orig, rtx reg)
5728 rtx l1, labelno, offset_rtx, insn;
5730 gcc_assert (flag_pic);
5732 /* We use an UNSPEC rather than a LABEL_REF because this label
5733 never appears in the code stream. */
5734 labelno = GEN_INT (pic_labelno++);
5735 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
5736 l1 = gen_rtx_CONST (VOIDmode, l1);
5738 /* On the ARM the PC register contains 'dot + 8' at the time of the
5739 addition, on the Thumb it is 'dot + 4'. */
5740 offset_rtx = plus_constant (Pmode, l1, TARGET_ARM ? 8 : 4);
5741 offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx),
5742 UNSPEC_SYMBOL_OFFSET);
5743 offset_rtx = gen_rtx_CONST (Pmode, offset_rtx);
5745 insn = emit_insn (gen_pic_load_addr_unified (reg, offset_rtx, labelno));
5749 /* Return nonzero if X is valid as an ARM state addressing register. */
5751 arm_address_register_rtx_p (rtx x, int strict_p)
5761 return ARM_REGNO_OK_FOR_BASE_P (regno);
5763 return (regno <= LAST_ARM_REGNUM
5764 || regno >= FIRST_PSEUDO_REGISTER
5765 || regno == FRAME_POINTER_REGNUM
5766 || regno == ARG_POINTER_REGNUM);
5769 /* Return TRUE if this rtx is the difference of a symbol and a label,
5770 and will reduce to a PC-relative relocation in the object file.
5771 Expressions like this can be left alone when generating PIC, rather
5772 than forced through the GOT. */
5774 pcrel_constant_p (rtx x)
5776 if (GET_CODE (x) == MINUS)
5777 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
5782 /* Return true if X will surely end up in an index register after next
5785 will_be_in_index_register (const_rtx x)
5787 /* arm.md: calculate_pic_address will split this into a register. */
5788 return GET_CODE (x) == UNSPEC && (XINT (x, 1) == UNSPEC_PIC_SYM);
5791 /* Return nonzero if X is a valid ARM state address operand. */
5793 arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer,
5797 enum rtx_code code = GET_CODE (x);
5799 if (arm_address_register_rtx_p (x, strict_p))
5802 use_ldrd = (TARGET_LDRD
5804 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
5806 if (code == POST_INC || code == PRE_DEC
5807 || ((code == PRE_INC || code == POST_DEC)
5808 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
5809 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
5811 else if ((code == POST_MODIFY || code == PRE_MODIFY)
5812 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
5813 && GET_CODE (XEXP (x, 1)) == PLUS
5814 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5816 rtx addend = XEXP (XEXP (x, 1), 1);
5818 /* Don't allow ldrd post increment by register because it's hard
5819 to fixup invalid register choices. */
5821 && GET_CODE (x) == POST_MODIFY
5825 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
5826 && arm_legitimate_index_p (mode, addend, outer, strict_p));
5829 /* After reload constants split into minipools will have addresses
5830 from a LABEL_REF. */
5831 else if (reload_completed
5832 && (code == LABEL_REF
5834 && GET_CODE (XEXP (x, 0)) == PLUS
5835 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
5836 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
5839 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
5842 else if (code == PLUS)
5844 rtx xop0 = XEXP (x, 0);
5845 rtx xop1 = XEXP (x, 1);
5847 return ((arm_address_register_rtx_p (xop0, strict_p)
5848 && ((CONST_INT_P (xop1)
5849 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
5850 || (!strict_p && will_be_in_index_register (xop1))))
5851 || (arm_address_register_rtx_p (xop1, strict_p)
5852 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
5856 /* Reload currently can't handle MINUS, so disable this for now */
5857 else if (GET_CODE (x) == MINUS)
5859 rtx xop0 = XEXP (x, 0);
5860 rtx xop1 = XEXP (x, 1);
5862 return (arm_address_register_rtx_p (xop0, strict_p)
5863 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
5867 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
5868 && code == SYMBOL_REF
5869 && CONSTANT_POOL_ADDRESS_P (x)
5871 && symbol_mentioned_p (get_pool_constant (x))
5872 && ! pcrel_constant_p (get_pool_constant (x))))
5878 /* Return nonzero if X is a valid Thumb-2 address operand. */
5880 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
5883 enum rtx_code code = GET_CODE (x);
5885 if (arm_address_register_rtx_p (x, strict_p))
5888 use_ldrd = (TARGET_LDRD
5890 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
5892 if (code == POST_INC || code == PRE_DEC
5893 || ((code == PRE_INC || code == POST_DEC)
5894 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
5895 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
5897 else if ((code == POST_MODIFY || code == PRE_MODIFY)
5898 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
5899 && GET_CODE (XEXP (x, 1)) == PLUS
5900 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5902 /* Thumb-2 only has autoincrement by constant. */
5903 rtx addend = XEXP (XEXP (x, 1), 1);
5904 HOST_WIDE_INT offset;
5906 if (!CONST_INT_P (addend))
5909 offset = INTVAL(addend);
5910 if (GET_MODE_SIZE (mode) <= 4)
5911 return (offset > -256 && offset < 256);
5913 return (use_ldrd && offset > -1024 && offset < 1024
5914 && (offset & 3) == 0);
5917 /* After reload constants split into minipools will have addresses
5918 from a LABEL_REF. */
5919 else if (reload_completed
5920 && (code == LABEL_REF
5922 && GET_CODE (XEXP (x, 0)) == PLUS
5923 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
5924 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
5927 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
5930 else if (code == PLUS)
5932 rtx xop0 = XEXP (x, 0);
5933 rtx xop1 = XEXP (x, 1);
5935 return ((arm_address_register_rtx_p (xop0, strict_p)
5936 && (thumb2_legitimate_index_p (mode, xop1, strict_p)
5937 || (!strict_p && will_be_in_index_register (xop1))))
5938 || (arm_address_register_rtx_p (xop1, strict_p)
5939 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
5942 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
5943 && code == SYMBOL_REF
5944 && CONSTANT_POOL_ADDRESS_P (x)
5946 && symbol_mentioned_p (get_pool_constant (x))
5947 && ! pcrel_constant_p (get_pool_constant (x))))
5953 /* Return nonzero if INDEX is valid for an address index operand in
5956 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
5959 HOST_WIDE_INT range;
5960 enum rtx_code code = GET_CODE (index);
5962 /* Standard coprocessor addressing modes. */
5963 if (TARGET_HARD_FLOAT
5965 && (mode == SFmode || mode == DFmode))
5966 return (code == CONST_INT && INTVAL (index) < 1024
5967 && INTVAL (index) > -1024
5968 && (INTVAL (index) & 3) == 0);
5970 /* For quad modes, we restrict the constant offset to be slightly less
5971 than what the instruction format permits. We do this because for
5972 quad mode moves, we will actually decompose them into two separate
5973 double-mode reads or writes. INDEX must therefore be a valid
5974 (double-mode) offset and so should INDEX+8. */
5975 if (TARGET_NEON && VALID_NEON_QREG_MODE (mode))
5976 return (code == CONST_INT
5977 && INTVAL (index) < 1016
5978 && INTVAL (index) > -1024
5979 && (INTVAL (index) & 3) == 0);
5981 /* We have no such constraint on double mode offsets, so we permit the
5982 full range of the instruction format. */
5983 if (TARGET_NEON && VALID_NEON_DREG_MODE (mode))
5984 return (code == CONST_INT
5985 && INTVAL (index) < 1024
5986 && INTVAL (index) > -1024
5987 && (INTVAL (index) & 3) == 0);
5989 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
5990 return (code == CONST_INT
5991 && INTVAL (index) < 1024
5992 && INTVAL (index) > -1024
5993 && (INTVAL (index) & 3) == 0);
5995 if (arm_address_register_rtx_p (index, strict_p)
5996 && (GET_MODE_SIZE (mode) <= 4))
5999 if (mode == DImode || mode == DFmode)
6001 if (code == CONST_INT)
6003 HOST_WIDE_INT val = INTVAL (index);
6006 return val > -256 && val < 256;
6008 return val > -4096 && val < 4092;
6011 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
6014 if (GET_MODE_SIZE (mode) <= 4
6018 || (mode == QImode && outer == SIGN_EXTEND))))
6022 rtx xiop0 = XEXP (index, 0);
6023 rtx xiop1 = XEXP (index, 1);
6025 return ((arm_address_register_rtx_p (xiop0, strict_p)
6026 && power_of_two_operand (xiop1, SImode))
6027 || (arm_address_register_rtx_p (xiop1, strict_p)
6028 && power_of_two_operand (xiop0, SImode)));
6030 else if (code == LSHIFTRT || code == ASHIFTRT
6031 || code == ASHIFT || code == ROTATERT)
6033 rtx op = XEXP (index, 1);
6035 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
6038 && INTVAL (op) <= 31);
6042 /* For ARM v4 we may be doing a sign-extend operation during the
6048 || (outer == SIGN_EXTEND && mode == QImode))
6054 range = (mode == HImode || mode == HFmode) ? 4095 : 4096;
6056 return (code == CONST_INT
6057 && INTVAL (index) < range
6058 && INTVAL (index) > -range);
6061 /* Return true if OP is a valid index scaling factor for Thumb-2 address
6062 index operand. i.e. 1, 2, 4 or 8. */
6064 thumb2_index_mul_operand (rtx op)
6068 if (!CONST_INT_P (op))
6072 return (val == 1 || val == 2 || val == 4 || val == 8);
6075 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
6077 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
6079 enum rtx_code code = GET_CODE (index);
6081 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
6082 /* Standard coprocessor addressing modes. */
6083 if (TARGET_HARD_FLOAT
6085 && (mode == SFmode || mode == DFmode))
6086 return (code == CONST_INT && INTVAL (index) < 1024
6087 /* Thumb-2 allows only > -256 index range for it's core register
6088 load/stores. Since we allow SF/DF in core registers, we have
6089 to use the intersection between -256~4096 (core) and -1024~1024
6091 && INTVAL (index) > -256
6092 && (INTVAL (index) & 3) == 0);
6094 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
6096 /* For DImode assume values will usually live in core regs
6097 and only allow LDRD addressing modes. */
6098 if (!TARGET_LDRD || mode != DImode)
6099 return (code == CONST_INT
6100 && INTVAL (index) < 1024
6101 && INTVAL (index) > -1024
6102 && (INTVAL (index) & 3) == 0);
6105 /* For quad modes, we restrict the constant offset to be slightly less
6106 than what the instruction format permits. We do this because for
6107 quad mode moves, we will actually decompose them into two separate
6108 double-mode reads or writes. INDEX must therefore be a valid
6109 (double-mode) offset and so should INDEX+8. */
6110 if (TARGET_NEON && VALID_NEON_QREG_MODE (mode))
6111 return (code == CONST_INT
6112 && INTVAL (index) < 1016
6113 && INTVAL (index) > -1024
6114 && (INTVAL (index) & 3) == 0);
6116 /* We have no such constraint on double mode offsets, so we permit the
6117 full range of the instruction format. */
6118 if (TARGET_NEON && VALID_NEON_DREG_MODE (mode))
6119 return (code == CONST_INT
6120 && INTVAL (index) < 1024
6121 && INTVAL (index) > -1024
6122 && (INTVAL (index) & 3) == 0);
6124 if (arm_address_register_rtx_p (index, strict_p)
6125 && (GET_MODE_SIZE (mode) <= 4))
6128 if (mode == DImode || mode == DFmode)
6130 if (code == CONST_INT)
6132 HOST_WIDE_INT val = INTVAL (index);
6133 /* ??? Can we assume ldrd for thumb2? */
6134 /* Thumb-2 ldrd only has reg+const addressing modes. */
6135 /* ldrd supports offsets of +-1020.
6136 However the ldr fallback does not. */
6137 return val > -256 && val < 256 && (val & 3) == 0;
6145 rtx xiop0 = XEXP (index, 0);
6146 rtx xiop1 = XEXP (index, 1);
6148 return ((arm_address_register_rtx_p (xiop0, strict_p)
6149 && thumb2_index_mul_operand (xiop1))
6150 || (arm_address_register_rtx_p (xiop1, strict_p)
6151 && thumb2_index_mul_operand (xiop0)));
6153 else if (code == ASHIFT)
6155 rtx op = XEXP (index, 1);
6157 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
6160 && INTVAL (op) <= 3);
6163 return (code == CONST_INT
6164 && INTVAL (index) < 4096
6165 && INTVAL (index) > -256);
6168 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
6170 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
6180 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
6182 return (regno <= LAST_LO_REGNUM
6183 || regno > LAST_VIRTUAL_REGISTER
6184 || regno == FRAME_POINTER_REGNUM
6185 || (GET_MODE_SIZE (mode) >= 4
6186 && (regno == STACK_POINTER_REGNUM
6187 || regno >= FIRST_PSEUDO_REGISTER
6188 || x == hard_frame_pointer_rtx
6189 || x == arg_pointer_rtx)));
6192 /* Return nonzero if x is a legitimate index register. This is the case
6193 for any base register that can access a QImode object. */
6195 thumb1_index_register_rtx_p (rtx x, int strict_p)
6197 return thumb1_base_register_rtx_p (x, QImode, strict_p);
6200 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
6202 The AP may be eliminated to either the SP or the FP, so we use the
6203 least common denominator, e.g. SImode, and offsets from 0 to 64.
6205 ??? Verify whether the above is the right approach.
6207 ??? Also, the FP may be eliminated to the SP, so perhaps that
6208 needs special handling also.
6210 ??? Look at how the mips16 port solves this problem. It probably uses
6211 better ways to solve some of these problems.
6213 Although it is not incorrect, we don't accept QImode and HImode
6214 addresses based on the frame pointer or arg pointer until the
6215 reload pass starts. This is so that eliminating such addresses
6216 into stack based ones won't produce impossible code. */
6218 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
6220 /* ??? Not clear if this is right. Experiment. */
6221 if (GET_MODE_SIZE (mode) < 4
6222 && !(reload_in_progress || reload_completed)
6223 && (reg_mentioned_p (frame_pointer_rtx, x)
6224 || reg_mentioned_p (arg_pointer_rtx, x)
6225 || reg_mentioned_p (virtual_incoming_args_rtx, x)
6226 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
6227 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
6228 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
6231 /* Accept any base register. SP only in SImode or larger. */
6232 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
6235 /* This is PC relative data before arm_reorg runs. */
6236 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
6237 && GET_CODE (x) == SYMBOL_REF
6238 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
6241 /* This is PC relative data after arm_reorg runs. */
6242 else if ((GET_MODE_SIZE (mode) >= 4 || mode == HFmode)
6244 && (GET_CODE (x) == LABEL_REF
6245 || (GET_CODE (x) == CONST
6246 && GET_CODE (XEXP (x, 0)) == PLUS
6247 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
6248 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
6251 /* Post-inc indexing only supported for SImode and larger. */
6252 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
6253 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
6256 else if (GET_CODE (x) == PLUS)
6258 /* REG+REG address can be any two index registers. */
6259 /* We disallow FRAME+REG addressing since we know that FRAME
6260 will be replaced with STACK, and SP relative addressing only
6261 permits SP+OFFSET. */
6262 if (GET_MODE_SIZE (mode) <= 4
6263 && XEXP (x, 0) != frame_pointer_rtx
6264 && XEXP (x, 1) != frame_pointer_rtx
6265 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
6266 && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)
6267 || (!strict_p && will_be_in_index_register (XEXP (x, 1)))))
6270 /* REG+const has 5-7 bit offset for non-SP registers. */
6271 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
6272 || XEXP (x, 0) == arg_pointer_rtx)
6273 && CONST_INT_P (XEXP (x, 1))
6274 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
6277 /* REG+const has 10-bit offset for SP, but only SImode and
6278 larger is supported. */
6279 /* ??? Should probably check for DI/DFmode overflow here
6280 just like GO_IF_LEGITIMATE_OFFSET does. */
6281 else if (REG_P (XEXP (x, 0))
6282 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
6283 && GET_MODE_SIZE (mode) >= 4
6284 && CONST_INT_P (XEXP (x, 1))
6285 && INTVAL (XEXP (x, 1)) >= 0
6286 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
6287 && (INTVAL (XEXP (x, 1)) & 3) == 0)
6290 else if (REG_P (XEXP (x, 0))
6291 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
6292 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
6293 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
6294 && REGNO (XEXP (x, 0))
6295 <= LAST_VIRTUAL_POINTER_REGISTER))
6296 && GET_MODE_SIZE (mode) >= 4
6297 && CONST_INT_P (XEXP (x, 1))
6298 && (INTVAL (XEXP (x, 1)) & 3) == 0)
6302 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
6303 && GET_MODE_SIZE (mode) == 4
6304 && GET_CODE (x) == SYMBOL_REF
6305 && CONSTANT_POOL_ADDRESS_P (x)
6307 && symbol_mentioned_p (get_pool_constant (x))
6308 && ! pcrel_constant_p (get_pool_constant (x))))
6314 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
6315 instruction of mode MODE. */
6317 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
6319 switch (GET_MODE_SIZE (mode))
6322 return val >= 0 && val < 32;
6325 return val >= 0 && val < 64 && (val & 1) == 0;
6329 && (val + GET_MODE_SIZE (mode)) <= 128
6335 arm_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
6338 return arm_legitimate_address_outer_p (mode, x, SET, strict_p);
6339 else if (TARGET_THUMB2)
6340 return thumb2_legitimate_address_p (mode, x, strict_p);
6341 else /* if (TARGET_THUMB1) */
6342 return thumb1_legitimate_address_p (mode, x, strict_p);
6345 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
6347 Given an rtx X being reloaded into a reg required to be
6348 in class CLASS, return the class of reg to actually use.
6349 In general this is just CLASS, but for the Thumb core registers and
6350 immediate constants we prefer a LO_REGS class or a subset. */
6353 arm_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
6359 if (rclass == GENERAL_REGS
6360 || rclass == HI_REGS
6361 || rclass == NO_REGS
6362 || rclass == STACK_REG)
6369 /* Build the SYMBOL_REF for __tls_get_addr. */
6371 static GTY(()) rtx tls_get_addr_libfunc;
6374 get_tls_get_addr (void)
6376 if (!tls_get_addr_libfunc)
6377 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
6378 return tls_get_addr_libfunc;
6382 arm_load_tp (rtx target)
6385 target = gen_reg_rtx (SImode);
6389 /* Can return in any reg. */
6390 emit_insn (gen_load_tp_hard (target));
6394 /* Always returned in r0. Immediately copy the result into a pseudo,
6395 otherwise other uses of r0 (e.g. setting up function arguments) may
6396 clobber the value. */
6400 emit_insn (gen_load_tp_soft ());
6402 tmp = gen_rtx_REG (SImode, 0);
6403 emit_move_insn (target, tmp);
6409 load_tls_operand (rtx x, rtx reg)
6413 if (reg == NULL_RTX)
6414 reg = gen_reg_rtx (SImode);
6416 tmp = gen_rtx_CONST (SImode, x);
6418 emit_move_insn (reg, tmp);
6424 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
6426 rtx insns, label, labelno, sum;
6428 gcc_assert (reloc != TLS_DESCSEQ);
6431 labelno = GEN_INT (pic_labelno++);
6432 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
6433 label = gen_rtx_CONST (VOIDmode, label);
6435 sum = gen_rtx_UNSPEC (Pmode,
6436 gen_rtvec (4, x, GEN_INT (reloc), label,
6437 GEN_INT (TARGET_ARM ? 8 : 4)),
6439 reg = load_tls_operand (sum, reg);
6442 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
6444 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
6446 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX,
6447 LCT_PURE, /* LCT_CONST? */
6448 Pmode, 1, reg, Pmode);
6450 insns = get_insns ();
6457 arm_tls_descseq_addr (rtx x, rtx reg)
6459 rtx labelno = GEN_INT (pic_labelno++);
6460 rtx label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
6461 rtx sum = gen_rtx_UNSPEC (Pmode,
6462 gen_rtvec (4, x, GEN_INT (TLS_DESCSEQ),
6463 gen_rtx_CONST (VOIDmode, label),
6464 GEN_INT (!TARGET_ARM)),
6466 rtx reg0 = load_tls_operand (sum, gen_rtx_REG (SImode, 0));
6468 emit_insn (gen_tlscall (x, labelno));
6470 reg = gen_reg_rtx (SImode);
6472 gcc_assert (REGNO (reg) != 0);
6474 emit_move_insn (reg, reg0);
6480 legitimize_tls_address (rtx x, rtx reg)
6482 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
6483 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
6487 case TLS_MODEL_GLOBAL_DYNAMIC:
6488 if (TARGET_GNU2_TLS)
6490 reg = arm_tls_descseq_addr (x, reg);
6492 tp = arm_load_tp (NULL_RTX);
6494 dest = gen_rtx_PLUS (Pmode, tp, reg);
6498 /* Original scheme */
6499 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
6500 dest = gen_reg_rtx (Pmode);
6501 emit_libcall_block (insns, dest, ret, x);
6505 case TLS_MODEL_LOCAL_DYNAMIC:
6506 if (TARGET_GNU2_TLS)
6508 reg = arm_tls_descseq_addr (x, reg);
6510 tp = arm_load_tp (NULL_RTX);
6512 dest = gen_rtx_PLUS (Pmode, tp, reg);
6516 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
6518 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
6519 share the LDM result with other LD model accesses. */
6520 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
6522 dest = gen_reg_rtx (Pmode);
6523 emit_libcall_block (insns, dest, ret, eqv);
6525 /* Load the addend. */
6526 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x,
6527 GEN_INT (TLS_LDO32)),
6529 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
6530 dest = gen_rtx_PLUS (Pmode, dest, addend);
6534 case TLS_MODEL_INITIAL_EXEC:
6535 labelno = GEN_INT (pic_labelno++);
6536 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
6537 label = gen_rtx_CONST (VOIDmode, label);
6538 sum = gen_rtx_UNSPEC (Pmode,
6539 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
6540 GEN_INT (TARGET_ARM ? 8 : 4)),
6542 reg = load_tls_operand (sum, reg);
6545 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
6546 else if (TARGET_THUMB2)
6547 emit_insn (gen_tls_load_dot_plus_four (reg, NULL, reg, labelno));
6550 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
6551 emit_move_insn (reg, gen_const_mem (SImode, reg));
6554 tp = arm_load_tp (NULL_RTX);
6556 return gen_rtx_PLUS (Pmode, tp, reg);
6558 case TLS_MODEL_LOCAL_EXEC:
6559 tp = arm_load_tp (NULL_RTX);
6561 reg = gen_rtx_UNSPEC (Pmode,
6562 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
6564 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
6566 return gen_rtx_PLUS (Pmode, tp, reg);
6573 /* Try machine-dependent ways of modifying an illegitimate address
6574 to be legitimate. If we find one, return the new, valid address. */
6576 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
6580 /* TODO: legitimize_address for Thumb2. */
6583 return thumb_legitimize_address (x, orig_x, mode);
6586 if (arm_tls_symbol_p (x))
6587 return legitimize_tls_address (x, NULL_RTX);
6589 if (GET_CODE (x) == PLUS)
6591 rtx xop0 = XEXP (x, 0);
6592 rtx xop1 = XEXP (x, 1);
6594 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
6595 xop0 = force_reg (SImode, xop0);
6597 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
6598 xop1 = force_reg (SImode, xop1);
6600 if (ARM_BASE_REGISTER_RTX_P (xop0)
6601 && CONST_INT_P (xop1))
6603 HOST_WIDE_INT n, low_n;
6607 /* VFP addressing modes actually allow greater offsets, but for
6608 now we just stick with the lowest common denominator. */
6610 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
6622 low_n = ((mode) == TImode ? 0
6623 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
6627 base_reg = gen_reg_rtx (SImode);
6628 val = force_operand (plus_constant (Pmode, xop0, n), NULL_RTX);
6629 emit_move_insn (base_reg, val);
6630 x = plus_constant (Pmode, base_reg, low_n);
6632 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
6633 x = gen_rtx_PLUS (SImode, xop0, xop1);
6636 /* XXX We don't allow MINUS any more -- see comment in
6637 arm_legitimate_address_outer_p (). */
6638 else if (GET_CODE (x) == MINUS)
6640 rtx xop0 = XEXP (x, 0);
6641 rtx xop1 = XEXP (x, 1);
6643 if (CONSTANT_P (xop0))
6644 xop0 = force_reg (SImode, xop0);
6646 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
6647 xop1 = force_reg (SImode, xop1);
6649 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
6650 x = gen_rtx_MINUS (SImode, xop0, xop1);
6653 /* Make sure to take full advantage of the pre-indexed addressing mode
6654 with absolute addresses which often allows for the base register to
6655 be factorized for multiple adjacent memory references, and it might
6656 even allows for the mini pool to be avoided entirely. */
6657 else if (CONST_INT_P (x) && optimize > 0)
6660 HOST_WIDE_INT mask, base, index;
6663 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
6664 use a 8-bit index. So let's use a 12-bit index for SImode only and
6665 hope that arm_gen_constant will enable ldrb to use more bits. */
6666 bits = (mode == SImode) ? 12 : 8;
6667 mask = (1 << bits) - 1;
6668 base = INTVAL (x) & ~mask;
6669 index = INTVAL (x) & mask;
6670 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
6672 /* It'll most probably be more efficient to generate the base
6673 with more bits set and use a negative index instead. */
6677 base_reg = force_reg (SImode, GEN_INT (base));
6678 x = plus_constant (Pmode, base_reg, index);
6683 /* We need to find and carefully transform any SYMBOL and LABEL
6684 references; so go back to the original address expression. */
6685 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
6687 if (new_x != orig_x)
6695 /* Try machine-dependent ways of modifying an illegitimate Thumb address
6696 to be legitimate. If we find one, return the new, valid address. */
6698 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
6700 if (arm_tls_symbol_p (x))
6701 return legitimize_tls_address (x, NULL_RTX);
6703 if (GET_CODE (x) == PLUS
6704 && CONST_INT_P (XEXP (x, 1))
6705 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
6706 || INTVAL (XEXP (x, 1)) < 0))
6708 rtx xop0 = XEXP (x, 0);
6709 rtx xop1 = XEXP (x, 1);
6710 HOST_WIDE_INT offset = INTVAL (xop1);
6712 /* Try and fold the offset into a biasing of the base register and
6713 then offsetting that. Don't do this when optimizing for space
6714 since it can cause too many CSEs. */
6715 if (optimize_size && offset >= 0
6716 && offset < 256 + 31 * GET_MODE_SIZE (mode))
6718 HOST_WIDE_INT delta;
6721 delta = offset - (256 - GET_MODE_SIZE (mode));
6722 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
6723 delta = 31 * GET_MODE_SIZE (mode);
6725 delta = offset & (~31 * GET_MODE_SIZE (mode));
6727 xop0 = force_operand (plus_constant (Pmode, xop0, offset - delta),
6729 x = plus_constant (Pmode, xop0, delta);
6731 else if (offset < 0 && offset > -256)
6732 /* Small negative offsets are best done with a subtract before the
6733 dereference, forcing these into a register normally takes two
6735 x = force_operand (x, NULL_RTX);
6738 /* For the remaining cases, force the constant into a register. */
6739 xop1 = force_reg (SImode, xop1);
6740 x = gen_rtx_PLUS (SImode, xop0, xop1);
6743 else if (GET_CODE (x) == PLUS
6744 && s_register_operand (XEXP (x, 1), SImode)
6745 && !s_register_operand (XEXP (x, 0), SImode))
6747 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
6749 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
6754 /* We need to find and carefully transform any SYMBOL and LABEL
6755 references; so go back to the original address expression. */
6756 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
6758 if (new_x != orig_x)
6766 arm_legitimize_reload_address (rtx *p,
6767 enum machine_mode mode,
6768 int opnum, int type,
6769 int ind_levels ATTRIBUTE_UNUSED)
6771 /* We must recognize output that we have already generated ourselves. */
6772 if (GET_CODE (*p) == PLUS
6773 && GET_CODE (XEXP (*p, 0)) == PLUS
6774 && REG_P (XEXP (XEXP (*p, 0), 0))
6775 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
6776 && CONST_INT_P (XEXP (*p, 1)))
6778 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
6779 MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
6780 VOIDmode, 0, 0, opnum, (enum reload_type) type);
6784 if (GET_CODE (*p) == PLUS
6785 && REG_P (XEXP (*p, 0))
6786 && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0)))
6787 /* If the base register is equivalent to a constant, let the generic
6788 code handle it. Otherwise we will run into problems if a future
6789 reload pass decides to rematerialize the constant. */
6790 && !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p, 0)))
6791 && CONST_INT_P (XEXP (*p, 1)))
6793 HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
6794 HOST_WIDE_INT low, high;
6796 /* Detect coprocessor load/stores. */
6797 bool coproc_p = ((TARGET_HARD_FLOAT
6799 && (mode == SFmode || mode == DFmode))
6800 || (TARGET_REALLY_IWMMXT
6801 && VALID_IWMMXT_REG_MODE (mode))
6803 && (VALID_NEON_DREG_MODE (mode)
6804 || VALID_NEON_QREG_MODE (mode))));
6806 /* For some conditions, bail out when lower two bits are unaligned. */
6807 if ((val & 0x3) != 0
6808 /* Coprocessor load/store indexes are 8-bits + '00' appended. */
6810 /* For DI, and DF under soft-float: */
6811 || ((mode == DImode || mode == DFmode)
6812 /* Without ldrd, we use stm/ldm, which does not
6813 fair well with unaligned bits. */
6815 /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
6816 || TARGET_THUMB2))))
6819 /* When breaking down a [reg+index] reload address into [(reg+high)+low],
6820 of which the (reg+high) gets turned into a reload add insn,
6821 we try to decompose the index into high/low values that can often
6822 also lead to better reload CSE.
6824 ldr r0, [r2, #4100] // Offset too large
6825 ldr r1, [r2, #4104] // Offset too large
6827 is best reloaded as:
6833 which post-reload CSE can simplify in most cases to eliminate the
6834 second add instruction:
6839 The idea here is that we want to split out the bits of the constant
6840 as a mask, rather than as subtracting the maximum offset that the
6841 respective type of load/store used can handle.
6843 When encountering negative offsets, we can still utilize it even if
6844 the overall offset is positive; sometimes this may lead to an immediate
6845 that can be constructed with fewer instructions.
6847 ldr r0, [r2, #0x3FFFFC]
6849 This is best reloaded as:
6850 add t1, r2, #0x400000
6853 The trick for spotting this for a load insn with N bits of offset
6854 (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
6855 negative offset that is going to make bit N and all the bits below
6856 it become zero in the remainder part.
6858 The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
6859 to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
6860 used in most cases of ARM load/store instructions. */
6862 #define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
6863 (((VAL) & ((1 << (N)) - 1)) \
6864 ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
6869 low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
6871 /* NEON quad-word load/stores are made of two double-word accesses,
6872 so the valid index range is reduced by 8. Treat as 9-bit range if
6874 if (TARGET_NEON && VALID_NEON_QREG_MODE (mode) && low >= 1016)
6875 low = SIGN_MAG_LOW_ADDR_BITS (val, 9);
6877 else if (GET_MODE_SIZE (mode) == 8)
6880 low = (TARGET_THUMB2
6881 ? SIGN_MAG_LOW_ADDR_BITS (val, 10)
6882 : SIGN_MAG_LOW_ADDR_BITS (val, 8));
6884 /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
6885 to access doublewords. The supported load/store offsets are
6886 -8, -4, and 4, which we try to produce here. */
6887 low = ((val & 0xf) ^ 0x8) - 0x8;
6889 else if (GET_MODE_SIZE (mode) < 8)
6891 /* NEON element load/stores do not have an offset. */
6892 if (TARGET_NEON_FP16 && mode == HFmode)
6897 /* Thumb-2 has an asymmetrical index range of (-256,4096).
6898 Try the wider 12-bit range first, and re-try if the result
6900 low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
6902 low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
6906 if (mode == HImode || mode == HFmode)
6909 low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
6912 /* The storehi/movhi_bytes fallbacks can use only
6913 [-4094,+4094] of the full ldrb/strb index range. */
6914 low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
6915 if (low == 4095 || low == -4095)
6920 low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
6926 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff)
6927 ^ (unsigned HOST_WIDE_INT) 0x80000000)
6928 - (unsigned HOST_WIDE_INT) 0x80000000);
6929 /* Check for overflow or zero */
6930 if (low == 0 || high == 0 || (high + low != val))
6933 /* Reload the high part into a base reg; leave the low part
6935 *p = gen_rtx_PLUS (GET_MODE (*p),
6936 gen_rtx_PLUS (GET_MODE (*p), XEXP (*p, 0),
6939 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
6940 MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
6941 VOIDmode, 0, 0, opnum, (enum reload_type) type);
6949 thumb_legitimize_reload_address (rtx *x_p,
6950 enum machine_mode mode,
6951 int opnum, int type,
6952 int ind_levels ATTRIBUTE_UNUSED)
6956 if (GET_CODE (x) == PLUS
6957 && GET_MODE_SIZE (mode) < 4
6958 && REG_P (XEXP (x, 0))
6959 && XEXP (x, 0) == stack_pointer_rtx
6960 && CONST_INT_P (XEXP (x, 1))
6961 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
6966 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
6967 Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type);
6971 /* If both registers are hi-regs, then it's better to reload the
6972 entire expression rather than each register individually. That
6973 only requires one reload register rather than two. */
6974 if (GET_CODE (x) == PLUS
6975 && REG_P (XEXP (x, 0))
6976 && REG_P (XEXP (x, 1))
6977 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
6978 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
6983 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
6984 Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type);
6991 /* Test for various thread-local symbols. */
6993 /* Return TRUE if X is a thread-local symbol. */
6996 arm_tls_symbol_p (rtx x)
6998 if (! TARGET_HAVE_TLS)
7001 if (GET_CODE (x) != SYMBOL_REF)
7004 return SYMBOL_REF_TLS_MODEL (x) != 0;
7007 /* Helper for arm_tls_referenced_p. */
7010 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7012 if (GET_CODE (*x) == SYMBOL_REF)
7013 return SYMBOL_REF_TLS_MODEL (*x) != 0;
7015 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
7016 TLS offsets, not real symbol references. */
7017 if (GET_CODE (*x) == UNSPEC
7018 && XINT (*x, 1) == UNSPEC_TLS)
7024 /* Return TRUE if X contains any TLS symbol references. */
7027 arm_tls_referenced_p (rtx x)
7029 if (! TARGET_HAVE_TLS)
7032 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
7035 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
7037 On the ARM, allow any integer (invalid ones are removed later by insn
7038 patterns), nice doubles and symbol_refs which refer to the function's
7041 When generating pic allow anything. */
7044 arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
7046 /* At present, we have no support for Neon structure constants, so forbid
7047 them here. It might be possible to handle simple cases like 0 and -1
7049 if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
7052 return flag_pic || !label_mentioned_p (x);
7056 thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
7058 return (CONST_INT_P (x)
7059 || CONST_DOUBLE_P (x)
7060 || CONSTANT_ADDRESS_P (x)
7065 arm_legitimate_constant_p (enum machine_mode mode, rtx x)
7067 return (!arm_cannot_force_const_mem (mode, x)
7069 ? arm_legitimate_constant_p_1 (mode, x)
7070 : thumb_legitimate_constant_p (mode, x)));
7073 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7076 arm_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
7080 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
7082 split_const (x, &base, &offset);
7083 if (GET_CODE (base) == SYMBOL_REF
7084 && !offset_within_block_p (base, INTVAL (offset)))
7087 return arm_tls_referenced_p (x);
7090 #define REG_OR_SUBREG_REG(X) \
7092 || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))))
7094 #define REG_OR_SUBREG_RTX(X) \
7095 (REG_P (X) ? (X) : SUBREG_REG (X))
7098 thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
7100 enum machine_mode mode = GET_MODE (x);
7114 return COSTS_N_INSNS (1);
7117 if (CONST_INT_P (XEXP (x, 1)))
7120 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
7127 return COSTS_N_INSNS (2) + cycles;
7129 return COSTS_N_INSNS (1) + 16;
7132 return (COSTS_N_INSNS (1)
7133 + 4 * ((MEM_P (SET_SRC (x)))
7134 + MEM_P (SET_DEST (x))));
7139 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
7141 if (thumb_shiftable_const (INTVAL (x)))
7142 return COSTS_N_INSNS (2);
7143 return COSTS_N_INSNS (3);
7145 else if ((outer == PLUS || outer == COMPARE)
7146 && INTVAL (x) < 256 && INTVAL (x) > -256)
7148 else if ((outer == IOR || outer == XOR || outer == AND)
7149 && INTVAL (x) < 256 && INTVAL (x) >= -256)
7150 return COSTS_N_INSNS (1);
7151 else if (outer == AND)
7154 /* This duplicates the tests in the andsi3 expander. */
7155 for (i = 9; i <= 31; i++)
7156 if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
7157 || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
7158 return COSTS_N_INSNS (2);
7160 else if (outer == ASHIFT || outer == ASHIFTRT
7161 || outer == LSHIFTRT)
7163 return COSTS_N_INSNS (2);
7169 return COSTS_N_INSNS (3);
7187 /* XXX another guess. */
7188 /* Memory costs quite a lot for the first word, but subsequent words
7189 load at the equivalent of a single insn each. */
7190 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
7191 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
7196 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
7202 total = mode == DImode ? COSTS_N_INSNS (1) : 0;
7203 total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code);
7209 return total + COSTS_N_INSNS (1);
7211 /* Assume a two-shift sequence. Increase the cost slightly so
7212 we prefer actual shifts over an extend operation. */
7213 return total + 1 + COSTS_N_INSNS (2);
7221 arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
7223 enum machine_mode mode = GET_MODE (x);
7224 enum rtx_code subcode;
7226 enum rtx_code code = GET_CODE (x);
7232 /* Memory costs quite a lot for the first word, but subsequent words
7233 load at the equivalent of a single insn each. */
7234 *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
7241 if (TARGET_HARD_FLOAT && mode == SFmode)
7242 *total = COSTS_N_INSNS (2);
7243 else if (TARGET_HARD_FLOAT && mode == DFmode && !TARGET_VFP_SINGLE)
7244 *total = COSTS_N_INSNS (4);
7246 *total = COSTS_N_INSNS (20);
7250 if (REG_P (XEXP (x, 1)))
7251 *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
7252 else if (!CONST_INT_P (XEXP (x, 1)))
7253 *total = rtx_cost (XEXP (x, 1), code, 1, speed);
7259 *total += COSTS_N_INSNS (4);
7264 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
7265 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7268 *total += COSTS_N_INSNS (3);
7272 *total += COSTS_N_INSNS (1);
7273 /* Increase the cost of complex shifts because they aren't any faster,
7274 and reduce dual issue opportunities. */
7275 if (arm_tune_cortex_a9
7276 && outer != SET && !CONST_INT_P (XEXP (x, 1)))
7284 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7285 if (CONST_INT_P (XEXP (x, 0))
7286 && const_ok_for_arm (INTVAL (XEXP (x, 0))))
7288 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7292 if (CONST_INT_P (XEXP (x, 1))
7293 && const_ok_for_arm (INTVAL (XEXP (x, 1))))
7295 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7302 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7304 if (TARGET_HARD_FLOAT
7306 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7308 *total = COSTS_N_INSNS (1);
7309 if (CONST_DOUBLE_P (XEXP (x, 0))
7310 && arm_const_double_rtx (XEXP (x, 0)))
7312 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7316 if (CONST_DOUBLE_P (XEXP (x, 1))
7317 && arm_const_double_rtx (XEXP (x, 1)))
7319 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7325 *total = COSTS_N_INSNS (20);
7329 *total = COSTS_N_INSNS (1);
7330 if (CONST_INT_P (XEXP (x, 0))
7331 && const_ok_for_arm (INTVAL (XEXP (x, 0))))
7333 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7337 subcode = GET_CODE (XEXP (x, 1));
7338 if (subcode == ASHIFT || subcode == ASHIFTRT
7339 || subcode == LSHIFTRT
7340 || subcode == ROTATE || subcode == ROTATERT)
7342 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7343 *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, 0, speed);
7347 /* A shift as a part of RSB costs no more than RSB itself. */
7348 if (GET_CODE (XEXP (x, 0)) == MULT
7349 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7351 *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, 0, speed);
7352 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7357 && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode))
7359 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7360 *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, 0, speed);
7364 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE
7365 || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE)
7367 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
7368 if (REG_P (XEXP (XEXP (x, 1), 0))
7369 && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM)
7370 *total += COSTS_N_INSNS (1);
7378 if (code == PLUS && arm_arch6 && mode == SImode
7379 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
7380 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
7382 *total = COSTS_N_INSNS (1);
7383 *total += rtx_cost (XEXP (XEXP (x, 0), 0), GET_CODE (XEXP (x, 0)),
7385 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7389 /* MLA: All arguments must be registers. We filter out
7390 multiplication by a power of two, so that we fall down into
7392 if (GET_CODE (XEXP (x, 0)) == MULT
7393 && !power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7395 /* The cost comes from the cost of the multiply. */
7399 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7401 if (TARGET_HARD_FLOAT
7403 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7405 *total = COSTS_N_INSNS (1);
7406 if (CONST_DOUBLE_P (XEXP (x, 1))
7407 && arm_const_double_rtx (XEXP (x, 1)))
7409 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7416 *total = COSTS_N_INSNS (20);
7420 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE
7421 || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE)
7423 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, 1, speed);
7424 if (REG_P (XEXP (XEXP (x, 0), 0))
7425 && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM)
7426 *total += COSTS_N_INSNS (1);
7432 case AND: case XOR: case IOR:
7434 /* Normally the frame registers will be spilt into reg+const during
7435 reload, so it is a bad idea to combine them with other instructions,
7436 since then they might not be moved outside of loops. As a compromise
7437 we allow integration with ops that have a constant as their second
7439 if (REG_OR_SUBREG_REG (XEXP (x, 0))
7440 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
7441 && !CONST_INT_P (XEXP (x, 1)))
7442 *total = COSTS_N_INSNS (1);
7446 *total += COSTS_N_INSNS (2);
7447 if (CONST_INT_P (XEXP (x, 1))
7448 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
7450 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7457 *total += COSTS_N_INSNS (1);
7458 if (CONST_INT_P (XEXP (x, 1))
7459 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
7461 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7464 subcode = GET_CODE (XEXP (x, 0));
7465 if (subcode == ASHIFT || subcode == ASHIFTRT
7466 || subcode == LSHIFTRT
7467 || subcode == ROTATE || subcode == ROTATERT)
7469 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7470 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7475 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7477 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7478 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7482 if (subcode == UMIN || subcode == UMAX
7483 || subcode == SMIN || subcode == SMAX)
7485 *total = COSTS_N_INSNS (3);
7492 /* This should have been handled by the CPU specific routines. */
7496 if (arm_arch3m && mode == SImode
7497 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
7498 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
7499 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
7500 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
7501 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
7502 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
7504 *total = rtx_cost (XEXP (XEXP (x, 0), 0), LSHIFTRT, 0, speed);
7507 *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */
7511 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7513 if (TARGET_HARD_FLOAT
7515 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7517 *total = COSTS_N_INSNS (1);
7520 *total = COSTS_N_INSNS (2);
7526 *total = COSTS_N_INSNS (ARM_NUM_REGS(mode));
7527 if (mode == SImode && code == NOT)
7529 subcode = GET_CODE (XEXP (x, 0));
7530 if (subcode == ASHIFT || subcode == ASHIFTRT
7531 || subcode == LSHIFTRT
7532 || subcode == ROTATE || subcode == ROTATERT
7534 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)))
7536 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7537 /* Register shifts cost an extra cycle. */
7538 if (!CONST_INT_P (XEXP (XEXP (x, 0), 1)))
7539 *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1),
7548 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
7550 *total = COSTS_N_INSNS (4);
7554 operand = XEXP (x, 0);
7556 if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE
7557 || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE)
7558 && REG_P (XEXP (operand, 0))
7559 && REGNO (XEXP (operand, 0)) == CC_REGNUM))
7560 *total += COSTS_N_INSNS (1);
7561 *total += (rtx_cost (XEXP (x, 1), code, 1, speed)
7562 + rtx_cost (XEXP (x, 2), code, 2, speed));
7566 if (mode == SImode && XEXP (x, 1) == const0_rtx)
7568 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
7574 if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
7575 && mode == SImode && XEXP (x, 1) == const0_rtx)
7577 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
7583 if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
7584 && mode == SImode && XEXP (x, 1) == const0_rtx)
7586 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
7606 /* SCC insns. In the case where the comparison has already been
7607 performed, then they cost 2 instructions. Otherwise they need
7608 an additional comparison before them. */
7609 *total = COSTS_N_INSNS (2);
7610 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
7617 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
7623 *total += COSTS_N_INSNS (1);
7624 if (CONST_INT_P (XEXP (x, 1))
7625 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
7627 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7631 subcode = GET_CODE (XEXP (x, 0));
7632 if (subcode == ASHIFT || subcode == ASHIFTRT
7633 || subcode == LSHIFTRT
7634 || subcode == ROTATE || subcode == ROTATERT)
7636 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7637 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7642 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
7644 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7645 *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
7655 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
7656 if (!CONST_INT_P (XEXP (x, 1))
7657 || !const_ok_for_arm (INTVAL (XEXP (x, 1))))
7658 *total += rtx_cost (XEXP (x, 1), code, 1, speed);
7662 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7664 if (TARGET_HARD_FLOAT
7666 || (mode == DFmode && !TARGET_VFP_SINGLE)))
7668 *total = COSTS_N_INSNS (1);
7671 *total = COSTS_N_INSNS (20);
7674 *total = COSTS_N_INSNS (1);
7676 *total += COSTS_N_INSNS (3);
7682 if (GET_MODE_CLASS (mode) == MODE_INT)
7684 rtx op = XEXP (x, 0);
7685 enum machine_mode opmode = GET_MODE (op);
7688 *total += COSTS_N_INSNS (1);
7690 if (opmode != SImode)
7694 /* If !arm_arch4, we use one of the extendhisi2_mem
7695 or movhi_bytes patterns for HImode. For a QImode
7696 sign extension, we first zero-extend from memory
7697 and then perform a shift sequence. */
7698 if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND))
7699 *total += COSTS_N_INSNS (2);
7702 *total += COSTS_N_INSNS (1);
7704 /* We don't have the necessary insn, so we need to perform some
7706 else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode)
7707 /* An and with constant 255. */
7708 *total += COSTS_N_INSNS (1);
7710 /* A shift sequence. Increase costs slightly to avoid
7711 combining two shifts into an extend operation. */
7712 *total += COSTS_N_INSNS (2) + 1;
7718 switch (GET_MODE (XEXP (x, 0)))
7725 *total = COSTS_N_INSNS (1);
7735 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
7739 if (const_ok_for_arm (INTVAL (x))
7740 || const_ok_for_arm (~INTVAL (x)))
7741 *total = COSTS_N_INSNS (1);
7743 *total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX,
7744 INTVAL (x), NULL_RTX,
7751 *total = COSTS_N_INSNS (3);
7755 *total = COSTS_N_INSNS (1);
7759 *total = COSTS_N_INSNS (1);
7760 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
7764 if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x)
7765 && (mode == SFmode || !TARGET_VFP_SINGLE))
7766 *total = COSTS_N_INSNS (1);
7768 *total = COSTS_N_INSNS (4);
7772 /* The vec_extract patterns accept memory operands that require an
7773 address reload. Account for the cost of that reload to give the
7774 auto-inc-dec pass an incentive to try to replace them. */
7775 if (TARGET_NEON && MEM_P (SET_DEST (x))
7776 && GET_CODE (SET_SRC (x)) == VEC_SELECT)
7778 *total = rtx_cost (SET_DEST (x), code, 0, speed);
7779 if (!neon_vector_mem_operand (SET_DEST (x), 2))
7780 *total += COSTS_N_INSNS (1);
7783 /* Likewise for the vec_set patterns. */
7784 if (TARGET_NEON && GET_CODE (SET_SRC (x)) == VEC_MERGE
7785 && GET_CODE (XEXP (SET_SRC (x), 0)) == VEC_DUPLICATE
7786 && MEM_P (XEXP (XEXP (SET_SRC (x), 0), 0)))
7788 rtx mem = XEXP (XEXP (SET_SRC (x), 0), 0);
7789 *total = rtx_cost (mem, code, 0, speed);
7790 if (!neon_vector_mem_operand (mem, 2))
7791 *total += COSTS_N_INSNS (1);
7797 /* We cost this as high as our memory costs to allow this to
7798 be hoisted from loops. */
7799 if (XINT (x, 1) == UNSPEC_PIC_UNIFIED)
7801 *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
7807 && TARGET_HARD_FLOAT
7809 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
7810 && neon_immediate_valid_for_move (x, mode, NULL, NULL))
7811 *total = COSTS_N_INSNS (1);
7813 *total = COSTS_N_INSNS (4);
7817 *total = COSTS_N_INSNS (4);
7822 /* Estimates the size cost of thumb1 instructions.
7823 For now most of the code is copied from thumb1_rtx_costs. We need more
7824 fine grain tuning when we have more related test cases. */
7826 thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
7828 enum machine_mode mode = GET_MODE (x);
7841 return COSTS_N_INSNS (1);
7844 if (CONST_INT_P (XEXP (x, 1)))
7846 /* Thumb1 mul instruction can't operate on const. We must Load it
7847 into a register first. */
7848 int const_size = thumb1_size_rtx_costs (XEXP (x, 1), CONST_INT, SET);
7849 return COSTS_N_INSNS (1) + const_size;
7851 return COSTS_N_INSNS (1);
7854 return (COSTS_N_INSNS (1)
7855 + 4 * ((MEM_P (SET_SRC (x)))
7856 + MEM_P (SET_DEST (x))));
7861 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
7862 return COSTS_N_INSNS (1);
7863 /* See split "TARGET_THUMB1 && satisfies_constraint_J". */
7864 if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
7865 return COSTS_N_INSNS (2);
7866 /* See split "TARGET_THUMB1 && satisfies_constraint_K". */
7867 if (thumb_shiftable_const (INTVAL (x)))
7868 return COSTS_N_INSNS (2);
7869 return COSTS_N_INSNS (3);
7871 else if ((outer == PLUS || outer == COMPARE)
7872 && INTVAL (x) < 256 && INTVAL (x) > -256)
7874 else if ((outer == IOR || outer == XOR || outer == AND)
7875 && INTVAL (x) < 256 && INTVAL (x) >= -256)
7876 return COSTS_N_INSNS (1);
7877 else if (outer == AND)
7880 /* This duplicates the tests in the andsi3 expander. */
7881 for (i = 9; i <= 31; i++)
7882 if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
7883 || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
7884 return COSTS_N_INSNS (2);
7886 else if (outer == ASHIFT || outer == ASHIFTRT
7887 || outer == LSHIFTRT)
7889 return COSTS_N_INSNS (2);
7895 return COSTS_N_INSNS (3);
7913 /* XXX another guess. */
7914 /* Memory costs quite a lot for the first word, but subsequent words
7915 load at the equivalent of a single insn each. */
7916 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
7917 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
7922 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
7927 /* XXX still guessing. */
7928 switch (GET_MODE (XEXP (x, 0)))
7931 return (1 + (mode == DImode ? 4 : 0)
7932 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
7935 return (4 + (mode == DImode ? 4 : 0)
7936 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
7939 return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
7950 /* RTX costs when optimizing for size. */
7952 arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
7955 enum machine_mode mode = GET_MODE (x);
7958 *total = thumb1_size_rtx_costs (x, code, outer_code);
7962 /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */
7966 /* A memory access costs 1 insn if the mode is small, or the address is
7967 a single register, otherwise it costs one insn per word. */
7968 if (REG_P (XEXP (x, 0)))
7969 *total = COSTS_N_INSNS (1);
7971 && GET_CODE (XEXP (x, 0)) == PLUS
7972 && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))
7973 /* This will be split into two instructions.
7974 See arm.md:calculate_pic_address. */
7975 *total = COSTS_N_INSNS (2);
7977 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
7984 /* Needs a libcall, so it costs about this. */
7985 *total = COSTS_N_INSNS (2);
7989 if (mode == SImode && REG_P (XEXP (x, 1)))
7991 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, false);
7999 if (mode == DImode && CONST_INT_P (XEXP (x, 1)))
8001 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, 0, false);
8004 else if (mode == SImode)
8006 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, false);
8007 /* Slightly disparage register shifts, but not by much. */
8008 if (!CONST_INT_P (XEXP (x, 1)))
8009 *total += 1 + rtx_cost (XEXP (x, 1), code, 1, false);
8013 /* Needs a libcall. */
8014 *total = COSTS_N_INSNS (2);
8018 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
8019 && (mode == SFmode || !TARGET_VFP_SINGLE))
8021 *total = COSTS_N_INSNS (1);
8027 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
8028 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
8030 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
8031 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
8032 || subcode1 == ROTATE || subcode1 == ROTATERT
8033 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
8034 || subcode1 == ASHIFTRT)
8036 /* It's just the cost of the two operands. */
8041 *total = COSTS_N_INSNS (1);
8045 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
8049 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
8050 && (mode == SFmode || !TARGET_VFP_SINGLE))
8052 *total = COSTS_N_INSNS (1);
8056 /* A shift as a part of ADD costs nothing. */
8057 if (GET_CODE (XEXP (x, 0)) == MULT
8058 && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
8060 *total = COSTS_N_INSNS (TARGET_THUMB2 ? 2 : 1);
8061 *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, 0, false);
8062 *total += rtx_cost (XEXP (x, 1), code, 1, false);
8067 case AND: case XOR: case IOR:
8070 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
8072 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
8073 || subcode == LSHIFTRT || subcode == ASHIFTRT
8074 || (code == AND && subcode == NOT))
8076 /* It's just the cost of the two operands. */
8082 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
8086 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
8090 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
8091 && (mode == SFmode || !TARGET_VFP_SINGLE))
8093 *total = COSTS_N_INSNS (1);
8099 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
8108 if (cc_register (XEXP (x, 0), VOIDmode))
8111 *total = COSTS_N_INSNS (1);
8115 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
8116 && (mode == SFmode || !TARGET_VFP_SINGLE))
8117 *total = COSTS_N_INSNS (1);
8119 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
8124 return arm_rtx_costs_1 (x, outer_code, total, 0);
8127 if (const_ok_for_arm (INTVAL (x)))
8128 /* A multiplication by a constant requires another instruction
8129 to load the constant to a register. */
8130 *total = COSTS_N_INSNS ((outer_code == SET || outer_code == MULT)
8132 else if (const_ok_for_arm (~INTVAL (x)))
8133 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
8134 else if (const_ok_for_arm (-INTVAL (x)))
8136 if (outer_code == COMPARE || outer_code == PLUS
8137 || outer_code == MINUS)
8140 *total = COSTS_N_INSNS (1);
8143 *total = COSTS_N_INSNS (2);
8149 *total = COSTS_N_INSNS (2);
8153 *total = COSTS_N_INSNS (4);
8158 && TARGET_HARD_FLOAT
8159 && outer_code == SET
8160 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
8161 && neon_immediate_valid_for_move (x, mode, NULL, NULL))
8162 *total = COSTS_N_INSNS (1);
8164 *total = COSTS_N_INSNS (4);
8169 /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
8170 cost of these slightly. */
8171 *total = COSTS_N_INSNS (1) + 1;
8178 if (mode != VOIDmode)
8179 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
8181 *total = COSTS_N_INSNS (4); /* How knows? */
8186 /* RTX costs when optimizing for size. */
8188 arm_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
8189 int *total, bool speed)
8192 return arm_size_rtx_costs (x, (enum rtx_code) code,
8193 (enum rtx_code) outer_code, total);
8195 return current_tune->rtx_costs (x, (enum rtx_code) code,
8196 (enum rtx_code) outer_code,
8200 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
8201 supported on any "slowmul" cores, so it can be ignored. */
8204 arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8205 int *total, bool speed)
8207 enum machine_mode mode = GET_MODE (x);
8211 *total = thumb1_rtx_costs (x, code, outer_code);
8218 if (GET_MODE_CLASS (mode) == MODE_FLOAT
8221 *total = COSTS_N_INSNS (20);
8225 if (CONST_INT_P (XEXP (x, 1)))
8227 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
8228 & (unsigned HOST_WIDE_INT) 0xffffffff);
8229 int cost, const_ok = const_ok_for_arm (i);
8230 int j, booth_unit_size;
8232 /* Tune as appropriate. */
8233 cost = const_ok ? 4 : 8;
8234 booth_unit_size = 2;
8235 for (j = 0; i && j < 32; j += booth_unit_size)
8237 i >>= booth_unit_size;
8241 *total = COSTS_N_INSNS (cost);
8242 *total += rtx_cost (XEXP (x, 0), code, 0, speed);
8246 *total = COSTS_N_INSNS (20);
8250 return arm_rtx_costs_1 (x, outer_code, total, speed);;
8255 /* RTX cost for cores with a fast multiply unit (M variants). */
8258 arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8259 int *total, bool speed)
8261 enum machine_mode mode = GET_MODE (x);
8265 *total = thumb1_rtx_costs (x, code, outer_code);
8269 /* ??? should thumb2 use different costs? */
8273 /* There is no point basing this on the tuning, since it is always the
8274 fast variant if it exists at all. */
8276 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
8277 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8278 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
8280 *total = COSTS_N_INSNS(2);
8287 *total = COSTS_N_INSNS (5);
8291 if (CONST_INT_P (XEXP (x, 1)))
8293 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
8294 & (unsigned HOST_WIDE_INT) 0xffffffff);
8295 int cost, const_ok = const_ok_for_arm (i);
8296 int j, booth_unit_size;
8298 /* Tune as appropriate. */
8299 cost = const_ok ? 4 : 8;
8300 booth_unit_size = 8;
8301 for (j = 0; i && j < 32; j += booth_unit_size)
8303 i >>= booth_unit_size;
8307 *total = COSTS_N_INSNS(cost);
8313 *total = COSTS_N_INSNS (4);
8317 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
8319 if (TARGET_HARD_FLOAT
8321 || (mode == DFmode && !TARGET_VFP_SINGLE)))
8323 *total = COSTS_N_INSNS (1);
8328 /* Requires a lib call */
8329 *total = COSTS_N_INSNS (20);
8333 return arm_rtx_costs_1 (x, outer_code, total, speed);
8338 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
8339 so it can be ignored. */
8342 arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8343 int *total, bool speed)
8345 enum machine_mode mode = GET_MODE (x);
8349 *total = thumb1_rtx_costs (x, code, outer_code);
8356 if (GET_CODE (XEXP (x, 0)) != MULT)
8357 return arm_rtx_costs_1 (x, outer_code, total, speed);
8359 /* A COMPARE of a MULT is slow on XScale; the muls instruction
8360 will stall until the multiplication is complete. */
8361 *total = COSTS_N_INSNS (3);
8365 /* There is no point basing this on the tuning, since it is always the
8366 fast variant if it exists at all. */
8368 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
8369 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8370 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
8372 *total = COSTS_N_INSNS (2);
8379 *total = COSTS_N_INSNS (5);
8383 if (CONST_INT_P (XEXP (x, 1)))
8385 /* If operand 1 is a constant we can more accurately
8386 calculate the cost of the multiply. The multiplier can
8387 retire 15 bits on the first cycle and a further 12 on the
8388 second. We do, of course, have to load the constant into
8389 a register first. */
8390 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
8391 /* There's a general overhead of one cycle. */
8393 unsigned HOST_WIDE_INT masked_const;
8398 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
8400 masked_const = i & 0xffff8000;
8401 if (masked_const != 0)
8404 masked_const = i & 0xf8000000;
8405 if (masked_const != 0)
8408 *total = COSTS_N_INSNS (cost);
8414 *total = COSTS_N_INSNS (3);
8418 /* Requires a lib call */
8419 *total = COSTS_N_INSNS (20);
8423 return arm_rtx_costs_1 (x, outer_code, total, speed);
8428 /* RTX costs for 9e (and later) cores. */
8431 arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
8432 int *total, bool speed)
8434 enum machine_mode mode = GET_MODE (x);
8441 *total = COSTS_N_INSNS (3);
8445 *total = thumb1_rtx_costs (x, code, outer_code);
8453 /* There is no point basing this on the tuning, since it is always the
8454 fast variant if it exists at all. */
8456 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
8457 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8458 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
8460 *total = COSTS_N_INSNS (2);
8467 *total = COSTS_N_INSNS (5);
8473 *total = COSTS_N_INSNS (2);
8477 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
8479 if (TARGET_HARD_FLOAT
8481 || (mode == DFmode && !TARGET_VFP_SINGLE)))
8483 *total = COSTS_N_INSNS (1);
8488 *total = COSTS_N_INSNS (20);
8492 return arm_rtx_costs_1 (x, outer_code, total, speed);
8495 /* All address computations that can be done are free, but rtx cost returns
8496 the same for practically all of them. So we weight the different types
8497 of address here in the order (most pref first):
8498 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
8500 arm_arm_address_cost (rtx x)
8502 enum rtx_code c = GET_CODE (x);
8504 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
8506 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
8511 if (CONST_INT_P (XEXP (x, 1)))
8514 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
8524 arm_thumb_address_cost (rtx x)
8526 enum rtx_code c = GET_CODE (x);
8531 && REG_P (XEXP (x, 0))
8532 && CONST_INT_P (XEXP (x, 1)))
8539 arm_address_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED,
8540 addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED)
8542 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
8545 /* Adjust cost hook for XScale. */
8547 xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
8549 /* Some true dependencies can have a higher cost depending
8550 on precisely how certain input operands are used. */
8551 if (REG_NOTE_KIND(link) == 0
8552 && recog_memoized (insn) >= 0
8553 && recog_memoized (dep) >= 0)
8555 int shift_opnum = get_attr_shift (insn);
8556 enum attr_type attr_type = get_attr_type (dep);
8558 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
8559 operand for INSN. If we have a shifted input operand and the
8560 instruction we depend on is another ALU instruction, then we may
8561 have to account for an additional stall. */
8562 if (shift_opnum != 0
8563 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
8565 rtx shifted_operand;
8568 /* Get the shifted operand. */
8569 extract_insn (insn);
8570 shifted_operand = recog_data.operand[shift_opnum];
8572 /* Iterate over all the operands in DEP. If we write an operand
8573 that overlaps with SHIFTED_OPERAND, then we have increase the
8574 cost of this dependency. */
8576 preprocess_constraints ();
8577 for (opno = 0; opno < recog_data.n_operands; opno++)
8579 /* We can ignore strict inputs. */
8580 if (recog_data.operand_type[opno] == OP_IN)
8583 if (reg_overlap_mentioned_p (recog_data.operand[opno],
8595 /* Adjust cost hook for Cortex A9. */
8597 cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
8599 switch (REG_NOTE_KIND (link))
8606 case REG_DEP_OUTPUT:
8607 if (recog_memoized (insn) >= 0
8608 && recog_memoized (dep) >= 0)
8610 if (GET_CODE (PATTERN (insn)) == SET)
8613 (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT
8615 (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
8617 enum attr_type attr_type_insn = get_attr_type (insn);
8618 enum attr_type attr_type_dep = get_attr_type (dep);
8620 /* By default all dependencies of the form
8623 have an extra latency of 1 cycle because
8624 of the input and output dependency in this
8625 case. However this gets modeled as an true
8626 dependency and hence all these checks. */
8627 if (REG_P (SET_DEST (PATTERN (insn)))
8628 && REG_P (SET_DEST (PATTERN (dep)))
8629 && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)),
8630 SET_DEST (PATTERN (dep))))
8632 /* FMACS is a special case where the dependent
8633 instruction can be issued 3 cycles before
8634 the normal latency in case of an output
8636 if ((attr_type_insn == TYPE_FMACS
8637 || attr_type_insn == TYPE_FMACD)
8638 && (attr_type_dep == TYPE_FMACS
8639 || attr_type_dep == TYPE_FMACD))
8641 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
8642 *cost = insn_default_latency (dep) - 3;
8644 *cost = insn_default_latency (dep);
8649 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
8650 *cost = insn_default_latency (dep) + 1;
8652 *cost = insn_default_latency (dep);
8668 /* Adjust cost hook for FA726TE. */
8670 fa726te_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
8672 /* For FA726TE, true dependency on CPSR (i.e. set cond followed by predicated)
8673 have penalty of 3. */
8674 if (REG_NOTE_KIND (link) == REG_DEP_TRUE
8675 && recog_memoized (insn) >= 0
8676 && recog_memoized (dep) >= 0
8677 && get_attr_conds (dep) == CONDS_SET)
8679 /* Use of carry (e.g. 64-bit arithmetic) in ALU: 3-cycle latency. */
8680 if (get_attr_conds (insn) == CONDS_USE
8681 && get_attr_type (insn) != TYPE_BRANCH)
8687 if (GET_CODE (PATTERN (insn)) == COND_EXEC
8688 || get_attr_conds (insn) == CONDS_USE)
8698 /* Implement TARGET_REGISTER_MOVE_COST.
8700 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
8701 it is typically more expensive than a single memory access. We set
8702 the cost to less than two memory accesses so that floating
8703 point to integer conversion does not go through memory. */
8706 arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8707 reg_class_t from, reg_class_t to)
8711 if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to))
8712 || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to)))
8714 else if ((from == IWMMXT_REGS && to != IWMMXT_REGS)
8715 || (from != IWMMXT_REGS && to == IWMMXT_REGS))
8717 else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS)
8724 if (from == HI_REGS || to == HI_REGS)
8731 /* Implement TARGET_MEMORY_MOVE_COST. */
8734 arm_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
8735 bool in ATTRIBUTE_UNUSED)
8741 if (GET_MODE_SIZE (mode) < 4)
8744 return ((2 * GET_MODE_SIZE (mode)) * (rclass == LO_REGS ? 1 : 2));
8748 /* Vectorizer cost model implementation. */
8750 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8752 arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
8754 int misalign ATTRIBUTE_UNUSED)
8758 switch (type_of_cost)
8761 return current_tune->vec_costs->scalar_stmt_cost;
8764 return current_tune->vec_costs->scalar_load_cost;
8767 return current_tune->vec_costs->scalar_store_cost;
8770 return current_tune->vec_costs->vec_stmt_cost;
8773 return current_tune->vec_costs->vec_align_load_cost;
8776 return current_tune->vec_costs->vec_store_cost;
8779 return current_tune->vec_costs->vec_to_scalar_cost;
8782 return current_tune->vec_costs->scalar_to_vec_cost;
8784 case unaligned_load:
8785 return current_tune->vec_costs->vec_unalign_load_cost;
8787 case unaligned_store:
8788 return current_tune->vec_costs->vec_unalign_store_cost;
8790 case cond_branch_taken:
8791 return current_tune->vec_costs->cond_taken_branch_cost;
8793 case cond_branch_not_taken:
8794 return current_tune->vec_costs->cond_not_taken_branch_cost;
8797 case vec_promote_demote:
8798 return current_tune->vec_costs->vec_stmt_cost;
8801 elements = TYPE_VECTOR_SUBPARTS (vectype);
8802 return elements / 2 + 1;
8809 /* Implement targetm.vectorize.add_stmt_cost. */
8812 arm_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
8813 struct _stmt_vec_info *stmt_info, int misalign,
8814 enum vect_cost_model_location where)
8816 unsigned *cost = (unsigned *) data;
8817 unsigned retval = 0;
8819 if (flag_vect_cost_model)
8821 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
8822 int stmt_cost = arm_builtin_vectorization_cost (kind, vectype, misalign);
8824 /* Statements in an inner loop relative to the loop being
8825 vectorized are weighted more heavily. The value here is
8826 arbitrary and could potentially be improved with analysis. */
8827 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
8828 count *= 50; /* FIXME. */
8830 retval = (unsigned) (count * stmt_cost);
8831 cost[where] += retval;
8837 /* Return true if and only if this insn can dual-issue only as older. */
8839 cortexa7_older_only (rtx insn)
8841 if (recog_memoized (insn) < 0)
8844 if (get_attr_insn (insn) == INSN_MOV)
8847 switch (get_attr_type (insn))
8850 case TYPE_LOAD_BYTE:
8879 /* Return true if and only if this insn can dual-issue as younger. */
8881 cortexa7_younger (FILE *file, int verbose, rtx insn)
8883 if (recog_memoized (insn) < 0)
8886 fprintf (file, ";; not cortexa7_younger %d\n", INSN_UID (insn));
8890 if (get_attr_insn (insn) == INSN_MOV)
8893 switch (get_attr_type (insn))
8895 case TYPE_SIMPLE_ALU_IMM:
8896 case TYPE_SIMPLE_ALU_SHIFT:
8906 /* Look for an instruction that can dual issue only as an older
8907 instruction, and move it in front of any instructions that can
8908 dual-issue as younger, while preserving the relative order of all
8909 other instructions in the ready list. This is a hueuristic to help
8910 dual-issue in later cycles, by postponing issue of more flexible
8911 instructions. This heuristic may affect dual issue opportunities
8912 in the current cycle. */
8914 cortexa7_sched_reorder (FILE *file, int verbose, rtx *ready, int *n_readyp,
8918 int first_older_only = -1, first_younger = -1;
8922 ";; sched_reorder for cycle %d with %d insns in ready list\n",
8926 /* Traverse the ready list from the head (the instruction to issue
8927 first), and looking for the first instruction that can issue as
8928 younger and the first instruction that can dual-issue only as
8930 for (i = *n_readyp - 1; i >= 0; i--)
8932 rtx insn = ready[i];
8933 if (cortexa7_older_only (insn))
8935 first_older_only = i;
8937 fprintf (file, ";; reorder older found %d\n", INSN_UID (insn));
8940 else if (cortexa7_younger (file, verbose, insn) && first_younger == -1)
8944 /* Nothing to reorder because either no younger insn found or insn
8945 that can dual-issue only as older appears before any insn that
8946 can dual-issue as younger. */
8947 if (first_younger == -1)
8950 fprintf (file, ";; sched_reorder nothing to reorder as no younger\n");
8954 /* Nothing to reorder because no older-only insn in the ready list. */
8955 if (first_older_only == -1)
8958 fprintf (file, ";; sched_reorder nothing to reorder as no older_only\n");
8962 /* Move first_older_only insn before first_younger. */
8964 fprintf (file, ";; cortexa7_sched_reorder insn %d before %d\n",
8965 INSN_UID(ready [first_older_only]),
8966 INSN_UID(ready [first_younger]));
8967 rtx first_older_only_insn = ready [first_older_only];
8968 for (i = first_older_only; i < first_younger; i++)
8970 ready[i] = ready[i+1];
8973 ready[i] = first_older_only_insn;
8977 /* Implement TARGET_SCHED_REORDER. */
8979 arm_sched_reorder (FILE *file, int verbose, rtx *ready, int *n_readyp,
8985 cortexa7_sched_reorder (file, verbose, ready, n_readyp, clock);
8988 /* Do nothing for other cores. */
8992 return arm_issue_rate ();
8995 /* This function implements the target macro TARGET_SCHED_ADJUST_COST.
8996 It corrects the value of COST based on the relationship between
8997 INSN and DEP through the dependence LINK. It returns the new
8998 value. There is a per-core adjust_cost hook to adjust scheduler costs
8999 and the per-core hook can choose to completely override the generic
9000 adjust_cost function. Only put bits of code into arm_adjust_cost that
9001 are common across all cores. */
9003 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
9007 /* When generating Thumb-1 code, we want to place flag-setting operations
9008 close to a conditional branch which depends on them, so that we can
9009 omit the comparison. */
9011 && REG_NOTE_KIND (link) == 0
9012 && recog_memoized (insn) == CODE_FOR_cbranchsi4_insn
9013 && recog_memoized (dep) >= 0
9014 && get_attr_conds (dep) == CONDS_SET)
9017 if (current_tune->sched_adjust_cost != NULL)
9019 if (!current_tune->sched_adjust_cost (insn, link, dep, &cost))
9023 /* XXX Is this strictly true? */
9024 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9025 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
9028 /* Call insns don't incur a stall, even if they follow a load. */
9029 if (REG_NOTE_KIND (link) == 0
9033 if ((i_pat = single_set (insn)) != NULL
9034 && MEM_P (SET_SRC (i_pat))
9035 && (d_pat = single_set (dep)) != NULL
9036 && MEM_P (SET_DEST (d_pat)))
9038 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
9039 /* This is a load after a store, there is no conflict if the load reads
9040 from a cached area. Assume that loads from the stack, and from the
9041 constant pool are cached, and that others will miss. This is a
9044 if ((GET_CODE (src_mem) == SYMBOL_REF
9045 && CONSTANT_POOL_ADDRESS_P (src_mem))
9046 || reg_mentioned_p (stack_pointer_rtx, src_mem)
9047 || reg_mentioned_p (frame_pointer_rtx, src_mem)
9048 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
9056 arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED)
9059 return (TARGET_THUMB2 && !speed_p) ? 1 : 4;
9061 return (optimize > 0) ? 2 : 0;
9065 arm_cortex_a5_branch_cost (bool speed_p, bool predictable_p)
9067 return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
9070 static bool fp_consts_inited = false;
9072 static REAL_VALUE_TYPE value_fp0;
9075 init_fp_table (void)
9079 r = REAL_VALUE_ATOF ("0", DFmode);
9081 fp_consts_inited = true;
9084 /* Return TRUE if rtx X is a valid immediate FP constant. */
9086 arm_const_double_rtx (rtx x)
9090 if (!fp_consts_inited)
9093 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9094 if (REAL_VALUE_MINUS_ZERO (r))
9097 if (REAL_VALUES_EQUAL (r, value_fp0))
9103 /* VFPv3 has a fairly wide range of representable immediates, formed from
9104 "quarter-precision" floating-point values. These can be evaluated using this
9105 formula (with ^ for exponentiation):
9109 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
9110 16 <= n <= 31 and 0 <= r <= 7.
9112 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
9114 - A (most-significant) is the sign bit.
9115 - BCD are the exponent (encoded as r XOR 3).
9116 - EFGH are the mantissa (encoded as n - 16).
9119 /* Return an integer index for a VFPv3 immediate operand X suitable for the
9120 fconst[sd] instruction, or -1 if X isn't suitable. */
9122 vfp3_const_double_index (rtx x)
9124 REAL_VALUE_TYPE r, m;
9126 unsigned HOST_WIDE_INT mantissa, mant_hi;
9127 unsigned HOST_WIDE_INT mask;
9128 HOST_WIDE_INT m1, m2;
9129 int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
9131 if (!TARGET_VFP3 || !CONST_DOUBLE_P (x))
9134 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9136 /* We can't represent these things, so detect them first. */
9137 if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r))
9140 /* Extract sign, exponent and mantissa. */
9141 sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0;
9142 r = real_value_abs (&r);
9143 exponent = REAL_EXP (&r);
9144 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
9145 highest (sign) bit, with a fixed binary point at bit point_pos.
9146 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
9147 bits for the mantissa, this may fail (low bits would be lost). */
9148 real_ldexp (&m, &r, point_pos - exponent);
9149 REAL_VALUE_TO_INT (&m1, &m2, m);
9153 /* If there are bits set in the low part of the mantissa, we can't
9154 represent this value. */
9158 /* Now make it so that mantissa contains the most-significant bits, and move
9159 the point_pos to indicate that the least-significant bits have been
9161 point_pos -= HOST_BITS_PER_WIDE_INT;
9164 /* We can permit four significant bits of mantissa only, plus a high bit
9165 which is always 1. */
9166 mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
9167 if ((mantissa & mask) != 0)
9170 /* Now we know the mantissa is in range, chop off the unneeded bits. */
9171 mantissa >>= point_pos - 5;
9173 /* The mantissa may be zero. Disallow that case. (It's possible to load the
9174 floating-point immediate zero with Neon using an integer-zero load, but
9175 that case is handled elsewhere.) */
9179 gcc_assert (mantissa >= 16 && mantissa <= 31);
9181 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
9182 normalized significands are in the range [1, 2). (Our mantissa is shifted
9183 left 4 places at this point relative to normalized IEEE754 values). GCC
9184 internally uses [0.5, 1) (see real.c), so the exponent returned from
9185 REAL_EXP must be altered. */
9186 exponent = 5 - exponent;
9188 if (exponent < 0 || exponent > 7)
9191 /* Sign, mantissa and exponent are now in the correct form to plug into the
9192 formula described in the comment above. */
9193 return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16);
9196 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
9198 vfp3_const_double_rtx (rtx x)
9203 return vfp3_const_double_index (x) != -1;
9206 /* Recognize immediates which can be used in various Neon instructions. Legal
9207 immediates are described by the following table (for VMVN variants, the
9208 bitwise inverse of the constant shown is recognized. In either case, VMOV
9209 is output and the correct instruction to use for a given constant is chosen
9210 by the assembler). The constant shown is replicated across all elements of
9211 the destination vector.
9213 insn elems variant constant (binary)
9214 ---- ----- ------- -----------------
9215 vmov i32 0 00000000 00000000 00000000 abcdefgh
9216 vmov i32 1 00000000 00000000 abcdefgh 00000000
9217 vmov i32 2 00000000 abcdefgh 00000000 00000000
9218 vmov i32 3 abcdefgh 00000000 00000000 00000000
9219 vmov i16 4 00000000 abcdefgh
9220 vmov i16 5 abcdefgh 00000000
9221 vmvn i32 6 00000000 00000000 00000000 abcdefgh
9222 vmvn i32 7 00000000 00000000 abcdefgh 00000000
9223 vmvn i32 8 00000000 abcdefgh 00000000 00000000
9224 vmvn i32 9 abcdefgh 00000000 00000000 00000000
9225 vmvn i16 10 00000000 abcdefgh
9226 vmvn i16 11 abcdefgh 00000000
9227 vmov i32 12 00000000 00000000 abcdefgh 11111111
9228 vmvn i32 13 00000000 00000000 abcdefgh 11111111
9229 vmov i32 14 00000000 abcdefgh 11111111 11111111
9230 vmvn i32 15 00000000 abcdefgh 11111111 11111111
9232 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
9233 eeeeeeee ffffffff gggggggg hhhhhhhh
9234 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
9235 vmov f32 19 00000000 00000000 00000000 00000000
9237 For case 18, B = !b. Representable values are exactly those accepted by
9238 vfp3_const_double_index, but are output as floating-point numbers rather
9241 For case 19, we will change it to vmov.i32 when assembling.
9243 Variants 0-5 (inclusive) may also be used as immediates for the second
9244 operand of VORR/VBIC instructions.
9246 The INVERSE argument causes the bitwise inverse of the given operand to be
9247 recognized instead (used for recognizing legal immediates for the VAND/VORN
9248 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
9249 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
9250 output, rather than the real insns vbic/vorr).
9252 INVERSE makes no difference to the recognition of float vectors.
9254 The return value is the variant of immediate as shown in the above table, or
9255 -1 if the given value doesn't match any of the listed patterns.
9258 neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
9259 rtx *modconst, int *elementwidth)
9261 #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
9263 for (i = 0; i < idx; i += (STRIDE)) \
9268 immtype = (CLASS); \
9269 elsize = (ELSIZE); \
9273 unsigned int i, elsize = 0, idx = 0, n_elts;
9274 unsigned int innersize;
9275 unsigned char bytes[16];
9276 int immtype = -1, matches;
9277 unsigned int invmask = inverse ? 0xff : 0;
9278 bool vector = GET_CODE (op) == CONST_VECTOR;
9282 n_elts = CONST_VECTOR_NUNITS (op);
9283 innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
9288 if (mode == VOIDmode)
9290 innersize = GET_MODE_SIZE (mode);
9293 /* Vectors of float constants. */
9294 if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
9296 rtx el0 = CONST_VECTOR_ELT (op, 0);
9299 if (!vfp3_const_double_rtx (el0) && el0 != CONST0_RTX (GET_MODE (el0)))
9302 REAL_VALUE_FROM_CONST_DOUBLE (r0, el0);
9304 for (i = 1; i < n_elts; i++)
9306 rtx elt = CONST_VECTOR_ELT (op, i);
9309 REAL_VALUE_FROM_CONST_DOUBLE (re, elt);
9311 if (!REAL_VALUES_EQUAL (r0, re))
9316 *modconst = CONST_VECTOR_ELT (op, 0);
9321 if (el0 == CONST0_RTX (GET_MODE (el0)))
9327 /* Splat vector constant out into a byte vector. */
9328 for (i = 0; i < n_elts; i++)
9330 rtx el = vector ? CONST_VECTOR_ELT (op, i) : op;
9331 unsigned HOST_WIDE_INT elpart;
9332 unsigned int part, parts;
9334 if (CONST_INT_P (el))
9336 elpart = INTVAL (el);
9339 else if (CONST_DOUBLE_P (el))
9341 elpart = CONST_DOUBLE_LOW (el);
9347 for (part = 0; part < parts; part++)
9350 for (byte = 0; byte < innersize; byte++)
9352 bytes[idx++] = (elpart & 0xff) ^ invmask;
9353 elpart >>= BITS_PER_UNIT;
9355 if (CONST_DOUBLE_P (el))
9356 elpart = CONST_DOUBLE_HIGH (el);
9361 gcc_assert (idx == GET_MODE_SIZE (mode));
9365 CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0
9366 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
9368 CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1]
9369 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
9371 CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0
9372 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
9374 CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0
9375 && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]);
9377 CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0);
9379 CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]);
9381 CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff
9382 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
9384 CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
9385 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
9387 CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff
9388 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
9390 CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff
9391 && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]);
9393 CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff);
9395 CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]);
9397 CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
9398 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
9400 CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1]
9401 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
9403 CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff
9404 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
9406 CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0
9407 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
9409 CHECK (1, 8, 16, bytes[i] == bytes[0]);
9411 CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff)
9412 && bytes[i] == bytes[(i + 8) % idx]);
9420 *elementwidth = elsize;
9424 unsigned HOST_WIDE_INT imm = 0;
9426 /* Un-invert bytes of recognized vector, if necessary. */
9428 for (i = 0; i < idx; i++)
9429 bytes[i] ^= invmask;
9433 /* FIXME: Broken on 32-bit H_W_I hosts. */
9434 gcc_assert (sizeof (HOST_WIDE_INT) == 8);
9436 for (i = 0; i < 8; i++)
9437 imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0)
9438 << (i * BITS_PER_UNIT);
9440 *modconst = GEN_INT (imm);
9444 unsigned HOST_WIDE_INT imm = 0;
9446 for (i = 0; i < elsize / BITS_PER_UNIT; i++)
9447 imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT);
9449 *modconst = GEN_INT (imm);
9457 /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly,
9458 VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for
9459 float elements), and a modified constant (whatever should be output for a
9460 VMOV) in *MODCONST. */
9463 neon_immediate_valid_for_move (rtx op, enum machine_mode mode,
9464 rtx *modconst, int *elementwidth)
9468 int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth);
9474 *modconst = tmpconst;
9477 *elementwidth = tmpwidth;
9482 /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
9483 the immediate is valid, write a constant suitable for using as an operand
9484 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
9485 *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */
9488 neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse,
9489 rtx *modconst, int *elementwidth)
9493 int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth);
9495 if (retval < 0 || retval > 5)
9499 *modconst = tmpconst;
9502 *elementwidth = tmpwidth;
9507 /* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction. If
9508 the immediate is valid, write a constant suitable for using as an operand
9509 to VSHR/VSHL to *MODCONST and the corresponding element width to
9510 *ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
9511 because they have different limitations. */
9514 neon_immediate_valid_for_shift (rtx op, enum machine_mode mode,
9515 rtx *modconst, int *elementwidth,
9518 unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
9519 unsigned int n_elts = CONST_VECTOR_NUNITS (op), i;
9520 unsigned HOST_WIDE_INT last_elt = 0;
9521 unsigned HOST_WIDE_INT maxshift;
9523 /* Split vector constant out into a byte vector. */
9524 for (i = 0; i < n_elts; i++)
9526 rtx el = CONST_VECTOR_ELT (op, i);
9527 unsigned HOST_WIDE_INT elpart;
9529 if (CONST_INT_P (el))
9530 elpart = INTVAL (el);
9531 else if (CONST_DOUBLE_P (el))
9536 if (i != 0 && elpart != last_elt)
9542 /* Shift less than element size. */
9543 maxshift = innersize * 8;
9547 /* Left shift immediate value can be from 0 to <size>-1. */
9548 if (last_elt >= maxshift)
9553 /* Right shift immediate value can be from 1 to <size>. */
9554 if (last_elt == 0 || last_elt > maxshift)
9559 *elementwidth = innersize * 8;
9562 *modconst = CONST_VECTOR_ELT (op, 0);
9567 /* Return a string suitable for output of Neon immediate logic operation
9571 neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode,
9572 int inverse, int quad)
9574 int width, is_valid;
9575 static char templ[40];
9577 is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width);
9579 gcc_assert (is_valid != 0);
9582 sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width);
9584 sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width);
9589 /* Return a string suitable for output of Neon immediate shift operation
9590 (VSHR or VSHL) MNEM. */
9593 neon_output_shift_immediate (const char *mnem, char sign, rtx *op2,
9594 enum machine_mode mode, int quad,
9597 int width, is_valid;
9598 static char templ[40];
9600 is_valid = neon_immediate_valid_for_shift (*op2, mode, op2, &width, isleftshift);
9601 gcc_assert (is_valid != 0);
9604 sprintf (templ, "%s.%c%d\t%%q0, %%q1, %%2", mnem, sign, width);
9606 sprintf (templ, "%s.%c%d\t%%P0, %%P1, %%2", mnem, sign, width);
9611 /* Output a sequence of pairwise operations to implement a reduction.
9612 NOTE: We do "too much work" here, because pairwise operations work on two
9613 registers-worth of operands in one go. Unfortunately we can't exploit those
9614 extra calculations to do the full operation in fewer steps, I don't think.
9615 Although all vector elements of the result but the first are ignored, we
9616 actually calculate the same result in each of the elements. An alternative
9617 such as initially loading a vector with zero to use as each of the second
9618 operands would use up an additional register and take an extra instruction,
9619 for no particular gain. */
9622 neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
9623 rtx (*reduc) (rtx, rtx, rtx))
9625 enum machine_mode inner = GET_MODE_INNER (mode);
9626 unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner);
9629 for (i = parts / 2; i >= 1; i /= 2)
9631 rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode);
9632 emit_insn (reduc (dest, tmpsum, tmpsum));
9637 /* If VALS is a vector constant that can be loaded into a register
9638 using VDUP, generate instructions to do so and return an RTX to
9639 assign to the register. Otherwise return NULL_RTX. */
9642 neon_vdup_constant (rtx vals)
9644 enum machine_mode mode = GET_MODE (vals);
9645 enum machine_mode inner_mode = GET_MODE_INNER (mode);
9646 int n_elts = GET_MODE_NUNITS (mode);
9647 bool all_same = true;
9651 if (GET_CODE (vals) != CONST_VECTOR || GET_MODE_SIZE (inner_mode) > 4)
9654 for (i = 0; i < n_elts; ++i)
9656 x = XVECEXP (vals, 0, i);
9657 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
9662 /* The elements are not all the same. We could handle repeating
9663 patterns of a mode larger than INNER_MODE here (e.g. int8x8_t
9664 {0, C, 0, C, 0, C, 0, C} which can be loaded using
9668 /* We can load this constant by using VDUP and a constant in a
9669 single ARM register. This will be cheaper than a vector
9672 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
9673 return gen_rtx_VEC_DUPLICATE (mode, x);
9676 /* Generate code to load VALS, which is a PARALLEL containing only
9677 constants (for vec_init) or CONST_VECTOR, efficiently into a
9678 register. Returns an RTX to copy into the register, or NULL_RTX
9679 for a PARALLEL that can not be converted into a CONST_VECTOR. */
9682 neon_make_constant (rtx vals)
9684 enum machine_mode mode = GET_MODE (vals);
9686 rtx const_vec = NULL_RTX;
9687 int n_elts = GET_MODE_NUNITS (mode);
9691 if (GET_CODE (vals) == CONST_VECTOR)
9693 else if (GET_CODE (vals) == PARALLEL)
9695 /* A CONST_VECTOR must contain only CONST_INTs and
9696 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
9697 Only store valid constants in a CONST_VECTOR. */
9698 for (i = 0; i < n_elts; ++i)
9700 rtx x = XVECEXP (vals, 0, i);
9701 if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
9704 if (n_const == n_elts)
9705 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
9710 if (const_vec != NULL
9711 && neon_immediate_valid_for_move (const_vec, mode, NULL, NULL))
9712 /* Load using VMOV. On Cortex-A8 this takes one cycle. */
9714 else if ((target = neon_vdup_constant (vals)) != NULL_RTX)
9715 /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON
9716 pipeline cycle; creating the constant takes one or two ARM
9719 else if (const_vec != NULL_RTX)
9720 /* Load from constant pool. On Cortex-A8 this takes two cycles
9721 (for either double or quad vectors). We can not take advantage
9722 of single-cycle VLD1 because we need a PC-relative addressing
9726 /* A PARALLEL containing something not valid inside CONST_VECTOR.
9727 We can not construct an initializer. */
9731 /* Initialize vector TARGET to VALS. */
9734 neon_expand_vector_init (rtx target, rtx vals)
9736 enum machine_mode mode = GET_MODE (target);
9737 enum machine_mode inner_mode = GET_MODE_INNER (mode);
9738 int n_elts = GET_MODE_NUNITS (mode);
9739 int n_var = 0, one_var = -1;
9740 bool all_same = true;
9744 for (i = 0; i < n_elts; ++i)
9746 x = XVECEXP (vals, 0, i);
9747 if (!CONSTANT_P (x))
9748 ++n_var, one_var = i;
9750 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
9756 rtx constant = neon_make_constant (vals);
9757 if (constant != NULL_RTX)
9759 emit_move_insn (target, constant);
9764 /* Splat a single non-constant element if we can. */
9765 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
9767 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
9768 emit_insn (gen_rtx_SET (VOIDmode, target,
9769 gen_rtx_VEC_DUPLICATE (mode, x)));
9773 /* One field is non-constant. Load constant then overwrite varying
9774 field. This is more efficient than using the stack. */
9777 rtx copy = copy_rtx (vals);
9778 rtx index = GEN_INT (one_var);
9780 /* Load constant part of vector, substitute neighboring value for
9782 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
9783 neon_expand_vector_init (target, copy);
9785 /* Insert variable. */
9786 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
9790 emit_insn (gen_neon_vset_lanev8qi (target, x, target, index));
9793 emit_insn (gen_neon_vset_lanev16qi (target, x, target, index));
9796 emit_insn (gen_neon_vset_lanev4hi (target, x, target, index));
9799 emit_insn (gen_neon_vset_lanev8hi (target, x, target, index));
9802 emit_insn (gen_neon_vset_lanev2si (target, x, target, index));
9805 emit_insn (gen_neon_vset_lanev4si (target, x, target, index));
9808 emit_insn (gen_neon_vset_lanev2sf (target, x, target, index));
9811 emit_insn (gen_neon_vset_lanev4sf (target, x, target, index));
9814 emit_insn (gen_neon_vset_lanev2di (target, x, target, index));
9822 /* Construct the vector in memory one field at a time
9823 and load the whole vector. */
9824 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
9825 for (i = 0; i < n_elts; i++)
9826 emit_move_insn (adjust_address_nv (mem, inner_mode,
9827 i * GET_MODE_SIZE (inner_mode)),
9828 XVECEXP (vals, 0, i));
9829 emit_move_insn (target, mem);
9832 /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise
9833 ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so
9834 reported source locations are bogus. */
9837 bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
9842 gcc_assert (CONST_INT_P (operand));
9844 lane = INTVAL (operand);
9846 if (lane < low || lane >= high)
9850 /* Bounds-check lanes. */
9853 neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
9855 bounds_check (operand, low, high, "lane out of range");
9858 /* Bounds-check constants. */
9861 neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
9863 bounds_check (operand, low, high, "constant out of range");
9867 neon_element_bits (enum machine_mode mode)
9870 return GET_MODE_BITSIZE (mode);
9872 return GET_MODE_BITSIZE (GET_MODE_INNER (mode));
9876 /* Predicates for `match_operand' and `match_operator'. */
9878 /* Return TRUE if OP is a valid coprocessor memory address pattern.
9879 WB is true if full writeback address modes are allowed and is false
9880 if limited writeback address modes (POST_INC and PRE_DEC) are
9884 arm_coproc_mem_operand (rtx op, bool wb)
9888 /* Reject eliminable registers. */
9889 if (! (reload_in_progress || reload_completed)
9890 && ( reg_mentioned_p (frame_pointer_rtx, op)
9891 || reg_mentioned_p (arg_pointer_rtx, op)
9892 || reg_mentioned_p (virtual_incoming_args_rtx, op)
9893 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
9894 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
9895 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
9898 /* Constants are converted into offsets from labels. */
9904 if (reload_completed
9905 && (GET_CODE (ind) == LABEL_REF
9906 || (GET_CODE (ind) == CONST
9907 && GET_CODE (XEXP (ind, 0)) == PLUS
9908 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
9909 && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
9912 /* Match: (mem (reg)). */
9914 return arm_address_register_rtx_p (ind, 0);
9916 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
9917 acceptable in any case (subject to verification by
9918 arm_address_register_rtx_p). We need WB to be true to accept
9919 PRE_INC and POST_DEC. */
9920 if (GET_CODE (ind) == POST_INC
9921 || GET_CODE (ind) == PRE_DEC
9923 && (GET_CODE (ind) == PRE_INC
9924 || GET_CODE (ind) == POST_DEC)))
9925 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
9928 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
9929 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
9930 && GET_CODE (XEXP (ind, 1)) == PLUS
9931 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
9932 ind = XEXP (ind, 1);
9937 if (GET_CODE (ind) == PLUS
9938 && REG_P (XEXP (ind, 0))
9939 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
9940 && CONST_INT_P (XEXP (ind, 1))
9941 && INTVAL (XEXP (ind, 1)) > -1024
9942 && INTVAL (XEXP (ind, 1)) < 1024
9943 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
9949 /* Return TRUE if OP is a memory operand which we can load or store a vector
9950 to/from. TYPE is one of the following values:
9951 0 - Vector load/stor (vldr)
9952 1 - Core registers (ldm)
9953 2 - Element/structure loads (vld1)
9956 neon_vector_mem_operand (rtx op, int type)
9960 /* Reject eliminable registers. */
9961 if (! (reload_in_progress || reload_completed)
9962 && ( reg_mentioned_p (frame_pointer_rtx, op)
9963 || reg_mentioned_p (arg_pointer_rtx, op)
9964 || reg_mentioned_p (virtual_incoming_args_rtx, op)
9965 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
9966 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
9967 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
9970 /* Constants are converted into offsets from labels. */
9976 if (reload_completed
9977 && (GET_CODE (ind) == LABEL_REF
9978 || (GET_CODE (ind) == CONST
9979 && GET_CODE (XEXP (ind, 0)) == PLUS
9980 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
9981 && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
9984 /* Match: (mem (reg)). */
9986 return arm_address_register_rtx_p (ind, 0);
9988 /* Allow post-increment with Neon registers. */
9989 if ((type != 1 && GET_CODE (ind) == POST_INC)
9990 || (type == 0 && GET_CODE (ind) == PRE_DEC))
9991 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
9993 /* FIXME: vld1 allows register post-modify. */
9999 && GET_CODE (ind) == PLUS
10000 && REG_P (XEXP (ind, 0))
10001 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
10002 && CONST_INT_P (XEXP (ind, 1))
10003 && INTVAL (XEXP (ind, 1)) > -1024
10004 /* For quad modes, we restrict the constant offset to be slightly less
10005 than what the instruction format permits. We have no such constraint
10006 on double mode offsets. (This must match arm_legitimate_index_p.) */
10007 && (INTVAL (XEXP (ind, 1))
10008 < (VALID_NEON_QREG_MODE (GET_MODE (op))? 1016 : 1024))
10009 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
10015 /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
10018 neon_struct_mem_operand (rtx op)
10022 /* Reject eliminable registers. */
10023 if (! (reload_in_progress || reload_completed)
10024 && ( reg_mentioned_p (frame_pointer_rtx, op)
10025 || reg_mentioned_p (arg_pointer_rtx, op)
10026 || reg_mentioned_p (virtual_incoming_args_rtx, op)
10027 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
10028 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
10029 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
10032 /* Constants are converted into offsets from labels. */
10036 ind = XEXP (op, 0);
10038 if (reload_completed
10039 && (GET_CODE (ind) == LABEL_REF
10040 || (GET_CODE (ind) == CONST
10041 && GET_CODE (XEXP (ind, 0)) == PLUS
10042 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
10043 && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
10046 /* Match: (mem (reg)). */
10048 return arm_address_register_rtx_p (ind, 0);
10050 /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
10051 if (GET_CODE (ind) == POST_INC
10052 || GET_CODE (ind) == PRE_DEC)
10053 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
10058 /* Return true if X is a register that will be eliminated later on. */
10060 arm_eliminable_register (rtx x)
10062 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
10063 || REGNO (x) == ARG_POINTER_REGNUM
10064 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
10065 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
10068 /* Return GENERAL_REGS if a scratch register required to reload x to/from
10069 coprocessor registers. Otherwise return NO_REGS. */
10072 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
10074 if (mode == HFmode)
10076 if (!TARGET_NEON_FP16)
10077 return GENERAL_REGS;
10078 if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2))
10080 return GENERAL_REGS;
10083 /* The neon move patterns handle all legitimate vector and struct
10086 && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
10087 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
10088 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
10089 || VALID_NEON_STRUCT_MODE (mode)))
10092 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
10095 return GENERAL_REGS;
10098 /* Values which must be returned in the most-significant end of the return
10102 arm_return_in_msb (const_tree valtype)
10104 return (TARGET_AAPCS_BASED
10105 && BYTES_BIG_ENDIAN
10106 && (AGGREGATE_TYPE_P (valtype)
10107 || TREE_CODE (valtype) == COMPLEX_TYPE
10108 || FIXED_POINT_TYPE_P (valtype)));
10111 /* Return TRUE if X references a SYMBOL_REF. */
10113 symbol_mentioned_p (rtx x)
10118 if (GET_CODE (x) == SYMBOL_REF)
10121 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
10122 are constant offsets, not symbols. */
10123 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
10126 fmt = GET_RTX_FORMAT (GET_CODE (x));
10128 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
10134 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10135 if (symbol_mentioned_p (XVECEXP (x, i, j)))
10138 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
10145 /* Return TRUE if X references a LABEL_REF. */
10147 label_mentioned_p (rtx x)
10152 if (GET_CODE (x) == LABEL_REF)
10155 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
10156 instruction, but they are constant offsets, not symbols. */
10157 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
10160 fmt = GET_RTX_FORMAT (GET_CODE (x));
10161 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
10167 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10168 if (label_mentioned_p (XVECEXP (x, i, j)))
10171 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
10179 tls_mentioned_p (rtx x)
10181 switch (GET_CODE (x))
10184 return tls_mentioned_p (XEXP (x, 0));
10187 if (XINT (x, 1) == UNSPEC_TLS)
10195 /* Must not copy any rtx that uses a pc-relative address. */
10198 arm_note_pic_base (rtx *x, void *date ATTRIBUTE_UNUSED)
10200 if (GET_CODE (*x) == UNSPEC
10201 && (XINT (*x, 1) == UNSPEC_PIC_BASE
10202 || XINT (*x, 1) == UNSPEC_PIC_UNIFIED))
10208 arm_cannot_copy_insn_p (rtx insn)
10210 /* The tls call insn cannot be copied, as it is paired with a data
10212 if (recog_memoized (insn) == CODE_FOR_tlscall)
10215 return for_each_rtx (&PATTERN (insn), arm_note_pic_base, NULL);
10219 minmax_code (rtx x)
10221 enum rtx_code code = GET_CODE (x);
10234 gcc_unreachable ();
10238 /* Match pair of min/max operators that can be implemented via usat/ssat. */
10241 arm_sat_operator_match (rtx lo_bound, rtx hi_bound,
10242 int *mask, bool *signed_sat)
10244 /* The high bound must be a power of two minus one. */
10245 int log = exact_log2 (INTVAL (hi_bound) + 1);
10249 /* The low bound is either zero (for usat) or one less than the
10250 negation of the high bound (for ssat). */
10251 if (INTVAL (lo_bound) == 0)
10256 *signed_sat = false;
10261 if (INTVAL (lo_bound) == -INTVAL (hi_bound) - 1)
10266 *signed_sat = true;
10274 /* Return 1 if memory locations are adjacent. */
10276 adjacent_mem_locations (rtx a, rtx b)
10278 /* We don't guarantee to preserve the order of these memory refs. */
10279 if (volatile_refs_p (a) || volatile_refs_p (b))
10282 if ((REG_P (XEXP (a, 0))
10283 || (GET_CODE (XEXP (a, 0)) == PLUS
10284 && CONST_INT_P (XEXP (XEXP (a, 0), 1))))
10285 && (REG_P (XEXP (b, 0))
10286 || (GET_CODE (XEXP (b, 0)) == PLUS
10287 && CONST_INT_P (XEXP (XEXP (b, 0), 1)))))
10289 HOST_WIDE_INT val0 = 0, val1 = 0;
10293 if (GET_CODE (XEXP (a, 0)) == PLUS)
10295 reg0 = XEXP (XEXP (a, 0), 0);
10296 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
10299 reg0 = XEXP (a, 0);
10301 if (GET_CODE (XEXP (b, 0)) == PLUS)
10303 reg1 = XEXP (XEXP (b, 0), 0);
10304 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
10307 reg1 = XEXP (b, 0);
10309 /* Don't accept any offset that will require multiple
10310 instructions to handle, since this would cause the
10311 arith_adjacentmem pattern to output an overlong sequence. */
10312 if (!const_ok_for_op (val0, PLUS) || !const_ok_for_op (val1, PLUS))
10315 /* Don't allow an eliminable register: register elimination can make
10316 the offset too large. */
10317 if (arm_eliminable_register (reg0))
10320 val_diff = val1 - val0;
10324 /* If the target has load delay slots, then there's no benefit
10325 to using an ldm instruction unless the offset is zero and
10326 we are optimizing for size. */
10327 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
10328 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
10329 && (val_diff == 4 || val_diff == -4));
10332 return ((REGNO (reg0) == REGNO (reg1))
10333 && (val_diff == 4 || val_diff == -4));
10339 /* Return true if OP is a valid load or store multiple operation. LOAD is true
10340 for load operations, false for store operations. CONSECUTIVE is true
10341 if the register numbers in the operation must be consecutive in the register
10342 bank. RETURN_PC is true if value is to be loaded in PC.
10343 The pattern we are trying to match for load is:
10344 [(SET (R_d0) (MEM (PLUS (addr) (offset))))
10345 (SET (R_d1) (MEM (PLUS (addr) (offset + <reg_increment>))))
10348 (SET (R_dn) (MEM (PLUS (addr) (offset + n * <reg_increment>))))
10351 1. If offset is 0, first insn should be (SET (R_d0) (MEM (src_addr))).
10352 2. REGNO (R_d0) < REGNO (R_d1) < ... < REGNO (R_dn).
10353 3. If consecutive is TRUE, then for kth register being loaded,
10354 REGNO (R_dk) = REGNO (R_d0) + k.
10355 The pattern for store is similar. */
10357 ldm_stm_operation_p (rtx op, bool load, enum machine_mode mode,
10358 bool consecutive, bool return_pc)
10360 HOST_WIDE_INT count = XVECLEN (op, 0);
10361 rtx reg, mem, addr;
10363 unsigned first_regno;
10364 HOST_WIDE_INT i = 1, base = 0, offset = 0;
10366 bool addr_reg_in_reglist = false;
10367 bool update = false;
10372 /* If not in SImode, then registers must be consecutive
10373 (e.g., VLDM instructions for DFmode). */
10374 gcc_assert ((mode == SImode) || consecutive);
10375 /* Setting return_pc for stores is illegal. */
10376 gcc_assert (!return_pc || load);
10378 /* Set up the increments and the regs per val based on the mode. */
10379 reg_increment = GET_MODE_SIZE (mode);
10380 regs_per_val = reg_increment / 4;
10381 offset_adj = return_pc ? 1 : 0;
10384 || GET_CODE (XVECEXP (op, 0, offset_adj)) != SET
10385 || (load && !REG_P (SET_DEST (XVECEXP (op, 0, offset_adj)))))
10388 /* Check if this is a write-back. */
10389 elt = XVECEXP (op, 0, offset_adj);
10390 if (GET_CODE (SET_SRC (elt)) == PLUS)
10396 /* The offset adjustment must be the number of registers being
10397 popped times the size of a single register. */
10398 if (!REG_P (SET_DEST (elt))
10399 || !REG_P (XEXP (SET_SRC (elt), 0))
10400 || (REGNO (SET_DEST (elt)) != REGNO (XEXP (SET_SRC (elt), 0)))
10401 || !CONST_INT_P (XEXP (SET_SRC (elt), 1))
10402 || INTVAL (XEXP (SET_SRC (elt), 1)) !=
10403 ((count - 1 - offset_adj) * reg_increment))
10407 i = i + offset_adj;
10408 base = base + offset_adj;
10409 /* Perform a quick check so we don't blow up below. If only one reg is loaded,
10410 success depends on the type: VLDM can do just one reg,
10411 LDM must do at least two. */
10412 if ((count <= i) && (mode == SImode))
10415 elt = XVECEXP (op, 0, i - 1);
10416 if (GET_CODE (elt) != SET)
10421 reg = SET_DEST (elt);
10422 mem = SET_SRC (elt);
10426 reg = SET_SRC (elt);
10427 mem = SET_DEST (elt);
10430 if (!REG_P (reg) || !MEM_P (mem))
10433 regno = REGNO (reg);
10434 first_regno = regno;
10435 addr = XEXP (mem, 0);
10436 if (GET_CODE (addr) == PLUS)
10438 if (!CONST_INT_P (XEXP (addr, 1)))
10441 offset = INTVAL (XEXP (addr, 1));
10442 addr = XEXP (addr, 0);
10448 /* Don't allow SP to be loaded unless it is also the base register. It
10449 guarantees that SP is reset correctly when an LDM instruction
10450 is interruptted. Otherwise, we might end up with a corrupt stack. */
10451 if (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != SP_REGNUM))
10454 for (; i < count; i++)
10456 elt = XVECEXP (op, 0, i);
10457 if (GET_CODE (elt) != SET)
10462 reg = SET_DEST (elt);
10463 mem = SET_SRC (elt);
10467 reg = SET_SRC (elt);
10468 mem = SET_DEST (elt);
10472 || GET_MODE (reg) != mode
10473 || REGNO (reg) <= regno
10476 (unsigned int) (first_regno + regs_per_val * (i - base))))
10477 /* Don't allow SP to be loaded unless it is also the base register. It
10478 guarantees that SP is reset correctly when an LDM instruction
10479 is interrupted. Otherwise, we might end up with a corrupt stack. */
10480 || (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != SP_REGNUM))
10482 || GET_MODE (mem) != mode
10483 || ((GET_CODE (XEXP (mem, 0)) != PLUS
10484 || !rtx_equal_p (XEXP (XEXP (mem, 0), 0), addr)
10485 || !CONST_INT_P (XEXP (XEXP (mem, 0), 1))
10486 || (INTVAL (XEXP (XEXP (mem, 0), 1)) !=
10487 offset + (i - base) * reg_increment))
10488 && (!REG_P (XEXP (mem, 0))
10489 || offset + (i - base) * reg_increment != 0)))
10492 regno = REGNO (reg);
10493 if (regno == REGNO (addr))
10494 addr_reg_in_reglist = true;
10499 if (update && addr_reg_in_reglist)
10502 /* For Thumb-1, address register is always modified - either by write-back
10503 or by explicit load. If the pattern does not describe an update,
10504 then the address register must be in the list of loaded registers. */
10506 return update || addr_reg_in_reglist;
10512 /* Return true iff it would be profitable to turn a sequence of NOPS loads
10513 or stores (depending on IS_STORE) into a load-multiple or store-multiple
10514 instruction. ADD_OFFSET is nonzero if the base address register needs
10515 to be modified with an add instruction before we can use it. */
10518 multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED,
10519 int nops, HOST_WIDE_INT add_offset)
10521 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
10522 if the offset isn't small enough. The reason 2 ldrs are faster
10523 is because these ARMs are able to do more than one cache access
10524 in a single cycle. The ARM9 and StrongARM have Harvard caches,
10525 whilst the ARM8 has a double bandwidth cache. This means that
10526 these cores can do both an instruction fetch and a data fetch in
10527 a single cycle, so the trick of calculating the address into a
10528 scratch register (one of the result regs) and then doing a load
10529 multiple actually becomes slower (and no smaller in code size).
10530 That is the transformation
10532 ldr rd1, [rbase + offset]
10533 ldr rd2, [rbase + offset + 4]
10537 add rd1, rbase, offset
10538 ldmia rd1, {rd1, rd2}
10540 produces worse code -- '3 cycles + any stalls on rd2' instead of
10541 '2 cycles + any stalls on rd2'. On ARMs with only one cache
10542 access per cycle, the first sequence could never complete in less
10543 than 6 cycles, whereas the ldm sequence would only take 5 and
10544 would make better use of sequential accesses if not hitting the
10547 We cheat here and test 'arm_ld_sched' which we currently know to
10548 only be true for the ARM8, ARM9 and StrongARM. If this ever
10549 changes, then the test below needs to be reworked. */
10550 if (nops == 2 && arm_ld_sched && add_offset != 0)
10553 /* XScale has load-store double instructions, but they have stricter
10554 alignment requirements than load-store multiple, so we cannot
10557 For XScale ldm requires 2 + NREGS cycles to complete and blocks
10558 the pipeline until completion.
10566 An ldr instruction takes 1-3 cycles, but does not block the
10575 Best case ldr will always win. However, the more ldr instructions
10576 we issue, the less likely we are to be able to schedule them well.
10577 Using ldr instructions also increases code size.
10579 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
10580 for counts of 3 or 4 regs. */
10581 if (nops <= 2 && arm_tune_xscale && !optimize_size)
10586 /* Subroutine of load_multiple_sequence and store_multiple_sequence.
10587 Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
10588 an array ORDER which describes the sequence to use when accessing the
10589 offsets that produces an ascending order. In this sequence, each
10590 offset must be larger by exactly 4 than the previous one. ORDER[0]
10591 must have been filled in with the lowest offset by the caller.
10592 If UNSORTED_REGS is nonnull, it is an array of register numbers that
10593 we use to verify that ORDER produces an ascending order of registers.
10594 Return true if it was possible to construct such an order, false if
10598 compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order,
10599 int *unsorted_regs)
10602 for (i = 1; i < nops; i++)
10606 order[i] = order[i - 1];
10607 for (j = 0; j < nops; j++)
10608 if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4)
10610 /* We must find exactly one offset that is higher than the
10611 previous one by 4. */
10612 if (order[i] != order[i - 1])
10616 if (order[i] == order[i - 1])
10618 /* The register numbers must be ascending. */
10619 if (unsorted_regs != NULL
10620 && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]])
10626 /* Used to determine in a peephole whether a sequence of load
10627 instructions can be changed into a load-multiple instruction.
10628 NOPS is the number of separate load instructions we are examining. The
10629 first NOPS entries in OPERANDS are the destination registers, the
10630 next NOPS entries are memory operands. If this function is
10631 successful, *BASE is set to the common base register of the memory
10632 accesses; *LOAD_OFFSET is set to the first memory location's offset
10633 from that base register.
10634 REGS is an array filled in with the destination register numbers.
10635 SAVED_ORDER (if nonnull), is an array filled in with an order that maps
10636 insn numbers to an ascending order of stores. If CHECK_REGS is true,
10637 the sequence of registers in REGS matches the loads from ascending memory
10638 locations, and the function verifies that the register numbers are
10639 themselves ascending. If CHECK_REGS is false, the register numbers
10640 are stored in the order they are found in the operands. */
10642 load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
10643 int *base, HOST_WIDE_INT *load_offset, bool check_regs)
10645 int unsorted_regs[MAX_LDM_STM_OPS];
10646 HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
10647 int order[MAX_LDM_STM_OPS];
10648 rtx base_reg_rtx = NULL;
10652 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
10653 easily extended if required. */
10654 gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
10656 memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
10658 /* Loop over the operands and check that the memory references are
10659 suitable (i.e. immediate offsets from the same base register). At
10660 the same time, extract the target register, and the memory
10662 for (i = 0; i < nops; i++)
10667 /* Convert a subreg of a mem into the mem itself. */
10668 if (GET_CODE (operands[nops + i]) == SUBREG)
10669 operands[nops + i] = alter_subreg (operands + (nops + i), true);
10671 gcc_assert (MEM_P (operands[nops + i]));
10673 /* Don't reorder volatile memory references; it doesn't seem worth
10674 looking for the case where the order is ok anyway. */
10675 if (MEM_VOLATILE_P (operands[nops + i]))
10678 offset = const0_rtx;
10680 if ((REG_P (reg = XEXP (operands[nops + i], 0))
10681 || (GET_CODE (reg) == SUBREG
10682 && REG_P (reg = SUBREG_REG (reg))))
10683 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
10684 && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
10685 || (GET_CODE (reg) == SUBREG
10686 && REG_P (reg = SUBREG_REG (reg))))
10687 && (CONST_INT_P (offset
10688 = XEXP (XEXP (operands[nops + i], 0), 1)))))
10692 base_reg = REGNO (reg);
10693 base_reg_rtx = reg;
10694 if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
10697 else if (base_reg != (int) REGNO (reg))
10698 /* Not addressed from the same base register. */
10701 unsorted_regs[i] = (REG_P (operands[i])
10702 ? REGNO (operands[i])
10703 : REGNO (SUBREG_REG (operands[i])));
10705 /* If it isn't an integer register, or if it overwrites the
10706 base register but isn't the last insn in the list, then
10707 we can't do this. */
10708 if (unsorted_regs[i] < 0
10709 || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
10710 || unsorted_regs[i] > 14
10711 || (i != nops - 1 && unsorted_regs[i] == base_reg))
10714 /* Don't allow SP to be loaded unless it is also the base
10715 register. It guarantees that SP is reset correctly when
10716 an LDM instruction is interrupted. Otherwise, we might
10717 end up with a corrupt stack. */
10718 if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM)
10721 unsorted_offsets[i] = INTVAL (offset);
10722 if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
10726 /* Not a suitable memory address. */
10730 /* All the useful information has now been extracted from the
10731 operands into unsorted_regs and unsorted_offsets; additionally,
10732 order[0] has been set to the lowest offset in the list. Sort
10733 the offsets into order, verifying that they are adjacent, and
10734 check that the register numbers are ascending. */
10735 if (!compute_offset_order (nops, unsorted_offsets, order,
10736 check_regs ? unsorted_regs : NULL))
10740 memcpy (saved_order, order, sizeof order);
10746 for (i = 0; i < nops; i++)
10747 regs[i] = unsorted_regs[check_regs ? order[i] : i];
10749 *load_offset = unsorted_offsets[order[0]];
10753 && !peep2_reg_dead_p (nops, base_reg_rtx))
10756 if (unsorted_offsets[order[0]] == 0)
10757 ldm_case = 1; /* ldmia */
10758 else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
10759 ldm_case = 2; /* ldmib */
10760 else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
10761 ldm_case = 3; /* ldmda */
10762 else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
10763 ldm_case = 4; /* ldmdb */
10764 else if (const_ok_for_arm (unsorted_offsets[order[0]])
10765 || const_ok_for_arm (-unsorted_offsets[order[0]]))
10770 if (!multiple_operation_profitable_p (false, nops,
10772 ? unsorted_offsets[order[0]] : 0))
10778 /* Used to determine in a peephole whether a sequence of store instructions can
10779 be changed into a store-multiple instruction.
10780 NOPS is the number of separate store instructions we are examining.
10781 NOPS_TOTAL is the total number of instructions recognized by the peephole
10783 The first NOPS entries in OPERANDS are the source registers, the next
10784 NOPS entries are memory operands. If this function is successful, *BASE is
10785 set to the common base register of the memory accesses; *LOAD_OFFSET is set
10786 to the first memory location's offset from that base register. REGS is an
10787 array filled in with the source register numbers, REG_RTXS (if nonnull) is
10788 likewise filled with the corresponding rtx's.
10789 SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn
10790 numbers to an ascending order of stores.
10791 If CHECK_REGS is true, the sequence of registers in *REGS matches the stores
10792 from ascending memory locations, and the function verifies that the register
10793 numbers are themselves ascending. If CHECK_REGS is false, the register
10794 numbers are stored in the order they are found in the operands. */
10796 store_multiple_sequence (rtx *operands, int nops, int nops_total,
10797 int *regs, rtx *reg_rtxs, int *saved_order, int *base,
10798 HOST_WIDE_INT *load_offset, bool check_regs)
10800 int unsorted_regs[MAX_LDM_STM_OPS];
10801 rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS];
10802 HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
10803 int order[MAX_LDM_STM_OPS];
10805 rtx base_reg_rtx = NULL;
10808 /* Write back of base register is currently only supported for Thumb 1. */
10809 int base_writeback = TARGET_THUMB1;
10811 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
10812 easily extended if required. */
10813 gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS);
10815 memset (order, 0, MAX_LDM_STM_OPS * sizeof (int));
10817 /* Loop over the operands and check that the memory references are
10818 suitable (i.e. immediate offsets from the same base register). At
10819 the same time, extract the target register, and the memory
10821 for (i = 0; i < nops; i++)
10826 /* Convert a subreg of a mem into the mem itself. */
10827 if (GET_CODE (operands[nops + i]) == SUBREG)
10828 operands[nops + i] = alter_subreg (operands + (nops + i), true);
10830 gcc_assert (MEM_P (operands[nops + i]));
10832 /* Don't reorder volatile memory references; it doesn't seem worth
10833 looking for the case where the order is ok anyway. */
10834 if (MEM_VOLATILE_P (operands[nops + i]))
10837 offset = const0_rtx;
10839 if ((REG_P (reg = XEXP (operands[nops + i], 0))
10840 || (GET_CODE (reg) == SUBREG
10841 && REG_P (reg = SUBREG_REG (reg))))
10842 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
10843 && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
10844 || (GET_CODE (reg) == SUBREG
10845 && REG_P (reg = SUBREG_REG (reg))))
10846 && (CONST_INT_P (offset
10847 = XEXP (XEXP (operands[nops + i], 0), 1)))))
10849 unsorted_reg_rtxs[i] = (REG_P (operands[i])
10850 ? operands[i] : SUBREG_REG (operands[i]));
10851 unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]);
10855 base_reg = REGNO (reg);
10856 base_reg_rtx = reg;
10857 if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM)
10860 else if (base_reg != (int) REGNO (reg))
10861 /* Not addressed from the same base register. */
10864 /* If it isn't an integer register, then we can't do this. */
10865 if (unsorted_regs[i] < 0
10866 || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM)
10867 /* The effects are unpredictable if the base register is
10868 both updated and stored. */
10869 || (base_writeback && unsorted_regs[i] == base_reg)
10870 || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM)
10871 || unsorted_regs[i] > 14)
10874 unsorted_offsets[i] = INTVAL (offset);
10875 if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
10879 /* Not a suitable memory address. */
10883 /* All the useful information has now been extracted from the
10884 operands into unsorted_regs and unsorted_offsets; additionally,
10885 order[0] has been set to the lowest offset in the list. Sort
10886 the offsets into order, verifying that they are adjacent, and
10887 check that the register numbers are ascending. */
10888 if (!compute_offset_order (nops, unsorted_offsets, order,
10889 check_regs ? unsorted_regs : NULL))
10893 memcpy (saved_order, order, sizeof order);
10899 for (i = 0; i < nops; i++)
10901 regs[i] = unsorted_regs[check_regs ? order[i] : i];
10903 reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i];
10906 *load_offset = unsorted_offsets[order[0]];
10910 && !peep2_reg_dead_p (nops_total, base_reg_rtx))
10913 if (unsorted_offsets[order[0]] == 0)
10914 stm_case = 1; /* stmia */
10915 else if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
10916 stm_case = 2; /* stmib */
10917 else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
10918 stm_case = 3; /* stmda */
10919 else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)
10920 stm_case = 4; /* stmdb */
10924 if (!multiple_operation_profitable_p (false, nops, 0))
10930 /* Routines for use in generating RTL. */
10932 /* Generate a load-multiple instruction. COUNT is the number of loads in
10933 the instruction; REGS and MEMS are arrays containing the operands.
10934 BASEREG is the base register to be used in addressing the memory operands.
10935 WBACK_OFFSET is nonzero if the instruction should update the base
10939 arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
10940 HOST_WIDE_INT wback_offset)
10945 if (!multiple_operation_profitable_p (false, count, 0))
10951 for (i = 0; i < count; i++)
10952 emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]);
10954 if (wback_offset != 0)
10955 emit_move_insn (basereg, plus_constant (Pmode, basereg, wback_offset));
10957 seq = get_insns ();
10963 result = gen_rtx_PARALLEL (VOIDmode,
10964 rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
10965 if (wback_offset != 0)
10967 XVECEXP (result, 0, 0)
10968 = gen_rtx_SET (VOIDmode, basereg,
10969 plus_constant (Pmode, basereg, wback_offset));
10974 for (j = 0; i < count; i++, j++)
10975 XVECEXP (result, 0, i)
10976 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]);
10981 /* Generate a store-multiple instruction. COUNT is the number of stores in
10982 the instruction; REGS and MEMS are arrays containing the operands.
10983 BASEREG is the base register to be used in addressing the memory operands.
10984 WBACK_OFFSET is nonzero if the instruction should update the base
10988 arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
10989 HOST_WIDE_INT wback_offset)
10994 if (GET_CODE (basereg) == PLUS)
10995 basereg = XEXP (basereg, 0);
10997 if (!multiple_operation_profitable_p (false, count, 0))
11003 for (i = 0; i < count; i++)
11004 emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i]));
11006 if (wback_offset != 0)
11007 emit_move_insn (basereg, plus_constant (Pmode, basereg, wback_offset));
11009 seq = get_insns ();
11015 result = gen_rtx_PARALLEL (VOIDmode,
11016 rtvec_alloc (count + (wback_offset != 0 ? 1 : 0)));
11017 if (wback_offset != 0)
11019 XVECEXP (result, 0, 0)
11020 = gen_rtx_SET (VOIDmode, basereg,
11021 plus_constant (Pmode, basereg, wback_offset));
11026 for (j = 0; i < count; i++, j++)
11027 XVECEXP (result, 0, i)
11028 = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j]));
11033 /* Generate either a load-multiple or a store-multiple instruction. This
11034 function can be used in situations where we can start with a single MEM
11035 rtx and adjust its address upwards.
11036 COUNT is the number of operations in the instruction, not counting a
11037 possible update of the base register. REGS is an array containing the
11039 BASEREG is the base register to be used in addressing the memory operands,
11040 which are constructed from BASEMEM.
11041 WRITE_BACK specifies whether the generated instruction should include an
11042 update of the base register.
11043 OFFSETP is used to pass an offset to and from this function; this offset
11044 is not used when constructing the address (instead BASEMEM should have an
11045 appropriate offset in its address), it is used only for setting
11046 MEM_OFFSET. It is updated only if WRITE_BACK is true.*/
11049 arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg,
11050 bool write_back, rtx basemem, HOST_WIDE_INT *offsetp)
11052 rtx mems[MAX_LDM_STM_OPS];
11053 HOST_WIDE_INT offset = *offsetp;
11056 gcc_assert (count <= MAX_LDM_STM_OPS);
11058 if (GET_CODE (basereg) == PLUS)
11059 basereg = XEXP (basereg, 0);
11061 for (i = 0; i < count; i++)
11063 rtx addr = plus_constant (Pmode, basereg, i * 4);
11064 mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset);
11072 return arm_gen_load_multiple_1 (count, regs, mems, basereg,
11073 write_back ? 4 * count : 0);
11075 return arm_gen_store_multiple_1 (count, regs, mems, basereg,
11076 write_back ? 4 * count : 0);
11080 arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back,
11081 rtx basemem, HOST_WIDE_INT *offsetp)
11083 return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem,
11088 arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back,
11089 rtx basemem, HOST_WIDE_INT *offsetp)
11091 return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem,
11095 /* Called from a peephole2 expander to turn a sequence of loads into an
11096 LDM instruction. OPERANDS are the operands found by the peephole matcher;
11097 NOPS indicates how many separate loads we are trying to combine. SORT_REGS
11098 is true if we can reorder the registers because they are used commutatively
11100 Returns true iff we could generate a new instruction. */
11103 gen_ldm_seq (rtx *operands, int nops, bool sort_regs)
11105 int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
11106 rtx mems[MAX_LDM_STM_OPS];
11107 int i, j, base_reg;
11109 HOST_WIDE_INT offset;
11110 int write_back = FALSE;
11114 ldm_case = load_multiple_sequence (operands, nops, regs, mem_order,
11115 &base_reg, &offset, !sort_regs);
11121 for (i = 0; i < nops - 1; i++)
11122 for (j = i + 1; j < nops; j++)
11123 if (regs[i] > regs[j])
11129 base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
11133 gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx));
11134 gcc_assert (ldm_case == 1 || ldm_case == 5);
11140 rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]);
11141 emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset)));
11143 if (!TARGET_THUMB1)
11145 base_reg = regs[0];
11146 base_reg_rtx = newbase;
11150 for (i = 0; i < nops; i++)
11152 addr = plus_constant (Pmode, base_reg_rtx, offset + i * 4);
11153 mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
11156 emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx,
11157 write_back ? offset + i * 4 : 0));
11161 /* Called from a peephole2 expander to turn a sequence of stores into an
11162 STM instruction. OPERANDS are the operands found by the peephole matcher;
11163 NOPS indicates how many separate stores we are trying to combine.
11164 Returns true iff we could generate a new instruction. */
11167 gen_stm_seq (rtx *operands, int nops)
11170 int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
11171 rtx mems[MAX_LDM_STM_OPS];
11174 HOST_WIDE_INT offset;
11175 int write_back = FALSE;
11178 bool base_reg_dies;
11180 stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL,
11181 mem_order, &base_reg, &offset, true);
11186 base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
11188 base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx);
11191 gcc_assert (base_reg_dies);
11197 gcc_assert (base_reg_dies);
11198 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
11202 addr = plus_constant (Pmode, base_reg_rtx, offset);
11204 for (i = 0; i < nops; i++)
11206 addr = plus_constant (Pmode, base_reg_rtx, offset + i * 4);
11207 mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
11210 emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx,
11211 write_back ? offset + i * 4 : 0));
11215 /* Called from a peephole2 expander to turn a sequence of stores that are
11216 preceded by constant loads into an STM instruction. OPERANDS are the
11217 operands found by the peephole matcher; NOPS indicates how many
11218 separate stores we are trying to combine; there are 2 * NOPS
11219 instructions in the peephole.
11220 Returns true iff we could generate a new instruction. */
11223 gen_const_stm_seq (rtx *operands, int nops)
11225 int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS];
11226 int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS];
11227 rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS];
11228 rtx mems[MAX_LDM_STM_OPS];
11231 HOST_WIDE_INT offset;
11232 int write_back = FALSE;
11235 bool base_reg_dies;
11237 HARD_REG_SET allocated;
11239 stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs,
11240 mem_order, &base_reg, &offset, false);
11245 memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs);
11247 /* If the same register is used more than once, try to find a free
11249 CLEAR_HARD_REG_SET (allocated);
11250 for (i = 0; i < nops; i++)
11252 for (j = i + 1; j < nops; j++)
11253 if (regs[i] == regs[j])
11255 rtx t = peep2_find_free_register (0, nops * 2,
11256 TARGET_THUMB1 ? "l" : "r",
11257 SImode, &allocated);
11261 regs[i] = REGNO (t);
11265 /* Compute an ordering that maps the register numbers to an ascending
11268 for (i = 0; i < nops; i++)
11269 if (regs[i] < regs[reg_order[0]])
11272 for (i = 1; i < nops; i++)
11274 int this_order = reg_order[i - 1];
11275 for (j = 0; j < nops; j++)
11276 if (regs[j] > regs[reg_order[i - 1]]
11277 && (this_order == reg_order[i - 1]
11278 || regs[j] < regs[this_order]))
11280 reg_order[i] = this_order;
11283 /* Ensure that registers that must be live after the instruction end
11284 up with the correct value. */
11285 for (i = 0; i < nops; i++)
11287 int this_order = reg_order[i];
11288 if ((this_order != mem_order[i]
11289 || orig_reg_rtxs[this_order] != reg_rtxs[this_order])
11290 && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order]))
11294 /* Load the constants. */
11295 for (i = 0; i < nops; i++)
11297 rtx op = operands[2 * nops + mem_order[i]];
11298 sorted_regs[i] = regs[reg_order[i]];
11299 emit_move_insn (reg_rtxs[reg_order[i]], op);
11302 base_reg_rtx = gen_rtx_REG (Pmode, base_reg);
11304 base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx);
11307 gcc_assert (base_reg_dies);
11313 gcc_assert (base_reg_dies);
11314 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));
11318 addr = plus_constant (Pmode, base_reg_rtx, offset);
11320 for (i = 0; i < nops; i++)
11322 addr = plus_constant (Pmode, base_reg_rtx, offset + i * 4);
11323 mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]],
11326 emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx,
11327 write_back ? offset + i * 4 : 0));
11331 /* Copy a block of memory using plain ldr/str/ldrh/strh instructions, to permit
11332 unaligned copies on processors which support unaligned semantics for those
11333 instructions. INTERLEAVE_FACTOR can be used to attempt to hide load latency
11334 (using more registers) by doing e.g. load/load/store/store for a factor of 2.
11335 An interleave factor of 1 (the minimum) will perform no interleaving.
11336 Load/store multiple are used for aligned addresses where possible. */
11339 arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
11340 HOST_WIDE_INT length,
11341 unsigned int interleave_factor)
11343 rtx *regs = XALLOCAVEC (rtx, interleave_factor);
11344 int *regnos = XALLOCAVEC (int, interleave_factor);
11345 HOST_WIDE_INT block_size_bytes = interleave_factor * UNITS_PER_WORD;
11346 HOST_WIDE_INT i, j;
11347 HOST_WIDE_INT remaining = length, words;
11348 rtx halfword_tmp = NULL, byte_tmp = NULL;
11350 bool src_aligned = MEM_ALIGN (srcbase) >= BITS_PER_WORD;
11351 bool dst_aligned = MEM_ALIGN (dstbase) >= BITS_PER_WORD;
11352 HOST_WIDE_INT srcoffset, dstoffset;
11353 HOST_WIDE_INT src_autoinc, dst_autoinc;
11356 gcc_assert (1 <= interleave_factor && interleave_factor <= 4);
11358 /* Use hard registers if we have aligned source or destination so we can use
11359 load/store multiple with contiguous registers. */
11360 if (dst_aligned || src_aligned)
11361 for (i = 0; i < interleave_factor; i++)
11362 regs[i] = gen_rtx_REG (SImode, i);
11364 for (i = 0; i < interleave_factor; i++)
11365 regs[i] = gen_reg_rtx (SImode);
11367 dst = copy_addr_to_reg (XEXP (dstbase, 0));
11368 src = copy_addr_to_reg (XEXP (srcbase, 0));
11370 srcoffset = dstoffset = 0;
11372 /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST.
11373 For copying the last bytes we want to subtract this offset again. */
11374 src_autoinc = dst_autoinc = 0;
11376 for (i = 0; i < interleave_factor; i++)
11379 /* Copy BLOCK_SIZE_BYTES chunks. */
11381 for (i = 0; i + block_size_bytes <= length; i += block_size_bytes)
11384 if (src_aligned && interleave_factor > 1)
11386 emit_insn (arm_gen_load_multiple (regnos, interleave_factor, src,
11387 TRUE, srcbase, &srcoffset));
11388 src_autoinc += UNITS_PER_WORD * interleave_factor;
11392 for (j = 0; j < interleave_factor; j++)
11394 addr = plus_constant (Pmode, src, (srcoffset + j * UNITS_PER_WORD
11396 mem = adjust_automodify_address (srcbase, SImode, addr,
11397 srcoffset + j * UNITS_PER_WORD);
11398 emit_insn (gen_unaligned_loadsi (regs[j], mem));
11400 srcoffset += block_size_bytes;
11404 if (dst_aligned && interleave_factor > 1)
11406 emit_insn (arm_gen_store_multiple (regnos, interleave_factor, dst,
11407 TRUE, dstbase, &dstoffset));
11408 dst_autoinc += UNITS_PER_WORD * interleave_factor;
11412 for (j = 0; j < interleave_factor; j++)
11414 addr = plus_constant (Pmode, dst, (dstoffset + j * UNITS_PER_WORD
11416 mem = adjust_automodify_address (dstbase, SImode, addr,
11417 dstoffset + j * UNITS_PER_WORD);
11418 emit_insn (gen_unaligned_storesi (mem, regs[j]));
11420 dstoffset += block_size_bytes;
11423 remaining -= block_size_bytes;
11426 /* Copy any whole words left (note these aren't interleaved with any
11427 subsequent halfword/byte load/stores in the interests of simplicity). */
11429 words = remaining / UNITS_PER_WORD;
11431 gcc_assert (words < interleave_factor);
11433 if (src_aligned && words > 1)
11435 emit_insn (arm_gen_load_multiple (regnos, words, src, TRUE, srcbase,
11437 src_autoinc += UNITS_PER_WORD * words;
11441 for (j = 0; j < words; j++)
11443 addr = plus_constant (Pmode, src,
11444 srcoffset + j * UNITS_PER_WORD - src_autoinc);
11445 mem = adjust_automodify_address (srcbase, SImode, addr,
11446 srcoffset + j * UNITS_PER_WORD);
11447 emit_insn (gen_unaligned_loadsi (regs[j], mem));
11449 srcoffset += words * UNITS_PER_WORD;
11452 if (dst_aligned && words > 1)
11454 emit_insn (arm_gen_store_multiple (regnos, words, dst, TRUE, dstbase,
11456 dst_autoinc += words * UNITS_PER_WORD;
11460 for (j = 0; j < words; j++)
11462 addr = plus_constant (Pmode, dst,
11463 dstoffset + j * UNITS_PER_WORD - dst_autoinc);
11464 mem = adjust_automodify_address (dstbase, SImode, addr,
11465 dstoffset + j * UNITS_PER_WORD);
11466 emit_insn (gen_unaligned_storesi (mem, regs[j]));
11468 dstoffset += words * UNITS_PER_WORD;
11471 remaining -= words * UNITS_PER_WORD;
11473 gcc_assert (remaining < 4);
11475 /* Copy a halfword if necessary. */
11477 if (remaining >= 2)
11479 halfword_tmp = gen_reg_rtx (SImode);
11481 addr = plus_constant (Pmode, src, srcoffset - src_autoinc);
11482 mem = adjust_automodify_address (srcbase, HImode, addr, srcoffset);
11483 emit_insn (gen_unaligned_loadhiu (halfword_tmp, mem));
11485 /* Either write out immediately, or delay until we've loaded the last
11486 byte, depending on interleave factor. */
11487 if (interleave_factor == 1)
11489 addr = plus_constant (Pmode, dst, dstoffset - dst_autoinc);
11490 mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
11491 emit_insn (gen_unaligned_storehi (mem,
11492 gen_lowpart (HImode, halfword_tmp)));
11493 halfword_tmp = NULL;
11501 gcc_assert (remaining < 2);
11503 /* Copy last byte. */
11505 if ((remaining & 1) != 0)
11507 byte_tmp = gen_reg_rtx (SImode);
11509 addr = plus_constant (Pmode, src, srcoffset - src_autoinc);
11510 mem = adjust_automodify_address (srcbase, QImode, addr, srcoffset);
11511 emit_move_insn (gen_lowpart (QImode, byte_tmp), mem);
11513 if (interleave_factor == 1)
11515 addr = plus_constant (Pmode, dst, dstoffset - dst_autoinc);
11516 mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
11517 emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
11526 /* Store last halfword if we haven't done so already. */
11530 addr = plus_constant (Pmode, dst, dstoffset - dst_autoinc);
11531 mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
11532 emit_insn (gen_unaligned_storehi (mem,
11533 gen_lowpart (HImode, halfword_tmp)));
11537 /* Likewise for last byte. */
11541 addr = plus_constant (Pmode, dst, dstoffset - dst_autoinc);
11542 mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
11543 emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
11547 gcc_assert (remaining == 0 && srcoffset == dstoffset);
11550 /* From mips_adjust_block_mem:
11552 Helper function for doing a loop-based block operation on memory
11553 reference MEM. Each iteration of the loop will operate on LENGTH
11556 Create a new base register for use within the loop and point it to
11557 the start of MEM. Create a new memory reference that uses this
11558 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
11561 arm_adjust_block_mem (rtx mem, HOST_WIDE_INT length, rtx *loop_reg,
11564 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
11566 /* Although the new mem does not refer to a known location,
11567 it does keep up to LENGTH bytes of alignment. */
11568 *loop_mem = change_address (mem, BLKmode, *loop_reg);
11569 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
11572 /* From mips_block_move_loop:
11574 Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
11575 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
11576 the memory regions do not overlap. */
11579 arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length,
11580 unsigned int interleave_factor,
11581 HOST_WIDE_INT bytes_per_iter)
11583 rtx label, src_reg, dest_reg, final_src, test;
11584 HOST_WIDE_INT leftover;
11586 leftover = length % bytes_per_iter;
11587 length -= leftover;
11589 /* Create registers and memory references for use within the loop. */
11590 arm_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
11591 arm_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
11593 /* Calculate the value that SRC_REG should have after the last iteration of
11595 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
11596 0, 0, OPTAB_WIDEN);
11598 /* Emit the start of the loop. */
11599 label = gen_label_rtx ();
11600 emit_label (label);
11602 /* Emit the loop body. */
11603 arm_block_move_unaligned_straight (dest, src, bytes_per_iter,
11604 interleave_factor);
11606 /* Move on to the next block. */
11607 emit_move_insn (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
11608 emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
11610 /* Emit the loop condition. */
11611 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
11612 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
11614 /* Mop up any left-over bytes. */
11616 arm_block_move_unaligned_straight (dest, src, leftover, interleave_factor);
11619 /* Emit a block move when either the source or destination is unaligned (not
11620 aligned to a four-byte boundary). This may need further tuning depending on
11621 core type, optimize_size setting, etc. */
11624 arm_movmemqi_unaligned (rtx *operands)
11626 HOST_WIDE_INT length = INTVAL (operands[2]);
11630 bool src_aligned = MEM_ALIGN (operands[1]) >= BITS_PER_WORD;
11631 bool dst_aligned = MEM_ALIGN (operands[0]) >= BITS_PER_WORD;
11632 /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
11633 size of code if optimizing for size. We'll use ldm/stm if src_aligned
11634 or dst_aligned though: allow more interleaving in those cases since the
11635 resulting code can be smaller. */
11636 unsigned int interleave_factor = (src_aligned || dst_aligned) ? 2 : 1;
11637 HOST_WIDE_INT bytes_per_iter = (src_aligned || dst_aligned) ? 8 : 4;
11640 arm_block_move_unaligned_loop (operands[0], operands[1], length,
11641 interleave_factor, bytes_per_iter);
11643 arm_block_move_unaligned_straight (operands[0], operands[1], length,
11644 interleave_factor);
11648 /* Note that the loop created by arm_block_move_unaligned_loop may be
11649 subject to loop unrolling, which makes tuning this condition a little
11652 arm_block_move_unaligned_loop (operands[0], operands[1], length, 4, 16);
11654 arm_block_move_unaligned_straight (operands[0], operands[1], length, 4);
11661 arm_gen_movmemqi (rtx *operands)
11663 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
11664 HOST_WIDE_INT srcoffset, dstoffset;
11666 rtx src, dst, srcbase, dstbase;
11667 rtx part_bytes_reg = NULL;
11670 if (!CONST_INT_P (operands[2])
11671 || !CONST_INT_P (operands[3])
11672 || INTVAL (operands[2]) > 64)
11675 if (unaligned_access && (INTVAL (operands[3]) & 3) != 0)
11676 return arm_movmemqi_unaligned (operands);
11678 if (INTVAL (operands[3]) & 3)
11681 dstbase = operands[0];
11682 srcbase = operands[1];
11684 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
11685 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
11687 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
11688 out_words_to_go = INTVAL (operands[2]) / 4;
11689 last_bytes = INTVAL (operands[2]) & 3;
11690 dstoffset = srcoffset = 0;
11692 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
11693 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
11695 for (i = 0; in_words_to_go >= 2; i+=4)
11697 if (in_words_to_go > 4)
11698 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src,
11699 TRUE, srcbase, &srcoffset));
11701 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go,
11702 src, FALSE, srcbase,
11705 if (out_words_to_go)
11707 if (out_words_to_go > 4)
11708 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst,
11709 TRUE, dstbase, &dstoffset));
11710 else if (out_words_to_go != 1)
11711 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence,
11712 out_words_to_go, dst,
11715 dstbase, &dstoffset));
11718 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
11719 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
11720 if (last_bytes != 0)
11722 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
11728 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
11729 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
11732 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
11733 if (out_words_to_go)
11737 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
11738 sreg = copy_to_reg (mem);
11740 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
11741 emit_move_insn (mem, sreg);
11744 gcc_assert (!in_words_to_go); /* Sanity check */
11747 if (in_words_to_go)
11749 gcc_assert (in_words_to_go > 0);
11751 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
11752 part_bytes_reg = copy_to_mode_reg (SImode, mem);
11755 gcc_assert (!last_bytes || part_bytes_reg);
11757 if (BYTES_BIG_ENDIAN && last_bytes)
11759 rtx tmp = gen_reg_rtx (SImode);
11761 /* The bytes we want are in the top end of the word. */
11762 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
11763 GEN_INT (8 * (4 - last_bytes))));
11764 part_bytes_reg = tmp;
11768 mem = adjust_automodify_address (dstbase, QImode,
11769 plus_constant (Pmode, dst,
11771 dstoffset + last_bytes - 1);
11772 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
11776 tmp = gen_reg_rtx (SImode);
11777 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
11778 part_bytes_reg = tmp;
11785 if (last_bytes > 1)
11787 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
11788 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
11792 rtx tmp = gen_reg_rtx (SImode);
11793 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
11794 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
11795 part_bytes_reg = tmp;
11802 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
11803 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
11810 /* Select a dominance comparison mode if possible for a test of the general
11811 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
11812 COND_OR == DOM_CC_X_AND_Y => (X && Y)
11813 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
11814 COND_OR == DOM_CC_X_OR_Y => (X || Y)
11815 In all cases OP will be either EQ or NE, but we don't need to know which
11816 here. If we are unable to support a dominance comparison we return
11817 CC mode. This will then fail to match for the RTL expressions that
11818 generate this call. */
11820 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
11822 enum rtx_code cond1, cond2;
11825 /* Currently we will probably get the wrong result if the individual
11826 comparisons are not simple. This also ensures that it is safe to
11827 reverse a comparison if necessary. */
11828 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
11830 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
11834 /* The if_then_else variant of this tests the second condition if the
11835 first passes, but is true if the first fails. Reverse the first
11836 condition to get a true "inclusive-or" expression. */
11837 if (cond_or == DOM_CC_NX_OR_Y)
11838 cond1 = reverse_condition (cond1);
11840 /* If the comparisons are not equal, and one doesn't dominate the other,
11841 then we can't do this. */
11843 && !comparison_dominates_p (cond1, cond2)
11844 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
11849 enum rtx_code temp = cond1;
11857 if (cond_or == DOM_CC_X_AND_Y)
11862 case EQ: return CC_DEQmode;
11863 case LE: return CC_DLEmode;
11864 case LEU: return CC_DLEUmode;
11865 case GE: return CC_DGEmode;
11866 case GEU: return CC_DGEUmode;
11867 default: gcc_unreachable ();
11871 if (cond_or == DOM_CC_X_AND_Y)
11883 gcc_unreachable ();
11887 if (cond_or == DOM_CC_X_AND_Y)
11899 gcc_unreachable ();
11903 if (cond_or == DOM_CC_X_AND_Y)
11904 return CC_DLTUmode;
11909 return CC_DLTUmode;
11911 return CC_DLEUmode;
11915 gcc_unreachable ();
11919 if (cond_or == DOM_CC_X_AND_Y)
11920 return CC_DGTUmode;
11925 return CC_DGTUmode;
11927 return CC_DGEUmode;
11931 gcc_unreachable ();
11934 /* The remaining cases only occur when both comparisons are the
11937 gcc_assert (cond1 == cond2);
11941 gcc_assert (cond1 == cond2);
11945 gcc_assert (cond1 == cond2);
11949 gcc_assert (cond1 == cond2);
11950 return CC_DLEUmode;
11953 gcc_assert (cond1 == cond2);
11954 return CC_DGEUmode;
11957 gcc_unreachable ();
11962 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
11964 /* All floating point compares return CCFP if it is an equality
11965 comparison, and CCFPE otherwise. */
11966 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11989 gcc_unreachable ();
11993 /* A compare with a shifted operand. Because of canonicalization, the
11994 comparison will have to be swapped when we emit the assembler. */
11995 if (GET_MODE (y) == SImode
11996 && (REG_P (y) || (GET_CODE (y) == SUBREG))
11997 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
11998 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
11999 || GET_CODE (x) == ROTATERT))
12002 /* This operation is performed swapped, but since we only rely on the Z
12003 flag we don't need an additional mode. */
12004 if (GET_MODE (y) == SImode
12005 && (REG_P (y) || (GET_CODE (y) == SUBREG))
12006 && GET_CODE (x) == NEG
12007 && (op == EQ || op == NE))
12010 /* This is a special case that is used by combine to allow a
12011 comparison of a shifted byte load to be split into a zero-extend
12012 followed by a comparison of the shifted integer (only valid for
12013 equalities and unsigned inequalities). */
12014 if (GET_MODE (x) == SImode
12015 && GET_CODE (x) == ASHIFT
12016 && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 24
12017 && GET_CODE (XEXP (x, 0)) == SUBREG
12018 && MEM_P (SUBREG_REG (XEXP (x, 0)))
12019 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
12020 && (op == EQ || op == NE
12021 || op == GEU || op == GTU || op == LTU || op == LEU)
12022 && CONST_INT_P (y))
12025 /* A construct for a conditional compare, if the false arm contains
12026 0, then both conditions must be true, otherwise either condition
12027 must be true. Not all conditions are possible, so CCmode is
12028 returned if it can't be done. */
12029 if (GET_CODE (x) == IF_THEN_ELSE
12030 && (XEXP (x, 2) == const0_rtx
12031 || XEXP (x, 2) == const1_rtx)
12032 && COMPARISON_P (XEXP (x, 0))
12033 && COMPARISON_P (XEXP (x, 1)))
12034 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
12035 INTVAL (XEXP (x, 2)));
12037 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
12038 if (GET_CODE (x) == AND
12039 && (op == EQ || op == NE)
12040 && COMPARISON_P (XEXP (x, 0))
12041 && COMPARISON_P (XEXP (x, 1)))
12042 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
12045 if (GET_CODE (x) == IOR
12046 && (op == EQ || op == NE)
12047 && COMPARISON_P (XEXP (x, 0))
12048 && COMPARISON_P (XEXP (x, 1)))
12049 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
12052 /* An operation (on Thumb) where we want to test for a single bit.
12053 This is done by shifting that bit up into the top bit of a
12054 scratch register; we can then branch on the sign bit. */
12056 && GET_MODE (x) == SImode
12057 && (op == EQ || op == NE)
12058 && GET_CODE (x) == ZERO_EXTRACT
12059 && XEXP (x, 1) == const1_rtx)
12062 /* An operation that sets the condition codes as a side-effect, the
12063 V flag is not set correctly, so we can only use comparisons where
12064 this doesn't matter. (For LT and GE we can use "mi" and "pl"
12066 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
12067 if (GET_MODE (x) == SImode
12069 && (op == EQ || op == NE || op == LT || op == GE)
12070 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
12071 || GET_CODE (x) == AND || GET_CODE (x) == IOR
12072 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
12073 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
12074 || GET_CODE (x) == LSHIFTRT
12075 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
12076 || GET_CODE (x) == ROTATERT
12077 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
12078 return CC_NOOVmode;
12080 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
12083 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
12084 && GET_CODE (x) == PLUS
12085 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
12088 if (GET_MODE (x) == DImode || GET_MODE (y) == DImode)
12094 /* A DImode comparison against zero can be implemented by
12095 or'ing the two halves together. */
12096 if (y == const0_rtx)
12099 /* We can do an equality test in three Thumb instructions. */
12109 /* DImode unsigned comparisons can be implemented by cmp +
12110 cmpeq without a scratch register. Not worth doing in
12121 /* DImode signed and unsigned comparisons can be implemented
12122 by cmp + sbcs with a scratch register, but that does not
12123 set the Z flag - we must reverse GT/LE/GTU/LEU. */
12124 gcc_assert (op != EQ && op != NE);
12128 gcc_unreachable ();
12132 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
12133 return GET_MODE (x);
12138 /* X and Y are two things to compare using CODE. Emit the compare insn and
12139 return the rtx for register 0 in the proper mode. FP means this is a
12140 floating point compare: I don't think that it is needed on the arm. */
12142 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y, rtx scratch)
12144 enum machine_mode mode;
12146 int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode;
12148 /* We might have X as a constant, Y as a register because of the predicates
12149 used for cmpdi. If so, force X to a register here. */
12150 if (dimode_comparison && !REG_P (x))
12151 x = force_reg (DImode, x);
12153 mode = SELECT_CC_MODE (code, x, y);
12154 cc_reg = gen_rtx_REG (mode, CC_REGNUM);
12156 if (dimode_comparison
12157 && mode != CC_CZmode)
12161 /* To compare two non-zero values for equality, XOR them and
12162 then compare against zero. Not used for ARM mode; there
12163 CC_CZmode is cheaper. */
12164 if (mode == CC_Zmode && y != const0_rtx)
12166 gcc_assert (!reload_completed);
12167 x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN);
12171 /* A scratch register is required. */
12172 if (reload_completed)
12173 gcc_assert (scratch != NULL && GET_MODE (scratch) == SImode);
12175 scratch = gen_rtx_SCRATCH (SImode);
12177 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
12178 set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y));
12179 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
12182 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
12187 /* Generate a sequence of insns that will generate the correct return
12188 address mask depending on the physical architecture that the program
12191 arm_gen_return_addr_mask (void)
12193 rtx reg = gen_reg_rtx (Pmode);
12195 emit_insn (gen_return_addr_mask (reg));
12200 arm_reload_in_hi (rtx *operands)
12202 rtx ref = operands[1];
12204 HOST_WIDE_INT offset = 0;
12206 if (GET_CODE (ref) == SUBREG)
12208 offset = SUBREG_BYTE (ref);
12209 ref = SUBREG_REG (ref);
12214 /* We have a pseudo which has been spilt onto the stack; there
12215 are two cases here: the first where there is a simple
12216 stack-slot replacement and a second where the stack-slot is
12217 out of range, or is used as a subreg. */
12218 if (reg_equiv_mem (REGNO (ref)))
12220 ref = reg_equiv_mem (REGNO (ref));
12221 base = find_replacement (&XEXP (ref, 0));
12224 /* The slot is out of range, or was dressed up in a SUBREG. */
12225 base = reg_equiv_address (REGNO (ref));
12228 base = find_replacement (&XEXP (ref, 0));
12230 /* Handle the case where the address is too complex to be offset by 1. */
12231 if (GET_CODE (base) == MINUS
12232 || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1))))
12234 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
12236 emit_set_insn (base_plus, base);
12239 else if (GET_CODE (base) == PLUS)
12241 /* The addend must be CONST_INT, or we would have dealt with it above. */
12242 HOST_WIDE_INT hi, lo;
12244 offset += INTVAL (XEXP (base, 1));
12245 base = XEXP (base, 0);
12247 /* Rework the address into a legal sequence of insns. */
12248 /* Valid range for lo is -4095 -> 4095 */
12251 : -((-offset) & 0xfff));
12253 /* Corner case, if lo is the max offset then we would be out of range
12254 once we have added the additional 1 below, so bump the msb into the
12255 pre-loading insn(s). */
12259 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
12260 ^ (HOST_WIDE_INT) 0x80000000)
12261 - (HOST_WIDE_INT) 0x80000000);
12263 gcc_assert (hi + lo == offset);
12267 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
12269 /* Get the base address; addsi3 knows how to handle constants
12270 that require more than one insn. */
12271 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
12277 /* Operands[2] may overlap operands[0] (though it won't overlap
12278 operands[1]), that's why we asked for a DImode reg -- so we can
12279 use the bit that does not overlap. */
12280 if (REGNO (operands[2]) == REGNO (operands[0]))
12281 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
12283 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
12285 emit_insn (gen_zero_extendqisi2 (scratch,
12286 gen_rtx_MEM (QImode,
12287 plus_constant (Pmode, base,
12289 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
12290 gen_rtx_MEM (QImode,
12291 plus_constant (Pmode, base,
12293 if (!BYTES_BIG_ENDIAN)
12294 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
12295 gen_rtx_IOR (SImode,
12298 gen_rtx_SUBREG (SImode, operands[0], 0),
12302 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
12303 gen_rtx_IOR (SImode,
12304 gen_rtx_ASHIFT (SImode, scratch,
12306 gen_rtx_SUBREG (SImode, operands[0], 0)));
12309 /* Handle storing a half-word to memory during reload by synthesizing as two
12310 byte stores. Take care not to clobber the input values until after we
12311 have moved them somewhere safe. This code assumes that if the DImode
12312 scratch in operands[2] overlaps either the input value or output address
12313 in some way, then that value must die in this insn (we absolutely need
12314 two scratch registers for some corner cases). */
12316 arm_reload_out_hi (rtx *operands)
12318 rtx ref = operands[0];
12319 rtx outval = operands[1];
12321 HOST_WIDE_INT offset = 0;
12323 if (GET_CODE (ref) == SUBREG)
12325 offset = SUBREG_BYTE (ref);
12326 ref = SUBREG_REG (ref);
12331 /* We have a pseudo which has been spilt onto the stack; there
12332 are two cases here: the first where there is a simple
12333 stack-slot replacement and a second where the stack-slot is
12334 out of range, or is used as a subreg. */
12335 if (reg_equiv_mem (REGNO (ref)))
12337 ref = reg_equiv_mem (REGNO (ref));
12338 base = find_replacement (&XEXP (ref, 0));
12341 /* The slot is out of range, or was dressed up in a SUBREG. */
12342 base = reg_equiv_address (REGNO (ref));
12345 base = find_replacement (&XEXP (ref, 0));
12347 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
12349 /* Handle the case where the address is too complex to be offset by 1. */
12350 if (GET_CODE (base) == MINUS
12351 || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1))))
12353 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
12355 /* Be careful not to destroy OUTVAL. */
12356 if (reg_overlap_mentioned_p (base_plus, outval))
12358 /* Updating base_plus might destroy outval, see if we can
12359 swap the scratch and base_plus. */
12360 if (!reg_overlap_mentioned_p (scratch, outval))
12363 scratch = base_plus;
12368 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
12370 /* Be conservative and copy OUTVAL into the scratch now,
12371 this should only be necessary if outval is a subreg
12372 of something larger than a word. */
12373 /* XXX Might this clobber base? I can't see how it can,
12374 since scratch is known to overlap with OUTVAL, and
12375 must be wider than a word. */
12376 emit_insn (gen_movhi (scratch_hi, outval));
12377 outval = scratch_hi;
12381 emit_set_insn (base_plus, base);
12384 else if (GET_CODE (base) == PLUS)
12386 /* The addend must be CONST_INT, or we would have dealt with it above. */
12387 HOST_WIDE_INT hi, lo;
12389 offset += INTVAL (XEXP (base, 1));
12390 base = XEXP (base, 0);
12392 /* Rework the address into a legal sequence of insns. */
12393 /* Valid range for lo is -4095 -> 4095 */
12396 : -((-offset) & 0xfff));
12398 /* Corner case, if lo is the max offset then we would be out of range
12399 once we have added the additional 1 below, so bump the msb into the
12400 pre-loading insn(s). */
12404 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
12405 ^ (HOST_WIDE_INT) 0x80000000)
12406 - (HOST_WIDE_INT) 0x80000000);
12408 gcc_assert (hi + lo == offset);
12412 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
12414 /* Be careful not to destroy OUTVAL. */
12415 if (reg_overlap_mentioned_p (base_plus, outval))
12417 /* Updating base_plus might destroy outval, see if we
12418 can swap the scratch and base_plus. */
12419 if (!reg_overlap_mentioned_p (scratch, outval))
12422 scratch = base_plus;
12427 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
12429 /* Be conservative and copy outval into scratch now,
12430 this should only be necessary if outval is a
12431 subreg of something larger than a word. */
12432 /* XXX Might this clobber base? I can't see how it
12433 can, since scratch is known to overlap with
12435 emit_insn (gen_movhi (scratch_hi, outval));
12436 outval = scratch_hi;
12440 /* Get the base address; addsi3 knows how to handle constants
12441 that require more than one insn. */
12442 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
12448 if (BYTES_BIG_ENDIAN)
12450 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
12451 plus_constant (Pmode, base,
12453 gen_lowpart (QImode, outval)));
12454 emit_insn (gen_lshrsi3 (scratch,
12455 gen_rtx_SUBREG (SImode, outval, 0),
12457 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (Pmode, base,
12459 gen_lowpart (QImode, scratch)));
12463 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (Pmode, base,
12465 gen_lowpart (QImode, outval)));
12466 emit_insn (gen_lshrsi3 (scratch,
12467 gen_rtx_SUBREG (SImode, outval, 0),
12469 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
12470 plus_constant (Pmode, base,
12472 gen_lowpart (QImode, scratch)));
12476 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
12477 (padded to the size of a word) should be passed in a register. */
12480 arm_must_pass_in_stack (enum machine_mode mode, const_tree type)
12482 if (TARGET_AAPCS_BASED)
12483 return must_pass_in_stack_var_size (mode, type);
12485 return must_pass_in_stack_var_size_or_pad (mode, type);
12489 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
12490 Return true if an argument passed on the stack should be padded upwards,
12491 i.e. if the least-significant byte has useful data.
12492 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
12493 aggregate types are placed in the lowest memory address. */
12496 arm_pad_arg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, const_tree type)
12498 if (!TARGET_AAPCS_BASED)
12499 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
12501 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
12508 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
12509 Return !BYTES_BIG_ENDIAN if the least significant byte of the
12510 register has useful data, and return the opposite if the most
12511 significant byte does. */
12514 arm_pad_reg_upward (enum machine_mode mode,
12515 tree type, int first ATTRIBUTE_UNUSED)
12517 if (TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN)
12519 /* For AAPCS, small aggregates, small fixed-point types,
12520 and small complex types are always padded upwards. */
12523 if ((AGGREGATE_TYPE_P (type)
12524 || TREE_CODE (type) == COMPLEX_TYPE
12525 || FIXED_POINT_TYPE_P (type))
12526 && int_size_in_bytes (type) <= 4)
12531 if ((COMPLEX_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))
12532 && GET_MODE_SIZE (mode) <= 4)
12537 /* Otherwise, use default padding. */
12538 return !BYTES_BIG_ENDIAN;
12541 /* Returns true iff OFFSET is valid for use in an LDRD/STRD instruction,
12542 assuming that the address in the base register is word aligned. */
12544 offset_ok_for_ldrd_strd (HOST_WIDE_INT offset)
12546 HOST_WIDE_INT max_offset;
12548 /* Offset must be a multiple of 4 in Thumb mode. */
12549 if (TARGET_THUMB2 && ((offset & 3) != 0))
12554 else if (TARGET_ARM)
12559 return ((offset <= max_offset) && (offset >= -max_offset));
12562 /* Checks whether the operands are valid for use in an LDRD/STRD instruction.
12563 Assumes that RT, RT2, and RN are REG. This is guaranteed by the patterns.
12564 Assumes that the address in the base register RN is word aligned. Pattern
12565 guarantees that both memory accesses use the same base register,
12566 the offsets are constants within the range, and the gap between the offsets is 4.
12567 If preload complete then check that registers are legal. WBACK indicates whether
12568 address is updated. LOAD indicates whether memory access is load or store. */
12570 operands_ok_ldrd_strd (rtx rt, rtx rt2, rtx rn, HOST_WIDE_INT offset,
12571 bool wback, bool load)
12573 unsigned int t, t2, n;
12575 if (!reload_completed)
12578 if (!offset_ok_for_ldrd_strd (offset))
12585 if ((TARGET_THUMB2)
12586 && ((wback && (n == t || n == t2))
12587 || (t == SP_REGNUM)
12588 || (t == PC_REGNUM)
12589 || (t2 == SP_REGNUM)
12590 || (t2 == PC_REGNUM)
12591 || (!load && (n == PC_REGNUM))
12592 || (load && (t == t2))
12593 /* Triggers Cortex-M3 LDRD errata. */
12594 || (!wback && load && fix_cm3_ldrd && (n == t))))
12598 && ((wback && (n == t || n == t2))
12599 || (t2 == PC_REGNUM)
12600 || (t % 2 != 0) /* First destination register is not even. */
12602 /* PC can be used as base register (for offset addressing only),
12603 but it is depricated. */
12604 || (n == PC_REGNUM)))
12611 /* Print a symbolic form of X to the debug file, F. */
12613 arm_print_value (FILE *f, rtx x)
12615 switch (GET_CODE (x))
12618 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
12622 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
12630 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
12632 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
12633 if (i < (CONST_VECTOR_NUNITS (x) - 1))
12641 fprintf (f, "\"%s\"", XSTR (x, 0));
12645 fprintf (f, "`%s'", XSTR (x, 0));
12649 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
12653 arm_print_value (f, XEXP (x, 0));
12657 arm_print_value (f, XEXP (x, 0));
12659 arm_print_value (f, XEXP (x, 1));
12667 fprintf (f, "????");
12672 /* Routines for manipulation of the constant pool. */
12674 /* Arm instructions cannot load a large constant directly into a
12675 register; they have to come from a pc relative load. The constant
12676 must therefore be placed in the addressable range of the pc
12677 relative load. Depending on the precise pc relative load
12678 instruction the range is somewhere between 256 bytes and 4k. This
12679 means that we often have to dump a constant inside a function, and
12680 generate code to branch around it.
12682 It is important to minimize this, since the branches will slow
12683 things down and make the code larger.
12685 Normally we can hide the table after an existing unconditional
12686 branch so that there is no interruption of the flow, but in the
12687 worst case the code looks like this:
12705 We fix this by performing a scan after scheduling, which notices
12706 which instructions need to have their operands fetched from the
12707 constant table and builds the table.
12709 The algorithm starts by building a table of all the constants that
12710 need fixing up and all the natural barriers in the function (places
12711 where a constant table can be dropped without breaking the flow).
12712 For each fixup we note how far the pc-relative replacement will be
12713 able to reach and the offset of the instruction into the function.
12715 Having built the table we then group the fixes together to form
12716 tables that are as large as possible (subject to addressing
12717 constraints) and emit each table of constants after the last
12718 barrier that is within range of all the instructions in the group.
12719 If a group does not contain a barrier, then we forcibly create one
12720 by inserting a jump instruction into the flow. Once the table has
12721 been inserted, the insns are then modified to reference the
12722 relevant entry in the pool.
12724 Possible enhancements to the algorithm (not implemented) are:
12726 1) For some processors and object formats, there may be benefit in
12727 aligning the pools to the start of cache lines; this alignment
12728 would need to be taken into account when calculating addressability
12731 /* These typedefs are located at the start of this file, so that
12732 they can be used in the prototypes there. This comment is to
12733 remind readers of that fact so that the following structures
12734 can be understood more easily.
12736 typedef struct minipool_node Mnode;
12737 typedef struct minipool_fixup Mfix; */
12739 struct minipool_node
12741 /* Doubly linked chain of entries. */
12744 /* The maximum offset into the code that this entry can be placed. While
12745 pushing fixes for forward references, all entries are sorted in order
12746 of increasing max_address. */
12747 HOST_WIDE_INT max_address;
12748 /* Similarly for an entry inserted for a backwards ref. */
12749 HOST_WIDE_INT min_address;
12750 /* The number of fixes referencing this entry. This can become zero
12751 if we "unpush" an entry. In this case we ignore the entry when we
12752 come to emit the code. */
12754 /* The offset from the start of the minipool. */
12755 HOST_WIDE_INT offset;
12756 /* The value in table. */
12758 /* The mode of value. */
12759 enum machine_mode mode;
12760 /* The size of the value. With iWMMXt enabled
12761 sizes > 4 also imply an alignment of 8-bytes. */
12765 struct minipool_fixup
12769 HOST_WIDE_INT address;
12771 enum machine_mode mode;
12775 HOST_WIDE_INT forwards;
12776 HOST_WIDE_INT backwards;
12779 /* Fixes less than a word need padding out to a word boundary. */
12780 #define MINIPOOL_FIX_SIZE(mode) \
12781 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
12783 static Mnode * minipool_vector_head;
12784 static Mnode * minipool_vector_tail;
12785 static rtx minipool_vector_label;
12786 static int minipool_pad;
12788 /* The linked list of all minipool fixes required for this function. */
12789 Mfix * minipool_fix_head;
12790 Mfix * minipool_fix_tail;
12791 /* The fix entry for the current minipool, once it has been placed. */
12792 Mfix * minipool_barrier;
12794 /* Determines if INSN is the start of a jump table. Returns the end
12795 of the TABLE or NULL_RTX. */
12797 is_jump_table (rtx insn)
12801 if (jump_to_label_p (insn)
12802 && ((table = next_real_insn (JUMP_LABEL (insn)))
12803 == next_real_insn (insn))
12806 && (GET_CODE (PATTERN (table)) == ADDR_VEC
12807 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
12813 #ifndef JUMP_TABLES_IN_TEXT_SECTION
12814 #define JUMP_TABLES_IN_TEXT_SECTION 0
12817 static HOST_WIDE_INT
12818 get_jump_table_size (rtx insn)
12820 /* ADDR_VECs only take room if read-only data does into the text
12822 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
12824 rtx body = PATTERN (insn);
12825 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
12826 HOST_WIDE_INT size;
12827 HOST_WIDE_INT modesize;
12829 modesize = GET_MODE_SIZE (GET_MODE (body));
12830 size = modesize * XVECLEN (body, elt);
12834 /* Round up size of TBB table to a halfword boundary. */
12835 size = (size + 1) & ~(HOST_WIDE_INT)1;
12838 /* No padding necessary for TBH. */
12841 /* Add two bytes for alignment on Thumb. */
12846 gcc_unreachable ();
12854 /* Return the maximum amount of padding that will be inserted before
12857 static HOST_WIDE_INT
12858 get_label_padding (rtx label)
12860 HOST_WIDE_INT align, min_insn_size;
12862 align = 1 << label_to_alignment (label);
12863 min_insn_size = TARGET_THUMB ? 2 : 4;
12864 return align > min_insn_size ? align - min_insn_size : 0;
12867 /* Move a minipool fix MP from its current location to before MAX_MP.
12868 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
12869 constraints may need updating. */
12871 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
12872 HOST_WIDE_INT max_address)
12874 /* The code below assumes these are different. */
12875 gcc_assert (mp != max_mp);
12877 if (max_mp == NULL)
12879 if (max_address < mp->max_address)
12880 mp->max_address = max_address;
12884 if (max_address > max_mp->max_address - mp->fix_size)
12885 mp->max_address = max_mp->max_address - mp->fix_size;
12887 mp->max_address = max_address;
12889 /* Unlink MP from its current position. Since max_mp is non-null,
12890 mp->prev must be non-null. */
12891 mp->prev->next = mp->next;
12892 if (mp->next != NULL)
12893 mp->next->prev = mp->prev;
12895 minipool_vector_tail = mp->prev;
12897 /* Re-insert it before MAX_MP. */
12899 mp->prev = max_mp->prev;
12902 if (mp->prev != NULL)
12903 mp->prev->next = mp;
12905 minipool_vector_head = mp;
12908 /* Save the new entry. */
12911 /* Scan over the preceding entries and adjust their addresses as
12913 while (mp->prev != NULL
12914 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
12916 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
12923 /* Add a constant to the minipool for a forward reference. Returns the
12924 node added or NULL if the constant will not fit in this pool. */
12926 add_minipool_forward_ref (Mfix *fix)
12928 /* If set, max_mp is the first pool_entry that has a lower
12929 constraint than the one we are trying to add. */
12930 Mnode * max_mp = NULL;
12931 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
12934 /* If the minipool starts before the end of FIX->INSN then this FIX
12935 can not be placed into the current pool. Furthermore, adding the
12936 new constant pool entry may cause the pool to start FIX_SIZE bytes
12938 if (minipool_vector_head &&
12939 (fix->address + get_attr_length (fix->insn)
12940 >= minipool_vector_head->max_address - fix->fix_size))
12943 /* Scan the pool to see if a constant with the same value has
12944 already been added. While we are doing this, also note the
12945 location where we must insert the constant if it doesn't already
12947 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
12949 if (GET_CODE (fix->value) == GET_CODE (mp->value)
12950 && fix->mode == mp->mode
12951 && (!LABEL_P (fix->value)
12952 || (CODE_LABEL_NUMBER (fix->value)
12953 == CODE_LABEL_NUMBER (mp->value)))
12954 && rtx_equal_p (fix->value, mp->value))
12956 /* More than one fix references this entry. */
12958 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
12961 /* Note the insertion point if necessary. */
12963 && mp->max_address > max_address)
12966 /* If we are inserting an 8-bytes aligned quantity and
12967 we have not already found an insertion point, then
12968 make sure that all such 8-byte aligned quantities are
12969 placed at the start of the pool. */
12970 if (ARM_DOUBLEWORD_ALIGN
12972 && fix->fix_size >= 8
12973 && mp->fix_size < 8)
12976 max_address = mp->max_address;
12980 /* The value is not currently in the minipool, so we need to create
12981 a new entry for it. If MAX_MP is NULL, the entry will be put on
12982 the end of the list since the placement is less constrained than
12983 any existing entry. Otherwise, we insert the new fix before
12984 MAX_MP and, if necessary, adjust the constraints on the other
12987 mp->fix_size = fix->fix_size;
12988 mp->mode = fix->mode;
12989 mp->value = fix->value;
12991 /* Not yet required for a backwards ref. */
12992 mp->min_address = -65536;
12994 if (max_mp == NULL)
12996 mp->max_address = max_address;
12998 mp->prev = minipool_vector_tail;
13000 if (mp->prev == NULL)
13002 minipool_vector_head = mp;
13003 minipool_vector_label = gen_label_rtx ();
13006 mp->prev->next = mp;
13008 minipool_vector_tail = mp;
13012 if (max_address > max_mp->max_address - mp->fix_size)
13013 mp->max_address = max_mp->max_address - mp->fix_size;
13015 mp->max_address = max_address;
13018 mp->prev = max_mp->prev;
13020 if (mp->prev != NULL)
13021 mp->prev->next = mp;
13023 minipool_vector_head = mp;
13026 /* Save the new entry. */
13029 /* Scan over the preceding entries and adjust their addresses as
13031 while (mp->prev != NULL
13032 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
13034 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
13042 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
13043 HOST_WIDE_INT min_address)
13045 HOST_WIDE_INT offset;
13047 /* The code below assumes these are different. */
13048 gcc_assert (mp != min_mp);
13050 if (min_mp == NULL)
13052 if (min_address > mp->min_address)
13053 mp->min_address = min_address;
13057 /* We will adjust this below if it is too loose. */
13058 mp->min_address = min_address;
13060 /* Unlink MP from its current position. Since min_mp is non-null,
13061 mp->next must be non-null. */
13062 mp->next->prev = mp->prev;
13063 if (mp->prev != NULL)
13064 mp->prev->next = mp->next;
13066 minipool_vector_head = mp->next;
13068 /* Reinsert it after MIN_MP. */
13070 mp->next = min_mp->next;
13072 if (mp->next != NULL)
13073 mp->next->prev = mp;
13075 minipool_vector_tail = mp;
13081 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
13083 mp->offset = offset;
13084 if (mp->refcount > 0)
13085 offset += mp->fix_size;
13087 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
13088 mp->next->min_address = mp->min_address + mp->fix_size;
13094 /* Add a constant to the minipool for a backward reference. Returns the
13095 node added or NULL if the constant will not fit in this pool.
13097 Note that the code for insertion for a backwards reference can be
13098 somewhat confusing because the calculated offsets for each fix do
13099 not take into account the size of the pool (which is still under
13102 add_minipool_backward_ref (Mfix *fix)
13104 /* If set, min_mp is the last pool_entry that has a lower constraint
13105 than the one we are trying to add. */
13106 Mnode *min_mp = NULL;
13107 /* This can be negative, since it is only a constraint. */
13108 HOST_WIDE_INT min_address = fix->address - fix->backwards;
13111 /* If we can't reach the current pool from this insn, or if we can't
13112 insert this entry at the end of the pool without pushing other
13113 fixes out of range, then we don't try. This ensures that we
13114 can't fail later on. */
13115 if (min_address >= minipool_barrier->address
13116 || (minipool_vector_tail->min_address + fix->fix_size
13117 >= minipool_barrier->address))
13120 /* Scan the pool to see if a constant with the same value has
13121 already been added. While we are doing this, also note the
13122 location where we must insert the constant if it doesn't already
13124 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
13126 if (GET_CODE (fix->value) == GET_CODE (mp->value)
13127 && fix->mode == mp->mode
13128 && (!LABEL_P (fix->value)
13129 || (CODE_LABEL_NUMBER (fix->value)
13130 == CODE_LABEL_NUMBER (mp->value)))
13131 && rtx_equal_p (fix->value, mp->value)
13132 /* Check that there is enough slack to move this entry to the
13133 end of the table (this is conservative). */
13134 && (mp->max_address
13135 > (minipool_barrier->address
13136 + minipool_vector_tail->offset
13137 + minipool_vector_tail->fix_size)))
13140 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
13143 if (min_mp != NULL)
13144 mp->min_address += fix->fix_size;
13147 /* Note the insertion point if necessary. */
13148 if (mp->min_address < min_address)
13150 /* For now, we do not allow the insertion of 8-byte alignment
13151 requiring nodes anywhere but at the start of the pool. */
13152 if (ARM_DOUBLEWORD_ALIGN
13153 && fix->fix_size >= 8 && mp->fix_size < 8)
13158 else if (mp->max_address
13159 < minipool_barrier->address + mp->offset + fix->fix_size)
13161 /* Inserting before this entry would push the fix beyond
13162 its maximum address (which can happen if we have
13163 re-located a forwards fix); force the new fix to come
13165 if (ARM_DOUBLEWORD_ALIGN
13166 && fix->fix_size >= 8 && mp->fix_size < 8)
13171 min_address = mp->min_address + fix->fix_size;
13174 /* Do not insert a non-8-byte aligned quantity before 8-byte
13175 aligned quantities. */
13176 else if (ARM_DOUBLEWORD_ALIGN
13177 && fix->fix_size < 8
13178 && mp->fix_size >= 8)
13181 min_address = mp->min_address + fix->fix_size;
13186 /* We need to create a new entry. */
13188 mp->fix_size = fix->fix_size;
13189 mp->mode = fix->mode;
13190 mp->value = fix->value;
13192 mp->max_address = minipool_barrier->address + 65536;
13194 mp->min_address = min_address;
13196 if (min_mp == NULL)
13199 mp->next = minipool_vector_head;
13201 if (mp->next == NULL)
13203 minipool_vector_tail = mp;
13204 minipool_vector_label = gen_label_rtx ();
13207 mp->next->prev = mp;
13209 minipool_vector_head = mp;
13213 mp->next = min_mp->next;
13217 if (mp->next != NULL)
13218 mp->next->prev = mp;
13220 minipool_vector_tail = mp;
13223 /* Save the new entry. */
13231 /* Scan over the following entries and adjust their offsets. */
13232 while (mp->next != NULL)
13234 if (mp->next->min_address < mp->min_address + mp->fix_size)
13235 mp->next->min_address = mp->min_address + mp->fix_size;
13238 mp->next->offset = mp->offset + mp->fix_size;
13240 mp->next->offset = mp->offset;
13249 assign_minipool_offsets (Mfix *barrier)
13251 HOST_WIDE_INT offset = 0;
13254 minipool_barrier = barrier;
13256 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
13258 mp->offset = offset;
13260 if (mp->refcount > 0)
13261 offset += mp->fix_size;
13265 /* Output the literal table */
13267 dump_minipool (rtx scan)
13273 if (ARM_DOUBLEWORD_ALIGN)
13274 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
13275 if (mp->refcount > 0 && mp->fix_size >= 8)
13282 fprintf (dump_file,
13283 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
13284 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
13286 scan = emit_label_after (gen_label_rtx (), scan);
13287 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
13288 scan = emit_label_after (minipool_vector_label, scan);
13290 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
13292 if (mp->refcount > 0)
13296 fprintf (dump_file,
13297 ";; Offset %u, min %ld, max %ld ",
13298 (unsigned) mp->offset, (unsigned long) mp->min_address,
13299 (unsigned long) mp->max_address);
13300 arm_print_value (dump_file, mp->value);
13301 fputc ('\n', dump_file);
13304 switch (mp->fix_size)
13306 #ifdef HAVE_consttable_1
13308 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
13312 #ifdef HAVE_consttable_2
13314 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
13318 #ifdef HAVE_consttable_4
13320 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
13324 #ifdef HAVE_consttable_8
13326 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
13330 #ifdef HAVE_consttable_16
13332 scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
13337 gcc_unreachable ();
13345 minipool_vector_head = minipool_vector_tail = NULL;
13346 scan = emit_insn_after (gen_consttable_end (), scan);
13347 scan = emit_barrier_after (scan);
13350 /* Return the cost of forcibly inserting a barrier after INSN. */
13352 arm_barrier_cost (rtx insn)
13354 /* Basing the location of the pool on the loop depth is preferable,
13355 but at the moment, the basic block information seems to be
13356 corrupt by this stage of the compilation. */
13357 int base_cost = 50;
13358 rtx next = next_nonnote_insn (insn);
13360 if (next != NULL && LABEL_P (next))
13363 switch (GET_CODE (insn))
13366 /* It will always be better to place the table before the label, rather
13375 return base_cost - 10;
13378 return base_cost + 10;
13382 /* Find the best place in the insn stream in the range
13383 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
13384 Create the barrier by inserting a jump and add a new fix entry for
13387 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
13389 HOST_WIDE_INT count = 0;
13391 rtx from = fix->insn;
13392 /* The instruction after which we will insert the jump. */
13393 rtx selected = NULL;
13395 /* The address at which the jump instruction will be placed. */
13396 HOST_WIDE_INT selected_address;
13398 HOST_WIDE_INT max_count = max_address - fix->address;
13399 rtx label = gen_label_rtx ();
13401 selected_cost = arm_barrier_cost (from);
13402 selected_address = fix->address;
13404 while (from && count < max_count)
13409 /* This code shouldn't have been called if there was a natural barrier
13411 gcc_assert (!BARRIER_P (from));
13413 /* Count the length of this insn. This must stay in sync with the
13414 code that pushes minipool fixes. */
13415 if (LABEL_P (from))
13416 count += get_label_padding (from);
13418 count += get_attr_length (from);
13420 /* If there is a jump table, add its length. */
13421 tmp = is_jump_table (from);
13424 count += get_jump_table_size (tmp);
13426 /* Jump tables aren't in a basic block, so base the cost on
13427 the dispatch insn. If we select this location, we will
13428 still put the pool after the table. */
13429 new_cost = arm_barrier_cost (from);
13431 if (count < max_count
13432 && (!selected || new_cost <= selected_cost))
13435 selected_cost = new_cost;
13436 selected_address = fix->address + count;
13439 /* Continue after the dispatch table. */
13440 from = NEXT_INSN (tmp);
13444 new_cost = arm_barrier_cost (from);
13446 if (count < max_count
13447 && (!selected || new_cost <= selected_cost))
13450 selected_cost = new_cost;
13451 selected_address = fix->address + count;
13454 from = NEXT_INSN (from);
13457 /* Make sure that we found a place to insert the jump. */
13458 gcc_assert (selected);
13460 /* Make sure we do not split a call and its corresponding
13461 CALL_ARG_LOCATION note. */
13462 if (CALL_P (selected))
13464 rtx next = NEXT_INSN (selected);
13465 if (next && NOTE_P (next)
13466 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
13470 /* Create a new JUMP_INSN that branches around a barrier. */
13471 from = emit_jump_insn_after (gen_jump (label), selected);
13472 JUMP_LABEL (from) = label;
13473 barrier = emit_barrier_after (from);
13474 emit_label_after (label, barrier);
13476 /* Create a minipool barrier entry for the new barrier. */
13477 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
13478 new_fix->insn = barrier;
13479 new_fix->address = selected_address;
13480 new_fix->next = fix->next;
13481 fix->next = new_fix;
13486 /* Record that there is a natural barrier in the insn stream at
13489 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
13491 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
13494 fix->address = address;
13497 if (minipool_fix_head != NULL)
13498 minipool_fix_tail->next = fix;
13500 minipool_fix_head = fix;
13502 minipool_fix_tail = fix;
13505 /* Record INSN, which will need fixing up to load a value from the
13506 minipool. ADDRESS is the offset of the insn since the start of the
13507 function; LOC is a pointer to the part of the insn which requires
13508 fixing; VALUE is the constant that must be loaded, which is of type
13511 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
13512 enum machine_mode mode, rtx value)
13514 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
13517 fix->address = address;
13520 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
13521 fix->value = value;
13522 fix->forwards = get_attr_pool_range (insn);
13523 fix->backwards = get_attr_neg_pool_range (insn);
13524 fix->minipool = NULL;
13526 /* If an insn doesn't have a range defined for it, then it isn't
13527 expecting to be reworked by this code. Better to stop now than
13528 to generate duff assembly code. */
13529 gcc_assert (fix->forwards || fix->backwards);
13531 /* If an entry requires 8-byte alignment then assume all constant pools
13532 require 4 bytes of padding. Trying to do this later on a per-pool
13533 basis is awkward because existing pool entries have to be modified. */
13534 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8)
13539 fprintf (dump_file,
13540 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
13541 GET_MODE_NAME (mode),
13542 INSN_UID (insn), (unsigned long) address,
13543 -1 * (long)fix->backwards, (long)fix->forwards);
13544 arm_print_value (dump_file, fix->value);
13545 fprintf (dump_file, "\n");
13548 /* Add it to the chain of fixes. */
13551 if (minipool_fix_head != NULL)
13552 minipool_fix_tail->next = fix;
13554 minipool_fix_head = fix;
13556 minipool_fix_tail = fix;
13559 /* Return the cost of synthesizing a 64-bit constant VAL inline.
13560 Returns the number of insns needed, or 99 if we don't know how to
13563 arm_const_double_inline_cost (rtx val)
13565 rtx lowpart, highpart;
13566 enum machine_mode mode;
13568 mode = GET_MODE (val);
13570 if (mode == VOIDmode)
13573 gcc_assert (GET_MODE_SIZE (mode) == 8);
13575 lowpart = gen_lowpart (SImode, val);
13576 highpart = gen_highpart_mode (SImode, mode, val);
13578 gcc_assert (CONST_INT_P (lowpart));
13579 gcc_assert (CONST_INT_P (highpart));
13581 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
13582 NULL_RTX, NULL_RTX, 0, 0)
13583 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
13584 NULL_RTX, NULL_RTX, 0, 0));
13587 /* Return true if it is worthwhile to split a 64-bit constant into two
13588 32-bit operations. This is the case if optimizing for size, or
13589 if we have load delay slots, or if one 32-bit part can be done with
13590 a single data operation. */
13592 arm_const_double_by_parts (rtx val)
13594 enum machine_mode mode = GET_MODE (val);
13597 if (optimize_size || arm_ld_sched)
13600 if (mode == VOIDmode)
13603 part = gen_highpart_mode (SImode, mode, val);
13605 gcc_assert (CONST_INT_P (part));
13607 if (const_ok_for_arm (INTVAL (part))
13608 || const_ok_for_arm (~INTVAL (part)))
13611 part = gen_lowpart (SImode, val);
13613 gcc_assert (CONST_INT_P (part));
13615 if (const_ok_for_arm (INTVAL (part))
13616 || const_ok_for_arm (~INTVAL (part)))
13622 /* Return true if it is possible to inline both the high and low parts
13623 of a 64-bit constant into 32-bit data processing instructions. */
13625 arm_const_double_by_immediates (rtx val)
13627 enum machine_mode mode = GET_MODE (val);
13630 if (mode == VOIDmode)
13633 part = gen_highpart_mode (SImode, mode, val);
13635 gcc_assert (CONST_INT_P (part));
13637 if (!const_ok_for_arm (INTVAL (part)))
13640 part = gen_lowpart (SImode, val);
13642 gcc_assert (CONST_INT_P (part));
13644 if (!const_ok_for_arm (INTVAL (part)))
13650 /* Scan INSN and note any of its operands that need fixing.
13651 If DO_PUSHES is false we do not actually push any of the fixups
13654 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
13658 extract_insn (insn);
13660 if (!constrain_operands (1))
13661 fatal_insn_not_found (insn);
13663 if (recog_data.n_alternatives == 0)
13666 /* Fill in recog_op_alt with information about the constraints of
13668 preprocess_constraints ();
13670 for (opno = 0; opno < recog_data.n_operands; opno++)
13672 /* Things we need to fix can only occur in inputs. */
13673 if (recog_data.operand_type[opno] != OP_IN)
13676 /* If this alternative is a memory reference, then any mention
13677 of constants in this alternative is really to fool reload
13678 into allowing us to accept one there. We need to fix them up
13679 now so that we output the right code. */
13680 if (recog_op_alt[opno][which_alternative].memory_ok)
13682 rtx op = recog_data.operand[opno];
13684 if (CONSTANT_P (op))
13687 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
13688 recog_data.operand_mode[opno], op);
13690 else if (MEM_P (op)
13691 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
13692 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
13696 rtx cop = avoid_constant_pool_reference (op);
13698 /* Casting the address of something to a mode narrower
13699 than a word can cause avoid_constant_pool_reference()
13700 to return the pool reference itself. That's no good to
13701 us here. Lets just hope that we can use the
13702 constant pool value directly. */
13704 cop = get_pool_constant (XEXP (op, 0));
13706 push_minipool_fix (insn, address,
13707 recog_data.operand_loc[opno],
13708 recog_data.operand_mode[opno], cop);
13718 /* Rewrite move insn into subtract of 0 if the condition codes will
13719 be useful in next conditional jump insn. */
13722 thumb1_reorg (void)
13728 rtx set, dest, src;
13730 rtx prev, insn = BB_END (bb);
13732 while (insn != BB_HEAD (bb) && DEBUG_INSN_P (insn))
13733 insn = PREV_INSN (insn);
13735 /* Find the last cbranchsi4_insn in basic block BB. */
13736 if (INSN_CODE (insn) != CODE_FOR_cbranchsi4_insn)
13739 /* Find the first non-note insn before INSN in basic block BB. */
13740 gcc_assert (insn != BB_HEAD (bb));
13741 prev = PREV_INSN (insn);
13742 while (prev != BB_HEAD (bb) && (NOTE_P (prev) || DEBUG_INSN_P (prev)))
13743 prev = PREV_INSN (prev);
13745 set = single_set (prev);
13749 dest = SET_DEST (set);
13750 src = SET_SRC (set);
13751 if (!low_register_operand (dest, SImode)
13752 || !low_register_operand (src, SImode))
13755 pat = PATTERN (insn);
13756 op0 = XEXP (XEXP (SET_SRC (pat), 0), 0);
13757 /* Rewrite move into subtract of 0 if its operand is compared with ZERO
13758 in INSN. Don't need to check dest since cprop_hardreg pass propagates
13760 if (REGNO (op0) == REGNO (src))
13762 dest = copy_rtx (dest);
13763 src = copy_rtx (src);
13764 src = gen_rtx_MINUS (SImode, src, const0_rtx);
13765 PATTERN (prev) = gen_rtx_SET (VOIDmode, dest, src);
13766 INSN_CODE (prev) = -1;
13767 /* Set test register in INSN to dest. */
13768 XEXP (XEXP (SET_SRC (pat), 0), 0) = copy_rtx (dest);
13769 INSN_CODE (insn) = -1;
13774 /* Convert instructions to their cc-clobbering variant if possible, since
13775 that allows us to use smaller encodings. */
13778 thumb2_reorg (void)
13783 INIT_REG_SET (&live);
13785 /* We are freeing block_for_insn in the toplev to keep compatibility
13786 with old MDEP_REORGS that are not CFG based. Recompute it now. */
13787 compute_bb_for_insn ();
13794 COPY_REG_SET (&live, DF_LR_OUT (bb));
13795 df_simulate_initialize_backwards (bb, &live);
13796 FOR_BB_INSNS_REVERSE (bb, insn)
13798 if (NONJUMP_INSN_P (insn)
13799 && !REGNO_REG_SET_P (&live, CC_REGNUM)
13800 && GET_CODE (PATTERN (insn)) == SET)
13802 enum {SKIP, CONV, SWAP_CONV} action = SKIP;
13803 rtx pat = PATTERN (insn);
13804 rtx dst = XEXP (pat, 0);
13805 rtx src = XEXP (pat, 1);
13806 rtx op0 = NULL_RTX, op1 = NULL_RTX;
13808 if (!OBJECT_P (src))
13809 op0 = XEXP (src, 0);
13811 if (BINARY_P (src))
13812 op1 = XEXP (src, 1);
13814 if (low_register_operand (dst, SImode))
13816 switch (GET_CODE (src))
13819 /* Adding two registers and storing the result
13820 in the first source is already a 16-bit
13822 if (rtx_equal_p (dst, op0)
13823 && register_operand (op1, SImode))
13826 if (low_register_operand (op0, SImode))
13828 /* ADDS <Rd>,<Rn>,<Rm> */
13829 if (low_register_operand (op1, SImode))
13831 /* ADDS <Rdn>,#<imm8> */
13832 /* SUBS <Rdn>,#<imm8> */
13833 else if (rtx_equal_p (dst, op0)
13834 && CONST_INT_P (op1)
13835 && IN_RANGE (INTVAL (op1), -255, 255))
13837 /* ADDS <Rd>,<Rn>,#<imm3> */
13838 /* SUBS <Rd>,<Rn>,#<imm3> */
13839 else if (CONST_INT_P (op1)
13840 && IN_RANGE (INTVAL (op1), -7, 7))
13846 /* RSBS <Rd>,<Rn>,#0
13847 Not handled here: see NEG below. */
13848 /* SUBS <Rd>,<Rn>,#<imm3>
13850 Not handled here: see PLUS above. */
13851 /* SUBS <Rd>,<Rn>,<Rm> */
13852 if (low_register_operand (op0, SImode)
13853 && low_register_operand (op1, SImode))
13858 /* MULS <Rdm>,<Rn>,<Rdm>
13859 As an exception to the rule, this is only used
13860 when optimizing for size since MULS is slow on all
13861 known implementations. We do not even want to use
13862 MULS in cold code, if optimizing for speed, so we
13863 test the global flag here. */
13864 if (!optimize_size)
13866 /* else fall through. */
13870 /* ANDS <Rdn>,<Rm> */
13871 if (rtx_equal_p (dst, op0)
13872 && low_register_operand (op1, SImode))
13874 else if (rtx_equal_p (dst, op1)
13875 && low_register_operand (op0, SImode))
13876 action = SWAP_CONV;
13882 /* ASRS <Rdn>,<Rm> */
13883 /* LSRS <Rdn>,<Rm> */
13884 /* LSLS <Rdn>,<Rm> */
13885 if (rtx_equal_p (dst, op0)
13886 && low_register_operand (op1, SImode))
13888 /* ASRS <Rd>,<Rm>,#<imm5> */
13889 /* LSRS <Rd>,<Rm>,#<imm5> */
13890 /* LSLS <Rd>,<Rm>,#<imm5> */
13891 else if (low_register_operand (op0, SImode)
13892 && CONST_INT_P (op1)
13893 && IN_RANGE (INTVAL (op1), 0, 31))
13898 /* RORS <Rdn>,<Rm> */
13899 if (rtx_equal_p (dst, op0)
13900 && low_register_operand (op1, SImode))
13906 /* MVNS <Rd>,<Rm> */
13907 /* NEGS <Rd>,<Rm> (a.k.a RSBS) */
13908 if (low_register_operand (op0, SImode))
13913 /* MOVS <Rd>,#<imm8> */
13914 if (CONST_INT_P (src)
13915 && IN_RANGE (INTVAL (src), 0, 255))
13920 /* MOVS and MOV<c> with registers have different
13921 encodings, so are not relevant here. */
13929 if (action != SKIP)
13931 rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM);
13932 rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg);
13935 if (action == SWAP_CONV)
13937 src = copy_rtx (src);
13938 XEXP (src, 0) = op1;
13939 XEXP (src, 1) = op0;
13940 pat = gen_rtx_SET (VOIDmode, dst, src);
13941 vec = gen_rtvec (2, pat, clobber);
13943 else /* action == CONV */
13944 vec = gen_rtvec (2, pat, clobber);
13946 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
13947 INSN_CODE (insn) = -1;
13951 if (NONDEBUG_INSN_P (insn))
13952 df_simulate_one_insn_backwards (bb, insn, &live);
13956 CLEAR_REG_SET (&live);
13959 /* Gcc puts the pool in the wrong place for ARM, since we can only
13960 load addresses a limited distance around the pc. We do some
13961 special munging to move the constant pool values to the correct
13962 point in the code. */
13967 HOST_WIDE_INT address = 0;
13972 else if (TARGET_THUMB2)
13975 /* Ensure all insns that must be split have been split at this point.
13976 Otherwise, the pool placement code below may compute incorrect
13977 insn lengths. Note that when optimizing, all insns have already
13978 been split at this point. */
13980 split_all_insns_noflow ();
13982 minipool_fix_head = minipool_fix_tail = NULL;
13984 /* The first insn must always be a note, or the code below won't
13985 scan it properly. */
13986 insn = get_insns ();
13987 gcc_assert (NOTE_P (insn));
13990 /* Scan all the insns and record the operands that will need fixing. */
13991 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
13993 if (BARRIER_P (insn))
13994 push_minipool_barrier (insn, address);
13995 else if (INSN_P (insn))
13999 note_invalid_constants (insn, address, true);
14000 address += get_attr_length (insn);
14002 /* If the insn is a vector jump, add the size of the table
14003 and skip the table. */
14004 if ((table = is_jump_table (insn)) != NULL)
14006 address += get_jump_table_size (table);
14010 else if (LABEL_P (insn))
14011 /* Add the worst-case padding due to alignment. We don't add
14012 the _current_ padding because the minipool insertions
14013 themselves might change it. */
14014 address += get_label_padding (insn);
14017 fix = minipool_fix_head;
14019 /* Now scan the fixups and perform the required changes. */
14024 Mfix * last_added_fix;
14025 Mfix * last_barrier = NULL;
14028 /* Skip any further barriers before the next fix. */
14029 while (fix && BARRIER_P (fix->insn))
14032 /* No more fixes. */
14036 last_added_fix = NULL;
14038 for (ftmp = fix; ftmp; ftmp = ftmp->next)
14040 if (BARRIER_P (ftmp->insn))
14042 if (ftmp->address >= minipool_vector_head->max_address)
14045 last_barrier = ftmp;
14047 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
14050 last_added_fix = ftmp; /* Keep track of the last fix added. */
14053 /* If we found a barrier, drop back to that; any fixes that we
14054 could have reached but come after the barrier will now go in
14055 the next mini-pool. */
14056 if (last_barrier != NULL)
14058 /* Reduce the refcount for those fixes that won't go into this
14060 for (fdel = last_barrier->next;
14061 fdel && fdel != ftmp;
14064 fdel->minipool->refcount--;
14065 fdel->minipool = NULL;
14068 ftmp = last_barrier;
14072 /* ftmp is first fix that we can't fit into this pool and
14073 there no natural barriers that we could use. Insert a
14074 new barrier in the code somewhere between the previous
14075 fix and this one, and arrange to jump around it. */
14076 HOST_WIDE_INT max_address;
14078 /* The last item on the list of fixes must be a barrier, so
14079 we can never run off the end of the list of fixes without
14080 last_barrier being set. */
14083 max_address = minipool_vector_head->max_address;
14084 /* Check that there isn't another fix that is in range that
14085 we couldn't fit into this pool because the pool was
14086 already too large: we need to put the pool before such an
14087 instruction. The pool itself may come just after the
14088 fix because create_fix_barrier also allows space for a
14089 jump instruction. */
14090 if (ftmp->address < max_address)
14091 max_address = ftmp->address + 1;
14093 last_barrier = create_fix_barrier (last_added_fix, max_address);
14096 assign_minipool_offsets (last_barrier);
14100 if (!BARRIER_P (ftmp->insn)
14101 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
14108 /* Scan over the fixes we have identified for this pool, fixing them
14109 up and adding the constants to the pool itself. */
14110 for (this_fix = fix; this_fix && ftmp != this_fix;
14111 this_fix = this_fix->next)
14112 if (!BARRIER_P (this_fix->insn))
14115 = plus_constant (Pmode,
14116 gen_rtx_LABEL_REF (VOIDmode,
14117 minipool_vector_label),
14118 this_fix->minipool->offset);
14119 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
14122 dump_minipool (last_barrier->insn);
14126 /* From now on we must synthesize any constants that we can't handle
14127 directly. This can happen if the RTL gets split during final
14128 instruction generation. */
14129 after_arm_reorg = 1;
14131 /* Free the minipool memory. */
14132 obstack_free (&minipool_obstack, minipool_startobj);
14135 /* Routines to output assembly language. */
14137 /* If the rtx is the correct value then return the string of the number.
14138 In this way we can ensure that valid double constants are generated even
14139 when cross compiling. */
14141 fp_immediate_constant (rtx x)
14145 if (!fp_consts_inited)
14148 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
14150 gcc_assert (REAL_VALUES_EQUAL (r, value_fp0));
14154 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
14155 static const char *
14156 fp_const_from_val (REAL_VALUE_TYPE *r)
14158 if (!fp_consts_inited)
14161 gcc_assert (REAL_VALUES_EQUAL (*r, value_fp0));
14165 /* OPERANDS[0] is the entire list of insns that constitute pop,
14166 OPERANDS[1] is the base register, RETURN_PC is true iff return insn
14167 is in the list, UPDATE is true iff the list contains explicit
14168 update of base register. */
14170 arm_output_multireg_pop (rtx *operands, bool return_pc, rtx cond, bool reverse,
14176 const char *conditional;
14177 int num_saves = XVECLEN (operands[0], 0);
14178 unsigned int regno;
14179 unsigned int regno_base = REGNO (operands[1]);
14182 offset += update ? 1 : 0;
14183 offset += return_pc ? 1 : 0;
14185 /* Is the base register in the list? */
14186 for (i = offset; i < num_saves; i++)
14188 regno = REGNO (XEXP (XVECEXP (operands[0], 0, i), 0));
14189 /* If SP is in the list, then the base register must be SP. */
14190 gcc_assert ((regno != SP_REGNUM) || (regno_base == SP_REGNUM));
14191 /* If base register is in the list, there must be no explicit update. */
14192 if (regno == regno_base)
14193 gcc_assert (!update);
14196 conditional = reverse ? "%?%D0" : "%?%d0";
14197 if ((regno_base == SP_REGNUM) && TARGET_UNIFIED_ASM)
14199 /* Output pop (not stmfd) because it has a shorter encoding. */
14200 gcc_assert (update);
14201 sprintf (pattern, "pop%s\t{", conditional);
14205 /* Output ldmfd when the base register is SP, otherwise output ldmia.
14206 It's just a convention, their semantics are identical. */
14207 if (regno_base == SP_REGNUM)
14208 sprintf (pattern, "ldm%sfd\t", conditional);
14209 else if (TARGET_UNIFIED_ASM)
14210 sprintf (pattern, "ldmia%s\t", conditional);
14212 sprintf (pattern, "ldm%sia\t", conditional);
14214 strcat (pattern, reg_names[regno_base]);
14216 strcat (pattern, "!, {");
14218 strcat (pattern, ", {");
14221 /* Output the first destination register. */
14223 reg_names[REGNO (XEXP (XVECEXP (operands[0], 0, offset), 0))]);
14225 /* Output the rest of the destination registers. */
14226 for (i = offset + 1; i < num_saves; i++)
14228 strcat (pattern, ", ");
14230 reg_names[REGNO (XEXP (XVECEXP (operands[0], 0, i), 0))]);
14233 strcat (pattern, "}");
14235 if (IS_INTERRUPT (arm_current_func_type ()) && return_pc)
14236 strcat (pattern, "^");
14238 output_asm_insn (pattern, &cond);
14242 /* Output the assembly for a store multiple. */
14245 vfp_output_fstmd (rtx * operands)
14252 strcpy (pattern, "fstmfdd%?\t%m0!, {%P1");
14253 p = strlen (pattern);
14255 gcc_assert (REG_P (operands[1]));
14257 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
14258 for (i = 1; i < XVECLEN (operands[2], 0); i++)
14260 p += sprintf (&pattern[p], ", d%d", base + i);
14262 strcpy (&pattern[p], "}");
14264 output_asm_insn (pattern, operands);
14269 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
14270 number of bytes pushed. */
14273 vfp_emit_fstmd (int base_reg, int count)
14280 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
14281 register pairs are stored by a store multiple insn. We avoid this
14282 by pushing an extra pair. */
14283 if (count == 2 && !arm_arch6)
14285 if (base_reg == LAST_VFP_REGNUM - 3)
14290 /* FSTMD may not store more than 16 doubleword registers at once. Split
14291 larger stores into multiple parts (up to a maximum of two, in
14296 /* NOTE: base_reg is an internal register number, so each D register
14298 saved = vfp_emit_fstmd (base_reg + 32, count - 16);
14299 saved += vfp_emit_fstmd (base_reg, 16);
14303 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
14304 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
14306 reg = gen_rtx_REG (DFmode, base_reg);
14309 XVECEXP (par, 0, 0)
14310 = gen_rtx_SET (VOIDmode,
14313 gen_rtx_PRE_MODIFY (Pmode,
14316 (Pmode, stack_pointer_rtx,
14319 gen_rtx_UNSPEC (BLKmode,
14320 gen_rtvec (1, reg),
14321 UNSPEC_PUSH_MULT));
14323 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14324 plus_constant (Pmode, stack_pointer_rtx, -(count * 8)));
14325 RTX_FRAME_RELATED_P (tmp) = 1;
14326 XVECEXP (dwarf, 0, 0) = tmp;
14328 tmp = gen_rtx_SET (VOIDmode,
14329 gen_frame_mem (DFmode, stack_pointer_rtx),
14331 RTX_FRAME_RELATED_P (tmp) = 1;
14332 XVECEXP (dwarf, 0, 1) = tmp;
14334 for (i = 1; i < count; i++)
14336 reg = gen_rtx_REG (DFmode, base_reg);
14338 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
14340 tmp = gen_rtx_SET (VOIDmode,
14341 gen_frame_mem (DFmode,
14342 plus_constant (Pmode,
14346 RTX_FRAME_RELATED_P (tmp) = 1;
14347 XVECEXP (dwarf, 0, i + 1) = tmp;
14350 par = emit_insn (par);
14351 add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf);
14352 RTX_FRAME_RELATED_P (par) = 1;
14357 /* Emit a call instruction with pattern PAT. ADDR is the address of
14358 the call target. */
14361 arm_emit_call_insn (rtx pat, rtx addr)
14365 insn = emit_call_insn (pat);
14367 /* The PIC register is live on entry to VxWorks PIC PLT entries.
14368 If the call might use such an entry, add a use of the PIC register
14369 to the instruction's CALL_INSN_FUNCTION_USAGE. */
14370 if (TARGET_VXWORKS_RTP
14372 && GET_CODE (addr) == SYMBOL_REF
14373 && (SYMBOL_REF_DECL (addr)
14374 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
14375 : !SYMBOL_REF_LOCAL_P (addr)))
14377 require_pic_register ();
14378 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
14382 /* Output a 'call' insn. */
14384 output_call (rtx *operands)
14386 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
14388 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
14389 if (REGNO (operands[0]) == LR_REGNUM)
14391 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
14392 output_asm_insn ("mov%?\t%0, %|lr", operands);
14395 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
14397 if (TARGET_INTERWORK || arm_arch4t)
14398 output_asm_insn ("bx%?\t%0", operands);
14400 output_asm_insn ("mov%?\t%|pc, %0", operands);
14405 /* Output a 'call' insn that is a reference in memory. This is
14406 disabled for ARMv5 and we prefer a blx instead because otherwise
14407 there's a significant performance overhead. */
14409 output_call_mem (rtx *operands)
14411 gcc_assert (!arm_arch5);
14412 if (TARGET_INTERWORK)
14414 output_asm_insn ("ldr%?\t%|ip, %0", operands);
14415 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
14416 output_asm_insn ("bx%?\t%|ip", operands);
14418 else if (regno_use_in (LR_REGNUM, operands[0]))
14420 /* LR is used in the memory address. We load the address in the
14421 first instruction. It's safe to use IP as the target of the
14422 load since the call will kill it anyway. */
14423 output_asm_insn ("ldr%?\t%|ip, %0", operands);
14424 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
14426 output_asm_insn ("bx%?\t%|ip", operands);
14428 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
14432 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
14433 output_asm_insn ("ldr%?\t%|pc, %0", operands);
14440 /* Output a move from arm registers to arm registers of a long double
14441 OPERANDS[0] is the destination.
14442 OPERANDS[1] is the source. */
14444 output_mov_long_double_arm_from_arm (rtx *operands)
14446 /* We have to be careful here because the two might overlap. */
14447 int dest_start = REGNO (operands[0]);
14448 int src_start = REGNO (operands[1]);
14452 if (dest_start < src_start)
14454 for (i = 0; i < 3; i++)
14456 ops[0] = gen_rtx_REG (SImode, dest_start + i);
14457 ops[1] = gen_rtx_REG (SImode, src_start + i);
14458 output_asm_insn ("mov%?\t%0, %1", ops);
14463 for (i = 2; i >= 0; i--)
14465 ops[0] = gen_rtx_REG (SImode, dest_start + i);
14466 ops[1] = gen_rtx_REG (SImode, src_start + i);
14467 output_asm_insn ("mov%?\t%0, %1", ops);
14475 arm_emit_movpair (rtx dest, rtx src)
14477 /* If the src is an immediate, simplify it. */
14478 if (CONST_INT_P (src))
14480 HOST_WIDE_INT val = INTVAL (src);
14481 emit_set_insn (dest, GEN_INT (val & 0x0000ffff));
14482 if ((val >> 16) & 0x0000ffff)
14483 emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode, dest, GEN_INT (16),
14485 GEN_INT ((val >> 16) & 0x0000ffff));
14488 emit_set_insn (dest, gen_rtx_HIGH (SImode, src));
14489 emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src));
14492 /* Output a move between double words. It must be REG<-MEM
14495 output_move_double (rtx *operands, bool emit, int *count)
14497 enum rtx_code code0 = GET_CODE (operands[0]);
14498 enum rtx_code code1 = GET_CODE (operands[1]);
14503 /* The only case when this might happen is when
14504 you are looking at the length of a DImode instruction
14505 that has an invalid constant in it. */
14506 if (code0 == REG && code1 != MEM)
14508 gcc_assert (!emit);
14515 unsigned int reg0 = REGNO (operands[0]);
14517 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
14519 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
14521 switch (GET_CODE (XEXP (operands[1], 0)))
14528 && !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0))))
14529 output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands);
14531 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
14536 gcc_assert (TARGET_LDRD);
14538 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
14545 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
14547 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
14555 output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands);
14557 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
14562 gcc_assert (TARGET_LDRD);
14564 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
14569 /* Autoicrement addressing modes should never have overlapping
14570 base and destination registers, and overlapping index registers
14571 are already prohibited, so this doesn't need to worry about
14573 otherops[0] = operands[0];
14574 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
14575 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
14577 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
14579 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
14581 /* Registers overlap so split out the increment. */
14584 output_asm_insn ("add%?\t%1, %1, %2", otherops);
14585 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
14592 /* Use a single insn if we can.
14593 FIXME: IWMMXT allows offsets larger than ldrd can
14594 handle, fix these up with a pair of ldr. */
14596 || !CONST_INT_P (otherops[2])
14597 || (INTVAL (otherops[2]) > -256
14598 && INTVAL (otherops[2]) < 256))
14601 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
14607 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
14608 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
14618 /* Use a single insn if we can.
14619 FIXME: IWMMXT allows offsets larger than ldrd can handle,
14620 fix these up with a pair of ldr. */
14622 || !CONST_INT_P (otherops[2])
14623 || (INTVAL (otherops[2]) > -256
14624 && INTVAL (otherops[2]) < 256))
14627 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
14633 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
14634 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
14644 /* We might be able to use ldrd %0, %1 here. However the range is
14645 different to ldr/adr, and it is broken on some ARMv7-M
14646 implementations. */
14647 /* Use the second register of the pair to avoid problematic
14649 otherops[1] = operands[1];
14651 output_asm_insn ("adr%?\t%0, %1", otherops);
14652 operands[1] = otherops[0];
14656 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands);
14658 output_asm_insn ("ldm%(ia%)\t%1, %M0", operands);
14665 /* ??? This needs checking for thumb2. */
14667 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
14668 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
14670 otherops[0] = operands[0];
14671 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
14672 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
14674 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
14676 if (CONST_INT_P (otherops[2]) && !TARGET_LDRD)
14678 switch ((int) INTVAL (otherops[2]))
14682 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
14688 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
14694 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
14698 otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1);
14699 operands[1] = otherops[0];
14701 && (REG_P (otherops[2])
14703 || (CONST_INT_P (otherops[2])
14704 && INTVAL (otherops[2]) > -256
14705 && INTVAL (otherops[2]) < 256)))
14707 if (reg_overlap_mentioned_p (operands[0],
14711 /* Swap base and index registers over to
14712 avoid a conflict. */
14714 otherops[1] = otherops[2];
14717 /* If both registers conflict, it will usually
14718 have been fixed by a splitter. */
14719 if (reg_overlap_mentioned_p (operands[0], otherops[2])
14720 || (fix_cm3_ldrd && reg0 == REGNO (otherops[1])))
14724 output_asm_insn ("add%?\t%0, %1, %2", otherops);
14725 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands);
14732 otherops[0] = operands[0];
14734 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
14739 if (CONST_INT_P (otherops[2]))
14743 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
14744 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
14746 output_asm_insn ("add%?\t%0, %1, %2", otherops);
14752 output_asm_insn ("add%?\t%0, %1, %2", otherops);
14758 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
14765 return "ldr%(d%)\t%0, [%1]";
14767 return "ldm%(ia%)\t%1, %M0";
14771 otherops[1] = adjust_address (operands[1], SImode, 4);
14772 /* Take care of overlapping base/data reg. */
14773 if (reg_mentioned_p (operands[0], operands[1]))
14777 output_asm_insn ("ldr%?\t%0, %1", otherops);
14778 output_asm_insn ("ldr%?\t%0, %1", operands);
14788 output_asm_insn ("ldr%?\t%0, %1", operands);
14789 output_asm_insn ("ldr%?\t%0, %1", otherops);
14799 /* Constraints should ensure this. */
14800 gcc_assert (code0 == MEM && code1 == REG);
14801 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
14803 switch (GET_CODE (XEXP (operands[0], 0)))
14809 output_asm_insn ("str%(d%)\t%1, [%m0]", operands);
14811 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
14816 gcc_assert (TARGET_LDRD);
14818 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
14825 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
14827 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
14835 output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands);
14837 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
14842 gcc_assert (TARGET_LDRD);
14844 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
14849 otherops[0] = operands[1];
14850 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
14851 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
14853 /* IWMMXT allows offsets larger than ldrd can handle,
14854 fix these up with a pair of ldr. */
14856 && CONST_INT_P (otherops[2])
14857 && (INTVAL(otherops[2]) <= -256
14858 || INTVAL(otherops[2]) >= 256))
14860 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
14864 output_asm_insn ("str%?\t%0, [%1, %2]!", otherops);
14865 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
14874 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
14875 output_asm_insn ("str%?\t%0, [%1], %2", otherops);
14881 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
14884 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
14889 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
14894 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
14895 if (CONST_INT_P (otherops[2]) && !TARGET_LDRD)
14897 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
14901 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
14908 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
14915 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
14920 && (REG_P (otherops[2])
14922 || (CONST_INT_P (otherops[2])
14923 && INTVAL (otherops[2]) > -256
14924 && INTVAL (otherops[2]) < 256)))
14926 otherops[0] = operands[1];
14927 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
14929 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
14935 otherops[0] = adjust_address (operands[0], SImode, 4);
14936 otherops[1] = operands[1];
14939 output_asm_insn ("str%?\t%1, %0", operands);
14940 output_asm_insn ("str%?\t%H1, %0", otherops);
14950 /* Output a move, load or store for quad-word vectors in ARM registers. Only
14951 handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
14954 output_move_quad (rtx *operands)
14956 if (REG_P (operands[0]))
14958 /* Load, or reg->reg move. */
14960 if (MEM_P (operands[1]))
14962 switch (GET_CODE (XEXP (operands[1], 0)))
14965 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
14970 output_asm_insn ("adr%?\t%0, %1", operands);
14971 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
14975 gcc_unreachable ();
14983 gcc_assert (REG_P (operands[1]));
14985 dest = REGNO (operands[0]);
14986 src = REGNO (operands[1]);
14988 /* This seems pretty dumb, but hopefully GCC won't try to do it
14991 for (i = 0; i < 4; i++)
14993 ops[0] = gen_rtx_REG (SImode, dest + i);
14994 ops[1] = gen_rtx_REG (SImode, src + i);
14995 output_asm_insn ("mov%?\t%0, %1", ops);
14998 for (i = 3; i >= 0; i--)
15000 ops[0] = gen_rtx_REG (SImode, dest + i);
15001 ops[1] = gen_rtx_REG (SImode, src + i);
15002 output_asm_insn ("mov%?\t%0, %1", ops);
15008 gcc_assert (MEM_P (operands[0]));
15009 gcc_assert (REG_P (operands[1]));
15010 gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0]));
15012 switch (GET_CODE (XEXP (operands[0], 0)))
15015 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
15019 gcc_unreachable ();
15026 /* Output a VFP load or store instruction. */
15029 output_move_vfp (rtx *operands)
15031 rtx reg, mem, addr, ops[2];
15032 int load = REG_P (operands[0]);
15033 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
15034 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
15037 enum machine_mode mode;
15039 reg = operands[!load];
15040 mem = operands[load];
15042 mode = GET_MODE (reg);
15044 gcc_assert (REG_P (reg));
15045 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
15046 gcc_assert (mode == SFmode
15050 || (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
15051 gcc_assert (MEM_P (mem));
15053 addr = XEXP (mem, 0);
15055 switch (GET_CODE (addr))
15058 templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
15059 ops[0] = XEXP (addr, 0);
15064 templ = "f%smia%c%%?\t%%0!, {%%%s1}%s";
15065 ops[0] = XEXP (addr, 0);
15070 templ = "f%s%c%%?\t%%%s0, %%1%s";
15076 sprintf (buff, templ,
15077 load ? "ld" : "st",
15080 integer_p ? "\t%@ int" : "");
15081 output_asm_insn (buff, ops);
15086 /* Output a Neon double-word or quad-word load or store, or a load
15087 or store for larger structure modes.
15089 WARNING: The ordering of elements is weird in big-endian mode,
15090 because the EABI requires that vectors stored in memory appear
15091 as though they were stored by a VSTM, as required by the EABI.
15092 GCC RTL defines element ordering based on in-memory order.
15093 This can be different from the architectural ordering of elements
15094 within a NEON register. The intrinsics defined in arm_neon.h use the
15095 NEON register element ordering, not the GCC RTL element ordering.
15097 For example, the in-memory ordering of a big-endian a quadword
15098 vector with 16-bit elements when stored from register pair {d0,d1}
15099 will be (lowest address first, d0[N] is NEON register element N):
15101 [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]]
15103 When necessary, quadword registers (dN, dN+1) are moved to ARM
15104 registers from rN in the order:
15106 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
15108 So that STM/LDM can be used on vectors in ARM registers, and the
15109 same memory layout will result as if VSTM/VLDM were used.
15111 Instead of VSTM/VLDM we prefer to use VST1.64/VLD1.64 where
15112 possible, which allows use of appropriate alignment tags.
15113 Note that the choice of "64" is independent of the actual vector
15114 element size; this size simply ensures that the behavior is
15115 equivalent to VSTM/VLDM in both little-endian and big-endian mode.
15117 Due to limitations of those instructions, use of VST1.64/VLD1.64
15118 is not possible if:
15119 - the address contains PRE_DEC, or
15120 - the mode refers to more than 4 double-word registers
15122 In those cases, it would be possible to replace VSTM/VLDM by a
15123 sequence of instructions; this is not currently implemented since
15124 this is not certain to actually improve performance. */
15127 output_move_neon (rtx *operands)
15129 rtx reg, mem, addr, ops[2];
15130 int regno, nregs, load = REG_P (operands[0]);
15133 enum machine_mode mode;
15135 reg = operands[!load];
15136 mem = operands[load];
15138 mode = GET_MODE (reg);
15140 gcc_assert (REG_P (reg));
15141 regno = REGNO (reg);
15142 nregs = HARD_REGNO_NREGS (regno, mode) / 2;
15143 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno)
15144 || NEON_REGNO_OK_FOR_QUAD (regno));
15145 gcc_assert (VALID_NEON_DREG_MODE (mode)
15146 || VALID_NEON_QREG_MODE (mode)
15147 || VALID_NEON_STRUCT_MODE (mode));
15148 gcc_assert (MEM_P (mem));
15150 addr = XEXP (mem, 0);
15152 /* Strip off const from addresses like (const (plus (...))). */
15153 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS)
15154 addr = XEXP (addr, 0);
15156 switch (GET_CODE (addr))
15159 /* We have to use vldm / vstm for too-large modes. */
15162 templ = "v%smia%%?\t%%0!, %%h1";
15163 ops[0] = XEXP (addr, 0);
15167 templ = "v%s1.64\t%%h1, %%A0";
15174 /* We have to use vldm / vstm in this case, since there is no
15175 pre-decrement form of the vld1 / vst1 instructions. */
15176 templ = "v%smdb%%?\t%%0!, %%h1";
15177 ops[0] = XEXP (addr, 0);
15182 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
15183 gcc_unreachable ();
15190 for (i = 0; i < nregs; i++)
15192 /* We're only using DImode here because it's a convenient size. */
15193 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i);
15194 ops[1] = adjust_address (mem, DImode, 8 * i);
15195 if (reg_overlap_mentioned_p (ops[0], mem))
15197 gcc_assert (overlap == -1);
15202 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
15203 output_asm_insn (buff, ops);
15208 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap);
15209 ops[1] = adjust_address (mem, SImode, 8 * overlap);
15210 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
15211 output_asm_insn (buff, ops);
15218 /* We have to use vldm / vstm for too-large modes. */
15220 templ = "v%smia%%?\t%%m0, %%h1";
15222 templ = "v%s1.64\t%%h1, %%A0";
15228 sprintf (buff, templ, load ? "ld" : "st");
15229 output_asm_insn (buff, ops);
15234 /* Compute and return the length of neon_mov<mode>, where <mode> is
15235 one of VSTRUCT modes: EI, OI, CI or XI. */
15237 arm_attr_length_move_neon (rtx insn)
15239 rtx reg, mem, addr;
15241 enum machine_mode mode;
15243 extract_insn_cached (insn);
15245 if (REG_P (recog_data.operand[0]) && REG_P (recog_data.operand[1]))
15247 mode = GET_MODE (recog_data.operand[0]);
15258 gcc_unreachable ();
15262 load = REG_P (recog_data.operand[0]);
15263 reg = recog_data.operand[!load];
15264 mem = recog_data.operand[load];
15266 gcc_assert (MEM_P (mem));
15268 mode = GET_MODE (reg);
15269 addr = XEXP (mem, 0);
15271 /* Strip off const from addresses like (const (plus (...))). */
15272 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS)
15273 addr = XEXP (addr, 0);
15275 if (GET_CODE (addr) == LABEL_REF || GET_CODE (addr) == PLUS)
15277 int insns = HARD_REGNO_NREGS (REGNO (reg), mode) / 2;
15284 /* Return nonzero if the offset in the address is an immediate. Otherwise,
15288 arm_address_offset_is_imm (rtx insn)
15292 extract_insn_cached (insn);
15294 if (REG_P (recog_data.operand[0]))
15297 mem = recog_data.operand[0];
15299 gcc_assert (MEM_P (mem));
15301 addr = XEXP (mem, 0);
15304 || (GET_CODE (addr) == PLUS
15305 && REG_P (XEXP (addr, 0))
15306 && CONST_INT_P (XEXP (addr, 1))))
15312 /* Output an ADD r, s, #n where n may be too big for one instruction.
15313 If adding zero to one register, output nothing. */
15315 output_add_immediate (rtx *operands)
15317 HOST_WIDE_INT n = INTVAL (operands[2]);
15319 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
15322 output_multi_immediate (operands,
15323 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
15326 output_multi_immediate (operands,
15327 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
15334 /* Output a multiple immediate operation.
15335 OPERANDS is the vector of operands referred to in the output patterns.
15336 INSTR1 is the output pattern to use for the first constant.
15337 INSTR2 is the output pattern to use for subsequent constants.
15338 IMMED_OP is the index of the constant slot in OPERANDS.
15339 N is the constant value. */
15340 static const char *
15341 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
15342 int immed_op, HOST_WIDE_INT n)
15344 #if HOST_BITS_PER_WIDE_INT > 32
15350 /* Quick and easy output. */
15351 operands[immed_op] = const0_rtx;
15352 output_asm_insn (instr1, operands);
15357 const char * instr = instr1;
15359 /* Note that n is never zero here (which would give no output). */
15360 for (i = 0; i < 32; i += 2)
15364 operands[immed_op] = GEN_INT (n & (255 << i));
15365 output_asm_insn (instr, operands);
15375 /* Return the name of a shifter operation. */
15376 static const char *
15377 arm_shift_nmem(enum rtx_code code)
15382 return ARM_LSL_NAME;
15398 /* Return the appropriate ARM instruction for the operation code.
15399 The returned result should not be overwritten. OP is the rtx of the
15400 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
15403 arithmetic_instr (rtx op, int shift_first_arg)
15405 switch (GET_CODE (op))
15411 return shift_first_arg ? "rsb" : "sub";
15426 return arm_shift_nmem(GET_CODE(op));
15429 gcc_unreachable ();
15433 /* Ensure valid constant shifts and return the appropriate shift mnemonic
15434 for the operation code. The returned result should not be overwritten.
15435 OP is the rtx code of the shift.
15436 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
15438 static const char *
15439 shift_op (rtx op, HOST_WIDE_INT *amountp)
15442 enum rtx_code code = GET_CODE (op);
15447 if (!CONST_INT_P (XEXP (op, 1)))
15449 output_operand_lossage ("invalid shift operand");
15454 *amountp = 32 - INTVAL (XEXP (op, 1));
15462 mnem = arm_shift_nmem(code);
15463 if (CONST_INT_P (XEXP (op, 1)))
15465 *amountp = INTVAL (XEXP (op, 1));
15467 else if (REG_P (XEXP (op, 1)))
15474 output_operand_lossage ("invalid shift operand");
15480 /* We never have to worry about the amount being other than a
15481 power of 2, since this case can never be reloaded from a reg. */
15482 if (!CONST_INT_P (XEXP (op, 1)))
15484 output_operand_lossage ("invalid shift operand");
15488 *amountp = INTVAL (XEXP (op, 1)) & 0xFFFFFFFF;
15490 /* Amount must be a power of two. */
15491 if (*amountp & (*amountp - 1))
15493 output_operand_lossage ("invalid shift operand");
15497 *amountp = int_log2 (*amountp);
15498 return ARM_LSL_NAME;
15501 output_operand_lossage ("invalid shift operand");
15505 /* This is not 100% correct, but follows from the desire to merge
15506 multiplication by a power of 2 with the recognizer for a
15507 shift. >=32 is not a valid shift for "lsl", so we must try and
15508 output a shift that produces the correct arithmetical result.
15509 Using lsr #32 is identical except for the fact that the carry bit
15510 is not set correctly if we set the flags; but we never use the
15511 carry bit from such an operation, so we can ignore that. */
15512 if (code == ROTATERT)
15513 /* Rotate is just modulo 32. */
15515 else if (*amountp != (*amountp & 31))
15517 if (code == ASHIFT)
15522 /* Shifts of 0 are no-ops. */
15529 /* Obtain the shift from the POWER of two. */
15531 static HOST_WIDE_INT
15532 int_log2 (HOST_WIDE_INT power)
15534 HOST_WIDE_INT shift = 0;
15536 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
15538 gcc_assert (shift <= 31);
15545 /* Output a .ascii pseudo-op, keeping track of lengths. This is
15546 because /bin/as is horribly restrictive. The judgement about
15547 whether or not each character is 'printable' (and can be output as
15548 is) or not (and must be printed with an octal escape) must be made
15549 with reference to the *host* character set -- the situation is
15550 similar to that discussed in the comments above pp_c_char in
15551 c-pretty-print.c. */
15553 #define MAX_ASCII_LEN 51
15556 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
15559 int len_so_far = 0;
15561 fputs ("\t.ascii\t\"", stream);
15563 for (i = 0; i < len; i++)
15567 if (len_so_far >= MAX_ASCII_LEN)
15569 fputs ("\"\n\t.ascii\t\"", stream);
15575 if (c == '\\' || c == '\"')
15577 putc ('\\', stream);
15585 fprintf (stream, "\\%03o", c);
15590 fputs ("\"\n", stream);
15593 /* Compute the register save mask for registers 0 through 12
15594 inclusive. This code is used by arm_compute_save_reg_mask. */
15596 static unsigned long
15597 arm_compute_save_reg0_reg12_mask (void)
15599 unsigned long func_type = arm_current_func_type ();
15600 unsigned long save_reg_mask = 0;
15603 if (IS_INTERRUPT (func_type))
15605 unsigned int max_reg;
15606 /* Interrupt functions must not corrupt any registers,
15607 even call clobbered ones. If this is a leaf function
15608 we can just examine the registers used by the RTL, but
15609 otherwise we have to assume that whatever function is
15610 called might clobber anything, and so we have to save
15611 all the call-clobbered registers as well. */
15612 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
15613 /* FIQ handlers have registers r8 - r12 banked, so
15614 we only need to check r0 - r7, Normal ISRs only
15615 bank r14 and r15, so we must check up to r12.
15616 r13 is the stack pointer which is always preserved,
15617 so we do not need to consider it here. */
15622 for (reg = 0; reg <= max_reg; reg++)
15623 if (df_regs_ever_live_p (reg)
15624 || (! crtl->is_leaf && call_used_regs[reg]))
15625 save_reg_mask |= (1 << reg);
15627 /* Also save the pic base register if necessary. */
15629 && !TARGET_SINGLE_PIC_BASE
15630 && arm_pic_register != INVALID_REGNUM
15631 && crtl->uses_pic_offset_table)
15632 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
15634 else if (IS_VOLATILE(func_type))
15636 /* For noreturn functions we historically omitted register saves
15637 altogether. However this really messes up debugging. As a
15638 compromise save just the frame pointers. Combined with the link
15639 register saved elsewhere this should be sufficient to get
15641 if (frame_pointer_needed)
15642 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
15643 if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM))
15644 save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
15645 if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM))
15646 save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM;
15650 /* In the normal case we only need to save those registers
15651 which are call saved and which are used by this function. */
15652 for (reg = 0; reg <= 11; reg++)
15653 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
15654 save_reg_mask |= (1 << reg);
15656 /* Handle the frame pointer as a special case. */
15657 if (frame_pointer_needed)
15658 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
15660 /* If we aren't loading the PIC register,
15661 don't stack it even though it may be live. */
15663 && !TARGET_SINGLE_PIC_BASE
15664 && arm_pic_register != INVALID_REGNUM
15665 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)
15666 || crtl->uses_pic_offset_table))
15667 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
15669 /* The prologue will copy SP into R0, so save it. */
15670 if (IS_STACKALIGN (func_type))
15671 save_reg_mask |= 1;
15674 /* Save registers so the exception handler can modify them. */
15675 if (crtl->calls_eh_return)
15681 reg = EH_RETURN_DATA_REGNO (i);
15682 if (reg == INVALID_REGNUM)
15684 save_reg_mask |= 1 << reg;
15688 return save_reg_mask;
15692 /* Compute the number of bytes used to store the static chain register on the
15693 stack, above the stack frame. We need to know this accurately to get the
15694 alignment of the rest of the stack frame correct. */
15696 static int arm_compute_static_chain_stack_bytes (void)
15698 unsigned long func_type = arm_current_func_type ();
15699 int static_chain_stack_bytes = 0;
15701 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM &&
15702 IS_NESTED (func_type) &&
15703 df_regs_ever_live_p (3) && crtl->args.pretend_args_size == 0)
15704 static_chain_stack_bytes = 4;
15706 return static_chain_stack_bytes;
15710 /* Compute a bit mask of which registers need to be
15711 saved on the stack for the current function.
15712 This is used by arm_get_frame_offsets, which may add extra registers. */
15714 static unsigned long
15715 arm_compute_save_reg_mask (void)
15717 unsigned int save_reg_mask = 0;
15718 unsigned long func_type = arm_current_func_type ();
15721 if (IS_NAKED (func_type))
15722 /* This should never really happen. */
15725 /* If we are creating a stack frame, then we must save the frame pointer,
15726 IP (which will hold the old stack pointer), LR and the PC. */
15727 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
15729 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
15732 | (1 << PC_REGNUM);
15734 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
15736 /* Decide if we need to save the link register.
15737 Interrupt routines have their own banked link register,
15738 so they never need to save it.
15739 Otherwise if we do not use the link register we do not need to save
15740 it. If we are pushing other registers onto the stack however, we
15741 can save an instruction in the epilogue by pushing the link register
15742 now and then popping it back into the PC. This incurs extra memory
15743 accesses though, so we only do it when optimizing for size, and only
15744 if we know that we will not need a fancy return sequence. */
15745 if (df_regs_ever_live_p (LR_REGNUM)
15748 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
15749 && !crtl->calls_eh_return))
15750 save_reg_mask |= 1 << LR_REGNUM;
15752 if (cfun->machine->lr_save_eliminated)
15753 save_reg_mask &= ~ (1 << LR_REGNUM);
15755 if (TARGET_REALLY_IWMMXT
15756 && ((bit_count (save_reg_mask)
15757 + ARM_NUM_INTS (crtl->args.pretend_args_size +
15758 arm_compute_static_chain_stack_bytes())
15761 /* The total number of registers that are going to be pushed
15762 onto the stack is odd. We need to ensure that the stack
15763 is 64-bit aligned before we start to save iWMMXt registers,
15764 and also before we start to create locals. (A local variable
15765 might be a double or long long which we will load/store using
15766 an iWMMXt instruction). Therefore we need to push another
15767 ARM register, so that the stack will be 64-bit aligned. We
15768 try to avoid using the arg registers (r0 -r3) as they might be
15769 used to pass values in a tail call. */
15770 for (reg = 4; reg <= 12; reg++)
15771 if ((save_reg_mask & (1 << reg)) == 0)
15775 save_reg_mask |= (1 << reg);
15778 cfun->machine->sibcall_blocked = 1;
15779 save_reg_mask |= (1 << 3);
15783 /* We may need to push an additional register for use initializing the
15784 PIC base register. */
15785 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
15786 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
15788 reg = thumb_find_work_register (1 << 4);
15789 if (!call_used_regs[reg])
15790 save_reg_mask |= (1 << reg);
15793 return save_reg_mask;
15797 /* Compute a bit mask of which registers need to be
15798 saved on the stack for the current function. */
15799 static unsigned long
15800 thumb1_compute_save_reg_mask (void)
15802 unsigned long mask;
15806 for (reg = 0; reg < 12; reg ++)
15807 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
15811 && !TARGET_SINGLE_PIC_BASE
15812 && arm_pic_register != INVALID_REGNUM
15813 && crtl->uses_pic_offset_table)
15814 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
15816 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
15817 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
15818 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
15820 /* LR will also be pushed if any lo regs are pushed. */
15821 if (mask & 0xff || thumb_force_lr_save ())
15822 mask |= (1 << LR_REGNUM);
15824 /* Make sure we have a low work register if we need one.
15825 We will need one if we are going to push a high register,
15826 but we are not currently intending to push a low register. */
15827 if ((mask & 0xff) == 0
15828 && ((mask & 0x0f00) || TARGET_BACKTRACE))
15830 /* Use thumb_find_work_register to choose which register
15831 we will use. If the register is live then we will
15832 have to push it. Use LAST_LO_REGNUM as our fallback
15833 choice for the register to select. */
15834 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
15835 /* Make sure the register returned by thumb_find_work_register is
15836 not part of the return value. */
15837 if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ())
15838 reg = LAST_LO_REGNUM;
15840 if (! call_used_regs[reg])
15844 /* The 504 below is 8 bytes less than 512 because there are two possible
15845 alignment words. We can't tell here if they will be present or not so we
15846 have to play it safe and assume that they are. */
15847 if ((CALLER_INTERWORKING_SLOT_SIZE +
15848 ROUND_UP_WORD (get_frame_size ()) +
15849 crtl->outgoing_args_size) >= 504)
15851 /* This is the same as the code in thumb1_expand_prologue() which
15852 determines which register to use for stack decrement. */
15853 for (reg = LAST_ARG_REGNUM + 1; reg <= LAST_LO_REGNUM; reg++)
15854 if (mask & (1 << reg))
15857 if (reg > LAST_LO_REGNUM)
15859 /* Make sure we have a register available for stack decrement. */
15860 mask |= 1 << LAST_LO_REGNUM;
15868 /* Return the number of bytes required to save VFP registers. */
15870 arm_get_vfp_saved_size (void)
15872 unsigned int regno;
15877 /* Space for saved VFP registers. */
15878 if (TARGET_HARD_FLOAT && TARGET_VFP)
15881 for (regno = FIRST_VFP_REGNUM;
15882 regno < LAST_VFP_REGNUM;
15885 if ((!df_regs_ever_live_p (regno) || call_used_regs[regno])
15886 && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1]))
15890 /* Workaround ARM10 VFPr1 bug. */
15891 if (count == 2 && !arm_arch6)
15893 saved += count * 8;
15902 if (count == 2 && !arm_arch6)
15904 saved += count * 8;
15911 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
15912 everything bar the final return instruction. If simple_return is true,
15913 then do not output epilogue, because it has already been emitted in RTL. */
15915 output_return_instruction (rtx operand, bool really_return, bool reverse,
15916 bool simple_return)
15918 char conditional[10];
15921 unsigned long live_regs_mask;
15922 unsigned long func_type;
15923 arm_stack_offsets *offsets;
15925 func_type = arm_current_func_type ();
15927 if (IS_NAKED (func_type))
15930 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
15932 /* If this function was declared non-returning, and we have
15933 found a tail call, then we have to trust that the called
15934 function won't return. */
15939 /* Otherwise, trap an attempted return by aborting. */
15941 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
15943 assemble_external_libcall (ops[1]);
15944 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
15950 gcc_assert (!cfun->calls_alloca || really_return);
15952 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
15954 cfun->machine->return_used_this_function = 1;
15956 offsets = arm_get_frame_offsets ();
15957 live_regs_mask = offsets->saved_regs_mask;
15959 if (!simple_return && live_regs_mask)
15961 const char * return_reg;
15963 /* If we do not have any special requirements for function exit
15964 (e.g. interworking) then we can load the return address
15965 directly into the PC. Otherwise we must load it into LR. */
15967 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
15968 return_reg = reg_names[PC_REGNUM];
15970 return_reg = reg_names[LR_REGNUM];
15972 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
15974 /* There are three possible reasons for the IP register
15975 being saved. 1) a stack frame was created, in which case
15976 IP contains the old stack pointer, or 2) an ISR routine
15977 corrupted it, or 3) it was saved to align the stack on
15978 iWMMXt. In case 1, restore IP into SP, otherwise just
15980 if (frame_pointer_needed)
15982 live_regs_mask &= ~ (1 << IP_REGNUM);
15983 live_regs_mask |= (1 << SP_REGNUM);
15986 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
15989 /* On some ARM architectures it is faster to use LDR rather than
15990 LDM to load a single register. On other architectures, the
15991 cost is the same. In 26 bit mode, or for exception handlers,
15992 we have to use LDM to load the PC so that the CPSR is also
15994 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
15995 if (live_regs_mask == (1U << reg))
15998 if (reg <= LAST_ARM_REGNUM
15999 && (reg != LR_REGNUM
16001 || ! IS_INTERRUPT (func_type)))
16003 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
16004 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
16011 /* Generate the load multiple instruction to restore the
16012 registers. Note we can get here, even if
16013 frame_pointer_needed is true, but only if sp already
16014 points to the base of the saved core registers. */
16015 if (live_regs_mask & (1 << SP_REGNUM))
16017 unsigned HOST_WIDE_INT stack_adjust;
16019 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
16020 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
16022 if (stack_adjust && arm_arch5 && TARGET_ARM)
16023 if (TARGET_UNIFIED_ASM)
16024 sprintf (instr, "ldmib%s\t%%|sp, {", conditional);
16026 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
16029 /* If we can't use ldmib (SA110 bug),
16030 then try to pop r3 instead. */
16032 live_regs_mask |= 1 << 3;
16034 if (TARGET_UNIFIED_ASM)
16035 sprintf (instr, "ldmfd%s\t%%|sp, {", conditional);
16037 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
16041 if (TARGET_UNIFIED_ASM)
16042 sprintf (instr, "pop%s\t{", conditional);
16044 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
16046 p = instr + strlen (instr);
16048 for (reg = 0; reg <= SP_REGNUM; reg++)
16049 if (live_regs_mask & (1 << reg))
16051 int l = strlen (reg_names[reg]);
16057 memcpy (p, ", ", 2);
16061 memcpy (p, "%|", 2);
16062 memcpy (p + 2, reg_names[reg], l);
16066 if (live_regs_mask & (1 << LR_REGNUM))
16068 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
16069 /* If returning from an interrupt, restore the CPSR. */
16070 if (IS_INTERRUPT (func_type))
16077 output_asm_insn (instr, & operand);
16079 /* See if we need to generate an extra instruction to
16080 perform the actual function return. */
16082 && func_type != ARM_FT_INTERWORKED
16083 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
16085 /* The return has already been handled
16086 by loading the LR into the PC. */
16093 switch ((int) ARM_FUNC_TYPE (func_type))
16097 /* ??? This is wrong for unified assembly syntax. */
16098 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
16101 case ARM_FT_INTERWORKED:
16102 sprintf (instr, "bx%s\t%%|lr", conditional);
16105 case ARM_FT_EXCEPTION:
16106 /* ??? This is wrong for unified assembly syntax. */
16107 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
16111 /* Use bx if it's available. */
16112 if (arm_arch5 || arm_arch4t)
16113 sprintf (instr, "bx%s\t%%|lr", conditional);
16115 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
16119 output_asm_insn (instr, & operand);
16125 /* Write the function name into the code section, directly preceding
16126 the function prologue.
16128 Code will be output similar to this:
16130 .ascii "arm_poke_function_name", 0
16133 .word 0xff000000 + (t1 - t0)
16134 arm_poke_function_name
16136 stmfd sp!, {fp, ip, lr, pc}
16139 When performing a stack backtrace, code can inspect the value
16140 of 'pc' stored at 'fp' + 0. If the trace function then looks
16141 at location pc - 12 and the top 8 bits are set, then we know
16142 that there is a function name embedded immediately preceding this
16143 location and has length ((pc[-3]) & 0xff000000).
16145 We assume that pc is declared as a pointer to an unsigned long.
16147 It is of no benefit to output the function name if we are assembling
16148 a leaf function. These function types will not contain a stack
16149 backtrace structure, therefore it is not possible to determine the
16152 arm_poke_function_name (FILE *stream, const char *name)
16154 unsigned long alignlength;
16155 unsigned long length;
16158 length = strlen (name) + 1;
16159 alignlength = ROUND_UP_WORD (length);
16161 ASM_OUTPUT_ASCII (stream, name, length);
16162 ASM_OUTPUT_ALIGN (stream, 2);
16163 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
16164 assemble_aligned_integer (UNITS_PER_WORD, x);
16167 /* Place some comments into the assembler stream
16168 describing the current function. */
16170 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
16172 unsigned long func_type;
16174 /* ??? Do we want to print some of the below anyway? */
16178 /* Sanity check. */
16179 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
16181 func_type = arm_current_func_type ();
16183 switch ((int) ARM_FUNC_TYPE (func_type))
16186 case ARM_FT_NORMAL:
16188 case ARM_FT_INTERWORKED:
16189 asm_fprintf (f, "\t%@ Function supports interworking.\n");
16192 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
16195 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
16197 case ARM_FT_EXCEPTION:
16198 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
16202 if (IS_NAKED (func_type))
16203 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
16205 if (IS_VOLATILE (func_type))
16206 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
16208 if (IS_NESTED (func_type))
16209 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
16210 if (IS_STACKALIGN (func_type))
16211 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
16213 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
16215 crtl->args.pretend_args_size, frame_size);
16217 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
16218 frame_pointer_needed,
16219 cfun->machine->uses_anonymous_args);
16221 if (cfun->machine->lr_save_eliminated)
16222 asm_fprintf (f, "\t%@ link register save eliminated.\n");
16224 if (crtl->calls_eh_return)
16225 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
16230 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
16231 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
16233 arm_stack_offsets *offsets;
16239 /* Emit any call-via-reg trampolines that are needed for v4t support
16240 of call_reg and call_value_reg type insns. */
16241 for (regno = 0; regno < LR_REGNUM; regno++)
16243 rtx label = cfun->machine->call_via[regno];
16247 switch_to_section (function_section (current_function_decl));
16248 targetm.asm_out.internal_label (asm_out_file, "L",
16249 CODE_LABEL_NUMBER (label));
16250 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
16254 /* ??? Probably not safe to set this here, since it assumes that a
16255 function will be emitted as assembly immediately after we generate
16256 RTL for it. This does not happen for inline functions. */
16257 cfun->machine->return_used_this_function = 0;
16259 else /* TARGET_32BIT */
16261 /* We need to take into account any stack-frame rounding. */
16262 offsets = arm_get_frame_offsets ();
16264 gcc_assert (!use_return_insn (FALSE, NULL)
16265 || (cfun->machine->return_used_this_function != 0)
16266 || offsets->saved_regs == offsets->outgoing_args
16267 || frame_pointer_needed);
16269 /* Reset the ARM-specific per-function variables. */
16270 after_arm_reorg = 0;
16274 /* Generate and emit a pattern that will be recognized as STRD pattern. If even
16275 number of registers are being pushed, multiple STRD patterns are created for
16276 all register pairs. If odd number of registers are pushed, emit a
16277 combination of STRDs and STR for the prologue saves. */
16279 thumb2_emit_strd_push (unsigned long saved_regs_mask)
16283 rtx par = NULL_RTX;
16284 rtx insn = NULL_RTX;
16285 rtx dwarf = NULL_RTX;
16286 rtx tmp, reg, tmp1;
16288 for (i = 0; i <= LAST_ARM_REGNUM; i++)
16289 if (saved_regs_mask & (1 << i))
16292 gcc_assert (num_regs && num_regs <= 16);
16294 /* Pre-decrement the stack pointer, based on there being num_regs 4-byte
16295 registers to push. */
16296 tmp = gen_rtx_SET (VOIDmode,
16298 plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs));
16299 RTX_FRAME_RELATED_P (tmp) = 1;
16300 insn = emit_insn (tmp);
16302 /* Create sequence for DWARF info. */
16303 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1));
16305 /* RTLs cannot be shared, hence create new copy for dwarf. */
16306 tmp1 = gen_rtx_SET (VOIDmode,
16308 plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs));
16309 RTX_FRAME_RELATED_P (tmp1) = 1;
16310 XVECEXP (dwarf, 0, 0) = tmp1;
16312 gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM)));
16313 gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM)));
16315 /* Var j iterates over all the registers to gather all the registers in
16316 saved_regs_mask. Var i gives index of register R_j in stack frame.
16317 A PARALLEL RTX of register-pair is created here, so that pattern for
16318 STRD can be matched. If num_regs is odd, 1st register will be pushed
16319 using STR and remaining registers will be pushed with STRD in pairs.
16320 If num_regs is even, all registers are pushed with STRD in pairs.
16321 Hence, skip first element for odd num_regs. */
16322 for (i = num_regs - 1, j = LAST_ARM_REGNUM; i >= (num_regs % 2); j--)
16323 if (saved_regs_mask & (1 << j))
16325 /* Create RTX for store. New RTX is created for dwarf as
16326 they are not sharable. */
16327 reg = gen_rtx_REG (SImode, j);
16328 tmp = gen_rtx_SET (SImode,
16331 plus_constant (Pmode, stack_pointer_rtx, 4 * i)),
16334 tmp1 = gen_rtx_SET (SImode,
16337 plus_constant (Pmode, stack_pointer_rtx, 4 * i)),
16339 RTX_FRAME_RELATED_P (tmp) = 1;
16340 RTX_FRAME_RELATED_P (tmp1) = 1;
16342 if (((i - (num_regs % 2)) % 2) == 1)
16343 /* When (i - (num_regs % 2)) is odd, the RTX to be emitted is yet to
16344 be created. Hence create it first. The STRD pattern we are
16346 [ (SET (MEM (PLUS (SP) (NUM))) (reg_t1))
16347 (SET (MEM (PLUS (SP) (NUM + 4))) (reg_t2)) ]
16348 where the target registers need not be consecutive. */
16349 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
16351 /* Register R_j is added in PARALLEL RTX. If (i - (num_regs % 2)) is
16352 even, the reg_j is added as 0th element and if it is odd, reg_i is
16353 added as 1st element of STRD pattern shown above. */
16354 XVECEXP (par, 0, ((i - (num_regs % 2)) % 2)) = tmp;
16355 XVECEXP (dwarf, 0, (i + 1)) = tmp1;
16357 if (((i - (num_regs % 2)) % 2) == 0)
16358 /* When (i - (num_regs % 2)) is even, RTXs for both the registers
16359 to be loaded are generated in above given STRD pattern, and the
16360 pattern can be emitted now. */
16366 if ((num_regs % 2) == 1)
16368 /* If odd number of registers are pushed, generate STR pattern to store
16370 for (; (saved_regs_mask & (1 << j)) == 0; j--);
16372 tmp1 = gen_frame_mem (SImode, plus_constant (Pmode,
16373 stack_pointer_rtx, 4 * i));
16374 reg = gen_rtx_REG (SImode, j);
16375 tmp = gen_rtx_SET (SImode, tmp1, reg);
16376 RTX_FRAME_RELATED_P (tmp) = 1;
16380 tmp1 = gen_rtx_SET (SImode,
16383 plus_constant (Pmode, stack_pointer_rtx, 4 * i)),
16385 RTX_FRAME_RELATED_P (tmp1) = 1;
16386 XVECEXP (dwarf, 0, (i + 1)) = tmp1;
16389 add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
16390 RTX_FRAME_RELATED_P (insn) = 1;
16394 /* Generate and emit an insn that we will recognize as a push_multi.
16395 Unfortunately, since this insn does not reflect very well the actual
16396 semantics of the operation, we need to annotate the insn for the benefit
16397 of DWARF2 frame unwind information. */
16399 emit_multi_reg_push (unsigned long mask)
16402 int num_dwarf_regs;
16406 int dwarf_par_index;
16409 for (i = 0; i <= LAST_ARM_REGNUM; i++)
16410 if (mask & (1 << i))
16413 gcc_assert (num_regs && num_regs <= 16);
16415 /* We don't record the PC in the dwarf frame information. */
16416 num_dwarf_regs = num_regs;
16417 if (mask & (1 << PC_REGNUM))
16420 /* For the body of the insn we are going to generate an UNSPEC in
16421 parallel with several USEs. This allows the insn to be recognized
16422 by the push_multi pattern in the arm.md file.
16424 The body of the insn looks something like this:
16427 (set (mem:BLK (pre_modify:SI (reg:SI sp)
16428 (const_int:SI <num>)))
16429 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
16435 For the frame note however, we try to be more explicit and actually
16436 show each register being stored into the stack frame, plus a (single)
16437 decrement of the stack pointer. We do it this way in order to be
16438 friendly to the stack unwinding code, which only wants to see a single
16439 stack decrement per instruction. The RTL we generate for the note looks
16440 something like this:
16443 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
16444 (set (mem:SI (reg:SI sp)) (reg:SI r4))
16445 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX))
16446 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY))
16450 FIXME:: In an ideal world the PRE_MODIFY would not exist and
16451 instead we'd have a parallel expression detailing all
16452 the stores to the various memory addresses so that debug
16453 information is more up-to-date. Remember however while writing
16454 this to take care of the constraints with the push instruction.
16456 Note also that this has to be taken care of for the VFP registers.
16458 For more see PR43399. */
16460 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
16461 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
16462 dwarf_par_index = 1;
16464 for (i = 0; i <= LAST_ARM_REGNUM; i++)
16466 if (mask & (1 << i))
16468 reg = gen_rtx_REG (SImode, i);
16470 XVECEXP (par, 0, 0)
16471 = gen_rtx_SET (VOIDmode,
16474 gen_rtx_PRE_MODIFY (Pmode,
16477 (Pmode, stack_pointer_rtx,
16480 gen_rtx_UNSPEC (BLKmode,
16481 gen_rtvec (1, reg),
16482 UNSPEC_PUSH_MULT));
16484 if (i != PC_REGNUM)
16486 tmp = gen_rtx_SET (VOIDmode,
16487 gen_frame_mem (SImode, stack_pointer_rtx),
16489 RTX_FRAME_RELATED_P (tmp) = 1;
16490 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
16498 for (j = 1, i++; j < num_regs; i++)
16500 if (mask & (1 << i))
16502 reg = gen_rtx_REG (SImode, i);
16504 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
16506 if (i != PC_REGNUM)
16509 = gen_rtx_SET (VOIDmode,
16512 plus_constant (Pmode, stack_pointer_rtx,
16515 RTX_FRAME_RELATED_P (tmp) = 1;
16516 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
16523 par = emit_insn (par);
16525 tmp = gen_rtx_SET (VOIDmode,
16527 plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs));
16528 RTX_FRAME_RELATED_P (tmp) = 1;
16529 XVECEXP (dwarf, 0, 0) = tmp;
16531 add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf);
16536 /* Generate and emit an insn pattern that we will recognize as a pop_multi.
16537 SAVED_REGS_MASK shows which registers need to be restored.
16539 Unfortunately, since this insn does not reflect very well the actual
16540 semantics of the operation, we need to annotate the insn for the benefit
16541 of DWARF2 frame unwind information. */
16543 arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
16548 rtx dwarf = NULL_RTX;
16554 return_in_pc = (saved_regs_mask & (1 << PC_REGNUM)) ? true : false;
16555 offset_adj = return_in_pc ? 1 : 0;
16556 for (i = 0; i <= LAST_ARM_REGNUM; i++)
16557 if (saved_regs_mask & (1 << i))
16560 gcc_assert (num_regs && num_regs <= 16);
16562 /* If SP is in reglist, then we don't emit SP update insn. */
16563 emit_update = (saved_regs_mask & (1 << SP_REGNUM)) ? 0 : 1;
16565 /* The parallel needs to hold num_regs SETs
16566 and one SET for the stack update. */
16567 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs + emit_update + offset_adj));
16572 XVECEXP (par, 0, 0) = tmp;
16577 /* Increment the stack pointer, based on there being
16578 num_regs 4-byte registers to restore. */
16579 tmp = gen_rtx_SET (VOIDmode,
16581 plus_constant (Pmode,
16584 RTX_FRAME_RELATED_P (tmp) = 1;
16585 XVECEXP (par, 0, offset_adj) = tmp;
16588 /* Now restore every reg, which may include PC. */
16589 for (j = 0, i = 0; j < num_regs; i++)
16590 if (saved_regs_mask & (1 << i))
16592 reg = gen_rtx_REG (SImode, i);
16593 tmp = gen_rtx_SET (VOIDmode,
16597 plus_constant (Pmode, stack_pointer_rtx, 4 * j)));
16598 RTX_FRAME_RELATED_P (tmp) = 1;
16599 XVECEXP (par, 0, j + emit_update + offset_adj) = tmp;
16601 /* We need to maintain a sequence for DWARF info too. As dwarf info
16602 should not have PC, skip PC. */
16603 if (i != PC_REGNUM)
16604 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
16610 par = emit_jump_insn (par);
16612 par = emit_insn (par);
16614 REG_NOTES (par) = dwarf;
16617 /* Generate and emit an insn pattern that we will recognize as a pop_multi
16618 of NUM_REGS consecutive VFP regs, starting at FIRST_REG.
16620 Unfortunately, since this insn does not reflect very well the actual
16621 semantics of the operation, we need to annotate the insn for the benefit
16622 of DWARF2 frame unwind information. */
16624 arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
16628 rtx dwarf = NULL_RTX;
16631 gcc_assert (num_regs && num_regs <= 32);
16633 /* Workaround ARM10 VFPr1 bug. */
16634 if (num_regs == 2 && !arm_arch6)
16636 if (first_reg == 15)
16642 /* We can emit at most 16 D-registers in a single pop_multi instruction, and
16643 there could be up to 32 D-registers to restore.
16644 If there are more than 16 D-registers, make two recursive calls,
16645 each of which emits one pop_multi instruction. */
16648 arm_emit_vfp_multi_reg_pop (first_reg, 16, base_reg);
16649 arm_emit_vfp_multi_reg_pop (first_reg + 16, num_regs - 16, base_reg);
16653 /* The parallel needs to hold num_regs SETs
16654 and one SET for the stack update. */
16655 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs + 1));
16657 /* Increment the stack pointer, based on there being
16658 num_regs 8-byte registers to restore. */
16659 tmp = gen_rtx_SET (VOIDmode,
16661 plus_constant (Pmode, base_reg, 8 * num_regs));
16662 RTX_FRAME_RELATED_P (tmp) = 1;
16663 XVECEXP (par, 0, 0) = tmp;
16665 /* Now show every reg that will be restored, using a SET for each. */
16666 for (j = 0, i=first_reg; j < num_regs; i += 2)
16668 reg = gen_rtx_REG (DFmode, i);
16670 tmp = gen_rtx_SET (VOIDmode,
16674 plus_constant (Pmode, base_reg, 8 * j)));
16675 RTX_FRAME_RELATED_P (tmp) = 1;
16676 XVECEXP (par, 0, j + 1) = tmp;
16678 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
16683 par = emit_insn (par);
16684 REG_NOTES (par) = dwarf;
16687 /* Generate and emit a pattern that will be recognized as LDRD pattern. If even
16688 number of registers are being popped, multiple LDRD patterns are created for
16689 all register pairs. If odd number of registers are popped, last register is
16690 loaded by using LDR pattern. */
16692 thumb2_emit_ldrd_pop (unsigned long saved_regs_mask)
16696 rtx par = NULL_RTX;
16697 rtx dwarf = NULL_RTX;
16698 rtx tmp, reg, tmp1;
16701 return_in_pc = (saved_regs_mask & (1 << PC_REGNUM)) ? true : false;
16702 for (i = 0; i <= LAST_ARM_REGNUM; i++)
16703 if (saved_regs_mask & (1 << i))
16706 gcc_assert (num_regs && num_regs <= 16);
16708 /* We cannot generate ldrd for PC. Hence, reduce the count if PC is
16709 to be popped. So, if num_regs is even, now it will become odd,
16710 and we can generate pop with PC. If num_regs is odd, it will be
16711 even now, and ldr with return can be generated for PC. */
16715 gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM)));
16717 /* Var j iterates over all the registers to gather all the registers in
16718 saved_regs_mask. Var i gives index of saved registers in stack frame.
16719 A PARALLEL RTX of register-pair is created here, so that pattern for
16720 LDRD can be matched. As PC is always last register to be popped, and
16721 we have already decremented num_regs if PC, we don't have to worry
16722 about PC in this loop. */
16723 for (i = 0, j = 0; i < (num_regs - (num_regs % 2)); j++)
16724 if (saved_regs_mask & (1 << j))
16726 /* Create RTX for memory load. */
16727 reg = gen_rtx_REG (SImode, j);
16728 tmp = gen_rtx_SET (SImode,
16730 gen_frame_mem (SImode,
16731 plus_constant (Pmode,
16732 stack_pointer_rtx, 4 * i)));
16733 RTX_FRAME_RELATED_P (tmp) = 1;
16737 /* When saved-register index (i) is even, the RTX to be emitted is
16738 yet to be created. Hence create it first. The LDRD pattern we
16739 are generating is :
16740 [ (SET (reg_t0) (MEM (PLUS (SP) (NUM))))
16741 (SET (reg_t1) (MEM (PLUS (SP) (NUM + 4)))) ]
16742 where target registers need not be consecutive. */
16743 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
16747 /* ith register is added in PARALLEL RTX. If i is even, the reg_i is
16748 added as 0th element and if i is odd, reg_i is added as 1st element
16749 of LDRD pattern shown above. */
16750 XVECEXP (par, 0, (i % 2)) = tmp;
16751 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
16755 /* When saved-register index (i) is odd, RTXs for both the registers
16756 to be loaded are generated in above given LDRD pattern, and the
16757 pattern can be emitted now. */
16758 par = emit_insn (par);
16759 REG_NOTES (par) = dwarf;
16765 /* If the number of registers pushed is odd AND return_in_pc is false OR
16766 number of registers are even AND return_in_pc is true, last register is
16767 popped using LDR. It can be PC as well. Hence, adjust the stack first and
16768 then LDR with post increment. */
16770 /* Increment the stack pointer, based on there being
16771 num_regs 4-byte registers to restore. */
16772 tmp = gen_rtx_SET (VOIDmode,
16774 plus_constant (Pmode, stack_pointer_rtx, 4 * i));
16775 RTX_FRAME_RELATED_P (tmp) = 1;
16780 if (((num_regs % 2) == 1 && !return_in_pc)
16781 || ((num_regs % 2) == 0 && return_in_pc))
16783 /* Scan for the single register to be popped. Skip until the saved
16784 register is found. */
16785 for (; (saved_regs_mask & (1 << j)) == 0; j++);
16787 /* Gen LDR with post increment here. */
16788 tmp1 = gen_rtx_MEM (SImode,
16789 gen_rtx_POST_INC (SImode,
16790 stack_pointer_rtx));
16791 set_mem_alias_set (tmp1, get_frame_alias_set ());
16793 reg = gen_rtx_REG (SImode, j);
16794 tmp = gen_rtx_SET (SImode, reg, tmp1);
16795 RTX_FRAME_RELATED_P (tmp) = 1;
16796 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
16800 /* If return_in_pc, j must be PC_REGNUM. */
16801 gcc_assert (j == PC_REGNUM);
16802 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
16803 XVECEXP (par, 0, 0) = ret_rtx;
16804 XVECEXP (par, 0, 1) = tmp;
16805 par = emit_jump_insn (par);
16809 par = emit_insn (tmp);
16812 REG_NOTES (par) = dwarf;
16814 else if ((num_regs % 2) == 1 && return_in_pc)
16816 /* There are 2 registers to be popped. So, generate the pattern
16817 pop_multiple_with_stack_update_and_return to pop in PC. */
16818 arm_emit_multi_reg_pop (saved_regs_mask & (~((1 << j) - 1)));
16824 /* Calculate the size of the return value that is passed in registers. */
16826 arm_size_return_regs (void)
16828 enum machine_mode mode;
16830 if (crtl->return_rtx != 0)
16831 mode = GET_MODE (crtl->return_rtx);
16833 mode = DECL_MODE (DECL_RESULT (current_function_decl));
16835 return GET_MODE_SIZE (mode);
16838 /* Return true if the current function needs to save/restore LR. */
16840 thumb_force_lr_save (void)
16842 return !cfun->machine->lr_save_eliminated
16843 && (!leaf_function_p ()
16844 || thumb_far_jump_used_p ()
16845 || df_regs_ever_live_p (LR_REGNUM));
16849 /* Return true if r3 is used by any of the tail call insns in the
16850 current function. */
16852 any_sibcall_uses_r3 (void)
16857 if (!crtl->tail_call_emit)
16859 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
16860 if (e->flags & EDGE_SIBCALL)
16862 rtx call = BB_END (e->src);
16863 if (!CALL_P (call))
16864 call = prev_nonnote_nondebug_insn (call);
16865 gcc_assert (CALL_P (call) && SIBLING_CALL_P (call));
16866 if (find_regno_fusage (call, USE, 3))
16873 /* Compute the distance from register FROM to register TO.
16874 These can be the arg pointer (26), the soft frame pointer (25),
16875 the stack pointer (13) or the hard frame pointer (11).
16876 In thumb mode r7 is used as the soft frame pointer, if needed.
16877 Typical stack layout looks like this:
16879 old stack pointer -> | |
16882 | | saved arguments for
16883 | | vararg functions
16886 hard FP & arg pointer -> | | \
16894 soft frame pointer -> | | /
16899 locals base pointer -> | | /
16904 current stack pointer -> | | /
16907 For a given function some or all of these stack components
16908 may not be needed, giving rise to the possibility of
16909 eliminating some of the registers.
16911 The values returned by this function must reflect the behavior
16912 of arm_expand_prologue() and arm_compute_save_reg_mask().
16914 The sign of the number returned reflects the direction of stack
16915 growth, so the values are positive for all eliminations except
16916 from the soft frame pointer to the hard frame pointer.
16918 SFP may point just inside the local variables block to ensure correct
16922 /* Calculate stack offsets. These are used to calculate register elimination
16923 offsets and in prologue/epilogue code. Also calculates which registers
16924 should be saved. */
16926 static arm_stack_offsets *
16927 arm_get_frame_offsets (void)
16929 struct arm_stack_offsets *offsets;
16930 unsigned long func_type;
16934 HOST_WIDE_INT frame_size;
16937 offsets = &cfun->machine->stack_offsets;
16939 /* We need to know if we are a leaf function. Unfortunately, it
16940 is possible to be called after start_sequence has been called,
16941 which causes get_insns to return the insns for the sequence,
16942 not the function, which will cause leaf_function_p to return
16943 the incorrect result.
16945 to know about leaf functions once reload has completed, and the
16946 frame size cannot be changed after that time, so we can safely
16947 use the cached value. */
16949 if (reload_completed)
16952 /* Initially this is the size of the local variables. It will translated
16953 into an offset once we have determined the size of preceding data. */
16954 frame_size = ROUND_UP_WORD (get_frame_size ());
16956 leaf = leaf_function_p ();
16958 /* Space for variadic functions. */
16959 offsets->saved_args = crtl->args.pretend_args_size;
16961 /* In Thumb mode this is incorrect, but never used. */
16962 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0) +
16963 arm_compute_static_chain_stack_bytes();
16967 unsigned int regno;
16969 offsets->saved_regs_mask = arm_compute_save_reg_mask ();
16970 core_saved = bit_count (offsets->saved_regs_mask) * 4;
16971 saved = core_saved;
16973 /* We know that SP will be doubleword aligned on entry, and we must
16974 preserve that condition at any subroutine call. We also require the
16975 soft frame pointer to be doubleword aligned. */
16977 if (TARGET_REALLY_IWMMXT)
16979 /* Check for the call-saved iWMMXt registers. */
16980 for (regno = FIRST_IWMMXT_REGNUM;
16981 regno <= LAST_IWMMXT_REGNUM;
16983 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
16987 func_type = arm_current_func_type ();
16988 /* Space for saved VFP registers. */
16989 if (! IS_VOLATILE (func_type)
16990 && TARGET_HARD_FLOAT && TARGET_VFP)
16991 saved += arm_get_vfp_saved_size ();
16993 else /* TARGET_THUMB1 */
16995 offsets->saved_regs_mask = thumb1_compute_save_reg_mask ();
16996 core_saved = bit_count (offsets->saved_regs_mask) * 4;
16997 saved = core_saved;
16998 if (TARGET_BACKTRACE)
17002 /* Saved registers include the stack frame. */
17003 offsets->saved_regs = offsets->saved_args + saved +
17004 arm_compute_static_chain_stack_bytes();
17005 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
17006 /* A leaf function does not need any stack alignment if it has nothing
17008 if (leaf && frame_size == 0
17009 /* However if it calls alloca(), we have a dynamically allocated
17010 block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
17011 && ! cfun->calls_alloca)
17013 offsets->outgoing_args = offsets->soft_frame;
17014 offsets->locals_base = offsets->soft_frame;
17018 /* Ensure SFP has the correct alignment. */
17019 if (ARM_DOUBLEWORD_ALIGN
17020 && (offsets->soft_frame & 7))
17022 offsets->soft_frame += 4;
17023 /* Try to align stack by pushing an extra reg. Don't bother doing this
17024 when there is a stack frame as the alignment will be rolled into
17025 the normal stack adjustment. */
17026 if (frame_size + crtl->outgoing_args_size == 0)
17030 /* If it is safe to use r3, then do so. This sometimes
17031 generates better code on Thumb-2 by avoiding the need to
17032 use 32-bit push/pop instructions. */
17033 if (! any_sibcall_uses_r3 ()
17034 && arm_size_return_regs () <= 12
17035 && (offsets->saved_regs_mask & (1 << 3)) == 0)
17040 for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
17042 /* Avoid fixed registers; they may be changed at
17043 arbitrary times so it's unsafe to restore them
17044 during the epilogue. */
17046 && (offsets->saved_regs_mask & (1 << i)) == 0)
17055 offsets->saved_regs += 4;
17056 offsets->saved_regs_mask |= (1 << reg);
17061 offsets->locals_base = offsets->soft_frame + frame_size;
17062 offsets->outgoing_args = (offsets->locals_base
17063 + crtl->outgoing_args_size);
17065 if (ARM_DOUBLEWORD_ALIGN)
17067 /* Ensure SP remains doubleword aligned. */
17068 if (offsets->outgoing_args & 7)
17069 offsets->outgoing_args += 4;
17070 gcc_assert (!(offsets->outgoing_args & 7));
17077 /* Calculate the relative offsets for the different stack pointers. Positive
17078 offsets are in the direction of stack growth. */
17081 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
17083 arm_stack_offsets *offsets;
17085 offsets = arm_get_frame_offsets ();
17087 /* OK, now we have enough information to compute the distances.
17088 There must be an entry in these switch tables for each pair
17089 of registers in ELIMINABLE_REGS, even if some of the entries
17090 seem to be redundant or useless. */
17093 case ARG_POINTER_REGNUM:
17096 case THUMB_HARD_FRAME_POINTER_REGNUM:
17099 case FRAME_POINTER_REGNUM:
17100 /* This is the reverse of the soft frame pointer
17101 to hard frame pointer elimination below. */
17102 return offsets->soft_frame - offsets->saved_args;
17104 case ARM_HARD_FRAME_POINTER_REGNUM:
17105 /* This is only non-zero in the case where the static chain register
17106 is stored above the frame. */
17107 return offsets->frame - offsets->saved_args - 4;
17109 case STACK_POINTER_REGNUM:
17110 /* If nothing has been pushed on the stack at all
17111 then this will return -4. This *is* correct! */
17112 return offsets->outgoing_args - (offsets->saved_args + 4);
17115 gcc_unreachable ();
17117 gcc_unreachable ();
17119 case FRAME_POINTER_REGNUM:
17122 case THUMB_HARD_FRAME_POINTER_REGNUM:
17125 case ARM_HARD_FRAME_POINTER_REGNUM:
17126 /* The hard frame pointer points to the top entry in the
17127 stack frame. The soft frame pointer to the bottom entry
17128 in the stack frame. If there is no stack frame at all,
17129 then they are identical. */
17131 return offsets->frame - offsets->soft_frame;
17133 case STACK_POINTER_REGNUM:
17134 return offsets->outgoing_args - offsets->soft_frame;
17137 gcc_unreachable ();
17139 gcc_unreachable ();
17142 /* You cannot eliminate from the stack pointer.
17143 In theory you could eliminate from the hard frame
17144 pointer to the stack pointer, but this will never
17145 happen, since if a stack frame is not needed the
17146 hard frame pointer will never be used. */
17147 gcc_unreachable ();
17151 /* Given FROM and TO register numbers, say whether this elimination is
17152 allowed. Frame pointer elimination is automatically handled.
17154 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
17155 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
17156 pointer, we must eliminate FRAME_POINTER_REGNUM into
17157 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
17158 ARG_POINTER_REGNUM. */
17161 arm_can_eliminate (const int from, const int to)
17163 return ((to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) ? false :
17164 (to == STACK_POINTER_REGNUM && frame_pointer_needed) ? false :
17165 (to == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? false :
17166 (to == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? false :
17170 /* Emit RTL to save coprocessor registers on function entry. Returns the
17171 number of bytes pushed. */
17174 arm_save_coproc_regs(void)
17176 int saved_size = 0;
17178 unsigned start_reg;
17181 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
17182 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
17184 insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
17185 insn = gen_rtx_MEM (V2SImode, insn);
17186 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
17187 RTX_FRAME_RELATED_P (insn) = 1;
17191 if (TARGET_HARD_FLOAT && TARGET_VFP)
17193 start_reg = FIRST_VFP_REGNUM;
17195 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
17197 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
17198 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
17200 if (start_reg != reg)
17201 saved_size += vfp_emit_fstmd (start_reg,
17202 (reg - start_reg) / 2);
17203 start_reg = reg + 2;
17206 if (start_reg != reg)
17207 saved_size += vfp_emit_fstmd (start_reg,
17208 (reg - start_reg) / 2);
17214 /* Set the Thumb frame pointer from the stack pointer. */
17217 thumb_set_frame_pointer (arm_stack_offsets *offsets)
17219 HOST_WIDE_INT amount;
17222 amount = offsets->outgoing_args - offsets->locals_base;
17224 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
17225 stack_pointer_rtx, GEN_INT (amount)));
17228 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
17229 /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1
17230 expects the first two operands to be the same. */
17233 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
17235 hard_frame_pointer_rtx));
17239 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
17240 hard_frame_pointer_rtx,
17241 stack_pointer_rtx));
17243 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
17244 plus_constant (Pmode, stack_pointer_rtx, amount));
17245 RTX_FRAME_RELATED_P (dwarf) = 1;
17246 add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
17249 RTX_FRAME_RELATED_P (insn) = 1;
17252 /* Generate the prologue instructions for entry into an ARM or Thumb-2
17255 arm_expand_prologue (void)
17260 unsigned long live_regs_mask;
17261 unsigned long func_type;
17263 int saved_pretend_args = 0;
17264 int saved_regs = 0;
17265 unsigned HOST_WIDE_INT args_to_push;
17266 arm_stack_offsets *offsets;
17268 func_type = arm_current_func_type ();
17270 /* Naked functions don't have prologues. */
17271 if (IS_NAKED (func_type))
17274 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
17275 args_to_push = crtl->args.pretend_args_size;
17277 /* Compute which register we will have to save onto the stack. */
17278 offsets = arm_get_frame_offsets ();
17279 live_regs_mask = offsets->saved_regs_mask;
17281 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
17283 if (IS_STACKALIGN (func_type))
17287 /* Handle a word-aligned stack pointer. We generate the following:
17292 <save and restore r0 in normal prologue/epilogue>
17296 The unwinder doesn't need to know about the stack realignment.
17297 Just tell it we saved SP in r0. */
17298 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
17300 r0 = gen_rtx_REG (SImode, 0);
17301 r1 = gen_rtx_REG (SImode, 1);
17303 insn = emit_insn (gen_movsi (r0, stack_pointer_rtx));
17304 RTX_FRAME_RELATED_P (insn) = 1;
17305 add_reg_note (insn, REG_CFA_REGISTER, NULL);
17307 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
17309 /* ??? The CFA changes here, which may cause GDB to conclude that it
17310 has entered a different function. That said, the unwind info is
17311 correct, individually, before and after this instruction because
17312 we've described the save of SP, which will override the default
17313 handling of SP as restoring from the CFA. */
17314 emit_insn (gen_movsi (stack_pointer_rtx, r1));
17317 /* For APCS frames, if IP register is clobbered
17318 when creating frame, save that register in a special
17320 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
17322 if (IS_INTERRUPT (func_type))
17324 /* Interrupt functions must not corrupt any registers.
17325 Creating a frame pointer however, corrupts the IP
17326 register, so we must push it first. */
17327 emit_multi_reg_push (1 << IP_REGNUM);
17329 /* Do not set RTX_FRAME_RELATED_P on this insn.
17330 The dwarf stack unwinding code only wants to see one
17331 stack decrement per function, and this is not it. If
17332 this instruction is labeled as being part of the frame
17333 creation sequence then dwarf2out_frame_debug_expr will
17334 die when it encounters the assignment of IP to FP
17335 later on, since the use of SP here establishes SP as
17336 the CFA register and not IP.
17338 Anyway this instruction is not really part of the stack
17339 frame creation although it is part of the prologue. */
17341 else if (IS_NESTED (func_type))
17343 /* The Static chain register is the same as the IP register
17344 used as a scratch register during stack frame creation.
17345 To get around this need to find somewhere to store IP
17346 whilst the frame is being created. We try the following
17349 1. The last argument register.
17350 2. A slot on the stack above the frame. (This only
17351 works if the function is not a varargs function).
17352 3. Register r3, after pushing the argument registers
17355 Note - we only need to tell the dwarf2 backend about the SP
17356 adjustment in the second variant; the static chain register
17357 doesn't need to be unwound, as it doesn't contain a value
17358 inherited from the caller. */
17360 if (df_regs_ever_live_p (3) == false)
17361 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
17362 else if (args_to_push == 0)
17366 gcc_assert(arm_compute_static_chain_stack_bytes() == 4);
17369 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
17370 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
17373 /* Just tell the dwarf backend that we adjusted SP. */
17374 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
17375 plus_constant (Pmode, stack_pointer_rtx,
17377 RTX_FRAME_RELATED_P (insn) = 1;
17378 add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
17382 /* Store the args on the stack. */
17383 if (cfun->machine->uses_anonymous_args)
17384 insn = emit_multi_reg_push
17385 ((0xf0 >> (args_to_push / 4)) & 0xf);
17388 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
17389 GEN_INT (- args_to_push)));
17391 RTX_FRAME_RELATED_P (insn) = 1;
17393 saved_pretend_args = 1;
17394 fp_offset = args_to_push;
17397 /* Now reuse r3 to preserve IP. */
17398 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
17402 insn = emit_set_insn (ip_rtx,
17403 plus_constant (Pmode, stack_pointer_rtx,
17405 RTX_FRAME_RELATED_P (insn) = 1;
17410 /* Push the argument registers, or reserve space for them. */
17411 if (cfun->machine->uses_anonymous_args)
17412 insn = emit_multi_reg_push
17413 ((0xf0 >> (args_to_push / 4)) & 0xf);
17416 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
17417 GEN_INT (- args_to_push)));
17418 RTX_FRAME_RELATED_P (insn) = 1;
17421 /* If this is an interrupt service routine, and the link register
17422 is going to be pushed, and we're not generating extra
17423 push of IP (needed when frame is needed and frame layout if apcs),
17424 subtracting four from LR now will mean that the function return
17425 can be done with a single instruction. */
17426 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
17427 && (live_regs_mask & (1 << LR_REGNUM)) != 0
17428 && !(frame_pointer_needed && TARGET_APCS_FRAME)
17431 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
17433 emit_set_insn (lr, plus_constant (SImode, lr, -4));
17436 if (live_regs_mask)
17438 saved_regs += bit_count (live_regs_mask) * 4;
17439 if (optimize_size && !frame_pointer_needed
17440 && saved_regs == offsets->saved_regs - offsets->saved_args)
17442 /* If no coprocessor registers are being pushed and we don't have
17443 to worry about a frame pointer then push extra registers to
17444 create the stack frame. This is done is a way that does not
17445 alter the frame layout, so is independent of the epilogue. */
17449 while (n < 8 && (live_regs_mask & (1 << n)) == 0)
17451 frame = offsets->outgoing_args - (offsets->saved_args + saved_regs);
17452 if (frame && n * 4 >= frame)
17455 live_regs_mask |= (1 << n) - 1;
17456 saved_regs += frame;
17460 if (current_tune->prefer_ldrd_strd
17461 && !optimize_function_for_size_p (cfun))
17465 thumb2_emit_strd_push (live_regs_mask);
17469 insn = emit_multi_reg_push (live_regs_mask);
17470 RTX_FRAME_RELATED_P (insn) = 1;
17475 insn = emit_multi_reg_push (live_regs_mask);
17476 RTX_FRAME_RELATED_P (insn) = 1;
17480 if (! IS_VOLATILE (func_type))
17481 saved_regs += arm_save_coproc_regs ();
17483 if (frame_pointer_needed && TARGET_ARM)
17485 /* Create the new frame pointer. */
17486 if (TARGET_APCS_FRAME)
17488 insn = GEN_INT (-(4 + args_to_push + fp_offset));
17489 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
17490 RTX_FRAME_RELATED_P (insn) = 1;
17492 if (IS_NESTED (func_type))
17494 /* Recover the static chain register. */
17495 if (!df_regs_ever_live_p (3)
17496 || saved_pretend_args)
17497 insn = gen_rtx_REG (SImode, 3);
17498 else /* if (crtl->args.pretend_args_size == 0) */
17500 insn = plus_constant (Pmode, hard_frame_pointer_rtx, 4);
17501 insn = gen_frame_mem (SImode, insn);
17503 emit_set_insn (ip_rtx, insn);
17504 /* Add a USE to stop propagate_one_insn() from barfing. */
17505 emit_insn (gen_force_register_use (ip_rtx));
17510 insn = GEN_INT (saved_regs - 4);
17511 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
17512 stack_pointer_rtx, insn));
17513 RTX_FRAME_RELATED_P (insn) = 1;
17517 if (flag_stack_usage_info)
17518 current_function_static_stack_size
17519 = offsets->outgoing_args - offsets->saved_args;
17521 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
17523 /* This add can produce multiple insns for a large constant, so we
17524 need to get tricky. */
17525 rtx last = get_last_insn ();
17527 amount = GEN_INT (offsets->saved_args + saved_regs
17528 - offsets->outgoing_args);
17530 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
17534 last = last ? NEXT_INSN (last) : get_insns ();
17535 RTX_FRAME_RELATED_P (last) = 1;
17537 while (last != insn);
17539 /* If the frame pointer is needed, emit a special barrier that
17540 will prevent the scheduler from moving stores to the frame
17541 before the stack adjustment. */
17542 if (frame_pointer_needed)
17543 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
17544 hard_frame_pointer_rtx));
17548 if (frame_pointer_needed && TARGET_THUMB2)
17549 thumb_set_frame_pointer (offsets);
17551 if (flag_pic && arm_pic_register != INVALID_REGNUM)
17553 unsigned long mask;
17555 mask = live_regs_mask;
17556 mask &= THUMB2_WORK_REGS;
17557 if (!IS_NESTED (func_type))
17558 mask |= (1 << IP_REGNUM);
17559 arm_load_pic_register (mask);
17562 /* If we are profiling, make sure no instructions are scheduled before
17563 the call to mcount. Similarly if the user has requested no
17564 scheduling in the prolog. Similarly if we want non-call exceptions
17565 using the EABI unwinder, to prevent faulting instructions from being
17566 swapped with a stack adjustment. */
17567 if (crtl->profile || !TARGET_SCHED_PROLOG
17568 || (arm_except_unwind_info (&global_options) == UI_TARGET
17569 && cfun->can_throw_non_call_exceptions))
17570 emit_insn (gen_blockage ());
17572 /* If the link register is being kept alive, with the return address in it,
17573 then make sure that it does not get reused by the ce2 pass. */
17574 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
17575 cfun->machine->lr_save_eliminated = 1;
17578 /* Print condition code to STREAM. Helper function for arm_print_operand. */
17580 arm_print_condition (FILE *stream)
17582 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
17584 /* Branch conversion is not implemented for Thumb-2. */
17587 output_operand_lossage ("predicated Thumb instruction");
17590 if (current_insn_predicate != NULL)
17592 output_operand_lossage
17593 ("predicated instruction in conditional sequence");
17597 fputs (arm_condition_codes[arm_current_cc], stream);
17599 else if (current_insn_predicate)
17601 enum arm_cond_code code;
17605 output_operand_lossage ("predicated Thumb instruction");
17609 code = get_arm_condition_code (current_insn_predicate);
17610 fputs (arm_condition_codes[code], stream);
17615 /* If CODE is 'd', then the X is a condition operand and the instruction
17616 should only be executed if the condition is true.
17617 if CODE is 'D', then the X is a condition operand and the instruction
17618 should only be executed if the condition is false: however, if the mode
17619 of the comparison is CCFPEmode, then always execute the instruction -- we
17620 do this because in these circumstances !GE does not necessarily imply LT;
17621 in these cases the instruction pattern will take care to make sure that
17622 an instruction containing %d will follow, thereby undoing the effects of
17623 doing this instruction unconditionally.
17624 If CODE is 'N' then X is a floating point operand that must be negated
17626 If CODE is 'B' then output a bitwise inverted value of X (a const int).
17627 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
17629 arm_print_operand (FILE *stream, rtx x, int code)
17634 fputs (ASM_COMMENT_START, stream);
17638 fputs (user_label_prefix, stream);
17642 fputs (REGISTER_PREFIX, stream);
17646 arm_print_condition (stream);
17650 /* Nothing in unified syntax, otherwise the current condition code. */
17651 if (!TARGET_UNIFIED_ASM)
17652 arm_print_condition (stream);
17656 /* The current condition code in unified syntax, otherwise nothing. */
17657 if (TARGET_UNIFIED_ASM)
17658 arm_print_condition (stream);
17662 /* The current condition code for a condition code setting instruction.
17663 Preceded by 's' in unified syntax, otherwise followed by 's'. */
17664 if (TARGET_UNIFIED_ASM)
17666 fputc('s', stream);
17667 arm_print_condition (stream);
17671 arm_print_condition (stream);
17672 fputc('s', stream);
17677 /* If the instruction is conditionally executed then print
17678 the current condition code, otherwise print 's'. */
17679 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
17680 if (current_insn_predicate)
17681 arm_print_condition (stream);
17683 fputc('s', stream);
17686 /* %# is a "break" sequence. It doesn't output anything, but is used to
17687 separate e.g. operand numbers from following text, if that text consists
17688 of further digits which we don't want to be part of the operand
17696 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
17697 r = real_value_negate (&r);
17698 fprintf (stream, "%s", fp_const_from_val (&r));
17702 /* An integer or symbol address without a preceding # sign. */
17704 switch (GET_CODE (x))
17707 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
17711 output_addr_const (stream, x);
17715 if (GET_CODE (XEXP (x, 0)) == PLUS
17716 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
17718 output_addr_const (stream, x);
17721 /* Fall through. */
17724 output_operand_lossage ("Unsupported operand for code '%c'", code);
17728 /* An integer that we want to print in HEX. */
17730 switch (GET_CODE (x))
17733 fprintf (stream, "#" HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
17737 output_operand_lossage ("Unsupported operand for code '%c'", code);
17742 if (CONST_INT_P (x))
17745 val = ARM_SIGN_EXTEND (~INTVAL (x));
17746 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
17750 putc ('~', stream);
17751 output_addr_const (stream, x);
17756 /* The low 16 bits of an immediate constant. */
17757 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
17761 fprintf (stream, "%s", arithmetic_instr (x, 1));
17765 fprintf (stream, "%s", arithmetic_instr (x, 0));
17773 shift = shift_op (x, &val);
17777 fprintf (stream, ", %s ", shift);
17779 arm_print_operand (stream, XEXP (x, 1), 0);
17781 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
17786 /* An explanation of the 'Q', 'R' and 'H' register operands:
17788 In a pair of registers containing a DI or DF value the 'Q'
17789 operand returns the register number of the register containing
17790 the least significant part of the value. The 'R' operand returns
17791 the register number of the register containing the most
17792 significant part of the value.
17794 The 'H' operand returns the higher of the two register numbers.
17795 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
17796 same as the 'Q' operand, since the most significant part of the
17797 value is held in the lower number register. The reverse is true
17798 on systems where WORDS_BIG_ENDIAN is false.
17800 The purpose of these operands is to distinguish between cases
17801 where the endian-ness of the values is important (for example
17802 when they are added together), and cases where the endian-ness
17803 is irrelevant, but the order of register operations is important.
17804 For example when loading a value from memory into a register
17805 pair, the endian-ness does not matter. Provided that the value
17806 from the lower memory address is put into the lower numbered
17807 register, and the value from the higher address is put into the
17808 higher numbered register, the load will work regardless of whether
17809 the value being loaded is big-wordian or little-wordian. The
17810 order of the two register loads can matter however, if the address
17811 of the memory location is actually held in one of the registers
17812 being overwritten by the load.
17814 The 'Q' and 'R' constraints are also available for 64-bit
17817 if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
17819 rtx part = gen_lowpart (SImode, x);
17820 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
17824 if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
17826 output_operand_lossage ("invalid operand for code '%c'", code);
17830 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
17834 if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
17836 enum machine_mode mode = GET_MODE (x);
17839 if (mode == VOIDmode)
17841 part = gen_highpart_mode (SImode, mode, x);
17842 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
17846 if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
17848 output_operand_lossage ("invalid operand for code '%c'", code);
17852 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
17856 if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
17858 output_operand_lossage ("invalid operand for code '%c'", code);
17862 asm_fprintf (stream, "%r", REGNO (x) + 1);
17866 if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
17868 output_operand_lossage ("invalid operand for code '%c'", code);
17872 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2));
17876 if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
17878 output_operand_lossage ("invalid operand for code '%c'", code);
17882 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3));
17886 asm_fprintf (stream, "%r",
17887 REG_P (XEXP (x, 0))
17888 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
17892 asm_fprintf (stream, "{%r-%r}",
17894 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
17897 /* Like 'M', but writing doubleword vector registers, for use by Neon
17901 int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2;
17902 int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2;
17904 asm_fprintf (stream, "{d%d}", regno);
17906 asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1);
17911 /* CONST_TRUE_RTX means always -- that's the default. */
17912 if (x == const_true_rtx)
17915 if (!COMPARISON_P (x))
17917 output_operand_lossage ("invalid operand for code '%c'", code);
17921 fputs (arm_condition_codes[get_arm_condition_code (x)],
17926 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
17927 want to do that. */
17928 if (x == const_true_rtx)
17930 output_operand_lossage ("instruction never executed");
17933 if (!COMPARISON_P (x))
17935 output_operand_lossage ("invalid operand for code '%c'", code);
17939 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
17940 (get_arm_condition_code (x))],
17950 /* Former Maverick support, removed after GCC-4.7. */
17951 output_operand_lossage ("obsolete Maverick format code '%c'", code);
17956 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
17957 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
17958 /* Bad value for wCG register number. */
17960 output_operand_lossage ("invalid operand for code '%c'", code);
17965 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
17968 /* Print an iWMMXt control register name. */
17970 if (!CONST_INT_P (x)
17972 || INTVAL (x) >= 16)
17973 /* Bad value for wC register number. */
17975 output_operand_lossage ("invalid operand for code '%c'", code);
17981 static const char * wc_reg_names [16] =
17983 "wCID", "wCon", "wCSSF", "wCASF",
17984 "wC4", "wC5", "wC6", "wC7",
17985 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
17986 "wC12", "wC13", "wC14", "wC15"
17989 fputs (wc_reg_names [INTVAL (x)], stream);
17993 /* Print the high single-precision register of a VFP double-precision
17997 int mode = GET_MODE (x);
18000 if (GET_MODE_SIZE (mode) != 8 || !REG_P (x))
18002 output_operand_lossage ("invalid operand for code '%c'", code);
18007 if (!VFP_REGNO_OK_FOR_DOUBLE (regno))
18009 output_operand_lossage ("invalid operand for code '%c'", code);
18013 fprintf (stream, "s%d", regno - FIRST_VFP_REGNUM + 1);
18017 /* Print a VFP/Neon double precision or quad precision register name. */
18021 int mode = GET_MODE (x);
18022 int is_quad = (code == 'q');
18025 if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8))
18027 output_operand_lossage ("invalid operand for code '%c'", code);
18032 || !IS_VFP_REGNUM (REGNO (x)))
18034 output_operand_lossage ("invalid operand for code '%c'", code);
18039 if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno))
18040 || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno)))
18042 output_operand_lossage ("invalid operand for code '%c'", code);
18046 fprintf (stream, "%c%d", is_quad ? 'q' : 'd',
18047 (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1));
18051 /* These two codes print the low/high doubleword register of a Neon quad
18052 register, respectively. For pair-structure types, can also print
18053 low/high quadword registers. */
18057 int mode = GET_MODE (x);
18060 if ((GET_MODE_SIZE (mode) != 16
18061 && GET_MODE_SIZE (mode) != 32) || !REG_P (x))
18063 output_operand_lossage ("invalid operand for code '%c'", code);
18068 if (!NEON_REGNO_OK_FOR_QUAD (regno))
18070 output_operand_lossage ("invalid operand for code '%c'", code);
18074 if (GET_MODE_SIZE (mode) == 16)
18075 fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1)
18076 + (code == 'f' ? 1 : 0));
18078 fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2)
18079 + (code == 'f' ? 1 : 0));
18083 /* Print a VFPv3 floating-point constant, represented as an integer
18087 int index = vfp3_const_double_index (x);
18088 gcc_assert (index != -1);
18089 fprintf (stream, "%d", index);
18093 /* Print bits representing opcode features for Neon.
18095 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
18096 and polynomials as unsigned.
18098 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
18100 Bit 2 is 1 for rounding functions, 0 otherwise. */
18102 /* Identify the type as 's', 'u', 'p' or 'f'. */
18105 HOST_WIDE_INT bits = INTVAL (x);
18106 fputc ("uspf"[bits & 3], stream);
18110 /* Likewise, but signed and unsigned integers are both 'i'. */
18113 HOST_WIDE_INT bits = INTVAL (x);
18114 fputc ("iipf"[bits & 3], stream);
18118 /* As for 'T', but emit 'u' instead of 'p'. */
18121 HOST_WIDE_INT bits = INTVAL (x);
18122 fputc ("usuf"[bits & 3], stream);
18126 /* Bit 2: rounding (vs none). */
18129 HOST_WIDE_INT bits = INTVAL (x);
18130 fputs ((bits & 4) != 0 ? "r" : "", stream);
18134 /* Memory operand for vld1/vst1 instruction. */
18138 bool postinc = FALSE;
18139 unsigned align, memsize, align_bits;
18141 gcc_assert (MEM_P (x));
18142 addr = XEXP (x, 0);
18143 if (GET_CODE (addr) == POST_INC)
18146 addr = XEXP (addr, 0);
18148 asm_fprintf (stream, "[%r", REGNO (addr));
18150 /* We know the alignment of this access, so we can emit a hint in the
18151 instruction (for some alignments) as an aid to the memory subsystem
18153 align = MEM_ALIGN (x) >> 3;
18154 memsize = MEM_SIZE (x);
18156 /* Only certain alignment specifiers are supported by the hardware. */
18157 if (memsize == 32 && (align % 32) == 0)
18159 else if ((memsize == 16 || memsize == 32) && (align % 16) == 0)
18161 else if (memsize >= 8 && (align % 8) == 0)
18166 if (align_bits != 0)
18167 asm_fprintf (stream, ":%d", align_bits);
18169 asm_fprintf (stream, "]");
18172 fputs("!", stream);
18180 gcc_assert (MEM_P (x));
18181 addr = XEXP (x, 0);
18182 gcc_assert (REG_P (addr));
18183 asm_fprintf (stream, "[%r]", REGNO (addr));
18187 /* Translate an S register number into a D register number and element index. */
18190 int mode = GET_MODE (x);
18193 if (GET_MODE_SIZE (mode) != 4 || !REG_P (x))
18195 output_operand_lossage ("invalid operand for code '%c'", code);
18200 if (!VFP_REGNO_OK_FOR_SINGLE (regno))
18202 output_operand_lossage ("invalid operand for code '%c'", code);
18206 regno = regno - FIRST_VFP_REGNUM;
18207 fprintf (stream, "d%d[%d]", regno / 2, regno % 2);
18212 gcc_assert (CONST_DOUBLE_P (x));
18213 fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x));
18216 /* Register specifier for vld1.16/vst1.16. Translate the S register
18217 number into a D register number and element index. */
18220 int mode = GET_MODE (x);
18223 if (GET_MODE_SIZE (mode) != 2 || !REG_P (x))
18225 output_operand_lossage ("invalid operand for code '%c'", code);
18230 if (!VFP_REGNO_OK_FOR_SINGLE (regno))
18232 output_operand_lossage ("invalid operand for code '%c'", code);
18236 regno = regno - FIRST_VFP_REGNUM;
18237 fprintf (stream, "d%d[%d]", regno/2, ((regno % 2) ? 2 : 0));
18244 output_operand_lossage ("missing operand");
18248 switch (GET_CODE (x))
18251 asm_fprintf (stream, "%r", REGNO (x));
18255 output_memory_reference_mode = GET_MODE (x);
18256 output_address (XEXP (x, 0));
18263 real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
18264 sizeof (fpstr), 0, 1);
18265 fprintf (stream, "#%s", fpstr);
18268 fprintf (stream, "#%s", fp_immediate_constant (x));
18272 gcc_assert (GET_CODE (x) != NEG);
18273 fputc ('#', stream);
18274 if (GET_CODE (x) == HIGH)
18276 fputs (":lower16:", stream);
18280 output_addr_const (stream, x);
18286 /* Target hook for printing a memory address. */
18288 arm_print_operand_address (FILE *stream, rtx x)
18292 int is_minus = GET_CODE (x) == MINUS;
18295 asm_fprintf (stream, "[%r]", REGNO (x));
18296 else if (GET_CODE (x) == PLUS || is_minus)
18298 rtx base = XEXP (x, 0);
18299 rtx index = XEXP (x, 1);
18300 HOST_WIDE_INT offset = 0;
18302 || (REG_P (index) && REGNO (index) == SP_REGNUM))
18304 /* Ensure that BASE is a register. */
18305 /* (one of them must be). */
18306 /* Also ensure the SP is not used as in index register. */
18311 switch (GET_CODE (index))
18314 offset = INTVAL (index);
18317 asm_fprintf (stream, "[%r, #%wd]",
18318 REGNO (base), offset);
18322 asm_fprintf (stream, "[%r, %s%r]",
18323 REGNO (base), is_minus ? "-" : "",
18333 asm_fprintf (stream, "[%r, %s%r",
18334 REGNO (base), is_minus ? "-" : "",
18335 REGNO (XEXP (index, 0)));
18336 arm_print_operand (stream, index, 'S');
18337 fputs ("]", stream);
18342 gcc_unreachable ();
18345 else if (GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_INC
18346 || GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_DEC)
18348 extern enum machine_mode output_memory_reference_mode;
18350 gcc_assert (REG_P (XEXP (x, 0)));
18352 if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC)
18353 asm_fprintf (stream, "[%r, #%s%d]!",
18354 REGNO (XEXP (x, 0)),
18355 GET_CODE (x) == PRE_DEC ? "-" : "",
18356 GET_MODE_SIZE (output_memory_reference_mode));
18358 asm_fprintf (stream, "[%r], #%s%d",
18359 REGNO (XEXP (x, 0)),
18360 GET_CODE (x) == POST_DEC ? "-" : "",
18361 GET_MODE_SIZE (output_memory_reference_mode));
18363 else if (GET_CODE (x) == PRE_MODIFY)
18365 asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0)));
18366 if (CONST_INT_P (XEXP (XEXP (x, 1), 1)))
18367 asm_fprintf (stream, "#%wd]!",
18368 INTVAL (XEXP (XEXP (x, 1), 1)));
18370 asm_fprintf (stream, "%r]!",
18371 REGNO (XEXP (XEXP (x, 1), 1)));
18373 else if (GET_CODE (x) == POST_MODIFY)
18375 asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0)));
18376 if (CONST_INT_P (XEXP (XEXP (x, 1), 1)))
18377 asm_fprintf (stream, "#%wd",
18378 INTVAL (XEXP (XEXP (x, 1), 1)));
18380 asm_fprintf (stream, "%r",
18381 REGNO (XEXP (XEXP (x, 1), 1)));
18383 else output_addr_const (stream, x);
18388 asm_fprintf (stream, "[%r]", REGNO (x));
18389 else if (GET_CODE (x) == POST_INC)
18390 asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0)));
18391 else if (GET_CODE (x) == PLUS)
18393 gcc_assert (REG_P (XEXP (x, 0)));
18394 if (CONST_INT_P (XEXP (x, 1)))
18395 asm_fprintf (stream, "[%r, #%wd]",
18396 REGNO (XEXP (x, 0)),
18397 INTVAL (XEXP (x, 1)));
18399 asm_fprintf (stream, "[%r, %r]",
18400 REGNO (XEXP (x, 0)),
18401 REGNO (XEXP (x, 1)));
18404 output_addr_const (stream, x);
18408 /* Target hook for indicating whether a punctuation character for
18409 TARGET_PRINT_OPERAND is valid. */
18411 arm_print_operand_punct_valid_p (unsigned char code)
18413 return (code == '@' || code == '|' || code == '.'
18414 || code == '(' || code == ')' || code == '#'
18415 || (TARGET_32BIT && (code == '?'))
18416 || (TARGET_THUMB2 && (code == '!'))
18417 || (TARGET_THUMB && (code == '_')));
18420 /* Target hook for assembling integer objects. The ARM version needs to
18421 handle word-sized values specially. */
18423 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
18425 enum machine_mode mode;
18427 if (size == UNITS_PER_WORD && aligned_p)
18429 fputs ("\t.word\t", asm_out_file);
18430 output_addr_const (asm_out_file, x);
18432 /* Mark symbols as position independent. We only do this in the
18433 .text segment, not in the .data segment. */
18434 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
18435 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
18437 /* See legitimize_pic_address for an explanation of the
18438 TARGET_VXWORKS_RTP check. */
18439 if (TARGET_VXWORKS_RTP
18440 || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
18441 fputs ("(GOT)", asm_out_file);
18443 fputs ("(GOTOFF)", asm_out_file);
18445 fputc ('\n', asm_out_file);
18449 mode = GET_MODE (x);
18451 if (arm_vector_mode_supported_p (mode))
18455 gcc_assert (GET_CODE (x) == CONST_VECTOR);
18457 units = CONST_VECTOR_NUNITS (x);
18458 size = GET_MODE_SIZE (GET_MODE_INNER (mode));
18460 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
18461 for (i = 0; i < units; i++)
18463 rtx elt = CONST_VECTOR_ELT (x, i);
18465 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
18468 for (i = 0; i < units; i++)
18470 rtx elt = CONST_VECTOR_ELT (x, i);
18471 REAL_VALUE_TYPE rval;
18473 REAL_VALUE_FROM_CONST_DOUBLE (rval, elt);
18476 (rval, GET_MODE_INNER (mode),
18477 i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT);
18483 return default_assemble_integer (x, size, aligned_p);
18487 arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
18491 if (!TARGET_AAPCS_BASED)
18494 default_named_section_asm_out_constructor
18495 : default_named_section_asm_out_destructor) (symbol, priority);
18499 /* Put these in the .init_array section, using a special relocation. */
18500 if (priority != DEFAULT_INIT_PRIORITY)
18503 sprintf (buf, "%s.%.5u",
18504 is_ctor ? ".init_array" : ".fini_array",
18506 s = get_section (buf, SECTION_WRITE, NULL_TREE);
18513 switch_to_section (s);
18514 assemble_align (POINTER_SIZE);
18515 fputs ("\t.word\t", asm_out_file);
18516 output_addr_const (asm_out_file, symbol);
18517 fputs ("(target1)\n", asm_out_file);
18520 /* Add a function to the list of static constructors. */
18523 arm_elf_asm_constructor (rtx symbol, int priority)
18525 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
18528 /* Add a function to the list of static destructors. */
18531 arm_elf_asm_destructor (rtx symbol, int priority)
18533 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
18536 /* A finite state machine takes care of noticing whether or not instructions
18537 can be conditionally executed, and thus decrease execution time and code
18538 size by deleting branch instructions. The fsm is controlled by
18539 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
18541 /* The state of the fsm controlling condition codes are:
18542 0: normal, do nothing special
18543 1: make ASM_OUTPUT_OPCODE not output this instruction
18544 2: make ASM_OUTPUT_OPCODE not output this instruction
18545 3: make instructions conditional
18546 4: make instructions conditional
18548 State transitions (state->state by whom under condition):
18549 0 -> 1 final_prescan_insn if the `target' is a label
18550 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
18551 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
18552 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
18553 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
18554 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
18555 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
18556 (the target insn is arm_target_insn).
18558 If the jump clobbers the conditions then we use states 2 and 4.
18560 A similar thing can be done with conditional return insns.
18562 XXX In case the `target' is an unconditional branch, this conditionalising
18563 of the instructions always reduces code size, but not always execution
18564 time. But then, I want to reduce the code size to somewhere near what
18565 /bin/cc produces. */
18567 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
18568 instructions. When a COND_EXEC instruction is seen the subsequent
18569 instructions are scanned so that multiple conditional instructions can be
18570 combined into a single IT block. arm_condexec_count and arm_condexec_mask
18571 specify the length and true/false mask for the IT block. These will be
18572 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
18574 /* Returns the index of the ARM condition code string in
18575 `arm_condition_codes', or ARM_NV if the comparison is invalid.
18576 COMPARISON should be an rtx like `(eq (...) (...))'. */
18579 maybe_get_arm_condition_code (rtx comparison)
18581 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
18582 enum arm_cond_code code;
18583 enum rtx_code comp_code = GET_CODE (comparison);
18585 if (GET_MODE_CLASS (mode) != MODE_CC)
18586 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
18587 XEXP (comparison, 1));
18591 case CC_DNEmode: code = ARM_NE; goto dominance;
18592 case CC_DEQmode: code = ARM_EQ; goto dominance;
18593 case CC_DGEmode: code = ARM_GE; goto dominance;
18594 case CC_DGTmode: code = ARM_GT; goto dominance;
18595 case CC_DLEmode: code = ARM_LE; goto dominance;
18596 case CC_DLTmode: code = ARM_LT; goto dominance;
18597 case CC_DGEUmode: code = ARM_CS; goto dominance;
18598 case CC_DGTUmode: code = ARM_HI; goto dominance;
18599 case CC_DLEUmode: code = ARM_LS; goto dominance;
18600 case CC_DLTUmode: code = ARM_CC;
18603 if (comp_code == EQ)
18604 return ARM_INVERSE_CONDITION_CODE (code);
18605 if (comp_code == NE)
18612 case NE: return ARM_NE;
18613 case EQ: return ARM_EQ;
18614 case GE: return ARM_PL;
18615 case LT: return ARM_MI;
18616 default: return ARM_NV;
18622 case NE: return ARM_NE;
18623 case EQ: return ARM_EQ;
18624 default: return ARM_NV;
18630 case NE: return ARM_MI;
18631 case EQ: return ARM_PL;
18632 default: return ARM_NV;
18637 /* We can handle all cases except UNEQ and LTGT. */
18640 case GE: return ARM_GE;
18641 case GT: return ARM_GT;
18642 case LE: return ARM_LS;
18643 case LT: return ARM_MI;
18644 case NE: return ARM_NE;
18645 case EQ: return ARM_EQ;
18646 case ORDERED: return ARM_VC;
18647 case UNORDERED: return ARM_VS;
18648 case UNLT: return ARM_LT;
18649 case UNLE: return ARM_LE;
18650 case UNGT: return ARM_HI;
18651 case UNGE: return ARM_PL;
18652 /* UNEQ and LTGT do not have a representation. */
18653 case UNEQ: /* Fall through. */
18654 case LTGT: /* Fall through. */
18655 default: return ARM_NV;
18661 case NE: return ARM_NE;
18662 case EQ: return ARM_EQ;
18663 case GE: return ARM_LE;
18664 case GT: return ARM_LT;
18665 case LE: return ARM_GE;
18666 case LT: return ARM_GT;
18667 case GEU: return ARM_LS;
18668 case GTU: return ARM_CC;
18669 case LEU: return ARM_CS;
18670 case LTU: return ARM_HI;
18671 default: return ARM_NV;
18677 case LTU: return ARM_CS;
18678 case GEU: return ARM_CC;
18679 default: return ARM_NV;
18685 case NE: return ARM_NE;
18686 case EQ: return ARM_EQ;
18687 case GEU: return ARM_CS;
18688 case GTU: return ARM_HI;
18689 case LEU: return ARM_LS;
18690 case LTU: return ARM_CC;
18691 default: return ARM_NV;
18697 case GE: return ARM_GE;
18698 case LT: return ARM_LT;
18699 case GEU: return ARM_CS;
18700 case LTU: return ARM_CC;
18701 default: return ARM_NV;
18707 case NE: return ARM_NE;
18708 case EQ: return ARM_EQ;
18709 case GE: return ARM_GE;
18710 case GT: return ARM_GT;
18711 case LE: return ARM_LE;
18712 case LT: return ARM_LT;
18713 case GEU: return ARM_CS;
18714 case GTU: return ARM_HI;
18715 case LEU: return ARM_LS;
18716 case LTU: return ARM_CC;
18717 default: return ARM_NV;
18720 default: gcc_unreachable ();
18724 /* Like maybe_get_arm_condition_code, but never return ARM_NV. */
18725 static enum arm_cond_code
18726 get_arm_condition_code (rtx comparison)
18728 enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
18729 gcc_assert (code != ARM_NV);
18733 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
18736 thumb2_final_prescan_insn (rtx insn)
18738 rtx first_insn = insn;
18739 rtx body = PATTERN (insn);
18741 enum arm_cond_code code;
18745 /* Remove the previous insn from the count of insns to be output. */
18746 if (arm_condexec_count)
18747 arm_condexec_count--;
18749 /* Nothing to do if we are already inside a conditional block. */
18750 if (arm_condexec_count)
18753 if (GET_CODE (body) != COND_EXEC)
18756 /* Conditional jumps are implemented directly. */
18760 predicate = COND_EXEC_TEST (body);
18761 arm_current_cc = get_arm_condition_code (predicate);
18763 n = get_attr_ce_count (insn);
18764 arm_condexec_count = 1;
18765 arm_condexec_mask = (1 << n) - 1;
18766 arm_condexec_masklen = n;
18767 /* See if subsequent instructions can be combined into the same block. */
18770 insn = next_nonnote_insn (insn);
18772 /* Jumping into the middle of an IT block is illegal, so a label or
18773 barrier terminates the block. */
18774 if (!NONJUMP_INSN_P (insn) && !JUMP_P (insn))
18777 body = PATTERN (insn);
18778 /* USE and CLOBBER aren't really insns, so just skip them. */
18779 if (GET_CODE (body) == USE
18780 || GET_CODE (body) == CLOBBER)
18783 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
18784 if (GET_CODE (body) != COND_EXEC)
18786 /* Allow up to 4 conditionally executed instructions in a block. */
18787 n = get_attr_ce_count (insn);
18788 if (arm_condexec_masklen + n > 4)
18791 predicate = COND_EXEC_TEST (body);
18792 code = get_arm_condition_code (predicate);
18793 mask = (1 << n) - 1;
18794 if (arm_current_cc == code)
18795 arm_condexec_mask |= (mask << arm_condexec_masklen);
18796 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
18799 arm_condexec_count++;
18800 arm_condexec_masklen += n;
18802 /* A jump must be the last instruction in a conditional block. */
18806 /* Restore recog_data (getting the attributes of other insns can
18807 destroy this array, but final.c assumes that it remains intact
18808 across this call). */
18809 extract_constrain_insn_cached (first_insn);
18813 arm_final_prescan_insn (rtx insn)
18815 /* BODY will hold the body of INSN. */
18816 rtx body = PATTERN (insn);
18818 /* This will be 1 if trying to repeat the trick, and things need to be
18819 reversed if it appears to fail. */
18822 /* If we start with a return insn, we only succeed if we find another one. */
18823 int seeking_return = 0;
18824 enum rtx_code return_code = UNKNOWN;
18826 /* START_INSN will hold the insn from where we start looking. This is the
18827 first insn after the following code_label if REVERSE is true. */
18828 rtx start_insn = insn;
18830 /* If in state 4, check if the target branch is reached, in order to
18831 change back to state 0. */
18832 if (arm_ccfsm_state == 4)
18834 if (insn == arm_target_insn)
18836 arm_target_insn = NULL;
18837 arm_ccfsm_state = 0;
18842 /* If in state 3, it is possible to repeat the trick, if this insn is an
18843 unconditional branch to a label, and immediately following this branch
18844 is the previous target label which is only used once, and the label this
18845 branch jumps to is not too far off. */
18846 if (arm_ccfsm_state == 3)
18848 if (simplejump_p (insn))
18850 start_insn = next_nonnote_insn (start_insn);
18851 if (BARRIER_P (start_insn))
18853 /* XXX Isn't this always a barrier? */
18854 start_insn = next_nonnote_insn (start_insn);
18856 if (LABEL_P (start_insn)
18857 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
18858 && LABEL_NUSES (start_insn) == 1)
18863 else if (ANY_RETURN_P (body))
18865 start_insn = next_nonnote_insn (start_insn);
18866 if (BARRIER_P (start_insn))
18867 start_insn = next_nonnote_insn (start_insn);
18868 if (LABEL_P (start_insn)
18869 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
18870 && LABEL_NUSES (start_insn) == 1)
18873 seeking_return = 1;
18874 return_code = GET_CODE (body);
18883 gcc_assert (!arm_ccfsm_state || reverse);
18884 if (!JUMP_P (insn))
18887 /* This jump might be paralleled with a clobber of the condition codes
18888 the jump should always come first */
18889 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
18890 body = XVECEXP (body, 0, 0);
18893 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
18894 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
18897 int fail = FALSE, succeed = FALSE;
18898 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
18899 int then_not_else = TRUE;
18900 rtx this_insn = start_insn, label = 0;
18902 /* Register the insn jumped to. */
18905 if (!seeking_return)
18906 label = XEXP (SET_SRC (body), 0);
18908 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
18909 label = XEXP (XEXP (SET_SRC (body), 1), 0);
18910 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
18912 label = XEXP (XEXP (SET_SRC (body), 2), 0);
18913 then_not_else = FALSE;
18915 else if (ANY_RETURN_P (XEXP (SET_SRC (body), 1)))
18917 seeking_return = 1;
18918 return_code = GET_CODE (XEXP (SET_SRC (body), 1));
18920 else if (ANY_RETURN_P (XEXP (SET_SRC (body), 2)))
18922 seeking_return = 1;
18923 return_code = GET_CODE (XEXP (SET_SRC (body), 2));
18924 then_not_else = FALSE;
18927 gcc_unreachable ();
18929 /* See how many insns this branch skips, and what kind of insns. If all
18930 insns are okay, and the label or unconditional branch to the same
18931 label is not too far away, succeed. */
18932 for (insns_skipped = 0;
18933 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
18937 this_insn = next_nonnote_insn (this_insn);
18941 switch (GET_CODE (this_insn))
18944 /* Succeed if it is the target label, otherwise fail since
18945 control falls in from somewhere else. */
18946 if (this_insn == label)
18948 arm_ccfsm_state = 1;
18956 /* Succeed if the following insn is the target label.
18958 If return insns are used then the last insn in a function
18959 will be a barrier. */
18960 this_insn = next_nonnote_insn (this_insn);
18961 if (this_insn && this_insn == label)
18963 arm_ccfsm_state = 1;
18971 /* The AAPCS says that conditional calls should not be
18972 used since they make interworking inefficient (the
18973 linker can't transform BL<cond> into BLX). That's
18974 only a problem if the machine has BLX. */
18981 /* Succeed if the following insn is the target label, or
18982 if the following two insns are a barrier and the
18984 this_insn = next_nonnote_insn (this_insn);
18985 if (this_insn && BARRIER_P (this_insn))
18986 this_insn = next_nonnote_insn (this_insn);
18988 if (this_insn && this_insn == label
18989 && insns_skipped < max_insns_skipped)
18991 arm_ccfsm_state = 1;
18999 /* If this is an unconditional branch to the same label, succeed.
19000 If it is to another label, do nothing. If it is conditional,
19002 /* XXX Probably, the tests for SET and the PC are
19005 scanbody = PATTERN (this_insn);
19006 if (GET_CODE (scanbody) == SET
19007 && GET_CODE (SET_DEST (scanbody)) == PC)
19009 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
19010 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
19012 arm_ccfsm_state = 2;
19015 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
19018 /* Fail if a conditional return is undesirable (e.g. on a
19019 StrongARM), but still allow this if optimizing for size. */
19020 else if (GET_CODE (scanbody) == return_code
19021 && !use_return_insn (TRUE, NULL)
19024 else if (GET_CODE (scanbody) == return_code)
19026 arm_ccfsm_state = 2;
19029 else if (GET_CODE (scanbody) == PARALLEL)
19031 switch (get_attr_conds (this_insn))
19041 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
19046 /* Instructions using or affecting the condition codes make it
19048 scanbody = PATTERN (this_insn);
19049 if (!(GET_CODE (scanbody) == SET
19050 || GET_CODE (scanbody) == PARALLEL)
19051 || get_attr_conds (this_insn) != CONDS_NOCOND)
19061 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
19062 arm_target_label = CODE_LABEL_NUMBER (label);
19065 gcc_assert (seeking_return || arm_ccfsm_state == 2);
19067 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
19069 this_insn = next_nonnote_insn (this_insn);
19070 gcc_assert (!this_insn
19071 || (!BARRIER_P (this_insn)
19072 && !LABEL_P (this_insn)));
19076 /* Oh, dear! we ran off the end.. give up. */
19077 extract_constrain_insn_cached (insn);
19078 arm_ccfsm_state = 0;
19079 arm_target_insn = NULL;
19082 arm_target_insn = this_insn;
19085 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
19088 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 0));
19090 if (reverse || then_not_else)
19091 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
19094 /* Restore recog_data (getting the attributes of other insns can
19095 destroy this array, but final.c assumes that it remains intact
19096 across this call. */
19097 extract_constrain_insn_cached (insn);
19101 /* Output IT instructions. */
19103 thumb2_asm_output_opcode (FILE * stream)
19108 if (arm_condexec_mask)
19110 for (n = 0; n < arm_condexec_masklen; n++)
19111 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
19113 asm_fprintf(stream, "i%s\t%s\n\t", buff,
19114 arm_condition_codes[arm_current_cc]);
19115 arm_condexec_mask = 0;
19119 /* Returns true if REGNO is a valid register
19120 for holding a quantity of type MODE. */
19122 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
19124 if (GET_MODE_CLASS (mode) == MODE_CC)
19125 return (regno == CC_REGNUM
19126 || (TARGET_HARD_FLOAT && TARGET_VFP
19127 && regno == VFPCC_REGNUM));
19130 /* For the Thumb we only allow values bigger than SImode in
19131 registers 0 - 6, so that there is always a second low
19132 register available to hold the upper part of the value.
19133 We probably we ought to ensure that the register is the
19134 start of an even numbered register pair. */
19135 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
19137 if (TARGET_HARD_FLOAT && TARGET_VFP
19138 && IS_VFP_REGNUM (regno))
19140 if (mode == SFmode || mode == SImode)
19141 return VFP_REGNO_OK_FOR_SINGLE (regno);
19143 if (mode == DFmode)
19144 return VFP_REGNO_OK_FOR_DOUBLE (regno);
19146 /* VFP registers can hold HFmode values, but there is no point in
19147 putting them there unless we have hardware conversion insns. */
19148 if (mode == HFmode)
19149 return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno);
19152 return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
19153 || (VALID_NEON_QREG_MODE (mode)
19154 && NEON_REGNO_OK_FOR_QUAD (regno))
19155 || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2))
19156 || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3))
19157 || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4))
19158 || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6))
19159 || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8));
19164 if (TARGET_REALLY_IWMMXT)
19166 if (IS_IWMMXT_GR_REGNUM (regno))
19167 return mode == SImode;
19169 if (IS_IWMMXT_REGNUM (regno))
19170 return VALID_IWMMXT_REG_MODE (mode);
19173 /* We allow almost any value to be stored in the general registers.
19174 Restrict doubleword quantities to even register pairs so that we can
19175 use ldrd. Do not allow very large Neon structure opaque modes in
19176 general registers; they would use too many. */
19177 if (regno <= LAST_ARM_REGNUM)
19178 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0)
19179 && ARM_NUM_REGS (mode) <= 4;
19181 if (regno == FRAME_POINTER_REGNUM
19182 || regno == ARG_POINTER_REGNUM)
19183 /* We only allow integers in the fake hard registers. */
19184 return GET_MODE_CLASS (mode) == MODE_INT;
19189 /* Implement MODES_TIEABLE_P. */
19192 arm_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
19194 if (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2))
19197 /* We specifically want to allow elements of "structure" modes to
19198 be tieable to the structure. This more general condition allows
19199 other rarer situations too. */
19201 && (VALID_NEON_DREG_MODE (mode1)
19202 || VALID_NEON_QREG_MODE (mode1)
19203 || VALID_NEON_STRUCT_MODE (mode1))
19204 && (VALID_NEON_DREG_MODE (mode2)
19205 || VALID_NEON_QREG_MODE (mode2)
19206 || VALID_NEON_STRUCT_MODE (mode2)))
19212 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
19213 not used in arm mode. */
19216 arm_regno_class (int regno)
19220 if (regno == STACK_POINTER_REGNUM)
19222 if (regno == CC_REGNUM)
19229 if (TARGET_THUMB2 && regno < 8)
19232 if ( regno <= LAST_ARM_REGNUM
19233 || regno == FRAME_POINTER_REGNUM
19234 || regno == ARG_POINTER_REGNUM)
19235 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
19237 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
19238 return TARGET_THUMB2 ? CC_REG : NO_REGS;
19240 if (IS_VFP_REGNUM (regno))
19242 if (regno <= D7_VFP_REGNUM)
19243 return VFP_D0_D7_REGS;
19244 else if (regno <= LAST_LO_VFP_REGNUM)
19245 return VFP_LO_REGS;
19247 return VFP_HI_REGS;
19250 if (IS_IWMMXT_REGNUM (regno))
19251 return IWMMXT_REGS;
19253 if (IS_IWMMXT_GR_REGNUM (regno))
19254 return IWMMXT_GR_REGS;
19259 /* Handle a special case when computing the offset
19260 of an argument from the frame pointer. */
19262 arm_debugger_arg_offset (int value, rtx addr)
19266 /* We are only interested if dbxout_parms() failed to compute the offset. */
19270 /* We can only cope with the case where the address is held in a register. */
19274 /* If we are using the frame pointer to point at the argument, then
19275 an offset of 0 is correct. */
19276 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
19279 /* If we are using the stack pointer to point at the
19280 argument, then an offset of 0 is correct. */
19281 /* ??? Check this is consistent with thumb2 frame layout. */
19282 if ((TARGET_THUMB || !frame_pointer_needed)
19283 && REGNO (addr) == SP_REGNUM)
19286 /* Oh dear. The argument is pointed to by a register rather
19287 than being held in a register, or being stored at a known
19288 offset from the frame pointer. Since GDB only understands
19289 those two kinds of argument we must translate the address
19290 held in the register into an offset from the frame pointer.
19291 We do this by searching through the insns for the function
19292 looking to see where this register gets its value. If the
19293 register is initialized from the frame pointer plus an offset
19294 then we are in luck and we can continue, otherwise we give up.
19296 This code is exercised by producing debugging information
19297 for a function with arguments like this:
19299 double func (double a, double b, int c, double d) {return d;}
19301 Without this code the stab for parameter 'd' will be set to
19302 an offset of 0 from the frame pointer, rather than 8. */
19304 /* The if() statement says:
19306 If the insn is a normal instruction
19307 and if the insn is setting the value in a register
19308 and if the register being set is the register holding the address of the argument
19309 and if the address is computing by an addition
19310 that involves adding to a register
19311 which is the frame pointer
19316 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
19318 if ( NONJUMP_INSN_P (insn)
19319 && GET_CODE (PATTERN (insn)) == SET
19320 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
19321 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
19322 && REG_P (XEXP (XEXP (PATTERN (insn), 1), 0))
19323 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
19324 && CONST_INT_P (XEXP (XEXP (PATTERN (insn), 1), 1))
19327 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
19336 warning (0, "unable to compute real location of stacked parameter");
19337 value = 8; /* XXX magic hack */
19357 T_MAX /* Size of enum. Keep last. */
19358 } neon_builtin_type_mode;
19360 #define TYPE_MODE_BIT(X) (1 << (X))
19362 #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \
19363 | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF) \
19364 | TYPE_MODE_BIT (T_DI))
19365 #define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \
19366 | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \
19367 | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
19369 #define v8qi_UP T_V8QI
19370 #define v4hi_UP T_V4HI
19371 #define v2si_UP T_V2SI
19372 #define v2sf_UP T_V2SF
19374 #define v16qi_UP T_V16QI
19375 #define v8hi_UP T_V8HI
19376 #define v4si_UP T_V4SI
19377 #define v4sf_UP T_V4SF
19378 #define v2di_UP T_V2DI
19383 #define UP(X) X##_UP
19417 NEON_LOADSTRUCTLANE,
19419 NEON_STORESTRUCTLANE,
19428 const neon_itype itype;
19429 const neon_builtin_type_mode mode;
19430 const enum insn_code code;
19431 unsigned int fcode;
19432 } neon_builtin_datum;
19434 #define CF(N,X) CODE_FOR_neon_##N##X
19436 #define VAR1(T, N, A) \
19437 {#N, NEON_##T, UP (A), CF (N, A), 0}
19438 #define VAR2(T, N, A, B) \
19440 {#N, NEON_##T, UP (B), CF (N, B), 0}
19441 #define VAR3(T, N, A, B, C) \
19442 VAR2 (T, N, A, B), \
19443 {#N, NEON_##T, UP (C), CF (N, C), 0}
19444 #define VAR4(T, N, A, B, C, D) \
19445 VAR3 (T, N, A, B, C), \
19446 {#N, NEON_##T, UP (D), CF (N, D), 0}
19447 #define VAR5(T, N, A, B, C, D, E) \
19448 VAR4 (T, N, A, B, C, D), \
19449 {#N, NEON_##T, UP (E), CF (N, E), 0}
19450 #define VAR6(T, N, A, B, C, D, E, F) \
19451 VAR5 (T, N, A, B, C, D, E), \
19452 {#N, NEON_##T, UP (F), CF (N, F), 0}
19453 #define VAR7(T, N, A, B, C, D, E, F, G) \
19454 VAR6 (T, N, A, B, C, D, E, F), \
19455 {#N, NEON_##T, UP (G), CF (N, G), 0}
19456 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
19457 VAR7 (T, N, A, B, C, D, E, F, G), \
19458 {#N, NEON_##T, UP (H), CF (N, H), 0}
19459 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
19460 VAR8 (T, N, A, B, C, D, E, F, G, H), \
19461 {#N, NEON_##T, UP (I), CF (N, I), 0}
19462 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
19463 VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
19464 {#N, NEON_##T, UP (J), CF (N, J), 0}
19466 /* The mode entries in the following table correspond to the "key" type of the
19467 instruction variant, i.e. equivalent to that which would be specified after
19468 the assembler mnemonic, which usually refers to the last vector operand.
19469 (Signed/unsigned/polynomial types are not differentiated between though, and
19470 are all mapped onto the same mode for a given element size.) The modes
19471 listed per instruction should be the same as those defined for that
19472 instruction's pattern in neon.md. */
19474 static neon_builtin_datum neon_builtin_data[] =
19476 VAR10 (BINOP, vadd,
19477 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19478 VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
19479 VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
19480 VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19481 VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19482 VAR3 (BINOP, vaddhn, v8hi, v4si, v2di),
19483 VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19484 VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19485 VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si),
19486 VAR2 (TERNOP, vfma, v2sf, v4sf),
19487 VAR2 (TERNOP, vfms, v2sf, v4sf),
19488 VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19489 VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si),
19490 VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si),
19491 VAR2 (TERNOP, vqdmlal, v4hi, v2si),
19492 VAR2 (TERNOP, vqdmlsl, v4hi, v2si),
19493 VAR3 (BINOP, vmull, v8qi, v4hi, v2si),
19494 VAR2 (SCALARMULL, vmull_n, v4hi, v2si),
19495 VAR2 (LANEMULL, vmull_lane, v4hi, v2si),
19496 VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si),
19497 VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si),
19498 VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si),
19499 VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si),
19500 VAR2 (BINOP, vqdmull, v4hi, v2si),
19501 VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19502 VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19503 VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19504 VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di),
19505 VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di),
19506 VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di),
19507 VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19508 VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19509 VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19510 VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
19511 VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19512 VAR10 (BINOP, vsub,
19513 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19514 VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
19515 VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
19516 VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19517 VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19518 VAR3 (BINOP, vsubhn, v8hi, v4si, v2di),
19519 VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19520 VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19521 VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19522 VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19523 VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19524 VAR2 (BINOP, vcage, v2sf, v4sf),
19525 VAR2 (BINOP, vcagt, v2sf, v4sf),
19526 VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19527 VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19528 VAR3 (BINOP, vabdl, v8qi, v4hi, v2si),
19529 VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19530 VAR3 (TERNOP, vabal, v8qi, v4hi, v2si),
19531 VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19532 VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19533 VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf),
19534 VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19535 VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19536 VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf),
19537 VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf),
19538 VAR2 (BINOP, vrecps, v2sf, v4sf),
19539 VAR2 (BINOP, vrsqrts, v2sf, v4sf),
19540 VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19541 VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
19542 VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19543 VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19544 VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19545 VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19546 VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19547 VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19548 VAR2 (UNOP, vcnt, v8qi, v16qi),
19549 VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf),
19550 VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf),
19551 VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
19552 /* FIXME: vget_lane supports more variants than this! */
19553 VAR10 (GETLANE, vget_lane,
19554 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19555 VAR10 (SETLANE, vset_lane,
19556 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19557 VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di),
19558 VAR10 (DUP, vdup_n,
19559 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19560 VAR10 (DUPLANE, vdup_lane,
19561 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19562 VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di),
19563 VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di),
19564 VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di),
19565 VAR3 (UNOP, vmovn, v8hi, v4si, v2di),
19566 VAR3 (UNOP, vqmovn, v8hi, v4si, v2di),
19567 VAR3 (UNOP, vqmovun, v8hi, v4si, v2di),
19568 VAR3 (UNOP, vmovl, v8qi, v4hi, v2si),
19569 VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19570 VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19571 VAR2 (LANEMAC, vmlal_lane, v4hi, v2si),
19572 VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si),
19573 VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19574 VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si),
19575 VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si),
19576 VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19577 VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19578 VAR2 (SCALARMAC, vmlal_n, v4hi, v2si),
19579 VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si),
19580 VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19581 VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si),
19582 VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si),
19583 VAR10 (BINOP, vext,
19584 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19585 VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19586 VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi),
19587 VAR2 (UNOP, vrev16, v8qi, v16qi),
19588 VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf),
19589 VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf),
19590 VAR10 (SELECT, vbsl,
19591 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19592 VAR2 (RINT, vrintn, v2sf, v4sf),
19593 VAR2 (RINT, vrinta, v2sf, v4sf),
19594 VAR2 (RINT, vrintp, v2sf, v4sf),
19595 VAR2 (RINT, vrintm, v2sf, v4sf),
19596 VAR2 (RINT, vrintz, v2sf, v4sf),
19597 VAR2 (RINT, vrintx, v2sf, v4sf),
19598 VAR1 (VTBL, vtbl1, v8qi),
19599 VAR1 (VTBL, vtbl2, v8qi),
19600 VAR1 (VTBL, vtbl3, v8qi),
19601 VAR1 (VTBL, vtbl4, v8qi),
19602 VAR1 (VTBX, vtbx1, v8qi),
19603 VAR1 (VTBX, vtbx2, v8qi),
19604 VAR1 (VTBX, vtbx3, v8qi),
19605 VAR1 (VTBX, vtbx4, v8qi),
19606 VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19607 VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19608 VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
19609 VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di),
19610 VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
19611 VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
19612 VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di),
19613 VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di),
19614 VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di),
19615 VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di),
19616 VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di),
19617 VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di),
19618 VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di),
19619 VAR10 (LOAD1, vld1,
19620 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19621 VAR10 (LOAD1LANE, vld1_lane,
19622 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19623 VAR10 (LOAD1, vld1_dup,
19624 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19625 VAR10 (STORE1, vst1,
19626 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19627 VAR10 (STORE1LANE, vst1_lane,
19628 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19630 vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19631 VAR7 (LOADSTRUCTLANE, vld2_lane,
19632 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19633 VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di),
19634 VAR9 (STORESTRUCT, vst2,
19635 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19636 VAR7 (STORESTRUCTLANE, vst2_lane,
19637 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19639 vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19640 VAR7 (LOADSTRUCTLANE, vld3_lane,
19641 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19642 VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di),
19643 VAR9 (STORESTRUCT, vst3,
19644 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19645 VAR7 (STORESTRUCTLANE, vst3_lane,
19646 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19647 VAR9 (LOADSTRUCT, vld4,
19648 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19649 VAR7 (LOADSTRUCTLANE, vld4_lane,
19650 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19651 VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
19652 VAR9 (STORESTRUCT, vst4,
19653 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
19654 VAR7 (STORESTRUCTLANE, vst4_lane,
19655 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
19656 VAR10 (LOGICBINOP, vand,
19657 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19658 VAR10 (LOGICBINOP, vorr,
19659 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19660 VAR10 (BINOP, veor,
19661 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19662 VAR10 (LOGICBINOP, vbic,
19663 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
19664 VAR10 (LOGICBINOP, vorn,
19665 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
19680 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
19681 symbolic names defined here (which would require too much duplication).
19685 ARM_BUILTIN_GETWCGR0,
19686 ARM_BUILTIN_GETWCGR1,
19687 ARM_BUILTIN_GETWCGR2,
19688 ARM_BUILTIN_GETWCGR3,
19690 ARM_BUILTIN_SETWCGR0,
19691 ARM_BUILTIN_SETWCGR1,
19692 ARM_BUILTIN_SETWCGR2,
19693 ARM_BUILTIN_SETWCGR3,
19697 ARM_BUILTIN_WAVG2BR,
19698 ARM_BUILTIN_WAVG2HR,
19699 ARM_BUILTIN_WAVG2B,
19700 ARM_BUILTIN_WAVG2H,
19707 ARM_BUILTIN_WMACSZ,
19709 ARM_BUILTIN_WMACUZ,
19712 ARM_BUILTIN_WSADBZ,
19714 ARM_BUILTIN_WSADHZ,
19716 ARM_BUILTIN_WALIGNI,
19717 ARM_BUILTIN_WALIGNR0,
19718 ARM_BUILTIN_WALIGNR1,
19719 ARM_BUILTIN_WALIGNR2,
19720 ARM_BUILTIN_WALIGNR3,
19723 ARM_BUILTIN_TMIAPH,
19724 ARM_BUILTIN_TMIABB,
19725 ARM_BUILTIN_TMIABT,
19726 ARM_BUILTIN_TMIATB,
19727 ARM_BUILTIN_TMIATT,
19729 ARM_BUILTIN_TMOVMSKB,
19730 ARM_BUILTIN_TMOVMSKH,
19731 ARM_BUILTIN_TMOVMSKW,
19733 ARM_BUILTIN_TBCSTB,
19734 ARM_BUILTIN_TBCSTH,
19735 ARM_BUILTIN_TBCSTW,
19737 ARM_BUILTIN_WMADDS,
19738 ARM_BUILTIN_WMADDU,
19740 ARM_BUILTIN_WPACKHSS,
19741 ARM_BUILTIN_WPACKWSS,
19742 ARM_BUILTIN_WPACKDSS,
19743 ARM_BUILTIN_WPACKHUS,
19744 ARM_BUILTIN_WPACKWUS,
19745 ARM_BUILTIN_WPACKDUS,
19750 ARM_BUILTIN_WADDSSB,
19751 ARM_BUILTIN_WADDSSH,
19752 ARM_BUILTIN_WADDSSW,
19753 ARM_BUILTIN_WADDUSB,
19754 ARM_BUILTIN_WADDUSH,
19755 ARM_BUILTIN_WADDUSW,
19759 ARM_BUILTIN_WSUBSSB,
19760 ARM_BUILTIN_WSUBSSH,
19761 ARM_BUILTIN_WSUBSSW,
19762 ARM_BUILTIN_WSUBUSB,
19763 ARM_BUILTIN_WSUBUSH,
19764 ARM_BUILTIN_WSUBUSW,
19771 ARM_BUILTIN_WCMPEQB,
19772 ARM_BUILTIN_WCMPEQH,
19773 ARM_BUILTIN_WCMPEQW,
19774 ARM_BUILTIN_WCMPGTUB,
19775 ARM_BUILTIN_WCMPGTUH,
19776 ARM_BUILTIN_WCMPGTUW,
19777 ARM_BUILTIN_WCMPGTSB,
19778 ARM_BUILTIN_WCMPGTSH,
19779 ARM_BUILTIN_WCMPGTSW,
19781 ARM_BUILTIN_TEXTRMSB,
19782 ARM_BUILTIN_TEXTRMSH,
19783 ARM_BUILTIN_TEXTRMSW,
19784 ARM_BUILTIN_TEXTRMUB,
19785 ARM_BUILTIN_TEXTRMUH,
19786 ARM_BUILTIN_TEXTRMUW,
19787 ARM_BUILTIN_TINSRB,
19788 ARM_BUILTIN_TINSRH,
19789 ARM_BUILTIN_TINSRW,
19791 ARM_BUILTIN_WMAXSW,
19792 ARM_BUILTIN_WMAXSH,
19793 ARM_BUILTIN_WMAXSB,
19794 ARM_BUILTIN_WMAXUW,
19795 ARM_BUILTIN_WMAXUH,
19796 ARM_BUILTIN_WMAXUB,
19797 ARM_BUILTIN_WMINSW,
19798 ARM_BUILTIN_WMINSH,
19799 ARM_BUILTIN_WMINSB,
19800 ARM_BUILTIN_WMINUW,
19801 ARM_BUILTIN_WMINUH,
19802 ARM_BUILTIN_WMINUB,
19804 ARM_BUILTIN_WMULUM,
19805 ARM_BUILTIN_WMULSM,
19806 ARM_BUILTIN_WMULUL,
19808 ARM_BUILTIN_PSADBH,
19809 ARM_BUILTIN_WSHUFH,
19823 ARM_BUILTIN_WSLLHI,
19824 ARM_BUILTIN_WSLLWI,
19825 ARM_BUILTIN_WSLLDI,
19826 ARM_BUILTIN_WSRAHI,
19827 ARM_BUILTIN_WSRAWI,
19828 ARM_BUILTIN_WSRADI,
19829 ARM_BUILTIN_WSRLHI,
19830 ARM_BUILTIN_WSRLWI,
19831 ARM_BUILTIN_WSRLDI,
19832 ARM_BUILTIN_WRORHI,
19833 ARM_BUILTIN_WRORWI,
19834 ARM_BUILTIN_WRORDI,
19836 ARM_BUILTIN_WUNPCKIHB,
19837 ARM_BUILTIN_WUNPCKIHH,
19838 ARM_BUILTIN_WUNPCKIHW,
19839 ARM_BUILTIN_WUNPCKILB,
19840 ARM_BUILTIN_WUNPCKILH,
19841 ARM_BUILTIN_WUNPCKILW,
19843 ARM_BUILTIN_WUNPCKEHSB,
19844 ARM_BUILTIN_WUNPCKEHSH,
19845 ARM_BUILTIN_WUNPCKEHSW,
19846 ARM_BUILTIN_WUNPCKEHUB,
19847 ARM_BUILTIN_WUNPCKEHUH,
19848 ARM_BUILTIN_WUNPCKEHUW,
19849 ARM_BUILTIN_WUNPCKELSB,
19850 ARM_BUILTIN_WUNPCKELSH,
19851 ARM_BUILTIN_WUNPCKELSW,
19852 ARM_BUILTIN_WUNPCKELUB,
19853 ARM_BUILTIN_WUNPCKELUH,
19854 ARM_BUILTIN_WUNPCKELUW,
19860 ARM_BUILTIN_WADDSUBHX,
19861 ARM_BUILTIN_WSUBADDHX,
19863 ARM_BUILTIN_WABSDIFFB,
19864 ARM_BUILTIN_WABSDIFFH,
19865 ARM_BUILTIN_WABSDIFFW,
19867 ARM_BUILTIN_WADDCH,
19868 ARM_BUILTIN_WADDCW,
19871 ARM_BUILTIN_WAVG4R,
19873 ARM_BUILTIN_WMADDSX,
19874 ARM_BUILTIN_WMADDUX,
19876 ARM_BUILTIN_WMADDSN,
19877 ARM_BUILTIN_WMADDUN,
19879 ARM_BUILTIN_WMULWSM,
19880 ARM_BUILTIN_WMULWUM,
19882 ARM_BUILTIN_WMULWSMR,
19883 ARM_BUILTIN_WMULWUMR,
19885 ARM_BUILTIN_WMULWL,
19887 ARM_BUILTIN_WMULSMR,
19888 ARM_BUILTIN_WMULUMR,
19890 ARM_BUILTIN_WQMULM,
19891 ARM_BUILTIN_WQMULMR,
19893 ARM_BUILTIN_WQMULWM,
19894 ARM_BUILTIN_WQMULWMR,
19896 ARM_BUILTIN_WADDBHUSM,
19897 ARM_BUILTIN_WADDBHUSL,
19899 ARM_BUILTIN_WQMIABB,
19900 ARM_BUILTIN_WQMIABT,
19901 ARM_BUILTIN_WQMIATB,
19902 ARM_BUILTIN_WQMIATT,
19904 ARM_BUILTIN_WQMIABBN,
19905 ARM_BUILTIN_WQMIABTN,
19906 ARM_BUILTIN_WQMIATBN,
19907 ARM_BUILTIN_WQMIATTN,
19909 ARM_BUILTIN_WMIABB,
19910 ARM_BUILTIN_WMIABT,
19911 ARM_BUILTIN_WMIATB,
19912 ARM_BUILTIN_WMIATT,
19914 ARM_BUILTIN_WMIABBN,
19915 ARM_BUILTIN_WMIABTN,
19916 ARM_BUILTIN_WMIATBN,
19917 ARM_BUILTIN_WMIATTN,
19919 ARM_BUILTIN_WMIAWBB,
19920 ARM_BUILTIN_WMIAWBT,
19921 ARM_BUILTIN_WMIAWTB,
19922 ARM_BUILTIN_WMIAWTT,
19924 ARM_BUILTIN_WMIAWBBN,
19925 ARM_BUILTIN_WMIAWBTN,
19926 ARM_BUILTIN_WMIAWTBN,
19927 ARM_BUILTIN_WMIAWTTN,
19929 ARM_BUILTIN_WMERGE,
19931 ARM_BUILTIN_NEON_BASE,
19933 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE + ARRAY_SIZE (neon_builtin_data)
19936 static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX];
19939 arm_init_neon_builtins (void)
19941 unsigned int i, fcode;
19944 tree neon_intQI_type_node;
19945 tree neon_intHI_type_node;
19946 tree neon_polyQI_type_node;
19947 tree neon_polyHI_type_node;
19948 tree neon_intSI_type_node;
19949 tree neon_intDI_type_node;
19950 tree neon_float_type_node;
19952 tree intQI_pointer_node;
19953 tree intHI_pointer_node;
19954 tree intSI_pointer_node;
19955 tree intDI_pointer_node;
19956 tree float_pointer_node;
19958 tree const_intQI_node;
19959 tree const_intHI_node;
19960 tree const_intSI_node;
19961 tree const_intDI_node;
19962 tree const_float_node;
19964 tree const_intQI_pointer_node;
19965 tree const_intHI_pointer_node;
19966 tree const_intSI_pointer_node;
19967 tree const_intDI_pointer_node;
19968 tree const_float_pointer_node;
19970 tree V8QI_type_node;
19971 tree V4HI_type_node;
19972 tree V2SI_type_node;
19973 tree V2SF_type_node;
19974 tree V16QI_type_node;
19975 tree V8HI_type_node;
19976 tree V4SI_type_node;
19977 tree V4SF_type_node;
19978 tree V2DI_type_node;
19980 tree intUQI_type_node;
19981 tree intUHI_type_node;
19982 tree intUSI_type_node;
19983 tree intUDI_type_node;
19985 tree intEI_type_node;
19986 tree intOI_type_node;
19987 tree intCI_type_node;
19988 tree intXI_type_node;
19990 tree V8QI_pointer_node;
19991 tree V4HI_pointer_node;
19992 tree V2SI_pointer_node;
19993 tree V2SF_pointer_node;
19994 tree V16QI_pointer_node;
19995 tree V8HI_pointer_node;
19996 tree V4SI_pointer_node;
19997 tree V4SF_pointer_node;
19998 tree V2DI_pointer_node;
20000 tree void_ftype_pv8qi_v8qi_v8qi;
20001 tree void_ftype_pv4hi_v4hi_v4hi;
20002 tree void_ftype_pv2si_v2si_v2si;
20003 tree void_ftype_pv2sf_v2sf_v2sf;
20004 tree void_ftype_pdi_di_di;
20005 tree void_ftype_pv16qi_v16qi_v16qi;
20006 tree void_ftype_pv8hi_v8hi_v8hi;
20007 tree void_ftype_pv4si_v4si_v4si;
20008 tree void_ftype_pv4sf_v4sf_v4sf;
20009 tree void_ftype_pv2di_v2di_v2di;
20011 tree reinterp_ftype_dreg[5][5];
20012 tree reinterp_ftype_qreg[5][5];
20013 tree dreg_types[5], qreg_types[5];
20015 /* Create distinguished type nodes for NEON vector element types,
20016 and pointers to values of such types, so we can detect them later. */
20017 neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
20018 neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
20019 neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
20020 neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
20021 neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode));
20022 neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode));
20023 neon_float_type_node = make_node (REAL_TYPE);
20024 TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE;
20025 layout_type (neon_float_type_node);
20027 /* Define typedefs which exactly correspond to the modes we are basing vector
20028 types on. If you change these names you'll need to change
20029 the table used by arm_mangle_type too. */
20030 (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node,
20031 "__builtin_neon_qi");
20032 (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node,
20033 "__builtin_neon_hi");
20034 (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node,
20035 "__builtin_neon_si");
20036 (*lang_hooks.types.register_builtin_type) (neon_float_type_node,
20037 "__builtin_neon_sf");
20038 (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node,
20039 "__builtin_neon_di");
20040 (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node,
20041 "__builtin_neon_poly8");
20042 (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node,
20043 "__builtin_neon_poly16");
20045 intQI_pointer_node = build_pointer_type (neon_intQI_type_node);
20046 intHI_pointer_node = build_pointer_type (neon_intHI_type_node);
20047 intSI_pointer_node = build_pointer_type (neon_intSI_type_node);
20048 intDI_pointer_node = build_pointer_type (neon_intDI_type_node);
20049 float_pointer_node = build_pointer_type (neon_float_type_node);
20051 /* Next create constant-qualified versions of the above types. */
20052 const_intQI_node = build_qualified_type (neon_intQI_type_node,
20054 const_intHI_node = build_qualified_type (neon_intHI_type_node,
20056 const_intSI_node = build_qualified_type (neon_intSI_type_node,
20058 const_intDI_node = build_qualified_type (neon_intDI_type_node,
20060 const_float_node = build_qualified_type (neon_float_type_node,
20063 const_intQI_pointer_node = build_pointer_type (const_intQI_node);
20064 const_intHI_pointer_node = build_pointer_type (const_intHI_node);
20065 const_intSI_pointer_node = build_pointer_type (const_intSI_node);
20066 const_intDI_pointer_node = build_pointer_type (const_intDI_node);
20067 const_float_pointer_node = build_pointer_type (const_float_node);
20069 /* Now create vector types based on our NEON element types. */
20070 /* 64-bit vectors. */
20072 build_vector_type_for_mode (neon_intQI_type_node, V8QImode);
20074 build_vector_type_for_mode (neon_intHI_type_node, V4HImode);
20076 build_vector_type_for_mode (neon_intSI_type_node, V2SImode);
20078 build_vector_type_for_mode (neon_float_type_node, V2SFmode);
20079 /* 128-bit vectors. */
20081 build_vector_type_for_mode (neon_intQI_type_node, V16QImode);
20083 build_vector_type_for_mode (neon_intHI_type_node, V8HImode);
20085 build_vector_type_for_mode (neon_intSI_type_node, V4SImode);
20087 build_vector_type_for_mode (neon_float_type_node, V4SFmode);
20089 build_vector_type_for_mode (neon_intDI_type_node, V2DImode);
20091 /* Unsigned integer types for various mode sizes. */
20092 intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode));
20093 intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode));
20094 intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode));
20095 intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode));
20097 (*lang_hooks.types.register_builtin_type) (intUQI_type_node,
20098 "__builtin_neon_uqi");
20099 (*lang_hooks.types.register_builtin_type) (intUHI_type_node,
20100 "__builtin_neon_uhi");
20101 (*lang_hooks.types.register_builtin_type) (intUSI_type_node,
20102 "__builtin_neon_usi");
20103 (*lang_hooks.types.register_builtin_type) (intUDI_type_node,
20104 "__builtin_neon_udi");
20106 /* Opaque integer types for structures of vectors. */
20107 intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode));
20108 intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode));
20109 intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode));
20110 intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode));
20112 (*lang_hooks.types.register_builtin_type) (intTI_type_node,
20113 "__builtin_neon_ti");
20114 (*lang_hooks.types.register_builtin_type) (intEI_type_node,
20115 "__builtin_neon_ei");
20116 (*lang_hooks.types.register_builtin_type) (intOI_type_node,
20117 "__builtin_neon_oi");
20118 (*lang_hooks.types.register_builtin_type) (intCI_type_node,
20119 "__builtin_neon_ci");
20120 (*lang_hooks.types.register_builtin_type) (intXI_type_node,
20121 "__builtin_neon_xi");
20123 /* Pointers to vector types. */
20124 V8QI_pointer_node = build_pointer_type (V8QI_type_node);
20125 V4HI_pointer_node = build_pointer_type (V4HI_type_node);
20126 V2SI_pointer_node = build_pointer_type (V2SI_type_node);
20127 V2SF_pointer_node = build_pointer_type (V2SF_type_node);
20128 V16QI_pointer_node = build_pointer_type (V16QI_type_node);
20129 V8HI_pointer_node = build_pointer_type (V8HI_type_node);
20130 V4SI_pointer_node = build_pointer_type (V4SI_type_node);
20131 V4SF_pointer_node = build_pointer_type (V4SF_type_node);
20132 V2DI_pointer_node = build_pointer_type (V2DI_type_node);
20134 /* Operations which return results as pairs. */
20135 void_ftype_pv8qi_v8qi_v8qi =
20136 build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node,
20137 V8QI_type_node, NULL);
20138 void_ftype_pv4hi_v4hi_v4hi =
20139 build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node,
20140 V4HI_type_node, NULL);
20141 void_ftype_pv2si_v2si_v2si =
20142 build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node,
20143 V2SI_type_node, NULL);
20144 void_ftype_pv2sf_v2sf_v2sf =
20145 build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node,
20146 V2SF_type_node, NULL);
20147 void_ftype_pdi_di_di =
20148 build_function_type_list (void_type_node, intDI_pointer_node,
20149 neon_intDI_type_node, neon_intDI_type_node, NULL);
20150 void_ftype_pv16qi_v16qi_v16qi =
20151 build_function_type_list (void_type_node, V16QI_pointer_node,
20152 V16QI_type_node, V16QI_type_node, NULL);
20153 void_ftype_pv8hi_v8hi_v8hi =
20154 build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node,
20155 V8HI_type_node, NULL);
20156 void_ftype_pv4si_v4si_v4si =
20157 build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node,
20158 V4SI_type_node, NULL);
20159 void_ftype_pv4sf_v4sf_v4sf =
20160 build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node,
20161 V4SF_type_node, NULL);
20162 void_ftype_pv2di_v2di_v2di =
20163 build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node,
20164 V2DI_type_node, NULL);
20166 dreg_types[0] = V8QI_type_node;
20167 dreg_types[1] = V4HI_type_node;
20168 dreg_types[2] = V2SI_type_node;
20169 dreg_types[3] = V2SF_type_node;
20170 dreg_types[4] = neon_intDI_type_node;
20172 qreg_types[0] = V16QI_type_node;
20173 qreg_types[1] = V8HI_type_node;
20174 qreg_types[2] = V4SI_type_node;
20175 qreg_types[3] = V4SF_type_node;
20176 qreg_types[4] = V2DI_type_node;
20178 for (i = 0; i < 5; i++)
20181 for (j = 0; j < 5; j++)
20183 reinterp_ftype_dreg[i][j]
20184 = build_function_type_list (dreg_types[i], dreg_types[j], NULL);
20185 reinterp_ftype_qreg[i][j]
20186 = build_function_type_list (qreg_types[i], qreg_types[j], NULL);
20190 for (i = 0, fcode = ARM_BUILTIN_NEON_BASE;
20191 i < ARRAY_SIZE (neon_builtin_data);
20194 neon_builtin_datum *d = &neon_builtin_data[i];
20196 const char* const modenames[] = {
20197 "v8qi", "v4hi", "v2si", "v2sf", "di",
20198 "v16qi", "v8hi", "v4si", "v4sf", "v2di",
20203 int is_load = 0, is_store = 0;
20205 gcc_assert (ARRAY_SIZE (modenames) == T_MAX);
20212 case NEON_LOAD1LANE:
20213 case NEON_LOADSTRUCT:
20214 case NEON_LOADSTRUCTLANE:
20216 /* Fall through. */
20218 case NEON_STORE1LANE:
20219 case NEON_STORESTRUCT:
20220 case NEON_STORESTRUCTLANE:
20223 /* Fall through. */
20227 case NEON_LOGICBINOP:
20228 case NEON_SHIFTINSERT:
20235 case NEON_SHIFTIMM:
20236 case NEON_SHIFTACC:
20242 case NEON_LANEMULL:
20243 case NEON_LANEMULH:
20245 case NEON_SCALARMUL:
20246 case NEON_SCALARMULL:
20247 case NEON_SCALARMULH:
20248 case NEON_SCALARMAC:
20254 tree return_type = void_type_node, args = void_list_node;
20256 /* Build a function type directly from the insn_data for
20257 this builtin. The build_function_type() function takes
20258 care of removing duplicates for us. */
20259 for (k = insn_data[d->code].n_generator_args - 1; k >= 0; k--)
20263 if (is_load && k == 1)
20265 /* Neon load patterns always have the memory
20266 operand in the operand 1 position. */
20267 gcc_assert (insn_data[d->code].operand[k].predicate
20268 == neon_struct_operand);
20274 eltype = const_intQI_pointer_node;
20279 eltype = const_intHI_pointer_node;
20284 eltype = const_intSI_pointer_node;
20289 eltype = const_float_pointer_node;
20294 eltype = const_intDI_pointer_node;
20297 default: gcc_unreachable ();
20300 else if (is_store && k == 0)
20302 /* Similarly, Neon store patterns use operand 0 as
20303 the memory location to store to. */
20304 gcc_assert (insn_data[d->code].operand[k].predicate
20305 == neon_struct_operand);
20311 eltype = intQI_pointer_node;
20316 eltype = intHI_pointer_node;
20321 eltype = intSI_pointer_node;
20326 eltype = float_pointer_node;
20331 eltype = intDI_pointer_node;
20334 default: gcc_unreachable ();
20339 switch (insn_data[d->code].operand[k].mode)
20341 case VOIDmode: eltype = void_type_node; break;
20343 case QImode: eltype = neon_intQI_type_node; break;
20344 case HImode: eltype = neon_intHI_type_node; break;
20345 case SImode: eltype = neon_intSI_type_node; break;
20346 case SFmode: eltype = neon_float_type_node; break;
20347 case DImode: eltype = neon_intDI_type_node; break;
20348 case TImode: eltype = intTI_type_node; break;
20349 case EImode: eltype = intEI_type_node; break;
20350 case OImode: eltype = intOI_type_node; break;
20351 case CImode: eltype = intCI_type_node; break;
20352 case XImode: eltype = intXI_type_node; break;
20353 /* 64-bit vectors. */
20354 case V8QImode: eltype = V8QI_type_node; break;
20355 case V4HImode: eltype = V4HI_type_node; break;
20356 case V2SImode: eltype = V2SI_type_node; break;
20357 case V2SFmode: eltype = V2SF_type_node; break;
20358 /* 128-bit vectors. */
20359 case V16QImode: eltype = V16QI_type_node; break;
20360 case V8HImode: eltype = V8HI_type_node; break;
20361 case V4SImode: eltype = V4SI_type_node; break;
20362 case V4SFmode: eltype = V4SF_type_node; break;
20363 case V2DImode: eltype = V2DI_type_node; break;
20364 default: gcc_unreachable ();
20368 if (k == 0 && !is_store)
20369 return_type = eltype;
20371 args = tree_cons (NULL_TREE, eltype, args);
20374 ftype = build_function_type (return_type, args);
20378 case NEON_RESULTPAIR:
20380 switch (insn_data[d->code].operand[1].mode)
20382 case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
20383 case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
20384 case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
20385 case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
20386 case DImode: ftype = void_ftype_pdi_di_di; break;
20387 case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
20388 case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
20389 case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
20390 case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
20391 case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
20392 default: gcc_unreachable ();
20397 case NEON_REINTERP:
20399 /* We iterate over 5 doubleword types, then 5 quadword
20401 int rhs = d->mode % 5;
20402 switch (insn_data[d->code].operand[0].mode)
20404 case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
20405 case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
20406 case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
20407 case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
20408 case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
20409 case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
20410 case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
20411 case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
20412 case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
20413 case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
20414 default: gcc_unreachable ();
20420 gcc_unreachable ();
20423 gcc_assert (ftype != NULL);
20425 sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[d->mode]);
20427 decl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, NULL,
20429 arm_builtin_decls[fcode] = decl;
20433 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
20436 if ((MASK) & insn_flags) \
20439 bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \
20440 BUILT_IN_MD, NULL, NULL_TREE); \
20441 arm_builtin_decls[CODE] = bdecl; \
20446 struct builtin_description
20448 const unsigned int mask;
20449 const enum insn_code icode;
20450 const char * const name;
20451 const enum arm_builtins code;
20452 const enum rtx_code comparison;
20453 const unsigned int flag;
20456 static const struct builtin_description bdesc_2arg[] =
20458 #define IWMMXT_BUILTIN(code, string, builtin) \
20459 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
20460 ARM_BUILTIN_##builtin, UNKNOWN, 0 },
20462 #define IWMMXT2_BUILTIN(code, string, builtin) \
20463 { FL_IWMMXT2, CODE_FOR_##code, "__builtin_arm_" string, \
20464 ARM_BUILTIN_##builtin, UNKNOWN, 0 },
20466 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
20467 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
20468 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
20469 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
20470 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
20471 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
20472 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
20473 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
20474 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
20475 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
20476 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
20477 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
20478 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
20479 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
20480 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
20481 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
20482 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
20483 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
20484 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
20485 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
20486 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
20487 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
20488 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
20489 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
20490 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
20491 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
20492 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
20493 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
20494 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
20495 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
20496 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
20497 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
20498 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
20499 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
20500 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
20501 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
20502 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
20503 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
20504 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
20505 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
20506 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
20507 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
20508 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
20509 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
20510 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
20511 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
20512 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
20513 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
20514 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
20515 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
20516 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
20517 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
20518 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
20519 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
20520 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
20521 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
20522 IWMMXT2_BUILTIN (iwmmxt_waddsubhx, "waddsubhx", WADDSUBHX)
20523 IWMMXT2_BUILTIN (iwmmxt_wsubaddhx, "wsubaddhx", WSUBADDHX)
20524 IWMMXT2_BUILTIN (iwmmxt_wabsdiffb, "wabsdiffb", WABSDIFFB)
20525 IWMMXT2_BUILTIN (iwmmxt_wabsdiffh, "wabsdiffh", WABSDIFFH)
20526 IWMMXT2_BUILTIN (iwmmxt_wabsdiffw, "wabsdiffw", WABSDIFFW)
20527 IWMMXT2_BUILTIN (iwmmxt_avg4, "wavg4", WAVG4)
20528 IWMMXT2_BUILTIN (iwmmxt_avg4r, "wavg4r", WAVG4R)
20529 IWMMXT2_BUILTIN (iwmmxt_wmulwsm, "wmulwsm", WMULWSM)
20530 IWMMXT2_BUILTIN (iwmmxt_wmulwum, "wmulwum", WMULWUM)
20531 IWMMXT2_BUILTIN (iwmmxt_wmulwsmr, "wmulwsmr", WMULWSMR)
20532 IWMMXT2_BUILTIN (iwmmxt_wmulwumr, "wmulwumr", WMULWUMR)
20533 IWMMXT2_BUILTIN (iwmmxt_wmulwl, "wmulwl", WMULWL)
20534 IWMMXT2_BUILTIN (iwmmxt_wmulsmr, "wmulsmr", WMULSMR)
20535 IWMMXT2_BUILTIN (iwmmxt_wmulumr, "wmulumr", WMULUMR)
20536 IWMMXT2_BUILTIN (iwmmxt_wqmulm, "wqmulm", WQMULM)
20537 IWMMXT2_BUILTIN (iwmmxt_wqmulmr, "wqmulmr", WQMULMR)
20538 IWMMXT2_BUILTIN (iwmmxt_wqmulwm, "wqmulwm", WQMULWM)
20539 IWMMXT2_BUILTIN (iwmmxt_wqmulwmr, "wqmulwmr", WQMULWMR)
20540 IWMMXT_BUILTIN (iwmmxt_walignr0, "walignr0", WALIGNR0)
20541 IWMMXT_BUILTIN (iwmmxt_walignr1, "walignr1", WALIGNR1)
20542 IWMMXT_BUILTIN (iwmmxt_walignr2, "walignr2", WALIGNR2)
20543 IWMMXT_BUILTIN (iwmmxt_walignr3, "walignr3", WALIGNR3)
20545 #define IWMMXT_BUILTIN2(code, builtin) \
20546 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
20548 #define IWMMXT2_BUILTIN2(code, builtin) \
20549 { FL_IWMMXT2, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
20551 IWMMXT2_BUILTIN2 (iwmmxt_waddbhusm, WADDBHUSM)
20552 IWMMXT2_BUILTIN2 (iwmmxt_waddbhusl, WADDBHUSL)
20553 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
20554 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
20555 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
20556 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
20557 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
20558 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
20559 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
20560 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
20563 static const struct builtin_description bdesc_1arg[] =
20565 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
20566 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
20567 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
20568 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
20569 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
20570 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
20571 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
20572 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
20573 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
20574 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
20575 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
20576 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
20577 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
20578 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
20579 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
20580 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
20581 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
20582 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
20583 IWMMXT2_BUILTIN (iwmmxt_wabsv8qi3, "wabsb", WABSB)
20584 IWMMXT2_BUILTIN (iwmmxt_wabsv4hi3, "wabsh", WABSH)
20585 IWMMXT2_BUILTIN (iwmmxt_wabsv2si3, "wabsw", WABSW)
20586 IWMMXT_BUILTIN (tbcstv8qi, "tbcstb", TBCSTB)
20587 IWMMXT_BUILTIN (tbcstv4hi, "tbcsth", TBCSTH)
20588 IWMMXT_BUILTIN (tbcstv2si, "tbcstw", TBCSTW)
20591 /* Set up all the iWMMXt builtins. This is not called if
20592 TARGET_IWMMXT is zero. */
20595 arm_init_iwmmxt_builtins (void)
20597 const struct builtin_description * d;
20600 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
20601 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
20602 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
20604 tree v8qi_ftype_v8qi_v8qi_int
20605 = build_function_type_list (V8QI_type_node,
20606 V8QI_type_node, V8QI_type_node,
20607 integer_type_node, NULL_TREE);
20608 tree v4hi_ftype_v4hi_int
20609 = build_function_type_list (V4HI_type_node,
20610 V4HI_type_node, integer_type_node, NULL_TREE);
20611 tree v2si_ftype_v2si_int
20612 = build_function_type_list (V2SI_type_node,
20613 V2SI_type_node, integer_type_node, NULL_TREE);
20614 tree v2si_ftype_di_di
20615 = build_function_type_list (V2SI_type_node,
20616 long_long_integer_type_node,
20617 long_long_integer_type_node,
20619 tree di_ftype_di_int
20620 = build_function_type_list (long_long_integer_type_node,
20621 long_long_integer_type_node,
20622 integer_type_node, NULL_TREE);
20623 tree di_ftype_di_int_int
20624 = build_function_type_list (long_long_integer_type_node,
20625 long_long_integer_type_node,
20627 integer_type_node, NULL_TREE);
20628 tree int_ftype_v8qi
20629 = build_function_type_list (integer_type_node,
20630 V8QI_type_node, NULL_TREE);
20631 tree int_ftype_v4hi
20632 = build_function_type_list (integer_type_node,
20633 V4HI_type_node, NULL_TREE);
20634 tree int_ftype_v2si
20635 = build_function_type_list (integer_type_node,
20636 V2SI_type_node, NULL_TREE);
20637 tree int_ftype_v8qi_int
20638 = build_function_type_list (integer_type_node,
20639 V8QI_type_node, integer_type_node, NULL_TREE);
20640 tree int_ftype_v4hi_int
20641 = build_function_type_list (integer_type_node,
20642 V4HI_type_node, integer_type_node, NULL_TREE);
20643 tree int_ftype_v2si_int
20644 = build_function_type_list (integer_type_node,
20645 V2SI_type_node, integer_type_node, NULL_TREE);
20646 tree v8qi_ftype_v8qi_int_int
20647 = build_function_type_list (V8QI_type_node,
20648 V8QI_type_node, integer_type_node,
20649 integer_type_node, NULL_TREE);
20650 tree v4hi_ftype_v4hi_int_int
20651 = build_function_type_list (V4HI_type_node,
20652 V4HI_type_node, integer_type_node,
20653 integer_type_node, NULL_TREE);
20654 tree v2si_ftype_v2si_int_int
20655 = build_function_type_list (V2SI_type_node,
20656 V2SI_type_node, integer_type_node,
20657 integer_type_node, NULL_TREE);
20658 /* Miscellaneous. */
20659 tree v8qi_ftype_v4hi_v4hi
20660 = build_function_type_list (V8QI_type_node,
20661 V4HI_type_node, V4HI_type_node, NULL_TREE);
20662 tree v4hi_ftype_v2si_v2si
20663 = build_function_type_list (V4HI_type_node,
20664 V2SI_type_node, V2SI_type_node, NULL_TREE);
20665 tree v8qi_ftype_v4hi_v8qi
20666 = build_function_type_list (V8QI_type_node,
20667 V4HI_type_node, V8QI_type_node, NULL_TREE);
20668 tree v2si_ftype_v4hi_v4hi
20669 = build_function_type_list (V2SI_type_node,
20670 V4HI_type_node, V4HI_type_node, NULL_TREE);
20671 tree v2si_ftype_v8qi_v8qi
20672 = build_function_type_list (V2SI_type_node,
20673 V8QI_type_node, V8QI_type_node, NULL_TREE);
20674 tree v4hi_ftype_v4hi_di
20675 = build_function_type_list (V4HI_type_node,
20676 V4HI_type_node, long_long_integer_type_node,
20678 tree v2si_ftype_v2si_di
20679 = build_function_type_list (V2SI_type_node,
20680 V2SI_type_node, long_long_integer_type_node,
20683 = build_function_type_list (long_long_unsigned_type_node, NULL_TREE);
20684 tree int_ftype_void
20685 = build_function_type_list (integer_type_node, NULL_TREE);
20687 = build_function_type_list (long_long_integer_type_node,
20688 V8QI_type_node, NULL_TREE);
20690 = build_function_type_list (long_long_integer_type_node,
20691 V4HI_type_node, NULL_TREE);
20693 = build_function_type_list (long_long_integer_type_node,
20694 V2SI_type_node, NULL_TREE);
20695 tree v2si_ftype_v4hi
20696 = build_function_type_list (V2SI_type_node,
20697 V4HI_type_node, NULL_TREE);
20698 tree v4hi_ftype_v8qi
20699 = build_function_type_list (V4HI_type_node,
20700 V8QI_type_node, NULL_TREE);
20701 tree v8qi_ftype_v8qi
20702 = build_function_type_list (V8QI_type_node,
20703 V8QI_type_node, NULL_TREE);
20704 tree v4hi_ftype_v4hi
20705 = build_function_type_list (V4HI_type_node,
20706 V4HI_type_node, NULL_TREE);
20707 tree v2si_ftype_v2si
20708 = build_function_type_list (V2SI_type_node,
20709 V2SI_type_node, NULL_TREE);
20711 tree di_ftype_di_v4hi_v4hi
20712 = build_function_type_list (long_long_unsigned_type_node,
20713 long_long_unsigned_type_node,
20714 V4HI_type_node, V4HI_type_node,
20717 tree di_ftype_v4hi_v4hi
20718 = build_function_type_list (long_long_unsigned_type_node,
20719 V4HI_type_node,V4HI_type_node,
20722 tree v2si_ftype_v2si_v4hi_v4hi
20723 = build_function_type_list (V2SI_type_node,
20724 V2SI_type_node, V4HI_type_node,
20725 V4HI_type_node, NULL_TREE);
20727 tree v2si_ftype_v2si_v8qi_v8qi
20728 = build_function_type_list (V2SI_type_node,
20729 V2SI_type_node, V8QI_type_node,
20730 V8QI_type_node, NULL_TREE);
20732 tree di_ftype_di_v2si_v2si
20733 = build_function_type_list (long_long_unsigned_type_node,
20734 long_long_unsigned_type_node,
20735 V2SI_type_node, V2SI_type_node,
20738 tree di_ftype_di_di_int
20739 = build_function_type_list (long_long_unsigned_type_node,
20740 long_long_unsigned_type_node,
20741 long_long_unsigned_type_node,
20742 integer_type_node, NULL_TREE);
20744 tree void_ftype_int
20745 = build_function_type_list (void_type_node,
20746 integer_type_node, NULL_TREE);
20748 tree v8qi_ftype_char
20749 = build_function_type_list (V8QI_type_node,
20750 signed_char_type_node, NULL_TREE);
20752 tree v4hi_ftype_short
20753 = build_function_type_list (V4HI_type_node,
20754 short_integer_type_node, NULL_TREE);
20756 tree v2si_ftype_int
20757 = build_function_type_list (V2SI_type_node,
20758 integer_type_node, NULL_TREE);
20760 /* Normal vector binops. */
20761 tree v8qi_ftype_v8qi_v8qi
20762 = build_function_type_list (V8QI_type_node,
20763 V8QI_type_node, V8QI_type_node, NULL_TREE);
20764 tree v4hi_ftype_v4hi_v4hi
20765 = build_function_type_list (V4HI_type_node,
20766 V4HI_type_node,V4HI_type_node, NULL_TREE);
20767 tree v2si_ftype_v2si_v2si
20768 = build_function_type_list (V2SI_type_node,
20769 V2SI_type_node, V2SI_type_node, NULL_TREE);
20770 tree di_ftype_di_di
20771 = build_function_type_list (long_long_unsigned_type_node,
20772 long_long_unsigned_type_node,
20773 long_long_unsigned_type_node,
20776 /* Add all builtins that are more or less simple operations on two
20778 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
20780 /* Use one of the operands; the target can have a different mode for
20781 mask-generating compares. */
20782 enum machine_mode mode;
20788 mode = insn_data[d->icode].operand[1].mode;
20793 type = v8qi_ftype_v8qi_v8qi;
20796 type = v4hi_ftype_v4hi_v4hi;
20799 type = v2si_ftype_v2si_v2si;
20802 type = di_ftype_di_di;
20806 gcc_unreachable ();
20809 def_mbuiltin (d->mask, d->name, type, d->code);
20812 /* Add the remaining MMX insns with somewhat more complicated types. */
20813 #define iwmmx_mbuiltin(NAME, TYPE, CODE) \
20814 def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \
20815 ARM_BUILTIN_ ## CODE)
20817 #define iwmmx2_mbuiltin(NAME, TYPE, CODE) \
20818 def_mbuiltin (FL_IWMMXT2, "__builtin_arm_" NAME, (TYPE), \
20819 ARM_BUILTIN_ ## CODE)
20821 iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);
20822 iwmmx_mbuiltin ("setwcgr0", void_ftype_int, SETWCGR0);
20823 iwmmx_mbuiltin ("setwcgr1", void_ftype_int, SETWCGR1);
20824 iwmmx_mbuiltin ("setwcgr2", void_ftype_int, SETWCGR2);
20825 iwmmx_mbuiltin ("setwcgr3", void_ftype_int, SETWCGR3);
20826 iwmmx_mbuiltin ("getwcgr0", int_ftype_void, GETWCGR0);
20827 iwmmx_mbuiltin ("getwcgr1", int_ftype_void, GETWCGR1);
20828 iwmmx_mbuiltin ("getwcgr2", int_ftype_void, GETWCGR2);
20829 iwmmx_mbuiltin ("getwcgr3", int_ftype_void, GETWCGR3);
20831 iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH);
20832 iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW);
20833 iwmmx_mbuiltin ("wslld", di_ftype_di_di, WSLLD);
20834 iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int, WSLLHI);
20835 iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int, WSLLWI);
20836 iwmmx_mbuiltin ("wslldi", di_ftype_di_int, WSLLDI);
20838 iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di, WSRLH);
20839 iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di, WSRLW);
20840 iwmmx_mbuiltin ("wsrld", di_ftype_di_di, WSRLD);
20841 iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int, WSRLHI);
20842 iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int, WSRLWI);
20843 iwmmx_mbuiltin ("wsrldi", di_ftype_di_int, WSRLDI);
20845 iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di, WSRAH);
20846 iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di, WSRAW);
20847 iwmmx_mbuiltin ("wsrad", di_ftype_di_di, WSRAD);
20848 iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int, WSRAHI);
20849 iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int, WSRAWI);
20850 iwmmx_mbuiltin ("wsradi", di_ftype_di_int, WSRADI);
20852 iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di, WRORH);
20853 iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di, WRORW);
20854 iwmmx_mbuiltin ("wrord", di_ftype_di_di, WRORD);
20855 iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int, WRORHI);
20856 iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int, WRORWI);
20857 iwmmx_mbuiltin ("wrordi", di_ftype_di_int, WRORDI);
20859 iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH);
20861 iwmmx_mbuiltin ("wsadb", v2si_ftype_v2si_v8qi_v8qi, WSADB);
20862 iwmmx_mbuiltin ("wsadh", v2si_ftype_v2si_v4hi_v4hi, WSADH);
20863 iwmmx_mbuiltin ("wmadds", v2si_ftype_v4hi_v4hi, WMADDS);
20864 iwmmx2_mbuiltin ("wmaddsx", v2si_ftype_v4hi_v4hi, WMADDSX);
20865 iwmmx2_mbuiltin ("wmaddsn", v2si_ftype_v4hi_v4hi, WMADDSN);
20866 iwmmx_mbuiltin ("wmaddu", v2si_ftype_v4hi_v4hi, WMADDU);
20867 iwmmx2_mbuiltin ("wmaddux", v2si_ftype_v4hi_v4hi, WMADDUX);
20868 iwmmx2_mbuiltin ("wmaddun", v2si_ftype_v4hi_v4hi, WMADDUN);
20869 iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ);
20870 iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ);
20872 iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int, TEXTRMSB);
20873 iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int, TEXTRMSH);
20874 iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int, TEXTRMSW);
20875 iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int, TEXTRMUB);
20876 iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int, TEXTRMUH);
20877 iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int, TEXTRMUW);
20878 iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int, TINSRB);
20879 iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int, TINSRH);
20880 iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int, TINSRW);
20882 iwmmx_mbuiltin ("waccb", di_ftype_v8qi, WACCB);
20883 iwmmx_mbuiltin ("wacch", di_ftype_v4hi, WACCH);
20884 iwmmx_mbuiltin ("waccw", di_ftype_v2si, WACCW);
20886 iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi, TMOVMSKB);
20887 iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH);
20888 iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW);
20890 iwmmx2_mbuiltin ("waddbhusm", v8qi_ftype_v4hi_v8qi, WADDBHUSM);
20891 iwmmx2_mbuiltin ("waddbhusl", v8qi_ftype_v4hi_v8qi, WADDBHUSL);
20893 iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS);
20894 iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS);
20895 iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS);
20896 iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si, WPACKWSS);
20897 iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di, WPACKDUS);
20898 iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di, WPACKDSS);
20900 iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi, WUNPCKEHUB);
20901 iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi, WUNPCKEHUH);
20902 iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si, WUNPCKEHUW);
20903 iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi, WUNPCKEHSB);
20904 iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi, WUNPCKEHSH);
20905 iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si, WUNPCKEHSW);
20906 iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi, WUNPCKELUB);
20907 iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi, WUNPCKELUH);
20908 iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si, WUNPCKELUW);
20909 iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi, WUNPCKELSB);
20910 iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi, WUNPCKELSH);
20911 iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si, WUNPCKELSW);
20913 iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi, WMACS);
20914 iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi, WMACSZ);
20915 iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU);
20916 iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ);
20918 iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGNI);
20919 iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA);
20920 iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH);
20921 iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB);
20922 iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int, TMIABT);
20923 iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB);
20924 iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT);
20926 iwmmx2_mbuiltin ("wabsb", v8qi_ftype_v8qi, WABSB);
20927 iwmmx2_mbuiltin ("wabsh", v4hi_ftype_v4hi, WABSH);
20928 iwmmx2_mbuiltin ("wabsw", v2si_ftype_v2si, WABSW);
20930 iwmmx2_mbuiltin ("wqmiabb", v2si_ftype_v2si_v4hi_v4hi, WQMIABB);
20931 iwmmx2_mbuiltin ("wqmiabt", v2si_ftype_v2si_v4hi_v4hi, WQMIABT);
20932 iwmmx2_mbuiltin ("wqmiatb", v2si_ftype_v2si_v4hi_v4hi, WQMIATB);
20933 iwmmx2_mbuiltin ("wqmiatt", v2si_ftype_v2si_v4hi_v4hi, WQMIATT);
20935 iwmmx2_mbuiltin ("wqmiabbn", v2si_ftype_v2si_v4hi_v4hi, WQMIABBN);
20936 iwmmx2_mbuiltin ("wqmiabtn", v2si_ftype_v2si_v4hi_v4hi, WQMIABTN);
20937 iwmmx2_mbuiltin ("wqmiatbn", v2si_ftype_v2si_v4hi_v4hi, WQMIATBN);
20938 iwmmx2_mbuiltin ("wqmiattn", v2si_ftype_v2si_v4hi_v4hi, WQMIATTN);
20940 iwmmx2_mbuiltin ("wmiabb", di_ftype_di_v4hi_v4hi, WMIABB);
20941 iwmmx2_mbuiltin ("wmiabt", di_ftype_di_v4hi_v4hi, WMIABT);
20942 iwmmx2_mbuiltin ("wmiatb", di_ftype_di_v4hi_v4hi, WMIATB);
20943 iwmmx2_mbuiltin ("wmiatt", di_ftype_di_v4hi_v4hi, WMIATT);
20945 iwmmx2_mbuiltin ("wmiabbn", di_ftype_di_v4hi_v4hi, WMIABBN);
20946 iwmmx2_mbuiltin ("wmiabtn", di_ftype_di_v4hi_v4hi, WMIABTN);
20947 iwmmx2_mbuiltin ("wmiatbn", di_ftype_di_v4hi_v4hi, WMIATBN);
20948 iwmmx2_mbuiltin ("wmiattn", di_ftype_di_v4hi_v4hi, WMIATTN);
20950 iwmmx2_mbuiltin ("wmiawbb", di_ftype_di_v2si_v2si, WMIAWBB);
20951 iwmmx2_mbuiltin ("wmiawbt", di_ftype_di_v2si_v2si, WMIAWBT);
20952 iwmmx2_mbuiltin ("wmiawtb", di_ftype_di_v2si_v2si, WMIAWTB);
20953 iwmmx2_mbuiltin ("wmiawtt", di_ftype_di_v2si_v2si, WMIAWTT);
20955 iwmmx2_mbuiltin ("wmiawbbn", di_ftype_di_v2si_v2si, WMIAWBBN);
20956 iwmmx2_mbuiltin ("wmiawbtn", di_ftype_di_v2si_v2si, WMIAWBTN);
20957 iwmmx2_mbuiltin ("wmiawtbn", di_ftype_di_v2si_v2si, WMIAWTBN);
20958 iwmmx2_mbuiltin ("wmiawttn", di_ftype_di_v2si_v2si, WMIAWTTN);
20960 iwmmx2_mbuiltin ("wmerge", di_ftype_di_di_int, WMERGE);
20962 iwmmx_mbuiltin ("tbcstb", v8qi_ftype_char, TBCSTB);
20963 iwmmx_mbuiltin ("tbcsth", v4hi_ftype_short, TBCSTH);
20964 iwmmx_mbuiltin ("tbcstw", v2si_ftype_int, TBCSTW);
20966 #undef iwmmx_mbuiltin
20967 #undef iwmmx2_mbuiltin
20971 arm_init_fp16_builtins (void)
20973 tree fp16_type = make_node (REAL_TYPE);
20974 TYPE_PRECISION (fp16_type) = 16;
20975 layout_type (fp16_type);
20976 (*lang_hooks.types.register_builtin_type) (fp16_type, "__fp16");
20980 arm_init_builtins (void)
20982 if (TARGET_REALLY_IWMMXT)
20983 arm_init_iwmmxt_builtins ();
20986 arm_init_neon_builtins ();
20988 if (arm_fp16_format)
20989 arm_init_fp16_builtins ();
20992 /* Return the ARM builtin for CODE. */
20995 arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
20997 if (code >= ARM_BUILTIN_MAX)
20998 return error_mark_node;
21000 return arm_builtin_decls[code];
21003 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
21005 static const char *
21006 arm_invalid_parameter_type (const_tree t)
21008 if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
21009 return N_("function parameters cannot have __fp16 type");
21013 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
21015 static const char *
21016 arm_invalid_return_type (const_tree t)
21018 if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
21019 return N_("functions cannot return __fp16 type");
21023 /* Implement TARGET_PROMOTED_TYPE. */
21026 arm_promoted_type (const_tree t)
21028 if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
21029 return float_type_node;
21033 /* Implement TARGET_CONVERT_TO_TYPE.
21034 Specifically, this hook implements the peculiarity of the ARM
21035 half-precision floating-point C semantics that requires conversions between
21036 __fp16 to or from double to do an intermediate conversion to float. */
21039 arm_convert_to_type (tree type, tree expr)
21041 tree fromtype = TREE_TYPE (expr);
21042 if (!SCALAR_FLOAT_TYPE_P (fromtype) || !SCALAR_FLOAT_TYPE_P (type))
21044 if ((TYPE_PRECISION (fromtype) == 16 && TYPE_PRECISION (type) > 32)
21045 || (TYPE_PRECISION (type) == 16 && TYPE_PRECISION (fromtype) > 32))
21046 return convert (type, convert (float_type_node, expr));
21050 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P.
21051 This simply adds HFmode as a supported mode; even though we don't
21052 implement arithmetic on this type directly, it's supported by
21053 optabs conversions, much the way the double-word arithmetic is
21054 special-cased in the default hook. */
21057 arm_scalar_mode_supported_p (enum machine_mode mode)
21059 if (mode == HFmode)
21060 return (arm_fp16_format != ARM_FP16_FORMAT_NONE);
21061 else if (ALL_FIXED_POINT_MODE_P (mode))
21064 return default_scalar_mode_supported_p (mode);
21067 /* Errors in the source file can cause expand_expr to return const0_rtx
21068 where we expect a vector. To avoid crashing, use one of the vector
21069 clear instructions. */
21072 safe_vector_operand (rtx x, enum machine_mode mode)
21074 if (x != const0_rtx)
21076 x = gen_reg_rtx (mode);
21078 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
21079 : gen_rtx_SUBREG (DImode, x, 0)));
21083 /* Subroutine of arm_expand_builtin to take care of binop insns. */
21086 arm_expand_binop_builtin (enum insn_code icode,
21087 tree exp, rtx target)
21090 tree arg0 = CALL_EXPR_ARG (exp, 0);
21091 tree arg1 = CALL_EXPR_ARG (exp, 1);
21092 rtx op0 = expand_normal (arg0);
21093 rtx op1 = expand_normal (arg1);
21094 enum machine_mode tmode = insn_data[icode].operand[0].mode;
21095 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
21096 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
21098 if (VECTOR_MODE_P (mode0))
21099 op0 = safe_vector_operand (op0, mode0);
21100 if (VECTOR_MODE_P (mode1))
21101 op1 = safe_vector_operand (op1, mode1);
21104 || GET_MODE (target) != tmode
21105 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21106 target = gen_reg_rtx (tmode);
21108 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
21109 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
21111 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21112 op0 = copy_to_mode_reg (mode0, op0);
21113 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
21114 op1 = copy_to_mode_reg (mode1, op1);
21116 pat = GEN_FCN (icode) (target, op0, op1);
21123 /* Subroutine of arm_expand_builtin to take care of unop insns. */
21126 arm_expand_unop_builtin (enum insn_code icode,
21127 tree exp, rtx target, int do_load)
21130 tree arg0 = CALL_EXPR_ARG (exp, 0);
21131 rtx op0 = expand_normal (arg0);
21132 enum machine_mode tmode = insn_data[icode].operand[0].mode;
21133 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
21136 || GET_MODE (target) != tmode
21137 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21138 target = gen_reg_rtx (tmode);
21140 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
21143 if (VECTOR_MODE_P (mode0))
21144 op0 = safe_vector_operand (op0, mode0);
21146 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21147 op0 = copy_to_mode_reg (mode0, op0);
21150 pat = GEN_FCN (icode) (target, op0);
21158 NEON_ARG_COPY_TO_REG,
21164 #define NEON_MAX_BUILTIN_ARGS 5
21166 /* EXP is a pointer argument to a Neon load or store intrinsic. Derive
21167 and return an expression for the accessed memory.
21169 The intrinsic function operates on a block of registers that has
21170 mode REG_MODE. This block contains vectors of type TYPE_MODE. The
21171 function references the memory at EXP of type TYPE and in mode
21172 MEM_MODE; this mode may be BLKmode if no more suitable mode is
21176 neon_dereference_pointer (tree exp, tree type, enum machine_mode mem_mode,
21177 enum machine_mode reg_mode,
21178 neon_builtin_type_mode type_mode)
21180 HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
21181 tree elem_type, upper_bound, array_type;
21183 /* Work out the size of the register block in bytes. */
21184 reg_size = GET_MODE_SIZE (reg_mode);
21186 /* Work out the size of each vector in bytes. */
21187 gcc_assert (TYPE_MODE_BIT (type_mode) & (TB_DREG | TB_QREG));
21188 vector_size = (TYPE_MODE_BIT (type_mode) & TB_QREG ? 16 : 8);
21190 /* Work out how many vectors there are. */
21191 gcc_assert (reg_size % vector_size == 0);
21192 nvectors = reg_size / vector_size;
21194 /* Work out the type of each element. */
21195 gcc_assert (POINTER_TYPE_P (type));
21196 elem_type = TREE_TYPE (type);
21198 /* Work out how many elements are being loaded or stored.
21199 MEM_MODE == REG_MODE implies a one-to-one mapping between register
21200 and memory elements; anything else implies a lane load or store. */
21201 if (mem_mode == reg_mode)
21202 nelems = vector_size * nvectors / int_size_in_bytes (elem_type);
21206 /* Create a type that describes the full access. */
21207 upper_bound = build_int_cst (size_type_node, nelems - 1);
21208 array_type = build_array_type (elem_type, build_index_type (upper_bound));
21210 /* Dereference EXP using that type. */
21211 return fold_build2 (MEM_REF, array_type, exp,
21212 build_int_cst (build_pointer_type (array_type), 0));
21215 /* Expand a Neon builtin. */
21217 arm_expand_neon_args (rtx target, int icode, int have_retval,
21218 neon_builtin_type_mode type_mode,
21219 tree exp, int fcode, ...)
21223 tree arg[NEON_MAX_BUILTIN_ARGS];
21224 rtx op[NEON_MAX_BUILTIN_ARGS];
21227 enum machine_mode tmode = insn_data[icode].operand[0].mode;
21228 enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
21229 enum machine_mode other_mode;
21235 || GET_MODE (target) != tmode
21236 || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
21237 target = gen_reg_rtx (tmode);
21239 va_start (ap, fcode);
21241 formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode]));
21245 builtin_arg thisarg = (builtin_arg) va_arg (ap, int);
21247 if (thisarg == NEON_ARG_STOP)
21251 opno = argc + have_retval;
21252 mode[argc] = insn_data[icode].operand[opno].mode;
21253 arg[argc] = CALL_EXPR_ARG (exp, argc);
21254 arg_type = TREE_VALUE (formals);
21255 if (thisarg == NEON_ARG_MEMORY)
21257 other_mode = insn_data[icode].operand[1 - opno].mode;
21258 arg[argc] = neon_dereference_pointer (arg[argc], arg_type,
21259 mode[argc], other_mode,
21263 op[argc] = expand_normal (arg[argc]);
21267 case NEON_ARG_COPY_TO_REG:
21268 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
21269 if (!(*insn_data[icode].operand[opno].predicate)
21270 (op[argc], mode[argc]))
21271 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
21274 case NEON_ARG_CONSTANT:
21275 /* FIXME: This error message is somewhat unhelpful. */
21276 if (!(*insn_data[icode].operand[opno].predicate)
21277 (op[argc], mode[argc]))
21278 error ("argument must be a constant");
21281 case NEON_ARG_MEMORY:
21282 gcc_assert (MEM_P (op[argc]));
21283 PUT_MODE (op[argc], mode[argc]);
21284 /* ??? arm_neon.h uses the same built-in functions for signed
21285 and unsigned accesses, casting where necessary. This isn't
21287 set_mem_alias_set (op[argc], 0);
21288 if (!(*insn_data[icode].operand[opno].predicate)
21289 (op[argc], mode[argc]))
21290 op[argc] = (replace_equiv_address
21291 (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
21294 case NEON_ARG_STOP:
21295 gcc_unreachable ();
21299 formals = TREE_CHAIN (formals);
21309 pat = GEN_FCN (icode) (target, op[0]);
21313 pat = GEN_FCN (icode) (target, op[0], op[1]);
21317 pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
21321 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
21325 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
21329 gcc_unreachable ();
21335 pat = GEN_FCN (icode) (op[0]);
21339 pat = GEN_FCN (icode) (op[0], op[1]);
21343 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
21347 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
21351 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
21355 gcc_unreachable ();
21366 /* Expand a Neon builtin. These are "special" because they don't have symbolic
21367 constants defined per-instruction or per instruction-variant. Instead, the
21368 required info is looked up in the table neon_builtin_data. */
21370 arm_expand_neon_builtin (int fcode, tree exp, rtx target)
21372 neon_builtin_datum *d = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE];
21373 neon_itype itype = d->itype;
21374 enum insn_code icode = d->code;
21375 neon_builtin_type_mode type_mode = d->mode;
21382 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21383 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
21387 case NEON_SCALARMUL:
21388 case NEON_SCALARMULL:
21389 case NEON_SCALARMULH:
21390 case NEON_SHIFTINSERT:
21391 case NEON_LOGICBINOP:
21392 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21393 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
21397 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21398 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
21399 NEON_ARG_CONSTANT, NEON_ARG_STOP);
21403 case NEON_SHIFTIMM:
21404 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21405 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
21409 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21410 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
21415 case NEON_REINTERP:
21416 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21417 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
21421 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21422 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
21424 case NEON_RESULTPAIR:
21425 return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
21426 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
21430 case NEON_LANEMULL:
21431 case NEON_LANEMULH:
21432 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21433 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
21434 NEON_ARG_CONSTANT, NEON_ARG_STOP);
21437 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21438 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
21439 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
21441 case NEON_SHIFTACC:
21442 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21443 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
21444 NEON_ARG_CONSTANT, NEON_ARG_STOP);
21446 case NEON_SCALARMAC:
21447 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21448 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
21449 NEON_ARG_CONSTANT, NEON_ARG_STOP);
21453 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21454 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
21458 case NEON_LOADSTRUCT:
21459 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21460 NEON_ARG_MEMORY, NEON_ARG_STOP);
21462 case NEON_LOAD1LANE:
21463 case NEON_LOADSTRUCTLANE:
21464 return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
21465 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
21469 case NEON_STORESTRUCT:
21470 return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
21471 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
21473 case NEON_STORE1LANE:
21474 case NEON_STORESTRUCTLANE:
21475 return arm_expand_neon_args (target, icode, 0, type_mode, exp, fcode,
21476 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
21480 gcc_unreachable ();
21483 /* Emit code to reinterpret one Neon type as another, without altering bits. */
21485 neon_reinterpret (rtx dest, rtx src)
21487 emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src));
21490 /* Emit code to place a Neon pair result in memory locations (with equal
21493 neon_emit_pair_result_insn (enum machine_mode mode,
21494 rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr,
21497 rtx mem = gen_rtx_MEM (mode, destaddr);
21498 rtx tmp1 = gen_reg_rtx (mode);
21499 rtx tmp2 = gen_reg_rtx (mode);
21501 emit_insn (intfn (tmp1, op1, op2, tmp2));
21503 emit_move_insn (mem, tmp1);
21504 mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
21505 emit_move_insn (mem, tmp2);
21508 /* Set up OPERANDS for a register copy from SRC to DEST, taking care
21509 not to early-clobber SRC registers in the process.
21511 We assume that the operands described by SRC and DEST represent a
21512 decomposed copy of OPERANDS[1] into OPERANDS[0]. COUNT is the
21513 number of components into which the copy has been decomposed. */
21515 neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count)
21519 if (!reg_overlap_mentioned_p (operands[0], operands[1])
21520 || REGNO (operands[0]) < REGNO (operands[1]))
21522 for (i = 0; i < count; i++)
21524 operands[2 * i] = dest[i];
21525 operands[2 * i + 1] = src[i];
21530 for (i = 0; i < count; i++)
21532 operands[2 * i] = dest[count - i - 1];
21533 operands[2 * i + 1] = src[count - i - 1];
21538 /* Split operands into moves from op[1] + op[2] into op[0]. */
21541 neon_split_vcombine (rtx operands[3])
21543 unsigned int dest = REGNO (operands[0]);
21544 unsigned int src1 = REGNO (operands[1]);
21545 unsigned int src2 = REGNO (operands[2]);
21546 enum machine_mode halfmode = GET_MODE (operands[1]);
21547 unsigned int halfregs = HARD_REGNO_NREGS (src1, halfmode);
21548 rtx destlo, desthi;
21550 if (src1 == dest && src2 == dest + halfregs)
21552 /* No-op move. Can't split to nothing; emit something. */
21553 emit_note (NOTE_INSN_DELETED);
21557 /* Preserve register attributes for variable tracking. */
21558 destlo = gen_rtx_REG_offset (operands[0], halfmode, dest, 0);
21559 desthi = gen_rtx_REG_offset (operands[0], halfmode, dest + halfregs,
21560 GET_MODE_SIZE (halfmode));
21562 /* Special case of reversed high/low parts. Use VSWP. */
21563 if (src2 == dest && src1 == dest + halfregs)
21565 rtx x = gen_rtx_SET (VOIDmode, destlo, operands[1]);
21566 rtx y = gen_rtx_SET (VOIDmode, desthi, operands[2]);
21567 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y)));
21571 if (!reg_overlap_mentioned_p (operands[2], destlo))
21573 /* Try to avoid unnecessary moves if part of the result
21574 is in the right place already. */
21576 emit_move_insn (destlo, operands[1]);
21577 if (src2 != dest + halfregs)
21578 emit_move_insn (desthi, operands[2]);
21582 if (src2 != dest + halfregs)
21583 emit_move_insn (desthi, operands[2]);
21585 emit_move_insn (destlo, operands[1]);
21589 /* Expand an expression EXP that calls a built-in function,
21590 with result going to TARGET if that's convenient
21591 (and in mode MODE if that's convenient).
21592 SUBTARGET may be used as the target for computing one of EXP's operands.
21593 IGNORE is nonzero if the value is to be ignored. */
21596 arm_expand_builtin (tree exp,
21598 rtx subtarget ATTRIBUTE_UNUSED,
21599 enum machine_mode mode ATTRIBUTE_UNUSED,
21600 int ignore ATTRIBUTE_UNUSED)
21602 const struct builtin_description * d;
21603 enum insn_code icode;
21604 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
21612 int fcode = DECL_FUNCTION_CODE (fndecl);
21614 enum machine_mode tmode;
21615 enum machine_mode mode0;
21616 enum machine_mode mode1;
21617 enum machine_mode mode2;
21623 if (fcode >= ARM_BUILTIN_NEON_BASE)
21624 return arm_expand_neon_builtin (fcode, exp, target);
21628 case ARM_BUILTIN_TEXTRMSB:
21629 case ARM_BUILTIN_TEXTRMUB:
21630 case ARM_BUILTIN_TEXTRMSH:
21631 case ARM_BUILTIN_TEXTRMUH:
21632 case ARM_BUILTIN_TEXTRMSW:
21633 case ARM_BUILTIN_TEXTRMUW:
21634 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
21635 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
21636 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
21637 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
21638 : CODE_FOR_iwmmxt_textrmw);
21640 arg0 = CALL_EXPR_ARG (exp, 0);
21641 arg1 = CALL_EXPR_ARG (exp, 1);
21642 op0 = expand_normal (arg0);
21643 op1 = expand_normal (arg1);
21644 tmode = insn_data[icode].operand[0].mode;
21645 mode0 = insn_data[icode].operand[1].mode;
21646 mode1 = insn_data[icode].operand[2].mode;
21648 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21649 op0 = copy_to_mode_reg (mode0, op0);
21650 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
21652 /* @@@ better error message */
21653 error ("selector must be an immediate");
21654 return gen_reg_rtx (tmode);
21657 opint = INTVAL (op1);
21658 if (fcode == ARM_BUILTIN_TEXTRMSB || fcode == ARM_BUILTIN_TEXTRMUB)
21660 if (opint > 7 || opint < 0)
21661 error ("the range of selector should be in 0 to 7");
21663 else if (fcode == ARM_BUILTIN_TEXTRMSH || fcode == ARM_BUILTIN_TEXTRMUH)
21665 if (opint > 3 || opint < 0)
21666 error ("the range of selector should be in 0 to 3");
21668 else /* ARM_BUILTIN_TEXTRMSW || ARM_BUILTIN_TEXTRMUW. */
21670 if (opint > 1 || opint < 0)
21671 error ("the range of selector should be in 0 to 1");
21675 || GET_MODE (target) != tmode
21676 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21677 target = gen_reg_rtx (tmode);
21678 pat = GEN_FCN (icode) (target, op0, op1);
21684 case ARM_BUILTIN_WALIGNI:
21685 /* If op2 is immediate, call walighi, else call walighr. */
21686 arg0 = CALL_EXPR_ARG (exp, 0);
21687 arg1 = CALL_EXPR_ARG (exp, 1);
21688 arg2 = CALL_EXPR_ARG (exp, 2);
21689 op0 = expand_normal (arg0);
21690 op1 = expand_normal (arg1);
21691 op2 = expand_normal (arg2);
21692 if (CONST_INT_P (op2))
21694 icode = CODE_FOR_iwmmxt_waligni;
21695 tmode = insn_data[icode].operand[0].mode;
21696 mode0 = insn_data[icode].operand[1].mode;
21697 mode1 = insn_data[icode].operand[2].mode;
21698 mode2 = insn_data[icode].operand[3].mode;
21699 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
21700 op0 = copy_to_mode_reg (mode0, op0);
21701 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
21702 op1 = copy_to_mode_reg (mode1, op1);
21703 gcc_assert ((*insn_data[icode].operand[3].predicate) (op2, mode2));
21704 selector = INTVAL (op2);
21705 if (selector > 7 || selector < 0)
21706 error ("the range of selector should be in 0 to 7");
21710 icode = CODE_FOR_iwmmxt_walignr;
21711 tmode = insn_data[icode].operand[0].mode;
21712 mode0 = insn_data[icode].operand[1].mode;
21713 mode1 = insn_data[icode].operand[2].mode;
21714 mode2 = insn_data[icode].operand[3].mode;
21715 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
21716 op0 = copy_to_mode_reg (mode0, op0);
21717 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
21718 op1 = copy_to_mode_reg (mode1, op1);
21719 if (!(*insn_data[icode].operand[3].predicate) (op2, mode2))
21720 op2 = copy_to_mode_reg (mode2, op2);
21723 || GET_MODE (target) != tmode
21724 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
21725 target = gen_reg_rtx (tmode);
21726 pat = GEN_FCN (icode) (target, op0, op1, op2);
21732 case ARM_BUILTIN_TINSRB:
21733 case ARM_BUILTIN_TINSRH:
21734 case ARM_BUILTIN_TINSRW:
21735 case ARM_BUILTIN_WMERGE:
21736 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
21737 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
21738 : fcode == ARM_BUILTIN_WMERGE ? CODE_FOR_iwmmxt_wmerge
21739 : CODE_FOR_iwmmxt_tinsrw);
21740 arg0 = CALL_EXPR_ARG (exp, 0);
21741 arg1 = CALL_EXPR_ARG (exp, 1);
21742 arg2 = CALL_EXPR_ARG (exp, 2);
21743 op0 = expand_normal (arg0);
21744 op1 = expand_normal (arg1);
21745 op2 = expand_normal (arg2);
21746 tmode = insn_data[icode].operand[0].mode;
21747 mode0 = insn_data[icode].operand[1].mode;
21748 mode1 = insn_data[icode].operand[2].mode;
21749 mode2 = insn_data[icode].operand[3].mode;
21751 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21752 op0 = copy_to_mode_reg (mode0, op0);
21753 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
21754 op1 = copy_to_mode_reg (mode1, op1);
21755 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
21757 error ("selector must be an immediate");
21760 if (icode == CODE_FOR_iwmmxt_wmerge)
21762 selector = INTVAL (op2);
21763 if (selector > 7 || selector < 0)
21764 error ("the range of selector should be in 0 to 7");
21766 if ((icode == CODE_FOR_iwmmxt_tinsrb)
21767 || (icode == CODE_FOR_iwmmxt_tinsrh)
21768 || (icode == CODE_FOR_iwmmxt_tinsrw))
21771 selector= INTVAL (op2);
21772 if (icode == CODE_FOR_iwmmxt_tinsrb && (selector < 0 || selector > 7))
21773 error ("the range of selector should be in 0 to 7");
21774 else if (icode == CODE_FOR_iwmmxt_tinsrh && (selector < 0 ||selector > 3))
21775 error ("the range of selector should be in 0 to 3");
21776 else if (icode == CODE_FOR_iwmmxt_tinsrw && (selector < 0 ||selector > 1))
21777 error ("the range of selector should be in 0 to 1");
21779 op2 = GEN_INT (mask);
21782 || GET_MODE (target) != tmode
21783 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21784 target = gen_reg_rtx (tmode);
21785 pat = GEN_FCN (icode) (target, op0, op1, op2);
21791 case ARM_BUILTIN_SETWCGR0:
21792 case ARM_BUILTIN_SETWCGR1:
21793 case ARM_BUILTIN_SETWCGR2:
21794 case ARM_BUILTIN_SETWCGR3:
21795 icode = (fcode == ARM_BUILTIN_SETWCGR0 ? CODE_FOR_iwmmxt_setwcgr0
21796 : fcode == ARM_BUILTIN_SETWCGR1 ? CODE_FOR_iwmmxt_setwcgr1
21797 : fcode == ARM_BUILTIN_SETWCGR2 ? CODE_FOR_iwmmxt_setwcgr2
21798 : CODE_FOR_iwmmxt_setwcgr3);
21799 arg0 = CALL_EXPR_ARG (exp, 0);
21800 op0 = expand_normal (arg0);
21801 mode0 = insn_data[icode].operand[0].mode;
21802 if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
21803 op0 = copy_to_mode_reg (mode0, op0);
21804 pat = GEN_FCN (icode) (op0);
21810 case ARM_BUILTIN_GETWCGR0:
21811 case ARM_BUILTIN_GETWCGR1:
21812 case ARM_BUILTIN_GETWCGR2:
21813 case ARM_BUILTIN_GETWCGR3:
21814 icode = (fcode == ARM_BUILTIN_GETWCGR0 ? CODE_FOR_iwmmxt_getwcgr0
21815 : fcode == ARM_BUILTIN_GETWCGR1 ? CODE_FOR_iwmmxt_getwcgr1
21816 : fcode == ARM_BUILTIN_GETWCGR2 ? CODE_FOR_iwmmxt_getwcgr2
21817 : CODE_FOR_iwmmxt_getwcgr3);
21818 tmode = insn_data[icode].operand[0].mode;
21820 || GET_MODE (target) != tmode
21821 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
21822 target = gen_reg_rtx (tmode);
21823 pat = GEN_FCN (icode) (target);
21829 case ARM_BUILTIN_WSHUFH:
21830 icode = CODE_FOR_iwmmxt_wshufh;
21831 arg0 = CALL_EXPR_ARG (exp, 0);
21832 arg1 = CALL_EXPR_ARG (exp, 1);
21833 op0 = expand_normal (arg0);
21834 op1 = expand_normal (arg1);
21835 tmode = insn_data[icode].operand[0].mode;
21836 mode1 = insn_data[icode].operand[1].mode;
21837 mode2 = insn_data[icode].operand[2].mode;
21839 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21840 op0 = copy_to_mode_reg (mode1, op0);
21841 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21843 error ("mask must be an immediate");
21846 selector = INTVAL (op1);
21847 if (selector < 0 || selector > 255)
21848 error ("the range of mask should be in 0 to 255");
21850 || GET_MODE (target) != tmode
21851 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21852 target = gen_reg_rtx (tmode);
21853 pat = GEN_FCN (icode) (target, op0, op1);
21859 case ARM_BUILTIN_WMADDS:
21860 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmadds, exp, target);
21861 case ARM_BUILTIN_WMADDSX:
21862 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsx, exp, target);
21863 case ARM_BUILTIN_WMADDSN:
21864 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsn, exp, target);
21865 case ARM_BUILTIN_WMADDU:
21866 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddu, exp, target);
21867 case ARM_BUILTIN_WMADDUX:
21868 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddux, exp, target);
21869 case ARM_BUILTIN_WMADDUN:
21870 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddun, exp, target);
21871 case ARM_BUILTIN_WSADBZ:
21872 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
21873 case ARM_BUILTIN_WSADHZ:
21874 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target);
21876 /* Several three-argument builtins. */
21877 case ARM_BUILTIN_WMACS:
21878 case ARM_BUILTIN_WMACU:
21879 case ARM_BUILTIN_TMIA:
21880 case ARM_BUILTIN_TMIAPH:
21881 case ARM_BUILTIN_TMIATT:
21882 case ARM_BUILTIN_TMIATB:
21883 case ARM_BUILTIN_TMIABT:
21884 case ARM_BUILTIN_TMIABB:
21885 case ARM_BUILTIN_WQMIABB:
21886 case ARM_BUILTIN_WQMIABT:
21887 case ARM_BUILTIN_WQMIATB:
21888 case ARM_BUILTIN_WQMIATT:
21889 case ARM_BUILTIN_WQMIABBN:
21890 case ARM_BUILTIN_WQMIABTN:
21891 case ARM_BUILTIN_WQMIATBN:
21892 case ARM_BUILTIN_WQMIATTN:
21893 case ARM_BUILTIN_WMIABB:
21894 case ARM_BUILTIN_WMIABT:
21895 case ARM_BUILTIN_WMIATB:
21896 case ARM_BUILTIN_WMIATT:
21897 case ARM_BUILTIN_WMIABBN:
21898 case ARM_BUILTIN_WMIABTN:
21899 case ARM_BUILTIN_WMIATBN:
21900 case ARM_BUILTIN_WMIATTN:
21901 case ARM_BUILTIN_WMIAWBB:
21902 case ARM_BUILTIN_WMIAWBT:
21903 case ARM_BUILTIN_WMIAWTB:
21904 case ARM_BUILTIN_WMIAWTT:
21905 case ARM_BUILTIN_WMIAWBBN:
21906 case ARM_BUILTIN_WMIAWBTN:
21907 case ARM_BUILTIN_WMIAWTBN:
21908 case ARM_BUILTIN_WMIAWTTN:
21909 case ARM_BUILTIN_WSADB:
21910 case ARM_BUILTIN_WSADH:
21911 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
21912 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
21913 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
21914 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
21915 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
21916 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
21917 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
21918 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
21919 : fcode == ARM_BUILTIN_WQMIABB ? CODE_FOR_iwmmxt_wqmiabb
21920 : fcode == ARM_BUILTIN_WQMIABT ? CODE_FOR_iwmmxt_wqmiabt
21921 : fcode == ARM_BUILTIN_WQMIATB ? CODE_FOR_iwmmxt_wqmiatb
21922 : fcode == ARM_BUILTIN_WQMIATT ? CODE_FOR_iwmmxt_wqmiatt
21923 : fcode == ARM_BUILTIN_WQMIABBN ? CODE_FOR_iwmmxt_wqmiabbn
21924 : fcode == ARM_BUILTIN_WQMIABTN ? CODE_FOR_iwmmxt_wqmiabtn
21925 : fcode == ARM_BUILTIN_WQMIATBN ? CODE_FOR_iwmmxt_wqmiatbn
21926 : fcode == ARM_BUILTIN_WQMIATTN ? CODE_FOR_iwmmxt_wqmiattn
21927 : fcode == ARM_BUILTIN_WMIABB ? CODE_FOR_iwmmxt_wmiabb
21928 : fcode == ARM_BUILTIN_WMIABT ? CODE_FOR_iwmmxt_wmiabt
21929 : fcode == ARM_BUILTIN_WMIATB ? CODE_FOR_iwmmxt_wmiatb
21930 : fcode == ARM_BUILTIN_WMIATT ? CODE_FOR_iwmmxt_wmiatt
21931 : fcode == ARM_BUILTIN_WMIABBN ? CODE_FOR_iwmmxt_wmiabbn
21932 : fcode == ARM_BUILTIN_WMIABTN ? CODE_FOR_iwmmxt_wmiabtn
21933 : fcode == ARM_BUILTIN_WMIATBN ? CODE_FOR_iwmmxt_wmiatbn
21934 : fcode == ARM_BUILTIN_WMIATTN ? CODE_FOR_iwmmxt_wmiattn
21935 : fcode == ARM_BUILTIN_WMIAWBB ? CODE_FOR_iwmmxt_wmiawbb
21936 : fcode == ARM_BUILTIN_WMIAWBT ? CODE_FOR_iwmmxt_wmiawbt
21937 : fcode == ARM_BUILTIN_WMIAWTB ? CODE_FOR_iwmmxt_wmiawtb
21938 : fcode == ARM_BUILTIN_WMIAWTT ? CODE_FOR_iwmmxt_wmiawtt
21939 : fcode == ARM_BUILTIN_WMIAWBBN ? CODE_FOR_iwmmxt_wmiawbbn
21940 : fcode == ARM_BUILTIN_WMIAWBTN ? CODE_FOR_iwmmxt_wmiawbtn
21941 : fcode == ARM_BUILTIN_WMIAWTBN ? CODE_FOR_iwmmxt_wmiawtbn
21942 : fcode == ARM_BUILTIN_WMIAWTTN ? CODE_FOR_iwmmxt_wmiawttn
21943 : fcode == ARM_BUILTIN_WSADB ? CODE_FOR_iwmmxt_wsadb
21944 : CODE_FOR_iwmmxt_wsadh);
21945 arg0 = CALL_EXPR_ARG (exp, 0);
21946 arg1 = CALL_EXPR_ARG (exp, 1);
21947 arg2 = CALL_EXPR_ARG (exp, 2);
21948 op0 = expand_normal (arg0);
21949 op1 = expand_normal (arg1);
21950 op2 = expand_normal (arg2);
21951 tmode = insn_data[icode].operand[0].mode;
21952 mode0 = insn_data[icode].operand[1].mode;
21953 mode1 = insn_data[icode].operand[2].mode;
21954 mode2 = insn_data[icode].operand[3].mode;
21956 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21957 op0 = copy_to_mode_reg (mode0, op0);
21958 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
21959 op1 = copy_to_mode_reg (mode1, op1);
21960 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
21961 op2 = copy_to_mode_reg (mode2, op2);
21963 || GET_MODE (target) != tmode
21964 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21965 target = gen_reg_rtx (tmode);
21966 pat = GEN_FCN (icode) (target, op0, op1, op2);
21972 case ARM_BUILTIN_WZERO:
21973 target = gen_reg_rtx (DImode);
21974 emit_insn (gen_iwmmxt_clrdi (target));
21977 case ARM_BUILTIN_WSRLHI:
21978 case ARM_BUILTIN_WSRLWI:
21979 case ARM_BUILTIN_WSRLDI:
21980 case ARM_BUILTIN_WSLLHI:
21981 case ARM_BUILTIN_WSLLWI:
21982 case ARM_BUILTIN_WSLLDI:
21983 case ARM_BUILTIN_WSRAHI:
21984 case ARM_BUILTIN_WSRAWI:
21985 case ARM_BUILTIN_WSRADI:
21986 case ARM_BUILTIN_WRORHI:
21987 case ARM_BUILTIN_WRORWI:
21988 case ARM_BUILTIN_WRORDI:
21989 case ARM_BUILTIN_WSRLH:
21990 case ARM_BUILTIN_WSRLW:
21991 case ARM_BUILTIN_WSRLD:
21992 case ARM_BUILTIN_WSLLH:
21993 case ARM_BUILTIN_WSLLW:
21994 case ARM_BUILTIN_WSLLD:
21995 case ARM_BUILTIN_WSRAH:
21996 case ARM_BUILTIN_WSRAW:
21997 case ARM_BUILTIN_WSRAD:
21998 case ARM_BUILTIN_WRORH:
21999 case ARM_BUILTIN_WRORW:
22000 case ARM_BUILTIN_WRORD:
22001 icode = (fcode == ARM_BUILTIN_WSRLHI ? CODE_FOR_lshrv4hi3_iwmmxt
22002 : fcode == ARM_BUILTIN_WSRLWI ? CODE_FOR_lshrv2si3_iwmmxt
22003 : fcode == ARM_BUILTIN_WSRLDI ? CODE_FOR_lshrdi3_iwmmxt
22004 : fcode == ARM_BUILTIN_WSLLHI ? CODE_FOR_ashlv4hi3_iwmmxt
22005 : fcode == ARM_BUILTIN_WSLLWI ? CODE_FOR_ashlv2si3_iwmmxt
22006 : fcode == ARM_BUILTIN_WSLLDI ? CODE_FOR_ashldi3_iwmmxt
22007 : fcode == ARM_BUILTIN_WSRAHI ? CODE_FOR_ashrv4hi3_iwmmxt
22008 : fcode == ARM_BUILTIN_WSRAWI ? CODE_FOR_ashrv2si3_iwmmxt
22009 : fcode == ARM_BUILTIN_WSRADI ? CODE_FOR_ashrdi3_iwmmxt
22010 : fcode == ARM_BUILTIN_WRORHI ? CODE_FOR_rorv4hi3
22011 : fcode == ARM_BUILTIN_WRORWI ? CODE_FOR_rorv2si3
22012 : fcode == ARM_BUILTIN_WRORDI ? CODE_FOR_rordi3
22013 : fcode == ARM_BUILTIN_WSRLH ? CODE_FOR_lshrv4hi3_di
22014 : fcode == ARM_BUILTIN_WSRLW ? CODE_FOR_lshrv2si3_di
22015 : fcode == ARM_BUILTIN_WSRLD ? CODE_FOR_lshrdi3_di
22016 : fcode == ARM_BUILTIN_WSLLH ? CODE_FOR_ashlv4hi3_di
22017 : fcode == ARM_BUILTIN_WSLLW ? CODE_FOR_ashlv2si3_di
22018 : fcode == ARM_BUILTIN_WSLLD ? CODE_FOR_ashldi3_di
22019 : fcode == ARM_BUILTIN_WSRAH ? CODE_FOR_ashrv4hi3_di
22020 : fcode == ARM_BUILTIN_WSRAW ? CODE_FOR_ashrv2si3_di
22021 : fcode == ARM_BUILTIN_WSRAD ? CODE_FOR_ashrdi3_di
22022 : fcode == ARM_BUILTIN_WRORH ? CODE_FOR_rorv4hi3_di
22023 : fcode == ARM_BUILTIN_WRORW ? CODE_FOR_rorv2si3_di
22024 : fcode == ARM_BUILTIN_WRORD ? CODE_FOR_rordi3_di
22025 : CODE_FOR_nothing);
22026 arg1 = CALL_EXPR_ARG (exp, 1);
22027 op1 = expand_normal (arg1);
22028 if (GET_MODE (op1) == VOIDmode)
22030 imm = INTVAL (op1);
22031 if ((fcode == ARM_BUILTIN_WRORHI || fcode == ARM_BUILTIN_WRORWI
22032 || fcode == ARM_BUILTIN_WRORH || fcode == ARM_BUILTIN_WRORW)
22033 && (imm < 0 || imm > 32))
22035 if (fcode == ARM_BUILTIN_WRORHI)
22036 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi16 in code.");
22037 else if (fcode == ARM_BUILTIN_WRORWI)
22038 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi32 in code.");
22039 else if (fcode == ARM_BUILTIN_WRORH)
22040 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi16 in code.");
22042 error ("the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi32 in code.");
22044 else if ((fcode == ARM_BUILTIN_WRORDI || fcode == ARM_BUILTIN_WRORD)
22045 && (imm < 0 || imm > 64))
22047 if (fcode == ARM_BUILTIN_WRORDI)
22048 error ("the range of count should be in 0 to 64. please check the intrinsic _mm_rori_si64 in code.");
22050 error ("the range of count should be in 0 to 64. please check the intrinsic _mm_ror_si64 in code.");
22054 if (fcode == ARM_BUILTIN_WSRLHI)
22055 error ("the count should be no less than 0. please check the intrinsic _mm_srli_pi16 in code.");
22056 else if (fcode == ARM_BUILTIN_WSRLWI)
22057 error ("the count should be no less than 0. please check the intrinsic _mm_srli_pi32 in code.");
22058 else if (fcode == ARM_BUILTIN_WSRLDI)
22059 error ("the count should be no less than 0. please check the intrinsic _mm_srli_si64 in code.");
22060 else if (fcode == ARM_BUILTIN_WSLLHI)
22061 error ("the count should be no less than 0. please check the intrinsic _mm_slli_pi16 in code.");
22062 else if (fcode == ARM_BUILTIN_WSLLWI)
22063 error ("the count should be no less than 0. please check the intrinsic _mm_slli_pi32 in code.");
22064 else if (fcode == ARM_BUILTIN_WSLLDI)
22065 error ("the count should be no less than 0. please check the intrinsic _mm_slli_si64 in code.");
22066 else if (fcode == ARM_BUILTIN_WSRAHI)
22067 error ("the count should be no less than 0. please check the intrinsic _mm_srai_pi16 in code.");
22068 else if (fcode == ARM_BUILTIN_WSRAWI)
22069 error ("the count should be no less than 0. please check the intrinsic _mm_srai_pi32 in code.");
22070 else if (fcode == ARM_BUILTIN_WSRADI)
22071 error ("the count should be no less than 0. please check the intrinsic _mm_srai_si64 in code.");
22072 else if (fcode == ARM_BUILTIN_WSRLH)
22073 error ("the count should be no less than 0. please check the intrinsic _mm_srl_pi16 in code.");
22074 else if (fcode == ARM_BUILTIN_WSRLW)
22075 error ("the count should be no less than 0. please check the intrinsic _mm_srl_pi32 in code.");
22076 else if (fcode == ARM_BUILTIN_WSRLD)
22077 error ("the count should be no less than 0. please check the intrinsic _mm_srl_si64 in code.");
22078 else if (fcode == ARM_BUILTIN_WSLLH)
22079 error ("the count should be no less than 0. please check the intrinsic _mm_sll_pi16 in code.");
22080 else if (fcode == ARM_BUILTIN_WSLLW)
22081 error ("the count should be no less than 0. please check the intrinsic _mm_sll_pi32 in code.");
22082 else if (fcode == ARM_BUILTIN_WSLLD)
22083 error ("the count should be no less than 0. please check the intrinsic _mm_sll_si64 in code.");
22084 else if (fcode == ARM_BUILTIN_WSRAH)
22085 error ("the count should be no less than 0. please check the intrinsic _mm_sra_pi16 in code.");
22086 else if (fcode == ARM_BUILTIN_WSRAW)
22087 error ("the count should be no less than 0. please check the intrinsic _mm_sra_pi32 in code.");
22089 error ("the count should be no less than 0. please check the intrinsic _mm_sra_si64 in code.");
22092 return arm_expand_binop_builtin (icode, exp, target);
22098 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
22099 if (d->code == (const enum arm_builtins) fcode)
22100 return arm_expand_binop_builtin (d->icode, exp, target);
22102 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
22103 if (d->code == (const enum arm_builtins) fcode)
22104 return arm_expand_unop_builtin (d->icode, exp, target, 0);
22106 /* @@@ Should really do something sensible here. */
22110 /* Return the number (counting from 0) of
22111 the least significant set bit in MASK. */
22114 number_of_first_bit_set (unsigned mask)
22116 return ctz_hwi (mask);
22119 /* Like emit_multi_reg_push, but allowing for a different set of
22120 registers to be described as saved. MASK is the set of registers
22121 to be saved; REAL_REGS is the set of registers to be described as
22122 saved. If REAL_REGS is 0, only describe the stack adjustment. */
22125 thumb1_emit_multi_reg_push (unsigned long mask, unsigned long real_regs)
22127 unsigned long regno;
22128 rtx par[10], tmp, reg, insn;
22131 /* Build the parallel of the registers actually being stored. */
22132 for (i = 0; mask; ++i, mask &= mask - 1)
22134 regno = ctz_hwi (mask);
22135 reg = gen_rtx_REG (SImode, regno);
22138 tmp = gen_rtx_UNSPEC (BLKmode, gen_rtvec (1, reg), UNSPEC_PUSH_MULT);
22140 tmp = gen_rtx_USE (VOIDmode, reg);
22145 tmp = plus_constant (Pmode, stack_pointer_rtx, -4 * i);
22146 tmp = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, tmp);
22147 tmp = gen_frame_mem (BLKmode, tmp);
22148 tmp = gen_rtx_SET (VOIDmode, tmp, par[0]);
22151 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (i, par));
22152 insn = emit_insn (tmp);
22154 /* Always build the stack adjustment note for unwind info. */
22155 tmp = plus_constant (Pmode, stack_pointer_rtx, -4 * i);
22156 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp);
22159 /* Build the parallel of the registers recorded as saved for unwind. */
22160 for (j = 0; real_regs; ++j, real_regs &= real_regs - 1)
22162 regno = ctz_hwi (real_regs);
22163 reg = gen_rtx_REG (SImode, regno);
22165 tmp = plus_constant (Pmode, stack_pointer_rtx, j * 4);
22166 tmp = gen_frame_mem (SImode, tmp);
22167 tmp = gen_rtx_SET (VOIDmode, tmp, reg);
22168 RTX_FRAME_RELATED_P (tmp) = 1;
22176 RTX_FRAME_RELATED_P (par[0]) = 1;
22177 tmp = gen_rtx_SEQUENCE (VOIDmode, gen_rtvec_v (j + 1, par));
22180 add_reg_note (insn, REG_FRAME_RELATED_EXPR, tmp);
22185 /* Emit code to push or pop registers to or from the stack. F is the
22186 assembly file. MASK is the registers to pop. */
22188 thumb_pop (FILE *f, unsigned long mask)
22191 int lo_mask = mask & 0xFF;
22192 int pushed_words = 0;
22196 if (lo_mask == 0 && (mask & (1 << PC_REGNUM)))
22198 /* Special case. Do not generate a POP PC statement here, do it in
22200 thumb_exit (f, -1);
22204 fprintf (f, "\tpop\t{");
22206 /* Look at the low registers first. */
22207 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
22211 asm_fprintf (f, "%r", regno);
22213 if ((lo_mask & ~1) != 0)
22220 if (mask & (1 << PC_REGNUM))
22222 /* Catch popping the PC. */
22223 if (TARGET_INTERWORK || TARGET_BACKTRACE
22224 || crtl->calls_eh_return)
22226 /* The PC is never poped directly, instead
22227 it is popped into r3 and then BX is used. */
22228 fprintf (f, "}\n");
22230 thumb_exit (f, -1);
22239 asm_fprintf (f, "%r", PC_REGNUM);
22243 fprintf (f, "}\n");
22246 /* Generate code to return from a thumb function.
22247 If 'reg_containing_return_addr' is -1, then the return address is
22248 actually on the stack, at the stack pointer. */
22250 thumb_exit (FILE *f, int reg_containing_return_addr)
22252 unsigned regs_available_for_popping;
22253 unsigned regs_to_pop;
22255 unsigned available;
22259 int restore_a4 = FALSE;
22261 /* Compute the registers we need to pop. */
22265 if (reg_containing_return_addr == -1)
22267 regs_to_pop |= 1 << LR_REGNUM;
22271 if (TARGET_BACKTRACE)
22273 /* Restore the (ARM) frame pointer and stack pointer. */
22274 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
22278 /* If there is nothing to pop then just emit the BX instruction and
22280 if (pops_needed == 0)
22282 if (crtl->calls_eh_return)
22283 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
22285 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
22288 /* Otherwise if we are not supporting interworking and we have not created
22289 a backtrace structure and the function was not entered in ARM mode then
22290 just pop the return address straight into the PC. */
22291 else if (!TARGET_INTERWORK
22292 && !TARGET_BACKTRACE
22293 && !is_called_in_ARM_mode (current_function_decl)
22294 && !crtl->calls_eh_return)
22296 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
22300 /* Find out how many of the (return) argument registers we can corrupt. */
22301 regs_available_for_popping = 0;
22303 /* If returning via __builtin_eh_return, the bottom three registers
22304 all contain information needed for the return. */
22305 if (crtl->calls_eh_return)
22309 /* If we can deduce the registers used from the function's
22310 return value. This is more reliable that examining
22311 df_regs_ever_live_p () because that will be set if the register is
22312 ever used in the function, not just if the register is used
22313 to hold a return value. */
22315 if (crtl->return_rtx != 0)
22316 mode = GET_MODE (crtl->return_rtx);
22318 mode = DECL_MODE (DECL_RESULT (current_function_decl));
22320 size = GET_MODE_SIZE (mode);
22324 /* In a void function we can use any argument register.
22325 In a function that returns a structure on the stack
22326 we can use the second and third argument registers. */
22327 if (mode == VOIDmode)
22328 regs_available_for_popping =
22329 (1 << ARG_REGISTER (1))
22330 | (1 << ARG_REGISTER (2))
22331 | (1 << ARG_REGISTER (3));
22333 regs_available_for_popping =
22334 (1 << ARG_REGISTER (2))
22335 | (1 << ARG_REGISTER (3));
22337 else if (size <= 4)
22338 regs_available_for_popping =
22339 (1 << ARG_REGISTER (2))
22340 | (1 << ARG_REGISTER (3));
22341 else if (size <= 8)
22342 regs_available_for_popping =
22343 (1 << ARG_REGISTER (3));
22346 /* Match registers to be popped with registers into which we pop them. */
22347 for (available = regs_available_for_popping,
22348 required = regs_to_pop;
22349 required != 0 && available != 0;
22350 available &= ~(available & - available),
22351 required &= ~(required & - required))
22354 /* If we have any popping registers left over, remove them. */
22356 regs_available_for_popping &= ~available;
22358 /* Otherwise if we need another popping register we can use
22359 the fourth argument register. */
22360 else if (pops_needed)
22362 /* If we have not found any free argument registers and
22363 reg a4 contains the return address, we must move it. */
22364 if (regs_available_for_popping == 0
22365 && reg_containing_return_addr == LAST_ARG_REGNUM)
22367 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
22368 reg_containing_return_addr = LR_REGNUM;
22370 else if (size > 12)
22372 /* Register a4 is being used to hold part of the return value,
22373 but we have dire need of a free, low register. */
22376 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
22379 if (reg_containing_return_addr != LAST_ARG_REGNUM)
22381 /* The fourth argument register is available. */
22382 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
22388 /* Pop as many registers as we can. */
22389 thumb_pop (f, regs_available_for_popping);
22391 /* Process the registers we popped. */
22392 if (reg_containing_return_addr == -1)
22394 /* The return address was popped into the lowest numbered register. */
22395 regs_to_pop &= ~(1 << LR_REGNUM);
22397 reg_containing_return_addr =
22398 number_of_first_bit_set (regs_available_for_popping);
22400 /* Remove this register for the mask of available registers, so that
22401 the return address will not be corrupted by further pops. */
22402 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
22405 /* If we popped other registers then handle them here. */
22406 if (regs_available_for_popping)
22410 /* Work out which register currently contains the frame pointer. */
22411 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
22413 /* Move it into the correct place. */
22414 asm_fprintf (f, "\tmov\t%r, %r\n",
22415 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
22417 /* (Temporarily) remove it from the mask of popped registers. */
22418 regs_available_for_popping &= ~(1 << frame_pointer);
22419 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
22421 if (regs_available_for_popping)
22425 /* We popped the stack pointer as well,
22426 find the register that contains it. */
22427 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
22429 /* Move it into the stack register. */
22430 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
22432 /* At this point we have popped all necessary registers, so
22433 do not worry about restoring regs_available_for_popping
22434 to its correct value:
22436 assert (pops_needed == 0)
22437 assert (regs_available_for_popping == (1 << frame_pointer))
22438 assert (regs_to_pop == (1 << STACK_POINTER)) */
22442 /* Since we have just move the popped value into the frame
22443 pointer, the popping register is available for reuse, and
22444 we know that we still have the stack pointer left to pop. */
22445 regs_available_for_popping |= (1 << frame_pointer);
22449 /* If we still have registers left on the stack, but we no longer have
22450 any registers into which we can pop them, then we must move the return
22451 address into the link register and make available the register that
22453 if (regs_available_for_popping == 0 && pops_needed > 0)
22455 regs_available_for_popping |= 1 << reg_containing_return_addr;
22457 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
22458 reg_containing_return_addr);
22460 reg_containing_return_addr = LR_REGNUM;
22463 /* If we have registers left on the stack then pop some more.
22464 We know that at most we will want to pop FP and SP. */
22465 if (pops_needed > 0)
22470 thumb_pop (f, regs_available_for_popping);
22472 /* We have popped either FP or SP.
22473 Move whichever one it is into the correct register. */
22474 popped_into = number_of_first_bit_set (regs_available_for_popping);
22475 move_to = number_of_first_bit_set (regs_to_pop);
22477 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
22479 regs_to_pop &= ~(1 << move_to);
22484 /* If we still have not popped everything then we must have only
22485 had one register available to us and we are now popping the SP. */
22486 if (pops_needed > 0)
22490 thumb_pop (f, regs_available_for_popping);
22492 popped_into = number_of_first_bit_set (regs_available_for_popping);
22494 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
22496 assert (regs_to_pop == (1 << STACK_POINTER))
22497 assert (pops_needed == 1)
22501 /* If necessary restore the a4 register. */
22504 if (reg_containing_return_addr != LR_REGNUM)
22506 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
22507 reg_containing_return_addr = LR_REGNUM;
22510 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
22513 if (crtl->calls_eh_return)
22514 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
22516 /* Return to caller. */
22517 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
22520 /* Scan INSN just before assembler is output for it.
22521 For Thumb-1, we track the status of the condition codes; this
22522 information is used in the cbranchsi4_insn pattern. */
22524 thumb1_final_prescan_insn (rtx insn)
22526 if (flag_print_asm_name)
22527 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
22528 INSN_ADDRESSES (INSN_UID (insn)));
22529 /* Don't overwrite the previous setter when we get to a cbranch. */
22530 if (INSN_CODE (insn) != CODE_FOR_cbranchsi4_insn)
22532 enum attr_conds conds;
22534 if (cfun->machine->thumb1_cc_insn)
22536 if (modified_in_p (cfun->machine->thumb1_cc_op0, insn)
22537 || modified_in_p (cfun->machine->thumb1_cc_op1, insn))
22540 conds = get_attr_conds (insn);
22541 if (conds == CONDS_SET)
22543 rtx set = single_set (insn);
22544 cfun->machine->thumb1_cc_insn = insn;
22545 cfun->machine->thumb1_cc_op0 = SET_DEST (set);
22546 cfun->machine->thumb1_cc_op1 = const0_rtx;
22547 cfun->machine->thumb1_cc_mode = CC_NOOVmode;
22548 if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn)
22550 rtx src1 = XEXP (SET_SRC (set), 1);
22551 if (src1 == const0_rtx)
22552 cfun->machine->thumb1_cc_mode = CCmode;
22554 else if (REG_P (SET_DEST (set)) && REG_P (SET_SRC (set)))
22556 /* Record the src register operand instead of dest because
22557 cprop_hardreg pass propagates src. */
22558 cfun->machine->thumb1_cc_op0 = SET_SRC (set);
22561 else if (conds != CONDS_NOCOND)
22562 cfun->machine->thumb1_cc_insn = NULL_RTX;
22567 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
22569 unsigned HOST_WIDE_INT mask = 0xff;
22572 val = val & (unsigned HOST_WIDE_INT)0xffffffffu;
22573 if (val == 0) /* XXX */
22576 for (i = 0; i < 25; i++)
22577 if ((val & (mask << i)) == val)
22583 /* Returns nonzero if the current function contains,
22584 or might contain a far jump. */
22586 thumb_far_jump_used_p (void)
22590 /* This test is only important for leaf functions. */
22591 /* assert (!leaf_function_p ()); */
22593 /* If we have already decided that far jumps may be used,
22594 do not bother checking again, and always return true even if
22595 it turns out that they are not being used. Once we have made
22596 the decision that far jumps are present (and that hence the link
22597 register will be pushed onto the stack) we cannot go back on it. */
22598 if (cfun->machine->far_jump_used)
22601 /* If this function is not being called from the prologue/epilogue
22602 generation code then it must be being called from the
22603 INITIAL_ELIMINATION_OFFSET macro. */
22604 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
22606 /* In this case we know that we are being asked about the elimination
22607 of the arg pointer register. If that register is not being used,
22608 then there are no arguments on the stack, and we do not have to
22609 worry that a far jump might force the prologue to push the link
22610 register, changing the stack offsets. In this case we can just
22611 return false, since the presence of far jumps in the function will
22612 not affect stack offsets.
22614 If the arg pointer is live (or if it was live, but has now been
22615 eliminated and so set to dead) then we do have to test to see if
22616 the function might contain a far jump. This test can lead to some
22617 false negatives, since before reload is completed, then length of
22618 branch instructions is not known, so gcc defaults to returning their
22619 longest length, which in turn sets the far jump attribute to true.
22621 A false negative will not result in bad code being generated, but it
22622 will result in a needless push and pop of the link register. We
22623 hope that this does not occur too often.
22625 If we need doubleword stack alignment this could affect the other
22626 elimination offsets so we can't risk getting it wrong. */
22627 if (df_regs_ever_live_p (ARG_POINTER_REGNUM))
22628 cfun->machine->arg_pointer_live = 1;
22629 else if (!cfun->machine->arg_pointer_live)
22633 /* Check to see if the function contains a branch
22634 insn with the far jump attribute set. */
22635 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
22638 /* Ignore tablejump patterns. */
22639 && GET_CODE (PATTERN (insn)) != ADDR_VEC
22640 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
22641 && get_attr_far_jump (insn) == FAR_JUMP_YES
22644 /* Record the fact that we have decided that
22645 the function does use far jumps. */
22646 cfun->machine->far_jump_used = 1;
22654 /* Return nonzero if FUNC must be entered in ARM mode. */
22656 is_called_in_ARM_mode (tree func)
22658 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
22660 /* Ignore the problem about functions whose address is taken. */
22661 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
22665 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
22671 /* Given the stack offsets and register mask in OFFSETS, decide how
22672 many additional registers to push instead of subtracting a constant
22673 from SP. For epilogues the principle is the same except we use pop.
22674 FOR_PROLOGUE indicates which we're generating. */
22676 thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue)
22678 HOST_WIDE_INT amount;
22679 unsigned long live_regs_mask = offsets->saved_regs_mask;
22680 /* Extract a mask of the ones we can give to the Thumb's push/pop
22682 unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff);
22683 /* Then count how many other high registers will need to be pushed. */
22684 unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
22685 int n_free, reg_base, size;
22687 if (!for_prologue && frame_pointer_needed)
22688 amount = offsets->locals_base - offsets->saved_regs;
22690 amount = offsets->outgoing_args - offsets->saved_regs;
22692 /* If the stack frame size is 512 exactly, we can save one load
22693 instruction, which should make this a win even when optimizing
22695 if (!optimize_size && amount != 512)
22698 /* Can't do this if there are high registers to push. */
22699 if (high_regs_pushed != 0)
22702 /* Shouldn't do it in the prologue if no registers would normally
22703 be pushed at all. In the epilogue, also allow it if we'll have
22704 a pop insn for the PC. */
22707 || TARGET_BACKTRACE
22708 || (live_regs_mask & 1 << LR_REGNUM) == 0
22709 || TARGET_INTERWORK
22710 || crtl->args.pretend_args_size != 0))
22713 /* Don't do this if thumb_expand_prologue wants to emit instructions
22714 between the push and the stack frame allocation. */
22716 && ((flag_pic && arm_pic_register != INVALID_REGNUM)
22717 || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)))
22724 size = arm_size_return_regs ();
22725 reg_base = ARM_NUM_INTS (size);
22726 live_regs_mask >>= reg_base;
22729 while (reg_base + n_free < 8 && !(live_regs_mask & 1)
22730 && (for_prologue || call_used_regs[reg_base + n_free]))
22732 live_regs_mask >>= 1;
22738 gcc_assert (amount / 4 * 4 == amount);
22740 if (amount >= 512 && (amount - n_free * 4) < 512)
22741 return (amount - 508) / 4;
22742 if (amount <= n_free * 4)
22747 /* The bits which aren't usefully expanded as rtl. */
22749 thumb1_unexpanded_epilogue (void)
22751 arm_stack_offsets *offsets;
22753 unsigned long live_regs_mask = 0;
22754 int high_regs_pushed = 0;
22756 int had_to_push_lr;
22759 if (cfun->machine->return_used_this_function != 0)
22762 if (IS_NAKED (arm_current_func_type ()))
22765 offsets = arm_get_frame_offsets ();
22766 live_regs_mask = offsets->saved_regs_mask;
22767 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
22769 /* If we can deduce the registers used from the function's return value.
22770 This is more reliable that examining df_regs_ever_live_p () because that
22771 will be set if the register is ever used in the function, not just if
22772 the register is used to hold a return value. */
22773 size = arm_size_return_regs ();
22775 extra_pop = thumb1_extra_regs_pushed (offsets, false);
22778 unsigned long extra_mask = (1 << extra_pop) - 1;
22779 live_regs_mask |= extra_mask << ARM_NUM_INTS (size);
22782 /* The prolog may have pushed some high registers to use as
22783 work registers. e.g. the testsuite file:
22784 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
22785 compiles to produce:
22786 push {r4, r5, r6, r7, lr}
22790 as part of the prolog. We have to undo that pushing here. */
22792 if (high_regs_pushed)
22794 unsigned long mask = live_regs_mask & 0xff;
22797 /* The available low registers depend on the size of the value we are
22805 /* Oh dear! We have no low registers into which we can pop
22808 ("no low registers available for popping high registers");
22810 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
22811 if (live_regs_mask & (1 << next_hi_reg))
22814 while (high_regs_pushed)
22816 /* Find lo register(s) into which the high register(s) can
22818 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
22820 if (mask & (1 << regno))
22821 high_regs_pushed--;
22822 if (high_regs_pushed == 0)
22826 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
22828 /* Pop the values into the low register(s). */
22829 thumb_pop (asm_out_file, mask);
22831 /* Move the value(s) into the high registers. */
22832 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
22834 if (mask & (1 << regno))
22836 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
22839 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
22840 if (live_regs_mask & (1 << next_hi_reg))
22845 live_regs_mask &= ~0x0f00;
22848 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
22849 live_regs_mask &= 0xff;
22851 if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE)
22853 /* Pop the return address into the PC. */
22854 if (had_to_push_lr)
22855 live_regs_mask |= 1 << PC_REGNUM;
22857 /* Either no argument registers were pushed or a backtrace
22858 structure was created which includes an adjusted stack
22859 pointer, so just pop everything. */
22860 if (live_regs_mask)
22861 thumb_pop (asm_out_file, live_regs_mask);
22863 /* We have either just popped the return address into the
22864 PC or it is was kept in LR for the entire function.
22865 Note that thumb_pop has already called thumb_exit if the
22866 PC was in the list. */
22867 if (!had_to_push_lr)
22868 thumb_exit (asm_out_file, LR_REGNUM);
22872 /* Pop everything but the return address. */
22873 if (live_regs_mask)
22874 thumb_pop (asm_out_file, live_regs_mask);
22876 if (had_to_push_lr)
22880 /* We have no free low regs, so save one. */
22881 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
22885 /* Get the return address into a temporary register. */
22886 thumb_pop (asm_out_file, 1 << LAST_ARG_REGNUM);
22890 /* Move the return address to lr. */
22891 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
22893 /* Restore the low register. */
22894 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
22899 regno = LAST_ARG_REGNUM;
22904 /* Remove the argument registers that were pushed onto the stack. */
22905 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
22906 SP_REGNUM, SP_REGNUM,
22907 crtl->args.pretend_args_size);
22909 thumb_exit (asm_out_file, regno);
22915 /* Functions to save and restore machine-specific function data. */
22916 static struct machine_function *
22917 arm_init_machine_status (void)
22919 struct machine_function *machine;
22920 machine = ggc_alloc_cleared_machine_function ();
22922 #if ARM_FT_UNKNOWN != 0
22923 machine->func_type = ARM_FT_UNKNOWN;
22928 /* Return an RTX indicating where the return address to the
22929 calling function can be found. */
22931 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
22936 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
22939 /* Do anything needed before RTL is emitted for each function. */
22941 arm_init_expanders (void)
22943 /* Arrange to initialize and mark the machine per-function status. */
22944 init_machine_status = arm_init_machine_status;
22946 /* This is to stop the combine pass optimizing away the alignment
22947 adjustment of va_arg. */
22948 /* ??? It is claimed that this should not be necessary. */
22950 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
22954 /* Like arm_compute_initial_elimination offset. Simpler because there
22955 isn't an ABI specified frame pointer for Thumb. Instead, we set it
22956 to point at the base of the local variables after static stack
22957 space for a function has been allocated. */
22960 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
22962 arm_stack_offsets *offsets;
22964 offsets = arm_get_frame_offsets ();
22968 case ARG_POINTER_REGNUM:
22971 case STACK_POINTER_REGNUM:
22972 return offsets->outgoing_args - offsets->saved_args;
22974 case FRAME_POINTER_REGNUM:
22975 return offsets->soft_frame - offsets->saved_args;
22977 case ARM_HARD_FRAME_POINTER_REGNUM:
22978 return offsets->saved_regs - offsets->saved_args;
22980 case THUMB_HARD_FRAME_POINTER_REGNUM:
22981 return offsets->locals_base - offsets->saved_args;
22984 gcc_unreachable ();
22988 case FRAME_POINTER_REGNUM:
22991 case STACK_POINTER_REGNUM:
22992 return offsets->outgoing_args - offsets->soft_frame;
22994 case ARM_HARD_FRAME_POINTER_REGNUM:
22995 return offsets->saved_regs - offsets->soft_frame;
22997 case THUMB_HARD_FRAME_POINTER_REGNUM:
22998 return offsets->locals_base - offsets->soft_frame;
23001 gcc_unreachable ();
23006 gcc_unreachable ();
23010 /* Generate the function's prologue. */
23013 thumb1_expand_prologue (void)
23017 HOST_WIDE_INT amount;
23018 arm_stack_offsets *offsets;
23019 unsigned long func_type;
23021 unsigned long live_regs_mask;
23022 unsigned long l_mask;
23023 unsigned high_regs_pushed = 0;
23025 func_type = arm_current_func_type ();
23027 /* Naked functions don't have prologues. */
23028 if (IS_NAKED (func_type))
23031 if (IS_INTERRUPT (func_type))
23033 error ("interrupt Service Routines cannot be coded in Thumb mode");
23037 if (is_called_in_ARM_mode (current_function_decl))
23038 emit_insn (gen_prologue_thumb1_interwork ());
23040 offsets = arm_get_frame_offsets ();
23041 live_regs_mask = offsets->saved_regs_mask;
23043 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
23044 l_mask = live_regs_mask & 0x40ff;
23045 /* Then count how many other high registers will need to be pushed. */
23046 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
23048 if (crtl->args.pretend_args_size)
23050 rtx x = GEN_INT (-crtl->args.pretend_args_size);
23052 if (cfun->machine->uses_anonymous_args)
23054 int num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size);
23055 unsigned long mask;
23057 mask = 1ul << (LAST_ARG_REGNUM + 1);
23058 mask -= 1ul << (LAST_ARG_REGNUM + 1 - num_pushes);
23060 insn = thumb1_emit_multi_reg_push (mask, 0);
23064 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
23065 stack_pointer_rtx, x));
23067 RTX_FRAME_RELATED_P (insn) = 1;
23070 if (TARGET_BACKTRACE)
23072 HOST_WIDE_INT offset = 0;
23073 unsigned work_register;
23074 rtx work_reg, x, arm_hfp_rtx;
23076 /* We have been asked to create a stack backtrace structure.
23077 The code looks like this:
23081 0 sub SP, #16 Reserve space for 4 registers.
23082 2 push {R7} Push low registers.
23083 4 add R7, SP, #20 Get the stack pointer before the push.
23084 6 str R7, [SP, #8] Store the stack pointer
23085 (before reserving the space).
23086 8 mov R7, PC Get hold of the start of this code + 12.
23087 10 str R7, [SP, #16] Store it.
23088 12 mov R7, FP Get hold of the current frame pointer.
23089 14 str R7, [SP, #4] Store it.
23090 16 mov R7, LR Get hold of the current return address.
23091 18 str R7, [SP, #12] Store it.
23092 20 add R7, SP, #16 Point at the start of the
23093 backtrace structure.
23094 22 mov FP, R7 Put this value into the frame pointer. */
23096 work_register = thumb_find_work_register (live_regs_mask);
23097 work_reg = gen_rtx_REG (SImode, work_register);
23098 arm_hfp_rtx = gen_rtx_REG (SImode, ARM_HARD_FRAME_POINTER_REGNUM);
23100 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
23101 stack_pointer_rtx, GEN_INT (-16)));
23102 RTX_FRAME_RELATED_P (insn) = 1;
23106 insn = thumb1_emit_multi_reg_push (l_mask, l_mask);
23107 RTX_FRAME_RELATED_P (insn) = 1;
23109 offset = bit_count (l_mask) * UNITS_PER_WORD;
23112 x = GEN_INT (offset + 16 + crtl->args.pretend_args_size);
23113 emit_insn (gen_addsi3 (work_reg, stack_pointer_rtx, x));
23115 x = plus_constant (Pmode, stack_pointer_rtx, offset + 4);
23116 x = gen_frame_mem (SImode, x);
23117 emit_move_insn (x, work_reg);
23119 /* Make sure that the instruction fetching the PC is in the right place
23120 to calculate "start of backtrace creation code + 12". */
23121 /* ??? The stores using the common WORK_REG ought to be enough to
23122 prevent the scheduler from doing anything weird. Failing that
23123 we could always move all of the following into an UNSPEC_VOLATILE. */
23126 x = gen_rtx_REG (SImode, PC_REGNUM);
23127 emit_move_insn (work_reg, x);
23129 x = plus_constant (Pmode, stack_pointer_rtx, offset + 12);
23130 x = gen_frame_mem (SImode, x);
23131 emit_move_insn (x, work_reg);
23133 emit_move_insn (work_reg, arm_hfp_rtx);
23135 x = plus_constant (Pmode, stack_pointer_rtx, offset);
23136 x = gen_frame_mem (SImode, x);
23137 emit_move_insn (x, work_reg);
23141 emit_move_insn (work_reg, arm_hfp_rtx);
23143 x = plus_constant (Pmode, stack_pointer_rtx, offset);
23144 x = gen_frame_mem (SImode, x);
23145 emit_move_insn (x, work_reg);
23147 x = gen_rtx_REG (SImode, PC_REGNUM);
23148 emit_move_insn (work_reg, x);
23150 x = plus_constant (Pmode, stack_pointer_rtx, offset + 12);
23151 x = gen_frame_mem (SImode, x);
23152 emit_move_insn (x, work_reg);
23155 x = gen_rtx_REG (SImode, LR_REGNUM);
23156 emit_move_insn (work_reg, x);
23158 x = plus_constant (Pmode, stack_pointer_rtx, offset + 8);
23159 x = gen_frame_mem (SImode, x);
23160 emit_move_insn (x, work_reg);
23162 x = GEN_INT (offset + 12);
23163 emit_insn (gen_addsi3 (work_reg, stack_pointer_rtx, x));
23165 emit_move_insn (arm_hfp_rtx, work_reg);
23167 /* Optimization: If we are not pushing any low registers but we are going
23168 to push some high registers then delay our first push. This will just
23169 be a push of LR and we can combine it with the push of the first high
23171 else if ((l_mask & 0xff) != 0
23172 || (high_regs_pushed == 0 && l_mask))
23174 unsigned long mask = l_mask;
23175 mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1;
23176 insn = thumb1_emit_multi_reg_push (mask, mask);
23177 RTX_FRAME_RELATED_P (insn) = 1;
23180 if (high_regs_pushed)
23182 unsigned pushable_regs;
23183 unsigned next_hi_reg;
23184 unsigned arg_regs_num = TARGET_AAPCS_BASED ? crtl->args.info.aapcs_ncrn
23185 : crtl->args.info.nregs;
23186 unsigned arg_regs_mask = (1 << arg_regs_num) - 1;
23188 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
23189 if (live_regs_mask & (1 << next_hi_reg))
23192 /* Here we need to mask out registers used for passing arguments
23193 even if they can be pushed. This is to avoid using them to stash the high
23194 registers. Such kind of stash may clobber the use of arguments. */
23195 pushable_regs = l_mask & (~arg_regs_mask) & 0xff;
23197 if (pushable_regs == 0)
23198 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
23200 while (high_regs_pushed > 0)
23202 unsigned long real_regs_mask = 0;
23204 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
23206 if (pushable_regs & (1 << regno))
23208 emit_move_insn (gen_rtx_REG (SImode, regno),
23209 gen_rtx_REG (SImode, next_hi_reg));
23211 high_regs_pushed --;
23212 real_regs_mask |= (1 << next_hi_reg);
23214 if (high_regs_pushed)
23216 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
23218 if (live_regs_mask & (1 << next_hi_reg))
23223 pushable_regs &= ~((1 << regno) - 1);
23229 /* If we had to find a work register and we have not yet
23230 saved the LR then add it to the list of regs to push. */
23231 if (l_mask == (1 << LR_REGNUM))
23233 pushable_regs |= l_mask;
23234 real_regs_mask |= l_mask;
23238 insn = thumb1_emit_multi_reg_push (pushable_regs, real_regs_mask);
23239 RTX_FRAME_RELATED_P (insn) = 1;
23243 /* Load the pic register before setting the frame pointer,
23244 so we can use r7 as a temporary work register. */
23245 if (flag_pic && arm_pic_register != INVALID_REGNUM)
23246 arm_load_pic_register (live_regs_mask);
23248 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
23249 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
23250 stack_pointer_rtx);
23252 if (flag_stack_usage_info)
23253 current_function_static_stack_size
23254 = offsets->outgoing_args - offsets->saved_args;
23256 amount = offsets->outgoing_args - offsets->saved_regs;
23257 amount -= 4 * thumb1_extra_regs_pushed (offsets, true);
23262 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
23263 GEN_INT (- amount)));
23264 RTX_FRAME_RELATED_P (insn) = 1;
23270 /* The stack decrement is too big for an immediate value in a single
23271 insn. In theory we could issue multiple subtracts, but after
23272 three of them it becomes more space efficient to place the full
23273 value in the constant pool and load into a register. (Also the
23274 ARM debugger really likes to see only one stack decrement per
23275 function). So instead we look for a scratch register into which
23276 we can load the decrement, and then we subtract this from the
23277 stack pointer. Unfortunately on the thumb the only available
23278 scratch registers are the argument registers, and we cannot use
23279 these as they may hold arguments to the function. Instead we
23280 attempt to locate a call preserved register which is used by this
23281 function. If we can find one, then we know that it will have
23282 been pushed at the start of the prologue and so we can corrupt
23284 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
23285 if (live_regs_mask & (1 << regno))
23288 gcc_assert(regno <= LAST_LO_REGNUM);
23290 reg = gen_rtx_REG (SImode, regno);
23292 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
23294 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
23295 stack_pointer_rtx, reg));
23297 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
23298 plus_constant (Pmode, stack_pointer_rtx,
23300 add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
23301 RTX_FRAME_RELATED_P (insn) = 1;
23305 if (frame_pointer_needed)
23306 thumb_set_frame_pointer (offsets);
23308 /* If we are profiling, make sure no instructions are scheduled before
23309 the call to mcount. Similarly if the user has requested no
23310 scheduling in the prolog. Similarly if we want non-call exceptions
23311 using the EABI unwinder, to prevent faulting instructions from being
23312 swapped with a stack adjustment. */
23313 if (crtl->profile || !TARGET_SCHED_PROLOG
23314 || (arm_except_unwind_info (&global_options) == UI_TARGET
23315 && cfun->can_throw_non_call_exceptions))
23316 emit_insn (gen_blockage ());
23318 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
23319 if (live_regs_mask & 0xff)
23320 cfun->machine->lr_save_eliminated = 0;
23323 /* Generate pattern *pop_multiple_with_stack_update_and_return if single
23324 POP instruction can be generated. LR should be replaced by PC. All
23325 the checks required are already done by USE_RETURN_INSN (). Hence,
23326 all we really need to check here is if single register is to be
23327 returned, or multiple register return. */
23329 thumb2_expand_return (void)
23332 unsigned long saved_regs_mask;
23333 arm_stack_offsets *offsets;
23335 offsets = arm_get_frame_offsets ();
23336 saved_regs_mask = offsets->saved_regs_mask;
23338 for (i = 0, num_regs = 0; i <= LAST_ARM_REGNUM; i++)
23339 if (saved_regs_mask & (1 << i))
23342 if (saved_regs_mask)
23346 rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
23347 rtx reg = gen_rtx_REG (SImode, PC_REGNUM);
23348 rtx addr = gen_rtx_MEM (SImode,
23349 gen_rtx_POST_INC (SImode,
23350 stack_pointer_rtx));
23351 set_mem_alias_set (addr, get_frame_alias_set ());
23352 XVECEXP (par, 0, 0) = ret_rtx;
23353 XVECEXP (par, 0, 1) = gen_rtx_SET (SImode, reg, addr);
23354 RTX_FRAME_RELATED_P (XVECEXP (par, 0, 1)) = 1;
23355 emit_jump_insn (par);
23359 saved_regs_mask &= ~ (1 << LR_REGNUM);
23360 saved_regs_mask |= (1 << PC_REGNUM);
23361 arm_emit_multi_reg_pop (saved_regs_mask);
23366 emit_jump_insn (simple_return_rtx);
23371 thumb1_expand_epilogue (void)
23373 HOST_WIDE_INT amount;
23374 arm_stack_offsets *offsets;
23377 /* Naked functions don't have prologues. */
23378 if (IS_NAKED (arm_current_func_type ()))
23381 offsets = arm_get_frame_offsets ();
23382 amount = offsets->outgoing_args - offsets->saved_regs;
23384 if (frame_pointer_needed)
23386 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
23387 amount = offsets->locals_base - offsets->saved_regs;
23389 amount -= 4 * thumb1_extra_regs_pushed (offsets, false);
23391 gcc_assert (amount >= 0);
23394 emit_insn (gen_blockage ());
23397 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
23398 GEN_INT (amount)));
23401 /* r3 is always free in the epilogue. */
23402 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
23404 emit_insn (gen_movsi (reg, GEN_INT (amount)));
23405 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
23409 /* Emit a USE (stack_pointer_rtx), so that
23410 the stack adjustment will not be deleted. */
23411 emit_insn (gen_force_register_use (stack_pointer_rtx));
23413 if (crtl->profile || !TARGET_SCHED_PROLOG)
23414 emit_insn (gen_blockage ());
23416 /* Emit a clobber for each insn that will be restored in the epilogue,
23417 so that flow2 will get register lifetimes correct. */
23418 for (regno = 0; regno < 13; regno++)
23419 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
23420 emit_clobber (gen_rtx_REG (SImode, regno));
23422 if (! df_regs_ever_live_p (LR_REGNUM))
23423 emit_use (gen_rtx_REG (SImode, LR_REGNUM));
23426 /* Epilogue code for APCS frame. */
23428 arm_expand_epilogue_apcs_frame (bool really_return)
23430 unsigned long func_type;
23431 unsigned long saved_regs_mask;
23434 int floats_from_frame = 0;
23435 arm_stack_offsets *offsets;
23437 gcc_assert (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM);
23438 func_type = arm_current_func_type ();
23440 /* Get frame offsets for ARM. */
23441 offsets = arm_get_frame_offsets ();
23442 saved_regs_mask = offsets->saved_regs_mask;
23444 /* Find the offset of the floating-point save area in the frame. */
23445 floats_from_frame = offsets->saved_args - offsets->frame;
23447 /* Compute how many core registers saved and how far away the floats are. */
23448 for (i = 0; i <= LAST_ARM_REGNUM; i++)
23449 if (saved_regs_mask & (1 << i))
23452 floats_from_frame += 4;
23455 if (TARGET_HARD_FLOAT && TARGET_VFP)
23459 /* The offset is from IP_REGNUM. */
23460 int saved_size = arm_get_vfp_saved_size ();
23461 if (saved_size > 0)
23463 floats_from_frame += saved_size;
23464 emit_insn (gen_addsi3 (gen_rtx_REG (SImode, IP_REGNUM),
23465 hard_frame_pointer_rtx,
23466 GEN_INT (-floats_from_frame)));
23469 /* Generate VFP register multi-pop. */
23470 start_reg = FIRST_VFP_REGNUM;
23472 for (i = FIRST_VFP_REGNUM; i < LAST_VFP_REGNUM; i += 2)
23473 /* Look for a case where a reg does not need restoring. */
23474 if ((!df_regs_ever_live_p (i) || call_used_regs[i])
23475 && (!df_regs_ever_live_p (i + 1)
23476 || call_used_regs[i + 1]))
23478 if (start_reg != i)
23479 arm_emit_vfp_multi_reg_pop (start_reg,
23480 (i - start_reg) / 2,
23481 gen_rtx_REG (SImode,
23486 /* Restore the remaining regs that we have discovered (or possibly
23487 even all of them, if the conditional in the for loop never
23489 if (start_reg != i)
23490 arm_emit_vfp_multi_reg_pop (start_reg,
23491 (i - start_reg) / 2,
23492 gen_rtx_REG (SImode, IP_REGNUM));
23497 /* The frame pointer is guaranteed to be non-double-word aligned, as
23498 it is set to double-word-aligned old_stack_pointer - 4. */
23500 int lrm_count = (num_regs % 2) ? (num_regs + 2) : (num_regs + 1);
23502 for (i = LAST_IWMMXT_REGNUM; i >= FIRST_IWMMXT_REGNUM; i--)
23503 if (df_regs_ever_live_p (i) && !call_used_regs[i])
23505 rtx addr = gen_frame_mem (V2SImode,
23506 plus_constant (Pmode, hard_frame_pointer_rtx,
23508 insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr));
23509 REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE,
23510 gen_rtx_REG (V2SImode, i),
23516 /* saved_regs_mask should contain IP which contains old stack pointer
23517 at the time of activation creation. Since SP and IP are adjacent registers,
23518 we can restore the value directly into SP. */
23519 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
23520 saved_regs_mask &= ~(1 << IP_REGNUM);
23521 saved_regs_mask |= (1 << SP_REGNUM);
23523 /* There are two registers left in saved_regs_mask - LR and PC. We
23524 only need to restore LR (the return address), but to
23525 save time we can load it directly into PC, unless we need a
23526 special function exit sequence, or we are not really returning. */
23528 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
23529 && !crtl->calls_eh_return)
23530 /* Delete LR from the register mask, so that LR on
23531 the stack is loaded into the PC in the register mask. */
23532 saved_regs_mask &= ~(1 << LR_REGNUM);
23534 saved_regs_mask &= ~(1 << PC_REGNUM);
23536 num_regs = bit_count (saved_regs_mask);
23537 if ((offsets->outgoing_args != (1 + num_regs)) || cfun->calls_alloca)
23539 /* Unwind the stack to just below the saved registers. */
23540 emit_insn (gen_addsi3 (stack_pointer_rtx,
23541 hard_frame_pointer_rtx,
23542 GEN_INT (- 4 * num_regs)));
23545 arm_emit_multi_reg_pop (saved_regs_mask);
23547 if (IS_INTERRUPT (func_type))
23549 /* Interrupt handlers will have pushed the
23550 IP onto the stack, so restore it now. */
23552 rtx addr = gen_rtx_MEM (SImode,
23553 gen_rtx_POST_INC (SImode,
23554 stack_pointer_rtx));
23555 set_mem_alias_set (addr, get_frame_alias_set ());
23556 insn = emit_insn (gen_movsi (gen_rtx_REG (SImode, IP_REGNUM), addr));
23557 REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE,
23558 gen_rtx_REG (SImode, IP_REGNUM),
23562 if (!really_return || (saved_regs_mask & (1 << PC_REGNUM)))
23565 if (crtl->calls_eh_return)
23566 emit_insn (gen_addsi3 (stack_pointer_rtx,
23568 GEN_INT (ARM_EH_STACKADJ_REGNUM)));
23570 if (IS_STACKALIGN (func_type))
23571 /* Restore the original stack pointer. Before prologue, the stack was
23572 realigned and the original stack pointer saved in r0. For details,
23573 see comment in arm_expand_prologue. */
23574 emit_insn (gen_movsi (stack_pointer_rtx, gen_rtx_REG (SImode, 0)));
23576 emit_jump_insn (simple_return_rtx);
23579 /* Generate RTL to represent ARM epilogue. Really_return is true if the
23580 function is not a sibcall. */
23582 arm_expand_epilogue (bool really_return)
23584 unsigned long func_type;
23585 unsigned long saved_regs_mask;
23589 arm_stack_offsets *offsets;
23591 func_type = arm_current_func_type ();
23593 /* Naked functions don't have epilogue. Hence, generate return pattern, and
23594 let output_return_instruction take care of instruction emition if any. */
23595 if (IS_NAKED (func_type)
23596 || (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN))
23599 emit_jump_insn (simple_return_rtx);
23603 /* If we are throwing an exception, then we really must be doing a
23604 return, so we can't tail-call. */
23605 gcc_assert (!crtl->calls_eh_return || really_return);
23607 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
23609 arm_expand_epilogue_apcs_frame (really_return);
23613 /* Get frame offsets for ARM. */
23614 offsets = arm_get_frame_offsets ();
23615 saved_regs_mask = offsets->saved_regs_mask;
23616 num_regs = bit_count (saved_regs_mask);
23618 if (frame_pointer_needed)
23620 /* Restore stack pointer if necessary. */
23623 /* In ARM mode, frame pointer points to first saved register.
23624 Restore stack pointer to last saved register. */
23625 amount = offsets->frame - offsets->saved_regs;
23627 /* Force out any pending memory operations that reference stacked data
23628 before stack de-allocation occurs. */
23629 emit_insn (gen_blockage ());
23630 emit_insn (gen_addsi3 (stack_pointer_rtx,
23631 hard_frame_pointer_rtx,
23632 GEN_INT (amount)));
23634 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
23636 emit_insn (gen_force_register_use (stack_pointer_rtx));
23640 /* In Thumb-2 mode, the frame pointer points to the last saved
23642 amount = offsets->locals_base - offsets->saved_regs;
23644 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
23645 hard_frame_pointer_rtx,
23646 GEN_INT (amount)));
23648 /* Force out any pending memory operations that reference stacked data
23649 before stack de-allocation occurs. */
23650 emit_insn (gen_blockage ());
23651 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
23652 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
23654 emit_insn (gen_force_register_use (stack_pointer_rtx));
23659 /* Pop off outgoing args and local frame to adjust stack pointer to
23660 last saved register. */
23661 amount = offsets->outgoing_args - offsets->saved_regs;
23664 /* Force out any pending memory operations that reference stacked data
23665 before stack de-allocation occurs. */
23666 emit_insn (gen_blockage ());
23667 emit_insn (gen_addsi3 (stack_pointer_rtx,
23669 GEN_INT (amount)));
23670 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is
23672 emit_insn (gen_force_register_use (stack_pointer_rtx));
23676 if (TARGET_HARD_FLOAT && TARGET_VFP)
23678 /* Generate VFP register multi-pop. */
23679 int end_reg = LAST_VFP_REGNUM + 1;
23681 /* Scan the registers in reverse order. We need to match
23682 any groupings made in the prologue and generate matching
23683 vldm operations. The need to match groups is because,
23684 unlike pop, vldm can only do consecutive regs. */
23685 for (i = LAST_VFP_REGNUM - 1; i >= FIRST_VFP_REGNUM; i -= 2)
23686 /* Look for a case where a reg does not need restoring. */
23687 if ((!df_regs_ever_live_p (i) || call_used_regs[i])
23688 && (!df_regs_ever_live_p (i + 1)
23689 || call_used_regs[i + 1]))
23691 /* Restore the regs discovered so far (from reg+2 to
23693 if (end_reg > i + 2)
23694 arm_emit_vfp_multi_reg_pop (i + 2,
23695 (end_reg - (i + 2)) / 2,
23696 stack_pointer_rtx);
23700 /* Restore the remaining regs that we have discovered (or possibly
23701 even all of them, if the conditional in the for loop never
23703 if (end_reg > i + 2)
23704 arm_emit_vfp_multi_reg_pop (i + 2,
23705 (end_reg - (i + 2)) / 2,
23706 stack_pointer_rtx);
23710 for (i = FIRST_IWMMXT_REGNUM; i <= LAST_IWMMXT_REGNUM; i++)
23711 if (df_regs_ever_live_p (i) && !call_used_regs[i])
23714 rtx addr = gen_rtx_MEM (V2SImode,
23715 gen_rtx_POST_INC (SImode,
23716 stack_pointer_rtx));
23717 set_mem_alias_set (addr, get_frame_alias_set ());
23718 insn = emit_insn (gen_movsi (gen_rtx_REG (V2SImode, i), addr));
23719 REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE,
23720 gen_rtx_REG (V2SImode, i),
23724 if (saved_regs_mask)
23727 bool return_in_pc = false;
23729 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
23730 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
23731 && !IS_STACKALIGN (func_type)
23733 && crtl->args.pretend_args_size == 0
23734 && saved_regs_mask & (1 << LR_REGNUM)
23735 && !crtl->calls_eh_return)
23737 saved_regs_mask &= ~(1 << LR_REGNUM);
23738 saved_regs_mask |= (1 << PC_REGNUM);
23739 return_in_pc = true;
23742 if (num_regs == 1 && (!IS_INTERRUPT (func_type) || !return_in_pc))
23744 for (i = 0; i <= LAST_ARM_REGNUM; i++)
23745 if (saved_regs_mask & (1 << i))
23747 rtx addr = gen_rtx_MEM (SImode,
23748 gen_rtx_POST_INC (SImode,
23749 stack_pointer_rtx));
23750 set_mem_alias_set (addr, get_frame_alias_set ());
23752 if (i == PC_REGNUM)
23754 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
23755 XVECEXP (insn, 0, 0) = ret_rtx;
23756 XVECEXP (insn, 0, 1) = gen_rtx_SET (SImode,
23757 gen_rtx_REG (SImode, i),
23759 RTX_FRAME_RELATED_P (XVECEXP (insn, 0, 1)) = 1;
23760 insn = emit_jump_insn (insn);
23764 insn = emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
23766 REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE,
23767 gen_rtx_REG (SImode, i),
23774 if (current_tune->prefer_ldrd_strd
23775 && !optimize_function_for_size_p (cfun))
23778 thumb2_emit_ldrd_pop (saved_regs_mask);
23780 arm_emit_multi_reg_pop (saved_regs_mask);
23783 arm_emit_multi_reg_pop (saved_regs_mask);
23786 if (return_in_pc == true)
23790 if (crtl->args.pretend_args_size)
23791 emit_insn (gen_addsi3 (stack_pointer_rtx,
23793 GEN_INT (crtl->args.pretend_args_size)));
23795 if (!really_return)
23798 if (crtl->calls_eh_return)
23799 emit_insn (gen_addsi3 (stack_pointer_rtx,
23801 gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)));
23803 if (IS_STACKALIGN (func_type))
23804 /* Restore the original stack pointer. Before prologue, the stack was
23805 realigned and the original stack pointer saved in r0. For details,
23806 see comment in arm_expand_prologue. */
23807 emit_insn (gen_movsi (stack_pointer_rtx, gen_rtx_REG (SImode, 0)));
23809 emit_jump_insn (simple_return_rtx);
23812 /* Implementation of insn prologue_thumb1_interwork. This is the first
23813 "instruction" of a function called in ARM mode. Swap to thumb mode. */
23816 thumb1_output_interwork (void)
23819 FILE *f = asm_out_file;
23821 gcc_assert (MEM_P (DECL_RTL (current_function_decl)));
23822 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
23824 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
23826 /* Generate code sequence to switch us into Thumb mode. */
23827 /* The .code 32 directive has already been emitted by
23828 ASM_DECLARE_FUNCTION_NAME. */
23829 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
23830 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
23832 /* Generate a label, so that the debugger will notice the
23833 change in instruction sets. This label is also used by
23834 the assembler to bypass the ARM code when this function
23835 is called from a Thumb encoded function elsewhere in the
23836 same file. Hence the definition of STUB_NAME here must
23837 agree with the definition in gas/config/tc-arm.c. */
23839 #define STUB_NAME ".real_start_of"
23841 fprintf (f, "\t.code\t16\n");
23843 if (arm_dllexport_name_p (name))
23844 name = arm_strip_name_encoding (name);
23846 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
23847 fprintf (f, "\t.thumb_func\n");
23848 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
23853 /* Handle the case of a double word load into a low register from
23854 a computed memory address. The computed address may involve a
23855 register which is overwritten by the load. */
23857 thumb_load_double_from_address (rtx *operands)
23865 gcc_assert (REG_P (operands[0]));
23866 gcc_assert (MEM_P (operands[1]));
23868 /* Get the memory address. */
23869 addr = XEXP (operands[1], 0);
23871 /* Work out how the memory address is computed. */
23872 switch (GET_CODE (addr))
23875 operands[2] = adjust_address (operands[1], SImode, 4);
23877 if (REGNO (operands[0]) == REGNO (addr))
23879 output_asm_insn ("ldr\t%H0, %2", operands);
23880 output_asm_insn ("ldr\t%0, %1", operands);
23884 output_asm_insn ("ldr\t%0, %1", operands);
23885 output_asm_insn ("ldr\t%H0, %2", operands);
23890 /* Compute <address> + 4 for the high order load. */
23891 operands[2] = adjust_address (operands[1], SImode, 4);
23893 output_asm_insn ("ldr\t%0, %1", operands);
23894 output_asm_insn ("ldr\t%H0, %2", operands);
23898 arg1 = XEXP (addr, 0);
23899 arg2 = XEXP (addr, 1);
23901 if (CONSTANT_P (arg1))
23902 base = arg2, offset = arg1;
23904 base = arg1, offset = arg2;
23906 gcc_assert (REG_P (base));
23908 /* Catch the case of <address> = <reg> + <reg> */
23909 if (REG_P (offset))
23911 int reg_offset = REGNO (offset);
23912 int reg_base = REGNO (base);
23913 int reg_dest = REGNO (operands[0]);
23915 /* Add the base and offset registers together into the
23916 higher destination register. */
23917 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
23918 reg_dest + 1, reg_base, reg_offset);
23920 /* Load the lower destination register from the address in
23921 the higher destination register. */
23922 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
23923 reg_dest, reg_dest + 1);
23925 /* Load the higher destination register from its own address
23927 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
23928 reg_dest + 1, reg_dest + 1);
23932 /* Compute <address> + 4 for the high order load. */
23933 operands[2] = adjust_address (operands[1], SImode, 4);
23935 /* If the computed address is held in the low order register
23936 then load the high order register first, otherwise always
23937 load the low order register first. */
23938 if (REGNO (operands[0]) == REGNO (base))
23940 output_asm_insn ("ldr\t%H0, %2", operands);
23941 output_asm_insn ("ldr\t%0, %1", operands);
23945 output_asm_insn ("ldr\t%0, %1", operands);
23946 output_asm_insn ("ldr\t%H0, %2", operands);
23952 /* With no registers to worry about we can just load the value
23954 operands[2] = adjust_address (operands[1], SImode, 4);
23956 output_asm_insn ("ldr\t%H0, %2", operands);
23957 output_asm_insn ("ldr\t%0, %1", operands);
23961 gcc_unreachable ();
23968 thumb_output_move_mem_multiple (int n, rtx *operands)
23975 if (REGNO (operands[4]) > REGNO (operands[5]))
23978 operands[4] = operands[5];
23981 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
23982 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
23986 if (REGNO (operands[4]) > REGNO (operands[5]))
23989 operands[4] = operands[5];
23992 if (REGNO (operands[5]) > REGNO (operands[6]))
23995 operands[5] = operands[6];
23998 if (REGNO (operands[4]) > REGNO (operands[5]))
24001 operands[4] = operands[5];
24005 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
24006 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
24010 gcc_unreachable ();
24016 /* Output a call-via instruction for thumb state. */
24018 thumb_call_via_reg (rtx reg)
24020 int regno = REGNO (reg);
24023 gcc_assert (regno < LR_REGNUM);
24025 /* If we are in the normal text section we can use a single instance
24026 per compilation unit. If we are doing function sections, then we need
24027 an entry per section, since we can't rely on reachability. */
24028 if (in_section == text_section)
24030 thumb_call_reg_needed = 1;
24032 if (thumb_call_via_label[regno] == NULL)
24033 thumb_call_via_label[regno] = gen_label_rtx ();
24034 labelp = thumb_call_via_label + regno;
24038 if (cfun->machine->call_via[regno] == NULL)
24039 cfun->machine->call_via[regno] = gen_label_rtx ();
24040 labelp = cfun->machine->call_via + regno;
24043 output_asm_insn ("bl\t%a0", labelp);
24047 /* Routines for generating rtl. */
24049 thumb_expand_movmemqi (rtx *operands)
24051 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
24052 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
24053 HOST_WIDE_INT len = INTVAL (operands[2]);
24054 HOST_WIDE_INT offset = 0;
24058 emit_insn (gen_movmem12b (out, in, out, in));
24064 emit_insn (gen_movmem8b (out, in, out, in));
24070 rtx reg = gen_reg_rtx (SImode);
24071 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
24072 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
24079 rtx reg = gen_reg_rtx (HImode);
24080 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
24081 plus_constant (Pmode, in,
24083 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (Pmode, out,
24092 rtx reg = gen_reg_rtx (QImode);
24093 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
24094 plus_constant (Pmode, in,
24096 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (Pmode, out,
24103 thumb_reload_out_hi (rtx *operands)
24105 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
24108 /* Handle reading a half-word from memory during reload. */
24110 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
24112 gcc_unreachable ();
24115 /* Return the length of a function name prefix
24116 that starts with the character 'c'. */
24118 arm_get_strip_length (int c)
24122 ARM_NAME_ENCODING_LENGTHS
24127 /* Return a pointer to a function's name with any
24128 and all prefix encodings stripped from it. */
24130 arm_strip_name_encoding (const char *name)
24134 while ((skip = arm_get_strip_length (* name)))
24140 /* If there is a '*' anywhere in the name's prefix, then
24141 emit the stripped name verbatim, otherwise prepend an
24142 underscore if leading underscores are being used. */
24144 arm_asm_output_labelref (FILE *stream, const char *name)
24149 while ((skip = arm_get_strip_length (* name)))
24151 verbatim |= (*name == '*');
24156 fputs (name, stream);
24158 asm_fprintf (stream, "%U%s", name);
24161 /* This function is used to emit an EABI tag and its associated value.
24162 We emit the numerical value of the tag in case the assembler does not
24163 support textual tags. (Eg gas prior to 2.20). If requested we include
24164 the tag name in a comment so that anyone reading the assembler output
24165 will know which tag is being set.
24167 This function is not static because arm-c.c needs it too. */
24170 arm_emit_eabi_attribute (const char *name, int num, int val)
24172 asm_fprintf (asm_out_file, "\t.eabi_attribute %d, %d", num, val);
24173 if (flag_verbose_asm || flag_debug_asm)
24174 asm_fprintf (asm_out_file, "\t%s %s", ASM_COMMENT_START, name);
24175 asm_fprintf (asm_out_file, "\n");
24179 arm_file_start (void)
24183 if (TARGET_UNIFIED_ASM)
24184 asm_fprintf (asm_out_file, "\t.syntax unified\n");
24188 const char *fpu_name;
24189 if (arm_selected_arch)
24190 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name);
24191 else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
24192 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8);
24194 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name);
24196 if (TARGET_SOFT_FLOAT)
24198 fpu_name = "softvfp";
24202 fpu_name = arm_fpu_desc->name;
24203 if (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
24205 if (TARGET_HARD_FLOAT)
24206 arm_emit_eabi_attribute ("Tag_ABI_HardFP_use", 27, 3);
24207 if (TARGET_HARD_FLOAT_ABI)
24208 arm_emit_eabi_attribute ("Tag_ABI_VFP_args", 28, 1);
24211 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
24213 /* Some of these attributes only apply when the corresponding features
24214 are used. However we don't have any easy way of figuring this out.
24215 Conservatively record the setting that would have been used. */
24217 if (flag_rounding_math)
24218 arm_emit_eabi_attribute ("Tag_ABI_FP_rounding", 19, 1);
24220 if (!flag_unsafe_math_optimizations)
24222 arm_emit_eabi_attribute ("Tag_ABI_FP_denormal", 20, 1);
24223 arm_emit_eabi_attribute ("Tag_ABI_FP_exceptions", 21, 1);
24225 if (flag_signaling_nans)
24226 arm_emit_eabi_attribute ("Tag_ABI_FP_user_exceptions", 22, 1);
24228 arm_emit_eabi_attribute ("Tag_ABI_FP_number_model", 23,
24229 flag_finite_math_only ? 1 : 3);
24231 arm_emit_eabi_attribute ("Tag_ABI_align8_needed", 24, 1);
24232 arm_emit_eabi_attribute ("Tag_ABI_align8_preserved", 25, 1);
24233 arm_emit_eabi_attribute ("Tag_ABI_enum_size", 26,
24234 flag_short_enums ? 1 : 2);
24236 /* Tag_ABI_optimization_goals. */
24239 else if (optimize >= 2)
24245 arm_emit_eabi_attribute ("Tag_ABI_optimization_goals", 30, val);
24247 arm_emit_eabi_attribute ("Tag_CPU_unaligned_access", 34,
24250 if (arm_fp16_format)
24251 arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
24252 (int) arm_fp16_format);
24254 if (arm_lang_output_object_attributes_hook)
24255 arm_lang_output_object_attributes_hook();
24258 default_file_start ();
24262 arm_file_end (void)
24266 if (NEED_INDICATE_EXEC_STACK)
24267 /* Add .note.GNU-stack. */
24268 file_end_indicate_exec_stack ();
24270 if (! thumb_call_reg_needed)
24273 switch_to_section (text_section);
24274 asm_fprintf (asm_out_file, "\t.code 16\n");
24275 ASM_OUTPUT_ALIGN (asm_out_file, 1);
24277 for (regno = 0; regno < LR_REGNUM; regno++)
24279 rtx label = thumb_call_via_label[regno];
24283 targetm.asm_out.internal_label (asm_out_file, "L",
24284 CODE_LABEL_NUMBER (label));
24285 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
24291 /* Symbols in the text segment can be accessed without indirecting via the
24292 constant pool; it may take an extra binary operation, but this is still
24293 faster than indirecting via memory. Don't do this when not optimizing,
24294 since we won't be calculating al of the offsets necessary to do this
24298 arm_encode_section_info (tree decl, rtx rtl, int first)
24300 if (optimize > 0 && TREE_CONSTANT (decl))
24301 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
24303 default_encode_section_info (decl, rtl, first);
24305 #endif /* !ARM_PE */
24308 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
24310 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
24311 && !strcmp (prefix, "L"))
24313 arm_ccfsm_state = 0;
24314 arm_target_insn = NULL;
24316 default_internal_label (stream, prefix, labelno);
24319 /* Output code to add DELTA to the first argument, and then jump
24320 to FUNCTION. Used for C++ multiple inheritance. */
24322 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
24323 HOST_WIDE_INT delta,
24324 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
24327 static int thunk_label = 0;
24330 int mi_delta = delta;
24331 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
24333 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
24336 mi_delta = - mi_delta;
24338 final_start_function (emit_barrier (), file, 1);
24342 int labelno = thunk_label++;
24343 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
24344 /* Thunks are entered in arm mode when avaiable. */
24345 if (TARGET_THUMB1_ONLY)
24347 /* push r3 so we can use it as a temporary. */
24348 /* TODO: Omit this save if r3 is not used. */
24349 fputs ("\tpush {r3}\n", file);
24350 fputs ("\tldr\tr3, ", file);
24354 fputs ("\tldr\tr12, ", file);
24356 assemble_name (file, label);
24357 fputc ('\n', file);
24360 /* If we are generating PIC, the ldr instruction below loads
24361 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
24362 the address of the add + 8, so we have:
24364 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
24367 Note that we have "+ 1" because some versions of GNU ld
24368 don't set the low bit of the result for R_ARM_REL32
24369 relocations against thumb function symbols.
24370 On ARMv6M this is +4, not +8. */
24371 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
24372 assemble_name (file, labelpc);
24373 fputs (":\n", file);
24374 if (TARGET_THUMB1_ONLY)
24376 /* This is 2 insns after the start of the thunk, so we know it
24377 is 4-byte aligned. */
24378 fputs ("\tadd\tr3, pc, r3\n", file);
24379 fputs ("\tmov r12, r3\n", file);
24382 fputs ("\tadd\tr12, pc, r12\n", file);
24384 else if (TARGET_THUMB1_ONLY)
24385 fputs ("\tmov r12, r3\n", file);
24387 if (TARGET_THUMB1_ONLY)
24389 if (mi_delta > 255)
24391 fputs ("\tldr\tr3, ", file);
24392 assemble_name (file, label);
24393 fputs ("+4\n", file);
24394 asm_fprintf (file, "\t%s\t%r, %r, r3\n",
24395 mi_op, this_regno, this_regno);
24397 else if (mi_delta != 0)
24399 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
24400 mi_op, this_regno, this_regno,
24406 /* TODO: Use movw/movt for large constants when available. */
24407 while (mi_delta != 0)
24409 if ((mi_delta & (3 << shift)) == 0)
24413 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
24414 mi_op, this_regno, this_regno,
24415 mi_delta & (0xff << shift));
24416 mi_delta &= ~(0xff << shift);
24423 if (TARGET_THUMB1_ONLY)
24424 fputs ("\tpop\t{r3}\n", file);
24426 fprintf (file, "\tbx\tr12\n");
24427 ASM_OUTPUT_ALIGN (file, 2);
24428 assemble_name (file, label);
24429 fputs (":\n", file);
24432 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
24433 rtx tem = XEXP (DECL_RTL (function), 0);
24434 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
24435 tem = gen_rtx_MINUS (GET_MODE (tem),
24437 gen_rtx_SYMBOL_REF (Pmode,
24438 ggc_strdup (labelpc)));
24439 assemble_integer (tem, 4, BITS_PER_WORD, 1);
24442 /* Output ".word .LTHUNKn". */
24443 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
24445 if (TARGET_THUMB1_ONLY && mi_delta > 255)
24446 assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1);
24450 fputs ("\tb\t", file);
24451 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
24452 if (NEED_PLT_RELOC)
24453 fputs ("(PLT)", file);
24454 fputc ('\n', file);
24457 final_end_function ();
24461 arm_emit_vector_const (FILE *file, rtx x)
24464 const char * pattern;
24466 gcc_assert (GET_CODE (x) == CONST_VECTOR);
24468 switch (GET_MODE (x))
24470 case V2SImode: pattern = "%08x"; break;
24471 case V4HImode: pattern = "%04x"; break;
24472 case V8QImode: pattern = "%02x"; break;
24473 default: gcc_unreachable ();
24476 fprintf (file, "0x");
24477 for (i = CONST_VECTOR_NUNITS (x); i--;)
24481 element = CONST_VECTOR_ELT (x, i);
24482 fprintf (file, pattern, INTVAL (element));
24488 /* Emit a fp16 constant appropriately padded to occupy a 4-byte word.
24489 HFmode constant pool entries are actually loaded with ldr. */
24491 arm_emit_fp16_const (rtx c)
24496 REAL_VALUE_FROM_CONST_DOUBLE (r, c);
24497 bits = real_to_target (NULL, &r, HFmode);
24498 if (WORDS_BIG_ENDIAN)
24499 assemble_zeros (2);
24500 assemble_integer (GEN_INT (bits), 2, BITS_PER_WORD, 1);
24501 if (!WORDS_BIG_ENDIAN)
24502 assemble_zeros (2);
24506 arm_output_load_gr (rtx *operands)
24513 if (!MEM_P (operands [1])
24514 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
24515 || !REG_P (reg = XEXP (sum, 0))
24516 || !CONST_INT_P (offset = XEXP (sum, 1))
24517 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
24518 return "wldrw%?\t%0, %1";
24520 /* Fix up an out-of-range load of a GR register. */
24521 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
24522 wcgr = operands[0];
24524 output_asm_insn ("ldr%?\t%0, %1", operands);
24526 operands[0] = wcgr;
24528 output_asm_insn ("tmcr%?\t%0, %1", operands);
24529 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
24534 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
24536 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
24537 named arg and all anonymous args onto the stack.
24538 XXX I know the prologue shouldn't be pushing registers, but it is faster
24542 arm_setup_incoming_varargs (cumulative_args_t pcum_v,
24543 enum machine_mode mode,
24546 int second_time ATTRIBUTE_UNUSED)
24548 CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
24551 cfun->machine->uses_anonymous_args = 1;
24552 if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
24554 nregs = pcum->aapcs_ncrn;
24555 if ((nregs & 1) && arm_needs_doubleword_align (mode, type))
24559 nregs = pcum->nregs;
24561 if (nregs < NUM_ARG_REGS)
24562 *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
24565 /* Return nonzero if the CONSUMER instruction (a store) does not need
24566 PRODUCER's value to calculate the address. */
24569 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
24571 rtx value = PATTERN (producer);
24572 rtx addr = PATTERN (consumer);
24574 if (GET_CODE (value) == COND_EXEC)
24575 value = COND_EXEC_CODE (value);
24576 if (GET_CODE (value) == PARALLEL)
24577 value = XVECEXP (value, 0, 0);
24578 value = XEXP (value, 0);
24579 if (GET_CODE (addr) == COND_EXEC)
24580 addr = COND_EXEC_CODE (addr);
24581 if (GET_CODE (addr) == PARALLEL)
24582 addr = XVECEXP (addr, 0, 0);
24583 addr = XEXP (addr, 0);
24585 return !reg_overlap_mentioned_p (value, addr);
24588 /* Return nonzero if the CONSUMER instruction (a store) does need
24589 PRODUCER's value to calculate the address. */
24592 arm_early_store_addr_dep (rtx producer, rtx consumer)
24594 return !arm_no_early_store_addr_dep (producer, consumer);
24597 /* Return nonzero if the CONSUMER instruction (a load) does need
24598 PRODUCER's value to calculate the address. */
24601 arm_early_load_addr_dep (rtx producer, rtx consumer)
24603 rtx value = PATTERN (producer);
24604 rtx addr = PATTERN (consumer);
24606 if (GET_CODE (value) == COND_EXEC)
24607 value = COND_EXEC_CODE (value);
24608 if (GET_CODE (value) == PARALLEL)
24609 value = XVECEXP (value, 0, 0);
24610 value = XEXP (value, 0);
24611 if (GET_CODE (addr) == COND_EXEC)
24612 addr = COND_EXEC_CODE (addr);
24613 if (GET_CODE (addr) == PARALLEL)
24615 if (GET_CODE (XVECEXP (addr, 0, 0)) == RETURN)
24616 addr = XVECEXP (addr, 0, 1);
24618 addr = XVECEXP (addr, 0, 0);
24620 addr = XEXP (addr, 1);
24622 return reg_overlap_mentioned_p (value, addr);
24625 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
24626 have an early register shift value or amount dependency on the
24627 result of PRODUCER. */
24630 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
24632 rtx value = PATTERN (producer);
24633 rtx op = PATTERN (consumer);
24636 if (GET_CODE (value) == COND_EXEC)
24637 value = COND_EXEC_CODE (value);
24638 if (GET_CODE (value) == PARALLEL)
24639 value = XVECEXP (value, 0, 0);
24640 value = XEXP (value, 0);
24641 if (GET_CODE (op) == COND_EXEC)
24642 op = COND_EXEC_CODE (op);
24643 if (GET_CODE (op) == PARALLEL)
24644 op = XVECEXP (op, 0, 0);
24647 early_op = XEXP (op, 0);
24648 /* This is either an actual independent shift, or a shift applied to
24649 the first operand of another operation. We want the whole shift
24651 if (REG_P (early_op))
24654 return !reg_overlap_mentioned_p (value, early_op);
24657 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
24658 have an early register shift value dependency on the result of
24662 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
24664 rtx value = PATTERN (producer);
24665 rtx op = PATTERN (consumer);
24668 if (GET_CODE (value) == COND_EXEC)
24669 value = COND_EXEC_CODE (value);
24670 if (GET_CODE (value) == PARALLEL)
24671 value = XVECEXP (value, 0, 0);
24672 value = XEXP (value, 0);
24673 if (GET_CODE (op) == COND_EXEC)
24674 op = COND_EXEC_CODE (op);
24675 if (GET_CODE (op) == PARALLEL)
24676 op = XVECEXP (op, 0, 0);
24679 early_op = XEXP (op, 0);
24681 /* This is either an actual independent shift, or a shift applied to
24682 the first operand of another operation. We want the value being
24683 shifted, in either case. */
24684 if (!REG_P (early_op))
24685 early_op = XEXP (early_op, 0);
24687 return !reg_overlap_mentioned_p (value, early_op);
24690 /* Return nonzero if the CONSUMER (a mul or mac op) does not
24691 have an early register mult dependency on the result of
24695 arm_no_early_mul_dep (rtx producer, rtx consumer)
24697 rtx value = PATTERN (producer);
24698 rtx op = PATTERN (consumer);
24700 if (GET_CODE (value) == COND_EXEC)
24701 value = COND_EXEC_CODE (value);
24702 if (GET_CODE (value) == PARALLEL)
24703 value = XVECEXP (value, 0, 0);
24704 value = XEXP (value, 0);
24705 if (GET_CODE (op) == COND_EXEC)
24706 op = COND_EXEC_CODE (op);
24707 if (GET_CODE (op) == PARALLEL)
24708 op = XVECEXP (op, 0, 0);
24711 if (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
24713 if (GET_CODE (XEXP (op, 0)) == MULT)
24714 return !reg_overlap_mentioned_p (value, XEXP (op, 0));
24716 return !reg_overlap_mentioned_p (value, XEXP (op, 1));
24722 /* We can't rely on the caller doing the proper promotion when
24723 using APCS or ATPCS. */
24726 arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED)
24728 return !TARGET_AAPCS_BASED;
24731 static enum machine_mode
24732 arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
24733 enum machine_mode mode,
24734 int *punsignedp ATTRIBUTE_UNUSED,
24735 const_tree fntype ATTRIBUTE_UNUSED,
24736 int for_return ATTRIBUTE_UNUSED)
24738 if (GET_MODE_CLASS (mode) == MODE_INT
24739 && GET_MODE_SIZE (mode) < 4)
24745 /* AAPCS based ABIs use short enums by default. */
24748 arm_default_short_enums (void)
24750 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
24754 /* AAPCS requires that anonymous bitfields affect structure alignment. */
24757 arm_align_anon_bitfield (void)
24759 return TARGET_AAPCS_BASED;
24763 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
24766 arm_cxx_guard_type (void)
24768 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
24771 /* Return non-zero iff the consumer (a multiply-accumulate or a
24772 multiple-subtract instruction) has an accumulator dependency on the
24773 result of the producer and no other dependency on that result. It
24774 does not check if the producer is multiply-accumulate instruction. */
24776 arm_mac_accumulator_is_result (rtx producer, rtx consumer)
24781 producer = PATTERN (producer);
24782 consumer = PATTERN (consumer);
24784 if (GET_CODE (producer) == COND_EXEC)
24785 producer = COND_EXEC_CODE (producer);
24786 if (GET_CODE (consumer) == COND_EXEC)
24787 consumer = COND_EXEC_CODE (consumer);
24789 if (GET_CODE (producer) != SET)
24792 result = XEXP (producer, 0);
24794 if (GET_CODE (consumer) != SET)
24797 /* Check that the consumer is of the form
24798 (set (...) (plus (mult ...) (...)))
24800 (set (...) (minus (...) (mult ...))). */
24801 if (GET_CODE (XEXP (consumer, 1)) == PLUS)
24803 if (GET_CODE (XEXP (XEXP (consumer, 1), 0)) != MULT)
24806 op0 = XEXP (XEXP (XEXP (consumer, 1), 0), 0);
24807 op1 = XEXP (XEXP (XEXP (consumer, 1), 0), 1);
24808 acc = XEXP (XEXP (consumer, 1), 1);
24810 else if (GET_CODE (XEXP (consumer, 1)) == MINUS)
24812 if (GET_CODE (XEXP (XEXP (consumer, 1), 1)) != MULT)
24815 op0 = XEXP (XEXP (XEXP (consumer, 1), 1), 0);
24816 op1 = XEXP (XEXP (XEXP (consumer, 1), 1), 1);
24817 acc = XEXP (XEXP (consumer, 1), 0);
24822 return (reg_overlap_mentioned_p (result, acc)
24823 && !reg_overlap_mentioned_p (result, op0)
24824 && !reg_overlap_mentioned_p (result, op1));
24827 /* Return non-zero if the consumer (a multiply-accumulate instruction)
24828 has an accumulator dependency on the result of the producer (a
24829 multiplication instruction) and no other dependency on that result. */
24831 arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer)
24833 rtx mul = PATTERN (producer);
24834 rtx mac = PATTERN (consumer);
24836 rtx mac_op0, mac_op1, mac_acc;
24838 if (GET_CODE (mul) == COND_EXEC)
24839 mul = COND_EXEC_CODE (mul);
24840 if (GET_CODE (mac) == COND_EXEC)
24841 mac = COND_EXEC_CODE (mac);
24843 /* Check that mul is of the form (set (...) (mult ...))
24844 and mla is of the form (set (...) (plus (mult ...) (...))). */
24845 if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT)
24846 || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS
24847 || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT))
24850 mul_result = XEXP (mul, 0);
24851 mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0);
24852 mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1);
24853 mac_acc = XEXP (XEXP (mac, 1), 1);
24855 return (reg_overlap_mentioned_p (mul_result, mac_acc)
24856 && !reg_overlap_mentioned_p (mul_result, mac_op0)
24857 && !reg_overlap_mentioned_p (mul_result, mac_op1));
24861 /* The EABI says test the least significant bit of a guard variable. */
24864 arm_cxx_guard_mask_bit (void)
24866 return TARGET_AAPCS_BASED;
24870 /* The EABI specifies that all array cookies are 8 bytes long. */
24873 arm_get_cookie_size (tree type)
24877 if (!TARGET_AAPCS_BASED)
24878 return default_cxx_get_cookie_size (type);
24880 size = build_int_cst (sizetype, 8);
24885 /* The EABI says that array cookies should also contain the element size. */
24888 arm_cookie_has_size (void)
24890 return TARGET_AAPCS_BASED;
24894 /* The EABI says constructors and destructors should return a pointer to
24895 the object constructed/destroyed. */
24898 arm_cxx_cdtor_returns_this (void)
24900 return TARGET_AAPCS_BASED;
24903 /* The EABI says that an inline function may never be the key
24907 arm_cxx_key_method_may_be_inline (void)
24909 return !TARGET_AAPCS_BASED;
24913 arm_cxx_determine_class_data_visibility (tree decl)
24915 if (!TARGET_AAPCS_BASED
24916 || !TARGET_DLLIMPORT_DECL_ATTRIBUTES)
24919 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
24920 is exported. However, on systems without dynamic vague linkage,
24921 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
24922 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
24923 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
24925 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
24926 DECL_VISIBILITY_SPECIFIED (decl) = 1;
24930 arm_cxx_class_data_always_comdat (void)
24932 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
24933 vague linkage if the class has no key function. */
24934 return !TARGET_AAPCS_BASED;
24938 /* The EABI says __aeabi_atexit should be used to register static
24942 arm_cxx_use_aeabi_atexit (void)
24944 return TARGET_AAPCS_BASED;
24949 arm_set_return_address (rtx source, rtx scratch)
24951 arm_stack_offsets *offsets;
24952 HOST_WIDE_INT delta;
24954 unsigned long saved_regs;
24956 offsets = arm_get_frame_offsets ();
24957 saved_regs = offsets->saved_regs_mask;
24959 if ((saved_regs & (1 << LR_REGNUM)) == 0)
24960 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
24963 if (frame_pointer_needed)
24964 addr = plus_constant (Pmode, hard_frame_pointer_rtx, -4);
24967 /* LR will be the first saved register. */
24968 delta = offsets->outgoing_args - (offsets->frame + 4);
24973 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
24974 GEN_INT (delta & ~4095)));
24979 addr = stack_pointer_rtx;
24981 addr = plus_constant (Pmode, addr, delta);
24983 emit_move_insn (gen_frame_mem (Pmode, addr), source);
24989 thumb_set_return_address (rtx source, rtx scratch)
24991 arm_stack_offsets *offsets;
24992 HOST_WIDE_INT delta;
24993 HOST_WIDE_INT limit;
24996 unsigned long mask;
25000 offsets = arm_get_frame_offsets ();
25001 mask = offsets->saved_regs_mask;
25002 if (mask & (1 << LR_REGNUM))
25005 /* Find the saved regs. */
25006 if (frame_pointer_needed)
25008 delta = offsets->soft_frame - offsets->saved_args;
25009 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
25015 delta = offsets->outgoing_args - offsets->saved_args;
25018 /* Allow for the stack frame. */
25019 if (TARGET_THUMB1 && TARGET_BACKTRACE)
25021 /* The link register is always the first saved register. */
25024 /* Construct the address. */
25025 addr = gen_rtx_REG (SImode, reg);
25028 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
25029 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
25033 addr = plus_constant (Pmode, addr, delta);
25035 emit_move_insn (gen_frame_mem (Pmode, addr), source);
25038 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
25041 /* Implements target hook vector_mode_supported_p. */
25043 arm_vector_mode_supported_p (enum machine_mode mode)
25045 /* Neon also supports V2SImode, etc. listed in the clause below. */
25046 if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode
25047 || mode == V16QImode || mode == V4SFmode || mode == V2DImode))
25050 if ((TARGET_NEON || TARGET_IWMMXT)
25051 && ((mode == V2SImode)
25052 || (mode == V4HImode)
25053 || (mode == V8QImode)))
25056 if (TARGET_INT_SIMD && (mode == V4UQQmode || mode == V4QQmode
25057 || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode
25058 || mode == V2HAmode))
25064 /* Implements target hook array_mode_supported_p. */
25067 arm_array_mode_supported_p (enum machine_mode mode,
25068 unsigned HOST_WIDE_INT nelems)
25071 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
25072 && (nelems >= 2 && nelems <= 4))
25078 /* Use the option -mvectorize-with-neon-double to override the use of quardword
25079 registers when autovectorizing for Neon, at least until multiple vector
25080 widths are supported properly by the middle-end. */
25082 static enum machine_mode
25083 arm_preferred_simd_mode (enum machine_mode mode)
25089 return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode;
25091 return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode;
25093 return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode;
25095 return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode;
25097 if (!TARGET_NEON_VECTORIZE_DOUBLE)
25104 if (TARGET_REALLY_IWMMXT)
25120 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
25122 We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
25123 using r0-r4 for function arguments, r7 for the stack frame and don't have
25124 enough left over to do doubleword arithmetic. For Thumb-2 all the
25125 potentially problematic instructions accept high registers so this is not
25126 necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
25127 that require many low registers. */
25129 arm_class_likely_spilled_p (reg_class_t rclass)
25131 if ((TARGET_THUMB1 && rclass == LO_REGS)
25132 || rclass == CC_REG)
25138 /* Implements target hook small_register_classes_for_mode_p. */
25140 arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
25142 return TARGET_THUMB1;
25145 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
25146 ARM insns and therefore guarantee that the shift count is modulo 256.
25147 DImode shifts (those implemented by lib1funcs.S or by optabs.c)
25148 guarantee no particular behavior for out-of-range counts. */
25150 static unsigned HOST_WIDE_INT
25151 arm_shift_truncation_mask (enum machine_mode mode)
25153 return mode == SImode ? 255 : 0;
25157 /* Map internal gcc register numbers to DWARF2 register numbers. */
25160 arm_dbx_register_number (unsigned int regno)
25165 if (IS_VFP_REGNUM (regno))
25167 /* See comment in arm_dwarf_register_span. */
25168 if (VFP_REGNO_OK_FOR_SINGLE (regno))
25169 return 64 + regno - FIRST_VFP_REGNUM;
25171 return 256 + (regno - FIRST_VFP_REGNUM) / 2;
25174 if (IS_IWMMXT_GR_REGNUM (regno))
25175 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
25177 if (IS_IWMMXT_REGNUM (regno))
25178 return 112 + regno - FIRST_IWMMXT_REGNUM;
25180 gcc_unreachable ();
25183 /* Dwarf models VFPv3 registers as 32 64-bit registers.
25184 GCC models tham as 64 32-bit registers, so we need to describe this to
25185 the DWARF generation code. Other registers can use the default. */
25187 arm_dwarf_register_span (rtx rtl)
25194 regno = REGNO (rtl);
25195 if (!IS_VFP_REGNUM (regno))
25198 /* XXX FIXME: The EABI defines two VFP register ranges:
25199 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
25201 The recommended encoding for S0-S31 is a DW_OP_bit_piece of the
25202 corresponding D register. Until GDB supports this, we shall use the
25203 legacy encodings. We also use these encodings for D0-D15 for
25204 compatibility with older debuggers. */
25205 if (VFP_REGNO_OK_FOR_SINGLE (regno))
25208 nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8;
25209 p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
25210 regno = (regno - FIRST_VFP_REGNUM) / 2;
25211 for (i = 0; i < nregs; i++)
25212 XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i);
25217 #if ARM_UNWIND_INFO
25218 /* Emit unwind directives for a store-multiple instruction or stack pointer
25219 push during alignment.
25220 These should only ever be generated by the function prologue code, so
25221 expect them to have a particular form. */
25224 arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
25227 HOST_WIDE_INT offset;
25228 HOST_WIDE_INT nregs;
25234 e = XVECEXP (p, 0, 0);
25235 if (GET_CODE (e) != SET)
25238 /* First insn will adjust the stack pointer. */
25239 if (GET_CODE (e) != SET
25240 || !REG_P (XEXP (e, 0))
25241 || REGNO (XEXP (e, 0)) != SP_REGNUM
25242 || GET_CODE (XEXP (e, 1)) != PLUS)
25245 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
25246 nregs = XVECLEN (p, 0) - 1;
25248 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
25251 /* The function prologue may also push pc, but not annotate it as it is
25252 never restored. We turn this into a stack pointer adjustment. */
25253 if (nregs * 4 == offset - 4)
25255 fprintf (asm_out_file, "\t.pad #4\n");
25259 fprintf (asm_out_file, "\t.save {");
25261 else if (IS_VFP_REGNUM (reg))
25264 fprintf (asm_out_file, "\t.vsave {");
25267 /* Unknown register type. */
25270 /* If the stack increment doesn't match the size of the saved registers,
25271 something has gone horribly wrong. */
25272 if (offset != nregs * reg_size)
25277 /* The remaining insns will describe the stores. */
25278 for (i = 1; i <= nregs; i++)
25280 /* Expect (set (mem <addr>) (reg)).
25281 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
25282 e = XVECEXP (p, 0, i);
25283 if (GET_CODE (e) != SET
25284 || !MEM_P (XEXP (e, 0))
25285 || !REG_P (XEXP (e, 1)))
25288 reg = REGNO (XEXP (e, 1));
25293 fprintf (asm_out_file, ", ");
25294 /* We can't use %r for vfp because we need to use the
25295 double precision register names. */
25296 if (IS_VFP_REGNUM (reg))
25297 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
25299 asm_fprintf (asm_out_file, "%r", reg);
25301 #ifdef ENABLE_CHECKING
25302 /* Check that the addresses are consecutive. */
25303 e = XEXP (XEXP (e, 0), 0);
25304 if (GET_CODE (e) == PLUS)
25306 offset += reg_size;
25307 if (!REG_P (XEXP (e, 0))
25308 || REGNO (XEXP (e, 0)) != SP_REGNUM
25309 || !CONST_INT_P (XEXP (e, 1))
25310 || offset != INTVAL (XEXP (e, 1)))
25315 || REGNO (e) != SP_REGNUM)
25319 fprintf (asm_out_file, "}\n");
25322 /* Emit unwind directives for a SET. */
25325 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
25333 switch (GET_CODE (e0))
25336 /* Pushing a single register. */
25337 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
25338 || !REG_P (XEXP (XEXP (e0, 0), 0))
25339 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
25342 asm_fprintf (asm_out_file, "\t.save ");
25343 if (IS_VFP_REGNUM (REGNO (e1)))
25344 asm_fprintf(asm_out_file, "{d%d}\n",
25345 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
25347 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
25351 if (REGNO (e0) == SP_REGNUM)
25353 /* A stack increment. */
25354 if (GET_CODE (e1) != PLUS
25355 || !REG_P (XEXP (e1, 0))
25356 || REGNO (XEXP (e1, 0)) != SP_REGNUM
25357 || !CONST_INT_P (XEXP (e1, 1)))
25360 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
25361 -INTVAL (XEXP (e1, 1)));
25363 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
25365 HOST_WIDE_INT offset;
25367 if (GET_CODE (e1) == PLUS)
25369 if (!REG_P (XEXP (e1, 0))
25370 || !CONST_INT_P (XEXP (e1, 1)))
25372 reg = REGNO (XEXP (e1, 0));
25373 offset = INTVAL (XEXP (e1, 1));
25374 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
25375 HARD_FRAME_POINTER_REGNUM, reg,
25378 else if (REG_P (e1))
25381 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
25382 HARD_FRAME_POINTER_REGNUM, reg);
25387 else if (REG_P (e1) && REGNO (e1) == SP_REGNUM)
25389 /* Move from sp to reg. */
25390 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
25392 else if (GET_CODE (e1) == PLUS
25393 && REG_P (XEXP (e1, 0))
25394 && REGNO (XEXP (e1, 0)) == SP_REGNUM
25395 && CONST_INT_P (XEXP (e1, 1)))
25397 /* Set reg to offset from sp. */
25398 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
25399 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
25411 /* Emit unwind directives for the given insn. */
25414 arm_unwind_emit (FILE * asm_out_file, rtx insn)
25417 bool handled_one = false;
25419 if (arm_except_unwind_info (&global_options) != UI_TARGET)
25422 if (!(flag_unwind_tables || crtl->uses_eh_lsda)
25423 && (TREE_NOTHROW (current_function_decl)
25424 || crtl->all_throwers_are_sibcalls))
25427 if (NOTE_P (insn) || !RTX_FRAME_RELATED_P (insn))
25430 for (note = REG_NOTES (insn); note ; note = XEXP (note, 1))
25432 pat = XEXP (note, 0);
25433 switch (REG_NOTE_KIND (note))
25435 case REG_FRAME_RELATED_EXPR:
25438 case REG_CFA_REGISTER:
25441 pat = PATTERN (insn);
25442 if (GET_CODE (pat) == PARALLEL)
25443 pat = XVECEXP (pat, 0, 0);
25446 /* Only emitted for IS_STACKALIGN re-alignment. */
25451 src = SET_SRC (pat);
25452 dest = SET_DEST (pat);
25454 gcc_assert (src == stack_pointer_rtx);
25455 reg = REGNO (dest);
25456 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
25459 handled_one = true;
25462 case REG_CFA_DEF_CFA:
25463 case REG_CFA_EXPRESSION:
25464 case REG_CFA_ADJUST_CFA:
25465 case REG_CFA_OFFSET:
25466 /* ??? Only handling here what we actually emit. */
25467 gcc_unreachable ();
25475 pat = PATTERN (insn);
25478 switch (GET_CODE (pat))
25481 arm_unwind_emit_set (asm_out_file, pat);
25485 /* Store multiple. */
25486 arm_unwind_emit_sequence (asm_out_file, pat);
25495 /* Output a reference from a function exception table to the type_info
25496 object X. The EABI specifies that the symbol should be relocated by
25497 an R_ARM_TARGET2 relocation. */
25500 arm_output_ttype (rtx x)
25502 fputs ("\t.word\t", asm_out_file);
25503 output_addr_const (asm_out_file, x);
25504 /* Use special relocations for symbol references. */
25505 if (!CONST_INT_P (x))
25506 fputs ("(TARGET2)", asm_out_file);
25507 fputc ('\n', asm_out_file);
25512 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
25515 arm_asm_emit_except_personality (rtx personality)
25517 fputs ("\t.personality\t", asm_out_file);
25518 output_addr_const (asm_out_file, personality);
25519 fputc ('\n', asm_out_file);
25522 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
25525 arm_asm_init_sections (void)
25527 exception_section = get_unnamed_section (0, output_section_asm_op,
25530 #endif /* ARM_UNWIND_INFO */
25532 /* Output unwind directives for the start/end of a function. */
25535 arm_output_fn_unwind (FILE * f, bool prologue)
25537 if (arm_except_unwind_info (&global_options) != UI_TARGET)
25541 fputs ("\t.fnstart\n", f);
25544 /* If this function will never be unwound, then mark it as such.
25545 The came condition is used in arm_unwind_emit to suppress
25546 the frame annotations. */
25547 if (!(flag_unwind_tables || crtl->uses_eh_lsda)
25548 && (TREE_NOTHROW (current_function_decl)
25549 || crtl->all_throwers_are_sibcalls))
25550 fputs("\t.cantunwind\n", f);
25552 fputs ("\t.fnend\n", f);
25557 arm_emit_tls_decoration (FILE *fp, rtx x)
25559 enum tls_reloc reloc;
25562 val = XVECEXP (x, 0, 0);
25563 reloc = (enum tls_reloc) INTVAL (XVECEXP (x, 0, 1));
25565 output_addr_const (fp, val);
25570 fputs ("(tlsgd)", fp);
25573 fputs ("(tlsldm)", fp);
25576 fputs ("(tlsldo)", fp);
25579 fputs ("(gottpoff)", fp);
25582 fputs ("(tpoff)", fp);
25585 fputs ("(tlsdesc)", fp);
25588 gcc_unreachable ();
25597 fputs (" + (. - ", fp);
25598 output_addr_const (fp, XVECEXP (x, 0, 2));
25599 /* For DESCSEQ the 3rd operand encodes thumbness, and is added */
25600 fputs (reloc == TLS_DESCSEQ ? " + " : " - ", fp);
25601 output_addr_const (fp, XVECEXP (x, 0, 3));
25611 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
25614 arm_output_dwarf_dtprel (FILE *file, int size, rtx x)
25616 gcc_assert (size == 4);
25617 fputs ("\t.word\t", file);
25618 output_addr_const (file, x);
25619 fputs ("(tlsldo)", file);
25622 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
25625 arm_output_addr_const_extra (FILE *fp, rtx x)
25627 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
25628 return arm_emit_tls_decoration (fp, x);
25629 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
25632 int labelno = INTVAL (XVECEXP (x, 0, 0));
25634 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
25635 assemble_name_raw (fp, label);
25639 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOTSYM_OFF)
25641 assemble_name (fp, "_GLOBAL_OFFSET_TABLE_");
25645 output_addr_const (fp, XVECEXP (x, 0, 0));
25649 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET)
25651 output_addr_const (fp, XVECEXP (x, 0, 0));
25655 output_addr_const (fp, XVECEXP (x, 0, 1));
25659 else if (GET_CODE (x) == CONST_VECTOR)
25660 return arm_emit_vector_const (fp, x);
25665 /* Output assembly for a shift instruction.
25666 SET_FLAGS determines how the instruction modifies the condition codes.
25667 0 - Do not set condition codes.
25668 1 - Set condition codes.
25669 2 - Use smallest instruction. */
25671 arm_output_shift(rtx * operands, int set_flags)
25674 static const char flag_chars[3] = {'?', '.', '!'};
25679 c = flag_chars[set_flags];
25680 if (TARGET_UNIFIED_ASM)
25682 shift = shift_op(operands[3], &val);
25686 operands[2] = GEN_INT(val);
25687 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
25690 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
25693 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
25694 output_asm_insn (pattern, operands);
25698 /* Output assembly for a WMMX immediate shift instruction. */
25700 arm_output_iwmmxt_shift_immediate (const char *insn_name, rtx *operands, bool wror_or_wsra)
25702 int shift = INTVAL (operands[2]);
25704 enum machine_mode opmode = GET_MODE (operands[0]);
25706 gcc_assert (shift >= 0);
25708 /* If the shift value in the register versions is > 63 (for D qualifier),
25709 31 (for W qualifier) or 15 (for H qualifier). */
25710 if (((opmode == V4HImode) && (shift > 15))
25711 || ((opmode == V2SImode) && (shift > 31))
25712 || ((opmode == DImode) && (shift > 63)))
25716 sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32);
25717 output_asm_insn (templ, operands);
25718 if (opmode == DImode)
25720 sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, 32);
25721 output_asm_insn (templ, operands);
25726 /* The destination register will contain all zeros. */
25727 sprintf (templ, "wzero\t%%0");
25728 output_asm_insn (templ, operands);
25733 if ((opmode == DImode) && (shift > 32))
25735 sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32);
25736 output_asm_insn (templ, operands);
25737 sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, shift - 32);
25738 output_asm_insn (templ, operands);
25742 sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, shift);
25743 output_asm_insn (templ, operands);
25748 /* Output assembly for a WMMX tinsr instruction. */
25750 arm_output_iwmmxt_tinsr (rtx *operands)
25752 int mask = INTVAL (operands[3]);
25755 int units = mode_nunits[GET_MODE (operands[0])];
25756 gcc_assert ((mask & (mask - 1)) == 0);
25757 for (i = 0; i < units; ++i)
25759 if ((mask & 0x01) == 1)
25765 gcc_assert (i < units);
25767 switch (GET_MODE (operands[0]))
25770 sprintf (templ, "tinsrb%%?\t%%0, %%2, #%d", i);
25773 sprintf (templ, "tinsrh%%?\t%%0, %%2, #%d", i);
25776 sprintf (templ, "tinsrw%%?\t%%0, %%2, #%d", i);
25779 gcc_unreachable ();
25782 output_asm_insn (templ, operands);
25787 /* Output a Thumb-1 casesi dispatch sequence. */
25789 thumb1_output_casesi (rtx *operands)
25791 rtx diff_vec = PATTERN (next_real_insn (operands[0]));
25793 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
25795 switch (GET_MODE(diff_vec))
25798 return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ?
25799 "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi");
25801 return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ?
25802 "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi");
25804 return "bl\t%___gnu_thumb1_case_si";
25806 gcc_unreachable ();
25810 /* Output a Thumb-2 casesi instruction. */
25812 thumb2_output_casesi (rtx *operands)
25814 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
25816 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
25818 output_asm_insn ("cmp\t%0, %1", operands);
25819 output_asm_insn ("bhi\t%l3", operands);
25820 switch (GET_MODE(diff_vec))
25823 return "tbb\t[%|pc, %0]";
25825 return "tbh\t[%|pc, %0, lsl #1]";
25829 output_asm_insn ("adr\t%4, %l2", operands);
25830 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
25831 output_asm_insn ("add\t%4, %4, %5", operands);
25836 output_asm_insn ("adr\t%4, %l2", operands);
25837 return "ldr\t%|pc, [%4, %0, lsl #2]";
25840 gcc_unreachable ();
25844 /* Most ARM cores are single issue, but some newer ones can dual issue.
25845 The scheduler descriptions rely on this being correct. */
25847 arm_issue_rate (void)
25871 /* A table and a function to perform ARM-specific name mangling for
25872 NEON vector types in order to conform to the AAPCS (see "Procedure
25873 Call Standard for the ARM Architecture", Appendix A). To qualify
25874 for emission with the mangled names defined in that document, a
25875 vector type must not only be of the correct mode but also be
25876 composed of NEON vector element types (e.g. __builtin_neon_qi). */
25879 enum machine_mode mode;
25880 const char *element_type_name;
25881 const char *aapcs_name;
25882 } arm_mangle_map_entry;
25884 static arm_mangle_map_entry arm_mangle_map[] = {
25885 /* 64-bit containerized types. */
25886 { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" },
25887 { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" },
25888 { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" },
25889 { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" },
25890 { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" },
25891 { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" },
25892 { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" },
25893 { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" },
25894 { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" },
25895 /* 128-bit containerized types. */
25896 { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" },
25897 { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" },
25898 { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" },
25899 { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" },
25900 { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" },
25901 { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" },
25902 { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" },
25903 { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" },
25904 { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" },
25905 { VOIDmode, NULL, NULL }
25909 arm_mangle_type (const_tree type)
25911 arm_mangle_map_entry *pos = arm_mangle_map;
25913 /* The ARM ABI documents (10th October 2008) say that "__va_list"
25914 has to be managled as if it is in the "std" namespace. */
25915 if (TARGET_AAPCS_BASED
25916 && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type))
25917 return "St9__va_list";
25919 /* Half-precision float. */
25920 if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16)
25923 if (TREE_CODE (type) != VECTOR_TYPE)
25926 /* Check the mode of the vector type, and the name of the vector
25927 element type, against the table. */
25928 while (pos->mode != VOIDmode)
25930 tree elt_type = TREE_TYPE (type);
25932 if (pos->mode == TYPE_MODE (type)
25933 && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL
25934 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))),
25935 pos->element_type_name))
25936 return pos->aapcs_name;
25941 /* Use the default mangling for unrecognized (possibly user-defined)
25946 /* Order of allocation of core registers for Thumb: this allocation is
25947 written over the corresponding initial entries of the array
25948 initialized with REG_ALLOC_ORDER. We allocate all low registers
25949 first. Saving and restoring a low register is usually cheaper than
25950 using a call-clobbered high register. */
25952 static const int thumb_core_reg_alloc_order[] =
25954 3, 2, 1, 0, 4, 5, 6, 7,
25955 14, 12, 8, 9, 10, 11
25958 /* Adjust register allocation order when compiling for Thumb. */
25961 arm_order_regs_for_local_alloc (void)
25963 const int arm_reg_alloc_order[] = REG_ALLOC_ORDER;
25964 memcpy(reg_alloc_order, arm_reg_alloc_order, sizeof (reg_alloc_order));
25966 memcpy (reg_alloc_order, thumb_core_reg_alloc_order,
25967 sizeof (thumb_core_reg_alloc_order));
25970 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
25973 arm_frame_pointer_required (void)
25975 return (cfun->has_nonlocal_label
25976 || SUBTARGET_FRAME_POINTER_REQUIRED
25977 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()));
25980 /* Only thumb1 can't support conditional execution, so return true if
25981 the target is not thumb1. */
25983 arm_have_conditional_execution (void)
25985 return !TARGET_THUMB1;
25988 /* The AAPCS sets the maximum alignment of a vector to 64 bits. */
25989 static HOST_WIDE_INT
25990 arm_vector_alignment (const_tree type)
25992 HOST_WIDE_INT align = tree_low_cst (TYPE_SIZE (type), 0);
25994 if (TARGET_AAPCS_BASED)
25995 align = MIN (align, 64);
26000 static unsigned int
26001 arm_autovectorize_vector_sizes (void)
26003 return TARGET_NEON_VECTORIZE_DOUBLE ? 0 : (16 | 8);
26007 arm_vector_alignment_reachable (const_tree type, bool is_packed)
26009 /* Vectors which aren't in packed structures will not be less aligned than
26010 the natural alignment of their element type, so this is safe. */
26011 if (TARGET_NEON && !BYTES_BIG_ENDIAN)
26014 return default_builtin_vector_alignment_reachable (type, is_packed);
26018 arm_builtin_support_vector_misalignment (enum machine_mode mode,
26019 const_tree type, int misalignment,
26022 if (TARGET_NEON && !BYTES_BIG_ENDIAN)
26024 HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type);
26029 /* If the misalignment is unknown, we should be able to handle the access
26030 so long as it is not to a member of a packed data structure. */
26031 if (misalignment == -1)
26034 /* Return true if the misalignment is a multiple of the natural alignment
26035 of the vector's element type. This is probably always going to be
26036 true in practice, since we've already established that this isn't a
26038 return ((misalignment % align) == 0);
26041 return default_builtin_support_vector_misalignment (mode, type, misalignment,
26046 arm_conditional_register_usage (void)
26050 if (TARGET_THUMB1 && optimize_size)
26052 /* When optimizing for size on Thumb-1, it's better not
26053 to use the HI regs, because of the overhead of
26055 for (regno = FIRST_HI_REGNUM;
26056 regno <= LAST_HI_REGNUM; ++regno)
26057 fixed_regs[regno] = call_used_regs[regno] = 1;
26060 /* The link register can be clobbered by any branch insn,
26061 but we have no way to track that at present, so mark
26062 it as unavailable. */
26064 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
26066 if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP)
26068 /* VFPv3 registers are disabled when earlier VFP
26069 versions are selected due to the definition of
26070 LAST_VFP_REGNUM. */
26071 for (regno = FIRST_VFP_REGNUM;
26072 regno <= LAST_VFP_REGNUM; ++ regno)
26074 fixed_regs[regno] = 0;
26075 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16
26076 || regno >= FIRST_VFP_REGNUM + 32;
26080 if (TARGET_REALLY_IWMMXT)
26082 regno = FIRST_IWMMXT_GR_REGNUM;
26083 /* The 2002/10/09 revision of the XScale ABI has wCG0
26084 and wCG1 as call-preserved registers. The 2002/11/21
26085 revision changed this so that all wCG registers are
26086 scratch registers. */
26087 for (regno = FIRST_IWMMXT_GR_REGNUM;
26088 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno)
26089 fixed_regs[regno] = 0;
26090 /* The XScale ABI has wR0 - wR9 as scratch registers,
26091 the rest as call-preserved registers. */
26092 for (regno = FIRST_IWMMXT_REGNUM;
26093 regno <= LAST_IWMMXT_REGNUM; ++ regno)
26095 fixed_regs[regno] = 0;
26096 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10;
26100 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
26102 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
26103 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
26105 else if (TARGET_APCS_STACK)
26107 fixed_regs[10] = 1;
26108 call_used_regs[10] = 1;
26110 /* -mcaller-super-interworking reserves r11 for calls to
26111 _interwork_r11_call_via_rN(). Making the register global
26112 is an easy way of ensuring that it remains valid for all
26114 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING
26115 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME)
26117 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;
26118 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;
26119 if (TARGET_CALLER_INTERWORKING)
26120 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;
26122 SUBTARGET_CONDITIONAL_REGISTER_USAGE
26126 arm_preferred_rename_class (reg_class_t rclass)
26128 /* Thumb-2 instructions using LO_REGS may be smaller than instructions
26129 using GENERIC_REGS. During register rename pass, we prefer LO_REGS,
26130 and code size can be reduced. */
26131 if (TARGET_THUMB2 && rclass == GENERAL_REGS)
26137 /* Compute the atrribute "length" of insn "*push_multi".
26138 So this function MUST be kept in sync with that insn pattern. */
26140 arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
26142 int i, regno, hi_reg;
26143 int num_saves = XVECLEN (parallel_op, 0);
26153 regno = REGNO (first_op);
26154 hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
26155 for (i = 1; i < num_saves && !hi_reg; i++)
26157 regno = REGNO (XEXP (XVECEXP (parallel_op, 0, i), 0));
26158 hi_reg |= (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
26166 /* Compute the number of instructions emitted by output_move_double. */
26168 arm_count_output_move_double_insns (rtx *operands)
26172 /* output_move_double may modify the operands array, so call it
26173 here on a copy of the array. */
26174 ops[0] = operands[0];
26175 ops[1] = operands[1];
26176 output_move_double (ops, false, &count);
26181 vfp3_const_double_for_fract_bits (rtx operand)
26183 REAL_VALUE_TYPE r0;
26185 if (!CONST_DOUBLE_P (operand))
26188 REAL_VALUE_FROM_CONST_DOUBLE (r0, operand);
26189 if (exact_real_inverse (DFmode, &r0))
26191 if (exact_real_truncate (DFmode, &r0))
26193 HOST_WIDE_INT value = real_to_integer (&r0);
26194 value = value & 0xffffffff;
26195 if ((value != 0) && ( (value & (value - 1)) == 0))
26196 return int_log2 (value);
26202 /* Emit a memory barrier around an atomic sequence according to MODEL. */
26205 arm_pre_atomic_barrier (enum memmodel model)
26207 if (need_atomic_barrier_p (model, true))
26208 emit_insn (gen_memory_barrier ());
26212 arm_post_atomic_barrier (enum memmodel model)
26214 if (need_atomic_barrier_p (model, false))
26215 emit_insn (gen_memory_barrier ());
26218 /* Emit the load-exclusive and store-exclusive instructions. */
26221 arm_emit_load_exclusive (enum machine_mode mode, rtx rval, rtx mem)
26223 rtx (*gen) (rtx, rtx);
26227 case QImode: gen = gen_arm_load_exclusiveqi; break;
26228 case HImode: gen = gen_arm_load_exclusivehi; break;
26229 case SImode: gen = gen_arm_load_exclusivesi; break;
26230 case DImode: gen = gen_arm_load_exclusivedi; break;
26232 gcc_unreachable ();
26235 emit_insn (gen (rval, mem));
26239 arm_emit_store_exclusive (enum machine_mode mode, rtx bval, rtx rval, rtx mem)
26241 rtx (*gen) (rtx, rtx, rtx);
26245 case QImode: gen = gen_arm_store_exclusiveqi; break;
26246 case HImode: gen = gen_arm_store_exclusivehi; break;
26247 case SImode: gen = gen_arm_store_exclusivesi; break;
26248 case DImode: gen = gen_arm_store_exclusivedi; break;
26250 gcc_unreachable ();
26253 emit_insn (gen (bval, rval, mem));
26256 /* Mark the previous jump instruction as unlikely. */
26259 emit_unlikely_jump (rtx insn)
26261 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
26263 insn = emit_jump_insn (insn);
26264 add_reg_note (insn, REG_BR_PROB, very_unlikely);
26267 /* Expand a compare and swap pattern. */
26270 arm_expand_compare_and_swap (rtx operands[])
26272 rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
26273 enum machine_mode mode;
26274 rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
26276 bval = operands[0];
26277 rval = operands[1];
26279 oldval = operands[3];
26280 newval = operands[4];
26281 is_weak = operands[5];
26282 mod_s = operands[6];
26283 mod_f = operands[7];
26284 mode = GET_MODE (mem);
26290 /* For narrow modes, we're going to perform the comparison in SImode,
26291 so do the zero-extension now. */
26292 rval = gen_reg_rtx (SImode);
26293 oldval = convert_modes (SImode, mode, oldval, true);
26297 /* Force the value into a register if needed. We waited until after
26298 the zero-extension above to do this properly. */
26299 if (!arm_add_operand (oldval, SImode))
26300 oldval = force_reg (SImode, oldval);
26304 if (!cmpdi_operand (oldval, mode))
26305 oldval = force_reg (mode, oldval);
26309 gcc_unreachable ();
26314 case QImode: gen = gen_atomic_compare_and_swapqi_1; break;
26315 case HImode: gen = gen_atomic_compare_and_swaphi_1; break;
26316 case SImode: gen = gen_atomic_compare_and_swapsi_1; break;
26317 case DImode: gen = gen_atomic_compare_and_swapdi_1; break;
26319 gcc_unreachable ();
26322 emit_insn (gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
26324 if (mode == QImode || mode == HImode)
26325 emit_move_insn (operands[1], gen_lowpart (mode, rval));
26327 /* In all cases, we arrange for success to be signaled by Z set.
26328 This arrangement allows for the boolean result to be used directly
26329 in a subsequent branch, post optimization. */
26330 x = gen_rtx_REG (CCmode, CC_REGNUM);
26331 x = gen_rtx_EQ (SImode, x, const0_rtx);
26332 emit_insn (gen_rtx_SET (VOIDmode, bval, x));
26335 /* Split a compare and swap pattern. It is IMPLEMENTATION DEFINED whether
26336 another memory store between the load-exclusive and store-exclusive can
26337 reset the monitor from Exclusive to Open state. This means we must wait
26338 until after reload to split the pattern, lest we get a register spill in
26339 the middle of the atomic sequence. */
26342 arm_split_compare_and_swap (rtx operands[])
26344 rtx rval, mem, oldval, newval, scratch;
26345 enum machine_mode mode;
26346 enum memmodel mod_s, mod_f;
26348 rtx label1, label2, x, cond;
26350 rval = operands[0];
26352 oldval = operands[2];
26353 newval = operands[3];
26354 is_weak = (operands[4] != const0_rtx);
26355 mod_s = (enum memmodel) INTVAL (operands[5]);
26356 mod_f = (enum memmodel) INTVAL (operands[6]);
26357 scratch = operands[7];
26358 mode = GET_MODE (mem);
26360 arm_pre_atomic_barrier (mod_s);
26365 label1 = gen_label_rtx ();
26366 emit_label (label1);
26368 label2 = gen_label_rtx ();
26370 arm_emit_load_exclusive (mode, rval, mem);
26372 cond = arm_gen_compare_reg (NE, rval, oldval, scratch);
26373 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
26374 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
26375 gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
26376 emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x));
26378 arm_emit_store_exclusive (mode, scratch, mem, newval);
26380 /* Weak or strong, we want EQ to be true for success, so that we
26381 match the flags that we got from the compare above. */
26382 cond = gen_rtx_REG (CCmode, CC_REGNUM);
26383 x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx);
26384 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
26388 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
26389 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
26390 gen_rtx_LABEL_REF (Pmode, label1), pc_rtx);
26391 emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x));
26394 if (mod_f != MEMMODEL_RELAXED)
26395 emit_label (label2);
26397 arm_post_atomic_barrier (mod_s);
26399 if (mod_f == MEMMODEL_RELAXED)
26400 emit_label (label2);
26404 arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
26405 rtx value, rtx model_rtx, rtx cond)
26407 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
26408 enum machine_mode mode = GET_MODE (mem);
26409 enum machine_mode wmode = (mode == DImode ? DImode : SImode);
26412 arm_pre_atomic_barrier (model);
26414 label = gen_label_rtx ();
26415 emit_label (label);
26418 new_out = gen_lowpart (wmode, new_out);
26420 old_out = gen_lowpart (wmode, old_out);
26423 value = simplify_gen_subreg (wmode, value, mode, 0);
26425 arm_emit_load_exclusive (mode, old_out, mem);
26434 x = gen_rtx_AND (wmode, old_out, value);
26435 emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
26436 x = gen_rtx_NOT (wmode, new_out);
26437 emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
26441 if (CONST_INT_P (value))
26443 value = GEN_INT (-INTVAL (value));
26449 if (mode == DImode)
26451 /* DImode plus/minus need to clobber flags. */
26452 /* The adddi3 and subdi3 patterns are incorrectly written so that
26453 they require matching operands, even when we could easily support
26454 three operands. Thankfully, this can be fixed up post-splitting,
26455 as the individual add+adc patterns do accept three operands and
26456 post-reload cprop can make these moves go away. */
26457 emit_move_insn (new_out, old_out);
26459 x = gen_adddi3 (new_out, new_out, value);
26461 x = gen_subdi3 (new_out, new_out, value);
26468 x = gen_rtx_fmt_ee (code, wmode, old_out, value);
26469 emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
26473 arm_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out));
26475 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
26476 emit_unlikely_jump (gen_cbranchsi4 (x, cond, const0_rtx, label));
26478 arm_post_atomic_barrier (model);
26481 #define MAX_VECT_LEN 16
26483 struct expand_vec_perm_d
26485 rtx target, op0, op1;
26486 unsigned char perm[MAX_VECT_LEN];
26487 enum machine_mode vmode;
26488 unsigned char nelt;
26493 /* Generate a variable permutation. */
26496 arm_expand_vec_perm_1 (rtx target, rtx op0, rtx op1, rtx sel)
26498 enum machine_mode vmode = GET_MODE (target);
26499 bool one_vector_p = rtx_equal_p (op0, op1);
26501 gcc_checking_assert (vmode == V8QImode || vmode == V16QImode);
26502 gcc_checking_assert (GET_MODE (op0) == vmode);
26503 gcc_checking_assert (GET_MODE (op1) == vmode);
26504 gcc_checking_assert (GET_MODE (sel) == vmode);
26505 gcc_checking_assert (TARGET_NEON);
26509 if (vmode == V8QImode)
26510 emit_insn (gen_neon_vtbl1v8qi (target, op0, sel));
26512 emit_insn (gen_neon_vtbl1v16qi (target, op0, sel));
26518 if (vmode == V8QImode)
26520 pair = gen_reg_rtx (V16QImode);
26521 emit_insn (gen_neon_vcombinev8qi (pair, op0, op1));
26522 pair = gen_lowpart (TImode, pair);
26523 emit_insn (gen_neon_vtbl2v8qi (target, pair, sel));
26527 pair = gen_reg_rtx (OImode);
26528 emit_insn (gen_neon_vcombinev16qi (pair, op0, op1));
26529 emit_insn (gen_neon_vtbl2v16qi (target, pair, sel));
26535 arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
26537 enum machine_mode vmode = GET_MODE (target);
26538 unsigned int i, nelt = GET_MODE_NUNITS (vmode);
26539 bool one_vector_p = rtx_equal_p (op0, op1);
26540 rtx rmask[MAX_VECT_LEN], mask;
26542 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
26543 numbering of elements for big-endian, we must reverse the order. */
26544 gcc_checking_assert (!BYTES_BIG_ENDIAN);
26546 /* The VTBL instruction does not use a modulo index, so we must take care
26547 of that ourselves. */
26548 mask = GEN_INT (one_vector_p ? nelt - 1 : 2 * nelt - 1);
26549 for (i = 0; i < nelt; ++i)
26551 mask = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rmask));
26552 sel = expand_simple_binop (vmode, AND, sel, mask, NULL, 0, OPTAB_LIB_WIDEN);
26554 arm_expand_vec_perm_1 (target, op0, op1, sel);
26557 /* Generate or test for an insn that supports a constant permutation. */
26559 /* Recognize patterns for the VUZP insns. */
26562 arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
26564 unsigned int i, odd, mask, nelt = d->nelt;
26565 rtx out0, out1, in0, in1, x;
26566 rtx (*gen)(rtx, rtx, rtx, rtx);
26568 if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
26571 /* Note that these are little-endian tests. Adjust for big-endian later. */
26572 if (d->perm[0] == 0)
26574 else if (d->perm[0] == 1)
26578 mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
26580 for (i = 0; i < nelt; i++)
26582 unsigned elt = (i * 2 + odd) & mask;
26583 if (d->perm[i] != elt)
26593 case V16QImode: gen = gen_neon_vuzpv16qi_internal; break;
26594 case V8QImode: gen = gen_neon_vuzpv8qi_internal; break;
26595 case V8HImode: gen = gen_neon_vuzpv8hi_internal; break;
26596 case V4HImode: gen = gen_neon_vuzpv4hi_internal; break;
26597 case V4SImode: gen = gen_neon_vuzpv4si_internal; break;
26598 case V2SImode: gen = gen_neon_vuzpv2si_internal; break;
26599 case V2SFmode: gen = gen_neon_vuzpv2sf_internal; break;
26600 case V4SFmode: gen = gen_neon_vuzpv4sf_internal; break;
26602 gcc_unreachable ();
26607 if (BYTES_BIG_ENDIAN)
26609 x = in0, in0 = in1, in1 = x;
26614 out1 = gen_reg_rtx (d->vmode);
26616 x = out0, out0 = out1, out1 = x;
26618 emit_insn (gen (out0, in0, in1, out1));
26622 /* Recognize patterns for the VZIP insns. */
26625 arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
26627 unsigned int i, high, mask, nelt = d->nelt;
26628 rtx out0, out1, in0, in1, x;
26629 rtx (*gen)(rtx, rtx, rtx, rtx);
26631 if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
26634 /* Note that these are little-endian tests. Adjust for big-endian later. */
26636 if (d->perm[0] == high)
26638 else if (d->perm[0] == 0)
26642 mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
26644 for (i = 0; i < nelt / 2; i++)
26646 unsigned elt = (i + high) & mask;
26647 if (d->perm[i * 2] != elt)
26649 elt = (elt + nelt) & mask;
26650 if (d->perm[i * 2 + 1] != elt)
26660 case V16QImode: gen = gen_neon_vzipv16qi_internal; break;
26661 case V8QImode: gen = gen_neon_vzipv8qi_internal; break;
26662 case V8HImode: gen = gen_neon_vzipv8hi_internal; break;
26663 case V4HImode: gen = gen_neon_vzipv4hi_internal; break;
26664 case V4SImode: gen = gen_neon_vzipv4si_internal; break;
26665 case V2SImode: gen = gen_neon_vzipv2si_internal; break;
26666 case V2SFmode: gen = gen_neon_vzipv2sf_internal; break;
26667 case V4SFmode: gen = gen_neon_vzipv4sf_internal; break;
26669 gcc_unreachable ();
26674 if (BYTES_BIG_ENDIAN)
26676 x = in0, in0 = in1, in1 = x;
26681 out1 = gen_reg_rtx (d->vmode);
26683 x = out0, out0 = out1, out1 = x;
26685 emit_insn (gen (out0, in0, in1, out1));
26689 /* Recognize patterns for the VREV insns. */
26692 arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
26694 unsigned int i, j, diff, nelt = d->nelt;
26695 rtx (*gen)(rtx, rtx, rtx);
26697 if (!d->one_vector_p)
26706 case V16QImode: gen = gen_neon_vrev64v16qi; break;
26707 case V8QImode: gen = gen_neon_vrev64v8qi; break;
26715 case V16QImode: gen = gen_neon_vrev32v16qi; break;
26716 case V8QImode: gen = gen_neon_vrev32v8qi; break;
26717 case V8HImode: gen = gen_neon_vrev64v8hi; break;
26718 case V4HImode: gen = gen_neon_vrev64v4hi; break;
26726 case V16QImode: gen = gen_neon_vrev16v16qi; break;
26727 case V8QImode: gen = gen_neon_vrev16v8qi; break;
26728 case V8HImode: gen = gen_neon_vrev32v8hi; break;
26729 case V4HImode: gen = gen_neon_vrev32v4hi; break;
26730 case V4SImode: gen = gen_neon_vrev64v4si; break;
26731 case V2SImode: gen = gen_neon_vrev64v2si; break;
26732 case V4SFmode: gen = gen_neon_vrev64v4sf; break;
26733 case V2SFmode: gen = gen_neon_vrev64v2sf; break;
26742 for (i = 0; i < nelt ; i += diff + 1)
26743 for (j = 0; j <= diff; j += 1)
26745 /* This is guaranteed to be true as the value of diff
26746 is 7, 3, 1 and we should have enough elements in the
26747 queue to generate this. Getting a vector mask with a
26748 value of diff other than these values implies that
26749 something is wrong by the time we get here. */
26750 gcc_assert (i + j < nelt);
26751 if (d->perm[i + j] != i + diff - j)
26759 /* ??? The third operand is an artifact of the builtin infrastructure
26760 and is ignored by the actual instruction. */
26761 emit_insn (gen (d->target, d->op0, const0_rtx));
26765 /* Recognize patterns for the VTRN insns. */
26768 arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
26770 unsigned int i, odd, mask, nelt = d->nelt;
26771 rtx out0, out1, in0, in1, x;
26772 rtx (*gen)(rtx, rtx, rtx, rtx);
26774 if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
26777 /* Note that these are little-endian tests. Adjust for big-endian later. */
26778 if (d->perm[0] == 0)
26780 else if (d->perm[0] == 1)
26784 mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
26786 for (i = 0; i < nelt; i += 2)
26788 if (d->perm[i] != i + odd)
26790 if (d->perm[i + 1] != ((i + nelt + odd) & mask))
26800 case V16QImode: gen = gen_neon_vtrnv16qi_internal; break;
26801 case V8QImode: gen = gen_neon_vtrnv8qi_internal; break;
26802 case V8HImode: gen = gen_neon_vtrnv8hi_internal; break;
26803 case V4HImode: gen = gen_neon_vtrnv4hi_internal; break;
26804 case V4SImode: gen = gen_neon_vtrnv4si_internal; break;
26805 case V2SImode: gen = gen_neon_vtrnv2si_internal; break;
26806 case V2SFmode: gen = gen_neon_vtrnv2sf_internal; break;
26807 case V4SFmode: gen = gen_neon_vtrnv4sf_internal; break;
26809 gcc_unreachable ();
26814 if (BYTES_BIG_ENDIAN)
26816 x = in0, in0 = in1, in1 = x;
26821 out1 = gen_reg_rtx (d->vmode);
26823 x = out0, out0 = out1, out1 = x;
26825 emit_insn (gen (out0, in0, in1, out1));
26829 /* Recognize patterns for the VEXT insns. */
26832 arm_evpc_neon_vext (struct expand_vec_perm_d *d)
26834 unsigned int i, nelt = d->nelt;
26835 rtx (*gen) (rtx, rtx, rtx, rtx);
26838 unsigned int location;
26840 unsigned int next = d->perm[0] + 1;
26842 /* TODO: Handle GCC's numbering of elements for big-endian. */
26843 if (BYTES_BIG_ENDIAN)
26846 /* Check if the extracted indexes are increasing by one. */
26847 for (i = 1; i < nelt; next++, i++)
26849 /* If we hit the most significant element of the 2nd vector in
26850 the previous iteration, no need to test further. */
26851 if (next == 2 * nelt)
26854 /* If we are operating on only one vector: it could be a
26855 rotation. If there are only two elements of size < 64, let
26856 arm_evpc_neon_vrev catch it. */
26857 if (d->one_vector_p && (next == nelt))
26859 if ((nelt == 2) && (d->vmode != V2DImode))
26865 if (d->perm[i] != next)
26869 location = d->perm[0];
26873 case V16QImode: gen = gen_neon_vextv16qi; break;
26874 case V8QImode: gen = gen_neon_vextv8qi; break;
26875 case V4HImode: gen = gen_neon_vextv4hi; break;
26876 case V8HImode: gen = gen_neon_vextv8hi; break;
26877 case V2SImode: gen = gen_neon_vextv2si; break;
26878 case V4SImode: gen = gen_neon_vextv4si; break;
26879 case V2SFmode: gen = gen_neon_vextv2sf; break;
26880 case V4SFmode: gen = gen_neon_vextv4sf; break;
26881 case V2DImode: gen = gen_neon_vextv2di; break;
26890 offset = GEN_INT (location);
26891 emit_insn (gen (d->target, d->op0, d->op1, offset));
26895 /* The NEON VTBL instruction is a fully variable permuation that's even
26896 stronger than what we expose via VEC_PERM_EXPR. What it doesn't do
26897 is mask the index operand as VEC_PERM_EXPR requires. Therefore we
26898 can do slightly better by expanding this as a constant where we don't
26899 have to apply a mask. */
26902 arm_evpc_neon_vtbl (struct expand_vec_perm_d *d)
26904 rtx rperm[MAX_VECT_LEN], sel;
26905 enum machine_mode vmode = d->vmode;
26906 unsigned int i, nelt = d->nelt;
26908 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
26909 numbering of elements for big-endian, we must reverse the order. */
26910 if (BYTES_BIG_ENDIAN)
26916 /* Generic code will try constant permutation twice. Once with the
26917 original mode and again with the elements lowered to QImode.
26918 So wait and don't do the selector expansion ourselves. */
26919 if (vmode != V8QImode && vmode != V16QImode)
26922 for (i = 0; i < nelt; ++i)
26923 rperm[i] = GEN_INT (d->perm[i]);
26924 sel = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rperm));
26925 sel = force_reg (vmode, sel);
26927 arm_expand_vec_perm_1 (d->target, d->op0, d->op1, sel);
26932 arm_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
26934 /* Check if the input mask matches vext before reordering the
26937 if (arm_evpc_neon_vext (d))
26940 /* The pattern matching functions above are written to look for a small
26941 number to begin the sequence (0, 1, N/2). If we begin with an index
26942 from the second operand, we can swap the operands. */
26943 if (d->perm[0] >= d->nelt)
26945 unsigned i, nelt = d->nelt;
26948 for (i = 0; i < nelt; ++i)
26949 d->perm[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
26958 if (arm_evpc_neon_vuzp (d))
26960 if (arm_evpc_neon_vzip (d))
26962 if (arm_evpc_neon_vrev (d))
26964 if (arm_evpc_neon_vtrn (d))
26966 return arm_evpc_neon_vtbl (d);
26971 /* Expand a vec_perm_const pattern. */
26974 arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel)
26976 struct expand_vec_perm_d d;
26977 int i, nelt, which;
26983 d.vmode = GET_MODE (target);
26984 gcc_assert (VECTOR_MODE_P (d.vmode));
26985 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
26986 d.testing_p = false;
26988 for (i = which = 0; i < nelt; ++i)
26990 rtx e = XVECEXP (sel, 0, i);
26991 int ei = INTVAL (e) & (2 * nelt - 1);
26992 which |= (ei < nelt ? 1 : 2);
27002 d.one_vector_p = false;
27003 if (!rtx_equal_p (op0, op1))
27006 /* The elements of PERM do not suggest that only the first operand
27007 is used, but both operands are identical. Allow easier matching
27008 of the permutation by folding the permutation into the single
27012 for (i = 0; i < nelt; ++i)
27013 d.perm[i] &= nelt - 1;
27015 d.one_vector_p = true;
27020 d.one_vector_p = true;
27024 return arm_expand_vec_perm_const_1 (&d);
27027 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
27030 arm_vectorize_vec_perm_const_ok (enum machine_mode vmode,
27031 const unsigned char *sel)
27033 struct expand_vec_perm_d d;
27034 unsigned int i, nelt, which;
27038 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
27039 d.testing_p = true;
27040 memcpy (d.perm, sel, nelt);
27042 /* Categorize the set of elements in the selector. */
27043 for (i = which = 0; i < nelt; ++i)
27045 unsigned char e = d.perm[i];
27046 gcc_assert (e < 2 * nelt);
27047 which |= (e < nelt ? 1 : 2);
27050 /* For all elements from second vector, fold the elements to first. */
27052 for (i = 0; i < nelt; ++i)
27055 /* Check whether the mask can be applied to the vector type. */
27056 d.one_vector_p = (which != 3);
27058 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
27059 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
27060 if (!d.one_vector_p)
27061 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
27064 ret = arm_expand_vec_perm_const_1 (&d);
27071 arm_autoinc_modes_ok_p (enum machine_mode mode, enum arm_auto_incmodes code)
27073 /* If we are soft float and we do not have ldrd
27074 then all auto increment forms are ok. */
27075 if (TARGET_SOFT_FLOAT && (TARGET_LDRD || GET_MODE_SIZE (mode) <= 4))
27080 /* Post increment and Pre Decrement are supported for all
27081 instruction forms except for vector forms. */
27084 if (VECTOR_MODE_P (mode))
27086 if (code != ARM_PRE_DEC)
27096 /* Without LDRD and mode size greater than
27097 word size, there is no point in auto-incrementing
27098 because ldm and stm will not have these forms. */
27099 if (!TARGET_LDRD && GET_MODE_SIZE (mode) > 4)
27102 /* Vector and floating point modes do not support
27103 these auto increment forms. */
27104 if (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
27117 /* The default expansion of general 64-bit shifts in core-regs is suboptimal,
27118 on ARM, since we know that shifts by negative amounts are no-ops.
27119 Additionally, the default expansion code is not available or suitable
27120 for post-reload insn splits (this can occur when the register allocator
27121 chooses not to do a shift in NEON).
27123 This function is used in both initial expand and post-reload splits, and
27124 handles all kinds of 64-bit shifts.
27126 Input requirements:
27127 - It is safe for the input and output to be the same register, but
27128 early-clobber rules apply for the shift amount and scratch registers.
27129 - Shift by register requires both scratch registers. In all other cases
27130 the scratch registers may be NULL.
27131 - Ashiftrt by a register also clobbers the CC register. */
27133 arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
27134 rtx amount, rtx scratch1, rtx scratch2)
27136 rtx out_high = gen_highpart (SImode, out);
27137 rtx out_low = gen_lowpart (SImode, out);
27138 rtx in_high = gen_highpart (SImode, in);
27139 rtx in_low = gen_lowpart (SImode, in);
27142 in = the register pair containing the input value.
27143 out = the destination register pair.
27144 up = the high- or low-part of each pair.
27145 down = the opposite part to "up".
27146 In a shift, we can consider bits to shift from "up"-stream to
27147 "down"-stream, so in a left-shift "up" is the low-part and "down"
27148 is the high-part of each register pair. */
27150 rtx out_up = code == ASHIFT ? out_low : out_high;
27151 rtx out_down = code == ASHIFT ? out_high : out_low;
27152 rtx in_up = code == ASHIFT ? in_low : in_high;
27153 rtx in_down = code == ASHIFT ? in_high : in_low;
27155 gcc_assert (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT);
27157 && (REG_P (out) || GET_CODE (out) == SUBREG)
27158 && GET_MODE (out) == DImode);
27160 && (REG_P (in) || GET_CODE (in) == SUBREG)
27161 && GET_MODE (in) == DImode);
27163 && (((REG_P (amount) || GET_CODE (amount) == SUBREG)
27164 && GET_MODE (amount) == SImode)
27165 || CONST_INT_P (amount)));
27166 gcc_assert (scratch1 == NULL
27167 || (GET_CODE (scratch1) == SCRATCH)
27168 || (GET_MODE (scratch1) == SImode
27169 && REG_P (scratch1)));
27170 gcc_assert (scratch2 == NULL
27171 || (GET_CODE (scratch2) == SCRATCH)
27172 || (GET_MODE (scratch2) == SImode
27173 && REG_P (scratch2)));
27174 gcc_assert (!REG_P (out) || !REG_P (amount)
27175 || !HARD_REGISTER_P (out)
27176 || (REGNO (out) != REGNO (amount)
27177 && REGNO (out) + 1 != REGNO (amount)));
27179 /* Macros to make following code more readable. */
27180 #define SUB_32(DEST,SRC) \
27181 gen_addsi3 ((DEST), (SRC), GEN_INT (-32))
27182 #define RSB_32(DEST,SRC) \
27183 gen_subsi3 ((DEST), GEN_INT (32), (SRC))
27184 #define SUB_S_32(DEST,SRC) \
27185 gen_addsi3_compare0 ((DEST), (SRC), \
27187 #define SET(DEST,SRC) \
27188 gen_rtx_SET (SImode, (DEST), (SRC))
27189 #define SHIFT(CODE,SRC,AMOUNT) \
27190 gen_rtx_fmt_ee ((CODE), SImode, (SRC), (AMOUNT))
27191 #define LSHIFT(CODE,SRC,AMOUNT) \
27192 gen_rtx_fmt_ee ((CODE) == ASHIFT ? ASHIFT : LSHIFTRT, \
27193 SImode, (SRC), (AMOUNT))
27194 #define REV_LSHIFT(CODE,SRC,AMOUNT) \
27195 gen_rtx_fmt_ee ((CODE) == ASHIFT ? LSHIFTRT : ASHIFT, \
27196 SImode, (SRC), (AMOUNT))
27198 gen_rtx_IOR (SImode, (A), (B))
27199 #define BRANCH(COND,LABEL) \
27200 gen_arm_cond_branch ((LABEL), \
27201 gen_rtx_ ## COND (CCmode, cc_reg, \
27205 /* Shifts by register and shifts by constant are handled separately. */
27206 if (CONST_INT_P (amount))
27208 /* We have a shift-by-constant. */
27210 /* First, handle out-of-range shift amounts.
27211 In both cases we try to match the result an ARM instruction in a
27212 shift-by-register would give. This helps reduce execution
27213 differences between optimization levels, but it won't stop other
27214 parts of the compiler doing different things. This is "undefined
27215 behaviour, in any case. */
27216 if (INTVAL (amount) <= 0)
27217 emit_insn (gen_movdi (out, in));
27218 else if (INTVAL (amount) >= 64)
27220 if (code == ASHIFTRT)
27222 rtx const31_rtx = GEN_INT (31);
27223 emit_insn (SET (out_down, SHIFT (code, in_up, const31_rtx)));
27224 emit_insn (SET (out_up, SHIFT (code, in_up, const31_rtx)));
27227 emit_insn (gen_movdi (out, const0_rtx));
27230 /* Now handle valid shifts. */
27231 else if (INTVAL (amount) < 32)
27233 /* Shifts by a constant less than 32. */
27234 rtx reverse_amount = GEN_INT (32 - INTVAL (amount));
27236 emit_insn (SET (out_down, LSHIFT (code, in_down, amount)));
27237 emit_insn (SET (out_down,
27238 ORR (REV_LSHIFT (code, in_up, reverse_amount),
27240 emit_insn (SET (out_up, SHIFT (code, in_up, amount)));
27244 /* Shifts by a constant greater than 31. */
27245 rtx adj_amount = GEN_INT (INTVAL (amount) - 32);
27247 emit_insn (SET (out_down, SHIFT (code, in_up, adj_amount)));
27248 if (code == ASHIFTRT)
27249 emit_insn (gen_ashrsi3 (out_up, in_up,
27252 emit_insn (SET (out_up, const0_rtx));
27257 /* We have a shift-by-register. */
27258 rtx cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
27260 /* This alternative requires the scratch registers. */
27261 gcc_assert (scratch1 && REG_P (scratch1));
27262 gcc_assert (scratch2 && REG_P (scratch2));
27264 /* We will need the values "amount-32" and "32-amount" later.
27265 Swapping them around now allows the later code to be more general. */
27269 emit_insn (SUB_32 (scratch1, amount));
27270 emit_insn (RSB_32 (scratch2, amount));
27273 emit_insn (RSB_32 (scratch1, amount));
27274 /* Also set CC = amount > 32. */
27275 emit_insn (SUB_S_32 (scratch2, amount));
27278 emit_insn (RSB_32 (scratch1, amount));
27279 emit_insn (SUB_32 (scratch2, amount));
27282 gcc_unreachable ();
27285 /* Emit code like this:
27288 out_down = in_down << amount;
27289 out_down = (in_up << (amount - 32)) | out_down;
27290 out_down = ((unsigned)in_up >> (32 - amount)) | out_down;
27291 out_up = in_up << amount;
27294 out_down = in_down >> amount;
27295 out_down = (in_up << (32 - amount)) | out_down;
27297 out_down = ((signed)in_up >> (amount - 32)) | out_down;
27298 out_up = in_up << amount;
27301 out_down = in_down >> amount;
27302 out_down = (in_up << (32 - amount)) | out_down;
27304 out_down = ((unsigned)in_up >> (amount - 32)) | out_down;
27305 out_up = in_up << amount;
27307 The ARM and Thumb2 variants are the same but implemented slightly
27308 differently. If this were only called during expand we could just
27309 use the Thumb2 case and let combine do the right thing, but this
27310 can also be called from post-reload splitters. */
27312 emit_insn (SET (out_down, LSHIFT (code, in_down, amount)));
27314 if (!TARGET_THUMB2)
27316 /* Emit code for ARM mode. */
27317 emit_insn (SET (out_down,
27318 ORR (SHIFT (ASHIFT, in_up, scratch1), out_down)));
27319 if (code == ASHIFTRT)
27321 rtx done_label = gen_label_rtx ();
27322 emit_jump_insn (BRANCH (LT, done_label));
27323 emit_insn (SET (out_down, ORR (SHIFT (ASHIFTRT, in_up, scratch2),
27325 emit_label (done_label);
27328 emit_insn (SET (out_down, ORR (SHIFT (LSHIFTRT, in_up, scratch2),
27333 /* Emit code for Thumb2 mode.
27334 Thumb2 can't do shift and or in one insn. */
27335 emit_insn (SET (scratch1, SHIFT (ASHIFT, in_up, scratch1)));
27336 emit_insn (gen_iorsi3 (out_down, out_down, scratch1));
27338 if (code == ASHIFTRT)
27340 rtx done_label = gen_label_rtx ();
27341 emit_jump_insn (BRANCH (LT, done_label));
27342 emit_insn (SET (scratch2, SHIFT (ASHIFTRT, in_up, scratch2)));
27343 emit_insn (SET (out_down, ORR (out_down, scratch2)));
27344 emit_label (done_label);
27348 emit_insn (SET (scratch2, SHIFT (LSHIFTRT, in_up, scratch2)));
27349 emit_insn (gen_iorsi3 (out_down, out_down, scratch2));
27353 emit_insn (SET (out_up, SHIFT (code, in_up, amount)));
27368 /* Returns true if a valid comparison operation and makes
27369 the operands in a form that is valid. */
27371 arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
27373 enum rtx_code code = GET_CODE (*comparison);
27375 enum machine_mode mode = (GET_MODE (*op1) == VOIDmode)
27376 ? GET_MODE (*op2) : GET_MODE (*op1);
27378 gcc_assert (GET_MODE (*op1) != VOIDmode || GET_MODE (*op2) != VOIDmode);
27380 if (code == UNEQ || code == LTGT)
27383 code_int = (int)code;
27384 arm_canonicalize_comparison (&code_int, op1, op2, 0);
27385 PUT_CODE (*comparison, (enum rtx_code)code_int);
27390 if (!arm_add_operand (*op1, mode))
27391 *op1 = force_reg (mode, *op1);
27392 if (!arm_add_operand (*op2, mode))
27393 *op2 = force_reg (mode, *op2);
27397 if (!cmpdi_operand (*op1, mode))
27398 *op1 = force_reg (mode, *op1);
27399 if (!cmpdi_operand (*op2, mode))
27400 *op2 = force_reg (mode, *op2);
27405 if (!arm_float_compare_operand (*op1, mode))
27406 *op1 = force_reg (mode, *op1);
27407 if (!arm_float_compare_operand (*op2, mode))
27408 *op2 = force_reg (mode, *op2);
27418 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
27420 static unsigned HOST_WIDE_INT
27421 arm_asan_shadow_offset (void)
27423 return (unsigned HOST_WIDE_INT) 1 << 29;
27426 #include "gt-arm.h"