1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-flags.h"
37 #include "insn-attr.h"
49 /* Forward definitions of types. */
50 typedef struct minipool_node Mnode;
51 typedef struct minipool_fixup Mfix;
53 /* In order to improve the layout of the prototypes below
54 some short type abbreviations are defined here. */
55 #define Hint HOST_WIDE_INT
56 #define Mmode enum machine_mode
57 #define Ulong unsigned long
59 /* Forward function declarations. */
60 static void arm_add_gc_roots PARAMS ((void));
61 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
62 static int arm_naked_function_p PARAMS ((tree));
63 static Ulong bit_count PARAMS ((signed int));
64 static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
65 static int eliminate_lr2ip PARAMS ((rtx *));
66 static rtx emit_multi_reg_push PARAMS ((int));
67 static rtx emit_sfm PARAMS ((int, int));
68 static const char * fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
69 static arm_cc get_arm_condition_code PARAMS ((rtx));
70 static void init_fpa_table PARAMS ((void));
71 static Hint int_log2 PARAMS ((Hint));
72 static rtx is_jump_table PARAMS ((rtx));
73 static const char * output_multi_immediate PARAMS ((rtx *, const char *, const char *, int, Hint));
74 static void print_multi_reg PARAMS ((FILE *, const char *, int, int, int));
75 static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint));
76 static const char * shift_op PARAMS ((rtx, Hint *));
77 static void arm_init_machine_status PARAMS ((struct function *));
78 static void arm_mark_machine_status PARAMS ((struct function *));
79 static int number_of_first_bit_set PARAMS ((int));
80 static void replace_symbols_in_block PARAMS ((tree, rtx, rtx));
81 static void thumb_exit PARAMS ((FILE *, int, rtx));
82 static void thumb_pushpop PARAMS ((FILE *, int, int));
83 static const char * thumb_condition_code PARAMS ((rtx, int));
84 static rtx is_jump_table PARAMS ((rtx));
85 static Hint get_jump_table_size PARAMS ((rtx));
86 static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint));
87 static Mnode * add_minipool_forward_ref PARAMS ((Mfix *));
88 static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint));
89 static Mnode * add_minipool_backward_ref PARAMS ((Mfix *));
90 static void assign_minipool_offsets PARAMS ((Mfix *));
91 static void arm_print_value PARAMS ((FILE *, rtx));
92 static void dump_minipool PARAMS ((rtx));
93 static int arm_barrier_cost PARAMS ((rtx));
94 static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
95 static void push_minipool_barrier PARAMS ((rtx, Hint));
96 static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
97 static void note_invalid_constants PARAMS ((rtx, Hint));
98 static int current_file_function_operand PARAMS ((rtx));
104 /* Obstack for minipool constant handling. */
105 static struct obstack minipool_obstack;
106 static char *minipool_startobj;
108 #define obstack_chunk_alloc xmalloc
109 #define obstack_chunk_free free
111 /* The maximum number of insns skipped which will be conditionalised if
113 static int max_insns_skipped = 5;
115 extern FILE * asm_out_file;
117 /* True if we are currently building a constant table. */
118 int making_const_table;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 rtx arm_compare_op0, arm_compare_op1;
124 /* What type of floating point are we tuning for? */
125 enum floating_point_type arm_fpu;
127 /* What type of floating point instructions are available? */
128 enum floating_point_type arm_fpu_arch;
130 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
131 enum prog_mode_type arm_prgmode;
133 /* Set by the -mfp=... option. */
134 const char * target_fp_name = NULL;
136 /* Used to parse -mstructure_size_boundary command line option. */
137 const char * structure_size_string = NULL;
138 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
140 /* Bit values used to identify processor capabilities. */
141 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
142 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
143 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
144 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
145 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
146 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
147 #define FL_THUMB (1 << 6) /* Thumb aware */
148 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
149 #define FL_STRONG (1 << 8) /* StrongARM */
150 #define FL_ARCH5E (1 << 9) /* El Segundo extenstions to v5 */
151 #define FL_XSCALE (1 << 10) /* XScale */
153 /* The bits in this mask specify which instructions we are
154 allowed to generate. */
155 static int insn_flags = 0;
157 /* The bits in this mask specify which instruction scheduling options should
158 be used. Note - there is an overlap with the FL_FAST_MULT. For some
159 hardware we want to be able to generate the multiply instructions, but to
160 tune as if they were not present in the architecture. */
161 static int tune_flags = 0;
163 /* The following are used in the arm.md file as equivalents to bits
164 in the above two flag variables. */
166 /* Nonzero if this is an "M" variant of the processor. */
167 int arm_fast_multiply = 0;
169 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
172 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
175 /* Nonzero if this chip can benefit from load scheduling. */
176 int arm_ld_sched = 0;
178 /* Nonzero if this chip is a StrongARM. */
179 int arm_is_strong = 0;
181 /* Nonzero if this chip is an XScale. */
182 int arm_is_xscale = 0;
184 /* Nonzero if this chip is a an ARM6 or an ARM7. */
185 int arm_is_6_or_7 = 0;
187 /* Nonzero if generating Thumb instructions. */
190 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
191 must report the mode of the memory reference from PRINT_OPERAND to
192 PRINT_OPERAND_ADDRESS. */
193 enum machine_mode output_memory_reference_mode;
195 /* Nonzero if the prologue must setup `fp'. */
196 int current_function_anonymous_args;
198 /* The register number to be used for the PIC offset register. */
199 const char * arm_pic_register_string = NULL;
200 int arm_pic_register = 9;
202 /* Set to 1 when a return insn is output, this means that the epilogue
204 int return_used_this_function;
206 /* Set to 1 after arm_reorg has started. Reset to start at the start of
207 the next function. */
208 static int after_arm_reorg = 0;
210 /* The maximum number of insns to be used when loading a constant. */
211 static int arm_constant_limit = 3;
213 /* For an explanation of these variables, see final_prescan_insn below. */
215 enum arm_cond_code arm_current_cc;
217 int arm_target_label;
219 /* The condition codes of the ARM, and the inverse function. */
220 const char * arm_condition_codes[] =
222 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
223 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
226 #define streq(string1, string2) (strcmp (string1, string2) == 0)
228 /* Initialization code. */
236 /* Not all of these give usefully different compilation alternatives,
237 but there is no simple way of generalizing them. */
238 static struct processors all_cores[] =
242 {"arm2", FL_CO_PROC | FL_MODE26 },
243 {"arm250", FL_CO_PROC | FL_MODE26 },
244 {"arm3", FL_CO_PROC | FL_MODE26 },
245 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
246 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
247 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
248 {"arm610", FL_MODE26 | FL_MODE32 },
249 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
250 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
251 /* arm7m doesn't exist on its own, but only with D, (and I), but
252 those don't alter the code, so arm7m is sometimes used. */
253 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
254 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
255 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
256 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
257 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
258 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
259 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
260 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
261 {"arm710", FL_MODE26 | FL_MODE32 },
262 {"arm720", FL_MODE26 | FL_MODE32 },
263 {"arm710c", FL_MODE26 | FL_MODE32 },
264 {"arm7100", FL_MODE26 | FL_MODE32 },
265 {"arm7500", FL_MODE26 | FL_MODE32 },
266 /* Doesn't have an external co-proc, but does have embedded fpu. */
267 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
268 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
269 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
270 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
271 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
272 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
273 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
274 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
275 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
276 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
277 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
278 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_ARCH5 },
283 static struct processors all_architectures[] =
285 /* ARM Architectures */
287 { "armv2", FL_CO_PROC | FL_MODE26 },
288 { "armv2a", FL_CO_PROC | FL_MODE26 },
289 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
290 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
291 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
292 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
293 implementations that support it, so we will leave it out for now. */
294 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
295 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
296 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
297 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
301 /* This is a magic stucture. The 'string' field is magically filled in
302 with a pointer to the value specified by the user on the command line
303 assuming that the user has specified such a value. */
305 struct arm_cpu_select arm_select[] =
307 /* string name processors */
308 { NULL, "-mcpu=", all_cores },
309 { NULL, "-march=", all_architectures },
310 { NULL, "-mtune=", all_cores }
313 /* Return the number of bits set in value' */
318 unsigned long count = 0;
322 value &= ~(value & -value);
329 /* Fix up any incompatible options that the user has specified.
330 This has now turned into a maze. */
332 arm_override_options ()
336 /* Set up the flags based on the cpu/architecture selected by the user. */
337 for (i = ARRAY_SIZE (arm_select); i--;)
339 struct arm_cpu_select * ptr = arm_select + i;
341 if (ptr->string != NULL && ptr->string[0] != '\0')
343 const struct processors * sel;
345 for (sel = ptr->processors; sel->name != NULL; sel++)
346 if (streq (ptr->string, sel->name))
349 tune_flags = sel->flags;
352 /* If we have been given an architecture and a processor
353 make sure that they are compatible. We only generate
354 a warning though, and we prefer the CPU over the
356 if (insn_flags != 0 && (insn_flags ^ sel->flags))
357 warning ("switch -mcpu=%s conflicts with -march= switch",
360 insn_flags = sel->flags;
366 if (sel->name == NULL)
367 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
371 /* If the user did not specify a processor, choose one for them. */
374 struct processors * sel;
376 static struct cpu_default
383 { TARGET_CPU_arm2, "arm2" },
384 { TARGET_CPU_arm6, "arm6" },
385 { TARGET_CPU_arm610, "arm610" },
386 { TARGET_CPU_arm710, "arm710" },
387 { TARGET_CPU_arm7m, "arm7m" },
388 { TARGET_CPU_arm7500fe, "arm7500fe" },
389 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
390 { TARGET_CPU_arm8, "arm8" },
391 { TARGET_CPU_arm810, "arm810" },
392 { TARGET_CPU_arm9, "arm9" },
393 { TARGET_CPU_strongarm, "strongarm" },
394 { TARGET_CPU_xscale, "xscale" },
395 { TARGET_CPU_generic, "arm" },
398 struct cpu_default * def;
400 /* Find the default. */
401 for (def = cpu_defaults; def->name; def++)
402 if (def->cpu == TARGET_CPU_DEFAULT)
405 /* Make sure we found the default CPU. */
406 if (def->name == NULL)
409 /* Find the default CPU's flags. */
410 for (sel = all_cores; sel->name != NULL; sel++)
411 if (streq (def->name, sel->name))
414 if (sel->name == NULL)
417 insn_flags = sel->flags;
419 /* Now check to see if the user has specified some command line
420 switch that require certain abilities from the cpu. */
423 if (TARGET_INTERWORK || TARGET_THUMB)
425 sought |= (FL_THUMB | FL_MODE32);
427 /* Force apcs-32 to be used for interworking. */
428 target_flags |= ARM_FLAG_APCS_32;
430 /* There are no ARM processors that support both APCS-26 and
431 interworking. Therefore we force FL_MODE26 to be removed
432 from insn_flags here (if it was set), so that the search
433 below will always be able to find a compatible processor. */
434 insn_flags &= ~FL_MODE26;
436 else if (!TARGET_APCS_32)
439 if (sought != 0 && ((sought & insn_flags) != sought))
441 /* Try to locate a CPU type that supports all of the abilities
442 of the default CPU, plus the extra abilities requested by
444 for (sel = all_cores; sel->name != NULL; sel++)
445 if ((sel->flags & sought) == (sought | insn_flags))
448 if (sel->name == NULL)
450 unsigned int current_bit_count = 0;
451 struct processors * best_fit = NULL;
453 /* Ideally we would like to issue an error message here
454 saying that it was not possible to find a CPU compatible
455 with the default CPU, but which also supports the command
456 line options specified by the programmer, and so they
457 ought to use the -mcpu=<name> command line option to
458 override the default CPU type.
460 Unfortunately this does not work with multilibing. We
461 need to be able to support multilibs for -mapcs-26 and for
462 -mthumb-interwork and there is no CPU that can support both
463 options. Instead if we cannot find a cpu that has both the
464 characteristics of the default cpu and the given command line
465 options we scan the array again looking for a best match. */
466 for (sel = all_cores; sel->name != NULL; sel++)
467 if ((sel->flags & sought) == sought)
471 count = bit_count (sel->flags & insn_flags);
473 if (count >= current_bit_count)
476 current_bit_count = count;
480 if (best_fit == NULL)
486 insn_flags = sel->flags;
490 /* If tuning has not been specified, tune for whichever processor or
491 architecture has been selected. */
493 tune_flags = insn_flags;
495 /* Make sure that the processor choice does not conflict with any of the
496 other command line choices. */
497 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
499 /* If APCS-32 was not the default then it must have been set by the
500 user, so issue a warning message. If the user has specified
501 "-mapcs-32 -mcpu=arm2" then we loose here. */
502 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
503 warning ("target CPU does not support APCS-32" );
504 target_flags &= ~ARM_FLAG_APCS_32;
506 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
508 warning ("target CPU does not support APCS-26" );
509 target_flags |= ARM_FLAG_APCS_32;
512 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
514 warning ("target CPU does not support interworking" );
515 target_flags &= ~ARM_FLAG_INTERWORK;
518 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
520 warning ("target CPU does not supoport THUMB instructions.");
521 target_flags &= ~ARM_FLAG_THUMB;
524 if (TARGET_APCS_FRAME && TARGET_THUMB)
526 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
527 target_flags &= ~ARM_FLAG_APCS_FRAME;
530 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
531 from here where no function is being compiled currently. */
532 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
534 warning ("enabling backtrace support is only meaningful when compiling for the Thumb.");
536 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
537 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
539 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
540 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
542 /* If interworking is enabled then APCS-32 must be selected as well. */
543 if (TARGET_INTERWORK)
546 warning ("interworking forces APCS-32 to be used" );
547 target_flags |= ARM_FLAG_APCS_32;
550 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
552 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
553 target_flags |= ARM_FLAG_APCS_FRAME;
556 if (TARGET_POKE_FUNCTION_NAME)
557 target_flags |= ARM_FLAG_APCS_FRAME;
559 if (TARGET_APCS_REENT && flag_pic)
560 fatal ("-fpic and -mapcs-reent are incompatible");
562 if (TARGET_APCS_REENT)
563 warning ("APCS reentrant code not supported. Ignored");
565 /* If this target is normally configured to use APCS frames, warn if they
566 are turned off and debugging is turned on. */
568 && write_symbols != NO_DEBUG
569 && !TARGET_APCS_FRAME
570 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
571 warning ("-g with -mno-apcs-frame may not give sensible debugging");
573 /* If stack checking is disabled, we can use r10 as the PIC register,
574 which keeps r9 available. */
575 if (flag_pic && !TARGET_APCS_STACK)
576 arm_pic_register = 10;
578 if (TARGET_APCS_FLOAT)
579 warning ("Passing floating point arguments in fp regs not yet supported");
581 /* Initialise boolean versions of the flags, for use in the arm.md file. */
582 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
583 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
584 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
585 arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
587 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
588 arm_is_strong = (tune_flags & FL_STRONG) != 0;
589 thumb_code = (TARGET_ARM == 0);
590 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
591 && !(tune_flags & FL_ARCH4))) != 0;
593 /* Default value for floating point code... if no co-processor
594 bus, then schedule for emulated floating point. Otherwise,
595 assume the user has an FPA.
596 Note: this does not prevent use of floating point instructions,
597 -msoft-float does that. */
598 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
602 if (streq (target_fp_name, "2"))
603 arm_fpu_arch = FP_SOFT2;
604 else if (streq (target_fp_name, "3"))
605 arm_fpu_arch = FP_SOFT3;
607 fatal ("Invalid floating point emulation option: -mfpe-%s",
611 arm_fpu_arch = FP_DEFAULT;
613 if (TARGET_FPE && arm_fpu != FP_HARD)
616 /* For arm2/3 there is no need to do any scheduling if there is only
617 a floating point emulator, or we are doing software floating-point. */
618 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
619 && (tune_flags & FL_MODE32) == 0)
620 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
622 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
624 if (structure_size_string != NULL)
626 int size = strtol (structure_size_string, NULL, 0);
628 if (size == 8 || size == 32)
629 arm_structure_size_boundary = size;
631 warning ("Structure size boundary can only be set to 8 or 32");
634 if (arm_pic_register_string != NULL)
639 warning ("-mpic-register= is useless without -fpic");
641 pic_register = decode_reg_name (arm_pic_register_string);
643 /* Prevent the user from choosing an obviously stupid PIC register. */
644 if (pic_register < 0 || call_used_regs[pic_register]
645 || pic_register == HARD_FRAME_POINTER_REGNUM
646 || pic_register == STACK_POINTER_REGNUM
647 || pic_register >= PC_REGNUM)
648 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
650 arm_pic_register = pic_register;
653 if (TARGET_THUMB && flag_schedule_insns)
655 /* Don't warn since it's on by default in -O2. */
656 flag_schedule_insns = 0;
659 /* If optimizing for space, don't synthesize constants.
660 For processors with load scheduling, it never costs more than 2 cycles
661 to load a constant, and the load scheduler may well reduce that to 1. */
662 if (optimize_size || (tune_flags & FL_LDSCHED))
663 arm_constant_limit = 1;
666 arm_constant_limit = 2;
668 /* If optimizing for size, bump the number of instructions that we
669 are prepared to conditionally execute (even on a StrongARM).
670 Otherwise for the StrongARM, which has early execution of branches,
671 a sequence that is worth skipping is shorter. */
673 max_insns_skipped = 6;
674 else if (arm_is_strong)
675 max_insns_skipped = 3;
677 /* Register global variables with the garbage collector. */
684 ggc_add_rtx_root (&arm_compare_op0, 1);
685 ggc_add_rtx_root (&arm_compare_op1, 1);
686 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root */
688 gcc_obstack_init(&minipool_obstack);
689 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
692 /* Return 1 if it is possible to return using a single instruction. */
694 use_return_insn (iscond)
699 /* Never use a return instruction before reload has run. */
700 if (!reload_completed
701 /* Or if the function is variadic. */
702 || current_function_pretend_args_size
703 || current_function_anonymous_args
704 /* Of if the function calls __builtin_eh_return () */
705 || cfun->machine->eh_epilogue_sp_ofs != NULL
706 /* Or if there is no frame pointer and there is a stack adjustment. */
707 || ((get_frame_size () + current_function_outgoing_args_size != 0)
708 && !frame_pointer_needed))
711 /* Can't be done if interworking with Thumb, and any registers have been
712 stacked. Similarly, on StrongARM, conditional returns are expensive
713 if they aren't taken and registers have been stacked. */
714 if (iscond && arm_is_strong && frame_pointer_needed)
717 if ((iscond && arm_is_strong)
720 for (regno = 0; regno <= LAST_ARM_REGNUM; regno++)
721 if (regs_ever_live[regno] && !call_used_regs[regno])
724 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
728 /* Can't be done if any of the FPU regs are pushed, since this also
730 if (TARGET_HARD_FLOAT)
731 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
732 if (regs_ever_live[regno] && !call_used_regs[regno])
735 /* If a function is naked, don't use the "return" insn. */
736 if (arm_naked_function_p (current_function_decl))
742 /* Return TRUE if int I is a valid immediate ARM constant. */
748 unsigned HOST_WIDE_INT mask = ~HOST_UINT (0xFF);
750 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
751 be all zero, or all one. */
752 if ((i & ~HOST_UINT (0xffffffff)) != 0
753 && ((i & ~HOST_UINT (0xffffffff))
755 & ~HOST_UINT (0xffffffff))))
758 /* Fast return for 0 and powers of 2 */
759 if ((i & (i - 1)) == 0)
764 if ((i & mask & HOST_UINT (0xffffffff)) == 0)
767 (mask << 2) | ((mask & HOST_UINT (0xffffffff))
768 >> (32 - 2)) | ~(HOST_UINT (0xffffffff));
769 } while (mask != ~HOST_UINT (0xFF));
774 /* Return true if I is a valid constant for the operation CODE. */
776 const_ok_for_op (i, code)
780 if (const_ok_for_arm (i))
786 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
788 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
794 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
801 /* Emit a sequence of insns to handle a large constant.
802 CODE is the code of the operation required, it can be any of SET, PLUS,
803 IOR, AND, XOR, MINUS;
804 MODE is the mode in which the operation is being performed;
805 VAL is the integer to operate on;
806 SOURCE is the other operand (a register, or a null-pointer for SET);
807 SUBTARGETS means it is safe to create scratch registers if that will
808 either produce a simpler sequence, or we will want to cse the values.
809 Return value is the number of insns emitted. */
812 arm_split_constant (code, mode, val, target, source, subtargets)
814 enum machine_mode mode;
820 if (subtargets || code == SET
821 || (GET_CODE (target) == REG && GET_CODE (source) == REG
822 && REGNO (target) != REGNO (source)))
824 /* After arm_reorg has been called, we can't fix up expensive
825 constants by pushing them into memory so we must synthesise
826 them in-line, regardless of the cost. This is only likely to
827 be more costly on chips that have load delay slots and we are
828 compiling without running the scheduler (so no splitting
829 occurred before the final instruction emission).
831 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
834 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
835 > arm_constant_limit + (code != SET)))
839 /* Currently SET is the only monadic value for CODE, all
840 the rest are diadic. */
841 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
846 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
848 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
849 /* For MINUS, the value is subtracted from, since we never
850 have subtraction of a constant. */
852 emit_insn (gen_rtx_SET (VOIDmode, target,
853 gen_rtx_MINUS (mode, temp, source)));
855 emit_insn (gen_rtx_SET (VOIDmode, target,
856 gen_rtx (code, mode, source, temp)));
862 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
865 /* As above, but extra parameter GENERATE which, if clear, suppresses
868 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
870 enum machine_mode mode;
879 int can_negate_initial = 0;
882 int num_bits_set = 0;
883 int set_sign_bit_copies = 0;
884 int clear_sign_bit_copies = 0;
885 int clear_zero_bit_copies = 0;
886 int set_zero_bit_copies = 0;
888 unsigned HOST_WIDE_INT temp1, temp2;
889 unsigned HOST_WIDE_INT remainder = val & HOST_UINT (0xffffffff);
891 /* Find out which operations are safe for a given CODE. Also do a quick
892 check for degenerate cases; these can occur when DImode operations
904 can_negate_initial = 1;
908 if (remainder == HOST_UINT (0xffffffff))
911 emit_insn (gen_rtx_SET (VOIDmode, target,
912 GEN_INT (ARM_SIGN_EXTEND (val))));
917 if (reload_completed && rtx_equal_p (target, source))
920 emit_insn (gen_rtx_SET (VOIDmode, target, source));
929 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
932 if (remainder == HOST_UINT (0xffffffff))
934 if (reload_completed && rtx_equal_p (target, source))
937 emit_insn (gen_rtx_SET (VOIDmode, target, source));
946 if (reload_completed && rtx_equal_p (target, source))
949 emit_insn (gen_rtx_SET (VOIDmode, target, source));
952 if (remainder == HOST_UINT (0xffffffff))
955 emit_insn (gen_rtx_SET (VOIDmode, target,
956 gen_rtx_NOT (mode, source)));
960 /* We don't know how to handle this yet below. */
964 /* We treat MINUS as (val - source), since (source - val) is always
965 passed as (source + (-val)). */
969 emit_insn (gen_rtx_SET (VOIDmode, target,
970 gen_rtx_NEG (mode, source)));
973 if (const_ok_for_arm (val))
976 emit_insn (gen_rtx_SET (VOIDmode, target,
977 gen_rtx_MINUS (mode, GEN_INT (val),
989 /* If we can do it in one insn get out quickly. */
990 if (const_ok_for_arm (val)
991 || (can_negate_initial && const_ok_for_arm (-val))
992 || (can_invert && const_ok_for_arm (~val)))
995 emit_insn (gen_rtx_SET (VOIDmode, target,
996 (source ? gen_rtx (code, mode, source,
1002 /* Calculate a few attributes that may be useful for specific
1004 for (i = 31; i >= 0; i--)
1006 if ((remainder & (1 << i)) == 0)
1007 clear_sign_bit_copies++;
1012 for (i = 31; i >= 0; i--)
1014 if ((remainder & (1 << i)) != 0)
1015 set_sign_bit_copies++;
1020 for (i = 0; i <= 31; i++)
1022 if ((remainder & (1 << i)) == 0)
1023 clear_zero_bit_copies++;
1028 for (i = 0; i <= 31; i++)
1030 if ((remainder & (1 << i)) != 0)
1031 set_zero_bit_copies++;
1039 /* See if we can do this by sign_extending a constant that is known
1040 to be negative. This is a good, way of doing it, since the shift
1041 may well merge into a subsequent insn. */
1042 if (set_sign_bit_copies > 1)
1044 if (const_ok_for_arm
1045 (temp1 = ARM_SIGN_EXTEND (remainder
1046 << (set_sign_bit_copies - 1))))
1050 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1051 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1053 emit_insn (gen_ashrsi3 (target, new_src,
1054 GEN_INT (set_sign_bit_copies - 1)));
1058 /* For an inverted constant, we will need to set the low bits,
1059 these will be shifted out of harm's way. */
1060 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1061 if (const_ok_for_arm (~temp1))
1065 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1066 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1068 emit_insn (gen_ashrsi3 (target, new_src,
1069 GEN_INT (set_sign_bit_copies - 1)));
1075 /* See if we can generate this by setting the bottom (or the top)
1076 16 bits, and then shifting these into the other half of the
1077 word. We only look for the simplest cases, to do more would cost
1078 too much. Be careful, however, not to generate this when the
1079 alternative would take fewer insns. */
1080 if (val & HOST_UINT (0xffff0000))
1082 temp1 = remainder & HOST_UINT (0xffff0000);
1083 temp2 = remainder & 0x0000ffff;
1085 /* Overlaps outside this range are best done using other methods. */
1086 for (i = 9; i < 24; i++)
1088 if ((((temp2 | (temp2 << i))
1089 & HOST_UINT (0xffffffff)) == remainder)
1090 && !const_ok_for_arm (temp2))
1092 rtx new_src = (subtargets
1093 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1095 insns = arm_gen_constant (code, mode, temp2, new_src,
1096 source, subtargets, generate);
1099 emit_insn (gen_rtx_SET
1102 gen_rtx_ASHIFT (mode, source,
1109 /* Don't duplicate cases already considered. */
1110 for (i = 17; i < 24; i++)
1112 if (((temp1 | (temp1 >> i)) == remainder)
1113 && !const_ok_for_arm (temp1))
1115 rtx new_src = (subtargets
1116 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1118 insns = arm_gen_constant (code, mode, temp1, new_src,
1119 source, subtargets, generate);
1123 (gen_rtx_SET (VOIDmode, target,
1126 gen_rtx_LSHIFTRT (mode, source,
1137 /* If we have IOR or XOR, and the constant can be loaded in a
1138 single instruction, and we can find a temporary to put it in,
1139 then this can be done in two instructions instead of 3-4. */
1141 /* TARGET can't be NULL if SUBTARGETS is 0 */
1142 || (reload_completed && !reg_mentioned_p (target, source)))
1144 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1148 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1150 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1151 emit_insn (gen_rtx_SET (VOIDmode, target,
1152 gen_rtx (code, mode, source, sub)));
1161 if (set_sign_bit_copies > 8
1162 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1166 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1167 rtx shift = GEN_INT (set_sign_bit_copies);
1169 emit_insn (gen_rtx_SET (VOIDmode, sub,
1171 gen_rtx_ASHIFT (mode,
1174 emit_insn (gen_rtx_SET (VOIDmode, target,
1176 gen_rtx_LSHIFTRT (mode, sub,
1182 if (set_zero_bit_copies > 8
1183 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1187 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1188 rtx shift = GEN_INT (set_zero_bit_copies);
1190 emit_insn (gen_rtx_SET (VOIDmode, sub,
1192 gen_rtx_LSHIFTRT (mode,
1195 emit_insn (gen_rtx_SET (VOIDmode, target,
1197 gen_rtx_ASHIFT (mode, sub,
1203 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1207 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1208 emit_insn (gen_rtx_SET (VOIDmode, sub,
1209 gen_rtx_NOT (mode, source)));
1212 sub = gen_reg_rtx (mode);
1213 emit_insn (gen_rtx_SET (VOIDmode, sub,
1214 gen_rtx_AND (mode, source,
1216 emit_insn (gen_rtx_SET (VOIDmode, target,
1217 gen_rtx_NOT (mode, sub)));
1224 /* See if two shifts will do 2 or more insn's worth of work. */
1225 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1227 HOST_WIDE_INT shift_mask = (((HOST_UINT (0xffffffff))
1228 << (32 - clear_sign_bit_copies))
1229 & HOST_UINT (0xffffffff));
1231 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1235 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1236 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1237 new_src, source, subtargets, 1);
1242 rtx targ = subtargets ? NULL_RTX : target;
1243 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1244 targ, source, subtargets, 0);
1250 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1251 rtx shift = GEN_INT (clear_sign_bit_copies);
1253 emit_insn (gen_ashlsi3 (new_src, source, shift));
1254 emit_insn (gen_lshrsi3 (target, new_src, shift));
1260 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1262 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1264 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1268 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1270 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1271 new_src, source, subtargets, 1);
1276 rtx targ = subtargets ? NULL_RTX : target;
1278 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1279 targ, source, subtargets, 0);
1285 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1286 rtx shift = GEN_INT (clear_zero_bit_copies);
1288 emit_insn (gen_lshrsi3 (new_src, source, shift));
1289 emit_insn (gen_ashlsi3 (target, new_src, shift));
1301 for (i = 0; i < 32; i++)
1302 if (remainder & (1 << i))
1305 if (code == AND || (can_invert && num_bits_set > 16))
1306 remainder = (~remainder) & HOST_UINT (0xffffffff);
1307 else if (code == PLUS && num_bits_set > 16)
1308 remainder = (-remainder) & HOST_UINT (0xffffffff);
1315 /* Now try and find a way of doing the job in either two or three
1317 We start by looking for the largest block of zeros that are aligned on
1318 a 2-bit boundary, we then fill up the temps, wrapping around to the
1319 top of the word when we drop off the bottom.
1320 In the worst case this code should produce no more than four insns. */
1323 int best_consecutive_zeros = 0;
1325 for (i = 0; i < 32; i += 2)
1327 int consecutive_zeros = 0;
1329 if (!(remainder & (3 << i)))
1331 while ((i < 32) && !(remainder & (3 << i)))
1333 consecutive_zeros += 2;
1336 if (consecutive_zeros > best_consecutive_zeros)
1338 best_consecutive_zeros = consecutive_zeros;
1339 best_start = i - consecutive_zeros;
1345 /* Now start emitting the insns, starting with the one with the highest
1346 bit set: we do this so that the smallest number will be emitted last;
1347 this is more likely to be combinable with addressing insns. */
1355 if (remainder & (3 << (i - 2)))
1360 temp1 = remainder & ((0x0ff << end)
1361 | ((i < end) ? (0xff >> (32 - end)) : 0));
1362 remainder &= ~temp1;
1369 emit_insn (gen_rtx_SET (VOIDmode,
1370 new_src = (subtargets
1371 ? gen_reg_rtx (mode)
1374 ? ~temp1 : temp1)));
1375 else if (code == MINUS)
1376 emit_insn (gen_rtx_SET (VOIDmode,
1377 new_src = (subtargets
1378 ? gen_reg_rtx (mode)
1380 gen_rtx (code, mode, GEN_INT (temp1),
1383 emit_insn (gen_rtx_SET (VOIDmode,
1384 new_src = (remainder
1386 ? gen_reg_rtx (mode)
1389 gen_rtx (code, mode, source,
1390 GEN_INT (can_invert ? ~temp1
1402 else if (code == MINUS)
1409 } while (remainder);
1414 /* Canonicalize a comparison so that we are more likely to recognize it.
1415 This can be done for a few constant compares, where we can make the
1416 immediate value easier to load. */
1418 arm_canonicalize_comparison (code, op1)
1422 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1432 if (i != (((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1433 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1435 *op1 = GEN_INT (i + 1);
1436 return code == GT ? GE : LT;
1442 if (i != ((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1))
1443 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1445 *op1 = GEN_INT (i - 1);
1446 return code == GE ? GT : LE;
1452 if (i != ~(HOST_UINT (0))
1453 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1455 *op1 = GEN_INT (i + 1);
1456 return code == GTU ? GEU : LTU;
1463 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1465 *op1 = GEN_INT (i - 1);
1466 return code == GEU ? GTU : LEU;
1477 /* Decide whether a type should be returned in memory (true)
1478 or in a register (false). This is called by the macro
1479 RETURN_IN_MEMORY. */
1481 arm_return_in_memory (type)
1484 if (!AGGREGATE_TYPE_P (type))
1485 /* All simple types are returned in registers. */
1488 /* For the arm-wince targets we choose to be compitable with Microsoft's
1489 ARM and Thumb compilers, which always return aggregates in memory. */
1492 if (int_size_in_bytes (type) > 4)
1493 /* All structures/unions bigger than one word are returned in memory. */
1496 if (TREE_CODE (type) == RECORD_TYPE)
1500 /* For a struct the APCS says that we only return in a register
1501 if the type is 'integer like' and every addressable element
1502 has an offset of zero. For practical purposes this means
1503 that the structure can have at most one non bit-field element
1504 and that this element must be the first one in the structure. */
1506 /* Find the first field, ignoring non FIELD_DECL things which will
1507 have been created by C++. */
1508 for (field = TYPE_FIELDS (type);
1509 field && TREE_CODE (field) != FIELD_DECL;
1510 field = TREE_CHAIN (field))
1514 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1516 /* Check that the first field is valid for returning in a register. */
1518 /* ... Floats are not allowed */
1519 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1522 /* ... Aggregates that are not themselves valid for returning in
1523 a register are not allowed. */
1524 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1527 /* Now check the remaining fields, if any. Only bitfields are allowed,
1528 since they are not addressable. */
1529 for (field = TREE_CHAIN (field);
1531 field = TREE_CHAIN (field))
1533 if (TREE_CODE (field) != FIELD_DECL)
1536 if (!DECL_BIT_FIELD_TYPE (field))
1543 if (TREE_CODE (type) == UNION_TYPE)
1547 /* Unions can be returned in registers if every element is
1548 integral, or can be returned in an integer register. */
1549 for (field = TYPE_FIELDS (type);
1551 field = TREE_CHAIN (field))
1553 if (TREE_CODE (field) != FIELD_DECL)
1556 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1559 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1565 #endif /* not ARM_WINCE */
1567 /* Return all other types in memory. */
1571 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1572 for a call to a function whose data type is FNTYPE.
1573 For a library call, FNTYPE is NULL. */
1575 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1576 CUMULATIVE_ARGS * pcum;
1578 rtx libname ATTRIBUTE_UNUSED;
1579 int indirect ATTRIBUTE_UNUSED;
1581 /* On the ARM, the offset starts at 0. */
1582 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1584 pcum->call_cookie = CALL_NORMAL;
1586 if (TARGET_LONG_CALLS)
1587 pcum->call_cookie = CALL_LONG;
1589 /* Check for long call/short call attributes. The attributes
1590 override any command line option. */
1593 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1594 pcum->call_cookie = CALL_SHORT;
1595 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1596 pcum->call_cookie = CALL_LONG;
1600 /* Determine where to put an argument to a function.
1601 Value is zero to push the argument on the stack,
1602 or a hard register in which to store the argument.
1604 MODE is the argument's machine mode.
1605 TYPE is the data type of the argument (as a tree).
1606 This is null for libcalls where that information may
1608 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1609 the preceding args and about the function being called.
1610 NAMED is nonzero if this argument is a named parameter
1611 (otherwise it is an extra parameter matching an ellipsis). */
1613 arm_function_arg (pcum, mode, type, named)
1614 CUMULATIVE_ARGS * pcum;
1615 enum machine_mode mode;
1616 tree type ATTRIBUTE_UNUSED;
1619 if (mode == VOIDmode)
1620 /* Compute operand 2 of the call insn. */
1621 return GEN_INT (pcum->call_cookie);
1623 if (!named || pcum->nregs >= NUM_ARG_REGS)
1626 return gen_rtx_REG (mode, pcum->nregs);
1629 /* Encode the current state of the #pragma [no_]long_calls. */
1632 OFF, /* No #pramgma [no_]long_calls is in effect. */
1633 LONG, /* #pragma long_calls is in effect. */
1634 SHORT /* #pragma no_long_calls is in effect. */
1637 static arm_pragma_enum arm_pragma_long_calls = OFF;
1640 arm_pr_long_calls (pfile)
1641 cpp_reader *pfile ATTRIBUTE_UNUSED;
1643 arm_pragma_long_calls = LONG;
1647 arm_pr_no_long_calls (pfile)
1648 cpp_reader *pfile ATTRIBUTE_UNUSED;
1650 arm_pragma_long_calls = SHORT;
1654 arm_pr_long_calls_off (pfile)
1655 cpp_reader *pfile ATTRIBUTE_UNUSED;
1657 arm_pragma_long_calls = OFF;
1661 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1662 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1663 assigned to TYPE. */
1665 arm_valid_type_attribute_p (type, attributes, identifier, args)
1667 tree attributes ATTRIBUTE_UNUSED;
1671 if ( TREE_CODE (type) != FUNCTION_TYPE
1672 && TREE_CODE (type) != METHOD_TYPE
1673 && TREE_CODE (type) != FIELD_DECL
1674 && TREE_CODE (type) != TYPE_DECL)
1677 /* Function calls made to this symbol must be done indirectly, because
1678 it may lie outside of the 26 bit addressing range of a normal function
1680 if (is_attribute_p ("long_call", identifier))
1681 return (args == NULL_TREE);
1683 /* Whereas these functions are always known to reside within the 26 bit
1684 addressing range. */
1685 if (is_attribute_p ("short_call", identifier))
1686 return (args == NULL_TREE);
1691 /* Return 0 if the attributes for two types are incompatible, 1 if they
1692 are compatible, and 2 if they are nearly compatible (which causes a
1693 warning to be generated). */
1695 arm_comp_type_attributes (type1, type2)
1701 /* Check for mismatch of non-default calling convention. */
1702 if (TREE_CODE (type1) != FUNCTION_TYPE)
1705 /* Check for mismatched call attributes. */
1706 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
1707 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
1708 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
1709 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
1711 /* Only bother to check if an attribute is defined. */
1712 if (l1 | l2 | s1 | s2)
1714 /* If one type has an attribute, the other must have the same attribute. */
1715 if ((l1 != l2) || (s1 != s2))
1718 /* Disallow mixed attributes. */
1719 if ((l1 & s2) || (l2 & s1))
1726 /* Encode long_call or short_call attribute by prefixing
1727 symbol name in DECL with a special character FLAG. */
1729 arm_encode_call_attribute (decl, flag)
1733 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
1734 int len = strlen (str);
1737 if (TREE_CODE (decl) != FUNCTION_DECL)
1740 /* Do not allow weak functions to be treated as short call. */
1741 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
1744 newstr = alloca (len + 2);
1746 strcpy (newstr + 1, str);
1748 newstr = ggc_alloc_string (newstr, len + 1);
1749 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
1752 /* Assigns default attributes to newly defined type. This is used to
1753 set short_call/long_call attributes for function types of
1754 functions defined inside corresponding #pragma scopes. */
1756 arm_set_default_type_attributes (type)
1759 /* Add __attribute__ ((long_call)) to all functions, when
1760 inside #pragma long_calls or __attribute__ ((short_call)),
1761 when inside #pragma no_long_calls. */
1762 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
1764 tree type_attr_list, attr_name;
1765 type_attr_list = TYPE_ATTRIBUTES (type);
1767 if (arm_pragma_long_calls == LONG)
1768 attr_name = get_identifier ("long_call");
1769 else if (arm_pragma_long_calls == SHORT)
1770 attr_name = get_identifier ("short_call");
1774 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
1775 TYPE_ATTRIBUTES (type) = type_attr_list;
1779 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1780 defined within the current compilation unit. If this caanot be
1781 determined, then 0 is returned. */
1783 current_file_function_operand (sym_ref)
1786 /* This is a bit of a fib. A function will have a short call flag
1787 applied to its name if it has the short call attribute, or it has
1788 already been defined within the current compilation unit. */
1789 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
1792 /* The current function is always defined within the current compilation
1793 unit. if it s a weak defintion however, then this may not be the real
1794 defintion of the function, and so we have to say no. */
1795 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
1796 && !DECL_WEAK (current_function_decl))
1799 /* We cannot make the determination - default to returning 0. */
1803 /* Return non-zero if a 32 bit "long_call" should be generated for
1804 this call. We generate a long_call if the function:
1806 a. has an __attribute__((long call))
1807 or b. is within the scope of a #pragma long_calls
1808 or c. the -mlong-calls command line switch has been specified
1810 However we do not generate a long call if the function:
1812 d. has an __attribute__ ((short_call))
1813 or e. is inside the scope of a #pragma no_long_calls
1814 or f. has an __attribute__ ((section))
1815 or g. is defined within the current compilation unit.
1817 This function will be called by C fragments contained in the machine
1818 description file. CALL_REF and CALL_COOKIE correspond to the matched
1819 rtl operands. CALL_SYMBOL is used to distinguish between
1820 two different callers of the function. It is set to 1 in the
1821 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
1822 and "call_value" patterns. This is because of the difference in the
1823 SYM_REFs passed by these patterns. */
1825 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
1832 if (GET_CODE (sym_ref) != MEM)
1835 sym_ref = XEXP (sym_ref, 0);
1838 if (GET_CODE (sym_ref) != SYMBOL_REF)
1841 if (call_cookie & CALL_SHORT)
1844 if (TARGET_LONG_CALLS && flag_function_sections)
1847 if (current_file_function_operand (sym_ref))
1850 return (call_cookie & CALL_LONG)
1851 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
1852 || TARGET_LONG_CALLS;
1855 /* Return non-zero if it is ok to make a tail-call to DECL. */
1857 arm_function_ok_for_sibcall (decl)
1860 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
1862 /* Never tailcall something for which we have no decl, or if we
1863 are in Thumb mode. */
1864 if (decl == NULL || TARGET_THUMB)
1867 /* Get the calling method. */
1868 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
1869 call_type = CALL_SHORT;
1870 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
1871 call_type = CALL_LONG;
1873 /* Cannot tail-call to long calls, since these are out of range of
1874 a branch instruction. However, if not compiling PIC, we know
1875 we can reach the symbol if it is in this compilation unit. */
1876 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
1879 /* If we are interworking and the function is not declared static
1880 then we can't tail-call it unless we know that it exists in this
1881 compilation unit (since it might be a Thumb routine). */
1882 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
1885 /* Everything else is ok. */
1891 legitimate_pic_operand_p (x)
1896 && (GET_CODE (x) == SYMBOL_REF
1897 || (GET_CODE (x) == CONST
1898 && GET_CODE (XEXP (x, 0)) == PLUS
1899 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1906 legitimize_pic_address (orig, mode, reg)
1908 enum machine_mode mode;
1911 if (GET_CODE (orig) == SYMBOL_REF)
1913 rtx pic_ref, address;
1922 reg = gen_reg_rtx (Pmode);
1927 #ifdef AOF_ASSEMBLER
1928 /* The AOF assembler can generate relocations for these directly, and
1929 understands that the PIC register has to be added into the offset. */
1930 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1933 address = gen_reg_rtx (Pmode);
1938 emit_insn (gen_pic_load_addr_arm (address, orig));
1940 emit_insn (gen_pic_load_addr_thumb (address, orig));
1942 pic_ref = gen_rtx_MEM (Pmode,
1943 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1945 RTX_UNCHANGING_P (pic_ref) = 1;
1946 insn = emit_move_insn (reg, pic_ref);
1948 current_function_uses_pic_offset_table = 1;
1949 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1951 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1955 else if (GET_CODE (orig) == CONST)
1959 if (GET_CODE (XEXP (orig, 0)) == PLUS
1960 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1968 reg = gen_reg_rtx (Pmode);
1971 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1973 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1974 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1975 base == reg ? 0 : reg);
1980 if (GET_CODE (offset) == CONST_INT)
1982 /* The base register doesn't really matter, we only want to
1983 test the index for the appropriate mode. */
1984 ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1986 if (!no_new_pseudos)
1987 offset = force_reg (Pmode, offset);
1992 if (GET_CODE (offset) == CONST_INT)
1993 return plus_constant_for_output (base, INTVAL (offset));
1996 if (GET_MODE_SIZE (mode) > 4
1997 && (GET_MODE_CLASS (mode) == MODE_INT
1998 || TARGET_SOFT_FLOAT))
2000 emit_insn (gen_addsi3 (reg, base, offset));
2004 return gen_rtx_PLUS (Pmode, base, offset);
2006 else if (GET_CODE (orig) == LABEL_REF)
2008 current_function_uses_pic_offset_table = 1;
2012 rtx pic_ref, address = gen_reg_rtx (Pmode);
2015 emit_insn (gen_pic_load_addr_arm (address, orig));
2017 emit_insn (gen_pic_load_addr_thumb (address, orig));
2019 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2021 emit_move_insn (address, pic_ref);
2043 #ifndef AOF_ASSEMBLER
2044 rtx l1, pic_tmp, pic_tmp2, seq;
2045 rtx global_offset_table;
2047 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2054 l1 = gen_label_rtx ();
2056 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2057 /* On the ARM the PC register contains 'dot + 8' at the time of the
2058 addition, on the Thumb it is 'dot + 4'. */
2059 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2061 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2062 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2064 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2066 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2070 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2071 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2075 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2076 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2079 seq = gen_sequence ();
2081 emit_insn_after (seq, get_insns ());
2083 /* Need to emit this whether or not we obey regdecls,
2084 since setjmp/longjmp can cause life info to screw up. */
2085 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2086 #endif /* AOF_ASSEMBLER */
2089 #define REG_OR_SUBREG_REG(X) \
2090 (GET_CODE (X) == REG \
2091 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2093 #define REG_OR_SUBREG_RTX(X) \
2094 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2096 #ifndef COSTS_N_INSNS
2097 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2101 arm_rtx_costs (x, code, outer)
2104 enum rtx_code outer;
2106 enum machine_mode mode = GET_MODE (x);
2107 enum rtx_code subcode;
2123 return COSTS_N_INSNS (1);
2126 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2129 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
2136 return COSTS_N_INSNS (2) + cycles;
2138 return COSTS_N_INSNS (1) + 16;
2141 return (COSTS_N_INSNS (1)
2142 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
2143 + GET_CODE (SET_DEST (x)) == MEM));
2148 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2150 if (thumb_shiftable_const (INTVAL (x)))
2151 return COSTS_N_INSNS (2);
2152 return COSTS_N_INSNS (3);
2154 else if (outer == PLUS
2155 && INTVAL (x) < 256 && INTVAL (x) > -256)
2157 else if (outer == COMPARE
2158 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2160 else if (outer == ASHIFT || outer == ASHIFTRT
2161 || outer == LSHIFTRT)
2163 return COSTS_N_INSNS (2);
2169 return COSTS_N_INSNS (3);
2188 /* XXX another guess. */
2189 /* Memory costs quite a lot for the first word, but subsequent words
2190 load at the equivalent of a single insn each. */
2191 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2192 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2196 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2201 /* XXX still guessing. */
2202 switch (GET_MODE (XEXP (x, 0)))
2205 return (1 + (mode == DImode ? 4 : 0)
2206 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2209 return (4 + (mode == DImode ? 4 : 0)
2210 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2213 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2227 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n",
2237 /* Memory costs quite a lot for the first word, but subsequent words
2238 load at the equivalent of a single insn each. */
2239 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2240 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2247 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
2254 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2256 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2257 + ((GET_CODE (XEXP (x, 0)) == REG
2258 || (GET_CODE (XEXP (x, 0)) == SUBREG
2259 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2261 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2262 || (GET_CODE (XEXP (x, 0)) == SUBREG
2263 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2265 + ((GET_CODE (XEXP (x, 1)) == REG
2266 || (GET_CODE (XEXP (x, 1)) == SUBREG
2267 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2268 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2273 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2274 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2275 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2276 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2279 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2280 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2281 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2282 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2284 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2285 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2286 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2289 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2290 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2291 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2292 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2293 || subcode == ASHIFTRT || subcode == LSHIFTRT
2294 || subcode == ROTATE || subcode == ROTATERT
2296 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2297 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2298 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2299 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2300 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2301 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2302 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2307 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2308 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2309 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2310 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2311 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2315 case AND: case XOR: case IOR:
2318 /* Normally the frame registers will be spilt into reg+const during
2319 reload, so it is a bad idea to combine them with other instructions,
2320 since then they might not be moved outside of loops. As a compromise
2321 we allow integration with ops that have a constant as their second
2323 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2324 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2325 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2326 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2327 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2331 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2332 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2333 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2334 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2337 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2338 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2339 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2340 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2341 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2344 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2345 return (1 + extra_cost
2346 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2347 || subcode == LSHIFTRT || subcode == ASHIFTRT
2348 || subcode == ROTATE || subcode == ROTATERT
2350 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2351 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2352 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2353 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2354 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2355 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2361 /* There is no point basing this on the tuning, since it is always the
2362 fast variant if it exists at all. */
2363 if (arm_fast_multiply && mode == DImode
2364 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2365 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2366 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2369 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2373 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2375 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2376 & HOST_UINT (0xffffffff));
2377 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2380 /* Tune as appropriate. */
2381 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2383 for (j = 0; i && j < 32; j += booth_unit_size)
2385 i >>= booth_unit_size;
2392 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2393 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2394 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2397 if (arm_fast_multiply && mode == SImode
2398 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2399 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2400 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2401 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2402 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2403 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2408 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2409 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2413 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2415 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2418 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2426 return 4 + (mode == DImode ? 4 : 0);
2429 if (GET_MODE (XEXP (x, 0)) == QImode)
2430 return (4 + (mode == DImode ? 4 : 0)
2431 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2434 switch (GET_MODE (XEXP (x, 0)))
2437 return (1 + (mode == DImode ? 4 : 0)
2438 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2441 return (4 + (mode == DImode ? 4 : 0)
2442 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2445 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2453 if (const_ok_for_arm (INTVAL (x)))
2454 return outer == SET ? 2 : -1;
2455 else if (outer == AND
2456 && const_ok_for_arm (~INTVAL (x)))
2458 else if ((outer == COMPARE
2459 || outer == PLUS || outer == MINUS)
2460 && const_ok_for_arm (-INTVAL (x)))
2471 if (const_double_rtx_ok_for_fpu (x))
2472 return outer == SET ? 2 : -1;
2473 else if ((outer == COMPARE || outer == PLUS)
2474 && neg_const_double_rtx_ok_for_fpu (x))
2484 arm_adjust_cost (insn, link, dep, cost)
2492 /* Some true dependencies can have a higher cost depending
2493 on precisely how certain input operands are used. */
2495 && REG_NOTE_KIND (link) == 0
2496 && recog_memoized (insn) < 0
2497 && recog_memoized (dep) < 0)
2499 int shift_opnum = get_attr_shift (insn);
2500 enum attr_type attr_type = get_attr_type (dep);
2502 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2503 operand for INSN. If we have a shifted input operand and the
2504 instruction we depend on is another ALU instruction, then we may
2505 have to account for an additional stall. */
2506 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
2508 rtx shifted_operand;
2511 /* Get the shifted operand. */
2512 extract_insn (insn);
2513 shifted_operand = recog_data.operand[shift_opnum];
2515 /* Iterate over all the operands in DEP. If we write an operand
2516 that overlaps with SHIFTED_OPERAND, then we have increase the
2517 cost of this dependency. */
2519 preprocess_constraints ();
2520 for (opno = 0; opno < recog_data.n_operands; opno++)
2522 /* We can ignore strict inputs. */
2523 if (recog_data.operand_type[opno] == OP_IN)
2526 if (reg_overlap_mentioned_p (recog_data.operand[opno],
2533 /* XXX This is not strictly true for the FPA. */
2534 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
2535 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
2538 /* Call insns don't incur a stall, even if they follow a load. */
2539 if (REG_NOTE_KIND (link) == 0
2540 && GET_CODE (insn) == CALL_INSN)
2543 if ((i_pat = single_set (insn)) != NULL
2544 && GET_CODE (SET_SRC (i_pat)) == MEM
2545 && (d_pat = single_set (dep)) != NULL
2546 && GET_CODE (SET_DEST (d_pat)) == MEM)
2548 /* This is a load after a store, there is no conflict if the load reads
2549 from a cached area. Assume that loads from the stack, and from the
2550 constant pool are cached, and that others will miss. This is a
2553 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2554 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2555 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2556 || reg_mentioned_p (hard_frame_pointer_rtx,
2557 XEXP (SET_SRC (i_pat), 0)))
2564 /* This code has been fixed for cross compilation. */
2566 static int fpa_consts_inited = 0;
2568 static const char * strings_fpa[8] =
2571 "4", "5", "0.5", "10"
2574 static REAL_VALUE_TYPE values_fpa[8];
2582 for (i = 0; i < 8; i++)
2584 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2588 fpa_consts_inited = 1;
2591 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2594 const_double_rtx_ok_for_fpu (x)
2600 if (!fpa_consts_inited)
2603 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2604 if (REAL_VALUE_MINUS_ZERO (r))
2607 for (i = 0; i < 8; i++)
2608 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2614 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2617 neg_const_double_rtx_ok_for_fpu (x)
2623 if (!fpa_consts_inited)
2626 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2627 r = REAL_VALUE_NEGATE (r);
2628 if (REAL_VALUE_MINUS_ZERO (r))
2631 for (i = 0; i < 8; i++)
2632 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2638 /* Predicates for `match_operand' and `match_operator'. */
2640 /* s_register_operand is the same as register_operand, but it doesn't accept
2643 This function exists because at the time it was put in it led to better
2644 code. SUBREG(MEM) always needs a reload in the places where
2645 s_register_operand is used, and this seemed to lead to excessive
2649 s_register_operand (op, mode)
2651 enum machine_mode mode;
2653 if (GET_MODE (op) != mode && mode != VOIDmode)
2656 if (GET_CODE (op) == SUBREG)
2657 op = SUBREG_REG (op);
2659 /* We don't consider registers whose class is NO_REGS
2660 to be a register operand. */
2661 /* XXX might have to check for lo regs only for thumb ??? */
2662 return (GET_CODE (op) == REG
2663 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2664 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2667 /* Only accept reg, subreg(reg), const_int. */
2670 reg_or_int_operand (op, mode)
2672 enum machine_mode mode;
2674 if (GET_CODE (op) == CONST_INT)
2677 if (GET_MODE (op) != mode && mode != VOIDmode)
2680 if (GET_CODE (op) == SUBREG)
2681 op = SUBREG_REG (op);
2683 /* We don't consider registers whose class is NO_REGS
2684 to be a register operand. */
2685 return (GET_CODE (op) == REG
2686 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2687 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2690 /* Return 1 if OP is an item in memory, given that we are in reload. */
2693 arm_reload_memory_operand (op, mode)
2695 enum machine_mode mode ATTRIBUTE_UNUSED;
2697 int regno = true_regnum (op);
2699 return (!CONSTANT_P (op)
2701 || (GET_CODE (op) == REG
2702 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2705 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2706 memory access (architecture V4).
2707 MODE is QImode if called when computing contraints, or VOIDmode when
2708 emitting patterns. In this latter case we cannot use memory_operand()
2709 because it will fail on badly formed MEMs, which is precisly what we are
2712 bad_signed_byte_operand (op, mode)
2714 enum machine_mode mode ATTRIBUTE_UNUSED;
2717 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM)
2720 if (GET_CODE (op) != MEM)
2725 /* A sum of anything more complex than reg + reg or reg + const is bad. */
2726 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2727 && (!s_register_operand (XEXP (op, 0), VOIDmode)
2728 || (!s_register_operand (XEXP (op, 1), VOIDmode)
2729 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2732 /* Big constants are also bad. */
2733 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2734 && (INTVAL (XEXP (op, 1)) > 0xff
2735 || -INTVAL (XEXP (op, 1)) > 0xff))
2738 /* Everything else is good, or can will automatically be made so. */
2742 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2745 arm_rhs_operand (op, mode)
2747 enum machine_mode mode;
2749 return (s_register_operand (op, mode)
2750 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2753 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2757 arm_rhsm_operand (op, mode)
2759 enum machine_mode mode;
2761 return (s_register_operand (op, mode)
2762 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2763 || memory_operand (op, mode));
2766 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2767 constant that is valid when negated. */
2770 arm_add_operand (op, mode)
2772 enum machine_mode mode;
2775 return thumb_cmp_operand (op, mode);
2777 return (s_register_operand (op, mode)
2778 || (GET_CODE (op) == CONST_INT
2779 && (const_ok_for_arm (INTVAL (op))
2780 || const_ok_for_arm (-INTVAL (op)))));
2784 arm_not_operand (op, mode)
2786 enum machine_mode mode;
2788 return (s_register_operand (op, mode)
2789 || (GET_CODE (op) == CONST_INT
2790 && (const_ok_for_arm (INTVAL (op))
2791 || const_ok_for_arm (~INTVAL (op)))));
2794 /* Return TRUE if the operand is a memory reference which contains an
2795 offsettable address. */
2797 offsettable_memory_operand (op, mode)
2799 enum machine_mode mode;
2801 if (mode == VOIDmode)
2802 mode = GET_MODE (op);
2804 return (mode == GET_MODE (op)
2805 && GET_CODE (op) == MEM
2806 && offsettable_address_p (reload_completed | reload_in_progress,
2807 mode, XEXP (op, 0)));
2810 /* Return TRUE if the operand is a memory reference which is, or can be
2811 made word aligned by adjusting the offset. */
2813 alignable_memory_operand (op, mode)
2815 enum machine_mode mode;
2819 if (mode == VOIDmode)
2820 mode = GET_MODE (op);
2822 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2827 return ((GET_CODE (reg = op) == REG
2828 || (GET_CODE (op) == SUBREG
2829 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2830 || (GET_CODE (op) == PLUS
2831 && GET_CODE (XEXP (op, 1)) == CONST_INT
2832 && (GET_CODE (reg = XEXP (op, 0)) == REG
2833 || (GET_CODE (XEXP (op, 0)) == SUBREG
2834 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2835 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
2838 /* Similar to s_register_operand, but does not allow hard integer
2841 f_register_operand (op, mode)
2843 enum machine_mode mode;
2845 if (GET_MODE (op) != mode && mode != VOIDmode)
2848 if (GET_CODE (op) == SUBREG)
2849 op = SUBREG_REG (op);
2851 /* We don't consider registers whose class is NO_REGS
2852 to be a register operand. */
2853 return (GET_CODE (op) == REG
2854 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2855 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2858 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2861 fpu_rhs_operand (op, mode)
2863 enum machine_mode mode;
2865 if (s_register_operand (op, mode))
2868 if (GET_MODE (op) != mode && mode != VOIDmode)
2871 if (GET_CODE (op) == CONST_DOUBLE)
2872 return const_double_rtx_ok_for_fpu (op);
2878 fpu_add_operand (op, mode)
2880 enum machine_mode mode;
2882 if (s_register_operand (op, mode))
2885 if (GET_MODE (op) != mode && mode != VOIDmode)
2888 if (GET_CODE (op) == CONST_DOUBLE)
2889 return (const_double_rtx_ok_for_fpu (op)
2890 || neg_const_double_rtx_ok_for_fpu (op));
2895 /* Return nonzero if OP is a constant power of two. */
2898 power_of_two_operand (op, mode)
2900 enum machine_mode mode ATTRIBUTE_UNUSED;
2902 if (GET_CODE (op) == CONST_INT)
2904 HOST_WIDE_INT value = INTVAL (op);
2905 return value != 0 && (value & (value - 1)) == 0;
2910 /* Return TRUE for a valid operand of a DImode operation.
2911 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2912 Note that this disallows MEM(REG+REG), but allows
2913 MEM(PRE/POST_INC/DEC(REG)). */
2916 di_operand (op, mode)
2918 enum machine_mode mode;
2920 if (s_register_operand (op, mode))
2923 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
2926 if (GET_CODE (op) == SUBREG)
2927 op = SUBREG_REG (op);
2929 switch (GET_CODE (op))
2936 return memory_address_p (DImode, XEXP (op, 0));
2943 /* Like di_operand, but don't accept constants. */
2945 nonimmediate_di_operand (op, mode)
2947 enum machine_mode mode;
2949 if (s_register_operand (op, mode))
2952 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
2955 if (GET_CODE (op) == SUBREG)
2956 op = SUBREG_REG (op);
2958 if (GET_CODE (op) == MEM)
2959 return memory_address_p (DImode, XEXP (op, 0));
2964 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2965 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2966 Note that this disallows MEM(REG+REG), but allows
2967 MEM(PRE/POST_INC/DEC(REG)). */
2970 soft_df_operand (op, mode)
2972 enum machine_mode mode;
2974 if (s_register_operand (op, mode))
2977 if (mode != VOIDmode && GET_MODE (op) != mode)
2980 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
2983 if (GET_CODE (op) == SUBREG)
2984 op = SUBREG_REG (op);
2986 switch (GET_CODE (op))
2992 return memory_address_p (DFmode, XEXP (op, 0));
2999 /* Like soft_df_operand, but don't accept constants. */
3001 nonimmediate_soft_df_operand (op, mode)
3003 enum machine_mode mode;
3005 if (s_register_operand (op, mode))
3008 if (mode != VOIDmode && GET_MODE (op) != mode)
3011 if (GET_CODE (op) == SUBREG)
3012 op = SUBREG_REG (op);
3014 if (GET_CODE (op) == MEM)
3015 return memory_address_p (DFmode, XEXP (op, 0));
3019 /* Return TRUE for valid index operands. */
3021 index_operand (op, mode)
3023 enum machine_mode mode;
3025 return (s_register_operand (op, mode)
3026 || (immediate_operand (op, mode)
3027 && (GET_CODE (op) != CONST_INT
3028 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
3031 /* Return TRUE for valid shifts by a constant. This also accepts any
3032 power of two on the (somewhat overly relaxed) assumption that the
3033 shift operator in this case was a mult. */
3036 const_shift_operand (op, mode)
3038 enum machine_mode mode;
3040 return (power_of_two_operand (op, mode)
3041 || (immediate_operand (op, mode)
3042 && (GET_CODE (op) != CONST_INT
3043 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
3046 /* Return TRUE for arithmetic operators which can be combined with a multiply
3050 shiftable_operator (x, mode)
3052 enum machine_mode mode;
3054 if (GET_MODE (x) != mode)
3058 enum rtx_code code = GET_CODE (x);
3060 return (code == PLUS || code == MINUS
3061 || code == IOR || code == XOR || code == AND);
3065 /* Return TRUE for binary logical operators. */
3068 logical_binary_operator (x, mode)
3070 enum machine_mode mode;
3072 if (GET_MODE (x) != mode)
3076 enum rtx_code code = GET_CODE (x);
3078 return (code == IOR || code == XOR || code == AND);
3082 /* Return TRUE for shift operators. */
3085 shift_operator (x, mode)
3087 enum machine_mode mode;
3089 if (GET_MODE (x) != mode)
3093 enum rtx_code code = GET_CODE (x);
3096 return power_of_two_operand (XEXP (x, 1), mode);
3098 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
3099 || code == ROTATERT);
3103 /* Return TRUE if x is EQ or NE. */
3105 equality_operator (x, mode)
3107 enum machine_mode mode ATTRIBUTE_UNUSED;
3109 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
3112 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3114 arm_comparison_operator (x, mode)
3116 enum machine_mode mode;
3118 return (comparison_operator (x, mode)
3119 && GET_CODE (x) != LTGT
3120 && GET_CODE (x) != UNEQ);
3123 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3125 minmax_operator (x, mode)
3127 enum machine_mode mode;
3129 enum rtx_code code = GET_CODE (x);
3131 if (GET_MODE (x) != mode)
3134 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
3137 /* Return TRUE if this is the condition code register, if we aren't given
3138 a mode, accept any class CCmode register. */
3140 cc_register (x, mode)
3142 enum machine_mode mode;
3144 if (mode == VOIDmode)
3146 mode = GET_MODE (x);
3148 if (GET_MODE_CLASS (mode) != MODE_CC)
3152 if ( GET_MODE (x) == mode
3153 && GET_CODE (x) == REG
3154 && REGNO (x) == CC_REGNUM)
3160 /* Return TRUE if this is the condition code register, if we aren't given
3161 a mode, accept any class CCmode register which indicates a dominance
3164 dominant_cc_register (x, mode)
3166 enum machine_mode mode;
3168 if (mode == VOIDmode)
3170 mode = GET_MODE (x);
3172 if (GET_MODE_CLASS (mode) != MODE_CC)
3176 if ( mode != CC_DNEmode && mode != CC_DEQmode
3177 && mode != CC_DLEmode && mode != CC_DLTmode
3178 && mode != CC_DGEmode && mode != CC_DGTmode
3179 && mode != CC_DLEUmode && mode != CC_DLTUmode
3180 && mode != CC_DGEUmode && mode != CC_DGTUmode)
3183 return cc_register (x, mode);
3186 /* Return TRUE if X references a SYMBOL_REF. */
3188 symbol_mentioned_p (x)
3191 register const char * fmt;
3194 if (GET_CODE (x) == SYMBOL_REF)
3197 fmt = GET_RTX_FORMAT (GET_CODE (x));
3199 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3205 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3206 if (symbol_mentioned_p (XVECEXP (x, i, j)))
3209 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
3216 /* Return TRUE if X references a LABEL_REF. */
3218 label_mentioned_p (x)
3221 register const char * fmt;
3224 if (GET_CODE (x) == LABEL_REF)
3227 fmt = GET_RTX_FORMAT (GET_CODE (x));
3228 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3234 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3235 if (label_mentioned_p (XVECEXP (x, i, j)))
3238 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
3249 enum rtx_code code = GET_CODE (x);
3253 else if (code == SMIN)
3255 else if (code == UMIN)
3257 else if (code == UMAX)
3263 /* Return 1 if memory locations are adjacent. */
3265 adjacent_mem_locations (a, b)
3268 int val0 = 0, val1 = 0;
3271 if ((GET_CODE (XEXP (a, 0)) == REG
3272 || (GET_CODE (XEXP (a, 0)) == PLUS
3273 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
3274 && (GET_CODE (XEXP (b, 0)) == REG
3275 || (GET_CODE (XEXP (b, 0)) == PLUS
3276 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
3278 if (GET_CODE (XEXP (a, 0)) == PLUS)
3280 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
3281 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
3284 reg0 = REGNO (XEXP (a, 0));
3285 if (GET_CODE (XEXP (b, 0)) == PLUS)
3287 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
3288 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
3291 reg1 = REGNO (XEXP (b, 0));
3292 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
3297 /* Return 1 if OP is a load multiple operation. It is known to be
3298 parallel and the first section will be tested. */
3300 load_multiple_operation (op, mode)
3302 enum machine_mode mode ATTRIBUTE_UNUSED;
3304 HOST_WIDE_INT count = XVECLEN (op, 0);
3307 HOST_WIDE_INT i = 1, base = 0;
3311 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3314 /* Check to see if this might be a write-back. */
3315 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3320 /* Now check it more carefully. */
3321 if (GET_CODE (SET_DEST (elt)) != REG
3322 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3323 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3324 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3325 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3329 /* Perform a quick check so we don't blow up below. */
3331 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3332 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
3333 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
3336 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
3337 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
3339 for (; i < count; i++)
3341 elt = XVECEXP (op, 0, i);
3343 if (GET_CODE (elt) != SET
3344 || GET_CODE (SET_DEST (elt)) != REG
3345 || GET_MODE (SET_DEST (elt)) != SImode
3346 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
3347 || GET_CODE (SET_SRC (elt)) != MEM
3348 || GET_MODE (SET_SRC (elt)) != SImode
3349 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3350 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3351 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3352 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
3359 /* Return 1 if OP is a store multiple operation. It is known to be
3360 parallel and the first section will be tested. */
3362 store_multiple_operation (op, mode)
3364 enum machine_mode mode ATTRIBUTE_UNUSED;
3366 HOST_WIDE_INT count = XVECLEN (op, 0);
3369 HOST_WIDE_INT i = 1, base = 0;
3373 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3376 /* Check to see if this might be a write-back. */
3377 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3382 /* Now check it more carefully. */
3383 if (GET_CODE (SET_DEST (elt)) != REG
3384 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3385 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3386 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3387 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3391 /* Perform a quick check so we don't blow up below. */
3393 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3394 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3395 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3398 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3399 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3401 for (; i < count; i++)
3403 elt = XVECEXP (op, 0, i);
3405 if (GET_CODE (elt) != SET
3406 || GET_CODE (SET_SRC (elt)) != REG
3407 || GET_MODE (SET_SRC (elt)) != SImode
3408 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
3409 || GET_CODE (SET_DEST (elt)) != MEM
3410 || GET_MODE (SET_DEST (elt)) != SImode
3411 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3412 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3413 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3414 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3422 load_multiple_sequence (operands, nops, regs, base, load_offset)
3427 HOST_WIDE_INT * load_offset;
3429 int unsorted_regs[4];
3430 HOST_WIDE_INT unsorted_offsets[4];
3435 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3436 extended if required. */
3437 if (nops < 2 || nops > 4)
3440 /* Loop over the operands and check that the memory references are
3441 suitable (ie immediate offsets from the same base register). At
3442 the same time, extract the target register, and the memory
3444 for (i = 0; i < nops; i++)
3449 /* Convert a subreg of a mem into the mem itself. */
3450 if (GET_CODE (operands[nops + i]) == SUBREG)
3451 operands[nops + i] = alter_subreg (operands[nops + i]);
3453 if (GET_CODE (operands[nops + i]) != MEM)
3456 /* Don't reorder volatile memory references; it doesn't seem worth
3457 looking for the case where the order is ok anyway. */
3458 if (MEM_VOLATILE_P (operands[nops + i]))
3461 offset = const0_rtx;
3463 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3464 || (GET_CODE (reg) == SUBREG
3465 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3466 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3467 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3469 || (GET_CODE (reg) == SUBREG
3470 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3471 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3476 base_reg = REGNO (reg);
3477 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3478 ? REGNO (operands[i])
3479 : REGNO (SUBREG_REG (operands[i])));
3484 if (base_reg != (int) REGNO (reg))
3485 /* Not addressed from the same base register. */
3488 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3489 ? REGNO (operands[i])
3490 : REGNO (SUBREG_REG (operands[i])));
3491 if (unsorted_regs[i] < unsorted_regs[order[0]])
3495 /* If it isn't an integer register, or if it overwrites the
3496 base register but isn't the last insn in the list, then
3497 we can't do this. */
3498 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3499 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3502 unsorted_offsets[i] = INTVAL (offset);
3505 /* Not a suitable memory address. */
3509 /* All the useful information has now been extracted from the
3510 operands into unsorted_regs and unsorted_offsets; additionally,
3511 order[0] has been set to the lowest numbered register in the
3512 list. Sort the registers into order, and check that the memory
3513 offsets are ascending and adjacent. */
3515 for (i = 1; i < nops; i++)
3519 order[i] = order[i - 1];
3520 for (j = 0; j < nops; j++)
3521 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3522 && (order[i] == order[i - 1]
3523 || unsorted_regs[j] < unsorted_regs[order[i]]))
3526 /* Have we found a suitable register? if not, one must be used more
3528 if (order[i] == order[i - 1])
3531 /* Is the memory address adjacent and ascending? */
3532 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3540 for (i = 0; i < nops; i++)
3541 regs[i] = unsorted_regs[order[i]];
3543 *load_offset = unsorted_offsets[order[0]];
3546 if (unsorted_offsets[order[0]] == 0)
3547 return 1; /* ldmia */
3549 if (unsorted_offsets[order[0]] == 4)
3550 return 2; /* ldmib */
3552 if (unsorted_offsets[order[nops - 1]] == 0)
3553 return 3; /* ldmda */
3555 if (unsorted_offsets[order[nops - 1]] == -4)
3556 return 4; /* ldmdb */
3558 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3559 if the offset isn't small enough. The reason 2 ldrs are faster
3560 is because these ARMs are able to do more than one cache access
3561 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3562 whilst the ARM8 has a double bandwidth cache. This means that
3563 these cores can do both an instruction fetch and a data fetch in
3564 a single cycle, so the trick of calculating the address into a
3565 scratch register (one of the result regs) and then doing a load
3566 multiple actually becomes slower (and no smaller in code size).
3567 That is the transformation
3569 ldr rd1, [rbase + offset]
3570 ldr rd2, [rbase + offset + 4]
3574 add rd1, rbase, offset
3575 ldmia rd1, {rd1, rd2}
3577 produces worse code -- '3 cycles + any stalls on rd2' instead of
3578 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3579 access per cycle, the first sequence could never complete in less
3580 than 6 cycles, whereas the ldm sequence would only take 5 and
3581 would make better use of sequential accesses if not hitting the
3584 We cheat here and test 'arm_ld_sched' which we currently know to
3585 only be true for the ARM8, ARM9 and StrongARM. If this ever
3586 changes, then the test below needs to be reworked. */
3587 if (nops == 2 && arm_ld_sched)
3590 /* Can't do it without setting up the offset, only do this if it takes
3591 no more than one insn. */
3592 return (const_ok_for_arm (unsorted_offsets[order[0]])
3593 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3597 emit_ldm_seq (operands, nops)
3603 HOST_WIDE_INT offset;
3607 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3610 strcpy (buf, "ldm%?ia\t");
3614 strcpy (buf, "ldm%?ib\t");
3618 strcpy (buf, "ldm%?da\t");
3622 strcpy (buf, "ldm%?db\t");
3627 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3628 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3631 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3632 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3634 output_asm_insn (buf, operands);
3636 strcpy (buf, "ldm%?ia\t");
3643 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3644 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3646 for (i = 1; i < nops; i++)
3647 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3648 reg_names[regs[i]]);
3650 strcat (buf, "}\t%@ phole ldm");
3652 output_asm_insn (buf, operands);
3657 store_multiple_sequence (operands, nops, regs, base, load_offset)
3662 HOST_WIDE_INT * load_offset;
3664 int unsorted_regs[4];
3665 HOST_WIDE_INT unsorted_offsets[4];
3670 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3671 extended if required. */
3672 if (nops < 2 || nops > 4)
3675 /* Loop over the operands and check that the memory references are
3676 suitable (ie immediate offsets from the same base register). At
3677 the same time, extract the target register, and the memory
3679 for (i = 0; i < nops; i++)
3684 /* Convert a subreg of a mem into the mem itself. */
3685 if (GET_CODE (operands[nops + i]) == SUBREG)
3686 operands[nops + i] = alter_subreg (operands[nops + i]);
3688 if (GET_CODE (operands[nops + i]) != MEM)
3691 /* Don't reorder volatile memory references; it doesn't seem worth
3692 looking for the case where the order is ok anyway. */
3693 if (MEM_VOLATILE_P (operands[nops + i]))
3696 offset = const0_rtx;
3698 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3699 || (GET_CODE (reg) == SUBREG
3700 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3701 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3702 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3704 || (GET_CODE (reg) == SUBREG
3705 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3706 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3711 base_reg = REGNO (reg);
3712 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3713 ? REGNO (operands[i])
3714 : REGNO (SUBREG_REG (operands[i])));
3719 if (base_reg != (int) REGNO (reg))
3720 /* Not addressed from the same base register. */
3723 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3724 ? REGNO (operands[i])
3725 : REGNO (SUBREG_REG (operands[i])));
3726 if (unsorted_regs[i] < unsorted_regs[order[0]])
3730 /* If it isn't an integer register, then we can't do this. */
3731 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
3734 unsorted_offsets[i] = INTVAL (offset);
3737 /* Not a suitable memory address. */
3741 /* All the useful information has now been extracted from the
3742 operands into unsorted_regs and unsorted_offsets; additionally,
3743 order[0] has been set to the lowest numbered register in the
3744 list. Sort the registers into order, and check that the memory
3745 offsets are ascending and adjacent. */
3747 for (i = 1; i < nops; i++)
3751 order[i] = order[i - 1];
3752 for (j = 0; j < nops; j++)
3753 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3754 && (order[i] == order[i - 1]
3755 || unsorted_regs[j] < unsorted_regs[order[i]]))
3758 /* Have we found a suitable register? if not, one must be used more
3760 if (order[i] == order[i - 1])
3763 /* Is the memory address adjacent and ascending? */
3764 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3772 for (i = 0; i < nops; i++)
3773 regs[i] = unsorted_regs[order[i]];
3775 *load_offset = unsorted_offsets[order[0]];
3778 if (unsorted_offsets[order[0]] == 0)
3779 return 1; /* stmia */
3781 if (unsorted_offsets[order[0]] == 4)
3782 return 2; /* stmib */
3784 if (unsorted_offsets[order[nops - 1]] == 0)
3785 return 3; /* stmda */
3787 if (unsorted_offsets[order[nops - 1]] == -4)
3788 return 4; /* stmdb */
3794 emit_stm_seq (operands, nops)
3800 HOST_WIDE_INT offset;
3804 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3807 strcpy (buf, "stm%?ia\t");
3811 strcpy (buf, "stm%?ib\t");
3815 strcpy (buf, "stm%?da\t");
3819 strcpy (buf, "stm%?db\t");
3826 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3827 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3829 for (i = 1; i < nops; i++)
3830 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3831 reg_names[regs[i]]);
3833 strcat (buf, "}\t%@ phole stm");
3835 output_asm_insn (buf, operands);
3840 multi_register_push (op, mode)
3842 enum machine_mode mode ATTRIBUTE_UNUSED;
3844 if (GET_CODE (op) != PARALLEL
3845 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3846 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3847 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3853 /* Routines for use with attributes. */
3855 /* Return nonzero if ATTR is a valid attribute for DECL.
3856 ATTRIBUTES are any existing attributes and ARGS are
3857 the arguments supplied with ATTR.
3859 Supported attributes:
3862 don't output any prologue or epilogue code, the user is assumed
3863 to do the right thing.
3866 Always assume that this function will be entered in ARM mode,
3867 not Thumb mode, and that the caller wishes to be returned to in
3870 arm_valid_machine_decl_attribute (decl, attr, args)
3875 if (args != NULL_TREE)
3878 if (is_attribute_p ("naked", attr))
3879 return TREE_CODE (decl) == FUNCTION_DECL;
3882 if (is_attribute_p ("interfacearm", attr))
3883 return TREE_CODE (decl) == FUNCTION_DECL;
3889 /* Return non-zero if FUNC is a naked function. */
3891 arm_naked_function_p (func)
3896 if (TREE_CODE (func) != FUNCTION_DECL)
3899 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3900 return a != NULL_TREE;
3903 /* Routines for use in generating RTL. */
3905 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3906 in_struct_p, scalar_p)
3918 int sign = up ? 1 : -1;
3921 /* XScale has load-store double instructions, but they have stricter
3922 alignment requirements than load-store multiple, so we can not
3925 For XScale ldm requires 2 + NREGS cycles to complete and blocks
3926 the pipeline until completion.
3934 An ldr instruction takes 1-3 cycles, but does not block the
3943 Best case ldr will always win. However, the more ldr instructions
3944 we issue, the less likely we are to be able to schedule them well.
3945 Using ldr instructions also increases code size.
3947 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
3948 for counts of 3 or 4 regs. */
3949 if (arm_is_xscale && count <= 2 && ! optimize_size)
3955 for (i = 0; i < count; i++)
3957 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
3958 RTX_UNCHANGING_P (mem) = unchanging_p;
3959 MEM_IN_STRUCT_P (mem) = in_struct_p;
3960 MEM_SCALAR_P (mem) = scalar_p;
3961 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
3965 emit_move_insn (from, plus_constant (from, count * 4 * sign));
3967 seq = gen_sequence ();
3973 result = gen_rtx_PARALLEL (VOIDmode,
3974 rtvec_alloc (count + (write_back ? 1 : 0)));
3977 XVECEXP (result, 0, 0)
3978 = gen_rtx_SET (GET_MODE (from), from,
3979 plus_constant (from, count * 4 * sign));
3984 for (j = 0; i < count; i++, j++)
3986 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3987 RTX_UNCHANGING_P (mem) = unchanging_p;
3988 MEM_IN_STRUCT_P (mem) = in_struct_p;
3989 MEM_SCALAR_P (mem) = scalar_p;
3990 XVECEXP (result, 0, i)
3991 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3998 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3999 in_struct_p, scalar_p)
4011 int sign = up ? 1 : -1;
4014 /* See arm_gen_load_multiple for discussion of
4015 the pros/cons of ldm/stm usage for XScale. */
4016 if (arm_is_xscale && count <= 2 && ! optimize_size)
4022 for (i = 0; i < count; i++)
4024 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
4025 RTX_UNCHANGING_P (mem) = unchanging_p;
4026 MEM_IN_STRUCT_P (mem) = in_struct_p;
4027 MEM_SCALAR_P (mem) = scalar_p;
4028 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
4032 emit_move_insn (to, plus_constant (to, count * 4 * sign));
4034 seq = gen_sequence ();
4040 result = gen_rtx_PARALLEL (VOIDmode,
4041 rtvec_alloc (count + (write_back ? 1 : 0)));
4044 XVECEXP (result, 0, 0)
4045 = gen_rtx_SET (GET_MODE (to), to,
4046 plus_constant (to, count * 4 * sign));
4051 for (j = 0; i < count; i++, j++)
4053 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
4054 RTX_UNCHANGING_P (mem) = unchanging_p;
4055 MEM_IN_STRUCT_P (mem) = in_struct_p;
4056 MEM_SCALAR_P (mem) = scalar_p;
4058 XVECEXP (result, 0, i)
4059 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
4066 arm_gen_movstrqi (operands)
4069 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
4072 rtx st_src, st_dst, fin_src, fin_dst;
4073 rtx part_bytes_reg = NULL;
4075 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
4076 int dst_scalar_p, src_scalar_p;
4078 if (GET_CODE (operands[2]) != CONST_INT
4079 || GET_CODE (operands[3]) != CONST_INT
4080 || INTVAL (operands[2]) > 64
4081 || INTVAL (operands[3]) & 3)
4084 st_dst = XEXP (operands[0], 0);
4085 st_src = XEXP (operands[1], 0);
4087 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
4088 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
4089 dst_scalar_p = MEM_SCALAR_P (operands[0]);
4090 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
4091 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
4092 src_scalar_p = MEM_SCALAR_P (operands[1]);
4094 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
4095 fin_src = src = copy_to_mode_reg (SImode, st_src);
4097 in_words_to_go = NUM_INTS (INTVAL (operands[2]));
4098 out_words_to_go = INTVAL (operands[2]) / 4;
4099 last_bytes = INTVAL (operands[2]) & 3;
4101 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
4102 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
4104 for (i = 0; in_words_to_go >= 2; i+=4)
4106 if (in_words_to_go > 4)
4107 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
4112 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
4113 FALSE, src_unchanging_p,
4114 src_in_struct_p, src_scalar_p));
4116 if (out_words_to_go)
4118 if (out_words_to_go > 4)
4119 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
4123 else if (out_words_to_go != 1)
4124 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
4133 mem = gen_rtx_MEM (SImode, dst);
4134 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4135 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4136 MEM_SCALAR_P (mem) = dst_scalar_p;
4137 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
4138 if (last_bytes != 0)
4139 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
4143 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
4144 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
4147 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4148 if (out_words_to_go)
4152 mem = gen_rtx_MEM (SImode, src);
4153 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4154 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4155 MEM_SCALAR_P (mem) = src_scalar_p;
4156 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
4157 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
4159 mem = gen_rtx_MEM (SImode, dst);
4160 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4161 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4162 MEM_SCALAR_P (mem) = dst_scalar_p;
4163 emit_move_insn (mem, sreg);
4164 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
4167 if (in_words_to_go) /* Sanity check */
4173 if (in_words_to_go < 0)
4176 mem = gen_rtx_MEM (SImode, src);
4177 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4178 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4179 MEM_SCALAR_P (mem) = src_scalar_p;
4180 part_bytes_reg = copy_to_mode_reg (SImode, mem);
4183 if (last_bytes && part_bytes_reg == NULL)
4186 if (BYTES_BIG_ENDIAN && last_bytes)
4188 rtx tmp = gen_reg_rtx (SImode);
4190 /* The bytes we want are in the top end of the word. */
4191 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
4192 GEN_INT (8 * (4 - last_bytes))));
4193 part_bytes_reg = tmp;
4197 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
4198 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4199 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4200 MEM_SCALAR_P (mem) = dst_scalar_p;
4201 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4205 tmp = gen_reg_rtx (SImode);
4206 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
4207 part_bytes_reg = tmp;
4216 mem = gen_rtx_MEM (HImode, dst);
4217 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4218 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4219 MEM_SCALAR_P (mem) = dst_scalar_p;
4220 emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
4224 rtx tmp = gen_reg_rtx (SImode);
4226 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
4227 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
4228 part_bytes_reg = tmp;
4234 mem = gen_rtx_MEM (QImode, dst);
4235 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4236 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4237 MEM_SCALAR_P (mem) = dst_scalar_p;
4238 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4245 /* Generate a memory reference for a half word, such that it will be loaded
4246 into the top 16 bits of the word. We can assume that the address is
4247 known to be alignable and of the form reg, or plus (reg, const). */
4249 arm_gen_rotated_half_load (memref)
4252 HOST_WIDE_INT offset = 0;
4253 rtx base = XEXP (memref, 0);
4255 if (GET_CODE (base) == PLUS)
4257 offset = INTVAL (XEXP (base, 1));
4258 base = XEXP (base, 0);
4261 /* If we aren't allowed to generate unaligned addresses, then fail. */
4262 if (TARGET_MMU_TRAPS
4263 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
4266 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
4268 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
4271 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
4274 /* Select a dominance comparison mode if possible. We support three forms.
4275 COND_OR == 0 => (X && Y)
4276 COND_OR == 1 => ((! X( || Y)
4277 COND_OR == 2 => (X || Y)
4278 If we are unable to support a dominance comparsison we return CC mode.
4279 This will then fail to match for the RTL expressions that generate this
4282 static enum machine_mode
4283 select_dominance_cc_mode (x, y, cond_or)
4286 HOST_WIDE_INT cond_or;
4288 enum rtx_code cond1, cond2;
4291 /* Currently we will probably get the wrong result if the individual
4292 comparisons are not simple. This also ensures that it is safe to
4293 reverse a comparison if necessary. */
4294 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
4296 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
4300 /* The if_then_else variant of this tests the second condition if the
4301 first passes, but is true if the first fails. Reverse the first
4302 condition to get a true "inclusive-or" expression. */
4304 cond1 = reverse_condition (cond1);
4306 /* If the comparisons are not equal, and one doesn't dominate the other,
4307 then we can't do this. */
4309 && !comparison_dominates_p (cond1, cond2)
4310 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
4315 enum rtx_code temp = cond1;
4323 if (cond2 == EQ || !cond_or)
4328 case LE: return CC_DLEmode;
4329 case LEU: return CC_DLEUmode;
4330 case GE: return CC_DGEmode;
4331 case GEU: return CC_DGEUmode;
4338 if (cond2 == LT || !cond_or)
4347 if (cond2 == GT || !cond_or)
4356 if (cond2 == LTU || !cond_or)
4365 if (cond2 == GTU || !cond_or)
4373 /* The remaining cases only occur when both comparisons are the
4398 arm_select_cc_mode (op, x, y)
4403 /* All floating point compares return CCFP if it is an equality
4404 comparison, and CCFPE otherwise. */
4405 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4432 /* A compare with a shifted operand. Because of canonicalization, the
4433 comparison will have to be swapped when we emit the assembler. */
4434 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
4435 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4436 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
4437 || GET_CODE (x) == ROTATERT))
4440 /* This is a special case that is used by combine to allow a
4441 comparison of a shifted byte load to be split into a zero-extend
4442 followed by a comparison of the shifted integer (only valid for
4443 equalities and unsigned inequalities). */
4444 if (GET_MODE (x) == SImode
4445 && GET_CODE (x) == ASHIFT
4446 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
4447 && GET_CODE (XEXP (x, 0)) == SUBREG
4448 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
4449 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
4450 && (op == EQ || op == NE
4451 || op == GEU || op == GTU || op == LTU || op == LEU)
4452 && GET_CODE (y) == CONST_INT)
4455 /* A construct for a conditional compare, if the false arm contains
4456 0, then both conditions must be true, otherwise either condition
4457 must be true. Not all conditions are possible, so CCmode is
4458 returned if it can't be done. */
4459 if (GET_CODE (x) == IF_THEN_ELSE
4460 && (XEXP (x, 2) == const0_rtx
4461 || XEXP (x, 2) == const1_rtx)
4462 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4463 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4464 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
4465 INTVAL (XEXP (x, 2)));
4467 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4468 if (GET_CODE (x) == AND
4469 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4470 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4471 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0);
4473 if (GET_CODE (x) == IOR
4474 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4475 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4476 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2);
4478 /* An operation that sets the condition codes as a side-effect, the
4479 V flag is not set correctly, so we can only use comparisons where
4480 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4482 if (GET_MODE (x) == SImode
4484 && (op == EQ || op == NE || op == LT || op == GE)
4485 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
4486 || GET_CODE (x) == AND || GET_CODE (x) == IOR
4487 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
4488 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
4489 || GET_CODE (x) == LSHIFTRT
4490 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4491 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
4494 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
4497 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
4498 && GET_CODE (x) == PLUS
4499 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
4505 /* X and Y are two things to compare using CODE. Emit the compare insn and
4506 return the rtx for register 0 in the proper mode. FP means this is a
4507 floating point compare: I don't think that it is needed on the arm. */
4510 arm_gen_compare_reg (code, x, y)
4514 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4515 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
4517 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4518 gen_rtx_COMPARE (mode, x, y)));
4524 arm_reload_in_hi (operands)
4527 rtx ref = operands[1];
4529 HOST_WIDE_INT offset = 0;
4531 if (GET_CODE (ref) == SUBREG)
4533 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4534 if (BYTES_BIG_ENDIAN)
4535 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4536 - MIN (UNITS_PER_WORD,
4537 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4538 ref = SUBREG_REG (ref);
4541 if (GET_CODE (ref) == REG)
4543 /* We have a pseudo which has been spilt onto the stack; there
4544 are two cases here: the first where there is a simple
4545 stack-slot replacement and a second where the stack-slot is
4546 out of range, or is used as a subreg. */
4547 if (reg_equiv_mem[REGNO (ref)])
4549 ref = reg_equiv_mem[REGNO (ref)];
4550 base = find_replacement (&XEXP (ref, 0));
4553 /* The slot is out of range, or was dressed up in a SUBREG. */
4554 base = reg_equiv_address[REGNO (ref)];
4557 base = find_replacement (&XEXP (ref, 0));
4559 /* Handle the case where the address is too complex to be offset by 1. */
4560 if (GET_CODE (base) == MINUS
4561 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4563 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4565 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4568 else if (GET_CODE (base) == PLUS)
4570 /* The addend must be CONST_INT, or we would have dealt with it above. */
4571 HOST_WIDE_INT hi, lo;
4573 offset += INTVAL (XEXP (base, 1));
4574 base = XEXP (base, 0);
4576 /* Rework the address into a legal sequence of insns. */
4577 /* Valid range for lo is -4095 -> 4095 */
4580 : -((-offset) & 0xfff));
4582 /* Corner case, if lo is the max offset then we would be out of range
4583 once we have added the additional 1 below, so bump the msb into the
4584 pre-loading insn(s). */
4588 hi = ((((offset - lo) & HOST_INT (0xffffffff))
4589 ^ HOST_INT (0x80000000))
4590 - HOST_INT (0x80000000));
4592 if (hi + lo != offset)
4597 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4599 /* Get the base address; addsi3 knows how to handle constants
4600 that require more than one insn. */
4601 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4607 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4608 emit_insn (gen_zero_extendqisi2 (scratch,
4609 gen_rtx_MEM (QImode,
4610 plus_constant (base,
4612 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4613 gen_rtx_MEM (QImode,
4614 plus_constant (base,
4616 if (!BYTES_BIG_ENDIAN)
4617 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4618 gen_rtx_IOR (SImode,
4621 gen_rtx_SUBREG (SImode, operands[0], 0),
4625 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4626 gen_rtx_IOR (SImode,
4627 gen_rtx_ASHIFT (SImode, scratch,
4629 gen_rtx_SUBREG (SImode, operands[0],
4633 /* Handle storing a half-word to memory during reload by synthesising as two
4634 byte stores. Take care not to clobber the input values until after we
4635 have moved them somewhere safe. This code assumes that if the DImode
4636 scratch in operands[2] overlaps either the input value or output address
4637 in some way, then that value must die in this insn (we absolutely need
4638 two scratch registers for some corner cases). */
4640 arm_reload_out_hi (operands)
4643 rtx ref = operands[0];
4644 rtx outval = operands[1];
4646 HOST_WIDE_INT offset = 0;
4648 if (GET_CODE (ref) == SUBREG)
4650 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4651 if (BYTES_BIG_ENDIAN)
4652 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4653 - MIN (UNITS_PER_WORD,
4654 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4655 ref = SUBREG_REG (ref);
4659 if (GET_CODE (ref) == REG)
4661 /* We have a pseudo which has been spilt onto the stack; there
4662 are two cases here: the first where there is a simple
4663 stack-slot replacement and a second where the stack-slot is
4664 out of range, or is used as a subreg. */
4665 if (reg_equiv_mem[REGNO (ref)])
4667 ref = reg_equiv_mem[REGNO (ref)];
4668 base = find_replacement (&XEXP (ref, 0));
4671 /* The slot is out of range, or was dressed up in a SUBREG. */
4672 base = reg_equiv_address[REGNO (ref)];
4675 base = find_replacement (&XEXP (ref, 0));
4677 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4679 /* Handle the case where the address is too complex to be offset by 1. */
4680 if (GET_CODE (base) == MINUS
4681 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4683 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4685 /* Be careful not to destroy OUTVAL. */
4686 if (reg_overlap_mentioned_p (base_plus, outval))
4688 /* Updating base_plus might destroy outval, see if we can
4689 swap the scratch and base_plus. */
4690 if (!reg_overlap_mentioned_p (scratch, outval))
4693 scratch = base_plus;
4698 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4700 /* Be conservative and copy OUTVAL into the scratch now,
4701 this should only be necessary if outval is a subreg
4702 of something larger than a word. */
4703 /* XXX Might this clobber base? I can't see how it can,
4704 since scratch is known to overlap with OUTVAL, and
4705 must be wider than a word. */
4706 emit_insn (gen_movhi (scratch_hi, outval));
4707 outval = scratch_hi;
4711 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4714 else if (GET_CODE (base) == PLUS)
4716 /* The addend must be CONST_INT, or we would have dealt with it above. */
4717 HOST_WIDE_INT hi, lo;
4719 offset += INTVAL (XEXP (base, 1));
4720 base = XEXP (base, 0);
4722 /* Rework the address into a legal sequence of insns. */
4723 /* Valid range for lo is -4095 -> 4095 */
4726 : -((-offset) & 0xfff));
4728 /* Corner case, if lo is the max offset then we would be out of range
4729 once we have added the additional 1 below, so bump the msb into the
4730 pre-loading insn(s). */
4734 hi = ((((offset - lo) & HOST_INT (0xffffffff))
4735 ^ HOST_INT (0x80000000))
4736 - HOST_INT (0x80000000));
4738 if (hi + lo != offset)
4743 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4745 /* Be careful not to destroy OUTVAL. */
4746 if (reg_overlap_mentioned_p (base_plus, outval))
4748 /* Updating base_plus might destroy outval, see if we
4749 can swap the scratch and base_plus. */
4750 if (!reg_overlap_mentioned_p (scratch, outval))
4753 scratch = base_plus;
4758 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4760 /* Be conservative and copy outval into scratch now,
4761 this should only be necessary if outval is a
4762 subreg of something larger than a word. */
4763 /* XXX Might this clobber base? I can't see how it
4764 can, since scratch is known to overlap with
4766 emit_insn (gen_movhi (scratch_hi, outval));
4767 outval = scratch_hi;
4771 /* Get the base address; addsi3 knows how to handle constants
4772 that require more than one insn. */
4773 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4779 if (BYTES_BIG_ENDIAN)
4781 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4782 plus_constant (base, offset + 1)),
4783 gen_rtx_SUBREG (QImode, outval, 0)));
4784 emit_insn (gen_lshrsi3 (scratch,
4785 gen_rtx_SUBREG (SImode, outval, 0),
4787 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4788 gen_rtx_SUBREG (QImode, scratch, 0)));
4792 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4793 gen_rtx_SUBREG (QImode, outval, 0)));
4794 emit_insn (gen_lshrsi3 (scratch,
4795 gen_rtx_SUBREG (SImode, outval, 0),
4797 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4798 plus_constant (base, offset + 1)),
4799 gen_rtx_SUBREG (QImode, scratch, 0)));
4803 /* Print a symbolic form of X to the debug file, F. */
4805 arm_print_value (f, x)
4809 switch (GET_CODE (x))
4812 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
4816 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
4820 fprintf (f, "\"%s\"", XSTR (x, 0));
4824 fprintf (f, "`%s'", XSTR (x, 0));
4828 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
4832 arm_print_value (f, XEXP (x, 0));
4836 arm_print_value (f, XEXP (x, 0));
4838 arm_print_value (f, XEXP (x, 1));
4846 fprintf (f, "????");
4851 /* Routines for manipulation of the constant pool. */
4853 /* Arm instructions cannot load a large constant directly into a
4854 register; they have to come from a pc relative load. The constant
4855 must therefore be placed in the addressable range of the pc
4856 relative load. Depending on the precise pc relative load
4857 instruction the range is somewhere between 256 bytes and 4k. This
4858 means that we often have to dump a constant inside a function, and
4859 generate code to branch around it.
4861 It is important to minimize this, since the branches will slow
4862 things down and make the code larger.
4864 Normally we can hide the table after an existing unconditional
4865 branch so that there is no interruption of the flow, but in the
4866 worst case the code looks like this:
4884 We fix this by performing a scan after scheduling, which notices
4885 which instructions need to have their operands fetched from the
4886 constant table and builds the table.
4888 The algorithm starts by building a table of all the constants that
4889 need fixing up and all the natural barriers in the function (places
4890 where a constant table can be dropped without breaking the flow).
4891 For each fixup we note how far the pc-relative replacement will be
4892 able to reach and the offset of the instruction into the function.
4894 Having built the table we then group the fixes together to form
4895 tables that are as large as possible (subject to addressing
4896 constraints) and emit each table of constants after the last
4897 barrier that is within range of all the instructions in the group.
4898 If a group does not contain a barrier, then we forcibly create one
4899 by inserting a jump instruction into the flow. Once the table has
4900 been inserted, the insns are then modified to reference the
4901 relevant entry in the pool.
4903 Possible enhancements to the algorithm (not implemented) are:
4905 1) For some processors and object formats, there may be benefit in
4906 aligning the pools to the start of cache lines; this alignment
4907 would need to be taken into account when calculating addressability
4910 /* These typedefs are located at the start of this file, so that
4911 they can be used in the prototypes there. This comment is to
4912 remind readers of that fact so that the following structures
4913 can be understood more easily.
4915 typedef struct minipool_node Mnode;
4916 typedef struct minipool_fixup Mfix; */
4918 struct minipool_node
4920 /* Doubly linked chain of entries. */
4923 /* The maximum offset into the code that this entry can be placed. While
4924 pushing fixes for forward references, all entries are sorted in order
4925 of increasing max_address. */
4926 HOST_WIDE_INT max_address;
4927 /* Similarly for a entry inserted for a backwards ref. */
4928 HOST_WIDE_INT min_address;
4929 /* The number of fixes referencing this entry. This can become zero
4930 if we "unpush" an entry. In this case we ignore the entry when we
4931 come to emit the code. */
4933 /* The offset from the start of the minipool. */
4934 HOST_WIDE_INT offset;
4935 /* The value in table. */
4937 /* The mode of value. */
4938 enum machine_mode mode;
4942 struct minipool_fixup
4946 HOST_WIDE_INT address;
4948 enum machine_mode mode;
4952 HOST_WIDE_INT forwards;
4953 HOST_WIDE_INT backwards;
4956 /* Fixes less than a word need padding out to a word boundary. */
4957 #define MINIPOOL_FIX_SIZE(mode) \
4958 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
4960 static Mnode * minipool_vector_head;
4961 static Mnode * minipool_vector_tail;
4962 static rtx minipool_vector_label;
4964 /* The linked list of all minipool fixes required for this function. */
4965 Mfix * minipool_fix_head;
4966 Mfix * minipool_fix_tail;
4967 /* The fix entry for the current minipool, once it has been placed. */
4968 Mfix * minipool_barrier;
4970 /* Determines if INSN is the start of a jump table. Returns the end
4971 of the TABLE or NULL_RTX. */
4973 is_jump_table (insn)
4978 if (GET_CODE (insn) == JUMP_INSN
4979 && JUMP_LABEL (insn) != NULL
4980 && ((table = next_real_insn (JUMP_LABEL (insn)))
4981 == next_real_insn (insn))
4983 && GET_CODE (table) == JUMP_INSN
4984 && (GET_CODE (PATTERN (table)) == ADDR_VEC
4985 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
4991 static HOST_WIDE_INT
4992 get_jump_table_size (insn)
4995 rtx body = PATTERN (insn);
4996 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
4998 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
5001 /* Move a minipool fix MP from its current location to before MAX_MP.
5002 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5003 contrains may need updating. */
5005 move_minipool_fix_forward_ref (mp, max_mp, max_address)
5008 HOST_WIDE_INT max_address;
5010 /* This should never be true and the code below assumes these are
5017 if (max_address < mp->max_address)
5018 mp->max_address = max_address;
5022 if (max_address > max_mp->max_address - mp->fix_size)
5023 mp->max_address = max_mp->max_address - mp->fix_size;
5025 mp->max_address = max_address;
5027 /* Unlink MP from its current position. Since max_mp is non-null,
5028 mp->prev must be non-null. */
5029 mp->prev->next = mp->next;
5030 if (mp->next != NULL)
5031 mp->next->prev = mp->prev;
5033 minipool_vector_tail = mp->prev;
5035 /* Re-insert it before MAX_MP. */
5037 mp->prev = max_mp->prev;
5040 if (mp->prev != NULL)
5041 mp->prev->next = mp;
5043 minipool_vector_head = mp;
5046 /* Save the new entry. */
5049 /* Scan over the preceeding entries and adjust their addresses as
5051 while (mp->prev != NULL
5052 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5054 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5061 /* Add a constant to the minipool for a forward reference. Returns the
5062 node added or NULL if the constant will not fit in this pool. */
5064 add_minipool_forward_ref (fix)
5067 /* If set, max_mp is the first pool_entry that has a lower
5068 constraint than the one we are trying to add. */
5069 Mnode * max_mp = NULL;
5070 HOST_WIDE_INT max_address = fix->address + fix->forwards;
5073 /* If this fix's address is greater than the address of the first
5074 entry, then we can't put the fix in this pool. We subtract the
5075 size of the current fix to ensure that if the table is fully
5076 packed we still have enough room to insert this value by suffling
5077 the other fixes forwards. */
5078 if (minipool_vector_head &&
5079 fix->address >= minipool_vector_head->max_address - fix->fix_size)
5082 /* Scan the pool to see if a constant with the same value has
5083 already been added. While we are doing this, also note the
5084 location where we must insert the constant if it doesn't already
5086 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5088 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5089 && fix->mode == mp->mode
5090 && (GET_CODE (fix->value) != CODE_LABEL
5091 || (CODE_LABEL_NUMBER (fix->value)
5092 == CODE_LABEL_NUMBER (mp->value)))
5093 && rtx_equal_p (fix->value, mp->value))
5095 /* More than one fix references this entry. */
5097 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
5100 /* Note the insertion point if necessary. */
5102 && mp->max_address > max_address)
5106 /* The value is not currently in the minipool, so we need to create
5107 a new entry for it. If MAX_MP is NULL, the entry will be put on
5108 the end of the list since the placement is less constrained than
5109 any existing entry. Otherwise, we insert the new fix before
5110 MAX_MP and, if neceesary, adjust the constraints on the other
5112 mp = xmalloc (sizeof (* mp));
5113 mp->fix_size = fix->fix_size;
5114 mp->mode = fix->mode;
5115 mp->value = fix->value;
5117 /* Not yet required for a backwards ref. */
5118 mp->min_address = -65536;
5122 mp->max_address = max_address;
5124 mp->prev = minipool_vector_tail;
5126 if (mp->prev == NULL)
5128 minipool_vector_head = mp;
5129 minipool_vector_label = gen_label_rtx ();
5132 mp->prev->next = mp;
5134 minipool_vector_tail = mp;
5138 if (max_address > max_mp->max_address - mp->fix_size)
5139 mp->max_address = max_mp->max_address - mp->fix_size;
5141 mp->max_address = max_address;
5144 mp->prev = max_mp->prev;
5146 if (mp->prev != NULL)
5147 mp->prev->next = mp;
5149 minipool_vector_head = mp;
5152 /* Save the new entry. */
5155 /* Scan over the preceeding entries and adjust their addresses as
5157 while (mp->prev != NULL
5158 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5160 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5168 move_minipool_fix_backward_ref (mp, min_mp, min_address)
5171 HOST_WIDE_INT min_address;
5173 HOST_WIDE_INT offset;
5175 /* This should never be true, and the code below assumes these are
5182 if (min_address > mp->min_address)
5183 mp->min_address = min_address;
5187 /* We will adjust this below if it is too loose. */
5188 mp->min_address = min_address;
5190 /* Unlink MP from its current position. Since min_mp is non-null,
5191 mp->next must be non-null. */
5192 mp->next->prev = mp->prev;
5193 if (mp->prev != NULL)
5194 mp->prev->next = mp->next;
5196 minipool_vector_head = mp->next;
5198 /* Reinsert it after MIN_MP. */
5200 mp->next = min_mp->next;
5202 if (mp->next != NULL)
5203 mp->next->prev = mp;
5205 minipool_vector_tail = mp;
5211 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5213 mp->offset = offset;
5214 if (mp->refcount > 0)
5215 offset += mp->fix_size;
5217 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
5218 mp->next->min_address = mp->min_address + mp->fix_size;
5224 /* Add a constant to the minipool for a backward reference. Returns the
5225 node added or NULL if the constant will not fit in this pool.
5227 Note that the code for insertion for a backwards reference can be
5228 somewhat confusing because the calculated offsets for each fix do
5229 not take into account the size of the pool (which is still under
5232 add_minipool_backward_ref (fix)
5235 /* If set, min_mp is the last pool_entry that has a lower constraint
5236 than the one we are trying to add. */
5237 Mnode * min_mp = NULL;
5238 /* This can be negative, since it is only a constraint. */
5239 HOST_WIDE_INT min_address = fix->address - fix->backwards;
5242 /* If we can't reach the current pool from this insn, or if we can't
5243 insert this entry at the end of the pool without pushing other
5244 fixes out of range, then we don't try. This ensures that we
5245 can't fail later on. */
5246 if (min_address >= minipool_barrier->address
5247 || (minipool_vector_tail->min_address + fix->fix_size
5248 >= minipool_barrier->address))
5251 /* Scan the pool to see if a constant with the same value has
5252 already been added. While we are doing this, also note the
5253 location where we must insert the constant if it doesn't already
5255 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
5257 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5258 && fix->mode == mp->mode
5259 && (GET_CODE (fix->value) != CODE_LABEL
5260 || (CODE_LABEL_NUMBER (fix->value)
5261 == CODE_LABEL_NUMBER (mp->value)))
5262 && rtx_equal_p (fix->value, mp->value)
5263 /* Check that there is enough slack to move this entry to the
5264 end of the table (this is conservative). */
5266 > (minipool_barrier->address
5267 + minipool_vector_tail->offset
5268 + minipool_vector_tail->fix_size)))
5271 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
5275 mp->min_address += fix->fix_size;
5278 /* Note the insertion point if necessary. */
5279 if (mp->min_address < min_address)
5281 else if (mp->max_address
5282 < minipool_barrier->address + mp->offset + fix->fix_size)
5284 /* Inserting before this entry would push the fix beyond
5285 its maximum address (which can happen if we have
5286 re-located a forwards fix); force the new fix to come
5289 min_address = mp->min_address + fix->fix_size;
5294 /* We need to create a new entry. */
5295 mp = xmalloc (sizeof (* mp));
5296 mp->fix_size = fix->fix_size;
5297 mp->mode = fix->mode;
5298 mp->value = fix->value;
5300 mp->max_address = minipool_barrier->address + 65536;
5302 mp->min_address = min_address;
5307 mp->next = minipool_vector_head;
5309 if (mp->next == NULL)
5311 minipool_vector_tail = mp;
5312 minipool_vector_label = gen_label_rtx ();
5315 mp->next->prev = mp;
5317 minipool_vector_head = mp;
5321 mp->next = min_mp->next;
5325 if (mp->next != NULL)
5326 mp->next->prev = mp;
5328 minipool_vector_tail = mp;
5331 /* Save the new entry. */
5339 /* Scan over the following entries and adjust their offsets. */
5340 while (mp->next != NULL)
5342 if (mp->next->min_address < mp->min_address + mp->fix_size)
5343 mp->next->min_address = mp->min_address + mp->fix_size;
5346 mp->next->offset = mp->offset + mp->fix_size;
5348 mp->next->offset = mp->offset;
5357 assign_minipool_offsets (barrier)
5360 HOST_WIDE_INT offset = 0;
5363 minipool_barrier = barrier;
5365 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5367 mp->offset = offset;
5369 if (mp->refcount > 0)
5370 offset += mp->fix_size;
5374 /* Output the literal table */
5376 dump_minipool (scan)
5383 fprintf (rtl_dump_file,
5384 ";; Emitting minipool after insn %u; address %ld\n",
5385 INSN_UID (scan), (unsigned long) minipool_barrier->address);
5387 scan = emit_label_after (gen_label_rtx (), scan);
5388 scan = emit_insn_after (gen_align_4 (), scan);
5389 scan = emit_label_after (minipool_vector_label, scan);
5391 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
5393 if (mp->refcount > 0)
5397 fprintf (rtl_dump_file,
5398 ";; Offset %u, min %ld, max %ld ",
5399 (unsigned) mp->offset, (unsigned long) mp->min_address,
5400 (unsigned long) mp->max_address);
5401 arm_print_value (rtl_dump_file, mp->value);
5402 fputc ('\n', rtl_dump_file);
5405 switch (mp->fix_size)
5407 #ifdef HAVE_consttable_1
5409 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
5413 #ifdef HAVE_consttable_2
5415 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
5419 #ifdef HAVE_consttable_4
5421 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
5425 #ifdef HAVE_consttable_8
5427 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
5441 minipool_vector_head = minipool_vector_tail = NULL;
5442 scan = emit_insn_after (gen_consttable_end (), scan);
5443 scan = emit_barrier_after (scan);
5446 /* Return the cost of forcibly inserting a barrier after INSN. */
5448 arm_barrier_cost (insn)
5451 /* Basing the location of the pool on the loop depth is preferable,
5452 but at the moment, the basic block information seems to be
5453 corrupt by this stage of the compilation. */
5455 rtx next = next_nonnote_insn (insn);
5457 if (next != NULL && GET_CODE (next) == CODE_LABEL)
5460 switch (GET_CODE (insn))
5463 /* It will always be better to place the table before the label, rather
5472 return base_cost - 10;
5475 return base_cost + 10;
5479 /* Find the best place in the insn stream in the range
5480 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5481 Create the barrier by inserting a jump and add a new fix entry for
5484 create_fix_barrier (fix, max_address)
5486 HOST_WIDE_INT max_address;
5488 HOST_WIDE_INT count = 0;
5490 rtx from = fix->insn;
5491 rtx selected = from;
5493 HOST_WIDE_INT selected_address;
5495 HOST_WIDE_INT max_count = max_address - fix->address;
5496 rtx label = gen_label_rtx ();
5498 selected_cost = arm_barrier_cost (from);
5499 selected_address = fix->address;
5501 while (from && count < max_count)
5506 /* This code shouldn't have been called if there was a natural barrier
5508 if (GET_CODE (from) == BARRIER)
5511 /* Count the length of this insn. */
5512 count += get_attr_length (from);
5514 /* If there is a jump table, add its length. */
5515 tmp = is_jump_table (from);
5518 count += get_jump_table_size (tmp);
5520 /* Jump tables aren't in a basic block, so base the cost on
5521 the dispatch insn. If we select this location, we will
5522 still put the pool after the table. */
5523 new_cost = arm_barrier_cost (from);
5525 if (count < max_count && new_cost <= selected_cost)
5528 selected_cost = new_cost;
5529 selected_address = fix->address + count;
5532 /* Continue after the dispatch table. */
5533 from = NEXT_INSN (tmp);
5537 new_cost = arm_barrier_cost (from);
5539 if (count < max_count && new_cost <= selected_cost)
5542 selected_cost = new_cost;
5543 selected_address = fix->address + count;
5546 from = NEXT_INSN (from);
5549 /* Create a new JUMP_INSN that branches around a barrier. */
5550 from = emit_jump_insn_after (gen_jump (label), selected);
5551 JUMP_LABEL (from) = label;
5552 barrier = emit_barrier_after (from);
5553 emit_label_after (label, barrier);
5555 /* Create a minipool barrier entry for the new barrier. */
5556 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
5557 new_fix->insn = barrier;
5558 new_fix->address = selected_address;
5559 new_fix->next = fix->next;
5560 fix->next = new_fix;
5565 /* Record that there is a natural barrier in the insn stream at
5568 push_minipool_barrier (insn, address)
5570 HOST_WIDE_INT address;
5572 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5575 fix->address = address;
5578 if (minipool_fix_head != NULL)
5579 minipool_fix_tail->next = fix;
5581 minipool_fix_head = fix;
5583 minipool_fix_tail = fix;
5586 /* Record INSN, which will need fixing up to load a value from the
5587 minipool. ADDRESS is the offset of the insn since the start of the
5588 function; LOC is a pointer to the part of the insn which requires
5589 fixing; VALUE is the constant that must be loaded, which is of type
5592 push_minipool_fix (insn, address, loc, mode, value)
5594 HOST_WIDE_INT address;
5596 enum machine_mode mode;
5599 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5601 #ifdef AOF_ASSEMBLER
5602 /* PIC symbol refereneces need to be converted into offsets into the
5604 /* XXX This shouldn't be done here. */
5605 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
5606 value = aof_pic_entry (value);
5607 #endif /* AOF_ASSEMBLER */
5610 fix->address = address;
5613 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
5615 fix->forwards = get_attr_pool_range (insn);
5616 fix->backwards = get_attr_neg_pool_range (insn);
5617 fix->minipool = NULL;
5619 /* If an insn doesn't have a range defined for it, then it isn't
5620 expecting to be reworked by this code. Better to abort now than
5621 to generate duff assembly code. */
5622 if (fix->forwards == 0 && fix->backwards == 0)
5627 fprintf (rtl_dump_file,
5628 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
5629 GET_MODE_NAME (mode),
5630 INSN_UID (insn), (unsigned long) address,
5631 -1 * (long)fix->backwards, (long)fix->forwards);
5632 arm_print_value (rtl_dump_file, fix->value);
5633 fprintf (rtl_dump_file, "\n");
5636 /* Add it to the chain of fixes. */
5639 if (minipool_fix_head != NULL)
5640 minipool_fix_tail->next = fix;
5642 minipool_fix_head = fix;
5644 minipool_fix_tail = fix;
5647 /* Scan INSN and note any of its operands that need fixing. */
5649 note_invalid_constants (insn, address)
5651 HOST_WIDE_INT address;
5655 extract_insn (insn);
5657 if (!constrain_operands (1))
5658 fatal_insn_not_found (insn);
5660 /* Fill in recog_op_alt with information about the constraints of this
5662 preprocess_constraints ();
5664 for (opno = 0; opno < recog_data.n_operands; opno++)
5666 /* Things we need to fix can only occur in inputs. */
5667 if (recog_data.operand_type[opno] != OP_IN)
5670 /* If this alternative is a memory reference, then any mention
5671 of constants in this alternative is really to fool reload
5672 into allowing us to accept one there. We need to fix them up
5673 now so that we output the right code. */
5674 if (recog_op_alt[opno][which_alternative].memory_ok)
5676 rtx op = recog_data.operand[opno];
5678 if (CONSTANT_P (op))
5679 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5680 recog_data.operand_mode[opno], op);
5682 /* RWE: Now we look correctly at the operands for the insn,
5683 this shouldn't be needed any more. */
5684 #ifndef AOF_ASSEMBLER
5685 /* XXX Is this still needed? */
5686 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
5687 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5688 recog_data.operand_mode[opno],
5689 XVECEXP (op, 0, 0));
5692 else if (GET_CODE (op) == MEM
5693 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5694 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
5695 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5696 recog_data.operand_mode[opno],
5697 get_pool_constant (XEXP (op, 0)));
5707 HOST_WIDE_INT address = 0;
5710 minipool_fix_head = minipool_fix_tail = NULL;
5712 /* The first insn must always be a note, or the code below won't
5713 scan it properly. */
5714 if (GET_CODE (first) != NOTE)
5717 /* Scan all the insns and record the operands that will need fixing. */
5718 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
5720 if (GET_CODE (insn) == BARRIER)
5721 push_minipool_barrier (insn, address);
5722 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
5723 || GET_CODE (insn) == JUMP_INSN)
5727 note_invalid_constants (insn, address);
5728 address += get_attr_length (insn);
5730 /* If the insn is a vector jump, add the size of the table
5731 and skip the table. */
5732 if ((table = is_jump_table (insn)) != NULL)
5734 address += get_jump_table_size (table);
5740 fix = minipool_fix_head;
5742 /* Now scan the fixups and perform the required changes. */
5747 Mfix * last_added_fix;
5748 Mfix * last_barrier = NULL;
5751 /* Skip any further barriers before the next fix. */
5752 while (fix && GET_CODE (fix->insn) == BARRIER)
5755 /* No more fixes. */
5759 last_added_fix = NULL;
5761 for (ftmp = fix; ftmp; ftmp = ftmp->next)
5763 if (GET_CODE (ftmp->insn) == BARRIER)
5765 if (ftmp->address >= minipool_vector_head->max_address)
5768 last_barrier = ftmp;
5770 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
5773 last_added_fix = ftmp; /* Keep track of the last fix added. */
5776 /* If we found a barrier, drop back to that; any fixes that we
5777 could have reached but come after the barrier will now go in
5778 the next mini-pool. */
5779 if (last_barrier != NULL)
5781 /* Reduce the refcount for those fixes that won't go into this
5783 for (fdel = last_barrier->next;
5784 fdel && fdel != ftmp;
5787 fdel->minipool->refcount--;
5788 fdel->minipool = NULL;
5791 ftmp = last_barrier;
5795 /* ftmp is first fix that we can't fit into this pool and
5796 there no natural barriers that we could use. Insert a
5797 new barrier in the code somewhere between the previous
5798 fix and this one, and arrange to jump around it. */
5799 HOST_WIDE_INT max_address;
5801 /* The last item on the list of fixes must be a barrier, so
5802 we can never run off the end of the list of fixes without
5803 last_barrier being set. */
5807 max_address = minipool_vector_head->max_address;
5808 /* Check that there isn't another fix that is in range that
5809 we couldn't fit into this pool because the pool was
5810 already too large: we need to put the pool before such an
5812 if (ftmp->address < max_address)
5813 max_address = ftmp->address;
5815 last_barrier = create_fix_barrier (last_added_fix, max_address);
5818 assign_minipool_offsets (last_barrier);
5822 if (GET_CODE (ftmp->insn) != BARRIER
5823 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
5830 /* Scan over the fixes we have identified for this pool, fixing them
5831 up and adding the constants to the pool itself. */
5832 for (this_fix = fix; this_fix && ftmp != this_fix;
5833 this_fix = this_fix->next)
5834 if (GET_CODE (this_fix->insn) != BARRIER)
5837 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
5838 minipool_vector_label),
5839 this_fix->minipool->offset);
5840 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
5843 dump_minipool (last_barrier->insn);
5847 /* From now on we must synthesize any constants that we can't handle
5848 directly. This can happen if the RTL gets split during final
5849 instruction generation. */
5850 after_arm_reorg = 1;
5852 /* Free the minipool memory. */
5853 obstack_free (&minipool_obstack, minipool_startobj);
5856 /* Routines to output assembly language. */
5858 /* If the rtx is the correct value then return the string of the number.
5859 In this way we can ensure that valid double constants are generated even
5860 when cross compiling. */
5862 fp_immediate_constant (x)
5868 if (!fpa_consts_inited)
5871 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5872 for (i = 0; i < 8; i++)
5873 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
5874 return strings_fpa[i];
5879 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
5881 fp_const_from_val (r)
5882 REAL_VALUE_TYPE * r;
5886 if (!fpa_consts_inited)
5889 for (i = 0; i < 8; i++)
5890 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
5891 return strings_fpa[i];
5896 /* Output the operands of a LDM/STM instruction to STREAM.
5897 MASK is the ARM register set mask of which only bits 0-15 are important.
5898 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
5899 must follow the register list. */
5902 print_multi_reg (stream, instr, reg, mask, hat)
5910 int not_first = FALSE;
5912 fputc ('\t', stream);
5913 asm_fprintf (stream, instr, reg);
5914 fputs (", {", stream);
5916 for (i = 0; i <= LAST_ARM_REGNUM; i++)
5917 if (mask & (1 << i))
5920 fprintf (stream, ", ");
5922 asm_fprintf (stream, "%r", i);
5926 fprintf (stream, "}%s\n", hat ? "^" : "");
5929 /* Output a 'call' insn. */
5932 output_call (operands)
5935 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
5937 if (REGNO (operands[0]) == LR_REGNUM)
5939 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
5940 output_asm_insn ("mov%?\t%0, %|lr", operands);
5943 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
5945 if (TARGET_INTERWORK)
5946 output_asm_insn ("bx%?\t%0", operands);
5948 output_asm_insn ("mov%?\t%|pc, %0", operands);
5957 int something_changed = 0;
5959 int code = GET_CODE (x0);
5961 register const char * fmt;
5966 if (REGNO (x0) == LR_REGNUM)
5968 *x = gen_rtx_REG (SImode, IP_REGNUM);
5973 /* Scan through the sub-elements and change any references there. */
5974 fmt = GET_RTX_FORMAT (code);
5976 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5978 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
5979 else if (fmt[i] == 'E')
5980 for (j = 0; j < XVECLEN (x0, i); j++)
5981 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
5983 return something_changed;
5987 /* Output a 'call' insn that is a reference in memory. */
5990 output_call_mem (operands)
5993 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
5994 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
5995 if (eliminate_lr2ip (&operands[0]))
5996 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
5998 if (TARGET_INTERWORK)
6000 output_asm_insn ("ldr%?\t%|ip, %0", operands);
6001 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6002 output_asm_insn ("bx%?\t%|ip", operands);
6006 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6007 output_asm_insn ("ldr%?\t%|pc, %0", operands);
6014 /* Output a move from arm registers to an fpu registers.
6015 OPERANDS[0] is an fpu register.
6016 OPERANDS[1] is the first registers of an arm register pair. */
6019 output_mov_long_double_fpu_from_arm (operands)
6022 int arm_reg0 = REGNO (operands[1]);
6025 if (arm_reg0 == IP_REGNUM)
6028 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6029 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6030 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6032 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
6033 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
6038 /* Output a move from an fpu register to arm registers.
6039 OPERANDS[0] is the first registers of an arm register pair.
6040 OPERANDS[1] is an fpu register. */
6043 output_mov_long_double_arm_from_fpu (operands)
6046 int arm_reg0 = REGNO (operands[0]);
6049 if (arm_reg0 == IP_REGNUM)
6052 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6053 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6054 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6056 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
6057 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
6061 /* Output a move from arm registers to arm registers of a long double
6062 OPERANDS[0] is the destination.
6063 OPERANDS[1] is the source. */
6065 output_mov_long_double_arm_from_arm (operands)
6068 /* We have to be careful here because the two might overlap. */
6069 int dest_start = REGNO (operands[0]);
6070 int src_start = REGNO (operands[1]);
6074 if (dest_start < src_start)
6076 for (i = 0; i < 3; i++)
6078 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6079 ops[1] = gen_rtx_REG (SImode, src_start + i);
6080 output_asm_insn ("mov%?\t%0, %1", ops);
6085 for (i = 2; i >= 0; i--)
6087 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6088 ops[1] = gen_rtx_REG (SImode, src_start + i);
6089 output_asm_insn ("mov%?\t%0, %1", ops);
6097 /* Output a move from arm registers to an fpu registers.
6098 OPERANDS[0] is an fpu register.
6099 OPERANDS[1] is the first registers of an arm register pair. */
6102 output_mov_double_fpu_from_arm (operands)
6105 int arm_reg0 = REGNO (operands[1]);
6108 if (arm_reg0 == IP_REGNUM)
6111 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6112 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6113 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
6114 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
6118 /* Output a move from an fpu register to arm registers.
6119 OPERANDS[0] is the first registers of an arm register pair.
6120 OPERANDS[1] is an fpu register. */
6123 output_mov_double_arm_from_fpu (operands)
6126 int arm_reg0 = REGNO (operands[0]);
6129 if (arm_reg0 == IP_REGNUM)
6132 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6133 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6134 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
6135 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
6139 /* Output a move between double words.
6140 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6141 or MEM<-REG and all MEMs must be offsettable addresses. */
6144 output_move_double (operands)
6147 enum rtx_code code0 = GET_CODE (operands[0]);
6148 enum rtx_code code1 = GET_CODE (operands[1]);
6153 int reg0 = REGNO (operands[0]);
6155 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
6159 int reg1 = REGNO (operands[1]);
6160 if (reg1 == IP_REGNUM)
6163 /* Ensure the second source is not overwritten. */
6164 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
6165 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
6167 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
6169 else if (code1 == CONST_DOUBLE)
6171 if (GET_MODE (operands[1]) == DFmode)
6174 union real_extract u;
6176 memcpy (&u, &CONST_DOUBLE_LOW (operands[1]), sizeof (u));
6177 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
6178 otherops[1] = GEN_INT (l[1]);
6179 operands[1] = GEN_INT (l[0]);
6181 else if (GET_MODE (operands[1]) != VOIDmode)
6183 else if (WORDS_BIG_ENDIAN)
6186 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6187 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6192 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6193 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6196 output_mov_immediate (operands);
6197 output_mov_immediate (otherops);
6199 else if (code1 == CONST_INT)
6201 #if HOST_BITS_PER_WIDE_INT > 32
6202 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6203 what the upper word is. */
6204 if (WORDS_BIG_ENDIAN)
6206 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6207 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6211 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6212 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6215 /* Sign extend the intval into the high-order word. */
6216 if (WORDS_BIG_ENDIAN)
6218 otherops[1] = operands[1];
6219 operands[1] = (INTVAL (operands[1]) < 0
6220 ? constm1_rtx : const0_rtx);
6223 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
6225 output_mov_immediate (otherops);
6226 output_mov_immediate (operands);
6228 else if (code1 == MEM)
6230 switch (GET_CODE (XEXP (operands[1], 0)))
6233 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
6237 abort (); /* Should never happen now. */
6241 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
6245 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
6249 abort (); /* Should never happen now. */
6254 output_asm_insn ("adr%?\t%0, %1", operands);
6255 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
6259 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
6260 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
6262 otherops[0] = operands[0];
6263 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
6264 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
6265 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
6267 if (GET_CODE (otherops[2]) == CONST_INT)
6269 switch (INTVAL (otherops[2]))
6272 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
6275 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
6278 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
6281 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
6282 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
6284 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6287 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6290 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
6292 return "ldm%?ia\t%0, %M0";
6296 otherops[1] = adj_offsettable_operand (operands[1], 4);
6297 /* Take care of overlapping base/data reg. */
6298 if (reg_mentioned_p (operands[0], operands[1]))
6300 output_asm_insn ("ldr%?\t%0, %1", otherops);
6301 output_asm_insn ("ldr%?\t%0, %1", operands);
6305 output_asm_insn ("ldr%?\t%0, %1", operands);
6306 output_asm_insn ("ldr%?\t%0, %1", otherops);
6312 abort (); /* Constraints should prevent this. */
6314 else if (code0 == MEM && code1 == REG)
6316 if (REGNO (operands[1]) == IP_REGNUM)
6319 switch (GET_CODE (XEXP (operands[0], 0)))
6322 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
6326 abort (); /* Should never happen now. */
6330 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
6334 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
6338 abort (); /* Should never happen now. */
6342 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
6344 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
6347 output_asm_insn ("stm%?db\t%m0, %M1", operands);
6351 output_asm_insn ("stm%?da\t%m0, %M1", operands);
6355 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
6362 otherops[0] = adj_offsettable_operand (operands[0], 4);
6363 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
6364 output_asm_insn ("str%?\t%1, %0", operands);
6365 output_asm_insn ("str%?\t%1, %0", otherops);
6369 abort (); /* Constraints should prevent this */
6375 /* Output an arbitrary MOV reg, #n.
6376 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6379 output_mov_immediate (operands)
6382 HOST_WIDE_INT n = INTVAL (operands[1]);
6386 /* Try to use one MOV */
6387 if (const_ok_for_arm (n))
6389 output_asm_insn ("mov%?\t%0, %1", operands);
6393 /* Try to use one MVN */
6394 if (const_ok_for_arm (~n))
6396 operands[1] = GEN_INT (~n);
6397 output_asm_insn ("mvn%?\t%0, %1", operands);
6401 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6403 for (i=0; i < 32; i++)
6407 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
6408 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~n);
6410 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
6416 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6417 adding zero to one register, output nothing. */
6420 output_add_immediate (operands)
6423 HOST_WIDE_INT n = INTVAL (operands[2]);
6425 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
6428 output_multi_immediate (operands,
6429 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6432 output_multi_immediate (operands,
6433 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6440 /* Output a multiple immediate operation.
6441 OPERANDS is the vector of operands referred to in the output patterns.
6442 INSTR1 is the output pattern to use for the first constant.
6443 INSTR2 is the output pattern to use for subsequent constants.
6444 IMMED_OP is the index of the constant slot in OPERANDS.
6445 N is the constant value. */
6448 output_multi_immediate (operands, instr1, instr2, immed_op, n)
6450 const char * instr1;
6451 const char * instr2;
6455 #if HOST_BITS_PER_WIDE_INT > 32
6456 n &= HOST_UINT (0xffffffff);
6461 operands[immed_op] = const0_rtx;
6462 output_asm_insn (instr1, operands); /* Quick and easy output. */
6467 const char * instr = instr1;
6469 /* Note that n is never zero here (which would give no output). */
6470 for (i = 0; i < 32; i += 2)
6474 operands[immed_op] = GEN_INT (n & (255 << i));
6475 output_asm_insn (instr, operands);
6486 /* Return the appropriate ARM instruction for the operation code.
6487 The returned result should not be overwritten. OP is the rtx of the
6488 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6492 arithmetic_instr (op, shift_first_arg)
6494 int shift_first_arg;
6496 switch (GET_CODE (op))
6502 return shift_first_arg ? "rsb" : "sub";
6519 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6520 for the operation code. The returned result should not be overwritten.
6521 OP is the rtx code of the shift.
6522 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6526 shift_op (op, amountp)
6528 HOST_WIDE_INT *amountp;
6531 enum rtx_code code = GET_CODE (op);
6533 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
6535 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
6536 *amountp = INTVAL (XEXP (op, 1));
6559 /* We never have to worry about the amount being other than a
6560 power of 2, since this case can never be reloaded from a reg. */
6562 *amountp = int_log2 (*amountp);
6573 /* This is not 100% correct, but follows from the desire to merge
6574 multiplication by a power of 2 with the recognizer for a
6575 shift. >=32 is not a valid shift for "asl", so we must try and
6576 output a shift that produces the correct arithmetical result.
6577 Using lsr #32 is identical except for the fact that the carry bit
6578 is not set correctly if we set the flags; but we never use the
6579 carry bit from such an operation, so we can ignore that. */
6580 if (code == ROTATERT)
6581 *amountp &= 31; /* Rotate is just modulo 32 */
6582 else if (*amountp != (*amountp & 31))
6589 /* Shifts of 0 are no-ops. */
6598 /* Obtain the shift from the POWER of two. */
6599 static HOST_WIDE_INT
6601 HOST_WIDE_INT power;
6603 HOST_WIDE_INT shift = 0;
6605 while ((((HOST_INT (1)) << shift) & power) == 0)
6615 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6616 /bin/as is horribly restrictive. */
6617 #define MAX_ASCII_LEN 51
6620 output_ascii_pseudo_op (stream, p, len)
6622 const unsigned char * p;
6628 fputs ("\t.ascii\t\"", stream);
6630 for (i = 0; i < len; i++)
6632 register int c = p[i];
6634 if (len_so_far >= MAX_ASCII_LEN)
6636 fputs ("\"\n\t.ascii\t\"", stream);
6643 fputs ("\\t", stream);
6648 fputs ("\\f", stream);
6653 fputs ("\\b", stream);
6658 fputs ("\\r", stream);
6662 case TARGET_NEWLINE:
6663 fputs ("\\n", stream);
6665 if ((c >= ' ' && c <= '~')
6667 /* This is a good place for a line break. */
6668 len_so_far = MAX_ASCII_LEN;
6675 putc ('\\', stream);
6680 if (c >= ' ' && c <= '~')
6687 fprintf (stream, "\\%03o", c);
6694 fputs ("\"\n", stream);
6699 output_return_instruction (operand, really_return, reverse)
6705 int reg, live_regs = 0;
6706 int volatile_func = arm_volatile_func ();
6708 /* If a function is naked, don't use the "return" insn. */
6709 if (arm_naked_function_p (current_function_decl))
6712 return_used_this_function = 1;
6714 if (TARGET_ABORT_NORETURN && volatile_func)
6716 /* If this function was declared non-returning, and we have found a tail
6717 call, then we have to trust that the called function won't return. */
6722 /* Otherwise, trap an attempted return by aborting. */
6724 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
6726 assemble_external_libcall (ops[1]);
6727 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
6733 if (current_function_calls_alloca && !really_return)
6736 for (reg = 0; reg <= 10; reg++)
6737 if (regs_ever_live[reg] && !call_used_regs[reg])
6740 if (!TARGET_APCS_FRAME
6741 && !frame_pointer_needed
6742 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
6743 && !call_used_regs[HARD_FRAME_POINTER_REGNUM])
6746 if (flag_pic && !TARGET_SINGLE_PIC_BASE
6747 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6750 if (live_regs || regs_ever_live[LR_REGNUM])
6753 if (frame_pointer_needed)
6756 /* On some ARM architectures it is faster to use LDR rather than LDM to
6757 load a single register. On other architectures, the cost is the same. */
6759 && regs_ever_live[LR_REGNUM]
6761 output_asm_insn (reverse ? "ldr%?%D0\t%|lr, [%|sp], #4"
6762 : "ldr%?%d0\t%|lr, [%|sp], #4", &operand);
6763 else if (live_regs == 1
6764 && regs_ever_live[LR_REGNUM]
6766 output_asm_insn (reverse ? "ldr%?%D0\t%|pc, [%|sp], #4"
6767 : "ldr%?%d0\t%|pc, [%|sp], #4", &operand);
6770 if (!regs_ever_live[LR_REGNUM])
6773 if (frame_pointer_needed)
6775 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
6778 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
6780 for (reg = 0; reg <= 10; reg++)
6781 if (regs_ever_live[reg]
6782 && (!call_used_regs[reg]
6783 || (flag_pic && !TARGET_SINGLE_PIC_BASE
6784 && reg == PIC_OFFSET_TABLE_REGNUM)))
6786 strcat (instr, "%|");
6787 strcat (instr, reg_names[reg]);
6789 strcat (instr, ", ");
6792 if (frame_pointer_needed)
6794 strcat (instr, "%|");
6795 strcat (instr, reg_names[11]);
6796 strcat (instr, ", ");
6797 strcat (instr, "%|");
6798 strcat (instr, reg_names[13]);
6799 strcat (instr, ", ");
6800 strcat (instr, "%|");
6801 strcat (instr, TARGET_INTERWORK || (!really_return)
6802 ? reg_names[LR_REGNUM] : reg_names[PC_REGNUM] );
6806 if (!TARGET_APCS_FRAME
6807 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
6808 && !call_used_regs[HARD_FRAME_POINTER_REGNUM])
6810 strcat (instr, "%|");
6811 strcat (instr, reg_names[HARD_FRAME_POINTER_REGNUM]);
6812 strcat (instr, ", ");
6815 strcat (instr, "%|");
6817 if (TARGET_INTERWORK && really_return)
6818 strcat (instr, reg_names[IP_REGNUM]);
6820 strcat (instr, really_return ? reg_names[PC_REGNUM] : reg_names[LR_REGNUM]);
6823 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
6824 output_asm_insn (instr, &operand);
6826 if (TARGET_INTERWORK && really_return)
6828 strcpy (instr, "bx%?");
6829 strcat (instr, reverse ? "%D0" : "%d0");
6830 strcat (instr, "\t%|");
6831 strcat (instr, frame_pointer_needed ? "lr" : "ip");
6833 output_asm_insn (instr, &operand);
6836 else if (really_return)
6838 if (TARGET_INTERWORK)
6839 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
6841 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
6842 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
6844 output_asm_insn (instr, &operand);
6850 /* Return nonzero if optimizing and the current function is volatile.
6851 Such functions never return, and many memory cycles can be saved
6852 by not storing register values that will never be needed again.
6853 This optimization was added to speed up context switching in a
6854 kernel application. */
6856 arm_volatile_func ()
6858 return (optimize > 0
6859 && current_function_nothrow
6860 && TREE_THIS_VOLATILE (current_function_decl));
6863 /* Write the function name into the code section, directly preceding
6864 the function prologue.
6866 Code will be output similar to this:
6868 .ascii "arm_poke_function_name", 0
6871 .word 0xff000000 + (t1 - t0)
6872 arm_poke_function_name
6874 stmfd sp!, {fp, ip, lr, pc}
6877 When performing a stack backtrace, code can inspect the value
6878 of 'pc' stored at 'fp' + 0. If the trace function then looks
6879 at location pc - 12 and the top 8 bits are set, then we know
6880 that there is a function name embedded immediately preceding this
6881 location and has length ((pc[-3]) & 0xff000000).
6883 We assume that pc is declared as a pointer to an unsigned long.
6885 It is of no benefit to output the function name if we are assembling
6886 a leaf function. These function types will not contain a stack
6887 backtrace structure, therefore it is not possible to determine the
6891 arm_poke_function_name (stream, name)
6895 unsigned long alignlength;
6896 unsigned long length;
6899 length = strlen (name) + 1;
6900 alignlength = ROUND_UP (length);
6902 ASM_OUTPUT_ASCII (stream, name, length);
6903 ASM_OUTPUT_ALIGN (stream, 2);
6904 x = GEN_INT (HOST_UINT(0xff000000) + alignlength);
6905 ASM_OUTPUT_INT (stream, x);
6908 /* The amount of stack adjustment that happens here, in output_return and in
6909 output_epilogue must be exactly the same as was calculated during reload,
6910 or things will point to the wrong place. The only time we can safely
6911 ignore this constraint is when a function has no arguments on the stack,
6912 no stack frame requirement and no live registers execpt for `lr'. If we
6913 can guarantee that by making all function calls into tail calls and that
6914 lr is not clobbered in any other way, then there is no need to push lr
6917 output_arm_prologue (f, frame_size)
6921 int reg, live_regs_mask = 0;
6922 int volatile_func = arm_volatile_func ();
6924 /* Nonzero if we must stuff some register arguments onto the stack as if
6925 they were passed there. */
6926 int store_arg_regs = 0;
6928 if (arm_ccfsm_state || arm_target_insn)
6929 abort (); /* Sanity check. */
6931 if (arm_naked_function_p (current_function_decl))
6934 return_used_this_function = 0;
6936 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
6937 current_function_args_size,
6938 current_function_pretend_args_size, frame_size);
6939 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
6940 frame_pointer_needed,
6941 current_function_anonymous_args);
6944 asm_fprintf (f, "\t%@ Volatile function.\n");
6946 if (current_function_needs_context)
6947 asm_fprintf (f, "\t%@ Nested function.\n");
6949 if (current_function_anonymous_args && current_function_pretend_args_size)
6952 for (reg = 0; reg <= 10; reg++)
6953 if (regs_ever_live[reg] && !call_used_regs[reg])
6954 live_regs_mask |= (1 << reg);
6956 if (!TARGET_APCS_FRAME
6957 && !frame_pointer_needed
6958 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
6959 && !call_used_regs[HARD_FRAME_POINTER_REGNUM])
6960 live_regs_mask |= (1 << HARD_FRAME_POINTER_REGNUM);
6962 if (flag_pic && !TARGET_SINGLE_PIC_BASE
6963 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6964 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
6966 if (frame_pointer_needed)
6967 live_regs_mask |= 0xD800;
6968 else if (regs_ever_live[LR_REGNUM])
6970 live_regs_mask |= 1 << LR_REGNUM;
6974 /* If a di mode load/store multiple is used, and the base register
6975 is r3, then r4 can become an ever live register without lr
6976 doing so, in this case we need to push lr as well, or we
6977 will fail to get a proper return. */
6978 live_regs_mask |= 1 << LR_REGNUM;
6980 #ifdef AOF_ASSEMBLER
6982 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
6987 arm_output_epilogue (really_return)
6991 int live_regs_mask = 0;
6992 /* If we need this, then it will always be at least this much. */
6993 int floats_offset = 12;
6995 int frame_size = get_frame_size ();
6996 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
6997 FILE * f = asm_out_file;
6998 int volatile_func = arm_volatile_func ();
7001 if (use_return_insn (FALSE) && return_used_this_function)
7004 /* Naked functions don't have epilogues. */
7005 if (arm_naked_function_p (current_function_decl))
7008 /* If we are throwing an exception, the address we want to jump to is in
7009 R1; otherwise, it's in LR. */
7010 return_regnum = eh_ofs ? 2 : LR_REGNUM;
7012 /* If we are throwing an exception, then we really must be doing a return,
7013 so we can't tail-call. */
7014 if (eh_ofs && !really_return)
7017 /* A volatile function should never return. Call abort. */
7018 if (TARGET_ABORT_NORETURN && volatile_func)
7021 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
7022 assemble_external_libcall (op);
7023 output_asm_insn ("bl\t%a0", &op);
7027 for (reg = 0; reg <= 10; reg++)
7028 if (regs_ever_live[reg] && !call_used_regs[reg])
7030 live_regs_mask |= (1 << reg);
7034 /* Handle the frame pointer as a special case. */
7035 if (!TARGET_APCS_FRAME
7036 && !frame_pointer_needed
7037 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7038 && !call_used_regs[HARD_FRAME_POINTER_REGNUM])
7040 live_regs_mask |= (1 << HARD_FRAME_POINTER_REGNUM);
7044 /* If we aren't loading the PIC register, don't stack it even though it may
7046 if (flag_pic && !TARGET_SINGLE_PIC_BASE
7047 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7049 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
7053 if (frame_pointer_needed)
7055 if (arm_fpu_arch == FP_SOFT2)
7057 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7058 if (regs_ever_live[reg] && !call_used_regs[reg])
7060 floats_offset += 12;
7061 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
7062 reg, FP_REGNUM, floats_offset);
7067 int start_reg = LAST_ARM_FP_REGNUM;
7069 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7071 if (regs_ever_live[reg] && !call_used_regs[reg])
7073 floats_offset += 12;
7075 /* We can't unstack more than four registers at once. */
7076 if (start_reg - reg == 3)
7078 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
7079 reg, FP_REGNUM, floats_offset);
7080 start_reg = reg - 1;
7085 if (reg != start_reg)
7086 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7087 reg + 1, start_reg - reg,
7088 FP_REGNUM, floats_offset);
7089 start_reg = reg - 1;
7093 /* Just in case the last register checked also needs unstacking. */
7094 if (reg != start_reg)
7095 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7096 reg + 1, start_reg - reg,
7097 FP_REGNUM, floats_offset);
7100 if (TARGET_INTERWORK)
7102 live_regs_mask |= 0x6800;
7103 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
7105 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7108 asm_fprintf (f, "\tbx\t%r\n", return_regnum);
7110 else if (eh_ofs || !really_return)
7112 live_regs_mask |= 0x6800;
7113 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
7116 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7118 /* Even in 26-bit mode we do a mov (rather than a movs)
7119 because we don't have the PSR bits set in the
7121 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, return_regnum);
7126 live_regs_mask |= 0xA800;
7127 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask,
7128 TARGET_APCS_32 ? FALSE : TRUE);
7133 /* Restore stack pointer if necessary. */
7134 if (frame_size + current_function_outgoing_args_size != 0)
7136 operands[0] = operands[1] = stack_pointer_rtx;
7137 operands[2] = GEN_INT (frame_size
7138 + current_function_outgoing_args_size);
7139 output_add_immediate (operands);
7142 if (arm_fpu_arch == FP_SOFT2)
7144 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7145 if (regs_ever_live[reg] && !call_used_regs[reg])
7146 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
7151 int start_reg = FIRST_ARM_FP_REGNUM;
7153 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7155 if (regs_ever_live[reg] && !call_used_regs[reg])
7157 if (reg - start_reg == 3)
7159 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
7160 start_reg, SP_REGNUM);
7161 start_reg = reg + 1;
7166 if (reg != start_reg)
7167 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7168 start_reg, reg - start_reg,
7171 start_reg = reg + 1;
7175 /* Just in case the last register checked also needs unstacking. */
7176 if (reg != start_reg)
7177 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7178 start_reg, reg - start_reg, SP_REGNUM);
7181 if (current_function_pretend_args_size == 0 && regs_ever_live[LR_REGNUM])
7183 if (TARGET_INTERWORK)
7185 live_regs_mask |= 1 << LR_REGNUM;
7187 /* Handle LR on its own. */
7188 if (live_regs_mask == (1 << LR_REGNUM))
7191 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM,
7194 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM,
7197 else if (live_regs_mask != 0)
7198 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask,
7202 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7206 asm_fprintf (f, "\tbx\t%r\n", return_regnum);
7210 if (live_regs_mask == 0)
7211 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
7213 print_multi_reg (f, "\tldmfd\t%r!", SP_REGNUM,
7214 live_regs_mask | (1 << LR_REGNUM), FALSE);
7216 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7218 /* Jump to the target; even in 26-bit mode. */
7219 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, return_regnum);
7221 else if (TARGET_APCS_32 && live_regs_mask == 0 && !really_return)
7222 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
7223 else if (TARGET_APCS_32 && live_regs_mask == 0 && really_return)
7224 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", PC_REGNUM, SP_REGNUM);
7225 else if (!really_return)
7226 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM,
7227 live_regs_mask | (1 << LR_REGNUM), FALSE);
7229 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM,
7230 live_regs_mask | (1 << PC_REGNUM),
7231 TARGET_APCS_32 ? FALSE : TRUE);
7235 if (live_regs_mask || regs_ever_live[LR_REGNUM])
7237 /* Restore the integer regs, and the return address into lr. */
7238 live_regs_mask |= 1 << LR_REGNUM;
7240 if (live_regs_mask == (1 << LR_REGNUM))
7243 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM,
7246 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM,
7249 else if (live_regs_mask != 0)
7250 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask,
7254 if (current_function_pretend_args_size)
7256 /* Unwind the pre-pushed regs. */
7257 operands[0] = operands[1] = stack_pointer_rtx;
7258 operands[2] = GEN_INT (current_function_pretend_args_size);
7259 output_add_immediate (operands);
7263 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7268 /* And finally, go home. */
7269 if (TARGET_INTERWORK)
7270 asm_fprintf (f, "\tbx\t%r\n", return_regnum);
7271 else if (TARGET_APCS_32 || eh_ofs)
7272 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, return_regnum);
7274 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, return_regnum);
7283 output_func_epilogue (frame_size)
7288 /* ??? Probably not safe to set this here, since it assumes that a
7289 function will be emitted as assembly immediately after we generate
7290 RTL for it. This does not happen for inline functions. */
7291 return_used_this_function = 0;
7295 if (use_return_insn (FALSE)
7296 && return_used_this_function
7297 && (frame_size + current_function_outgoing_args_size) != 0
7298 && !frame_pointer_needed)
7301 /* Reset the ARM-specific per-function variables. */
7302 current_function_anonymous_args = 0;
7303 after_arm_reorg = 0;
7307 /* Generate and emit an insn that we will recognize as a push_multi.
7308 Unfortunately, since this insn does not reflect very well the actual
7309 semantics of the operation, we need to annotate the insn for the benefit
7310 of DWARF2 frame unwind information. */
7312 emit_multi_reg_push (mask)
7319 int dwarf_par_index;
7322 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7323 if (mask & (1 << i))
7326 if (num_regs == 0 || num_regs > 16)
7329 /* For the body of the insn we are going to generate an UNSPEC in
7330 parallel with several USEs. This allows the insn to be recognised
7331 by the push_multi pattern in the arm.md file. The insn looks
7332 something like this:
7335 (set (mem:BLK (pre_dec:BLK (reg:SI sp))) (unspec:BLK [(reg:SI r4)] 2))
7336 (use (reg:SI 11 fp))
7337 (use (reg:SI 12 ip))
7338 (use (reg:SI 14 lr))
7339 (use (reg:SI 15 pc))
7342 For the frame note however, we try to be more explicit and actually
7343 show each register being stored into the stack frame, plus a (single)
7344 decrement of the stack pointer. We do it this way in order to be
7345 friendly to the stack unwinding code, which only wants to see a single
7346 stack decrement per instruction. The RTL we generate for the note looks
7347 something like this:
7350 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7351 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7352 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7353 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7354 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7355 (set (mem:SI (plus:SI (reg:SI sp) (const_int 16))) (reg:SI pc))
7358 This sequence is used both by the code to support stack unwinding for
7359 exceptions handlers and the code to generate dwarf2 frame debugging. */
7361 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
7362 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1));
7363 RTX_FRAME_RELATED_P (dwarf) = 1;
7364 dwarf_par_index = 1;
7366 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7368 if (mask & (1 << i))
7370 reg = gen_rtx_REG (SImode, i);
7373 = gen_rtx_SET (VOIDmode,
7374 gen_rtx_MEM (BLKmode,
7375 gen_rtx_PRE_DEC (BLKmode,
7376 stack_pointer_rtx)),
7377 gen_rtx_UNSPEC (BLKmode,
7381 tmp = gen_rtx_SET (VOIDmode,
7382 gen_rtx_MEM (SImode, stack_pointer_rtx),
7384 RTX_FRAME_RELATED_P (tmp) = 1;
7385 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
7392 for (j = 1, i++; j < num_regs; i++)
7394 if (mask & (1 << i))
7396 reg = gen_rtx_REG (SImode, i);
7398 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
7400 tmp = gen_rtx_SET (VOIDmode,
7401 gen_rtx_MEM (SImode,
7402 gen_rtx_PLUS (SImode,
7406 RTX_FRAME_RELATED_P (tmp) = 1;
7407 XVECEXP (dwarf, 0, dwarf_par_index ++) = tmp;
7413 par = emit_insn (par);
7415 tmp = gen_rtx_SET (SImode,
7417 gen_rtx_PLUS (SImode,
7419 GEN_INT (-4 * num_regs)));
7420 RTX_FRAME_RELATED_P (tmp) = 1;
7421 XVECEXP (dwarf, 0, 0) = tmp;
7423 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7429 emit_sfm (base_reg, count)
7438 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7439 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7440 RTX_FRAME_RELATED_P (dwarf) = 1;
7442 reg = gen_rtx_REG (XFmode, base_reg++);
7445 = gen_rtx_SET (VOIDmode,
7446 gen_rtx_MEM (BLKmode,
7447 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7448 gen_rtx_UNSPEC (BLKmode,
7452 = gen_rtx_SET (VOIDmode,
7453 gen_rtx_MEM (XFmode,
7454 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7456 RTX_FRAME_RELATED_P (tmp) = 1;
7457 XVECEXP (dwarf, 0, count - 1) = tmp;
7459 for (i = 1; i < count; i++)
7461 reg = gen_rtx_REG (XFmode, base_reg++);
7462 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7464 tmp = gen_rtx_SET (VOIDmode,
7465 gen_rtx_MEM (XFmode,
7466 gen_rtx_PRE_DEC (BLKmode,
7467 stack_pointer_rtx)),
7469 RTX_FRAME_RELATED_P (tmp) = 1;
7470 XVECEXP (dwarf, 0, count - i - 1) = tmp;
7473 par = emit_insn (par);
7474 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7480 arm_expand_prologue ()
7483 rtx amount = GEN_INT (-(get_frame_size ()
7484 + current_function_outgoing_args_size));
7485 int live_regs_mask = 0;
7486 int store_arg_regs = 0;
7487 /* If this function doesn't return, then there is no need to push
7488 the call-saved regs. */
7489 int volatile_func = arm_volatile_func ();
7495 /* Naked functions don't have prologues. */
7496 if (arm_naked_function_p (current_function_decl))
7499 if (current_function_anonymous_args && current_function_pretend_args_size)
7504 for (reg = 0; reg <= 10; reg++)
7505 if (regs_ever_live[reg] && !call_used_regs[reg])
7506 live_regs_mask |= 1 << reg;
7508 if (!TARGET_APCS_FRAME
7509 && !frame_pointer_needed
7510 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7511 && !call_used_regs[HARD_FRAME_POINTER_REGNUM])
7512 live_regs_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
7514 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7515 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
7517 if (regs_ever_live[LR_REGNUM])
7518 live_regs_mask |= 1 << LR_REGNUM;
7521 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
7523 if (frame_pointer_needed)
7525 if (current_function_needs_context)
7527 /* The Static chain register is the same as the IP register
7528 used as a scratch register during stack frame creation.
7529 To get around this need to find somewhere to store IP
7530 whilst the frame is being created. We try the following
7533 1. An unused argument register.
7534 2. A slot on the stack above the frame. (This only
7535 works if the function is not a varargs function).
7537 If neither of these places is available, we abort (for now). */
7538 if (regs_ever_live[3] == 0)
7540 insn = gen_rtx_REG (SImode, 3);
7541 insn = gen_rtx_SET (SImode, insn, ip_rtx);
7542 insn = emit_insn (insn);
7543 RTX_FRAME_RELATED_P (insn) = 1;
7545 else if (current_function_pretend_args_size == 0)
7547 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
7548 insn = gen_rtx_MEM (SImode, insn);
7549 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
7550 insn = emit_insn (insn);
7551 RTX_FRAME_RELATED_P (insn) = 1;
7555 /* FIXME - the way to handle this situation is to allow
7556 the pretend args to be dumped onto the stack, then
7557 reuse r3 to save IP. This would involve moving the
7558 copying os SP into IP until after the pretend args
7559 have been dumped, but this is not too hard. */
7560 error ("Unable to find a temporary location for static chanin register");
7563 live_regs_mask |= 0xD800;
7567 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
7568 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7571 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
7573 insn = emit_insn (insn);
7574 RTX_FRAME_RELATED_P (insn) = 1;
7577 if (current_function_pretend_args_size)
7580 insn = emit_multi_reg_push
7581 ((0xf0 >> (current_function_pretend_args_size / 4)) & 0xf);
7584 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7585 GEN_INT (-current_function_pretend_args_size)));
7586 RTX_FRAME_RELATED_P (insn) = 1;
7591 /* If we have to push any regs, then we must push lr as well, or
7592 we won't get a proper return. */
7593 live_regs_mask |= 1 << LR_REGNUM;
7594 insn = emit_multi_reg_push (live_regs_mask);
7595 RTX_FRAME_RELATED_P (insn) = 1;
7598 /* For now the integer regs are still pushed in output_arm_epilogue (). */
7602 if (arm_fpu_arch == FP_SOFT2)
7604 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
7605 if (regs_ever_live[reg] && !call_used_regs[reg])
7607 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
7608 insn = gen_rtx_MEM (XFmode, insn);
7609 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
7610 gen_rtx_REG (XFmode, reg)));
7611 RTX_FRAME_RELATED_P (insn) = 1;
7616 int start_reg = LAST_ARM_FP_REGNUM;
7618 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
7620 if (regs_ever_live[reg] && !call_used_regs[reg])
7622 if (start_reg - reg == 3)
7624 insn = emit_sfm (reg, 4);
7625 RTX_FRAME_RELATED_P (insn) = 1;
7626 start_reg = reg - 1;
7631 if (start_reg != reg)
7633 insn = emit_sfm (reg + 1, start_reg - reg);
7634 RTX_FRAME_RELATED_P (insn) = 1;
7636 start_reg = reg - 1;
7640 if (start_reg != reg)
7642 insn = emit_sfm (reg + 1, start_reg - reg);
7643 RTX_FRAME_RELATED_P (insn) = 1;
7648 if (frame_pointer_needed)
7650 insn = GEN_INT (-(4 + current_function_pretend_args_size + fp_offset));
7651 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
7652 RTX_FRAME_RELATED_P (insn) = 1;
7654 if (current_function_needs_context)
7656 /* Recover the static chain register. */
7657 if (regs_ever_live [3] == 0)
7659 insn = gen_rtx_REG (SImode, 3);
7660 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7661 insn = emit_insn (insn);
7662 RTX_FRAME_RELATED_P (insn) = 1;
7664 else /* if (current_function_pretend_args_size == 0) */
7666 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4));
7667 insn = gen_rtx_MEM (SImode, insn);
7668 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7669 insn = emit_insn (insn);
7670 RTX_FRAME_RELATED_P (insn) = 1;
7675 if (amount != const0_rtx)
7677 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7679 RTX_FRAME_RELATED_P (insn) = 1;
7681 /* If the frame pointer is needed, emit a special barrier that
7682 will prevent the scheduler from moving stores to the frame
7683 before the stack adjustment. */
7684 if (frame_pointer_needed)
7686 rtx unspec = gen_rtx_UNSPEC (SImode,
7687 gen_rtvec (2, stack_pointer_rtx,
7688 hard_frame_pointer_rtx), 4);
7690 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7691 gen_rtx_MEM (BLKmode, unspec)));
7695 /* If we are profiling, make sure no instructions are scheduled before
7696 the call to mcount. Similarly if the user has requested no
7697 scheduling in the prolog. */
7698 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
7699 emit_insn (gen_blockage ());
7702 /* If CODE is 'd', then the X is a condition operand and the instruction
7703 should only be executed if the condition is true.
7704 if CODE is 'D', then the X is a condition operand and the instruction
7705 should only be executed if the condition is false: however, if the mode
7706 of the comparison is CCFPEmode, then always execute the instruction -- we
7707 do this because in these circumstances !GE does not necessarily imply LT;
7708 in these cases the instruction pattern will take care to make sure that
7709 an instruction containing %d will follow, thereby undoing the effects of
7710 doing this instruction unconditionally.
7711 If CODE is 'N' then X is a floating point operand that must be negated
7713 If CODE is 'B' then output a bitwise inverted value of X (a const int).
7714 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
7717 arm_print_operand (stream, x, code)
7725 fputs (ASM_COMMENT_START, stream);
7729 fputs (user_label_prefix, stream);
7733 fputs (REGISTER_PREFIX, stream);
7737 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
7739 if (TARGET_THUMB || current_insn_predicate != NULL)
7742 fputs (arm_condition_codes[arm_current_cc], stream);
7744 else if (current_insn_predicate)
7746 enum arm_cond_code code;
7751 code = get_arm_condition_code (current_insn_predicate);
7752 fputs (arm_condition_codes[code], stream);
7759 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7760 r = REAL_VALUE_NEGATE (r);
7761 fprintf (stream, "%s", fp_const_from_val (&r));
7766 if (GET_CODE (x) == CONST_INT)
7769 val = ARM_SIGN_EXTEND (~INTVAL (x));
7770 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
7775 output_addr_const (stream, x);
7780 fprintf (stream, "%s", arithmetic_instr (x, 1));
7784 fprintf (stream, "%s", arithmetic_instr (x, 0));
7790 const char * shift = shift_op (x, &val);
7794 fprintf (stream, ", %s ", shift_op (x, &val));
7796 arm_print_operand (stream, XEXP (x, 1), 0);
7799 fputc ('#', stream);
7800 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
7806 /* An explanation of the 'Q', 'R' and 'H' register operands:
7808 In a pair of registers containing a DI or DF value the 'Q'
7809 operand returns the register number of the register containing
7810 the least signficant part of the value. The 'R' operand returns
7811 the register number of the register containing the most
7812 significant part of the value.
7814 The 'H' operand returns the higher of the two register numbers.
7815 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
7816 same as the 'Q' operand, since the most signficant part of the
7817 value is held in the lower number register. The reverse is true
7818 on systems where WORDS_BIG_ENDIAN is false.
7820 The purpose of these operands is to distinguish between cases
7821 where the endian-ness of the values is important (for example
7822 when they are added together), and cases where the endian-ness
7823 is irrelevant, but the order of register operations is important.
7824 For example when loading a value from memory into a register
7825 pair, the endian-ness does not matter. Provided that the value
7826 from the lower memory address is put into the lower numbered
7827 register, and the value from the higher address is put into the
7828 higher numbered register, the load will work regardless of whether
7829 the value being loaded is big-wordian or little-wordian. The
7830 order of the two register loads can matter however, if the address
7831 of the memory location is actually held in one of the registers
7832 being overwritten by the load. */
7834 if (REGNO (x) > LAST_ARM_REGNUM)
7836 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
7840 if (REGNO (x) > LAST_ARM_REGNUM)
7842 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
7846 if (REGNO (x) > LAST_ARM_REGNUM)
7848 asm_fprintf (stream, "%r", REGNO (x) + 1);
7852 asm_fprintf (stream, "%r",
7853 GET_CODE (XEXP (x, 0)) == REG
7854 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
7858 asm_fprintf (stream, "{%r-%r}",
7860 REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
7868 fputs (arm_condition_codes[get_arm_condition_code (x)],
7871 fputs (thumb_condition_code (x, 0), stream);
7879 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
7880 (get_arm_condition_code (x))],
7883 fputs (thumb_condition_code (x, 1), stream);
7890 if (GET_CODE (x) == REG)
7891 asm_fprintf (stream, "%r", REGNO (x));
7892 else if (GET_CODE (x) == MEM)
7894 output_memory_reference_mode = GET_MODE (x);
7895 output_address (XEXP (x, 0));
7897 else if (GET_CODE (x) == CONST_DOUBLE)
7898 fprintf (stream, "#%s", fp_immediate_constant (x));
7899 else if (GET_CODE (x) == NEG)
7900 abort (); /* This should never happen now. */
7903 fputc ('#', stream);
7904 output_addr_const (stream, x);
7909 /* A finite state machine takes care of noticing whether or not instructions
7910 can be conditionally executed, and thus decrease execution time and code
7911 size by deleting branch instructions. The fsm is controlled by
7912 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
7914 /* The state of the fsm controlling condition codes are:
7915 0: normal, do nothing special
7916 1: make ASM_OUTPUT_OPCODE not output this instruction
7917 2: make ASM_OUTPUT_OPCODE not output this instruction
7918 3: make instructions conditional
7919 4: make instructions conditional
7921 State transitions (state->state by whom under condition):
7922 0 -> 1 final_prescan_insn if the `target' is a label
7923 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
7924 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
7925 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
7926 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
7927 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
7928 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
7929 (the target insn is arm_target_insn).
7931 If the jump clobbers the conditions then we use states 2 and 4.
7933 A similar thing can be done with conditional return insns.
7935 XXX In case the `target' is an unconditional branch, this conditionalising
7936 of the instructions always reduces code size, but not always execution
7937 time. But then, I want to reduce the code size to somewhere near what
7938 /bin/cc produces. */
7940 /* Returns the index of the ARM condition code string in
7941 `arm_condition_codes'. COMPARISON should be an rtx like
7942 `(eq (...) (...))'. */
7944 static enum arm_cond_code
7945 get_arm_condition_code (comparison)
7948 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
7950 register enum rtx_code comp_code = GET_CODE (comparison);
7952 if (GET_MODE_CLASS (mode) != MODE_CC)
7953 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
7954 XEXP (comparison, 1));
7958 case CC_DNEmode: code = ARM_NE; goto dominance;
7959 case CC_DEQmode: code = ARM_EQ; goto dominance;
7960 case CC_DGEmode: code = ARM_GE; goto dominance;
7961 case CC_DGTmode: code = ARM_GT; goto dominance;
7962 case CC_DLEmode: code = ARM_LE; goto dominance;
7963 case CC_DLTmode: code = ARM_LT; goto dominance;
7964 case CC_DGEUmode: code = ARM_CS; goto dominance;
7965 case CC_DGTUmode: code = ARM_HI; goto dominance;
7966 case CC_DLEUmode: code = ARM_LS; goto dominance;
7967 case CC_DLTUmode: code = ARM_CC;
7970 if (comp_code != EQ && comp_code != NE)
7973 if (comp_code == EQ)
7974 return ARM_INVERSE_CONDITION_CODE (code);
7980 case NE: return ARM_NE;
7981 case EQ: return ARM_EQ;
7982 case GE: return ARM_PL;
7983 case LT: return ARM_MI;
7990 case NE: return ARM_NE;
7991 case EQ: return ARM_EQ;
7997 /* These encodings assume that AC=1 in the FPA system control
7998 byte. This allows us to handle all cases except UNEQ and
8002 case GE: return ARM_GE;
8003 case GT: return ARM_GT;
8004 case LE: return ARM_LS;
8005 case LT: return ARM_MI;
8006 case NE: return ARM_NE;
8007 case EQ: return ARM_EQ;
8008 case ORDERED: return ARM_VC;
8009 case UNORDERED: return ARM_VS;
8010 case UNLT: return ARM_LT;
8011 case UNLE: return ARM_LE;
8012 case UNGT: return ARM_HI;
8013 case UNGE: return ARM_PL;
8014 /* UNEQ and LTGT do not have a representation. */
8015 case UNEQ: /* Fall through. */
8016 case LTGT: /* Fall through. */
8023 case NE: return ARM_NE;
8024 case EQ: return ARM_EQ;
8025 case GE: return ARM_LE;
8026 case GT: return ARM_LT;
8027 case LE: return ARM_GE;
8028 case LT: return ARM_GT;
8029 case GEU: return ARM_LS;
8030 case GTU: return ARM_CC;
8031 case LEU: return ARM_CS;
8032 case LTU: return ARM_HI;
8039 case LTU: return ARM_CS;
8040 case GEU: return ARM_CC;
8047 case NE: return ARM_NE;
8048 case EQ: return ARM_EQ;
8049 case GE: return ARM_GE;
8050 case GT: return ARM_GT;
8051 case LE: return ARM_LE;
8052 case LT: return ARM_LT;
8053 case GEU: return ARM_CS;
8054 case GTU: return ARM_HI;
8055 case LEU: return ARM_LS;
8056 case LTU: return ARM_CC;
8068 arm_final_prescan_insn (insn)
8071 /* BODY will hold the body of INSN. */
8072 register rtx body = PATTERN (insn);
8074 /* This will be 1 if trying to repeat the trick, and things need to be
8075 reversed if it appears to fail. */
8078 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8079 taken are clobbered, even if the rtl suggests otherwise. It also
8080 means that we have to grub around within the jump expression to find
8081 out what the conditions are when the jump isn't taken. */
8082 int jump_clobbers = 0;
8084 /* If we start with a return insn, we only succeed if we find another one. */
8085 int seeking_return = 0;
8087 /* START_INSN will hold the insn from where we start looking. This is the
8088 first insn after the following code_label if REVERSE is true. */
8089 rtx start_insn = insn;
8091 /* If in state 4, check if the target branch is reached, in order to
8092 change back to state 0. */
8093 if (arm_ccfsm_state == 4)
8095 if (insn == arm_target_insn)
8097 arm_target_insn = NULL;
8098 arm_ccfsm_state = 0;
8103 /* If in state 3, it is possible to repeat the trick, if this insn is an
8104 unconditional branch to a label, and immediately following this branch
8105 is the previous target label which is only used once, and the label this
8106 branch jumps to is not too far off. */
8107 if (arm_ccfsm_state == 3)
8109 if (simplejump_p (insn))
8111 start_insn = next_nonnote_insn (start_insn);
8112 if (GET_CODE (start_insn) == BARRIER)
8114 /* XXX Isn't this always a barrier? */
8115 start_insn = next_nonnote_insn (start_insn);
8117 if (GET_CODE (start_insn) == CODE_LABEL
8118 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8119 && LABEL_NUSES (start_insn) == 1)
8124 else if (GET_CODE (body) == RETURN)
8126 start_insn = next_nonnote_insn (start_insn);
8127 if (GET_CODE (start_insn) == BARRIER)
8128 start_insn = next_nonnote_insn (start_insn);
8129 if (GET_CODE (start_insn) == CODE_LABEL
8130 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8131 && LABEL_NUSES (start_insn) == 1)
8143 if (arm_ccfsm_state != 0 && !reverse)
8145 if (GET_CODE (insn) != JUMP_INSN)
8148 /* This jump might be paralleled with a clobber of the condition codes
8149 the jump should always come first */
8150 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
8151 body = XVECEXP (body, 0, 0);
8154 /* If this is a conditional return then we don't want to know */
8155 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8156 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
8157 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
8158 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
8163 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8164 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
8167 int fail = FALSE, succeed = FALSE;
8168 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8169 int then_not_else = TRUE;
8170 rtx this_insn = start_insn, label = 0;
8172 /* If the jump cannot be done with one instruction, we cannot
8173 conditionally execute the instruction in the inverse case. */
8174 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
8180 /* Register the insn jumped to. */
8183 if (!seeking_return)
8184 label = XEXP (SET_SRC (body), 0);
8186 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
8187 label = XEXP (XEXP (SET_SRC (body), 1), 0);
8188 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
8190 label = XEXP (XEXP (SET_SRC (body), 2), 0);
8191 then_not_else = FALSE;
8193 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
8195 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
8198 then_not_else = FALSE;
8203 /* See how many insns this branch skips, and what kind of insns. If all
8204 insns are okay, and the label or unconditional branch to the same
8205 label is not too far away, succeed. */
8206 for (insns_skipped = 0;
8207 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
8211 this_insn = next_nonnote_insn (this_insn);
8215 switch (GET_CODE (this_insn))
8218 /* Succeed if it is the target label, otherwise fail since
8219 control falls in from somewhere else. */
8220 if (this_insn == label)
8224 arm_ccfsm_state = 2;
8225 this_insn = next_nonnote_insn (this_insn);
8228 arm_ccfsm_state = 1;
8236 /* Succeed if the following insn is the target label.
8238 If return insns are used then the last insn in a function
8239 will be a barrier. */
8240 this_insn = next_nonnote_insn (this_insn);
8241 if (this_insn && this_insn == label)
8245 arm_ccfsm_state = 2;
8246 this_insn = next_nonnote_insn (this_insn);
8249 arm_ccfsm_state = 1;
8257 /* If using 32-bit addresses the cc is not preserved over
8261 /* Succeed if the following insn is the target label,
8262 or if the following two insns are a barrier and
8263 the target label. */
8264 this_insn = next_nonnote_insn (this_insn);
8265 if (this_insn && GET_CODE (this_insn) == BARRIER)
8266 this_insn = next_nonnote_insn (this_insn);
8268 if (this_insn && this_insn == label
8269 && insns_skipped < max_insns_skipped)
8273 arm_ccfsm_state = 2;
8274 this_insn = next_nonnote_insn (this_insn);
8277 arm_ccfsm_state = 1;
8286 /* If this is an unconditional branch to the same label, succeed.
8287 If it is to another label, do nothing. If it is conditional,
8289 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8291 scanbody = PATTERN (this_insn);
8292 if (GET_CODE (scanbody) == SET
8293 && GET_CODE (SET_DEST (scanbody)) == PC)
8295 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
8296 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
8298 arm_ccfsm_state = 2;
8301 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
8304 /* Fail if a conditional return is undesirable (eg on a
8305 StrongARM), but still allow this if optimizing for size. */
8306 else if (GET_CODE (scanbody) == RETURN
8307 && !use_return_insn (TRUE)
8310 else if (GET_CODE (scanbody) == RETURN
8313 arm_ccfsm_state = 2;
8316 else if (GET_CODE (scanbody) == PARALLEL)
8318 switch (get_attr_conds (this_insn))
8328 fail = TRUE; /* Unrecognized jump (eg epilogue). */
8333 /* Instructions using or affecting the condition codes make it
8335 scanbody = PATTERN (this_insn);
8336 if (!(GET_CODE (scanbody) == SET
8337 || GET_CODE (scanbody) == PARALLEL)
8338 || get_attr_conds (this_insn) != CONDS_NOCOND)
8348 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
8349 arm_target_label = CODE_LABEL_NUMBER (label);
8350 else if (seeking_return || arm_ccfsm_state == 2)
8352 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
8354 this_insn = next_nonnote_insn (this_insn);
8355 if (this_insn && (GET_CODE (this_insn) == BARRIER
8356 || GET_CODE (this_insn) == CODE_LABEL))
8361 /* Oh, dear! we ran off the end.. give up */
8362 recog (PATTERN (insn), insn, NULL_PTR);
8363 arm_ccfsm_state = 0;
8364 arm_target_insn = NULL;
8367 arm_target_insn = this_insn;
8376 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
8378 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
8379 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8380 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
8381 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8385 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8388 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
8392 if (reverse || then_not_else)
8393 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8396 /* Restore recog_data (getting the attributes of other insns can
8397 destroy this array, but final.c assumes that it remains intact
8398 across this call; since the insn has been recognized already we
8399 call recog direct). */
8400 recog (PATTERN (insn), insn, NULL_PTR);
8405 arm_regno_class (regno)
8410 if (regno == STACK_POINTER_REGNUM)
8412 if (regno == CC_REGNUM)
8419 if ( regno <= LAST_ARM_REGNUM
8420 || regno == FRAME_POINTER_REGNUM
8421 || regno == ARG_POINTER_REGNUM)
8422 return GENERAL_REGS;
8424 if (regno == CC_REGNUM)
8430 /* Handle a special case when computing the offset
8431 of an argument from the frame pointer. */
8433 arm_debugger_arg_offset (value, addr)
8439 /* We are only interested if dbxout_parms() failed to compute the offset. */
8443 /* We can only cope with the case where the address is held in a register. */
8444 if (GET_CODE (addr) != REG)
8447 /* If we are using the frame pointer to point at the argument, then
8448 an offset of 0 is correct. */
8449 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
8452 /* If we are using the stack pointer to point at the
8453 argument, then an offset of 0 is correct. */
8454 if ((TARGET_THUMB || !frame_pointer_needed)
8455 && REGNO (addr) == SP_REGNUM)
8458 /* Oh dear. The argument is pointed to by a register rather
8459 than being held in a register, or being stored at a known
8460 offset from the frame pointer. Since GDB only understands
8461 those two kinds of argument we must translate the address
8462 held in the register into an offset from the frame pointer.
8463 We do this by searching through the insns for the function
8464 looking to see where this register gets its value. If the
8465 register is initialised from the frame pointer plus an offset
8466 then we are in luck and we can continue, otherwise we give up.
8468 This code is exercised by producing debugging information
8469 for a function with arguments like this:
8471 double func (double a, double b, int c, double d) {return d;}
8473 Without this code the stab for parameter 'd' will be set to
8474 an offset of 0 from the frame pointer, rather than 8. */
8476 /* The if() statement says:
8478 If the insn is a normal instruction
8479 and if the insn is setting the value in a register
8480 and if the register being set is the register holding the address of the argument
8481 and if the address is computing by an addition
8482 that involves adding to a register
8483 which is the frame pointer
8488 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8490 if ( GET_CODE (insn) == INSN
8491 && GET_CODE (PATTERN (insn)) == SET
8492 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
8493 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
8494 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
8495 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
8496 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
8499 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
8508 warning ("Unable to compute real location of stacked parameter");
8509 value = 8; /* XXX magic hack */
8515 #define def_builtin(NAME, TYPE, CODE) \
8516 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL_PTR)
8519 arm_init_builtins ()
8521 tree endlink = tree_cons (NULL_TREE, void_type_node, NULL_TREE);
8522 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
8523 tree pchar_type_node = build_pointer_type (char_type_node);
8525 tree int_ftype_int, void_ftype_pchar;
8527 /* void func (void *) */
8529 = build_function_type (void_type_node,
8530 tree_cons (NULL_TREE, pchar_type_node, endlink));
8532 /* int func (int) */
8534 = build_function_type (integer_type_node, int_endlink);
8536 /* Initialize arm V5 builtins. */
8539 def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
8540 def_builtin ("__builtin_prefetch", void_ftype_pchar,
8541 ARM_BUILTIN_PREFETCH);
8545 /* Expand an expression EXP that calls a built-in function,
8546 with result going to TARGET if that's convenient
8547 (and in mode MODE if that's convenient).
8548 SUBTARGET may be used as the target for computing one of EXP's operands.
8549 IGNORE is nonzero if the value is to be ignored. */
8552 arm_expand_builtin (exp, target, subtarget, mode, ignore)
8555 rtx subtarget ATTRIBUTE_UNUSED;
8556 enum machine_mode mode ATTRIBUTE_UNUSED;
8557 int ignore ATTRIBUTE_UNUSED;
8559 enum insn_code icode;
8560 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8561 tree arglist = TREE_OPERAND (exp, 1);
8564 enum machine_mode tmode, mode0;
8565 int fcode = DECL_FUNCTION_CODE (fndecl);
8572 case ARM_BUILTIN_CLZ:
8573 icode = CODE_FOR_clz;
8574 arg0 = TREE_VALUE (arglist);
8575 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
8576 tmode = insn_data[icode].operand[0].mode;
8577 mode0 = insn_data[icode].operand[1].mode;
8579 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8580 op0 = copy_to_mode_reg (mode0, op0);
8582 || GET_MODE (target) != tmode
8583 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8584 target = gen_reg_rtx (tmode);
8585 pat = GEN_FCN (icode) (target, op0);
8591 case ARM_BUILTIN_PREFETCH:
8592 icode = CODE_FOR_prefetch;
8593 arg0 = TREE_VALUE (arglist);
8594 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
8596 op0 = gen_rtx_MEM (SImode, copy_to_mode_reg (Pmode, op0));
8598 pat = GEN_FCN (icode) (op0);
8605 /* @@@ Should really do something sensible here. */
8609 /* Recursively search through all of the blocks in a function
8610 checking to see if any of the variables created in that
8611 function match the RTX called 'orig'. If they do then
8612 replace them with the RTX called 'new'. */
8615 replace_symbols_in_block (block, orig, new)
8620 for (; block; block = BLOCK_CHAIN (block))
8624 if (!TREE_USED (block))
8627 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
8629 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
8630 || DECL_IGNORED_P (sym)
8631 || TREE_CODE (sym) != VAR_DECL
8632 || DECL_EXTERNAL (sym)
8633 || !rtx_equal_p (DECL_RTL (sym), orig)
8637 DECL_RTL (sym) = new;
8640 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
8644 /* Return the number (counting from 0) of the least significant set
8650 number_of_first_bit_set (mask)
8656 (mask & (1 << bit)) == 0;
8663 /* Generate code to return from a thumb function.
8664 If 'reg_containing_return_addr' is -1, then the return address is
8665 actually on the stack, at the stack pointer. */
8667 thumb_exit (f, reg_containing_return_addr, eh_ofs)
8669 int reg_containing_return_addr;
8672 unsigned regs_available_for_popping;
8673 unsigned regs_to_pop;
8679 int restore_a4 = FALSE;
8681 /* Compute the registers we need to pop. */
8685 /* There is an assumption here, that if eh_ofs is not NULL, the
8686 normal return address will have been pushed. */
8687 if (reg_containing_return_addr == -1 || eh_ofs)
8689 /* When we are generating a return for __builtin_eh_return,
8690 reg_containing_return_addr must specify the return regno. */
8691 if (eh_ofs && reg_containing_return_addr == -1)
8694 regs_to_pop |= 1 << LR_REGNUM;
8698 if (TARGET_BACKTRACE)
8700 /* Restore the (ARM) frame pointer and stack pointer. */
8701 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
8705 /* If there is nothing to pop then just emit the BX instruction and
8707 if (pops_needed == 0)
8710 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
8712 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
8715 /* Otherwise if we are not supporting interworking and we have not created
8716 a backtrace structure and the function was not entered in ARM mode then
8717 just pop the return address straight into the PC. */
8718 else if (!TARGET_INTERWORK
8719 && !TARGET_BACKTRACE
8720 && !is_called_in_ARM_mode (current_function_decl))
8724 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
8725 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
8726 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
8729 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
8734 /* Find out how many of the (return) argument registers we can corrupt. */
8735 regs_available_for_popping = 0;
8737 /* If returning via __builtin_eh_return, the bottom three registers
8738 all contain information needed for the return. */
8744 /* If we can deduce the registers used from the function's
8745 return value. This is more reliable that examining
8746 regs_ever_live[] because that will be set if the register is
8747 ever used in the function, not just if the register is used
8748 to hold a return value. */
8750 if (current_function_return_rtx != 0)
8751 mode = GET_MODE (current_function_return_rtx);
8754 mode = DECL_MODE (DECL_RESULT (current_function_decl));
8756 size = GET_MODE_SIZE (mode);
8760 /* In a void function we can use any argument register.
8761 In a function that returns a structure on the stack
8762 we can use the second and third argument registers. */
8763 if (mode == VOIDmode)
8764 regs_available_for_popping =
8765 (1 << ARG_REGISTER (1))
8766 | (1 << ARG_REGISTER (2))
8767 | (1 << ARG_REGISTER (3));
8769 regs_available_for_popping =
8770 (1 << ARG_REGISTER (2))
8771 | (1 << ARG_REGISTER (3));
8774 regs_available_for_popping =
8775 (1 << ARG_REGISTER (2))
8776 | (1 << ARG_REGISTER (3));
8778 regs_available_for_popping =
8779 (1 << ARG_REGISTER (3));
8782 /* Match registers to be popped with registers into which we pop them. */
8783 for (available = regs_available_for_popping,
8784 required = regs_to_pop;
8785 required != 0 && available != 0;
8786 available &= ~(available & - available),
8787 required &= ~(required & - required))
8790 /* If we have any popping registers left over, remove them. */
8792 regs_available_for_popping &= ~available;
8794 /* Otherwise if we need another popping register we can use
8795 the fourth argument register. */
8796 else if (pops_needed)
8798 /* If we have not found any free argument registers and
8799 reg a4 contains the return address, we must move it. */
8800 if (regs_available_for_popping == 0
8801 && reg_containing_return_addr == LAST_ARG_REGNUM)
8803 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
8804 reg_containing_return_addr = LR_REGNUM;
8808 /* Register a4 is being used to hold part of the return value,
8809 but we have dire need of a free, low register. */
8812 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
8815 if (reg_containing_return_addr != LAST_ARG_REGNUM)
8817 /* The fourth argument register is available. */
8818 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
8824 /* Pop as many registers as we can. */
8825 thumb_pushpop (f, regs_available_for_popping, FALSE);
8827 /* Process the registers we popped. */
8828 if (reg_containing_return_addr == -1)
8830 /* The return address was popped into the lowest numbered register. */
8831 regs_to_pop &= ~(1 << LR_REGNUM);
8833 reg_containing_return_addr =
8834 number_of_first_bit_set (regs_available_for_popping);
8836 /* Remove this register for the mask of available registers, so that
8837 the return address will not be corrupted by futher pops. */
8838 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
8841 /* If we popped other registers then handle them here. */
8842 if (regs_available_for_popping)
8846 /* Work out which register currently contains the frame pointer. */
8847 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
8849 /* Move it into the correct place. */
8850 asm_fprintf (f, "\tmov\t%r, %r\n",
8851 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
8853 /* (Temporarily) remove it from the mask of popped registers. */
8854 regs_available_for_popping &= ~(1 << frame_pointer);
8855 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
8857 if (regs_available_for_popping)
8861 /* We popped the stack pointer as well,
8862 find the register that contains it. */
8863 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
8865 /* Move it into the stack register. */
8866 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
8868 /* At this point we have popped all necessary registers, so
8869 do not worry about restoring regs_available_for_popping
8870 to its correct value:
8872 assert (pops_needed == 0)
8873 assert (regs_available_for_popping == (1 << frame_pointer))
8874 assert (regs_to_pop == (1 << STACK_POINTER)) */
8878 /* Since we have just move the popped value into the frame
8879 pointer, the popping register is available for reuse, and
8880 we know that we still have the stack pointer left to pop. */
8881 regs_available_for_popping |= (1 << frame_pointer);
8885 /* If we still have registers left on the stack, but we no longer have
8886 any registers into which we can pop them, then we must move the return
8887 address into the link register and make available the register that
8889 if (regs_available_for_popping == 0 && pops_needed > 0)
8891 regs_available_for_popping |= 1 << reg_containing_return_addr;
8893 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
8894 reg_containing_return_addr);
8896 reg_containing_return_addr = LR_REGNUM;
8899 /* If we have registers left on the stack then pop some more.
8900 We know that at most we will want to pop FP and SP. */
8901 if (pops_needed > 0)
8906 thumb_pushpop (f, regs_available_for_popping, FALSE);
8908 /* We have popped either FP or SP.
8909 Move whichever one it is into the correct register. */
8910 popped_into = number_of_first_bit_set (regs_available_for_popping);
8911 move_to = number_of_first_bit_set (regs_to_pop);
8913 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
8915 regs_to_pop &= ~(1 << move_to);
8920 /* If we still have not popped everything then we must have only
8921 had one register available to us and we are now popping the SP. */
8922 if (pops_needed > 0)
8926 thumb_pushpop (f, regs_available_for_popping, FALSE);
8928 popped_into = number_of_first_bit_set (regs_available_for_popping);
8930 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
8932 assert (regs_to_pop == (1 << STACK_POINTER))
8933 assert (pops_needed == 1)
8937 /* If necessary restore the a4 register. */
8940 if (reg_containing_return_addr != LR_REGNUM)
8942 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
8943 reg_containing_return_addr = LR_REGNUM;
8946 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
8950 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
8952 /* Return to caller. */
8953 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
8956 /* Emit code to push or pop registers to or from the stack. */
8958 thumb_pushpop (f, mask, push)
8964 int lo_mask = mask & 0xFF;
8966 if (lo_mask == 0 && !push && (mask & (1 << 15)))
8968 /* Special case. Do not generate a POP PC statement here, do it in
8970 thumb_exit (f, -1, NULL_RTX);
8974 fprintf (f, "\t%s\t{", push ? "push" : "pop");
8976 /* Look at the low registers first. */
8977 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
8981 asm_fprintf (f, "%r", regno);
8983 if ((lo_mask & ~1) != 0)
8988 if (push && (mask & (1 << LR_REGNUM)))
8990 /* Catch pushing the LR. */
8994 asm_fprintf (f, "%r", LR_REGNUM);
8996 else if (!push && (mask & (1 << PC_REGNUM)))
8998 /* Catch popping the PC. */
8999 if (TARGET_INTERWORK || TARGET_BACKTRACE)
9001 /* The PC is never poped directly, instead
9002 it is popped into r3 and then BX is used. */
9005 thumb_exit (f, -1, NULL_RTX);
9014 asm_fprintf (f, "%r", PC_REGNUM);
9022 thumb_final_prescan_insn (insn)
9025 if (flag_print_asm_name)
9026 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
9027 INSN_ADDRESSES (INSN_UID (insn)));
9031 thumb_shiftable_const (val)
9032 unsigned HOST_WIDE_INT val;
9034 unsigned HOST_WIDE_INT mask = 0xff;
9037 if (val == 0) /* XXX */
9040 for (i = 0; i < 25; i++)
9041 if ((val & (mask << i)) == val)
9047 /* Returns non-zero if the current function contains,
9048 or might contain a far jump. */
9050 thumb_far_jump_used_p (int in_prologue)
9054 /* This test is only important for leaf functions. */
9055 /* assert (!leaf_function_p ()); */
9057 /* If we have already decided that far jumps may be used,
9058 do not bother checking again, and always return true even if
9059 it turns out that they are not being used. Once we have made
9060 the decision that far jumps are present (and that hence the link
9061 register will be pushed onto the stack) we cannot go back on it. */
9062 if (cfun->machine->far_jump_used)
9065 /* If this function is not being called from the prologue/epilogue
9066 generation code then it must be being called from the
9067 INITIAL_ELIMINATION_OFFSET macro. */
9070 /* In this case we know that we are being asked about the elimination
9071 of the arg pointer register. If that register is not being used,
9072 then there are no arguments on the stack, and we do not have to
9073 worry that a far jump might force the prologue to push the link
9074 register, changing the stack offsets. In this case we can just
9075 return false, since the presence of far jumps in the function will
9076 not affect stack offsets.
9078 If the arg pointer is live (or if it was live, but has now been
9079 eliminated and so set to dead) then we do have to test to see if
9080 the function might contain a far jump. This test can lead to some
9081 false negatives, since before reload is completed, then length of
9082 branch instructions is not known, so gcc defaults to returning their
9083 longest length, which in turn sets the far jump attribute to true.
9085 A false negative will not result in bad code being generated, but it
9086 will result in a needless push and pop of the link register. We
9087 hope that this does not occur too often. */
9088 if (regs_ever_live [ARG_POINTER_REGNUM])
9089 cfun->machine->arg_pointer_live = 1;
9090 else if (!cfun->machine->arg_pointer_live)
9094 /* Check to see if the function contains a branch
9095 insn with the far jump attribute set. */
9096 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9098 if (GET_CODE (insn) == JUMP_INSN
9099 /* Ignore tablejump patterns. */
9100 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9101 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9102 && get_attr_far_jump (insn) == FAR_JUMP_YES
9105 /* Record the fact that we have decied that
9106 the function does use far jumps. */
9107 cfun->machine->far_jump_used = 1;
9115 /* Return non-zero if FUNC must be entered in ARM mode. */
9117 is_called_in_ARM_mode (func)
9120 if (TREE_CODE (func) != FUNCTION_DECL)
9123 /* Ignore the problem about functions whoes address is taken. */
9124 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
9128 return lookup_attribute ("interfacearm", DECL_MACHINE_ATTRIBUTES (func)) != NULL_TREE;
9134 /* The bits which aren't usefully expanded as rtl. */
9136 thumb_unexpanded_epilogue ()
9139 int live_regs_mask = 0;
9140 int high_regs_pushed = 0;
9141 int leaf_function = leaf_function_p ();
9143 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9145 if (return_used_this_function)
9148 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9149 if (regs_ever_live[regno] && !call_used_regs[regno]
9150 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9151 live_regs_mask |= 1 << regno;
9153 for (regno = 8; regno < 13; regno++)
9155 if (regs_ever_live[regno] && !call_used_regs[regno]
9156 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9160 /* The prolog may have pushed some high registers to use as
9161 work registers. eg the testuite file:
9162 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9163 compiles to produce:
9164 push {r4, r5, r6, r7, lr}
9168 as part of the prolog. We have to undo that pushing here. */
9170 if (high_regs_pushed)
9172 int mask = live_regs_mask;
9178 /* If we can deduce the registers used from the function's return value.
9179 This is more reliable that examining regs_ever_live[] because that
9180 will be set if the register is ever used in the function, not just if
9181 the register is used to hold a return value. */
9183 if (current_function_return_rtx != 0)
9184 mode = GET_MODE (current_function_return_rtx);
9187 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9189 size = GET_MODE_SIZE (mode);
9191 /* Unless we are returning a type of size > 12 register r3 is
9197 /* Oh dear! We have no low registers into which we can pop
9199 fatal ("No low registers available for popping high registers");
9201 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
9202 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
9203 && !(TARGET_SINGLE_PIC_BASE && (next_hi_reg == arm_pic_register)))
9206 while (high_regs_pushed)
9208 /* Find lo register(s) into which the high register(s) can
9210 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9212 if (mask & (1 << regno))
9214 if (high_regs_pushed == 0)
9218 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
9220 /* Pop the values into the low register(s). */
9221 thumb_pushpop (asm_out_file, mask, 0);
9223 /* Move the value(s) into the high registers. */
9224 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9226 if (mask & (1 << regno))
9228 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
9231 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
9232 if (regs_ever_live[next_hi_reg]
9233 && !call_used_regs[next_hi_reg]
9234 && !(TARGET_SINGLE_PIC_BASE
9235 && (next_hi_reg == arm_pic_register)))
9242 had_to_push_lr = (live_regs_mask || !leaf_function
9243 || thumb_far_jump_used_p (1));
9245 if (TARGET_BACKTRACE
9246 && ((live_regs_mask & 0xFF) == 0)
9247 && regs_ever_live [LAST_ARG_REGNUM] != 0)
9249 /* The stack backtrace structure creation code had to
9250 push R7 in order to get a work register, so we pop
9252 live_regs_mask |= (1 << LAST_LO_REGNUM);
9255 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
9258 && !is_called_in_ARM_mode (current_function_decl)
9260 live_regs_mask |= 1 << PC_REGNUM;
9262 /* Either no argument registers were pushed or a backtrace
9263 structure was created which includes an adjusted stack
9264 pointer, so just pop everything. */
9266 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9269 thumb_exit (asm_out_file, 2, eh_ofs);
9270 /* We have either just popped the return address into the
9271 PC or it is was kept in LR for the entire function or
9272 it is still on the stack because we do not want to
9273 return by doing a pop {pc}. */
9274 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
9275 thumb_exit (asm_out_file,
9277 && is_called_in_ARM_mode (current_function_decl)) ?
9278 -1 : LR_REGNUM, NULL_RTX);
9282 /* Pop everything but the return address. */
9283 live_regs_mask &= ~(1 << PC_REGNUM);
9286 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9289 /* Get the return address into a temporary register. */
9290 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
9292 /* Remove the argument registers that were pushed onto the stack. */
9293 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
9294 SP_REGNUM, SP_REGNUM,
9295 current_function_pretend_args_size);
9298 thumb_exit (asm_out_file, 2, eh_ofs);
9300 thumb_exit (asm_out_file,
9301 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
9307 /* Functions to save and restore machine-specific function data. */
9310 arm_mark_machine_status (p)
9311 struct function * p;
9313 struct machine_function *machine = p->machine;
9315 ggc_mark_rtx (machine->ra_rtx);
9316 ggc_mark_rtx (machine->eh_epilogue_sp_ofs);
9320 arm_init_machine_status (p)
9321 struct function * p;
9324 (struct machine_function *) xcalloc (1, sizeof (struct machine_function));
9327 /* Return an RTX indicating where the return address to the
9328 calling function can be found. */
9330 arm_return_addr (count, frame)
9332 rtx frame ATTRIBUTE_UNUSED;
9339 reg = cfun->machine->ra_rtx;
9345 /* No rtx yet. Invent one, and initialize it for r14 (lr) in
9347 reg = gen_reg_rtx (Pmode);
9348 cfun->machine->ra_rtx = reg;
9350 if (!TARGET_APCS_32)
9351 init = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
9352 GEN_INT (RETURN_ADDR_MASK26));
9354 init = gen_rtx_REG (Pmode, LR_REGNUM);
9356 init = gen_rtx_SET (VOIDmode, reg, init);
9358 /* Emit the insn to the prologue with the other argument copies. */
9359 push_topmost_sequence ();
9360 emit_insn_after (init, get_insns ());
9361 pop_topmost_sequence ();
9367 /* Do anything needed before RTL is emitted for each function. */
9369 arm_init_expanders ()
9371 /* Arrange to initialize and mark the machine per-function status. */
9372 init_machine_status = arm_init_machine_status;
9373 mark_machine_status = arm_mark_machine_status;
9376 /* Generate the rest of a function's prologue. */
9378 thumb_expand_prologue ()
9380 HOST_WIDE_INT amount = (get_frame_size ()
9381 + current_function_outgoing_args_size);
9383 /* Naked functions don't have prologues. */
9384 if (arm_naked_function_p (current_function_decl))
9387 if (frame_pointer_needed)
9388 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
9392 amount = ROUND_UP (amount);
9395 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9396 GEN_INT (-amount)));
9402 /* The stack decrement is too big for an immediate value in a single
9403 insn. In theory we could issue multiple subtracts, but after
9404 three of them it becomes more space efficient to place the full
9405 value in the constant pool and load into a register. (Also the
9406 ARM debugger really likes to see only one stack decrement per
9407 function). So instead we look for a scratch register into which
9408 we can load the decrement, and then we subtract this from the
9409 stack pointer. Unfortunately on the thumb the only available
9410 scratch registers are the argument registers, and we cannot use
9411 these as they may hold arguments to the function. Instead we
9412 attempt to locate a call preserved register which is used by this
9413 function. If we can find one, then we know that it will have
9414 been pushed at the start of the prologue and so we can corrupt
9416 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
9417 if (regs_ever_live[regno]
9418 && !call_used_regs[regno] /* Paranoia */
9419 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))
9420 && !(frame_pointer_needed
9421 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
9424 if (regno > LAST_LO_REGNUM) /* Very unlikely */
9426 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
9428 /* Choose an arbitary, non-argument low register. */
9429 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
9431 /* Save it by copying it into a high, scratch register. */
9432 emit_insn (gen_movsi (spare, reg));
9434 /* Decrement the stack. */
9435 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9436 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9439 /* Restore the low register's original value. */
9440 emit_insn (gen_movsi (reg, spare));
9442 /* Emit a USE of the restored scratch register, so that flow
9443 analysis will not consider the restore redundant. The
9444 register won't be used again in this function and isn't
9445 restored by the epilogue. */
9446 emit_insn (gen_rtx_USE (VOIDmode, reg));
9450 reg = gen_rtx (REG, SImode, regno);
9452 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9453 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9459 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9460 emit_insn (gen_blockage ());
9464 thumb_expand_epilogue ()
9466 HOST_WIDE_INT amount = (get_frame_size ()
9467 + current_function_outgoing_args_size);
9469 /* Naked functions don't have epilogues. */
9470 if (arm_naked_function_p (current_function_decl))
9473 if (frame_pointer_needed)
9474 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
9477 amount = ROUND_UP (amount);
9480 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9484 /* r3 is always free in the epilogue. */
9485 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
9487 emit_insn (gen_movsi (reg, GEN_INT (amount)));
9488 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
9492 /* Emit a USE (stack_pointer_rtx), so that
9493 the stack adjustment will not be deleted. */
9494 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
9496 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9497 emit_insn (gen_blockage ());
9501 output_thumb_prologue (f)
9504 int live_regs_mask = 0;
9505 int high_regs_pushed = 0;
9506 int store_arg_regs = 0;
9509 if (arm_naked_function_p (current_function_decl))
9512 if (is_called_in_ARM_mode (current_function_decl))
9516 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
9518 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
9520 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9522 /* Generate code sequence to switch us into Thumb mode. */
9523 /* The .code 32 directive has already been emitted by
9524 ASM_DECLARE_FUNCTION_NAME. */
9525 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
9526 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
9528 /* Generate a label, so that the debugger will notice the
9529 change in instruction sets. This label is also used by
9530 the assembler to bypass the ARM code when this function
9531 is called from a Thumb encoded function elsewhere in the
9532 same file. Hence the definition of STUB_NAME here must
9533 agree with the definition in gas/config/tc-arm.c */
9535 #define STUB_NAME ".real_start_of"
9537 asm_fprintf (f, "\t.code\t16\n");
9539 if (arm_dllexport_name_p (name))
9540 name = arm_strip_name_encoding (name);
9542 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
9543 asm_fprintf (f, "\t.thumb_func\n");
9544 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
9547 if (current_function_anonymous_args && current_function_pretend_args_size)
9550 if (current_function_pretend_args_size)
9556 asm_fprintf (f, "\tpush\t{");
9558 num_pushes = NUM_INTS (current_function_pretend_args_size);
9560 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
9561 regno <= LAST_ARG_REGNUM;
9563 asm_fprintf (f, "%r%s", regno,
9564 regno == LAST_ARG_REGNUM ? "" : ", ");
9566 asm_fprintf (f, "}\n");
9569 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
9570 SP_REGNUM, SP_REGNUM,
9571 current_function_pretend_args_size);
9574 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9575 if (regs_ever_live[regno] && !call_used_regs[regno]
9576 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9577 live_regs_mask |= 1 << regno;
9579 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
9580 live_regs_mask |= 1 << LR_REGNUM;
9582 if (TARGET_BACKTRACE)
9585 int work_register = 0;
9588 /* We have been asked to create a stack backtrace structure.
9589 The code looks like this:
9593 0 sub SP, #16 Reserve space for 4 registers.
9594 2 push {R7} Get a work register.
9595 4 add R7, SP, #20 Get the stack pointer before the push.
9596 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
9597 8 mov R7, PC Get hold of the start of this code plus 12.
9598 10 str R7, [SP, #16] Store it.
9599 12 mov R7, FP Get hold of the current frame pointer.
9600 14 str R7, [SP, #4] Store it.
9601 16 mov R7, LR Get hold of the current return address.
9602 18 str R7, [SP, #12] Store it.
9603 20 add R7, SP, #16 Point at the start of the backtrace structure.
9604 22 mov FP, R7 Put this value into the frame pointer. */
9606 if ((live_regs_mask & 0xFF) == 0)
9608 /* See if the a4 register is free. */
9610 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
9611 work_register = LAST_ARG_REGNUM;
9612 else /* We must push a register of our own */
9613 live_regs_mask |= (1 << LAST_LO_REGNUM);
9616 if (work_register == 0)
9618 /* Select a register from the list that will be pushed to
9619 use as our work register. */
9620 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
9621 if ((1 << work_register) & live_regs_mask)
9626 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
9627 SP_REGNUM, SP_REGNUM);
9630 thumb_pushpop (f, live_regs_mask, 1);
9632 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
9633 if (wr & live_regs_mask)
9636 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
9637 offset + 16 + current_function_pretend_args_size);
9639 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9642 /* Make sure that the instruction fetching the PC is in the right place
9643 to calculate "start of backtrace creation code + 12". */
9646 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
9647 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9649 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
9650 ARM_HARD_FRAME_POINTER_REGNUM);
9651 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9656 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
9657 ARM_HARD_FRAME_POINTER_REGNUM);
9658 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9660 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
9661 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9665 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
9666 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9668 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
9670 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
9671 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
9673 else if (live_regs_mask)
9674 thumb_pushpop (f, live_regs_mask, 1);
9676 for (regno = 8; regno < 13; regno++)
9678 if (regs_ever_live[regno] && !call_used_regs[regno]
9679 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9683 if (high_regs_pushed)
9685 int pushable_regs = 0;
9686 int mask = live_regs_mask & 0xff;
9689 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
9691 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
9692 && !(TARGET_SINGLE_PIC_BASE
9693 && (next_hi_reg == arm_pic_register)))
9697 pushable_regs = mask;
9699 if (pushable_regs == 0)
9701 /* Desperation time -- this probably will never happen. */
9702 if (regs_ever_live[LAST_ARG_REGNUM]
9703 || !call_used_regs[LAST_ARG_REGNUM])
9704 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
9705 mask = 1 << LAST_ARG_REGNUM;
9708 while (high_regs_pushed > 0)
9710 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
9712 if (mask & (1 << regno))
9714 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
9718 if (high_regs_pushed)
9719 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
9722 if (regs_ever_live[next_hi_reg]
9723 && !call_used_regs[next_hi_reg]
9724 && !(TARGET_SINGLE_PIC_BASE
9725 && (next_hi_reg == arm_pic_register)))
9730 mask &= ~((1 << regno) - 1);
9736 thumb_pushpop (f, mask, 1);
9739 if (pushable_regs == 0
9740 && (regs_ever_live[LAST_ARG_REGNUM]
9741 || !call_used_regs[LAST_ARG_REGNUM]))
9742 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
9746 /* Handle the case of a double word load into a low register from
9747 a computed memory address. The computed address may involve a
9748 register which is overwritten by the load. */
9751 thumb_load_double_from_address (operands)
9760 if (GET_CODE (operands[0]) != REG)
9761 fatal ("thumb_load_double_from_address: destination is not a register");
9763 if (GET_CODE (operands[1]) != MEM)
9765 debug_rtx (operands[1]);
9766 fatal ("thumb_load_double_from_address: source is not a computed memory address");
9769 /* Get the memory address. */
9770 addr = XEXP (operands[1], 0);
9772 /* Work out how the memory address is computed. */
9773 switch (GET_CODE (addr))
9776 operands[2] = gen_rtx (MEM, SImode,
9777 plus_constant (XEXP (operands[1], 0), 4));
9779 if (REGNO (operands[0]) == REGNO (addr))
9781 output_asm_insn ("ldr\t%H0, %2", operands);
9782 output_asm_insn ("ldr\t%0, %1", operands);
9786 output_asm_insn ("ldr\t%0, %1", operands);
9787 output_asm_insn ("ldr\t%H0, %2", operands);
9792 /* Compute <address> + 4 for the high order load. */
9793 operands[2] = gen_rtx (MEM, SImode,
9794 plus_constant (XEXP (operands[1], 0), 4));
9796 output_asm_insn ("ldr\t%0, %1", operands);
9797 output_asm_insn ("ldr\t%H0, %2", operands);
9801 arg1 = XEXP (addr, 0);
9802 arg2 = XEXP (addr, 1);
9804 if (CONSTANT_P (arg1))
9805 base = arg2, offset = arg1;
9807 base = arg1, offset = arg2;
9809 if (GET_CODE (base) != REG)
9810 fatal ("thumb_load_double_from_address: base is not a register");
9812 /* Catch the case of <address> = <reg> + <reg> */
9813 if (GET_CODE (offset) == REG)
9815 int reg_offset = REGNO (offset);
9816 int reg_base = REGNO (base);
9817 int reg_dest = REGNO (operands[0]);
9819 /* Add the base and offset registers together into the
9820 higher destination register. */
9821 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
9822 reg_dest + 1, reg_base, reg_offset);
9824 /* Load the lower destination register from the address in
9825 the higher destination register. */
9826 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
9827 reg_dest, reg_dest + 1);
9829 /* Load the higher destination register from its own address
9831 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
9832 reg_dest + 1, reg_dest + 1);
9836 /* Compute <address> + 4 for the high order load. */
9837 operands[2] = gen_rtx (MEM, SImode,
9838 plus_constant (XEXP (operands[1], 0), 4));
9840 /* If the computed address is held in the low order register
9841 then load the high order register first, otherwise always
9842 load the low order register first. */
9843 if (REGNO (operands[0]) == REGNO (base))
9845 output_asm_insn ("ldr\t%H0, %2", operands);
9846 output_asm_insn ("ldr\t%0, %1", operands);
9850 output_asm_insn ("ldr\t%0, %1", operands);
9851 output_asm_insn ("ldr\t%H0, %2", operands);
9857 /* With no registers to worry about we can just load the value
9859 operands[2] = gen_rtx (MEM, SImode,
9860 plus_constant (XEXP (operands[1], 0), 4));
9862 output_asm_insn ("ldr\t%H0, %2", operands);
9863 output_asm_insn ("ldr\t%0, %1", operands);
9867 debug_rtx (operands[1]);
9868 fatal ("thumb_load_double_from_address: Unhandled address calculation");
9877 thumb_output_move_mem_multiple (n, operands)
9886 if (REGNO (operands[4]) > REGNO (operands[5]))
9889 operands[4] = operands[5];
9892 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
9893 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
9897 if (REGNO (operands[4]) > REGNO (operands[5]))
9900 operands[4] = operands[5];
9903 if (REGNO (operands[5]) > REGNO (operands[6]))
9906 operands[5] = operands[6];
9909 if (REGNO (operands[4]) > REGNO (operands[5]))
9912 operands[4] = operands[5];
9916 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
9917 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
9927 /* Routines for generating rtl */
9930 thumb_expand_movstrqi (operands)
9933 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
9934 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
9935 HOST_WIDE_INT len = INTVAL (operands[2]);
9936 HOST_WIDE_INT offset = 0;
9940 emit_insn (gen_movmem12b (out, in, out, in));
9946 emit_insn (gen_movmem8b (out, in, out, in));
9952 rtx reg = gen_reg_rtx (SImode);
9953 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
9954 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
9961 rtx reg = gen_reg_rtx (HImode);
9962 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
9963 plus_constant (in, offset))));
9964 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
9972 rtx reg = gen_reg_rtx (QImode);
9973 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
9974 plus_constant (in, offset))));
9975 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
9981 thumb_cmp_operand (op, mode)
9983 enum machine_mode mode;
9985 return ((GET_CODE (op) == CONST_INT
9986 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
9987 || register_operand (op, mode));
9991 thumb_condition_code (x, invert)
9995 static const char * conds[] =
9997 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
9998 "hi", "ls", "ge", "lt", "gt", "le"
10002 switch (GET_CODE (x))
10004 case EQ: val = 0; break;
10005 case NE: val = 1; break;
10006 case GEU: val = 2; break;
10007 case LTU: val = 3; break;
10008 case GTU: val = 8; break;
10009 case LEU: val = 9; break;
10010 case GE: val = 10; break;
10011 case LT: val = 11; break;
10012 case GT: val = 12; break;
10013 case LE: val = 13; break;
10018 return conds[val ^ invert];
10021 /* Handle storing a half-word to memory during reload. */
10023 thumb_reload_out_hi (operands)
10026 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
10029 /* Handle storing a half-word to memory during reload. */
10031 thumb_reload_in_hi (operands)
10032 rtx * operands ATTRIBUTE_UNUSED;
10037 /* Return the length of a function name prefix
10038 that starts with the character 'c'. */
10040 arm_get_strip_length (char c)
10044 ARM_NAME_ENCODING_LENGTHS
10049 /* Return a pointer to a function's name with any
10050 and all prefix encodings stripped from it. */
10052 arm_strip_name_encoding (const char * name)
10056 while ((skip = arm_get_strip_length (* name)))
10062 #ifdef AOF_ASSEMBLER
10063 /* Special functions only needed when producing AOF syntax assembler. */
10065 rtx aof_pic_label = NULL_RTX;
10068 struct pic_chain * next;
10072 static struct pic_chain * aof_pic_chain = NULL;
10078 struct pic_chain ** chainp;
10081 if (aof_pic_label == NULL_RTX)
10083 /* We mark this here and not in arm_add_gc_roots() to avoid
10084 polluting even more code with ifdefs, and because it never
10085 contains anything useful until we assign to it here. */
10086 ggc_add_rtx_root (&aof_pic_label, 1);
10087 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
10090 for (offset = 0, chainp = &aof_pic_chain; *chainp;
10091 offset += 4, chainp = &(*chainp)->next)
10092 if ((*chainp)->symname == XSTR (x, 0))
10093 return plus_constant (aof_pic_label, offset);
10095 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
10096 (*chainp)->next = NULL;
10097 (*chainp)->symname = XSTR (x, 0);
10098 return plus_constant (aof_pic_label, offset);
10102 aof_dump_pic_table (f)
10105 struct pic_chain * chain;
10107 if (aof_pic_chain == NULL)
10110 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
10111 PIC_OFFSET_TABLE_REGNUM,
10112 PIC_OFFSET_TABLE_REGNUM);
10113 fputs ("|x$adcons|\n", f);
10115 for (chain = aof_pic_chain; chain; chain = chain->next)
10117 fputs ("\tDCD\t", f);
10118 assemble_name (f, chain->symname);
10123 int arm_text_section_count = 1;
10126 aof_text_section ()
10128 static char buf[100];
10129 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
10130 arm_text_section_count++);
10132 strcat (buf, ", PIC, REENTRANT");
10136 static int arm_data_section_count = 1;
10139 aof_data_section ()
10141 static char buf[100];
10142 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
10146 /* The AOF assembler is religiously strict about declarations of
10147 imported and exported symbols, so that it is impossible to declare
10148 a function as imported near the beginning of the file, and then to
10149 export it later on. It is, however, possible to delay the decision
10150 until all the functions in the file have been compiled. To get
10151 around this, we maintain a list of the imports and exports, and
10152 delete from it any that are subsequently defined. At the end of
10153 compilation we spit the remainder of the list out before the END
10158 struct import * next;
10162 static struct import * imports_list = NULL;
10165 aof_add_import (name)
10168 struct import * new;
10170 for (new = imports_list; new; new = new->next)
10171 if (new->name == name)
10174 new = (struct import *) xmalloc (sizeof (struct import));
10175 new->next = imports_list;
10176 imports_list = new;
10181 aof_delete_import (name)
10184 struct import ** old;
10186 for (old = &imports_list; *old; old = & (*old)->next)
10188 if ((*old)->name == name)
10190 *old = (*old)->next;
10196 int arm_main_function = 0;
10199 aof_dump_imports (f)
10202 /* The AOF assembler needs this to cause the startup code to be extracted
10203 from the library. Brining in __main causes the whole thing to work
10205 if (arm_main_function)
10208 fputs ("\tIMPORT __main\n", f);
10209 fputs ("\tDCD __main\n", f);
10212 /* Now dump the remaining imports. */
10213 while (imports_list)
10215 fprintf (f, "\tIMPORT\t");
10216 assemble_name (f, imports_list->name);
10218 imports_list = imports_list->next;
10221 #endif /* AOF_ASSEMBLER */