1 /* Definitions of target machine for GNU compiler, for ARM with a.out
2 Copyright (C) 1995-2013 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rearnsha@armltd.co.uk).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
25 #define ASM_APP_OFF ""
28 /* Switch to the text or data segment. */
29 #define TEXT_SECTION_ASM_OP "\t.text"
30 #define DATA_SECTION_ASM_OP "\t.data"
31 #define BSS_SECTION_ASM_OP "\t.bss"
33 /* Note: If USER_LABEL_PREFIX or LOCAL_LABEL_PREFIX are changed,
34 make sure that this change is reflected in the function
35 coff_arm_is_local_label_name() in bfd/coff-arm.c. */
36 #ifndef REGISTER_PREFIX
37 #define REGISTER_PREFIX ""
40 #ifndef USER_LABEL_PREFIX
41 #define USER_LABEL_PREFIX "_"
44 #ifndef LOCAL_LABEL_PREFIX
45 #define LOCAL_LABEL_PREFIX ""
48 /* The assembler's names for the registers. Note that the ?xx registers are
49 there so that VFPv3/NEON registers D16-D31 have the same spacing as D0-D15
50 (each of which is overlaid on two S registers), although there are no
51 actual single-precision registers which correspond to D16-D31. */
52 #ifndef REGISTER_NAMES
53 #define REGISTER_NAMES \
55 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
56 "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc", \
57 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
58 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
59 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
60 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
61 "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
62 "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
63 "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
64 "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
65 "wr0", "wr1", "wr2", "wr3", \
66 "wr4", "wr5", "wr6", "wr7", \
67 "wr8", "wr9", "wr10", "wr11", \
68 "wr12", "wr13", "wr14", "wr15", \
69 "wcgr0", "wcgr1", "wcgr2", "wcgr3", \
70 "cc", "vfpcc", "sfp", "afp" \
74 #ifndef ADDITIONAL_REGISTER_NAMES
75 #define ADDITIONAL_REGISTER_NAMES \
87 {"rfp", 9}, /* Historical. */ \
88 {"sb", 9}, /* Historical. */ \
90 {"sl", 10}, /* Historical. */ \
91 {"r11", 11}, /* fp */ \
92 {"r12", 12}, /* ip */ \
93 {"r13", 13}, /* sp */ \
94 {"r14", 14}, /* lr */ \
95 {"r15", 15} /* pc */ \
99 #ifndef OVERLAPPING_REGISTER_NAMES
100 #define OVERLAPPING_REGISTER_NAMES \
102 {"d0", FIRST_VFP_REGNUM + 0, 2}, \
103 {"d1", FIRST_VFP_REGNUM + 2, 2}, \
104 {"d2", FIRST_VFP_REGNUM + 4, 2}, \
105 {"d3", FIRST_VFP_REGNUM + 6, 2}, \
106 {"d4", FIRST_VFP_REGNUM + 8, 2}, \
107 {"d5", FIRST_VFP_REGNUM + 10, 2}, \
108 {"d6", FIRST_VFP_REGNUM + 12, 2}, \
109 {"d7", FIRST_VFP_REGNUM + 14, 2}, \
110 {"d8", FIRST_VFP_REGNUM + 16, 2}, \
111 {"d9", FIRST_VFP_REGNUM + 18, 2}, \
112 {"d10", FIRST_VFP_REGNUM + 20, 2}, \
113 {"d11", FIRST_VFP_REGNUM + 22, 2}, \
114 {"d12", FIRST_VFP_REGNUM + 24, 2}, \
115 {"d13", FIRST_VFP_REGNUM + 26, 2}, \
116 {"d14", FIRST_VFP_REGNUM + 28, 2}, \
117 {"d15", FIRST_VFP_REGNUM + 30, 2}, \
118 {"q0", FIRST_VFP_REGNUM + 0, 4}, \
119 {"q1", FIRST_VFP_REGNUM + 4, 4}, \
120 {"q2", FIRST_VFP_REGNUM + 8, 4}, \
121 {"q3", FIRST_VFP_REGNUM + 12, 4}, \
122 {"q4", FIRST_VFP_REGNUM + 16, 4}, \
123 {"q5", FIRST_VFP_REGNUM + 20, 4}, \
124 {"q6", FIRST_VFP_REGNUM + 24, 4}, \
125 {"q7", FIRST_VFP_REGNUM + 28, 4}, \
126 {"q8", FIRST_VFP_REGNUM + 32, 4}, \
127 {"q9", FIRST_VFP_REGNUM + 36, 4}, \
128 {"q10", FIRST_VFP_REGNUM + 40, 4}, \
129 {"q11", FIRST_VFP_REGNUM + 44, 4}, \
130 {"q12", FIRST_VFP_REGNUM + 48, 4}, \
131 {"q13", FIRST_VFP_REGNUM + 52, 4}, \
132 {"q14", FIRST_VFP_REGNUM + 56, 4}, \
133 {"q15", FIRST_VFP_REGNUM + 60, 4} \
137 #ifndef NO_DOLLAR_IN_LABEL
138 #define NO_DOLLAR_IN_LABEL 1
141 /* Generate DBX debugging information. riscix.h will undefine this because
142 the native assembler does not support stabs. */
143 #define DBX_DEBUGGING_INFO 1
145 /* Acorn dbx moans about continuation chars, so don't use any. */
146 #ifndef DBX_CONTIN_LENGTH
147 #define DBX_CONTIN_LENGTH 0
150 /* Output a function label definition. */
151 #ifndef ASM_DECLARE_FUNCTION_NAME
152 #define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
155 ARM_DECLARE_FUNCTION_NAME (STREAM, NAME, DECL); \
156 ASM_OUTPUT_LABEL (STREAM, NAME); \
161 /* Globalizing directive for a label. */
162 #define GLOBAL_ASM_OP "\t.global\t"
164 /* Make an internal label into a string. */
165 #ifndef ASM_GENERATE_INTERNAL_LABEL
166 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
167 sprintf (STRING, "*%s%s%u", LOCAL_LABEL_PREFIX, PREFIX, (unsigned int)(NUM))
170 /* Output an element of a dispatch table. */
171 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
174 gcc_assert (!TARGET_THUMB2); \
175 asm_fprintf (STREAM, "\t.word\t%LL%d\n", VALUE); \
180 /* Thumb-2 always uses addr_diff_elf so that the Table Branch instructions
181 can be used. For non-pic code where the offsets do not suitable for
182 TBB/TBH the elements are output as absolute labels. */
183 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
187 asm_fprintf (STREAM, "\tb\t%LL%d\n", VALUE); \
188 else if (TARGET_THUMB1) \
190 if (flag_pic || optimize_size) \
192 switch (GET_MODE(body)) \
195 asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \
198 case HImode: /* TBH */ \
199 asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \
203 asm_fprintf (STREAM, "\t.word\t%LL%d-%LL%d\n", \
211 asm_fprintf (STREAM, "\t.word\t%LL%d+1\n", VALUE); \
215 switch (GET_MODE(body)) \
217 case QImode: /* TBB */ \
218 asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \
221 case HImode: /* TBH */ \
222 asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \
227 asm_fprintf (STREAM, "\t.word\t%LL%d+1-%LL%d\n", VALUE, REL); \
229 asm_fprintf (STREAM, "\t.word\t%LL%d+1\n", VALUE); \
239 #undef ASM_OUTPUT_ASCII
240 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
241 output_ascii_pseudo_op (STREAM, (const unsigned char *) (PTR), LEN)
243 /* Output a gap. In fact we fill it with nulls. */
244 #undef ASM_OUTPUT_SKIP
245 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
246 fprintf (STREAM, "\t.space\t%d\n", (int) (NBYTES))
248 /* Align output to a power of two. Horrible /bin/as. */
249 #ifndef ASM_OUTPUT_ALIGN
250 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
253 register int amount = 1 << (POWER); \
256 fprintf (STREAM, "\t.even\n"); \
257 else if (amount != 1) \
258 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
263 /* Output a common block. */
264 #ifndef ASM_OUTPUT_COMMON
265 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
268 fprintf (STREAM, "\t.comm\t"); \
269 assemble_name (STREAM, NAME); \
270 asm_fprintf (STREAM, ", %d\t%@ %d\n", \
271 (int)(ROUNDED), (int)(SIZE)); \
276 /* Output a local common block. /bin/as can't do this, so hack a
277 `.space' into the bss segment. Note that this is *bad* practice,
278 which is guaranteed NOT to work since it doesn't define STATIC
279 COMMON space but merely STATIC BSS space. */
280 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
281 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
284 switch_to_section (bss_section); \
285 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
286 ASM_OUTPUT_LABEL (STREAM, NAME); \
287 fprintf (STREAM, "\t.space\t%d\n", (int)(SIZE)); \
292 /* Output a zero-initialized block. */
293 #ifndef ASM_OUTPUT_ALIGNED_BSS
294 #define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGN) \
295 asm_output_aligned_bss (STREAM, DECL, NAME, SIZE, ALIGN)
298 #ifndef ASM_COMMENT_START
299 #define ASM_COMMENT_START "@"
302 /* This works for GAS and some other assemblers. */
303 #define SET_ASM_OP "\t.set\t"