1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Target CPU builtins. */
24 #define TARGET_CPU_CPP_BUILTINS() \
27 builtin_define ("__alpha"); \
28 builtin_define ("__alpha__"); \
29 builtin_assert ("cpu=alpha"); \
30 builtin_assert ("machine=alpha"); \
33 builtin_define ("__alpha_cix__"); \
34 builtin_assert ("cpu=cix"); \
38 builtin_define ("__alpha_fix__"); \
39 builtin_assert ("cpu=fix"); \
43 builtin_define ("__alpha_bwx__"); \
44 builtin_assert ("cpu=bwx"); \
48 builtin_define ("__alpha_max__"); \
49 builtin_assert ("cpu=max"); \
53 builtin_define ("__alpha_ev6__"); \
54 builtin_assert ("cpu=ev6"); \
56 else if (TARGET_CPU_EV5) \
58 builtin_define ("__alpha_ev5__"); \
59 builtin_assert ("cpu=ev5"); \
61 else /* Presumably ev4. */ \
63 builtin_define ("__alpha_ev4__"); \
64 builtin_assert ("cpu=ev4"); \
66 if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \
67 builtin_define ("_IEEE_FP"); \
68 if (TARGET_IEEE_WITH_INEXACT) \
69 builtin_define ("_IEEE_FP_INEXACT"); \
71 /* Macros dependent on the C dialect. */ \
72 SUBTARGET_LANGUAGE_CPP_BUILTINS(); \
75 #ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS
76 #define SUBTARGET_LANGUAGE_CPP_BUILTINS() \
79 if (preprocessing_asm_p ()) \
80 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
81 else if (c_language == clk_c) \
82 builtin_define_std ("LANGUAGE_C"); \
83 else if (c_language == clk_cplusplus) \
85 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
86 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
90 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
91 builtin_define ("__LANGUAGE_OBJECTIVE_C__"); \
97 #define CPP_SPEC "%(cpp_subtarget)"
99 #ifndef CPP_SUBTARGET_SPEC
100 #define CPP_SUBTARGET_SPEC ""
103 #define WORD_SWITCH_TAKES_ARG(STR) \
104 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
106 /* Print subsidiary information on the compiler version in use. */
107 #define TARGET_VERSION
109 /* Run-time compilation parameters selecting different hardware subsets. */
111 /* Which processor to schedule for. The cpu attribute defines a list that
112 mirrors this list, so changes to alpha.md must be made at the same time. */
115 {PROCESSOR_EV4, /* 2106[46]{a,} */
116 PROCESSOR_EV5, /* 21164{a,pc,} */
117 PROCESSOR_EV6}; /* 21264 */
119 extern enum processor_type alpha_cpu;
121 enum alpha_trap_precision
123 ALPHA_TP_PROG, /* No precision (default). */
124 ALPHA_TP_FUNC, /* Trap contained within originating function. */
125 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
128 enum alpha_fp_rounding_mode
130 ALPHA_FPRM_NORM, /* Normal rounding mode. */
131 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
132 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
133 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
136 enum alpha_fp_trap_mode
138 ALPHA_FPTM_N, /* Normal trap mode. */
139 ALPHA_FPTM_U, /* Underflow traps enabled. */
140 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
141 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
144 extern int target_flags;
146 extern enum alpha_trap_precision alpha_tp;
147 extern enum alpha_fp_rounding_mode alpha_fprm;
148 extern enum alpha_fp_trap_mode alpha_fptm;
149 extern int alpha_tls_size;
151 /* This means that floating-point support exists in the target implementation
152 of the Alpha architecture. This is usually the default. */
153 #define MASK_FP (1 << 0)
154 #define TARGET_FP (target_flags & MASK_FP)
156 /* This means that floating-point registers are allowed to be used. Note
157 that Alpha implementations without FP operations are required to
158 provide the FP registers. */
160 #define MASK_FPREGS (1 << 1)
161 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
163 /* This means that gas is used to process the assembler file. */
165 #define MASK_GAS (1 << 2)
166 #define TARGET_GAS (target_flags & MASK_GAS)
168 /* This means that we should mark procedures as IEEE conformant. */
170 #define MASK_IEEE_CONFORMANT (1 << 3)
171 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
173 /* This means we should be IEEE-compliant except for inexact. */
175 #define MASK_IEEE (1 << 4)
176 #define TARGET_IEEE (target_flags & MASK_IEEE)
178 /* This means we should be fully IEEE-compliant. */
180 #define MASK_IEEE_WITH_INEXACT (1 << 5)
181 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
183 /* This means we must construct all constants rather than emitting
184 them as literal data. */
186 #define MASK_BUILD_CONSTANTS (1 << 6)
187 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
189 /* This means we handle floating points in VAX F- (float)
190 or G- (double) Format. */
192 #define MASK_FLOAT_VAX (1 << 7)
193 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
195 /* This means that the processor has byte and half word loads and stores
196 (the BWX extension). */
198 #define MASK_BWX (1 << 8)
199 #define TARGET_BWX (target_flags & MASK_BWX)
201 /* This means that the processor has the MAX extension. */
202 #define MASK_MAX (1 << 9)
203 #define TARGET_MAX (target_flags & MASK_MAX)
205 /* This means that the processor has the FIX extension. */
206 #define MASK_FIX (1 << 10)
207 #define TARGET_FIX (target_flags & MASK_FIX)
209 /* This means that the processor has the CIX extension. */
210 #define MASK_CIX (1 << 11)
211 #define TARGET_CIX (target_flags & MASK_CIX)
213 /* This means use !literal style explicit relocations. */
214 #define MASK_EXPLICIT_RELOCS (1 << 12)
215 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
217 /* This means use 16-bit relocations to .sdata/.sbss. */
218 #define MASK_SMALL_DATA (1 << 13)
219 #define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)
221 /* This means emit thread pointer loads for kernel not user. */
222 #define MASK_TLS_KERNEL (1 << 14)
223 #define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL)
225 /* This means that the processor is an EV5, EV56, or PCA56.
226 Unlike alpha_cpu this is not affected by -mtune= setting. */
227 #define MASK_CPU_EV5 (1 << 28)
228 #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
230 /* Likewise for EV6. */
231 #define MASK_CPU_EV6 (1 << 29)
232 #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
234 /* This means we support the .arch directive in the assembler. Only
235 defined in TARGET_CPU_DEFAULT. */
236 #define MASK_SUPPORT_ARCH (1 << 30)
237 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
239 /* These are for target os support and cannot be changed at runtime. */
240 #define TARGET_ABI_WINDOWS_NT 0
241 #define TARGET_ABI_OPEN_VMS 0
242 #define TARGET_ABI_UNICOSMK 0
243 #define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT \
244 && !TARGET_ABI_OPEN_VMS \
245 && !TARGET_ABI_UNICOSMK)
247 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
248 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
250 #ifndef TARGET_AS_SLASH_BEFORE_SUFFIX
251 #define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS
253 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
254 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
256 #ifndef TARGET_HAS_XFLOATING_LIBS
257 #define TARGET_HAS_XFLOATING_LIBS 0
259 #ifndef TARGET_PROFILING_NEEDS_GP
260 #define TARGET_PROFILING_NEEDS_GP 0
262 #ifndef TARGET_LD_BUGGY_LDGP
263 #define TARGET_LD_BUGGY_LDGP 0
265 #ifndef TARGET_FIXUP_EV5_PREFETCH
266 #define TARGET_FIXUP_EV5_PREFETCH 0
269 #define HAVE_AS_TLS 0
272 /* Macro to define tables used to set the flags.
273 This is a list in braces of pairs in braces,
274 each pair being { "NAME", VALUE }
275 where VALUE is the bits to set or minus the bits to clear.
276 An empty string NAME is used to identify the default VALUE. */
278 #define TARGET_SWITCHES \
279 { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
280 {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
281 {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
282 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
283 N_("Do not use fp registers")}, \
284 {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
285 {"gas", MASK_GAS, N_("Assume GAS")}, \
286 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
287 N_("Request IEEE-conformant math library routines (OSF/1)")}, \
288 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
289 N_("Emit IEEE-conformant code, without inexact exceptions")}, \
290 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
291 N_("Emit IEEE-conformant code, with inexact exceptions")}, \
292 {"build-constants", MASK_BUILD_CONSTANTS, \
293 N_("Do not emit complex integer constants to read-only memory")}, \
294 {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
295 {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
296 {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
297 {"no-bwx", -MASK_BWX, ""}, \
299 N_("Emit code for the motion video ISA extension")}, \
300 {"no-max", -MASK_MAX, ""}, \
302 N_("Emit code for the fp move and sqrt ISA extension")}, \
303 {"no-fix", -MASK_FIX, ""}, \
304 {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
305 {"no-cix", -MASK_CIX, ""}, \
306 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
307 N_("Emit code using explicit relocation directives")}, \
308 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \
309 {"small-data", MASK_SMALL_DATA, \
310 N_("Emit 16-bit relocations to the small data areas")}, \
311 {"large-data", -MASK_SMALL_DATA, \
312 N_("Emit 32-bit relocations to the small data areas")}, \
313 {"tls-kernel", MASK_TLS_KERNEL, \
314 N_("Emit rdval instead of rduniq for thread pointer")}, \
315 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \
316 | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} }
318 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
320 #ifndef TARGET_CPU_DEFAULT
321 #define TARGET_CPU_DEFAULT 0
324 #ifndef TARGET_DEFAULT_EXPLICIT_RELOCS
325 #ifdef HAVE_AS_EXPLICIT_RELOCS
326 #define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS
328 #define TARGET_DEFAULT_EXPLICIT_RELOCS 0
332 extern const char *alpha_cpu_string; /* For -mcpu= */
333 extern const char *alpha_tune_string; /* For -mtune= */
334 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
335 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
336 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
337 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
338 extern const char *alpha_tls_size_string; /* For -mtls-size= */
340 #define TARGET_OPTIONS \
342 {"cpu=", &alpha_cpu_string, \
343 N_("Use features of and schedule given CPU")}, \
344 {"tune=", &alpha_tune_string, \
345 N_("Schedule given CPU")}, \
346 {"fp-rounding-mode=", &alpha_fprm_string, \
347 N_("Control the generated fp rounding mode")}, \
348 {"fp-trap-mode=", &alpha_fptm_string, \
349 N_("Control the IEEE trap mode")}, \
350 {"trap-precision=", &alpha_tp_string, \
351 N_("Control the precision given to fp exceptions")}, \
352 {"memory-latency=", &alpha_mlat_string, \
353 N_("Tune expected memory latency")}, \
354 {"tls-size=", &alpha_tls_size_string, \
355 N_("Specify bit size of immediate TLS offsets")}, \
358 /* This macro defines names of additional specifications to put in the
359 specs that can be used in various specifications like CC1_SPEC. Its
360 definition is an initializer with a subgrouping for each command option.
362 Each subgrouping contains a string constant, that defines the
363 specification name, and a string constant that used by the GNU CC driver
366 Do not define this macro if it does not need to do anything. */
368 #ifndef SUBTARGET_EXTRA_SPECS
369 #define SUBTARGET_EXTRA_SPECS
372 #define EXTRA_SPECS \
373 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
374 SUBTARGET_EXTRA_SPECS
377 /* Sometimes certain combinations of command options do not make sense
378 on a particular target machine. You can define a macro
379 `OVERRIDE_OPTIONS' to take account of this. This macro, if
380 defined, is executed once just after all the command options have
383 On the Alpha, it is used to translate target-option strings into
386 #define OVERRIDE_OPTIONS override_options ()
389 /* Define this macro to change register usage conditional on target flags.
391 On the Alpha, we use this to disable the floating-point registers when
394 #define CONDITIONAL_REGISTER_USAGE \
397 if (! TARGET_FPREGS) \
398 for (i = 32; i < 63; i++) \
399 fixed_regs[i] = call_used_regs[i] = 1; \
403 /* Show we can debug even without a frame pointer. */
404 #define CAN_DEBUG_WITHOUT_FP
406 /* target machine storage layout */
408 /* Define the size of `int'. The default is the same as the word size. */
409 #define INT_TYPE_SIZE 32
411 /* Define the size of `long long'. The default is the twice the word size. */
412 #define LONG_LONG_TYPE_SIZE 64
414 /* The two floating-point formats we support are S-floating, which is
415 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
416 and `long double' are T. */
418 #define FLOAT_TYPE_SIZE 32
419 #define DOUBLE_TYPE_SIZE 64
420 #define LONG_DOUBLE_TYPE_SIZE 64
422 #define WCHAR_TYPE "unsigned int"
423 #define WCHAR_TYPE_SIZE 32
425 /* Define this macro if it is advisable to hold scalars in registers
426 in a wider mode than that declared by the program. In such cases,
427 the value is constrained to be within the bounds of the declared
428 type, but kept valid in the wider mode. The signedness of the
429 extension may differ from that of the type.
431 For Alpha, we always store objects in a full register. 32-bit objects
432 are always sign-extended, but smaller objects retain their signedness. */
434 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
435 if (GET_MODE_CLASS (MODE) == MODE_INT \
436 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
438 if ((MODE) == SImode) \
443 /* Define this if function arguments should also be promoted using the above
446 #define PROMOTE_FUNCTION_ARGS
448 /* Likewise, if the function return value is promoted. */
450 #define PROMOTE_FUNCTION_RETURN
452 /* Define this if most significant bit is lowest numbered
453 in instructions that operate on numbered bit-fields.
455 There are no such instructions on the Alpha, but the documentation
457 #define BITS_BIG_ENDIAN 0
459 /* Define this if most significant byte of a word is the lowest numbered.
460 This is false on the Alpha. */
461 #define BYTES_BIG_ENDIAN 0
463 /* Define this if most significant word of a multiword number is lowest
466 For Alpha we can decide arbitrarily since there are no machine instructions
467 for them. Might as well be consistent with bytes. */
468 #define WORDS_BIG_ENDIAN 0
470 /* Width of a word, in units (bytes). */
471 #define UNITS_PER_WORD 8
473 /* Width in bits of a pointer.
474 See also the macro `Pmode' defined below. */
475 #define POINTER_SIZE 64
477 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
478 #define PARM_BOUNDARY 64
480 /* Boundary (in *bits*) on which stack pointer should be aligned. */
481 #define STACK_BOUNDARY 64
483 /* Allocation boundary (in *bits*) for the code of a function. */
484 #define FUNCTION_BOUNDARY 32
486 /* Alignment of field after `int : 0' in a structure. */
487 #define EMPTY_FIELD_BOUNDARY 64
489 /* Every structure's size must be a multiple of this. */
490 #define STRUCTURE_SIZE_BOUNDARY 8
492 /* A bitfield declared as `int' forces `int' alignment for the struct. */
493 #define PCC_BITFIELD_TYPE_MATTERS 1
495 /* No data type wants to be aligned rounder than this. */
496 #define BIGGEST_ALIGNMENT 128
498 /* For atomic access to objects, must have at least 32-bit alignment
499 unless the machine has byte operations. */
500 #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
502 /* Align all constants and variables to at least a word boundary so
503 we can pick up pieces of them faster. */
504 /* ??? Only if block-move stuff knows about different source/destination
507 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
508 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
511 /* Set this non-zero if move instructions will actually fail to work
512 when given unaligned data.
514 Since we get an error message when we do one, call them invalid. */
516 #define STRICT_ALIGNMENT 1
518 /* Set this non-zero if unaligned move instructions are extremely slow.
520 On the Alpha, they trap. */
522 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
524 /* Standard register usage. */
526 /* Number of actual hardware registers.
527 The hardware registers are assigned numbers for the compiler
528 from 0 to just below FIRST_PSEUDO_REGISTER.
529 All registers that the compiler knows about must be given numbers,
530 even those that are not normally considered general registers.
532 We define all 32 integer registers, even though $31 is always zero,
533 and all 32 floating-point registers, even though $f31 is also
534 always zero. We do not bother defining the FP status register and
535 there are no other registers.
537 Since $31 is always zero, we will use register number 31 as the
538 argument pointer. It will never appear in the generated code
539 because we will always be eliminating it in favor of the stack
540 pointer or hardware frame pointer.
542 Likewise, we use $f31 for the frame pointer, which will always
543 be eliminated in favor of the hardware frame pointer or the
546 #define FIRST_PSEUDO_REGISTER 64
548 /* 1 for registers that have pervasive standard uses
549 and are not available for the register allocator. */
551 #define FIXED_REGISTERS \
552 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
553 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
554 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
557 /* 1 for registers not available across function calls.
558 These must include the FIXED_REGISTERS and also any
559 registers that can be used without being saved.
560 The latter must include the registers where values are returned
561 and the register where structure-value addresses are passed.
562 Aside from that, you can include as many other registers as you like. */
563 #define CALL_USED_REGISTERS \
564 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
566 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
569 /* List the order in which to allocate registers. Each register must be
570 listed once, even those in FIXED_REGISTERS.
572 We allocate in the following order:
573 $f10-$f15 (nonsaved floating-point register)
575 $f21-$f16 (likewise, but input args)
576 $f0 (nonsaved, but return value)
577 $f1 (nonsaved, but immediate before saved)
578 $f2-$f9 (saved floating-point registers)
579 $1-$8 (nonsaved integer registers)
582 $0 (likewise, but return value)
583 $21-$16 (likewise, but input args)
584 $27 (procedure value in OSF, nonsaved in NT)
585 $9-$14 (saved integer registers)
589 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
591 #define REG_ALLOC_ORDER \
592 {42, 43, 44, 45, 46, 47, \
593 54, 55, 56, 57, 58, 59, 60, 61, 62, \
594 53, 52, 51, 50, 49, 48, \
596 34, 35, 36, 37, 38, 39, 40, 41, \
597 1, 2, 3, 4, 5, 6, 7, 8, \
601 21, 20, 19, 18, 17, 16, \
603 9, 10, 11, 12, 13, 14, \
609 /* Return number of consecutive hard regs needed starting at reg REGNO
610 to hold something of mode MODE.
611 This is ordinarily the length in words of a value of mode MODE
612 but can be less for certain modes in special long registers. */
614 #define HARD_REGNO_NREGS(REGNO, MODE) \
615 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
617 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
618 On Alpha, the integer registers can hold any mode. The floating-point
619 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
622 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
623 ((REGNO) >= 32 && (REGNO) <= 62 \
624 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
627 /* Value is 1 if MODE is a supported vector mode. */
629 #define VECTOR_MODE_SUPPORTED_P(MODE) \
631 && ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode))
633 /* A C expression that is nonzero if a value of mode
634 MODE1 is accessible in mode MODE2 without copying.
636 This asymmetric test is true when MODE1 could be put
637 in an FP register but MODE2 could not. */
639 #define MODES_TIEABLE_P(MODE1, MODE2) \
640 (HARD_REGNO_MODE_OK (32, (MODE1)) \
641 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
644 /* Specify the registers used for certain standard purposes.
645 The values of these macros are register numbers. */
647 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
648 /* #define PC_REGNUM */
650 /* Register to use for pushing function arguments. */
651 #define STACK_POINTER_REGNUM 30
653 /* Base register for access to local variables of the function. */
654 #define HARD_FRAME_POINTER_REGNUM 15
656 /* Value should be nonzero if functions must have frame pointers.
657 Zero means the frame pointer need not be set up (and parms
658 may be accessed via the stack pointer) in functions that seem suitable.
659 This is computed in `reload', in reload1.c. */
660 #define FRAME_POINTER_REQUIRED 0
662 /* Base register for access to arguments of the function. */
663 #define ARG_POINTER_REGNUM 31
665 /* Base register for access to local variables of function. */
666 #define FRAME_POINTER_REGNUM 63
668 /* Register in which static-chain is passed to a function.
670 For the Alpha, this is based on an example; the calling sequence
671 doesn't seem to specify this. */
672 #define STATIC_CHAIN_REGNUM 1
674 /* The register number of the register used to address a table of
675 static data addresses in memory. */
676 #define PIC_OFFSET_TABLE_REGNUM 29
678 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM'
679 is clobbered by calls. */
680 /* ??? It is and it isn't. It's required to be valid for a given
681 function when the function returns. It isn't clobbered by
682 current_file functions. Moreover, we do not expose the ldgp
683 until after reload, so we're probably safe. */
684 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
686 /* Register in which address to store a structure value
687 arrives in the function. On the Alpha, the address is passed
688 as a hidden argument. */
689 #define STRUCT_VALUE 0
691 /* Define the classes of registers for register constraints in the
692 machine description. Also define ranges of constants.
694 One of the classes must always be named ALL_REGS and include all hard regs.
695 If there is more than one class, another class must be named NO_REGS
696 and contain no registers.
698 The name GENERAL_REGS must be the name of a class (or an alias for
699 another name such as ALL_REGS). This is the class of registers
700 that is allowed by "g" or "r" in a register constraint.
701 Also, registers outside this class are allocated only when
702 instructions express preferences for them.
704 The classes must be numbered in nondecreasing order; that is,
705 a larger-numbered class must never be contained completely
706 in a smaller-numbered class.
708 For any two classes, it is very desirable that there be another
709 class that represents their union. */
712 NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG,
713 GENERAL_REGS, FLOAT_REGS, ALL_REGS,
717 #define N_REG_CLASSES (int) LIM_REG_CLASSES
719 /* Give names of register classes as strings for dump file. */
721 #define REG_CLASS_NAMES \
722 {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \
723 "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
725 /* Define which registers fit in which classes.
726 This is an initializer for a vector of HARD_REG_SET
727 of length N_REG_CLASSES. */
729 #define REG_CLASS_CONTENTS \
730 { {0x00000000, 0x00000000}, /* NO_REGS */ \
731 {0x00000001, 0x00000000}, /* R0_REG */ \
732 {0x01000000, 0x00000000}, /* R24_REG */ \
733 {0x02000000, 0x00000000}, /* R25_REG */ \
734 {0x08000000, 0x00000000}, /* R27_REG */ \
735 {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \
736 {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \
737 {0xffffffff, 0xffffffff} }
739 /* The same information, inverted:
740 Return the class number of the smallest class containing
741 reg number REGNO. This could be a conditional expression
742 or could index an array. */
744 #define REGNO_REG_CLASS(REGNO) \
745 ((REGNO) == 0 ? R0_REG \
746 : (REGNO) == 24 ? R24_REG \
747 : (REGNO) == 25 ? R25_REG \
748 : (REGNO) == 27 ? R27_REG \
749 : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
752 /* The class value for index registers, and the one for base regs. */
753 #define INDEX_REG_CLASS NO_REGS
754 #define BASE_REG_CLASS GENERAL_REGS
756 /* Get reg_class from a letter such as appears in the machine description. */
758 #define REG_CLASS_FROM_LETTER(C) \
759 ((C) == 'a' ? R24_REG \
760 : (C) == 'b' ? R25_REG \
761 : (C) == 'c' ? R27_REG \
762 : (C) == 'f' ? FLOAT_REGS \
763 : (C) == 'v' ? R0_REG \
766 /* Define this macro to change register usage conditional on target flags. */
767 /* #define CONDITIONAL_REGISTER_USAGE */
769 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
770 can be used to stand for particular ranges of immediate operands.
771 This macro defines what the ranges are.
772 C is the letter, and VALUE is a constant value.
773 Return 1 if VALUE is in the range specified by C.
776 `I' is used for the range of constants most insns can contain.
777 `J' is the constant zero.
778 `K' is used for the constant in an LDA insn.
779 `L' is used for the constant in a LDAH insn.
780 `M' is used for the constants that can be AND'ed with using a ZAP insn.
781 `N' is used for complemented 8-bit constants.
782 `O' is used for negated 8-bit constants.
783 `P' is used for the constants 1, 2 and 3. */
785 #define CONST_OK_FOR_LETTER_P alpha_const_ok_for_letter_p
787 /* Similar, but for floating or large integer constants, and defining letters
788 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
790 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
791 that is the operand of a ZAP insn. */
793 #define CONST_DOUBLE_OK_FOR_LETTER_P alpha_const_double_ok_for_letter_p
795 /* Optional extra constraints for this machine.
797 For the Alpha, `Q' means that this is a memory operand but not a
798 reference to an unaligned location.
800 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
803 'S' is a 6-bit constant (valid for a shift insn).
807 'U' is a symbolic operand.
809 'W' is a vector zero. */
811 #define EXTRA_CONSTRAINT alpha_extra_constraint
813 /* Given an rtx X being reloaded into a reg required to be
814 in class CLASS, return the class of reg to actually use.
815 In general this is just CLASS; but on some machines
816 in some cases it is preferable to use a more restrictive class. */
818 #define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class
820 /* Loading and storing HImode or QImode values to and from memory
821 usually requires a scratch register. The exceptions are loading
822 QImode and HImode from an aligned address to a general register
823 unless byte instructions are permitted.
824 We also cannot load an unaligned address or a paradoxical SUBREG into an
827 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
828 secondary_reload_class((CLASS), (MODE), (IN), 1)
830 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
831 secondary_reload_class((CLASS), (MODE), (OUT), 0)
833 /* If we are copying between general and FP registers, we need a memory
834 location unless the FIX extension is available. */
836 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
837 (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \
838 || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS)))
840 /* Specify the mode to be used for memory when a secondary memory
841 location is needed. If MODE is floating-point, use it. Otherwise,
842 widen to a word like the default. This is needed because we always
843 store integers in FP registers in quadword format. This whole
844 area is very tricky! */
845 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
846 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
847 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
848 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
850 /* Return the maximum number of consecutive registers
851 needed to represent mode MODE in a register of class CLASS. */
853 #define CLASS_MAX_NREGS(CLASS, MODE) \
854 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
856 /* If defined, gives a class of registers that cannot be used as the
857 operand of a SUBREG that changes the mode of the object illegally. */
859 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
861 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
863 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
864 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
866 /* Define the cost of moving between registers of various classes. Moving
867 between FLOAT_REGS and anything else except float regs is expensive.
868 In fact, we make it quite expensive because we really don't want to
869 do these moves unless it is clearly worth it. Optimizations may
870 reduce the impact of not being able to allocate a pseudo to a
873 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
874 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
876 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
878 /* A C expressions returning the cost of moving data of MODE from a register to
881 On the Alpha, bump this up a bit. */
883 extern int alpha_memory_latency;
884 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
886 /* Provide the cost of a branch. Exact meaning under development. */
887 #define BRANCH_COST 5
889 /* Stack layout; function entry, exit and calling. */
891 /* Define this if pushing a word on the stack
892 makes the stack pointer a smaller address. */
893 #define STACK_GROWS_DOWNWARD
895 /* Define this if the nominal address of the stack frame
896 is at the high-address end of the local variables;
897 that is, each additional local variable allocated
898 goes at a more negative offset in the frame. */
899 /* #define FRAME_GROWS_DOWNWARD */
901 /* Offset within stack frame to start allocating local variables at.
902 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
903 first local allocated. Otherwise, it is the offset to the BEGINNING
904 of the first local allocated. */
906 #define STARTING_FRAME_OFFSET 0
908 /* If we generate an insn to push BYTES bytes,
909 this says how many the stack pointer really advances by.
910 On Alpha, don't define this because there are no push insns. */
911 /* #define PUSH_ROUNDING(BYTES) */
913 /* Define this to be nonzero if stack checking is built into the ABI. */
914 #define STACK_CHECK_BUILTIN 1
916 /* Define this if the maximum size of all the outgoing args is to be
917 accumulated and pushed during the prologue. The amount can be
918 found in the variable current_function_outgoing_args_size. */
919 #define ACCUMULATE_OUTGOING_ARGS 1
921 /* Offset of first parameter from the argument pointer register value. */
923 #define FIRST_PARM_OFFSET(FNDECL) 0
925 /* Definitions for register eliminations.
927 We have two registers that can be eliminated on the Alpha. First, the
928 frame pointer register can often be eliminated in favor of the stack
929 pointer register. Secondly, the argument pointer register can always be
930 eliminated; it is replaced with either the stack or frame pointer. */
932 /* This is an array of structures. Each structure initializes one pair
933 of eliminable registers. The "from" register number is given first,
934 followed by "to". Eliminations of the same "from" register are listed
935 in order of preference. */
937 #define ELIMINABLE_REGS \
938 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
939 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
940 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
941 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
943 /* Given FROM and TO register numbers, say whether this elimination is allowed.
944 Frame pointer elimination is automatically handled.
946 All eliminations are valid since the cases where FP can't be
947 eliminated are already handled. */
949 #define CAN_ELIMINATE(FROM, TO) 1
951 /* Round up to a multiple of 16 bytes. */
952 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
954 /* Define the offset between two registers, one to be eliminated, and the other
955 its replacement, at the start of a routine. */
956 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
957 { if ((FROM) == FRAME_POINTER_REGNUM) \
958 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
959 + alpha_sa_size ()); \
960 else if ((FROM) == ARG_POINTER_REGNUM) \
961 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
963 + (ALPHA_ROUND (get_frame_size () \
964 + current_function_pretend_args_size) \
965 - current_function_pretend_args_size)); \
970 /* Define this if stack space is still allocated for a parameter passed
972 /* #define REG_PARM_STACK_SPACE */
974 /* Value is the number of bytes of arguments automatically
975 popped when returning from a subroutine call.
976 FUNDECL is the declaration node of the function (as a tree),
977 FUNTYPE is the data type of the function (as a tree),
978 or for a library call it is an identifier node for the subroutine name.
979 SIZE is the number of bytes of arguments passed on the stack. */
981 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
983 /* Define how to find the value returned by a function.
984 VALTYPE is the data type of the value (as a tree).
985 If the precise function being called is known, FUNC is its FUNCTION_DECL;
986 otherwise, FUNC is 0.
988 On Alpha the value is found in $0 for integer functions and
989 $f0 for floating-point functions. */
991 #define FUNCTION_VALUE(VALTYPE, FUNC) \
992 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
993 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
994 || POINTER_TYPE_P (VALTYPE)) \
995 ? word_mode : TYPE_MODE (VALTYPE), \
997 && (TREE_CODE (VALTYPE) == REAL_TYPE \
998 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1001 /* Define how to find the value returned by a library function
1002 assuming the value has mode MODE. */
1004 #define LIBCALL_VALUE(MODE) \
1005 gen_rtx_REG (MODE, \
1007 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1008 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1011 /* The definition of this macro implies that there are cases where
1012 a scalar value cannot be returned in registers.
1014 For the Alpha, any structure or union type is returned in memory, as
1015 are integers whose size is larger than 64 bits. */
1017 #define RETURN_IN_MEMORY(TYPE) \
1018 (TYPE_MODE (TYPE) == BLKmode \
1019 || TYPE_MODE (TYPE) == TFmode \
1020 || TYPE_MODE (TYPE) == TCmode \
1021 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1023 /* 1 if N is a possible register number for a function value
1024 as seen by the caller. */
1026 #define FUNCTION_VALUE_REGNO_P(N) \
1027 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1029 /* 1 if N is a possible register number for function argument passing.
1030 On Alpha, these are $16-$21 and $f16-$f21. */
1032 #define FUNCTION_ARG_REGNO_P(N) \
1033 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1035 /* Define a data type for recording info about an argument list
1036 during the scan of that argument list. This data type should
1037 hold all necessary information about the function itself
1038 and about the args processed so far, enough to enable macros
1039 such as FUNCTION_ARG to determine where the next arg should go.
1041 On Alpha, this is a single integer, which is a number of words
1042 of arguments scanned so far.
1043 Thus 6 or more means all following args should go on the stack. */
1045 #define CUMULATIVE_ARGS int
1047 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1048 for a call to a function whose data type is FNTYPE.
1049 For a library call, FNTYPE is 0. */
1051 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1053 /* Define intermediate macro to compute the size (in registers) of an argument
1056 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1057 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1058 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1059 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1061 /* Update the data in CUM to advance over an argument
1062 of mode MODE and data type TYPE.
1063 (TYPE is null for libcalls where that information may not be available.) */
1065 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1066 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1069 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1071 /* Determine where to put an argument to a function.
1072 Value is zero to push the argument on the stack,
1073 or a hard register in which to store the argument.
1075 MODE is the argument's machine mode.
1076 TYPE is the data type of the argument (as a tree).
1077 This is null for libcalls where that information may
1079 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1080 the preceding args and about the function being called.
1081 NAMED is nonzero if this argument is a named parameter
1082 (otherwise it is an extra parameter matching an ellipsis).
1084 On Alpha the first 6 words of args are normally in registers
1085 and the rest are pushed. */
1087 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1088 function_arg((CUM), (MODE), (TYPE), (NAMED))
1090 /* A C expression that indicates when an argument must be passed by
1091 reference. If nonzero for an argument, a copy of that argument is
1092 made in memory and a pointer to the argument is passed instead of
1093 the argument itself. The pointer is passed in whatever way is
1094 appropriate for passing a pointer to that type. */
1096 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1097 ((MODE) == TFmode || (MODE) == TCmode)
1099 /* Specify the padding direction of arguments.
1101 On the Alpha, we must pad upwards in order to be able to pass args in
1104 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1106 /* For an arg passed partly in registers and partly in memory,
1107 this is the number of registers used.
1108 For args passed entirely in registers or entirely in memory, zero. */
1110 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1111 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1114 /* Perform any needed actions needed for a function that is receiving a
1115 variable number of arguments.
1119 MODE and TYPE are the mode and type of the current parameter.
1121 PRETEND_SIZE is a variable that should be set to the amount of stack
1122 that must be pushed by the prolog to pretend that our caller pushed
1125 Normally, this macro will push all remaining incoming registers on the
1126 stack and set PRETEND_SIZE to the length of the registers pushed.
1128 On the Alpha, we allocate space for all 12 arg registers, but only
1129 push those that are remaining.
1131 However, if NO registers need to be saved, don't allocate any space.
1132 This is not only because we won't need the space, but because AP includes
1133 the current_pretend_args_size and we don't want to mess up any
1134 ap-relative addresses already made.
1136 If we are not to use the floating-point registers, save the integer
1137 registers where we would put the floating-point registers. This is
1138 not the most efficient way to implement varargs with just one register
1139 class, but it isn't worth doing anything more efficient in this rare
1142 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1147 rtx tmp; int set = get_varargs_alias_set (); \
1148 tmp = gen_rtx_MEM (BLKmode, \
1149 plus_constant (virtual_incoming_args_rtx, \
1150 ((CUM) + 6)* UNITS_PER_WORD)); \
1151 set_mem_alias_set (tmp, set); \
1152 move_block_from_reg \
1154 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1156 tmp = gen_rtx_MEM (BLKmode, \
1157 plus_constant (virtual_incoming_args_rtx, \
1158 (CUM) * UNITS_PER_WORD)); \
1159 set_mem_alias_set (tmp, set); \
1160 move_block_from_reg \
1161 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1162 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1164 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1168 /* We do not allow indirect calls to be optimized into sibling calls, nor
1169 can we allow a call to a function in a different compilation unit to
1170 be optimized into a sibcall. */
1171 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1173 && (! TREE_PUBLIC (DECL) \
1174 || (TREE_ASM_WRITTEN (DECL) && (*targetm.binds_local_p) (DECL))))
1176 /* Try to output insns to set TARGET equal to the constant C if it can be
1177 done in less than N insns. Do all computations in MODE. Returns the place
1178 where the output has been placed if it can be done and the insns have been
1179 emitted. If it would take more than N insns, zero is returned and no
1180 insns and emitted. */
1182 /* Define the information needed to generate branch and scc insns. This is
1183 stored from the compare operation. Note that we can't use "rtx" here
1184 since it hasn't been defined! */
1186 struct alpha_compare
1188 struct rtx_def *op0, *op1;
1192 extern struct alpha_compare alpha_compare;
1194 /* Make (or fake) .linkage entry for function call.
1195 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1197 /* This macro defines the start of an assembly comment. */
1199 #define ASM_COMMENT_START " #"
1201 /* This macro produces the initial definition of a function. */
1203 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1204 alpha_start_function(FILE,NAME,DECL);
1206 /* This macro closes up a function definition for the assembler. */
1208 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1209 alpha_end_function(FILE,NAME,DECL)
1211 /* Output any profiling code before the prologue. */
1213 #define PROFILE_BEFORE_PROLOGUE 1
1215 /* Output assembler code to FILE to increment profiler label # LABELNO
1216 for profiling a function entry. Under OSF/1, profiling is enabled
1217 by simply passing -pg to the assembler and linker. */
1219 #define FUNCTION_PROFILER(FILE, LABELNO)
1221 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1222 the stack pointer does not matter. The value is tested only in
1223 functions that have frame pointers.
1224 No definition is equivalent to always zero. */
1226 #define EXIT_IGNORE_STACK 1
1228 /* Define registers used by the epilogue and return instruction. */
1230 #define EPILOGUE_USES(REGNO) ((REGNO) == 26)
1232 /* Output assembler code for a block containing the constant parts
1233 of a trampoline, leaving space for the variable parts.
1235 The trampoline should set the static chain pointer to value placed
1236 into the trampoline and should branch to the specified routine.
1237 Note that $27 has been set to the address of the trampoline, so we can
1238 use it for addressability of the two data items. */
1240 #define TRAMPOLINE_TEMPLATE(FILE) \
1242 fprintf (FILE, "\tldq $1,24($27)\n"); \
1243 fprintf (FILE, "\tldq $27,16($27)\n"); \
1244 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1245 fprintf (FILE, "\tnop\n"); \
1246 fprintf (FILE, "\t.quad 0,0\n"); \
1249 /* Section in which to place the trampoline. On Alpha, instructions
1250 may only be placed in a text segment. */
1252 #define TRAMPOLINE_SECTION text_section
1254 /* Length in units of the trampoline for entering a nested function. */
1256 #define TRAMPOLINE_SIZE 32
1258 /* The alignment of a trampoline, in bits. */
1260 #define TRAMPOLINE_ALIGNMENT 64
1262 /* Emit RTL insns to initialize the variable parts of a trampoline.
1263 FNADDR is an RTX for the address of the function's pure code.
1264 CXT is an RTX for the static chain value for the function. */
1266 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1267 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1269 /* A C expression whose value is RTL representing the value of the return
1270 address for the frame COUNT steps up from the current frame.
1271 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1272 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1274 #define RETURN_ADDR_RTX alpha_return_addr
1276 /* Before the prologue, RA lives in $26. */
1277 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1278 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
1280 /* Describe how we implement __builtin_eh_return. */
1281 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM)
1282 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28)
1283 #define EH_RETURN_HANDLER_RTX \
1284 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1285 current_function_outgoing_args_size))
1287 /* Addressing modes, and classification of registers for them. */
1289 /* #define HAVE_POST_INCREMENT 0 */
1290 /* #define HAVE_POST_DECREMENT 0 */
1292 /* #define HAVE_PRE_DECREMENT 0 */
1293 /* #define HAVE_PRE_INCREMENT 0 */
1295 /* Macros to check register numbers against specific register classes. */
1297 /* These assume that REGNO is a hard or pseudo reg number.
1298 They give nonzero only if REGNO is a hard reg of the suitable class
1299 or a pseudo reg currently allocated to a suitable hard reg.
1300 Since they use reg_renumber, they are safe only once reg_renumber
1301 has been allocated, which happens in local-alloc.c. */
1303 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1304 #define REGNO_OK_FOR_BASE_P(REGNO) \
1305 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1306 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1308 /* Maximum number of registers that can appear in a valid memory address. */
1309 #define MAX_REGS_PER_ADDRESS 1
1311 /* Recognize any constant value that is a valid address. For the Alpha,
1312 there are only constants none since we want to use LDA to load any
1313 symbolic addresses into registers. */
1315 #define CONSTANT_ADDRESS_P(X) \
1316 (GET_CODE (X) == CONST_INT \
1317 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1319 /* Include all constant integers and constant doubles, but not
1320 floating-point, except for floating-point zero. */
1322 #define LEGITIMATE_CONSTANT_P(X) \
1323 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1324 || (X) == CONST0_RTX (GET_MODE (X)))
1326 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1327 and check its validity for a certain class.
1328 We have two alternate definitions for each of them.
1329 The usual definition accepts all pseudo regs; the other rejects
1330 them unless they have been allocated suitable hard regs.
1331 The symbol REG_OK_STRICT causes the latter definition to be used.
1333 Most source files want to accept pseudo regs in the hope that
1334 they will get allocated to the class that the insn wants them to be in.
1335 Source files for reload pass need to be strict.
1336 After reload, it makes no difference, since pseudo regs have
1337 been eliminated by then. */
1339 /* Nonzero if X is a hard reg that can be used as an index
1340 or if it is a pseudo reg. */
1341 #define REG_OK_FOR_INDEX_P(X) 0
1343 /* Nonzero if X is a hard reg that can be used as a base reg
1344 or if it is a pseudo reg. */
1345 #define NONSTRICT_REG_OK_FOR_BASE_P(X) \
1346 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1348 /* ??? Nonzero if X is the frame pointer, or some virtual register
1349 that may eliminate to the frame pointer. These will be allowed to
1350 have offsets greater than 32K. This is done because register
1351 elimination offsets will change the hi/lo split, and if we split
1352 before reload, we will require additional instructions. */
1353 #define NONSTRICT_REG_OK_FP_BASE_P(X) \
1354 (REGNO (X) == 31 || REGNO (X) == 63 \
1355 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1356 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1358 /* Nonzero if X is a hard reg that can be used as a base reg. */
1359 #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1361 #ifdef REG_OK_STRICT
1362 #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X)
1364 #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X)
1367 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1368 valid memory address for an instruction. */
1370 #ifdef REG_OK_STRICT
1371 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1373 if (alpha_legitimate_address_p (MODE, X, 1)) \
1377 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1379 if (alpha_legitimate_address_p (MODE, X, 0)) \
1384 /* Try machine-dependent ways of modifying an illegitimate address
1385 to be legitimate. If we find one, return the new, valid address.
1386 This macro is used in only one place: `memory_address' in explow.c. */
1388 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1390 rtx new_x = alpha_legitimize_address (X, NULL_RTX, MODE); \
1398 /* Try a machine-dependent way of reloading an illegitimate address
1399 operand. If we find one, push the reload and jump to WIN. This
1400 macro is used in only one place: `find_reloads_address' in reload.c. */
1402 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
1404 rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
1412 /* Go to LABEL if ADDR (a legitimate address expression)
1413 has an effect that depends on the machine mode it is used for.
1414 On the Alpha this is true only for the unaligned modes. We can
1415 simplify this test since we know that the address must be valid. */
1417 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1418 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1420 /* Compute the cost of an address. For the Alpha, all valid addresses are
1423 #define ADDRESS_COST(X) 0
1425 /* Machine-dependent reorg pass. */
1426 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1428 /* Specify the machine mode that this machine uses
1429 for the index in the tablejump instruction. */
1430 #define CASE_VECTOR_MODE SImode
1432 /* Define as C expression which evaluates to nonzero if the tablejump
1433 instruction expects the table to contain offsets from the address of the
1436 Do not define this if the table should contain absolute addresses.
1437 On the Alpha, the table is really GP-relative, not relative to the PC
1438 of the table, but we pretend that it is PC-relative; this should be OK,
1439 but we should try to find some better way sometime. */
1440 #define CASE_VECTOR_PC_RELATIVE 1
1442 /* Define this as 1 if `char' should by default be signed; else as 0. */
1443 #define DEFAULT_SIGNED_CHAR 1
1445 /* This flag, if defined, says the same insns that convert to a signed fixnum
1446 also convert validly to an unsigned one.
1448 We actually lie a bit here as overflow conditions are different. But
1449 they aren't being checked anyway. */
1451 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1453 /* Max number of bytes we can move to or from memory
1454 in one reasonably fast instruction. */
1458 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1459 move-instruction pairs, we will do a movstr or libcall instead.
1461 Without byte/word accesses, we want no more than four instructions;
1462 with, several single byte accesses are better. */
1464 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1466 /* Largest number of bytes of an object that can be placed in a register.
1467 On the Alpha we have plenty of registers, so use TImode. */
1468 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1470 /* Nonzero if access to memory by bytes is no faster than for words.
1471 Also non-zero if doing byte operations (specifically shifts) in registers
1474 On the Alpha, we want to not use the byte operation and instead use
1475 masking operations to access fields; these will save instructions. */
1477 #define SLOW_BYTE_ACCESS 1
1479 /* Define if operations between registers always perform the operation
1480 on the full register even if a narrower mode is specified. */
1481 #define WORD_REGISTER_OPERATIONS
1483 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1484 will either zero-extend or sign-extend. The value of this macro should
1485 be the code that says which one of the two operations is implicitly
1486 done, NIL if none. */
1487 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1489 /* Define if loading short immediate values into registers sign extends. */
1490 #define SHORT_IMMEDIATES_SIGN_EXTEND
1492 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1493 is done just by pretending it is already truncated. */
1494 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1496 /* We assume that the store-condition-codes instructions store 0 for false
1497 and some other value for true. This is the value stored for true. */
1499 #define STORE_FLAG_VALUE 1
1501 /* Define the value returned by a floating-point comparison instruction. */
1503 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1504 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1506 /* Canonicalize a comparison from one we don't have to one we do have. */
1508 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1510 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1511 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1516 (CODE) = swap_condition (CODE); \
1518 if (((CODE) == LT || (CODE) == LTU) \
1519 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1521 (CODE) = (CODE) == LT ? LE : LEU; \
1522 (OP1) = GEN_INT (255); \
1526 /* Specify the machine mode that pointers have.
1527 After generation of rtl, the compiler makes no further distinction
1528 between pointers and any other objects of this machine mode. */
1529 #define Pmode DImode
1531 /* Mode of a function address in a call instruction (for indexing purposes). */
1533 #define FUNCTION_MODE Pmode
1535 /* Define this if addresses of constant functions
1536 shouldn't be put through pseudo regs where they can be cse'd.
1537 Desirable on machines where ordinary constants are expensive
1538 but a CALL with constant address is cheap.
1540 We define this on the Alpha so that gen_call and gen_call_value
1541 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1542 then copy it into a register, thus actually letting the address be
1545 #define NO_FUNCTION_CSE
1547 /* Define this to be nonzero if shift instructions ignore all but the low-order
1549 #define SHIFT_COUNT_TRUNCATED 1
1551 /* Compute the cost of computing a constant rtl expression RTX
1552 whose rtx-code is CODE. The body of this macro is a portion
1553 of a switch statement. If the code is computed here,
1554 return it with a return statement. Otherwise, break from the switch.
1556 If this is an 8-bit constant, return zero since it can be used
1557 nearly anywhere with no cost. If it is a valid operand for an
1558 ADD or AND, likewise return 0 if we know it will be used in that
1559 context. Otherwise, return 2 since it might be used there later.
1560 All other constants take at least two insns. */
1562 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1564 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1566 case CONST_DOUBLE: \
1567 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1569 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1570 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1572 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1575 return COSTS_N_INSNS (2); \
1579 switch (alpha_cpu) \
1581 case PROCESSOR_EV4: \
1582 return COSTS_N_INSNS (3); \
1583 case PROCESSOR_EV5: \
1584 case PROCESSOR_EV6: \
1585 return COSTS_N_INSNS (2); \
1589 /* Provide the costs of a rtl expression. This is in the body of a
1592 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1593 case PLUS: case MINUS: \
1594 if (FLOAT_MODE_P (GET_MODE (X))) \
1595 switch (alpha_cpu) \
1597 case PROCESSOR_EV4: \
1598 return COSTS_N_INSNS (6); \
1599 case PROCESSOR_EV5: \
1600 case PROCESSOR_EV6: \
1601 return COSTS_N_INSNS (4); \
1604 else if (GET_CODE (XEXP (X, 0)) == MULT \
1605 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1606 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1607 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1610 switch (alpha_cpu) \
1612 case PROCESSOR_EV4: \
1613 if (FLOAT_MODE_P (GET_MODE (X))) \
1614 return COSTS_N_INSNS (6); \
1615 return COSTS_N_INSNS (23); \
1616 case PROCESSOR_EV5: \
1617 if (FLOAT_MODE_P (GET_MODE (X))) \
1618 return COSTS_N_INSNS (4); \
1619 else if (GET_MODE (X) == DImode) \
1620 return COSTS_N_INSNS (12); \
1622 return COSTS_N_INSNS (8); \
1623 case PROCESSOR_EV6: \
1624 if (FLOAT_MODE_P (GET_MODE (X))) \
1625 return COSTS_N_INSNS (4); \
1627 return COSTS_N_INSNS (7); \
1631 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1632 && INTVAL (XEXP (X, 1)) <= 3) \
1634 /* ... fall through ... */ \
1635 case ASHIFTRT: case LSHIFTRT: \
1636 switch (alpha_cpu) \
1638 case PROCESSOR_EV4: \
1639 return COSTS_N_INSNS (2); \
1640 case PROCESSOR_EV5: \
1641 case PROCESSOR_EV6: \
1642 return COSTS_N_INSNS (1); \
1645 case IF_THEN_ELSE: \
1646 switch (alpha_cpu) \
1648 case PROCESSOR_EV4: \
1649 case PROCESSOR_EV6: \
1650 return COSTS_N_INSNS (2); \
1651 case PROCESSOR_EV5: \
1652 return COSTS_N_INSNS (1); \
1655 case DIV: case UDIV: case MOD: case UMOD: \
1656 switch (alpha_cpu) \
1658 case PROCESSOR_EV4: \
1659 if (GET_MODE (X) == SFmode) \
1660 return COSTS_N_INSNS (34); \
1661 else if (GET_MODE (X) == DFmode) \
1662 return COSTS_N_INSNS (63); \
1664 return COSTS_N_INSNS (70); \
1665 case PROCESSOR_EV5: \
1666 if (GET_MODE (X) == SFmode) \
1667 return COSTS_N_INSNS (15); \
1668 else if (GET_MODE (X) == DFmode) \
1669 return COSTS_N_INSNS (22); \
1671 return COSTS_N_INSNS (70); /* ??? */ \
1672 case PROCESSOR_EV6: \
1673 if (GET_MODE (X) == SFmode) \
1674 return COSTS_N_INSNS (12); \
1675 else if (GET_MODE (X) == DFmode) \
1676 return COSTS_N_INSNS (15); \
1678 return COSTS_N_INSNS (70); /* ??? */ \
1682 switch (alpha_cpu) \
1684 case PROCESSOR_EV4: \
1685 case PROCESSOR_EV6: \
1686 return COSTS_N_INSNS (3); \
1687 case PROCESSOR_EV5: \
1688 return COSTS_N_INSNS (2); \
1691 case NEG: case ABS: \
1692 if (! FLOAT_MODE_P (GET_MODE (X))) \
1694 /* ... fall through ... */ \
1695 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1696 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1697 switch (alpha_cpu) \
1699 case PROCESSOR_EV4: \
1700 return COSTS_N_INSNS (6); \
1701 case PROCESSOR_EV5: \
1702 case PROCESSOR_EV6: \
1703 return COSTS_N_INSNS (4); \
1707 /* Control the assembler format that we output. */
1709 /* Output to assembler file text saying following lines
1710 may contain character constants, extra white space, comments, etc. */
1711 #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "")
1713 /* Output to assembler file text saying following lines
1714 no longer contain unusual constructs. */
1715 #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "")
1717 #define TEXT_SECTION_ASM_OP "\t.text"
1719 /* Output before read-only data. */
1721 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
1723 /* Output before writable data. */
1725 #define DATA_SECTION_ASM_OP "\t.data"
1727 /* How to refer to registers in assembler output.
1728 This sequence is indexed by compiler's hard-register-number (see above). */
1730 #define REGISTER_NAMES \
1731 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1732 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1733 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1734 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1735 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1736 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1737 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1738 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1740 /* Strip name encoding when emitting labels. */
1742 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1744 const char *name_ = NAME; \
1745 if (*name_ == '@' || *name_ == '%') \
1747 if (*name_ == '*') \
1750 fputs (user_label_prefix, STREAM); \
1751 fputs (name_, STREAM); \
1754 /* Globalizing directive for a label. */
1755 #define GLOBAL_ASM_OP "\t.globl "
1757 /* The prefix to add to user-visible assembler symbols. */
1759 #define USER_LABEL_PREFIX ""
1761 /* This is how to output an internal numbered label where
1762 PREFIX is the class of label and NUM is the number within the class. */
1764 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1765 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1767 /* This is how to output a label for a jump table. Arguments are the same as
1768 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1771 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1772 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1774 /* This is how to store into the string LABEL
1775 the symbol_ref name of an internal numbered label where
1776 PREFIX is the class of label and NUM is the number within the class.
1777 This is suitable for output with `assemble_name'. */
1779 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1780 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
1782 /* We use the default ASCII-output routine, except that we don't write more
1783 than 50 characters since the assembler doesn't support very long lines. */
1785 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
1787 FILE *_hide_asm_out_file = (MYFILE); \
1788 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
1789 int _hide_thissize = (MYLENGTH); \
1790 int _size_so_far = 0; \
1792 FILE *asm_out_file = _hide_asm_out_file; \
1793 const unsigned char *p = _hide_p; \
1794 int thissize = _hide_thissize; \
1796 fprintf (asm_out_file, "\t.ascii \""); \
1798 for (i = 0; i < thissize; i++) \
1800 register int c = p[i]; \
1802 if (_size_so_far ++ > 50 && i < thissize - 4) \
1803 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
1805 if (c == '\"' || c == '\\') \
1806 putc ('\\', asm_out_file); \
1807 if (c >= ' ' && c < 0177) \
1808 putc (c, asm_out_file); \
1811 fprintf (asm_out_file, "\\%o", c); \
1812 /* After an octal-escape, if a digit follows, \
1813 terminate one string constant and start another. \
1814 The VAX assembler fails to stop reading the escape \
1815 after three digits, so this is the only way we \
1816 can get it to parse the data properly. */ \
1817 if (i < thissize - 1 && ISDIGIT (p[i + 1])) \
1818 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
1821 fprintf (asm_out_file, "\"\n"); \
1826 /* This is how to output an insn to push a register on the stack.
1827 It need not be very fast code. */
1829 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1830 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
1831 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1834 /* This is how to output an insn to pop a register from the stack.
1835 It need not be very fast code. */
1837 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1838 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
1839 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1842 /* This is how to output an element of a case-vector that is absolute.
1843 (Alpha does not use such vectors, but we must define this macro anyway.) */
1845 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
1847 /* This is how to output an element of a case-vector that is relative. */
1849 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1850 fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \
1853 /* This is how to output an assembler line
1854 that says to advance the location counter
1855 to a multiple of 2**LOG bytes. */
1857 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1859 fprintf (FILE, "\t.align %d\n", LOG);
1861 /* This is how to advance the location counter by SIZE bytes. */
1863 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1864 fprintf (FILE, "\t.space %d\n", (SIZE))
1866 /* This says how to output an assembler line
1867 to define a global common symbol. */
1869 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1870 ( fputs ("\t.comm ", (FILE)), \
1871 assemble_name ((FILE), (NAME)), \
1872 fprintf ((FILE), ",%d\n", (SIZE)))
1874 /* This says how to output an assembler line
1875 to define a local common symbol. */
1877 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1878 ( fputs ("\t.lcomm ", (FILE)), \
1879 assemble_name ((FILE), (NAME)), \
1880 fprintf ((FILE), ",%d\n", (SIZE)))
1882 /* Store in OUTPUT a string (made with alloca) containing
1883 an assembler-name for a local static variable named NAME.
1884 LABELNO is an integer which is different for each call. */
1886 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1887 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1888 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1891 /* Print operand X (an rtx) in assembler syntax to file FILE.
1892 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1893 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1895 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1897 /* Determine which codes are valid without a following integer. These must
1900 ~ Generates the name of the current function.
1902 / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX
1903 attributes are examined to determine what is appropriate.
1905 , Generates single precision suffix for floating point
1906 instructions (s for IEEE, f for VAX)
1908 - Generates double precision suffix for floating point
1909 instructions (t for IEEE, g for VAX)
1912 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1913 ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \
1914 || (CODE) == '#' || (CODE) == '*' || (CODE) == '&')
1916 /* Print a memory address as an operand to reference that memory location. */
1918 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1919 print_operand_address((FILE), (ADDR))
1921 /* Define the codes that are matched by predicates in alpha.c. */
1923 #define PREDICATE_CODES \
1924 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, \
1926 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
1927 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
1928 {"reg_or_const_int_operand", {SUBREG, REG, CONST_INT}}, \
1929 {"cint8_operand", {CONST_INT}}, \
1930 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
1931 {"add_operand", {SUBREG, REG, CONST_INT}}, \
1932 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
1933 {"const48_operand", {CONST_INT}}, \
1934 {"and_operand", {SUBREG, REG, CONST_INT}}, \
1935 {"or_operand", {SUBREG, REG, CONST_INT}}, \
1936 {"mode_mask_operand", {CONST_INT}}, \
1937 {"mul8_operand", {CONST_INT}}, \
1938 {"mode_width_operand", {CONST_INT}}, \
1939 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
1940 {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \
1941 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
1942 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
1943 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
1944 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
1945 {"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}}, \
1946 {"current_file_function_operand", {SYMBOL_REF}}, \
1947 {"direct_call_operand", {SYMBOL_REF}}, \
1948 {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
1949 {"small_symbolic_operand", {SYMBOL_REF, CONST}}, \
1950 {"global_symbolic_operand", {SYMBOL_REF, CONST}}, \
1951 {"dtp16_symbolic_operand", {CONST}}, \
1952 {"dtp32_symbolic_operand", {CONST}}, \
1953 {"gotdtp_symbolic_operand", {CONST}}, \
1954 {"tp16_symbolic_operand", {CONST}}, \
1955 {"tp32_symbolic_operand", {CONST}}, \
1956 {"gottp_symbolic_operand", {CONST}}, \
1957 {"call_operand", {REG, SYMBOL_REF}}, \
1958 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
1959 CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}},\
1960 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
1961 CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \
1962 {"some_ni_operand", {SUBREG, REG, MEM}}, \
1963 {"aligned_memory_operand", {MEM}}, \
1964 {"unaligned_memory_operand", {MEM}}, \
1965 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
1966 {"any_memory_operand", {MEM}}, \
1967 {"hard_fp_register_operand", {SUBREG, REG}}, \
1968 {"hard_int_register_operand", {SUBREG, REG}}, \
1969 {"reg_not_elim_operand", {SUBREG, REG}}, \
1970 {"reg_no_subreg_operand", {REG}}, \
1971 {"addition_operation", {PLUS}}, \
1972 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
1973 {"some_small_symbolic_operand", {SET, PARALLEL, PREFETCH, UNSPEC, \
1976 /* Define the `__builtin_va_list' type for the ABI. */
1977 #define BUILD_VA_LIST_TYPE(VALIST) \
1978 (VALIST) = alpha_build_va_list ()
1980 /* Implement `va_start' for varargs and stdarg. */
1981 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1982 alpha_va_start (valist, nextarg)
1984 /* Implement `va_arg'. */
1985 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1986 alpha_va_arg (valist, type)
1988 /* Tell collect that the object format is ECOFF. */
1989 #define OBJECT_FORMAT_COFF
1990 #define EXTENDED_COFF
1992 /* If we use NM, pass -g to it so it only lists globals. */
1993 #define NM_FLAGS "-pg"
1995 /* Definitions for debugging. */
1997 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1998 #define DBX_DEBUGGING_INFO 1 /* generate embedded stabs */
1999 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
2001 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2002 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2006 /* Correct the offset of automatic variables and arguments. Note that
2007 the Alpha debug format wants all automatic variables and arguments
2008 to be in terms of two different offsets from the virtual frame pointer,
2009 which is the stack pointer before any adjustment in the function.
2010 The offset for the argument pointer is fixed for the native compiler,
2011 it is either zero (for the no arguments case) or large enough to hold
2012 all argument registers.
2013 The offset for the auto pointer is the fourth argument to the .frame
2014 directive (local_offset).
2015 To stay compatible with the native tools we use the same offsets
2016 from the virtual frame pointer and adjust the debugger arg/auto offsets
2017 accordingly. These debugger offsets are set up in output_prolog. */
2019 extern long alpha_arg_offset;
2020 extern long alpha_auto_offset;
2021 #define DEBUGGER_AUTO_OFFSET(X) \
2022 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2023 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2026 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2027 alpha_output_lineno (STREAM, LINE)
2029 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2030 alpha_output_filename (STREAM, NAME)
2032 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2033 number, because the real length runs past this up to the next
2034 continuation point. This is really a dbxout.c bug. */
2035 #define DBX_CONTIN_LENGTH 3000
2037 /* By default, turn on GDB extensions. */
2038 #define DEFAULT_GDB_EXTENSIONS 1
2040 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2041 #define NO_DBX_FUNCTION_END 1
2043 /* If we are smuggling stabs through the ALPHA ECOFF object
2044 format, put a comment in front of the .stab<x> operation so
2045 that the ALPHA assembler does not choke. The mips-tfile program
2046 will correctly put the stab into the object file. */
2048 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
2049 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
2050 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
2052 /* Forward references to tags are allowed. */
2053 #define SDB_ALLOW_FORWARD_REFERENCES
2055 /* Unknown tags are also allowed. */
2056 #define SDB_ALLOW_UNKNOWN_REFERENCES
2058 #define PUT_SDB_DEF(a) \
2060 fprintf (asm_out_file, "\t%s.def\t", \
2061 (TARGET_GAS) ? "" : "#"); \
2062 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2063 fputc (';', asm_out_file); \
2066 #define PUT_SDB_PLAIN_DEF(a) \
2068 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2069 (TARGET_GAS) ? "" : "#", (a)); \
2072 #define PUT_SDB_TYPE(a) \
2074 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2077 /* For block start and end, we create labels, so that
2078 later we can figure out where the correct offset is.
2079 The normal .ent/.end serve well enough for functions,
2080 so those are just commented out. */
2082 extern int sdb_label_count; /* block start/end next label # */
2084 #define PUT_SDB_BLOCK_START(LINE) \
2086 fprintf (asm_out_file, \
2087 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2089 (TARGET_GAS) ? "" : "#", \
2092 sdb_label_count++; \
2095 #define PUT_SDB_BLOCK_END(LINE) \
2097 fprintf (asm_out_file, \
2098 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2100 (TARGET_GAS) ? "" : "#", \
2103 sdb_label_count++; \
2106 #define PUT_SDB_FUNCTION_START(LINE)
2108 #define PUT_SDB_FUNCTION_END(LINE)
2110 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2112 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2113 mips-tdump.c to print them out.
2115 These must match the corresponding definitions in gdb/mipsread.c.
2116 Unfortunately, gcc and gdb do not currently share any directories. */
2118 #define CODE_MASK 0x8F300
2119 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2120 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2121 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2123 /* Override some mips-tfile definitions. */
2125 #define SHASH_SIZE 511
2126 #define THASH_SIZE 55
2128 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2130 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2132 /* The system headers under Alpha systems are generally C++-aware. */
2133 #define NO_IMPLICIT_EXTERN_C
2135 /* Generate calls to memcpy, etc., not bcopy, etc. */
2136 #define TARGET_MEM_FUNCTIONS 1
2138 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2139 Used for C++ multiple inheritance. */
2140 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2141 alpha_output_mi_thunk_osf (FILE, THUNK_FNDECL, DELTA, FUNCTION)
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