gcc/config/aarch64/large.md

   1 ;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
   2 ;;
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; In the absence of any ARMv8-A implementations, two examples derived
  22 ;; from ARM's most recent ARMv7-A cores (Cortex-A7 and Cortex-A15) are
  23 ;; included by way of example.  This is a temporary measure.
  24
  25 ;; Example pipeline description for an example 'large' core
  26 ;; implementing AArch64
  27
  28 ;;-------------------------------------------------------
  29 ;; General Description
  30 ;;-------------------------------------------------------
  31
  32 (define_automaton "large_cpu")
  33
  34 ;; The core is modelled as a triple issue pipeline that has
  35 ;; the following dispatch units.
  36 ;; 1. Two pipelines for simple integer operations: int1, int2
  37 ;; 2. Two pipelines for SIMD and FP data-processing operations: fpsimd1, fpsimd2
  38 ;; 3. One pipeline for branch operations: br
  39 ;; 4. One pipeline for integer multiply and divide operations: multdiv
  40 ;; 5. Two pipelines for load and store operations: ls1, ls2
  41 ;;
  42 ;; We can issue into three pipelines per-cycle.
  43 ;;
  44 ;; We assume that where we have unit pairs xxx1 is always filled before xxx2.
  45
  46 ;;-------------------------------------------------------
  47 ;; CPU Units and Reservations
  48 ;;-------------------------------------------------------
  49
  50 ;; The three issue units
  51 (define_cpu_unit "large_cpu_unit_i1, large_cpu_unit_i2, large_cpu_unit_i3" "large_cpu")
  52
  53 (define_reservation "large_cpu_resv_i1"
  54                     "(large_cpu_unit_i1 | large_cpu_unit_i2 | large_cpu_unit_i3)")
  55
  56 (define_reservation "large_cpu_resv_i2"
  57                     "((large_cpu_unit_i1 + large_cpu_unit_i2) | (large_cpu_unit_i2 + large_cpu_unit_i3))")
  58
  59 (define_reservation "large_cpu_resv_i3"
  60                     "(large_cpu_unit_i1 + large_cpu_unit_i2 + large_cpu_unit_i3)")
  61
  62 (final_presence_set "large_cpu_unit_i2" "large_cpu_unit_i1")
  63 (final_presence_set "large_cpu_unit_i3" "large_cpu_unit_i2")
  64
  65 ;; The main dispatch units
  66 (define_cpu_unit "large_cpu_unit_int1, large_cpu_unit_int2" "large_cpu")
  67 (define_cpu_unit "large_cpu_unit_fpsimd1, large_cpu_unit_fpsimd2" "large_cpu")
  68 (define_cpu_unit "large_cpu_unit_ls1, large_cpu_unit_ls2" "large_cpu")
  69 (define_cpu_unit "large_cpu_unit_br" "large_cpu")
  70 (define_cpu_unit "large_cpu_unit_multdiv" "large_cpu")
  71
  72 (define_reservation "large_cpu_resv_ls" "(large_cpu_unit_ls1 | large_cpu_unit_ls2)")
  73
  74 ;; The extended load-store pipeline
  75 (define_cpu_unit "large_cpu_unit_load, large_cpu_unit_store" "large_cpu")
  76
  77 ;; The extended ALU pipeline
  78 (define_cpu_unit "large_cpu_unit_int1_alu, large_cpu_unit_int2_alu" "large_cpu")
  79 (define_cpu_unit "large_cpu_unit_int1_shf, large_cpu_unit_int2_shf" "large_cpu")
  80 (define_cpu_unit "large_cpu_unit_int1_sat, large_cpu_unit_int2_sat" "large_cpu")
  81
  82
  83 ;;-------------------------------------------------------
  84 ;; Simple ALU Instructions
  85 ;;-------------------------------------------------------
  86
  87 ;; Simple ALU operations without shift
  88 (define_insn_reservation "large_cpu_alu" 2
  89   (and (eq_attr "tune" "large") (eq_attr "v8type" "adc,alu,alu_ext"))
  90   "large_cpu_resv_i1, \
  91    (large_cpu_unit_int1, large_cpu_unit_int1_alu) |\
  92      (large_cpu_unit_int2, large_cpu_unit_int2_alu)")
  93
  94 (define_insn_reservation "large_cpu_logic" 2
  95   (and (eq_attr "tune" "large") (eq_attr "v8type" "logic,logic_imm"))
  96   "large_cpu_resv_i1, \
  97    (large_cpu_unit_int1, large_cpu_unit_int1_alu) |\
  98      (large_cpu_unit_int2, large_cpu_unit_int2_alu)")
  99
 100 (define_insn_reservation "large_cpu_shift" 2
 101   (and (eq_attr "tune" "large") (eq_attr "v8type" "shift,shift_imm"))
 102   "large_cpu_resv_i1, \
 103    (large_cpu_unit_int1, large_cpu_unit_int1_shf) |\
 104      (large_cpu_unit_int2, large_cpu_unit_int2_shf)")
 105
 106 ;; Simple ALU operations with immediate shift
 107 (define_insn_reservation "large_cpu_alu_shift" 3
 108   (and (eq_attr "tune" "large") (eq_attr "v8type" "alu_shift"))
 109   "large_cpu_resv_i1, \
 110    (large_cpu_unit_int1,
 111      large_cpu_unit_int1 + large_cpu_unit_int1_shf, large_cpu_unit_int1_alu) | \
 112    (large_cpu_unit_int2,
 113      large_cpu_unit_int2 + large_cpu_unit_int2_shf, large_cpu_unit_int2_alu)")
 114
 115 (define_insn_reservation "large_cpu_logic_shift" 3
 116   (and (eq_attr "tune" "large") (eq_attr "v8type" "logic_shift"))
 117   "large_cpu_resv_i1, \
 118    (large_cpu_unit_int1, large_cpu_unit_int1_alu) |\
 119      (large_cpu_unit_int2, large_cpu_unit_int2_alu)")
 120
 121
 122 ;;-------------------------------------------------------
 123 ;; Multiplication/Division
 124 ;;-------------------------------------------------------
 125
 126 ;; Simple multiplication
 127 (define_insn_reservation "large_cpu_mult_single" 3
 128   (and (eq_attr "tune" "large")
 129        (and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "SI")))
 130   "large_cpu_resv_i1, large_cpu_unit_multdiv")
 131
 132 (define_insn_reservation "large_cpu_mult_double" 4
 133   (and (eq_attr "tune" "large")
 134        (and (eq_attr "v8type" "mult,madd") (eq_attr "mode" "DI")))
 135   "large_cpu_resv_i1, large_cpu_unit_multdiv")
 136
 137 ;; 64-bit multiplication
 138 (define_insn_reservation "large_cpu_mull" 4
 139   (and (eq_attr "tune" "large") (eq_attr "v8type" "mull,mulh,maddl"))
 140   "large_cpu_resv_i1, large_cpu_unit_multdiv * 2")
 141
 142 ;; Division
 143 (define_insn_reservation "large_cpu_udiv_single" 9
 144   (and (eq_attr "tune" "large")
 145        (and (eq_attr "v8type" "udiv") (eq_attr "mode" "SI")))
 146   "large_cpu_resv_i1, large_cpu_unit_multdiv")
 147
 148 (define_insn_reservation "large_cpu_udiv_double" 18
 149   (and (eq_attr "tune" "large")
 150        (and (eq_attr "v8type" "udiv") (eq_attr "mode" "DI")))
 151   "large_cpu_resv_i1, large_cpu_unit_multdiv")
 152
 153 (define_insn_reservation "large_cpu_sdiv_single" 10
 154   (and (eq_attr "tune" "large")
 155        (and (eq_attr "v8type" "sdiv") (eq_attr "mode" "SI")))
 156   "large_cpu_resv_i1, large_cpu_unit_multdiv")
 157
 158 (define_insn_reservation "large_cpu_sdiv_double" 20
 159   (and (eq_attr "tune" "large")
 160        (and (eq_attr "v8type" "sdiv") (eq_attr "mode" "DI")))
 161   "large_cpu_resv_i1, large_cpu_unit_multdiv")
 162
 163
 164 ;;-------------------------------------------------------
 165 ;; Branches
 166 ;;-------------------------------------------------------
 167
 168 ;; Branches take one issue slot.
 169 ;; No latency as there is no result
 170 (define_insn_reservation "large_cpu_branch" 0
 171   (and (eq_attr "tune" "large") (eq_attr "v8type" "branch"))
 172   "large_cpu_resv_i1, large_cpu_unit_br")
 173
 174
 175 ;; Calls take up all issue slots, and form a block in the
 176 ;; pipeline.  The result however is available the next cycle.
 177 ;; Addition of new units requires this to be updated.
 178 (define_insn_reservation "large_cpu_call" 1
 179   (and (eq_attr "tune" "large") (eq_attr "v8type" "call"))
 180   "large_cpu_resv_i3 | large_cpu_resv_i2, \
 181    large_cpu_unit_int1 + large_cpu_unit_int2 + large_cpu_unit_br + \
 182      large_cpu_unit_multdiv + large_cpu_unit_fpsimd1 + large_cpu_unit_fpsimd2 + \
 183      large_cpu_unit_ls1 + large_cpu_unit_ls2,\
 184    large_cpu_unit_int1_alu + large_cpu_unit_int1_shf + large_cpu_unit_int1_sat + \
 185      large_cpu_unit_int2_alu + large_cpu_unit_int2_shf + \
 186      large_cpu_unit_int2_sat + large_cpu_unit_load + large_cpu_unit_store")
 187
 188
 189 ;;-------------------------------------------------------
 190 ;; Load/Store Instructions
 191 ;;-------------------------------------------------------
 192
 193 ;; Loads of up to two words.
 194 (define_insn_reservation "large_cpu_load1" 4
 195   (and (eq_attr "tune" "large") (eq_attr "v8type" "load_acq,load1,load2"))
 196   "large_cpu_resv_i1, large_cpu_resv_ls, large_cpu_unit_load, nothing")
 197
 198 ;; Stores of up to two words.
 199 (define_insn_reservation "large_cpu_store1" 0
 200   (and (eq_attr "tune" "large") (eq_attr "v8type" "store_rel,store1,store2"))
 201   "large_cpu_resv_i1, large_cpu_resv_ls, large_cpu_unit_store")
 202
 203
 204 ;;-------------------------------------------------------
 205 ;; Floating-point arithmetic.
 206 ;;-------------------------------------------------------
 207
 208 (define_insn_reservation "large_cpu_fpalu" 4
 209   (and (eq_attr "tune" "large")
 210        (eq_attr "v8type" "ffarith,fadd,fccmp,fcvt,fcmp"))
 211   "large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
 212
 213 (define_insn_reservation "large_cpu_fconst" 3
 214   (and (eq_attr "tune" "large")
 215        (eq_attr "v8type" "fconst"))
 216   "large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
 217
 218 (define_insn_reservation "large_cpu_fpmuls" 4
 219   (and (eq_attr "tune" "large")
 220        (and (eq_attr "v8type" "fmul,fmadd") (eq_attr "mode" "SF")))
 221   "large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
 222
 223 (define_insn_reservation "large_cpu_fpmuld" 7
 224   (and (eq_attr "tune" "large")
 225        (and (eq_attr "v8type" "fmul,fmadd") (eq_attr "mode" "DF")))
 226   "large_cpu_resv_i1 + large_cpu_unit_fpsimd1, large_cpu_unit_fpsimd1 * 2,\
 227    large_cpu_resv_i1 + large_cpu_unit_fpsimd1")
 228
 229
 230 ;;-------------------------------------------------------
 231 ;; Floating-point Division
 232 ;;-------------------------------------------------------
 233
 234 ;; Single-precision divide takes 14 cycles to complete, and this
 235 ;; includes the time taken for the special instruction used to collect the
 236 ;; result to travel down the multiply pipeline.
 237
 238 (define_insn_reservation "large_cpu_fdivs" 14
 239   (and (eq_attr "tune" "large")
 240        (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "SF")))
 241   "large_cpu_resv_i1, large_cpu_unit_fpsimd1 * 13")
 242
 243 (define_insn_reservation "large_cpu_fdivd" 29
 244   (and (eq_attr "tune" "large")
 245        (and (eq_attr "v8type" "fdiv,fsqrt") (eq_attr "mode" "DF")))
 246   "large_cpu_resv_i1, large_cpu_unit_fpsimd1 * 28")
 247
 248
 249
 250 ;;-------------------------------------------------------
 251 ;; Floating-point Transfers
 252 ;;-------------------------------------------------------
 253
 254 (define_insn_reservation "large_cpu_i2f" 4
 255   (and (eq_attr "tune" "large")
 256        (eq_attr "v8type" "fmovi2f"))
 257   "large_cpu_resv_i1")
 258
 259 (define_insn_reservation "large_cpu_f2i" 2
 260   (and (eq_attr "tune" "large")
 261        (eq_attr "v8type" "fmovf2i"))
 262   "large_cpu_resv_i1")
 263
 264
 265 ;;-------------------------------------------------------
 266 ;; Floating-point Load/Store
 267 ;;-------------------------------------------------------
 268
 269 (define_insn_reservation "large_cpu_floads" 4
 270   (and (eq_attr "tune" "large")
 271        (and (eq_attr "v8type" "fpsimd_load,fpsimd_load2") (eq_attr "mode" "SF")))
 272   "large_cpu_resv_i1")
 273
 274 (define_insn_reservation "large_cpu_floadd" 5
 275   (and (eq_attr "tune" "large")
 276        (and (eq_attr "v8type" "fpsimd_load,fpsimd_load2") (eq_attr "mode" "DF")))
 277   "large_cpu_resv_i1 + large_cpu_unit_br, large_cpu_resv_i1")
 278
 279 (define_insn_reservation "large_cpu_fstores" 0
 280   (and (eq_attr "tune" "large")
 281        (and (eq_attr "v8type" "fpsimd_store,fpsimd_store2") (eq_attr "mode" "SF")))
 282   "large_cpu_resv_i1")
 283
 284 (define_insn_reservation "large_cpu_fstored" 0
 285   (and (eq_attr "tune" "large")
 286        (and (eq_attr "v8type" "fpsimd_store,fpsimd_store2") (eq_attr "mode" "DF")))
 287   "large_cpu_resv_i1 + large_cpu_unit_br, large_cpu_resv_i1")
 288
 289
 290 ;;-------------------------------------------------------
 291 ;; Bypasses
 292 ;;-------------------------------------------------------
 293
 294 (define_bypass 1 "large_cpu_alu, large_cpu_logic, large_cpu_shift"
 295   "large_cpu_alu, large_cpu_alu_shift, large_cpu_logic, large_cpu_logic_shift, large_cpu_shift")
 296
 297 (define_bypass 2 "large_cpu_alu_shift, large_cpu_logic_shift"
 298   "large_cpu_alu, large_cpu_alu_shift, large_cpu_logic, large_cpu_logic_shift, large_cpu_shift")
 299
 300 (define_bypass 1 "large_cpu_alu, large_cpu_logic, large_cpu_shift" "large_cpu_load1")
 301
 302 (define_bypass 2 "large_cpu_alu_shift, large_cpu_logic_shift" "large_cpu_load1")
 303
 304 (define_bypass 2 "large_cpu_floads"
 305                  "large_cpu_fpalu, large_cpu_fpmuld,\
 306                   large_cpu_fdivs, large_cpu_fdivd,\
 307                   large_cpu_f2i")
 308
 309 (define_bypass 3 "large_cpu_floadd"
 310                  "large_cpu_fpalu, large_cpu_fpmuld,\
 311                   large_cpu_fdivs, large_cpu_fdivd,\
 312                   large_cpu_f2i")