1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
77 /* Must precede rtl.h for FFS. */
84 #include "hard-reg-set.h"
86 #include "basic-block.h"
87 #include "insn-config.h"
88 #include "insn-flags.h"
89 #include "insn-codes.h"
90 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* If byte loads either zero- or sign- extend, define BYTE_LOADS_EXTEND
99 for cases when we don't care which is true. Define LOAD_EXTEND to
100 be ZERO_EXTEND or SIGN_EXTEND, depending on which was defined. */
102 #ifdef BYTE_LOADS_ZERO_EXTEND
103 #define BYTE_LOADS_EXTEND
104 #define LOAD_EXTEND ZERO_EXTEND
107 #ifdef BYTE_LOADS_SIGN_EXTEND
108 #define BYTE_LOADS_EXTEND
109 #define LOAD_EXTEND SIGN_EXTEND
112 /* Number of attempts to combine instructions in this function. */
114 static int combine_attempts;
116 /* Number of attempts that got as far as substitution in this function. */
118 static int combine_merges;
120 /* Number of instructions combined with added SETs in this function. */
122 static int combine_extras;
124 /* Number of instructions combined in this function. */
126 static int combine_successes;
128 /* Totals over entire compilation. */
130 static int total_attempts, total_merges, total_extras, total_successes;
132 /* Vector mapping INSN_UIDs to cuids.
133 The cuids are like uids but increase monotonically always.
134 Combine always uses cuids so that it can compare them.
135 But actually renumbering the uids, which we used to do,
136 proves to be a bad idea because it makes it hard to compare
137 the dumps produced by earlier passes with those from later passes. */
139 static int *uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
145 /* Maximum register number, which is the size of the tables below. */
147 static int combine_max_regno;
149 /* Record last point of death of (hard or pseudo) register n. */
151 static rtx *reg_last_death;
153 /* Record last point of modification of (hard or pseudo) register n. */
155 static rtx *reg_last_set;
157 /* Record the cuid of the last insn that invalidated memory
158 (anything that writes memory, and subroutine calls, but not pushes). */
160 static int mem_last_set;
162 /* Record the cuid of the last CALL_INSN
163 so we can tell whether a potential combination crosses any calls. */
165 static int last_call_cuid;
167 /* When `subst' is called, this is the insn that is being modified
168 (by combining in a previous insn). The PATTERN of this insn
169 is still the old pattern partially modified and it should not be
170 looked at, but this may be used to examine the successors of the insn
171 to judge whether a simplification is valid. */
173 static rtx subst_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This is the value of undobuf.num_undo when we started processing this
185 substitution. This will prevent gen_rtx_combine from re-used a piece
186 from the previous expression. Doing so can produce circular rtl
189 static int previous_num_undos;
191 /* Basic block number of the block in which we are performing combines. */
192 static int this_basic_block;
194 /* The next group of arrays allows the recording of the last value assigned
195 to (hard or pseudo) register n. We use this information to see if a
196 operation being processed is redundant given a prior operation performed
197 on the register. For example, an `and' with a constant is redundant if
198 all the zero bits are already known to be turned off.
200 We use an approach similar to that used by cse, but change it in the
203 (1) We do not want to reinitialize at each label.
204 (2) It is useful, but not critical, to know the actual value assigned
205 to a register. Often just its form is helpful.
207 Therefore, we maintain the following arrays:
209 reg_last_set_value the last value assigned
210 reg_last_set_label records the value of label_tick when the
211 register was assigned
212 reg_last_set_table_tick records the value of label_tick when a
213 value using the register is assigned
214 reg_last_set_invalid set to non-zero when it is not valid
215 to use the value of this register in some
218 To understand the usage of these tables, it is important to understand
219 the distinction between the value in reg_last_set_value being valid
220 and the register being validly contained in some other expression in the
223 Entry I in reg_last_set_value is valid if it is non-zero, and either
224 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
226 Register I may validly appear in any expression returned for the value
227 of another register if reg_n_sets[i] is 1. It may also appear in the
228 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
229 reg_last_set_invalid[j] is zero.
231 If an expression is found in the table containing a register which may
232 not validly appear in an expression, the register is replaced by
233 something that won't match, (clobber (const_int 0)).
235 reg_last_set_invalid[i] is set non-zero when register I is being assigned
236 to and reg_last_set_table_tick[i] == label_tick. */
238 /* Record last value assigned to (hard or pseudo) register n. */
240 static rtx *reg_last_set_value;
242 /* Record the value of label_tick when the value for register n is placed in
243 reg_last_set_value[n]. */
245 static int *reg_last_set_label;
247 /* Record the value of label_tick when an expression involving register n
248 is placed in reg_last_set_value. */
250 static int *reg_last_set_table_tick;
252 /* Set non-zero if references to register n in expressions should not be
255 static char *reg_last_set_invalid;
257 /* Incremented for each label. */
259 static int label_tick;
261 /* Some registers that are set more than once and used in more than one
262 basic block are nevertheless always set in similar ways. For example,
263 a QImode register may be loaded from memory in two places on a machine
264 where byte loads zero extend.
266 We record in the following array what we know about the nonzero
267 bits of a register, specifically which bits are known to be zero.
269 If an entry is zero, it means that we don't know anything special. */
271 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
273 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
274 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
276 static enum machine_mode nonzero_bits_mode;
278 /* Nonzero if we know that a register has some leading bits that are always
279 equal to the sign bit. */
281 static char *reg_sign_bit_copies;
283 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
284 It is zero while computing them and after combine has completed. This
285 former test prevents propagating values based on previously set values,
286 which can be incorrect if a variable is modified in a loop. */
288 static int nonzero_sign_valid;
290 /* These arrays are maintained in parallel with reg_last_set_value
291 and are used to store the mode in which the register was last set,
292 the bits that were known to be zero when it was last set, and the
293 number of sign bits copies it was known to have when it was last set. */
295 static enum machine_mode *reg_last_set_mode;
296 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
297 static char *reg_last_set_sign_bit_copies;
299 /* Record one modification to rtl structure
300 to be undone by storing old_contents into *where.
301 is_int is 1 if the contents are an int. */
306 union {rtx r; int i;} old_contents;
307 union {rtx *r; int *i;} where;
310 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
311 num_undo says how many are currently recorded.
313 storage is nonzero if we must undo the allocation of new storage.
314 The value of storage is what to pass to obfree.
316 other_insn is nonzero if we have modified some other insn in the process
317 of working on subst_insn. It must be verified too. */
325 struct undo undo[MAX_UNDO];
329 static struct undobuf undobuf;
331 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
332 insn. The substitution can be undone by undo_all. If INTO is already
333 set to NEWVAL, do not record this change. Because computing NEWVAL might
334 also call SUBST, we have to compute it before we put anything into
337 #define SUBST(INTO, NEWVAL) \
338 do { rtx _new = (NEWVAL); \
339 if (undobuf.num_undo < MAX_UNDO) \
341 undobuf.undo[undobuf.num_undo].is_int = 0; \
342 undobuf.undo[undobuf.num_undo].where.r = &INTO; \
343 undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \
345 if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \
346 undobuf.num_undo++; \
350 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
352 Note that substitution for the value of a CONST_INT is not safe. */
354 #define SUBST_INT(INTO, NEWVAL) \
355 do { if (undobuf.num_undo < MAX_UNDO) \
357 undobuf.undo[undobuf.num_undo].is_int = 1; \
358 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
359 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
361 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
362 undobuf.num_undo++; \
366 /* Number of times the pseudo being substituted for
367 was found and replaced. */
369 static int n_occurrences;
371 static void setup_incoming_promotions PROTO(());
372 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
373 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
374 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
375 static rtx try_combine PROTO((rtx, rtx, rtx));
376 static void undo_all PROTO((void));
377 static rtx *find_split_point PROTO((rtx *, rtx));
378 static rtx subst PROTO((rtx, rtx, rtx, int, int));
379 static rtx expand_compound_operation PROTO((rtx));
380 static rtx expand_field_assignment PROTO((rtx));
381 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
383 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
384 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
385 static rtx force_to_mode PROTO((rtx, enum machine_mode, int, rtx));
386 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
387 static rtx make_field_assignment PROTO((rtx));
388 static rtx apply_distributive_law PROTO((rtx));
389 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
390 unsigned HOST_WIDE_INT));
391 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
392 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
393 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
394 enum rtx_code, HOST_WIDE_INT,
395 enum machine_mode, int *));
396 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
398 static int recog_for_combine PROTO((rtx *, rtx, rtx *));
399 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
400 static rtx gen_rtx_combine (); /* This is varargs. */
401 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
403 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode, rtx));
404 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
405 static int reversible_comparison_p PROTO((rtx));
406 static void update_table_tick PROTO((rtx));
407 static void record_value_for_reg PROTO((rtx, rtx, rtx));
408 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
409 static void record_dead_and_set_regs PROTO((rtx));
410 static int get_last_value_validate PROTO((rtx *, int, int));
411 static rtx get_last_value PROTO((rtx));
412 static int use_crosses_set_p PROTO((rtx, int));
413 static void reg_dead_at_p_1 PROTO((rtx, rtx));
414 static int reg_dead_at_p PROTO((rtx, rtx));
415 static void move_deaths PROTO((rtx, int, rtx, rtx *));
416 static int reg_bitfield_target_p PROTO((rtx, rtx));
417 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
418 static void distribute_links PROTO((rtx));
420 /* Main entry point for combiner. F is the first insn of the function.
421 NREGS is the first unused pseudo-reg number. */
424 combine_instructions (f, nregs)
428 register rtx insn, next, prev;
430 register rtx links, nextlinks;
432 combine_attempts = 0;
435 combine_successes = 0;
436 undobuf.num_undo = previous_num_undos = 0;
438 combine_max_regno = nregs;
440 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
441 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
442 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
443 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
444 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
445 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
447 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
448 reg_last_set_nonzero_bits
449 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
450 reg_last_set_sign_bit_copies
451 = (char *) alloca (nregs * sizeof (char));
454 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
455 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
457 bzero (reg_last_death, nregs * sizeof (rtx));
458 bzero (reg_last_set, nregs * sizeof (rtx));
459 bzero (reg_last_set_value, nregs * sizeof (rtx));
460 bzero (reg_last_set_table_tick, nregs * sizeof (int));
461 bzero (reg_last_set_label, nregs * sizeof (int));
462 bzero (reg_last_set_invalid, nregs * sizeof (char));
463 bzero (reg_last_set_mode, nregs * sizeof (enum machine_mode));
464 bzero (reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
465 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
466 bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
467 bzero (reg_sign_bit_copies, nregs * sizeof (char));
469 init_recog_no_volatile ();
471 /* Compute maximum uid value so uid_cuid can be allocated. */
473 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
474 if (INSN_UID (insn) > i)
477 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
479 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
481 /* Don't use reg_nonzero_bits when computing it. This can cause problems
482 when, for example, we have j <<= 1 in a loop. */
484 nonzero_sign_valid = 0;
486 /* Compute the mapping from uids to cuids.
487 Cuids are numbers assigned to insns, like uids,
488 except that cuids increase monotonically through the code.
490 Scan all SETs and see if we can deduce anything about what
491 bits are known to be zero for some registers and how many copies
492 of the sign bit are known to exist for those registers.
494 Also set any known values so that we can use it while searching
495 for what bits are known to be set. */
499 setup_incoming_promotions ();
501 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
503 INSN_CUID (insn) = ++i;
507 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
509 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
510 record_dead_and_set_regs (insn);
513 if (GET_CODE (insn) == CODE_LABEL)
517 nonzero_sign_valid = 1;
519 /* Now scan all the insns in forward order. */
521 this_basic_block = -1;
525 bzero (reg_last_death, nregs * sizeof (rtx));
526 bzero (reg_last_set, nregs * sizeof (rtx));
527 bzero (reg_last_set_value, nregs * sizeof (rtx));
528 bzero (reg_last_set_table_tick, nregs * sizeof (int));
529 bzero (reg_last_set_label, nregs * sizeof (int));
530 bzero (reg_last_set_invalid, nregs * sizeof (char));
532 setup_incoming_promotions ();
534 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
538 /* If INSN starts a new basic block, update our basic block number. */
539 if (this_basic_block < n_basic_blocks + 1
540 && basic_block_head[this_basic_block + 1] == insn)
543 if (GET_CODE (insn) == CODE_LABEL)
546 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
548 /* Try this insn with each insn it links back to. */
550 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
551 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
554 /* Try each sequence of three linked insns ending with this one. */
556 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
557 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
558 nextlinks = XEXP (nextlinks, 1))
559 if ((next = try_combine (insn, XEXP (links, 0),
560 XEXP (nextlinks, 0))) != 0)
564 /* Try to combine a jump insn that uses CC0
565 with a preceding insn that sets CC0, and maybe with its
566 logical predecessor as well.
567 This is how we make decrement-and-branch insns.
568 We need this special code because data flow connections
569 via CC0 do not get entered in LOG_LINKS. */
571 if (GET_CODE (insn) == JUMP_INSN
572 && (prev = prev_nonnote_insn (insn)) != 0
573 && GET_CODE (prev) == INSN
574 && sets_cc0_p (PATTERN (prev)))
576 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
579 for (nextlinks = LOG_LINKS (prev); nextlinks;
580 nextlinks = XEXP (nextlinks, 1))
581 if ((next = try_combine (insn, prev,
582 XEXP (nextlinks, 0))) != 0)
586 /* Do the same for an insn that explicitly references CC0. */
587 if (GET_CODE (insn) == INSN
588 && (prev = prev_nonnote_insn (insn)) != 0
589 && GET_CODE (prev) == INSN
590 && sets_cc0_p (PATTERN (prev))
591 && GET_CODE (PATTERN (insn)) == SET
592 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
594 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
597 for (nextlinks = LOG_LINKS (prev); nextlinks;
598 nextlinks = XEXP (nextlinks, 1))
599 if ((next = try_combine (insn, prev,
600 XEXP (nextlinks, 0))) != 0)
604 /* Finally, see if any of the insns that this insn links to
605 explicitly references CC0. If so, try this insn, that insn,
606 and its predecessor if it sets CC0. */
607 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
608 if (GET_CODE (XEXP (links, 0)) == INSN
609 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
610 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
611 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
612 && GET_CODE (prev) == INSN
613 && sets_cc0_p (PATTERN (prev))
614 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
618 /* Try combining an insn with two different insns whose results it
620 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
621 for (nextlinks = XEXP (links, 1); nextlinks;
622 nextlinks = XEXP (nextlinks, 1))
623 if ((next = try_combine (insn, XEXP (links, 0),
624 XEXP (nextlinks, 0))) != 0)
627 if (GET_CODE (insn) != NOTE)
628 record_dead_and_set_regs (insn);
635 total_attempts += combine_attempts;
636 total_merges += combine_merges;
637 total_extras += combine_extras;
638 total_successes += combine_successes;
640 nonzero_sign_valid = 0;
643 /* Set up any promoted values for incoming argument registers. */
646 setup_incoming_promotions ()
648 #ifdef PROMOTE_FUNCTION_ARGS
651 enum machine_mode mode;
653 rtx first = get_insns ();
655 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
656 if (FUNCTION_ARG_REGNO_P (regno)
657 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
658 record_value_for_reg (reg, first,
659 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
661 gen_rtx (CLOBBER, mode, const0_rtx)));
665 /* Called via note_stores. If X is a pseudo that is used in more than
666 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
667 set, record what bits are known zero. If we are clobbering X,
668 ignore this "set" because the clobbered value won't be used.
670 If we are setting only a portion of X and we can't figure out what
671 portion, assume all bits will be used since we don't know what will
674 Similarly, set how many bits of X are known to be copies of the sign bit
675 at all locations in the function. This is the smallest number implied
679 set_nonzero_bits_and_sign_copies (x, set)
685 if (GET_CODE (x) == REG
686 && REGNO (x) >= FIRST_PSEUDO_REGISTER
687 && reg_n_sets[REGNO (x)] > 1
688 && reg_basic_block[REGNO (x)] < 0
689 /* If this register is undefined at the start of the file, we can't
690 say what its contents were. */
691 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
692 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
693 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
695 if (GET_CODE (set) == CLOBBER)
697 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
698 reg_sign_bit_copies[REGNO (x)] = 0;
702 /* If this is a complex assignment, see if we can convert it into a
703 simple assignment. */
704 set = expand_field_assignment (set);
706 /* If this is a simple assignment, or we have a paradoxical SUBREG,
707 set what we know about X. */
709 if (SET_DEST (set) == x
710 || (GET_CODE (SET_DEST (set)) == SUBREG
711 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
712 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
713 && SUBREG_REG (SET_DEST (set)) == x))
715 rtx src = SET_SRC (set);
717 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
718 /* If X is narrower than a word and SRC is a non-negative
719 constant that would appear negative in the mode of X,
720 sign-extend it for use in reg_nonzero_bits because some
721 machines (maybe most) will actually do the sign-extension
722 and this is the conservative approach.
724 ??? For 2.5, try to tighten up the MD files in this regard
725 instead of this kludge. */
727 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
728 && GET_CODE (src) == CONST_INT
730 && 0 != (INTVAL (src)
732 << GET_MODE_BITSIZE (GET_MODE (x)))))
733 src = GEN_INT (INTVAL (src)
734 | ((HOST_WIDE_INT) (-1)
735 << GET_MODE_BITSIZE (GET_MODE (x))));
738 reg_nonzero_bits[REGNO (x)]
739 |= nonzero_bits (src, nonzero_bits_mode);
740 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
741 if (reg_sign_bit_copies[REGNO (x)] == 0
742 || reg_sign_bit_copies[REGNO (x)] > num)
743 reg_sign_bit_copies[REGNO (x)] = num;
747 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
748 reg_sign_bit_copies[REGNO (x)] = 0;
753 /* See if INSN can be combined into I3. PRED and SUCC are optionally
754 insns that were previously combined into I3 or that will be combined
755 into the merger of INSN and I3.
757 Return 0 if the combination is not allowed for any reason.
759 If the combination is allowed, *PDEST will be set to the single
760 destination of INSN and *PSRC to the single source, and this function
764 can_combine_p (insn, i3, pred, succ, pdest, psrc)
771 rtx set = 0, src, dest;
773 int all_adjacent = (succ ? (next_active_insn (insn) == succ
774 && next_active_insn (succ) == i3)
775 : next_active_insn (insn) == i3);
777 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
778 or a PARALLEL consisting of such a SET and CLOBBERs.
780 If INSN has CLOBBER parallel parts, ignore them for our processing.
781 By definition, these happen during the execution of the insn. When it
782 is merged with another insn, all bets are off. If they are, in fact,
783 needed and aren't also supplied in I3, they may be added by
784 recog_for_combine. Otherwise, it won't match.
786 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
789 Get the source and destination of INSN. If more than one, can't
792 if (GET_CODE (PATTERN (insn)) == SET)
793 set = PATTERN (insn);
794 else if (GET_CODE (PATTERN (insn)) == PARALLEL
795 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
797 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
799 rtx elt = XVECEXP (PATTERN (insn), 0, i);
801 switch (GET_CODE (elt))
803 /* We can ignore CLOBBERs. */
808 /* Ignore SETs whose result isn't used but not those that
809 have side-effects. */
810 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
811 && ! side_effects_p (elt))
814 /* If we have already found a SET, this is a second one and
815 so we cannot combine with this insn. */
823 /* Anything else means we can't combine. */
829 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
830 so don't do anything with it. */
831 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
840 set = expand_field_assignment (set);
841 src = SET_SRC (set), dest = SET_DEST (set);
843 /* Don't eliminate a store in the stack pointer. */
844 if (dest == stack_pointer_rtx
845 /* Don't install a subreg involving two modes not tieable.
846 It can worsen register allocation, and can even make invalid reload
847 insns, since the reg inside may need to be copied from in the
848 outside mode, and that may be invalid if it is an fp reg copied in
849 integer mode. As a special exception, we can allow this if
850 I3 is simply copying DEST, a REG, to CC0. */
851 || (GET_CODE (src) == SUBREG
852 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
854 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
855 && SET_DEST (PATTERN (i3)) == cc0_rtx
856 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
859 /* If we couldn't eliminate a field assignment, we can't combine. */
860 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
861 /* Don't combine with an insn that sets a register to itself if it has
862 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
863 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
864 /* Can't merge a function call. */
865 || GET_CODE (src) == CALL
866 /* Don't substitute into an incremented register. */
867 || FIND_REG_INC_NOTE (i3, dest)
868 || (succ && FIND_REG_INC_NOTE (succ, dest))
869 /* Don't combine the end of a libcall into anything. */
870 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
871 /* Make sure that DEST is not used after SUCC but before I3. */
872 || (succ && ! all_adjacent
873 && reg_used_between_p (dest, succ, i3))
874 /* Make sure that the value that is to be substituted for the register
875 does not use any registers whose values alter in between. However,
876 If the insns are adjacent, a use can't cross a set even though we
877 think it might (this can happen for a sequence of insns each setting
878 the same destination; reg_last_set of that register might point to
879 a NOTE). Also, don't move a volatile asm or UNSPEC_VOLATILE across
882 && (use_crosses_set_p (src, INSN_CUID (insn))
883 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
884 || GET_CODE (src) == UNSPEC_VOLATILE))
885 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
886 better register allocation by not doing the combine. */
887 || find_reg_note (i3, REG_NO_CONFLICT, dest)
888 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
889 /* Don't combine across a CALL_INSN, because that would possibly
890 change whether the life span of some REGs crosses calls or not,
891 and it is a pain to update that information.
892 Exception: if source is a constant, moving it later can't hurt.
893 Accept that special case, because it helps -fforce-addr a lot. */
894 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
897 /* DEST must either be a REG or CC0. */
898 if (GET_CODE (dest) == REG)
900 /* If register alignment is being enforced for multi-word items in all
901 cases except for parameters, it is possible to have a register copy
902 insn referencing a hard register that is not allowed to contain the
903 mode being copied and which would not be valid as an operand of most
904 insns. Eliminate this problem by not combining with such an insn.
906 Also, on some machines we don't want to extend the life of a hard
909 if (GET_CODE (src) == REG
910 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
911 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
912 #ifdef SMALL_REGISTER_CLASSES
913 /* Don't extend the life of a hard register. */
914 || REGNO (src) < FIRST_PSEUDO_REGISTER
916 || (REGNO (src) < FIRST_PSEUDO_REGISTER
917 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
922 else if (GET_CODE (dest) != CC0)
925 /* Don't substitute for a register intended as a clobberable operand.
926 Similarly, don't substitute an expression containing a register that
927 will be clobbered in I3. */
928 if (GET_CODE (PATTERN (i3)) == PARALLEL)
929 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
930 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
931 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
933 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
936 /* If INSN contains anything volatile, or is an `asm' (whether volatile
937 or not), reject, unless nothing volatile comes between it and I3,
938 with the exception of SUCC. */
940 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
941 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
942 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
943 && p != succ && volatile_refs_p (PATTERN (p)))
946 /* If INSN or I2 contains an autoincrement or autodecrement,
947 make sure that register is not used between there and I3,
948 and not already used in I3 either.
949 Also insist that I3 not be a jump; if it were one
950 and the incremented register were spilled, we would lose. */
953 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
954 if (REG_NOTE_KIND (link) == REG_INC
955 && (GET_CODE (i3) == JUMP_INSN
956 || reg_used_between_p (XEXP (link, 0), insn, i3)
957 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
962 /* Don't combine an insn that follows a CC0-setting insn.
963 An insn that uses CC0 must not be separated from the one that sets it.
964 We do, however, allow I2 to follow a CC0-setting insn if that insn
965 is passed as I1; in that case it will be deleted also.
966 We also allow combining in this case if all the insns are adjacent
967 because that would leave the two CC0 insns adjacent as well.
968 It would be more logical to test whether CC0 occurs inside I1 or I2,
969 but that would be much slower, and this ought to be equivalent. */
971 p = prev_nonnote_insn (insn);
972 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
977 /* If we get here, we have passed all the tests and the combination is
986 /* LOC is the location within I3 that contains its pattern or the component
987 of a PARALLEL of the pattern. We validate that it is valid for combining.
989 One problem is if I3 modifies its output, as opposed to replacing it
990 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
991 so would produce an insn that is not equivalent to the original insns.
995 (set (reg:DI 101) (reg:DI 100))
996 (set (subreg:SI (reg:DI 101) 0) <foo>)
998 This is NOT equivalent to:
1000 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1001 (set (reg:DI 101) (reg:DI 100))])
1003 Not only does this modify 100 (in which case it might still be valid
1004 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1006 We can also run into a problem if I2 sets a register that I1
1007 uses and I1 gets directly substituted into I3 (not via I2). In that
1008 case, we would be getting the wrong value of I2DEST into I3, so we
1009 must reject the combination. This case occurs when I2 and I1 both
1010 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1011 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1012 of a SET must prevent combination from occurring.
1014 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1015 if the destination of a SET is a hard register.
1017 Before doing the above check, we first try to expand a field assignment
1018 into a set of logical operations.
1020 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1021 we place a register that is both set and used within I3. If more than one
1022 such register is detected, we fail.
1024 Return 1 if the combination is valid, zero otherwise. */
1027 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1033 rtx *pi3dest_killed;
1037 if (GET_CODE (x) == SET)
1039 rtx set = expand_field_assignment (x);
1040 rtx dest = SET_DEST (set);
1041 rtx src = SET_SRC (set);
1042 rtx inner_dest = dest, inner_src = src;
1046 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1047 || GET_CODE (inner_dest) == SUBREG
1048 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1049 inner_dest = XEXP (inner_dest, 0);
1051 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1054 while (GET_CODE (inner_src) == STRICT_LOW_PART
1055 || GET_CODE (inner_src) == SUBREG
1056 || GET_CODE (inner_src) == ZERO_EXTRACT)
1057 inner_src = XEXP (inner_src, 0);
1059 /* If it is better that two different modes keep two different pseudos,
1060 avoid combining them. This avoids producing the following pattern
1062 (set (subreg:SI (reg/v:QI 21) 0)
1063 (lshiftrt:SI (reg/v:SI 20)
1065 If that were made, reload could not handle the pair of
1066 reg 20/21, since it would try to get any GENERAL_REGS
1067 but some of them don't handle QImode. */
1069 if (rtx_equal_p (inner_src, i2dest)
1070 && GET_CODE (inner_dest) == REG
1071 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1075 /* Check for the case where I3 modifies its output, as
1077 if ((inner_dest != dest
1078 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1079 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1080 /* This is the same test done in can_combine_p except that we
1081 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1083 || (GET_CODE (inner_dest) == REG
1084 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1085 #ifdef SMALL_REGISTER_CLASSES
1086 && GET_CODE (src) != CALL
1088 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1089 GET_MODE (inner_dest))
1093 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1096 /* If DEST is used in I3, it is being killed in this insn,
1097 so record that for later.
1098 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1099 STACK_POINTER_REGNUM, since these are always considered to be
1100 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1101 if (pi3dest_killed && GET_CODE (dest) == REG
1102 && reg_referenced_p (dest, PATTERN (i3))
1103 && REGNO (dest) != FRAME_POINTER_REGNUM
1104 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1105 && (REGNO (dest) != ARG_POINTER_REGNUM
1106 || ! fixed_regs [REGNO (dest)])
1108 && REGNO (dest) != STACK_POINTER_REGNUM)
1110 if (*pi3dest_killed)
1113 *pi3dest_killed = dest;
1117 else if (GET_CODE (x) == PARALLEL)
1121 for (i = 0; i < XVECLEN (x, 0); i++)
1122 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1123 i1_not_in_src, pi3dest_killed))
1130 /* Try to combine the insns I1 and I2 into I3.
1131 Here I1 and I2 appear earlier than I3.
1132 I1 can be zero; then we combine just I2 into I3.
1134 It we are combining three insns and the resulting insn is not recognized,
1135 try splitting it into two insns. If that happens, I2 and I3 are retained
1136 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1139 If we created two insns, return I2; otherwise return I3.
1140 Return 0 if the combination does not work. Then nothing is changed. */
1143 try_combine (i3, i2, i1)
1144 register rtx i3, i2, i1;
1146 /* New patterns for I3 and I3, respectively. */
1147 rtx newpat, newi2pat = 0;
1148 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1149 int added_sets_1, added_sets_2;
1150 /* Total number of SETs to put into I3. */
1152 /* Nonzero is I2's body now appears in I3. */
1154 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1155 int insn_code_number, i2_code_number, other_code_number;
1156 /* Contains I3 if the destination of I3 is used in its source, which means
1157 that the old life of I3 is being killed. If that usage is placed into
1158 I2 and not in I3, a REG_DEAD note must be made. */
1159 rtx i3dest_killed = 0;
1160 /* SET_DEST and SET_SRC of I2 and I1. */
1161 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1162 /* PATTERN (I2), or a copy of it in certain cases. */
1164 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1165 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1166 int i1_feeds_i3 = 0;
1167 /* Notes that must be added to REG_NOTES in I3 and I2. */
1168 rtx new_i3_notes, new_i2_notes;
1175 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1176 This can occur when flow deletes an insn that it has merged into an
1177 auto-increment address. We also can't do anything if I3 has a
1178 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1181 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1182 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1183 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1184 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1189 undobuf.num_undo = previous_num_undos = 0;
1190 undobuf.other_insn = 0;
1192 /* Save the current high-water-mark so we can free storage if we didn't
1193 accept this combination. */
1194 undobuf.storage = (char *) oballoc (0);
1196 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1197 code below, set I1 to be the earlier of the two insns. */
1198 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1199 temp = i1, i1 = i2, i2 = temp;
1201 /* First check for one important special-case that the code below will
1202 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1203 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1204 we may be able to replace that destination with the destination of I3.
1205 This occurs in the common code where we compute both a quotient and
1206 remainder into a structure, in which case we want to do the computation
1207 directly into the structure to avoid register-register copies.
1209 We make very conservative checks below and only try to handle the
1210 most common cases of this. For example, we only handle the case
1211 where I2 and I3 are adjacent to avoid making difficult register
1214 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1215 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1216 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1217 #ifdef SMALL_REGISTER_CLASSES
1218 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1219 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1221 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1222 && GET_CODE (PATTERN (i2)) == PARALLEL
1223 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1224 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1225 below would need to check what is inside (and reg_overlap_mentioned_p
1226 doesn't support those codes anyway). Don't allow those destinations;
1227 the resulting insn isn't likely to be recognized anyway. */
1228 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1229 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1230 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1231 SET_DEST (PATTERN (i3)))
1232 && next_real_insn (i2) == i3)
1234 rtx p2 = PATTERN (i2);
1236 /* Make sure that the destination of I3,
1237 which we are going to substitute into one output of I2,
1238 is not used within another output of I2. We must avoid making this:
1239 (parallel [(set (mem (reg 69)) ...)
1240 (set (reg 69) ...)])
1241 which is not well-defined as to order of actions.
1242 (Besides, reload can't handle output reloads for this.)
1244 The problem can also happen if the dest of I3 is a memory ref,
1245 if another dest in I2 is an indirect memory ref. */
1246 for (i = 0; i < XVECLEN (p2, 0); i++)
1247 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1248 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1249 SET_DEST (XVECEXP (p2, 0, i))))
1252 if (i == XVECLEN (p2, 0))
1253 for (i = 0; i < XVECLEN (p2, 0); i++)
1254 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1259 subst_low_cuid = INSN_CUID (i2);
1262 i2dest = SET_SRC (PATTERN (i3));
1264 /* Replace the dest in I2 with our dest and make the resulting
1265 insn the new pattern for I3. Then skip to where we
1266 validate the pattern. Everything was set up above. */
1267 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1268 SET_DEST (PATTERN (i3)));
1271 goto validate_replacement;
1276 /* If we have no I1 and I2 looks like:
1277 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1279 make up a dummy I1 that is
1282 (set (reg:CC X) (compare:CC Y (const_int 0)))
1284 (We can ignore any trailing CLOBBERs.)
1286 This undoes a previous combination and allows us to match a branch-and-
1289 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1290 && XVECLEN (PATTERN (i2), 0) >= 2
1291 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1292 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1294 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1295 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1296 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1297 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1298 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1299 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1301 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1302 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1307 /* We make I1 with the same INSN_UID as I2. This gives it
1308 the same INSN_CUID for value tracking. Our fake I1 will
1309 never appear in the insn stream so giving it the same INSN_UID
1310 as I2 will not cause a problem. */
1312 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1313 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1315 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1316 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1317 SET_DEST (PATTERN (i1)));
1322 /* Verify that I2 and I1 are valid for combining. */
1323 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1324 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1330 /* Record whether I2DEST is used in I2SRC and similarly for the other
1331 cases. Knowing this will help in register status updating below. */
1332 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1333 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1334 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1336 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1338 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1340 /* Ensure that I3's pattern can be the destination of combines. */
1341 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1342 i1 && i2dest_in_i1src && i1_feeds_i3,
1349 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1350 We used to do this EXCEPT in one case: I3 has a post-inc in an
1351 output operand. However, that exception can give rise to insns like
1353 which is a famous insn on the PDP-11 where the value of r3 used as the
1354 source was model-dependent. Avoid this sort of thing. */
1357 if (!(GET_CODE (PATTERN (i3)) == SET
1358 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1359 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1360 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1361 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1362 /* It's not the exception. */
1365 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1366 if (REG_NOTE_KIND (link) == REG_INC
1367 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1369 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1376 /* See if the SETs in I1 or I2 need to be kept around in the merged
1377 instruction: whenever the value set there is still needed past I3.
1378 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1380 For the SET in I1, we have two cases: If I1 and I2 independently
1381 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1382 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1383 in I1 needs to be kept around unless I1DEST dies or is set in either
1384 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1385 I1DEST. If so, we know I1 feeds into I2. */
1387 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1390 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1391 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1393 /* If the set in I2 needs to be kept around, we must make a copy of
1394 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1395 PATTERN (I2), we are only substituting for the original I1DEST, not into
1396 an already-substituted copy. This also prevents making self-referential
1397 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1400 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1401 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1405 i2pat = copy_rtx (i2pat);
1409 /* Substitute in the latest insn for the regs set by the earlier ones. */
1411 maxreg = max_reg_num ();
1415 /* It is possible that the source of I2 or I1 may be performing an
1416 unneeded operation, such as a ZERO_EXTEND of something that is known
1417 to have the high part zero. Handle that case by letting subst look at
1418 the innermost one of them.
1420 Another way to do this would be to have a function that tries to
1421 simplify a single insn instead of merging two or more insns. We don't
1422 do this because of the potential of infinite loops and because
1423 of the potential extra memory required. However, doing it the way
1424 we are is a bit of a kludge and doesn't catch all cases.
1426 But only do this if -fexpensive-optimizations since it slows things down
1427 and doesn't usually win. */
1429 if (flag_expensive_optimizations)
1431 /* Pass pc_rtx so no substitutions are done, just simplifications.
1432 The cases that we are interested in here do not involve the few
1433 cases were is_replaced is checked. */
1436 subst_low_cuid = INSN_CUID (i1);
1437 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1441 subst_low_cuid = INSN_CUID (i2);
1442 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1445 previous_num_undos = undobuf.num_undo;
1449 /* Many machines that don't use CC0 have insns that can both perform an
1450 arithmetic operation and set the condition code. These operations will
1451 be represented as a PARALLEL with the first element of the vector
1452 being a COMPARE of an arithmetic operation with the constant zero.
1453 The second element of the vector will set some pseudo to the result
1454 of the same arithmetic operation. If we simplify the COMPARE, we won't
1455 match such a pattern and so will generate an extra insn. Here we test
1456 for this case, where both the comparison and the operation result are
1457 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1458 I2SRC. Later we will make the PARALLEL that contains I2. */
1460 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1461 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1462 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1463 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1466 enum machine_mode compare_mode;
1468 newpat = PATTERN (i3);
1469 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1473 #ifdef EXTRA_CC_MODES
1474 /* See if a COMPARE with the operand we substituted in should be done
1475 with the mode that is currently being used. If not, do the same
1476 processing we do in `subst' for a SET; namely, if the destination
1477 is used only once, try to replace it with a register of the proper
1478 mode and also replace the COMPARE. */
1479 if (undobuf.other_insn == 0
1480 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1481 &undobuf.other_insn))
1482 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1484 != GET_MODE (SET_DEST (newpat))))
1486 int regno = REGNO (SET_DEST (newpat));
1487 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1489 if (regno < FIRST_PSEUDO_REGISTER
1490 || (reg_n_sets[regno] == 1 && ! added_sets_2
1491 && ! REG_USERVAR_P (SET_DEST (newpat))))
1493 if (regno >= FIRST_PSEUDO_REGISTER)
1494 SUBST (regno_reg_rtx[regno], new_dest);
1496 SUBST (SET_DEST (newpat), new_dest);
1497 SUBST (XEXP (*cc_use, 0), new_dest);
1498 SUBST (SET_SRC (newpat),
1499 gen_rtx_combine (COMPARE, compare_mode,
1500 i2src, const0_rtx));
1503 undobuf.other_insn = 0;
1510 n_occurrences = 0; /* `subst' counts here */
1512 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1513 need to make a unique copy of I2SRC each time we substitute it
1514 to avoid self-referential rtl. */
1516 subst_low_cuid = INSN_CUID (i2);
1517 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1518 ! i1_feeds_i3 && i1dest_in_i1src);
1519 previous_num_undos = undobuf.num_undo;
1521 /* Record whether i2's body now appears within i3's body. */
1522 i2_is_used = n_occurrences;
1525 /* If we already got a failure, don't try to do more. Otherwise,
1526 try to substitute in I1 if we have it. */
1528 if (i1 && GET_CODE (newpat) != CLOBBER)
1530 /* Before we can do this substitution, we must redo the test done
1531 above (see detailed comments there) that ensures that I1DEST
1532 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1534 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1542 subst_low_cuid = INSN_CUID (i1);
1543 newpat = subst (newpat, i1dest, i1src, 0, 0);
1544 previous_num_undos = undobuf.num_undo;
1547 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1548 to count all the ways that I2SRC and I1SRC can be used. */
1549 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1550 && i2_is_used + added_sets_2 > 1)
1551 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1552 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1554 /* Fail if we tried to make a new register (we used to abort, but there's
1555 really no reason to). */
1556 || max_reg_num () != maxreg
1557 /* Fail if we couldn't do something and have a CLOBBER. */
1558 || GET_CODE (newpat) == CLOBBER)
1564 /* If the actions of the earlier insns must be kept
1565 in addition to substituting them into the latest one,
1566 we must make a new PARALLEL for the latest insn
1567 to hold additional the SETs. */
1569 if (added_sets_1 || added_sets_2)
1573 if (GET_CODE (newpat) == PARALLEL)
1575 rtvec old = XVEC (newpat, 0);
1576 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1577 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1578 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1579 sizeof (old->elem[0]) * old->num_elem);
1584 total_sets = 1 + added_sets_1 + added_sets_2;
1585 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1586 XVECEXP (newpat, 0, 0) = old;
1590 XVECEXP (newpat, 0, --total_sets)
1591 = (GET_CODE (PATTERN (i1)) == PARALLEL
1592 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1596 /* If there is no I1, use I2's body as is. We used to also not do
1597 the subst call below if I2 was substituted into I3,
1598 but that could lose a simplification. */
1600 XVECEXP (newpat, 0, --total_sets) = i2pat;
1602 /* See comment where i2pat is assigned. */
1603 XVECEXP (newpat, 0, --total_sets)
1604 = subst (i2pat, i1dest, i1src, 0, 0);
1608 /* We come here when we are replacing a destination in I2 with the
1609 destination of I3. */
1610 validate_replacement:
1612 /* Is the result of combination a valid instruction? */
1613 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1615 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1616 the second SET's destination is a register that is unused. In that case,
1617 we just need the first SET. This can occur when simplifying a divmod
1618 insn. We *must* test for this case here because the code below that
1619 splits two independent SETs doesn't handle this case correctly when it
1620 updates the register status. Also check the case where the first
1621 SET's destination is unused. That would not cause incorrect code, but
1622 does cause an unneeded insn to remain. */
1624 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1625 && XVECLEN (newpat, 0) == 2
1626 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1627 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1628 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1629 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1630 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1631 && asm_noperands (newpat) < 0)
1633 newpat = XVECEXP (newpat, 0, 0);
1634 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1637 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1638 && XVECLEN (newpat, 0) == 2
1639 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1640 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1641 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1642 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1643 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1644 && asm_noperands (newpat) < 0)
1646 newpat = XVECEXP (newpat, 0, 1);
1647 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1650 /* See if this is an XOR. If so, perhaps the problem is that the
1651 constant is out of range. Replace it with a complemented XOR with
1652 a complemented constant; it might be in range. */
1654 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1655 && GET_CODE (SET_SRC (newpat)) == XOR
1656 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1657 && ((temp = simplify_unary_operation (NOT,
1658 GET_MODE (SET_SRC (newpat)),
1659 XEXP (SET_SRC (newpat), 1),
1660 GET_MODE (SET_SRC (newpat))))
1663 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1665 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1666 gen_unary (NOT, i_mode,
1667 gen_binary (XOR, i_mode,
1668 XEXP (SET_SRC (newpat), 0),
1671 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1672 if (insn_code_number >= 0)
1676 /* If we were combining three insns and the result is a simple SET
1677 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1678 insns. There are two ways to do this. It can be split using a
1679 machine-specific method (like when you have an addition of a large
1680 constant) or by combine in the function find_split_point. */
1682 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1683 && asm_noperands (newpat) < 0)
1685 rtx m_split, *split;
1686 rtx ni2dest = i2dest;
1688 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1689 use I2DEST as a scratch register will help. In the latter case,
1690 convert I2DEST to the mode of the source of NEWPAT if we can. */
1692 m_split = split_insns (newpat, i3);
1694 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1695 inputs of NEWPAT. */
1697 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1698 possible to try that as a scratch reg. This would require adding
1699 more code to make it work though. */
1701 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1703 /* If I2DEST is a hard register or the only use of a pseudo,
1704 we can change its mode. */
1705 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1706 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1707 && GET_CODE (i2dest) == REG
1708 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1709 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1710 && ! REG_USERVAR_P (i2dest))))
1711 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1714 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1715 gen_rtvec (2, newpat,
1722 if (m_split && GET_CODE (m_split) == SEQUENCE
1723 && XVECLEN (m_split, 0) == 2
1724 && (next_real_insn (i2) == i3
1725 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1729 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1730 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1732 i3set = single_set (XVECEXP (m_split, 0, 1));
1733 i2set = single_set (XVECEXP (m_split, 0, 0));
1735 /* In case we changed the mode of I2DEST, replace it in the
1736 pseudo-register table here. We can't do it above in case this
1737 code doesn't get executed and we do a split the other way. */
1739 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1740 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1742 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1744 /* If I2 or I3 has multiple SETs, we won't know how to track
1745 register status, so don't use these insns. */
1747 if (i2_code_number >= 0 && i2set && i3set)
1748 insn_code_number = recog_for_combine (&newi3pat, i3,
1751 if (insn_code_number >= 0)
1754 /* It is possible that both insns now set the destination of I3.
1755 If so, we must show an extra use of it. */
1757 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1758 && GET_CODE (SET_DEST (i2set)) == REG
1759 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1760 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1763 /* If we can split it and use I2DEST, go ahead and see if that
1764 helps things be recognized. Verify that none of the registers
1765 are set between I2 and I3. */
1766 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1768 && GET_CODE (i2dest) == REG
1770 /* We need I2DEST in the proper mode. If it is a hard register
1771 or the only use of a pseudo, we can change its mode. */
1772 && (GET_MODE (*split) == GET_MODE (i2dest)
1773 || GET_MODE (*split) == VOIDmode
1774 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1775 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1776 && ! REG_USERVAR_P (i2dest)))
1777 && (next_real_insn (i2) == i3
1778 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1779 /* We can't overwrite I2DEST if its value is still used by
1781 && ! reg_referenced_p (i2dest, newpat))
1783 rtx newdest = i2dest;
1785 /* Get NEWDEST as a register in the proper mode. We have already
1786 validated that we can do this. */
1787 if (GET_MODE (i2dest) != GET_MODE (*split)
1788 && GET_MODE (*split) != VOIDmode)
1790 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1792 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1793 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1796 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1797 an ASHIFT. This can occur if it was inside a PLUS and hence
1798 appeared to be a memory address. This is a kludge. */
1799 if (GET_CODE (*split) == MULT
1800 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1801 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1802 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1803 XEXP (*split, 0), GEN_INT (i)));
1805 #ifdef INSN_SCHEDULING
1806 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1807 be written as a ZERO_EXTEND. */
1808 if (GET_CODE (*split) == SUBREG
1809 && GET_CODE (SUBREG_REG (*split)) == MEM)
1810 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1814 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1815 SUBST (*split, newdest);
1816 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1817 if (i2_code_number >= 0)
1818 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1822 /* Check for a case where we loaded from memory in a narrow mode and
1823 then sign extended it, but we need both registers. In that case,
1824 we have a PARALLEL with both loads from the same memory location.
1825 We can split this into a load from memory followed by a register-register
1826 copy. This saves at least one insn, more if register allocation can
1827 eliminate the copy. */
1829 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1830 && GET_CODE (newpat) == PARALLEL
1831 && XVECLEN (newpat, 0) == 2
1832 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1833 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1834 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1835 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1836 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1837 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1839 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1840 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1841 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1842 SET_SRC (XVECEXP (newpat, 0, 1)))
1843 && ! find_reg_note (i3, REG_UNUSED,
1844 SET_DEST (XVECEXP (newpat, 0, 0))))
1848 newi2pat = XVECEXP (newpat, 0, 0);
1849 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1850 newpat = XVECEXP (newpat, 0, 1);
1851 SUBST (SET_SRC (newpat),
1852 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1853 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1854 if (i2_code_number >= 0)
1855 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1857 if (insn_code_number >= 0)
1862 /* If we will be able to accept this, we have made a change to the
1863 destination of I3. This can invalidate a LOG_LINKS pointing
1864 to I3. No other part of combine.c makes such a transformation.
1866 The new I3 will have a destination that was previously the
1867 destination of I1 or I2 and which was used in i2 or I3. Call
1868 distribute_links to make a LOG_LINK from the next use of
1869 that destination. */
1871 PATTERN (i3) = newpat;
1872 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1874 /* I3 now uses what used to be its destination and which is
1875 now I2's destination. That means we need a LOG_LINK from
1876 I3 to I2. But we used to have one, so we still will.
1878 However, some later insn might be using I2's dest and have
1879 a LOG_LINK pointing at I3. We must remove this link.
1880 The simplest way to remove the link is to point it at I1,
1881 which we know will be a NOTE. */
1883 for (insn = NEXT_INSN (i3);
1884 insn && (this_basic_block == n_basic_blocks - 1
1885 || insn != basic_block_head[this_basic_block + 1]);
1886 insn = NEXT_INSN (insn))
1888 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1889 && reg_referenced_p (ni2dest, PATTERN (insn)))
1891 for (link = LOG_LINKS (insn); link;
1892 link = XEXP (link, 1))
1893 if (XEXP (link, 0) == i3)
1894 XEXP (link, 0) = i1;
1902 /* Similarly, check for a case where we have a PARALLEL of two independent
1903 SETs but we started with three insns. In this case, we can do the sets
1904 as two separate insns. This case occurs when some SET allows two
1905 other insns to combine, but the destination of that SET is still live. */
1907 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1908 && GET_CODE (newpat) == PARALLEL
1909 && XVECLEN (newpat, 0) == 2
1910 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1911 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1912 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1913 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1914 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1915 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1916 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1918 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1919 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1920 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1921 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1922 XVECEXP (newpat, 0, 0))
1923 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1924 XVECEXP (newpat, 0, 1)))
1926 newi2pat = XVECEXP (newpat, 0, 1);
1927 newpat = XVECEXP (newpat, 0, 0);
1929 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1930 if (i2_code_number >= 0)
1931 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1934 /* If it still isn't recognized, fail and change things back the way they
1936 if ((insn_code_number < 0
1937 /* Is the result a reasonable ASM_OPERANDS? */
1938 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1944 /* If we had to change another insn, make sure it is valid also. */
1945 if (undobuf.other_insn)
1947 rtx other_notes = REG_NOTES (undobuf.other_insn);
1948 rtx other_pat = PATTERN (undobuf.other_insn);
1949 rtx new_other_notes;
1952 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1955 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1961 PATTERN (undobuf.other_insn) = other_pat;
1963 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1964 are still valid. Then add any non-duplicate notes added by
1965 recog_for_combine. */
1966 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1968 next = XEXP (note, 1);
1970 if (REG_NOTE_KIND (note) == REG_UNUSED
1971 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1973 if (GET_CODE (XEXP (note, 0)) == REG)
1974 reg_n_deaths[REGNO (XEXP (note, 0))]--;
1976 remove_note (undobuf.other_insn, note);
1980 for (note = new_other_notes; note; note = XEXP (note, 1))
1981 if (GET_CODE (XEXP (note, 0)) == REG)
1982 reg_n_deaths[REGNO (XEXP (note, 0))]++;
1984 distribute_notes (new_other_notes, undobuf.other_insn,
1985 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1988 /* We now know that we can do this combination. Merge the insns and
1989 update the status of registers and LOG_LINKS. */
1992 rtx i3notes, i2notes, i1notes = 0;
1993 rtx i3links, i2links, i1links = 0;
1995 int all_adjacent = (next_real_insn (i2) == i3
1996 && (i1 == 0 || next_real_insn (i1) == i2));
1998 /* Compute which registers we expect to eliminate. */
1999 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2001 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2003 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2005 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2006 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2008 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2010 /* Ensure that we do not have something that should not be shared but
2011 occurs multiple times in the new insns. Check this by first
2012 resetting all the `used' flags and then copying anything is shared. */
2014 reset_used_flags (i3notes);
2015 reset_used_flags (i2notes);
2016 reset_used_flags (i1notes);
2017 reset_used_flags (newpat);
2018 reset_used_flags (newi2pat);
2019 if (undobuf.other_insn)
2020 reset_used_flags (PATTERN (undobuf.other_insn));
2022 i3notes = copy_rtx_if_shared (i3notes);
2023 i2notes = copy_rtx_if_shared (i2notes);
2024 i1notes = copy_rtx_if_shared (i1notes);
2025 newpat = copy_rtx_if_shared (newpat);
2026 newi2pat = copy_rtx_if_shared (newi2pat);
2027 if (undobuf.other_insn)
2028 reset_used_flags (PATTERN (undobuf.other_insn));
2030 INSN_CODE (i3) = insn_code_number;
2031 PATTERN (i3) = newpat;
2032 if (undobuf.other_insn)
2033 INSN_CODE (undobuf.other_insn) = other_code_number;
2035 /* We had one special case above where I2 had more than one set and
2036 we replaced a destination of one of those sets with the destination
2037 of I3. In that case, we have to update LOG_LINKS of insns later
2038 in this basic block. Note that this (expensive) case is rare. */
2040 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2041 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2042 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2043 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2044 && ! find_reg_note (i2, REG_UNUSED,
2045 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2046 for (temp = NEXT_INSN (i2);
2047 temp && (this_basic_block == n_basic_blocks - 1
2048 || basic_block_head[this_basic_block] != temp);
2049 temp = NEXT_INSN (temp))
2050 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2051 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2052 if (XEXP (link, 0) == i2)
2053 XEXP (link, 0) = i3;
2062 INSN_CODE (i2) = i2_code_number;
2063 PATTERN (i2) = newi2pat;
2067 PUT_CODE (i2, NOTE);
2068 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2069 NOTE_SOURCE_FILE (i2) = 0;
2076 PUT_CODE (i1, NOTE);
2077 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2078 NOTE_SOURCE_FILE (i1) = 0;
2081 /* Get death notes for everything that is now used in either I3 or
2082 I2 and used to die in a previous insn. */
2084 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2086 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2088 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2090 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2093 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2096 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2099 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2102 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2103 know these are REG_UNUSED and want them to go to the desired insn,
2104 so we always pass it as i3. We have not counted the notes in
2105 reg_n_deaths yet, so we need to do so now. */
2107 if (newi2pat && new_i2_notes)
2109 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2110 if (GET_CODE (XEXP (temp, 0)) == REG)
2111 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2113 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2118 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2119 if (GET_CODE (XEXP (temp, 0)) == REG)
2120 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2122 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2125 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2126 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2127 Show an additional death due to the REG_DEAD note we make here. If
2128 we discard it in distribute_notes, we will decrement it again. */
2132 if (GET_CODE (i3dest_killed) == REG)
2133 reg_n_deaths[REGNO (i3dest_killed)]++;
2135 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2137 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2138 NULL_RTX, NULL_RTX);
2141 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2142 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2143 we passed I3 in that case, it might delete I2. */
2145 if (i2dest_in_i2src)
2147 if (GET_CODE (i2dest) == REG)
2148 reg_n_deaths[REGNO (i2dest)]++;
2150 if (newi2pat && reg_set_p (i2dest, newi2pat))
2151 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2152 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2154 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2155 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2156 NULL_RTX, NULL_RTX);
2159 if (i1dest_in_i1src)
2161 if (GET_CODE (i1dest) == REG)
2162 reg_n_deaths[REGNO (i1dest)]++;
2164 if (newi2pat && reg_set_p (i1dest, newi2pat))
2165 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2166 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2168 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2169 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2170 NULL_RTX, NULL_RTX);
2173 distribute_links (i3links);
2174 distribute_links (i2links);
2175 distribute_links (i1links);
2177 if (GET_CODE (i2dest) == REG)
2180 rtx i2_insn = 0, i2_val = 0, set;
2182 /* The insn that used to set this register doesn't exist, and
2183 this life of the register may not exist either. See if one of
2184 I3's links points to an insn that sets I2DEST. If it does,
2185 that is now the last known value for I2DEST. If we don't update
2186 this and I2 set the register to a value that depended on its old
2187 contents, we will get confused. If this insn is used, thing
2188 will be set correctly in combine_instructions. */
2190 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2191 if ((set = single_set (XEXP (link, 0))) != 0
2192 && rtx_equal_p (i2dest, SET_DEST (set)))
2193 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2195 record_value_for_reg (i2dest, i2_insn, i2_val);
2197 /* If the reg formerly set in I2 died only once and that was in I3,
2198 zero its use count so it won't make `reload' do any work. */
2199 if (! added_sets_2 && newi2pat == 0)
2201 regno = REGNO (i2dest);
2202 reg_n_sets[regno]--;
2203 if (reg_n_sets[regno] == 0
2204 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2205 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2206 reg_n_refs[regno] = 0;
2210 if (i1 && GET_CODE (i1dest) == REG)
2213 rtx i1_insn = 0, i1_val = 0, set;
2215 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2216 if ((set = single_set (XEXP (link, 0))) != 0
2217 && rtx_equal_p (i1dest, SET_DEST (set)))
2218 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2220 record_value_for_reg (i1dest, i1_insn, i1_val);
2222 regno = REGNO (i1dest);
2225 reg_n_sets[regno]--;
2226 if (reg_n_sets[regno] == 0
2227 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2228 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2229 reg_n_refs[regno] = 0;
2233 /* Update reg_nonzero_bits et al for any changes that may have been made
2236 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2238 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2240 /* If I3 is now an unconditional jump, ensure that it has a
2241 BARRIER following it since it may have initially been a
2242 conditional jump. It may also be the last nonnote insn. */
2244 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2245 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2246 || GET_CODE (temp) != BARRIER))
2247 emit_barrier_after (i3);
2250 combine_successes++;
2252 return newi2pat ? i2 : i3;
2255 /* Undo all the modifications recorded in undobuf. */
2261 if (undobuf.num_undo > MAX_UNDO)
2262 undobuf.num_undo = MAX_UNDO;
2263 for (i = undobuf.num_undo - 1; i >= 0; i--)
2265 if (undobuf.undo[i].is_int)
2266 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2268 *undobuf.undo[i].where.r = undobuf.undo[i].old_contents.r;
2272 obfree (undobuf.storage);
2273 undobuf.num_undo = 0;
2276 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2277 where we have an arithmetic expression and return that point. LOC will
2280 try_combine will call this function to see if an insn can be split into
2284 find_split_point (loc, insn)
2289 enum rtx_code code = GET_CODE (x);
2291 int len = 0, pos, unsignedp;
2294 /* First special-case some codes. */
2298 #ifdef INSN_SCHEDULING
2299 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2301 if (GET_CODE (SUBREG_REG (x)) == MEM)
2304 return find_split_point (&SUBREG_REG (x), insn);
2308 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2309 using LO_SUM and HIGH. */
2310 if (GET_CODE (XEXP (x, 0)) == CONST
2311 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2314 gen_rtx_combine (LO_SUM, Pmode,
2315 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2317 return &XEXP (XEXP (x, 0), 0);
2321 /* If we have a PLUS whose second operand is a constant and the
2322 address is not valid, perhaps will can split it up using
2323 the machine-specific way to split large constants. We use
2324 the first psuedo-reg (one of the virtual regs) as a placeholder;
2325 it will not remain in the result. */
2326 if (GET_CODE (XEXP (x, 0)) == PLUS
2327 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2328 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2330 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2331 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2334 /* This should have produced two insns, each of which sets our
2335 placeholder. If the source of the second is a valid address,
2336 we can make put both sources together and make a split point
2339 if (seq && XVECLEN (seq, 0) == 2
2340 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2341 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2342 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2343 && ! reg_mentioned_p (reg,
2344 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2345 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2346 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2347 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2348 && memory_address_p (GET_MODE (x),
2349 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2351 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2352 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2354 /* Replace the placeholder in SRC2 with SRC1. If we can
2355 find where in SRC2 it was placed, that can become our
2356 split point and we can replace this address with SRC2.
2357 Just try two obvious places. */
2359 src2 = replace_rtx (src2, reg, src1);
2361 if (XEXP (src2, 0) == src1)
2362 split = &XEXP (src2, 0);
2363 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2364 && XEXP (XEXP (src2, 0), 0) == src1)
2365 split = &XEXP (XEXP (src2, 0), 0);
2369 SUBST (XEXP (x, 0), src2);
2374 /* If that didn't work, perhaps the first operand is complex and
2375 needs to be computed separately, so make a split point there.
2376 This will occur on machines that just support REG + CONST
2377 and have a constant moved through some previous computation. */
2379 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2380 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2381 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2383 return &XEXP (XEXP (x, 0), 0);
2389 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2390 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2391 we need to put the operand into a register. So split at that
2394 if (SET_DEST (x) == cc0_rtx
2395 && GET_CODE (SET_SRC (x)) != COMPARE
2396 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2397 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2398 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2399 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2400 return &SET_SRC (x);
2403 /* See if we can split SET_SRC as it stands. */
2404 split = find_split_point (&SET_SRC (x), insn);
2405 if (split && split != &SET_SRC (x))
2408 /* See if this is a bitfield assignment with everything constant. If
2409 so, this is an IOR of an AND, so split it into that. */
2410 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2411 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2412 <= HOST_BITS_PER_WIDE_INT)
2413 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2414 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2415 && GET_CODE (SET_SRC (x)) == CONST_INT
2416 && ((INTVAL (XEXP (SET_DEST (x), 1))
2417 + INTVAL (XEXP (SET_DEST (x), 2)))
2418 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2419 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2421 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2422 int len = INTVAL (XEXP (SET_DEST (x), 1));
2423 int src = INTVAL (SET_SRC (x));
2424 rtx dest = XEXP (SET_DEST (x), 0);
2425 enum machine_mode mode = GET_MODE (dest);
2426 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2429 pos = GET_MODE_BITSIZE (mode) - len - pos;
2434 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2437 gen_binary (IOR, mode,
2438 gen_binary (AND, mode, dest,
2439 GEN_INT (~ (mask << pos)
2440 & GET_MODE_MASK (mode))),
2441 GEN_INT (src << pos)));
2443 SUBST (SET_DEST (x), dest);
2445 split = find_split_point (&SET_SRC (x), insn);
2446 if (split && split != &SET_SRC (x))
2450 /* Otherwise, see if this is an operation that we can split into two.
2451 If so, try to split that. */
2452 code = GET_CODE (SET_SRC (x));
2457 /* If we are AND'ing with a large constant that is only a single
2458 bit and the result is only being used in a context where we
2459 need to know if it is zero or non-zero, replace it with a bit
2460 extraction. This will avoid the large constant, which might
2461 have taken more than one insn to make. If the constant were
2462 not a valid argument to the AND but took only one insn to make,
2463 this is no worse, but if it took more than one insn, it will
2466 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2467 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2468 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2469 && GET_CODE (SET_DEST (x)) == REG
2470 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2471 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2472 && XEXP (*split, 0) == SET_DEST (x)
2473 && XEXP (*split, 1) == const0_rtx)
2476 make_extraction (GET_MODE (SET_DEST (x)),
2477 XEXP (SET_SRC (x), 0),
2478 pos, NULL_RTX, 1, 1, 0, 0));
2479 return find_split_point (loc, insn);
2484 inner = XEXP (SET_SRC (x), 0);
2486 len = GET_MODE_BITSIZE (GET_MODE (inner));
2492 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2493 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2495 inner = XEXP (SET_SRC (x), 0);
2496 len = INTVAL (XEXP (SET_SRC (x), 1));
2497 pos = INTVAL (XEXP (SET_SRC (x), 2));
2500 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2502 unsignedp = (code == ZERO_EXTRACT);
2507 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2509 enum machine_mode mode = GET_MODE (SET_SRC (x));
2511 /* For unsigned, we have a choice of a shift followed by an
2512 AND or two shifts. Use two shifts for field sizes where the
2513 constant might be too large. We assume here that we can
2514 always at least get 8-bit constants in an AND insn, which is
2515 true for every current RISC. */
2517 if (unsignedp && len <= 8)
2522 gen_rtx_combine (LSHIFTRT, mode,
2523 gen_lowpart_for_combine (mode, inner),
2525 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2527 split = find_split_point (&SET_SRC (x), insn);
2528 if (split && split != &SET_SRC (x))
2535 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2536 gen_rtx_combine (ASHIFT, mode,
2537 gen_lowpart_for_combine (mode, inner),
2538 GEN_INT (GET_MODE_BITSIZE (mode)
2540 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2542 split = find_split_point (&SET_SRC (x), insn);
2543 if (split && split != &SET_SRC (x))
2548 /* See if this is a simple operation with a constant as the second
2549 operand. It might be that this constant is out of range and hence
2550 could be used as a split point. */
2551 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2552 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2553 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2554 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2555 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2556 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2557 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2559 return &XEXP (SET_SRC (x), 1);
2561 /* Finally, see if this is a simple operation with its first operand
2562 not in a register. The operation might require this operand in a
2563 register, so return it as a split point. We can always do this
2564 because if the first operand were another operation, we would have
2565 already found it as a split point. */
2566 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2567 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2568 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2569 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2570 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2571 return &XEXP (SET_SRC (x), 0);
2577 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2578 it is better to write this as (not (ior A B)) so we can split it.
2579 Similarly for IOR. */
2580 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2583 gen_rtx_combine (NOT, GET_MODE (x),
2584 gen_rtx_combine (code == IOR ? AND : IOR,
2586 XEXP (XEXP (x, 0), 0),
2587 XEXP (XEXP (x, 1), 0))));
2588 return find_split_point (loc, insn);
2591 /* Many RISC machines have a large set of logical insns. If the
2592 second operand is a NOT, put it first so we will try to split the
2593 other operand first. */
2594 if (GET_CODE (XEXP (x, 1)) == NOT)
2596 rtx tem = XEXP (x, 0);
2597 SUBST (XEXP (x, 0), XEXP (x, 1));
2598 SUBST (XEXP (x, 1), tem);
2603 /* Otherwise, select our actions depending on our rtx class. */
2604 switch (GET_RTX_CLASS (code))
2606 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2608 split = find_split_point (&XEXP (x, 2), insn);
2611 /* ... fall through ... */
2615 split = find_split_point (&XEXP (x, 1), insn);
2618 /* ... fall through ... */
2620 /* Some machines have (and (shift ...) ...) insns. If X is not
2621 an AND, but XEXP (X, 0) is, use it as our split point. */
2622 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2623 return &XEXP (x, 0);
2625 split = find_split_point (&XEXP (x, 0), insn);
2631 /* Otherwise, we don't have a split point. */
2635 /* Throughout X, replace FROM with TO, and return the result.
2636 The result is TO if X is FROM;
2637 otherwise the result is X, but its contents may have been modified.
2638 If they were modified, a record was made in undobuf so that
2639 undo_all will (among other things) return X to its original state.
2641 If the number of changes necessary is too much to record to undo,
2642 the excess changes are not made, so the result is invalid.
2643 The changes already made can still be undone.
2644 undobuf.num_undo is incremented for such changes, so by testing that
2645 the caller can tell whether the result is valid.
2647 `n_occurrences' is incremented each time FROM is replaced.
2649 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2651 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2652 by copying if `n_occurrences' is non-zero. */
2655 subst (x, from, to, in_dest, unique_copy)
2656 register rtx x, from, to;
2661 register int len, i;
2662 register enum rtx_code code = GET_CODE (x), orig_code = code;
2664 enum machine_mode mode = GET_MODE (x);
2665 enum machine_mode op0_mode = VOIDmode;
2670 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2671 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2672 If it is 0, that cannot be done. We can now do this for any MEM
2673 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2674 If not for that, MEM's would very rarely be safe. */
2676 /* Reject MODEs bigger than a word, because we might not be able
2677 to reference a two-register group starting with an arbitrary register
2678 (and currently gen_lowpart might crash for a SUBREG). */
2680 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2681 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2683 /* Two expressions are equal if they are identical copies of a shared
2684 RTX or if they are both registers with the same register number
2687 #define COMBINE_RTX_EQUAL_P(X,Y) \
2689 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2690 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2692 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2695 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2698 /* If X and FROM are the same register but different modes, they will
2699 not have been seen as equal above. However, flow.c will make a
2700 LOG_LINKS entry for that case. If we do nothing, we will try to
2701 rerecognize our original insn and, when it succeeds, we will
2702 delete the feeding insn, which is incorrect.
2704 So force this insn not to match in this (rare) case. */
2705 if (! in_dest && code == REG && GET_CODE (from) == REG
2706 && REGNO (x) == REGNO (from))
2707 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2709 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2710 of which may contain things that can be combined. */
2711 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2714 /* It is possible to have a subexpression appear twice in the insn.
2715 Suppose that FROM is a register that appears within TO.
2716 Then, after that subexpression has been scanned once by `subst',
2717 the second time it is scanned, TO may be found. If we were
2718 to scan TO here, we would find FROM within it and create a
2719 self-referent rtl structure which is completely wrong. */
2720 if (COMBINE_RTX_EQUAL_P (x, to))
2723 len = GET_RTX_LENGTH (code);
2724 fmt = GET_RTX_FORMAT (code);
2726 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2727 set up to skip this common case. All other cases where we want to
2728 suppress replacing something inside a SET_SRC are handled via the
2731 && (GET_CODE (SET_DEST (x)) == REG
2732 || GET_CODE (SET_DEST (x)) == CC0
2733 || GET_CODE (SET_DEST (x)) == PC))
2736 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2738 op0_mode = GET_MODE (XEXP (x, 0));
2740 for (i = 0; i < len; i++)
2745 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2748 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2750 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2755 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2757 /* If this substitution failed, this whole thing fails. */
2758 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2762 SUBST (XVECEXP (x, i, j), new);
2765 else if (fmt[i] == 'e')
2769 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2771 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2775 /* If we are in a SET_DEST, suppress most cases unless we
2776 have gone inside a MEM, in which case we want to
2777 simplify the address. We assume here that things that
2778 are actually part of the destination have their inner
2779 parts in the first expression. This is true for SUBREG,
2780 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2781 things aside from REG and MEM that should appear in a
2783 new = subst (XEXP (x, i), from, to,
2785 && (code == SUBREG || code == STRICT_LOW_PART
2786 || code == ZERO_EXTRACT))
2788 && i == 0), unique_copy);
2790 /* If we found that we will have to reject this combination,
2791 indicate that by returning the CLOBBER ourselves, rather than
2792 an expression containing it. This will speed things up as
2793 well as prevent accidents where two CLOBBERs are considered
2794 to be equal, thus producing an incorrect simplification. */
2796 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2799 SUBST (XEXP (x, i), new);
2803 /* We come back to here if we have replaced the expression with one of
2804 a different code and it is likely that further simplification will be
2809 /* If we have restarted more than 4 times, we are probably looping, so
2811 if (++n_restarts > 4)
2814 /* If we are restarting at all, it means that we no longer know the
2815 original mode of operand 0 (since we have probably changed the
2819 op0_mode = VOIDmode;
2821 code = GET_CODE (x);
2823 /* If this is a commutative operation, put a constant last and a complex
2824 expression first. We don't need to do this for comparisons here. */
2825 if (GET_RTX_CLASS (code) == 'c'
2826 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2827 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2828 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2829 || (GET_CODE (XEXP (x, 0)) == SUBREG
2830 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2831 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2834 SUBST (XEXP (x, 0), XEXP (x, 1));
2835 SUBST (XEXP (x, 1), temp);
2838 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2839 sign extension of a PLUS with a constant, reverse the order of the sign
2840 extension and the addition. Note that this not the same as the original
2841 code, but overflow is undefined for signed values. Also note that the
2842 PLUS will have been partially moved "inside" the sign-extension, so that
2843 the first operand of X will really look like:
2844 (ashiftrt (plus (ashift A C4) C5) C4).
2846 (plus (ashiftrt (ashift A C4) C2) C4)
2847 and replace the first operand of X with that expression. Later parts
2848 of this function may simplify the expression further.
2850 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2851 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2852 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2854 We do this to simplify address expressions. */
2856 if ((code == PLUS || code == MINUS || code == MULT)
2857 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2858 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2859 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2860 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2861 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2862 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2863 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2864 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2865 XEXP (XEXP (XEXP (x, 0), 0), 1),
2866 XEXP (XEXP (x, 0), 1))) != 0)
2869 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2870 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2871 INTVAL (XEXP (XEXP (x, 0), 1)));
2873 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2874 INTVAL (XEXP (XEXP (x, 0), 1)));
2876 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2879 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2880 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2881 things. Don't deal with operations that change modes here. */
2883 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2884 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2886 /* Don't do this by using SUBST inside X since we might be messing
2887 up a shared expression. */
2888 rtx cond = XEXP (XEXP (x, 0), 0);
2889 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2891 pc_rtx, pc_rtx, 0, 0);
2892 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2894 pc_rtx, pc_rtx, 0, 0);
2897 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2901 else if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2902 && GET_CODE (XEXP (x, 1)) == IF_THEN_ELSE)
2904 /* Don't do this by using SUBST inside X since we might be messing
2905 up a shared expression. */
2906 rtx cond = XEXP (XEXP (x, 1), 0);
2907 rtx t_arm = subst (gen_binary (code, mode, XEXP (x, 0),
2908 XEXP (XEXP (x, 1), 1)),
2909 pc_rtx, pc_rtx, 0, 0);
2910 rtx f_arm = subst (gen_binary (code, mode, XEXP (x, 0),
2911 XEXP (XEXP (x, 1), 2)),
2912 pc_rtx, pc_rtx, 0, 0);
2914 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2918 else if (GET_RTX_CLASS (code) == '1'
2919 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2920 && GET_MODE (XEXP (x, 0)) == mode)
2922 rtx cond = XEXP (XEXP (x, 0), 0);
2923 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2924 pc_rtx, pc_rtx, 0, 0);
2925 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2926 pc_rtx, pc_rtx, 0, 0);
2928 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2932 /* Try to fold this expression in case we have constants that weren't
2935 switch (GET_RTX_CLASS (code))
2938 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2941 temp = simplify_relational_operation (code, op0_mode,
2942 XEXP (x, 0), XEXP (x, 1));
2943 #ifdef FLOAT_STORE_FLAG_VALUE
2944 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2945 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2946 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2951 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2955 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2956 XEXP (x, 1), XEXP (x, 2));
2961 x = temp, code = GET_CODE (temp);
2963 /* First see if we can apply the inverse distributive law. */
2964 if (code == PLUS || code == MINUS
2965 || code == AND || code == IOR || code == XOR)
2967 x = apply_distributive_law (x);
2968 code = GET_CODE (x);
2971 /* If CODE is an associative operation not otherwise handled, see if we
2972 can associate some operands. This can win if they are constants or
2973 if they are logically related (i.e. (a & b) & a. */
2974 if ((code == PLUS || code == MINUS
2975 || code == MULT || code == AND || code == IOR || code == XOR
2976 || code == DIV || code == UDIV
2977 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2978 && INTEGRAL_MODE_P (mode))
2980 if (GET_CODE (XEXP (x, 0)) == code)
2982 rtx other = XEXP (XEXP (x, 0), 0);
2983 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2984 rtx inner_op1 = XEXP (x, 1);
2987 /* Make sure we pass the constant operand if any as the second
2988 one if this is a commutative operation. */
2989 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2991 rtx tem = inner_op0;
2992 inner_op0 = inner_op1;
2995 inner = simplify_binary_operation (code == MINUS ? PLUS
2996 : code == DIV ? MULT
2997 : code == UDIV ? MULT
2999 mode, inner_op0, inner_op1);
3001 /* For commutative operations, try the other pair if that one
3003 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3005 other = XEXP (XEXP (x, 0), 1);
3006 inner = simplify_binary_operation (code, mode,
3007 XEXP (XEXP (x, 0), 0),
3013 x = gen_binary (code, mode, other, inner);
3020 /* A little bit of algebraic simplification here. */
3024 /* Ensure that our address has any ASHIFTs converted to MULT in case
3025 address-recognizing predicates are called later. */
3026 temp = make_compound_operation (XEXP (x, 0), MEM);
3027 SUBST (XEXP (x, 0), temp);
3031 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3032 is paradoxical. If we can't do that safely, then it becomes
3033 something nonsensical so that this combination won't take place. */
3035 if (GET_CODE (SUBREG_REG (x)) == MEM
3036 && (GET_MODE_SIZE (mode)
3037 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3039 rtx inner = SUBREG_REG (x);
3040 int endian_offset = 0;
3041 /* Don't change the mode of the MEM
3042 if that would change the meaning of the address. */
3043 if (MEM_VOLATILE_P (SUBREG_REG (x))
3044 || mode_dependent_address_p (XEXP (inner, 0)))
3045 return gen_rtx (CLOBBER, mode, const0_rtx);
3047 #if BYTES_BIG_ENDIAN
3048 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3049 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3050 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3051 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
3053 /* Note if the plus_constant doesn't make a valid address
3054 then this combination won't be accepted. */
3055 x = gen_rtx (MEM, mode,
3056 plus_constant (XEXP (inner, 0),
3057 (SUBREG_WORD (x) * UNITS_PER_WORD
3059 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3060 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3061 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3065 /* If we are in a SET_DEST, these other cases can't apply. */
3069 /* Changing mode twice with SUBREG => just change it once,
3070 or not at all if changing back to starting mode. */
3071 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3073 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3074 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3075 return SUBREG_REG (SUBREG_REG (x));
3077 SUBST_INT (SUBREG_WORD (x),
3078 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3079 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3082 /* SUBREG of a hard register => just change the register number
3083 and/or mode. If the hard register is not valid in that mode,
3084 suppress this combination. If the hard register is the stack,
3085 frame, or argument pointer, leave this as a SUBREG. */
3087 if (GET_CODE (SUBREG_REG (x)) == REG
3088 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3089 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3090 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3091 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3093 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3095 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3097 return gen_rtx (REG, mode,
3098 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3100 return gen_rtx (CLOBBER, mode, const0_rtx);
3103 /* For a constant, try to pick up the part we want. Handle a full
3104 word and low-order part. Only do this if we are narrowing
3105 the constant; if it is being widened, we have no idea what
3106 the extra bits will have been set to. */
3108 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3109 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3110 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3111 && GET_MODE_CLASS (mode) == MODE_INT)
3113 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3119 /* If we want a subreg of a constant, at offset 0,
3120 take the low bits. On a little-endian machine, that's
3121 always valid. On a big-endian machine, it's valid
3122 only if the constant's mode fits in one word. */
3123 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3124 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode)
3125 #if WORDS_BIG_ENDIAN
3126 && GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD
3129 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3131 /* If we are narrowing the object, we need to see if we can simplify
3132 the expression for the object knowing that we only need the
3135 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
3136 && subreg_lowpart_p (x))
3137 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
3142 /* (not (plus X -1)) can become (neg X). */
3143 if (GET_CODE (XEXP (x, 0)) == PLUS
3144 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3146 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3150 /* Similarly, (not (neg X)) is (plus X -1). */
3151 if (GET_CODE (XEXP (x, 0)) == NEG)
3153 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3157 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3158 if (GET_CODE (XEXP (x, 0)) == XOR
3159 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3160 && (temp = simplify_unary_operation (NOT, mode,
3161 XEXP (XEXP (x, 0), 1),
3164 SUBST (XEXP (XEXP (x, 0), 1), temp);
3168 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3169 other than 1, but that is not valid. We could do a similar
3170 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3171 but this doesn't seem common enough to bother with. */
3172 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3173 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3175 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3176 XEXP (XEXP (x, 0), 1));
3180 if (GET_CODE (XEXP (x, 0)) == SUBREG
3181 && subreg_lowpart_p (XEXP (x, 0))
3182 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3183 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3184 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3185 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3187 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3189 x = gen_rtx (ROTATE, inner_mode,
3190 gen_unary (NOT, inner_mode, const1_rtx),
3191 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3192 x = gen_lowpart_for_combine (mode, x);
3196 #if STORE_FLAG_VALUE == -1
3197 /* (not (comparison foo bar)) can be done by reversing the comparison
3199 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3200 && reversible_comparison_p (XEXP (x, 0)))
3201 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3202 mode, XEXP (XEXP (x, 0), 0),
3203 XEXP (XEXP (x, 0), 1));
3205 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3206 is (lt foo (const_int 0)), so we can perform the above
3209 if (XEXP (x, 1) == const1_rtx
3210 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3211 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3212 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3213 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3216 /* Apply De Morgan's laws to reduce number of patterns for machines
3217 with negating logical insns (and-not, nand, etc.). If result has
3218 only one NOT, put it first, since that is how the patterns are
3221 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3223 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3225 if (GET_CODE (in1) == NOT)
3226 in1 = XEXP (in1, 0);
3228 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3230 if (GET_CODE (in2) == NOT)
3231 in2 = XEXP (in2, 0);
3232 else if (GET_CODE (in2) == CONST_INT
3233 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3234 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3236 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3238 if (GET_CODE (in2) == NOT)
3241 in2 = in1; in1 = tem;
3244 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3251 /* (neg (plus X 1)) can become (not X). */
3252 if (GET_CODE (XEXP (x, 0)) == PLUS
3253 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3255 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3259 /* Similarly, (neg (not X)) is (plus X 1). */
3260 if (GET_CODE (XEXP (x, 0)) == NOT)
3262 x = plus_constant (XEXP (XEXP (x, 0), 0), 1);
3266 /* (neg (minus X Y)) can become (minus Y X). */
3267 if (GET_CODE (XEXP (x, 0)) == MINUS
3268 && (! FLOAT_MODE_P (mode)
3269 /* x-y != -(y-x) with IEEE floating point. */
3270 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3272 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3273 XEXP (XEXP (x, 0), 0));
3277 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3278 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3279 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3281 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3285 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3286 if we can then eliminate the NEG (e.g.,
3287 if the operand is a constant). */
3289 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3291 temp = simplify_unary_operation (NEG, mode,
3292 XEXP (XEXP (x, 0), 0), mode);
3295 SUBST (XEXP (XEXP (x, 0), 0), temp);
3300 temp = expand_compound_operation (XEXP (x, 0));
3302 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3303 replaced by (lshiftrt X C). This will convert
3304 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3306 if (GET_CODE (temp) == ASHIFTRT
3307 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3308 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3310 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3311 INTVAL (XEXP (temp, 1)));
3315 /* If X has only a single bit that might be nonzero, say, bit I, convert
3316 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3317 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3318 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3319 or a SUBREG of one since we'd be making the expression more
3320 complex if it was just a register. */
3322 if (GET_CODE (temp) != REG
3323 && ! (GET_CODE (temp) == SUBREG
3324 && GET_CODE (SUBREG_REG (temp)) == REG)
3325 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3327 rtx temp1 = simplify_shift_const
3328 (NULL_RTX, ASHIFTRT, mode,
3329 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3330 GET_MODE_BITSIZE (mode) - 1 - i),
3331 GET_MODE_BITSIZE (mode) - 1 - i);
3333 /* If all we did was surround TEMP with the two shifts, we
3334 haven't improved anything, so don't use it. Otherwise,
3335 we are better off with TEMP1. */
3336 if (GET_CODE (temp1) != ASHIFTRT
3337 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3338 || XEXP (XEXP (temp1, 0), 0) != temp)
3346 case FLOAT_TRUNCATE:
3347 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3348 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3349 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3350 return XEXP (XEXP (x, 0), 0);
3355 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3356 using cc0, in which case we want to leave it as a COMPARE
3357 so we can distinguish it from a register-register-copy. */
3358 if (XEXP (x, 1) == const0_rtx)
3361 /* In IEEE floating point, x-0 is not the same as x. */
3362 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3363 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))))
3364 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3370 /* (const (const X)) can become (const X). Do it this way rather than
3371 returning the inner CONST since CONST can be shared with a
3373 if (GET_CODE (XEXP (x, 0)) == CONST)
3374 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3379 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3380 can add in an offset. find_split_point will split this address up
3381 again if it doesn't match. */
3382 if (GET_CODE (XEXP (x, 0)) == HIGH
3383 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3389 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3390 outermost. That's because that's the way indexed addresses are
3391 supposed to appear. This code used to check many more cases, but
3392 they are now checked elsewhere. */
3393 if (GET_CODE (XEXP (x, 0)) == PLUS
3394 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3395 return gen_binary (PLUS, mode,
3396 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3398 XEXP (XEXP (x, 0), 1));
3400 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3401 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3402 bit-field and can be replaced by either a sign_extend or a
3403 sign_extract. The `and' may be a zero_extend. */
3404 if (GET_CODE (XEXP (x, 0)) == XOR
3405 && GET_CODE (XEXP (x, 1)) == CONST_INT
3406 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3407 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3408 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3409 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3410 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3411 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3412 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3413 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3414 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3415 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3418 x = simplify_shift_const
3419 (NULL_RTX, ASHIFTRT, mode,
3420 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3421 XEXP (XEXP (XEXP (x, 0), 0), 0),
3422 GET_MODE_BITSIZE (mode) - (i + 1)),
3423 GET_MODE_BITSIZE (mode) - (i + 1));
3427 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3428 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3429 is 1. This produces better code than the alternative immediately
3431 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3432 && reversible_comparison_p (XEXP (x, 0))
3433 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3434 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3436 x = gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3437 mode, XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1));
3438 x = gen_unary (NEG, mode, x);
3442 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3443 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3444 the bitsize of the mode - 1. This allows simplification of
3445 "a = (b & 8) == 0;" */
3446 if (XEXP (x, 1) == constm1_rtx
3447 && GET_CODE (XEXP (x, 0)) != REG
3448 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3449 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3450 && nonzero_bits (XEXP (x, 0), mode) == 1)
3452 x = simplify_shift_const
3453 (NULL_RTX, ASHIFTRT, mode,
3454 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3455 gen_rtx_combine (XOR, mode,
3456 XEXP (x, 0), const1_rtx),
3457 GET_MODE_BITSIZE (mode) - 1),
3458 GET_MODE_BITSIZE (mode) - 1);
3462 /* If we are adding two things that have no bits in common, convert
3463 the addition into an IOR. This will often be further simplified,
3464 for example in cases like ((a & 1) + (a & 2)), which can
3467 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3468 && (nonzero_bits (XEXP (x, 0), mode)
3469 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3471 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3477 #if STORE_FLAG_VALUE == 1
3478 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3480 if (XEXP (x, 0) == const1_rtx
3481 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3482 && reversible_comparison_p (XEXP (x, 1)))
3483 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3484 mode, XEXP (XEXP (x, 1), 0),
3485 XEXP (XEXP (x, 1), 1));
3488 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3489 (and <foo> (const_int pow2-1)) */
3490 if (GET_CODE (XEXP (x, 1)) == AND
3491 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3492 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3493 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3495 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3496 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3502 /* If we have (mult (plus A B) C), apply the distributive law and then
3503 the inverse distributive law to see if things simplify. This
3504 occurs mostly in addresses, often when unrolling loops. */
3506 if (GET_CODE (XEXP (x, 0)) == PLUS)
3508 x = apply_distributive_law
3509 (gen_binary (PLUS, mode,
3510 gen_binary (MULT, mode,
3511 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3512 gen_binary (MULT, mode,
3513 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3515 if (GET_CODE (x) != MULT)
3519 /* If this is multiplication by a power of two and its first operand is
3520 a shift, treat the multiply as a shift to allow the shifts to
3521 possibly combine. */
3522 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3523 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3524 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3525 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3526 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3527 || GET_CODE (XEXP (x, 0)) == ROTATE
3528 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3530 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3534 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3535 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3536 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3537 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3538 XEXP (XEXP (x, 0), 1));
3542 /* If this is a divide by a power of two, treat it as a shift if
3543 its first operand is a shift. */
3544 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3545 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3546 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3547 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3548 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3549 || GET_CODE (XEXP (x, 0)) == ROTATE
3550 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3552 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3558 case GT: case GTU: case GE: case GEU:
3559 case LT: case LTU: case LE: case LEU:
3560 /* If the first operand is a condition code, we can't do anything
3562 if (GET_CODE (XEXP (x, 0)) == COMPARE
3563 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3565 && XEXP (x, 0) != cc0_rtx
3569 rtx op0 = XEXP (x, 0);
3570 rtx op1 = XEXP (x, 1);
3571 enum rtx_code new_code;
3573 if (GET_CODE (op0) == COMPARE)
3574 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3576 /* Simplify our comparison, if possible. */
3577 new_code = simplify_comparison (code, &op0, &op1);
3579 #if STORE_FLAG_VALUE == 1
3580 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3581 if only the low-order bit is possibly nonzero in X (such as when
3582 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3583 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3584 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3587 Remove any ZERO_EXTRACT we made when thinking this was a
3588 comparison. It may now be simpler to use, e.g., an AND. If a
3589 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3590 the call to make_compound_operation in the SET case. */
3592 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3593 && op1 == const0_rtx
3594 && nonzero_bits (op0, mode) == 1)
3595 return gen_lowpart_for_combine (mode,
3596 expand_compound_operation (op0));
3598 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3599 && op1 == const0_rtx
3600 && (num_sign_bit_copies (op0, mode)
3601 == GET_MODE_BITSIZE (mode)))
3603 op0 = expand_compound_operation (op0);
3604 x = gen_unary (NEG, mode, gen_lowpart_for_combine (mode, op0));
3608 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3609 && op1 == const0_rtx
3610 && nonzero_bits (op0, mode) == 1)
3612 op0 = expand_compound_operation (op0);
3613 x = gen_binary (XOR, mode,
3614 gen_lowpart_for_combine (mode, op0),
3619 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3620 && op1 == const0_rtx
3621 && (num_sign_bit_copies (op0, mode)
3622 == GET_MODE_BITSIZE (mode)))
3624 op0 = expand_compound_operation (op0);
3625 x = plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3630 #if STORE_FLAG_VALUE == -1
3631 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3633 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3634 && op1 == const0_rtx
3635 && (num_sign_bit_copies (op0, mode)
3636 == GET_MODE_BITSIZE (mode)))
3637 return gen_lowpart_for_combine (mode,
3638 expand_compound_operation (op0));
3640 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3641 && op1 == const0_rtx
3642 && nonzero_bits (op0, mode) == 1)
3644 op0 = expand_compound_operation (op0);
3645 x = gen_unary (NEG, mode, gen_lowpart_for_combine (mode, op0));
3649 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3650 && op1 == const0_rtx
3651 && (num_sign_bit_copies (op0, mode)
3652 == GET_MODE_BITSIZE (mode)))
3654 op0 = expand_compound_operation (op0);
3655 x = gen_unary (NOT, mode, gen_lowpart_for_combine (mode, op0));
3659 /* If X is 0/1, (eq X 0) is X-1. */
3660 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3661 && op1 == const0_rtx
3662 && nonzero_bits (op0, mode) == 1)
3664 op0 = expand_compound_operation (op0);
3665 x = plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3670 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3671 one bit that might be nonzero, we can convert (ne x 0) to
3672 (ashift x c) where C puts the bit in the sign bit. Remove any
3673 AND with STORE_FLAG_VALUE when we are done, since we are only
3674 going to test the sign bit. */
3675 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3676 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3677 && (STORE_FLAG_VALUE
3678 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3679 && op1 == const0_rtx
3680 && mode == GET_MODE (op0)
3681 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3683 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3684 expand_compound_operation (op0),
3685 GET_MODE_BITSIZE (mode) - 1 - i);
3686 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3692 /* If the code changed, return a whole new comparison. */
3693 if (new_code != code)
3694 return gen_rtx_combine (new_code, mode, op0, op1);
3696 /* Otherwise, keep this operation, but maybe change its operands.
3697 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3698 SUBST (XEXP (x, 0), op0);
3699 SUBST (XEXP (x, 1), op1);
3704 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3705 used in it is being compared against certain values. Get the
3706 true and false comparisons and see if that says anything about the
3707 value of each arm. */
3709 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3710 && reversible_comparison_p (XEXP (x, 0))
3711 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3714 rtx from = XEXP (XEXP (x, 0), 0);
3715 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3716 enum rtx_code false_code = reverse_condition (true_code);
3717 rtx true_val = XEXP (XEXP (x, 0), 1);
3718 rtx false_val = true_val;
3719 rtx true_arm = XEXP (x, 1);
3720 rtx false_arm = XEXP (x, 2);
3723 /* If FALSE_CODE is EQ, swap the codes and arms. */
3725 if (false_code == EQ)
3727 swapped = 1, true_code = EQ, false_code = NE;
3728 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3731 /* If we are comparing against zero and the expression being tested
3732 has only a single bit that might be nonzero, that is its value
3733 when it is not equal to zero. Similarly if it is known to be
3736 if (true_code == EQ && true_val == const0_rtx
3737 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3738 false_code = EQ, false_val = GEN_INT (nzb);
3739 else if (true_code == EQ && true_val == const0_rtx
3740 && (num_sign_bit_copies (from, GET_MODE (from))
3741 == GET_MODE_BITSIZE (GET_MODE (from))))
3742 false_code = EQ, false_val = constm1_rtx;
3744 /* Now simplify an arm if we know the value of the register
3745 in the branch and it is used in the arm. Be carefull due to
3746 the potential of locally-shared RTL. */
3748 if (reg_mentioned_p (from, true_arm))
3749 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3751 pc_rtx, pc_rtx, 0, 0);
3752 if (reg_mentioned_p (from, false_arm))
3753 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3755 pc_rtx, pc_rtx, 0, 0);
3757 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3758 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3761 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3762 reversed, do so to avoid needing two sets of patterns for
3763 subtract-and-branch insns. Similarly if we have a constant in that
3764 position or if the third operand is the same as the first operand
3765 of the comparison. */
3767 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3768 && reversible_comparison_p (XEXP (x, 0))
3769 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3770 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3773 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3774 GET_MODE (XEXP (x, 0)),
3775 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3778 SUBST (XEXP (x, 1), XEXP (x, 2));
3779 SUBST (XEXP (x, 2), temp);
3782 /* If the two arms are identical, we don't need the comparison. */
3784 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3785 && ! side_effects_p (XEXP (x, 0)))
3788 /* Look for cases where we have (abs x) or (neg (abs X)). */
3790 if (GET_MODE_CLASS (mode) == MODE_INT
3791 && GET_CODE (XEXP (x, 2)) == NEG
3792 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3793 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3794 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3795 && ! side_effects_p (XEXP (x, 1)))
3796 switch (GET_CODE (XEXP (x, 0)))
3800 x = gen_unary (ABS, mode, XEXP (x, 1));
3804 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3808 /* Look for MIN or MAX. */
3810 if (! FLOAT_MODE_P (mode)
3811 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3812 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3813 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3814 && ! side_effects_p (XEXP (x, 0)))
3815 switch (GET_CODE (XEXP (x, 0)))
3819 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3823 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3827 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3831 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3835 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
3837 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when
3838 its second operand is zero, this can be done as (OP Z (mult COND C2))
3839 where C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer
3840 ZERO_EXTEND or SIGN_EXTEND as long as Z is already extended (so
3841 we don't destroy it). We can do this kind of thing in some
3842 cases when STORE_FLAG_VALUE is neither of the above, but it isn't
3843 worth checking for. */
3845 if (mode != VOIDmode && ! side_effects_p (x))
3847 rtx t = make_compound_operation (XEXP (x, 1), SET);
3848 rtx f = make_compound_operation (XEXP (x, 2), SET);
3849 rtx cond_op0 = XEXP (XEXP (x, 0), 0);
3850 rtx cond_op1 = XEXP (XEXP (x, 0), 1);
3851 enum rtx_code cond_op = GET_CODE (XEXP (x, 0));
3852 enum rtx_code op, extend_op = NIL;
3853 enum machine_mode m = mode;
3856 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
3857 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
3858 || GET_CODE (t) == ASHIFT
3859 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
3860 && rtx_equal_p (XEXP (t, 0), f))
3861 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
3862 else if (GET_CODE (t) == SIGN_EXTEND
3863 && (GET_CODE (XEXP (t, 0)) == PLUS
3864 || GET_CODE (XEXP (t, 0)) == MINUS
3865 || GET_CODE (XEXP (t, 0)) == IOR
3866 || GET_CODE (XEXP (t, 0)) == XOR
3867 || GET_CODE (XEXP (t, 0)) == ASHIFT
3868 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
3869 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
3870 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
3871 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
3872 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
3873 && (num_sign_bit_copies (f, GET_MODE (f))
3874 > (GET_MODE_BITSIZE (mode)
3875 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
3877 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
3878 extend_op = SIGN_EXTEND;
3879 m = GET_MODE (XEXP (t, 0));
3881 else if (GET_CODE (t) == ZERO_EXTEND
3882 && (GET_CODE (XEXP (t, 0)) == PLUS
3883 || GET_CODE (XEXP (t, 0)) == MINUS
3884 || GET_CODE (XEXP (t, 0)) == IOR
3885 || GET_CODE (XEXP (t, 0)) == XOR
3886 || GET_CODE (XEXP (t, 0)) == ASHIFT
3887 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
3888 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
3889 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
3890 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3891 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
3892 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
3893 && ((nonzero_bits (f, GET_MODE (f))
3894 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
3897 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
3898 extend_op = ZERO_EXTEND;
3899 m = GET_MODE (XEXP (t, 0));
3902 if (reversible_comparison_p (XEXP (x, 0))
3903 && (GET_CODE (f) == PLUS || GET_CODE (f) == MINUS
3904 || GET_CODE (f) == IOR || GET_CODE (f) == XOR
3905 || GET_CODE (f) == ASHIFT
3906 || GET_CODE (f) == LSHIFTRT || GET_CODE (f) == ASHIFTRT)
3907 && rtx_equal_p (XEXP (f, 0), t))
3909 c1 = XEXP (f, 1), op = GET_CODE (f), z = t;
3910 cond_op = reverse_condition (cond_op);
3912 else if (GET_CODE (f) == SIGN_EXTEND
3913 && (GET_CODE (XEXP (f, 0)) == PLUS
3914 || GET_CODE (XEXP (f, 0)) == MINUS
3915 || GET_CODE (XEXP (f, 0)) == IOR
3916 || GET_CODE (XEXP (f, 0)) == XOR
3917 || GET_CODE (XEXP (f, 0)) == ASHIFT
3918 || GET_CODE (XEXP (f, 0)) == LSHIFTRT
3919 || GET_CODE (XEXP (f, 0)) == ASHIFTRT)
3920 && GET_CODE (XEXP (XEXP (f, 0), 0)) == SUBREG
3921 && subreg_lowpart_p (XEXP (XEXP (f, 0), 0))
3922 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (f, 0), 0)), f)
3923 && (num_sign_bit_copies (t, GET_MODE (t))
3924 > (GET_MODE_BITSIZE (mode)
3925 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (f, 0), 0))))))
3927 c1 = XEXP (XEXP (f, 0), 1); z = t; op = GET_CODE (XEXP (f, 0));
3928 extend_op = SIGN_EXTEND;
3929 m = GET_MODE (XEXP (f, 0));
3930 cond_op = reverse_condition (cond_op);
3932 else if (GET_CODE (f) == ZERO_EXTEND
3933 && (GET_CODE (XEXP (f, 0)) == PLUS
3934 || GET_CODE (XEXP (f, 0)) == MINUS
3935 || GET_CODE (XEXP (f, 0)) == IOR
3936 || GET_CODE (XEXP (f, 0)) == XOR
3937 || GET_CODE (XEXP (f, 0)) == ASHIFT
3938 || GET_CODE (XEXP (f, 0)) == LSHIFTRT
3939 || GET_CODE (XEXP (f, 0)) == ASHIFTRT)
3940 && GET_CODE (XEXP (XEXP (f, 0), 0)) == SUBREG
3941 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3942 && subreg_lowpart_p (XEXP (XEXP (f, 0), 0))
3943 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (f, 0), 0)), t)
3944 && ((nonzero_bits (t, GET_MODE (t))
3945 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (f, 0), 0))))
3948 c1 = XEXP (XEXP (f, 0), 1); z = t; op = GET_CODE (XEXP (f, 0));
3949 extend_op = ZERO_EXTEND;
3950 m = GET_MODE (XEXP (f, 0));
3951 cond_op = reverse_condition (cond_op);
3956 temp = subst (gen_binary (cond_op, m, cond_op0, cond_op1),
3957 pc_rtx, pc_rtx, 0, 0);
3960 temp = gen_binary (MULT, m, temp,
3961 gen_binary (MULT, m, c1,
3962 GEN_INT (STORE_FLAG_VALUE)));
3964 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
3966 if (extend_op != NIL)
3967 temp = gen_unary (extend_op, mode, temp);
3974 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to
3975 be 0 or 1 and C1 is a single bit or A is known to be 0 or -1 and
3976 C1 is the negation of a single bit, we can convert this operation
3977 to a shift. We can actually do this in more general cases, but it
3978 doesn't seem worth it. */
3980 if (GET_CODE (XEXP (x, 0)) == NE && XEXP (XEXP (x, 0), 1) == const0_rtx
3981 && XEXP (x, 2) == const0_rtx && GET_CODE (XEXP (x, 1)) == CONST_INT
3982 && ((1 == nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
3983 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
3984 || ((num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3985 == GET_MODE_BITSIZE (mode))
3986 && (i = exact_log2 (- INTVAL (XEXP (x, 1)))) >= 0)))
3988 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3989 gen_lowpart_for_combine (mode,
3990 XEXP (XEXP (x, 0), 0)),
3998 /* If we are processing SET_DEST, we are done. */
4002 x = expand_compound_operation (x);
4003 if (GET_CODE (x) != code)
4008 /* (set (pc) (return)) gets written as (return). */
4009 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
4012 /* Convert this into a field assignment operation, if possible. */
4013 x = make_field_assignment (x);
4015 /* If we are setting CC0 or if the source is a COMPARE, look for the
4016 use of the comparison result and try to simplify it unless we already
4017 have used undobuf.other_insn. */
4018 if ((GET_CODE (SET_SRC (x)) == COMPARE
4020 || SET_DEST (x) == cc0_rtx
4023 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
4025 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4026 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4027 && XEXP (*cc_use, 0) == SET_DEST (x))
4029 enum rtx_code old_code = GET_CODE (*cc_use);
4030 enum rtx_code new_code;
4032 int other_changed = 0;
4033 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
4035 if (GET_CODE (SET_SRC (x)) == COMPARE)
4036 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
4038 op0 = SET_SRC (x), op1 = const0_rtx;
4040 /* Simplify our comparison, if possible. */
4041 new_code = simplify_comparison (old_code, &op0, &op1);
4043 #ifdef EXTRA_CC_MODES
4044 /* If this machine has CC modes other than CCmode, check to see
4045 if we need to use a different CC mode here. */
4046 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4047 #endif /* EXTRA_CC_MODES */
4049 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4050 /* If the mode changed, we have to change SET_DEST, the mode
4051 in the compare, and the mode in the place SET_DEST is used.
4052 If SET_DEST is a hard register, just build new versions with
4053 the proper mode. If it is a pseudo, we lose unless it is only
4054 time we set the pseudo, in which case we can safely change
4056 if (compare_mode != GET_MODE (SET_DEST (x)))
4058 int regno = REGNO (SET_DEST (x));
4059 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4061 if (regno < FIRST_PSEUDO_REGISTER
4062 || (reg_n_sets[regno] == 1
4063 && ! REG_USERVAR_P (SET_DEST (x))))
4065 if (regno >= FIRST_PSEUDO_REGISTER)
4066 SUBST (regno_reg_rtx[regno], new_dest);
4068 SUBST (SET_DEST (x), new_dest);
4069 SUBST (XEXP (*cc_use, 0), new_dest);
4075 /* If the code changed, we have to build a new comparison
4076 in undobuf.other_insn. */
4077 if (new_code != old_code)
4079 unsigned HOST_WIDE_INT mask;
4081 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4082 SET_DEST (x), const0_rtx));
4084 /* If the only change we made was to change an EQ into an
4085 NE or vice versa, OP0 has only one bit that might be nonzero,
4086 and OP1 is zero, check if changing the user of the condition
4087 code will produce a valid insn. If it won't, we can keep
4088 the original code in that insn by surrounding our operation
4091 if (((old_code == NE && new_code == EQ)
4092 || (old_code == EQ && new_code == NE))
4093 && ! other_changed && op1 == const0_rtx
4094 && (GET_MODE_BITSIZE (GET_MODE (op0))
4095 <= HOST_BITS_PER_WIDE_INT)
4096 && (exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0)))
4099 rtx pat = PATTERN (other_insn), note = 0;
4101 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4102 && ! check_asm_operands (pat)))
4104 PUT_CODE (*cc_use, old_code);
4107 op0 = gen_binary (XOR, GET_MODE (op0), op0,
4116 undobuf.other_insn = other_insn;
4119 /* If we are now comparing against zero, change our source if
4120 needed. If we do not use cc0, we always have a COMPARE. */
4121 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
4122 SUBST (SET_SRC (x), op0);
4126 /* Otherwise, if we didn't previously have a COMPARE in the
4127 correct mode, we need one. */
4128 if (GET_CODE (SET_SRC (x)) != COMPARE
4129 || GET_MODE (SET_SRC (x)) != compare_mode)
4130 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
4134 /* Otherwise, update the COMPARE if needed. */
4135 SUBST (XEXP (SET_SRC (x), 0), op0);
4136 SUBST (XEXP (SET_SRC (x), 1), op1);
4141 /* Get SET_SRC in a form where we have placed back any
4142 compound expressions. Then do the checks below. */
4143 temp = make_compound_operation (SET_SRC (x), SET);
4144 SUBST (SET_SRC (x), temp);
4147 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
4148 operation, and X being a REG or (subreg (reg)), we may be able to
4149 convert this to (set (subreg:m2 x) (op)).
4151 We can always do this if M1 is narrower than M2 because that
4152 means that we only care about the low bits of the result.
4154 However, on most machines (those with neither BYTE_LOADS_ZERO_EXTEND
4155 nor BYTE_LOADS_SIGN_EXTEND defined), we cannot perform a
4156 narrower operation that requested since the high-order bits will
4157 be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
4158 however, this transformation is safe as long as M1 and M2 have
4159 the same number of words. */
4161 if (GET_CODE (SET_SRC (x)) == SUBREG
4162 && subreg_lowpart_p (SET_SRC (x))
4163 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
4164 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
4166 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
4167 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4168 #ifndef BYTE_LOADS_EXTEND
4169 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
4170 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
4172 && (GET_CODE (SET_DEST (x)) == REG
4173 || (GET_CODE (SET_DEST (x)) == SUBREG
4174 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
4176 SUBST (SET_DEST (x),
4177 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
4179 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
4182 #ifdef BYTE_LOADS_EXTEND
4183 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
4184 M wider than N, this would require a paradoxical subreg.
4185 Replace the subreg with a zero_extend to avoid the reload that
4186 would otherwise be required. */
4188 if (GET_CODE (SET_SRC (x)) == SUBREG
4189 && subreg_lowpart_p (SET_SRC (x))
4190 && SUBREG_WORD (SET_SRC (x)) == 0
4191 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
4192 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
4193 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
4194 SUBST (SET_SRC (x), gen_rtx_combine (LOAD_EXTEND,
4195 GET_MODE (SET_SRC (x)),
4196 XEXP (SET_SRC (x), 0)));
4199 #ifndef HAVE_conditional_move
4201 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
4202 and we are comparing an item known to be 0 or -1 against 0, use a
4203 logical operation instead. Check for one of the arms being an IOR
4204 of the other arm with some value. We compute three terms to be
4205 IOR'ed together. In practice, at most two will be nonzero. Then
4208 if (GET_CODE (SET_DEST (x)) != PC
4209 && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
4210 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
4211 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
4212 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
4213 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
4214 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
4215 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
4216 && ! side_effects_p (SET_SRC (x)))
4218 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
4219 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
4220 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
4221 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
4222 rtx term1 = const0_rtx, term2, term3;
4224 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4225 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4226 else if (GET_CODE (true) == IOR
4227 && rtx_equal_p (XEXP (true, 1), false))
4228 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4229 else if (GET_CODE (false) == IOR
4230 && rtx_equal_p (XEXP (false, 0), true))
4231 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4232 else if (GET_CODE (false) == IOR
4233 && rtx_equal_p (XEXP (false, 1), true))
4234 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4236 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4237 XEXP (XEXP (SET_SRC (x), 0), 0), true);
4238 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4239 gen_unary (NOT, GET_MODE (SET_SRC (x)),
4240 XEXP (XEXP (SET_SRC (x), 0), 0)),
4244 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4245 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4253 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4255 x = simplify_and_const_int (x, mode, XEXP (x, 0),
4256 INTVAL (XEXP (x, 1)));
4258 /* If we have (ior (and (X C1) C2)) and the next restart would be
4259 the last, simplify this by making C1 as small as possible
4261 if (n_restarts >= 3 && GET_CODE (x) == IOR
4262 && GET_CODE (XEXP (x, 0)) == AND
4263 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4264 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4266 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
4267 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
4268 & ~ INTVAL (XEXP (x, 1))));
4269 return gen_binary (IOR, mode, temp, XEXP (x, 1));
4272 if (GET_CODE (x) != AND)
4276 /* Convert (A | B) & A to A. */
4277 if (GET_CODE (XEXP (x, 0)) == IOR
4278 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4279 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4280 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4281 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4284 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4285 insn (and may simplify more). */
4286 else if (GET_CODE (XEXP (x, 0)) == XOR
4287 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4288 && ! side_effects_p (XEXP (x, 1)))
4290 x = gen_binary (AND, mode,
4291 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4295 else if (GET_CODE (XEXP (x, 0)) == XOR
4296 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4297 && ! side_effects_p (XEXP (x, 1)))
4299 x = gen_binary (AND, mode,
4300 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4305 /* Similarly for (~ (A ^ B)) & A. */
4306 else if (GET_CODE (XEXP (x, 0)) == NOT
4307 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4308 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
4309 && ! side_effects_p (XEXP (x, 1)))
4311 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
4315 else if (GET_CODE (XEXP (x, 0)) == NOT
4316 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4317 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
4318 && ! side_effects_p (XEXP (x, 1)))
4320 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
4325 /* If we have (and A B) with A not an object but that is known to
4326 be -1 or 0, this is equivalent to the expression
4327 (if_then_else (ne A (const_int 0)) B (const_int 0))
4328 We make this conversion because it may allow further
4329 simplifications and then allow use of conditional move insns.
4330 If the machine doesn't have condition moves, code in case SET
4331 will convert the IF_THEN_ELSE back to the logical operation.
4332 We build the IF_THEN_ELSE here in case further simplification
4333 is possible (e.g., we can convert it to ABS). */
4335 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
4336 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4337 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
4338 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4339 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4341 rtx op0 = XEXP (x, 0);
4342 rtx op1 = const0_rtx;
4343 enum rtx_code comp_code
4344 = simplify_comparison (NE, &op0, &op1);
4346 x = gen_rtx_combine (IF_THEN_ELSE, mode,
4347 gen_binary (comp_code, VOIDmode, op0, op1),
4348 XEXP (x, 1), const0_rtx);
4352 /* In the following group of tests (and those in case IOR below),
4353 we start with some combination of logical operations and apply
4354 the distributive law followed by the inverse distributive law.
4355 Most of the time, this results in no change. However, if some of
4356 the operands are the same or inverses of each other, simplifications
4359 For example, (and (ior A B) (not B)) can occur as the result of
4360 expanding a bit field assignment. When we apply the distributive
4361 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4362 which then simplifies to (and (A (not B))). */
4364 /* If we have (and (ior A B) C), apply the distributive law and then
4365 the inverse distributive law to see if things simplify. */
4367 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4369 x = apply_distributive_law
4370 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4371 gen_binary (AND, mode,
4372 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4373 gen_binary (AND, mode,
4374 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4375 if (GET_CODE (x) != AND)
4379 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4381 x = apply_distributive_law
4382 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4383 gen_binary (AND, mode,
4384 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4385 gen_binary (AND, mode,
4386 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4387 if (GET_CODE (x) != AND)
4391 /* Similarly, taking advantage of the fact that
4392 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4394 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4396 x = apply_distributive_law
4397 (gen_binary (XOR, mode,
4398 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4399 XEXP (XEXP (x, 1), 0)),
4400 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4401 XEXP (XEXP (x, 1), 1))));
4402 if (GET_CODE (x) != AND)
4406 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4408 x = apply_distributive_law
4409 (gen_binary (XOR, mode,
4410 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4411 XEXP (XEXP (x, 0), 0)),
4412 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4413 XEXP (XEXP (x, 0), 1))));
4414 if (GET_CODE (x) != AND)
4420 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4421 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4422 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4423 && (nonzero_bits (XEXP (x, 0), mode) & ~ INTVAL (XEXP (x, 1))) == 0)
4426 /* Convert (A & B) | A to A. */
4427 if (GET_CODE (XEXP (x, 0)) == AND
4428 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4429 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4430 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4431 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4434 /* If we have (ior (and A B) C), apply the distributive law and then
4435 the inverse distributive law to see if things simplify. */
4437 if (GET_CODE (XEXP (x, 0)) == AND)
4439 x = apply_distributive_law
4440 (gen_binary (AND, mode,
4441 gen_binary (IOR, mode,
4442 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4443 gen_binary (IOR, mode,
4444 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4446 if (GET_CODE (x) != IOR)
4450 if (GET_CODE (XEXP (x, 1)) == AND)
4452 x = apply_distributive_law
4453 (gen_binary (AND, mode,
4454 gen_binary (IOR, mode,
4455 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4456 gen_binary (IOR, mode,
4457 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4459 if (GET_CODE (x) != IOR)
4463 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4464 mode size to (rotate A CX). */
4466 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4467 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4468 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4469 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4470 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4471 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4472 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4473 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4474 == GET_MODE_BITSIZE (mode)))
4478 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4479 shift_count = XEXP (XEXP (x, 0), 1);
4481 shift_count = XEXP (XEXP (x, 1), 1);
4482 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4488 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4489 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4492 int num_negated = 0;
4493 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4495 if (GET_CODE (in1) == NOT)
4496 num_negated++, in1 = XEXP (in1, 0);
4497 if (GET_CODE (in2) == NOT)
4498 num_negated++, in2 = XEXP (in2, 0);
4500 if (num_negated == 2)
4502 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4503 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4505 else if (num_negated == 1)
4507 x = gen_unary (NOT, mode,
4508 gen_binary (XOR, mode, in1, in2));
4513 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4514 correspond to a machine insn or result in further simplifications
4515 if B is a constant. */
4517 if (GET_CODE (XEXP (x, 0)) == AND
4518 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4519 && ! side_effects_p (XEXP (x, 1)))
4521 x = gen_binary (AND, mode,
4522 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4526 else if (GET_CODE (XEXP (x, 0)) == AND
4527 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4528 && ! side_effects_p (XEXP (x, 1)))
4530 x = gen_binary (AND, mode,
4531 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4537 #if STORE_FLAG_VALUE == 1
4538 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4540 if (XEXP (x, 1) == const1_rtx
4541 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4542 && reversible_comparison_p (XEXP (x, 0)))
4543 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4544 mode, XEXP (XEXP (x, 0), 0),
4545 XEXP (XEXP (x, 0), 1));
4547 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4548 is (lt foo (const_int 0)), so we can perform the above
4551 if (XEXP (x, 1) == const1_rtx
4552 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4553 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4554 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
4555 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
4558 /* (xor (comparison foo bar) (const_int sign-bit))
4559 when STORE_FLAG_VALUE is the sign bit. */
4560 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4561 && (STORE_FLAG_VALUE
4562 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4563 && XEXP (x, 1) == const_true_rtx
4564 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4565 && reversible_comparison_p (XEXP (x, 0)))
4566 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4567 mode, XEXP (XEXP (x, 0), 0),
4568 XEXP (XEXP (x, 0), 1));
4572 /* (abs (neg <foo>)) -> (abs <foo>) */
4573 if (GET_CODE (XEXP (x, 0)) == NEG)
4574 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4576 /* If operand is something known to be positive, ignore the ABS. */
4577 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4578 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4579 <= HOST_BITS_PER_WIDE_INT)
4580 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4581 & ((HOST_WIDE_INT) 1
4582 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4587 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4588 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4590 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4596 /* (ffs (*_extend <X>)) = (ffs <X>) */
4597 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4598 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4599 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4603 /* (float (sign_extend <X>)) = (float <X>). */
4604 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4605 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4614 /* If this is a shift by a constant amount, simplify it. */
4615 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4617 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4618 INTVAL (XEXP (x, 1)));
4619 if (GET_CODE (x) != code)
4623 #ifdef SHIFT_COUNT_TRUNCATED
4624 else if (GET_CODE (XEXP (x, 1)) != REG)
4626 force_to_mode (XEXP (x, 1), GET_MODE (x),
4627 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
4637 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4638 operations" because they can be replaced with two more basic operations.
4639 ZERO_EXTEND is also considered "compound" because it can be replaced with
4640 an AND operation, which is simpler, though only one operation.
4642 The function expand_compound_operation is called with an rtx expression
4643 and will convert it to the appropriate shifts and AND operations,
4644 simplifying at each stage.
4646 The function make_compound_operation is called to convert an expression
4647 consisting of shifts and ANDs into the equivalent compound expression.
4648 It is the inverse of this function, loosely speaking. */
4651 expand_compound_operation (x)
4659 switch (GET_CODE (x))
4664 /* We can't necessarily use a const_int for a multiword mode;
4665 it depends on implicitly extending the value.
4666 Since we don't know the right way to extend it,
4667 we can't tell whether the implicit way is right.
4669 Even for a mode that is no wider than a const_int,
4670 we can't win, because we need to sign extend one of its bits through
4671 the rest of it, and we don't know which bit. */
4672 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4675 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4678 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4679 /* If the inner object has VOIDmode (the only way this can happen
4680 is if it is a ASM_OPERANDS), we can't do anything since we don't
4681 know how much masking to do. */
4690 /* If the operand is a CLOBBER, just return it. */
4691 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4694 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4695 || GET_CODE (XEXP (x, 2)) != CONST_INT
4696 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4699 len = INTVAL (XEXP (x, 1));
4700 pos = INTVAL (XEXP (x, 2));
4702 /* If this goes outside the object being extracted, replace the object
4703 with a (use (mem ...)) construct that only combine understands
4704 and is used only for this purpose. */
4705 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4706 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4709 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4717 /* If we reach here, we want to return a pair of shifts. The inner
4718 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4719 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4720 logical depending on the value of UNSIGNEDP.
4722 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4723 converted into an AND of a shift.
4725 We must check for the case where the left shift would have a negative
4726 count. This can happen in a case like (x >> 31) & 255 on machines
4727 that can't shift by a constant. On those machines, we would first
4728 combine the shift with the AND to produce a variable-position
4729 extraction. Then the constant of 31 would be substituted in to produce
4730 a such a position. */
4732 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4733 if (modewidth >= pos - len)
4734 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4736 simplify_shift_const (NULL_RTX, ASHIFT,
4739 modewidth - pos - len),
4742 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4743 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4744 simplify_shift_const (NULL_RTX, LSHIFTRT,
4747 ((HOST_WIDE_INT) 1 << len) - 1);
4749 /* Any other cases we can't handle. */
4753 /* If we couldn't do this for some reason, return the original
4755 if (GET_CODE (tem) == CLOBBER)
4761 /* X is a SET which contains an assignment of one object into
4762 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4763 or certain SUBREGS). If possible, convert it into a series of
4766 We half-heartedly support variable positions, but do not at all
4767 support variable lengths. */
4770 expand_field_assignment (x)
4774 rtx pos; /* Always counts from low bit. */
4777 enum machine_mode compute_mode;
4779 /* Loop until we find something we can't simplify. */
4782 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4783 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4785 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4786 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4789 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4790 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4792 inner = XEXP (SET_DEST (x), 0);
4793 len = INTVAL (XEXP (SET_DEST (x), 1));
4794 pos = XEXP (SET_DEST (x), 2);
4796 /* If the position is constant and spans the width of INNER,
4797 surround INNER with a USE to indicate this. */
4798 if (GET_CODE (pos) == CONST_INT
4799 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4800 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4803 if (GET_CODE (pos) == CONST_INT)
4804 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4806 else if (GET_CODE (pos) == MINUS
4807 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4808 && (INTVAL (XEXP (pos, 1))
4809 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4810 /* If position is ADJUST - X, new position is X. */
4811 pos = XEXP (pos, 0);
4813 pos = gen_binary (MINUS, GET_MODE (pos),
4814 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4820 /* A SUBREG between two modes that occupy the same numbers of words
4821 can be done by moving the SUBREG to the source. */
4822 else if (GET_CODE (SET_DEST (x)) == SUBREG
4823 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4824 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4825 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4826 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4828 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4829 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4836 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4837 inner = SUBREG_REG (inner);
4839 compute_mode = GET_MODE (inner);
4841 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4842 if (len < HOST_BITS_PER_WIDE_INT)
4843 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4847 /* Now compute the equivalent expression. Make a copy of INNER
4848 for the SET_DEST in case it is a MEM into which we will substitute;
4849 we don't want shared RTL in that case. */
4850 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4851 gen_binary (IOR, compute_mode,
4852 gen_binary (AND, compute_mode,
4853 gen_unary (NOT, compute_mode,
4858 gen_binary (ASHIFT, compute_mode,
4859 gen_binary (AND, compute_mode,
4860 gen_lowpart_for_combine
4870 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
4871 it is an RTX that represents a variable starting position; otherwise,
4872 POS is the (constant) starting bit position (counted from the LSB).
4874 INNER may be a USE. This will occur when we started with a bitfield
4875 that went outside the boundary of the object in memory, which is
4876 allowed on most machines. To isolate this case, we produce a USE
4877 whose mode is wide enough and surround the MEM with it. The only
4878 code that understands the USE is this routine. If it is not removed,
4879 it will cause the resulting insn not to match.
4881 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4884 IN_DEST is non-zero if this is a reference in the destination of a
4885 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4886 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4889 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4890 ZERO_EXTRACT should be built even for bits starting at bit 0.
4892 MODE is the desired mode of the result (if IN_DEST == 0). */
4895 make_extraction (mode, inner, pos, pos_rtx, len,
4896 unsignedp, in_dest, in_compare)
4897 enum machine_mode mode;
4903 int in_dest, in_compare;
4905 /* This mode describes the size of the storage area
4906 to fetch the overall value from. Within that, we
4907 ignore the POS lowest bits, etc. */
4908 enum machine_mode is_mode = GET_MODE (inner);
4909 enum machine_mode inner_mode;
4910 enum machine_mode wanted_mem_mode = byte_mode;
4911 enum machine_mode pos_mode = word_mode;
4912 enum machine_mode extraction_mode = word_mode;
4913 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4916 rtx orig_pos_rtx = pos_rtx;
4918 /* Get some information about INNER and get the innermost object. */
4919 if (GET_CODE (inner) == USE)
4920 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4921 /* We don't need to adjust the position because we set up the USE
4922 to pretend that it was a full-word object. */
4923 spans_byte = 1, inner = XEXP (inner, 0);
4924 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4926 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
4927 consider just the QI as the memory to extract from.
4928 The subreg adds or removes high bits; its mode is
4929 irrelevant to the meaning of this extraction,
4930 since POS and LEN count from the lsb. */
4931 if (GET_CODE (SUBREG_REG (inner)) == MEM)
4932 is_mode = GET_MODE (SUBREG_REG (inner));
4933 inner = SUBREG_REG (inner);
4936 inner_mode = GET_MODE (inner);
4938 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4939 pos = INTVAL (pos_rtx), pos_rtx = 0;
4941 /* See if this can be done without an extraction. We never can if the
4942 width of the field is not the same as that of some integer mode. For
4943 registers, we can only avoid the extraction if the position is at the
4944 low-order bit and this is either not in the destination or we have the
4945 appropriate STRICT_LOW_PART operation available.
4947 For MEM, we can avoid an extract if the field starts on an appropriate
4948 boundary and we can change the mode of the memory reference. However,
4949 we cannot directly access the MEM if we have a USE and the underlying
4950 MEM is not TMODE. This combination means that MEM was being used in a
4951 context where bits outside its mode were being referenced; that is only
4952 valid in bit-field insns. */
4954 if (tmode != BLKmode
4955 && ! (spans_byte && inner_mode != tmode)
4956 && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM
4958 || (GET_CODE (inner) == REG
4959 && (movstrict_optab->handlers[(int) tmode].insn_code
4960 != CODE_FOR_nothing))))
4961 || (GET_CODE (inner) == MEM && pos_rtx == 0
4963 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4964 : BITS_PER_UNIT)) == 0
4965 /* We can't do this if we are widening INNER_MODE (it
4966 may not be aligned, for one thing). */
4967 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4968 && (inner_mode == tmode
4969 || (! mode_dependent_address_p (XEXP (inner, 0))
4970 && ! MEM_VOLATILE_P (inner))))))
4972 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4973 field. If the original and current mode are the same, we need not
4974 adjust the offset. Otherwise, we do if bytes big endian.
4976 If INNER is not a MEM, get a piece consisting of the just the field
4977 of interest (in this case POS must be 0). */
4979 if (GET_CODE (inner) == MEM)
4982 /* POS counts from lsb, but make OFFSET count in memory order. */
4983 if (BYTES_BIG_ENDIAN)
4984 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
4986 offset = pos / BITS_PER_UNIT;
4988 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4989 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4990 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4991 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4993 else if (GET_CODE (inner) == REG)
4994 /* We can't call gen_lowpart_for_combine here since we always want
4995 a SUBREG and it would sometimes return a new hard register. */
4996 new = gen_rtx (SUBREG, tmode, inner,
4998 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
4999 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
5003 new = force_to_mode (inner, tmode, len, NULL_RTX);
5005 /* If this extraction is going into the destination of a SET,
5006 make a STRICT_LOW_PART unless we made a MEM. */
5009 return (GET_CODE (new) == MEM ? new
5010 : (GET_CODE (new) != SUBREG
5011 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5012 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5014 /* Otherwise, sign- or zero-extend unless we already are in the
5017 return (mode == tmode ? new
5018 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5022 /* Unless this is a COMPARE or we have a funny memory reference,
5023 don't do anything with zero-extending field extracts starting at
5024 the low-order bit since they are simple AND operations. */
5025 if (pos_rtx == 0 && pos == 0 && ! in_dest
5026 && ! in_compare && ! spans_byte && unsignedp)
5029 /* Get the mode to use should INNER be a MEM, the mode for the position,
5030 and the mode for the result. */
5034 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5035 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5036 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5041 if (! in_dest && unsignedp)
5043 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5044 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5045 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5050 if (! in_dest && ! unsignedp)
5052 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5053 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5054 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5058 /* Never narrow an object, since that might not be safe. */
5060 if (mode != VOIDmode
5061 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5062 extraction_mode = mode;
5064 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5065 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5066 pos_mode = GET_MODE (pos_rtx);
5068 /* If this is not from memory or we have to change the mode of memory and
5069 cannot, the desired mode is EXTRACTION_MODE. */
5070 if (GET_CODE (inner) != MEM
5071 || (inner_mode != wanted_mem_mode
5072 && (mode_dependent_address_p (XEXP (inner, 0))
5073 || MEM_VOLATILE_P (inner))))
5074 wanted_mem_mode = extraction_mode;
5077 /* If position is constant, compute new position. Otherwise, build
5080 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
5084 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5085 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
5086 GET_MODE_BITSIZE (wanted_mem_mode))
5091 /* If INNER has a wider mode, make it smaller. If this is a constant
5092 extract, try to adjust the byte to point to the byte containing
5094 if (wanted_mem_mode != VOIDmode
5095 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
5096 && ((GET_CODE (inner) == MEM
5097 && (inner_mode == wanted_mem_mode
5098 || (! mode_dependent_address_p (XEXP (inner, 0))
5099 && ! MEM_VOLATILE_P (inner))))))
5103 /* The computations below will be correct if the machine is big
5104 endian in both bits and bytes or little endian in bits and bytes.
5105 If it is mixed, we must adjust. */
5107 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5108 adjust OFFSET to compensate. */
5109 #if BYTES_BIG_ENDIAN
5111 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5112 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5115 /* If this is a constant position, we can move to the desired byte. */
5118 offset += pos / BITS_PER_UNIT;
5119 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
5122 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5123 if (! spans_byte && is_mode != wanted_mem_mode)
5124 offset = (GET_MODE_SIZE (is_mode)
5125 - GET_MODE_SIZE (wanted_mem_mode) - offset);
5128 if (offset != 0 || inner_mode != wanted_mem_mode)
5130 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
5131 plus_constant (XEXP (inner, 0), offset));
5132 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5133 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5134 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5139 /* If INNER is not memory, we can always get it into the proper mode. */
5140 else if (GET_CODE (inner) != MEM)
5141 inner = force_to_mode (inner, extraction_mode,
5142 (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
5146 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5147 have to zero extend. Otherwise, we can just use a SUBREG. */
5149 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5150 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5151 else if (pos_rtx != 0
5152 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5153 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5155 /* Make POS_RTX unless we already have it and it is correct. If we don't
5156 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5158 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5159 pos_rtx = orig_pos_rtx;
5161 else if (pos_rtx == 0)
5162 pos_rtx = GEN_INT (pos);
5164 /* Make the required operation. See if we can use existing rtx. */
5165 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5166 extraction_mode, inner, GEN_INT (len), pos_rtx);
5168 new = gen_lowpart_for_combine (mode, new);
5173 /* Look at the expression rooted at X. Look for expressions
5174 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5175 Form these expressions.
5177 Return the new rtx, usually just X.
5179 Also, for machines like the Vax that don't have logical shift insns,
5180 try to convert logical to arithmetic shift operations in cases where
5181 they are equivalent. This undoes the canonicalizations to logical
5182 shifts done elsewhere.
5184 We try, as much as possible, to re-use rtl expressions to save memory.
5186 IN_CODE says what kind of expression we are processing. Normally, it is
5187 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5188 being kludges), it is MEM. When processing the arguments of a comparison
5189 or a COMPARE against zero, it is COMPARE. */
5192 make_compound_operation (x, in_code)
5194 enum rtx_code in_code;
5196 enum rtx_code code = GET_CODE (x);
5197 enum machine_mode mode = GET_MODE (x);
5198 int mode_width = GET_MODE_BITSIZE (mode);
5199 enum rtx_code next_code;
5205 /* Select the code to be used in recursive calls. Once we are inside an
5206 address, we stay there. If we have a comparison, set to COMPARE,
5207 but once inside, go back to our default of SET. */
5209 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5210 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5211 && XEXP (x, 1) == const0_rtx) ? COMPARE
5212 : in_code == COMPARE ? SET : in_code);
5214 /* Process depending on the code of this operation. If NEW is set
5215 non-zero, it will be returned. */
5221 /* Convert shifts by constants into multiplications if inside
5223 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5224 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5225 && INTVAL (XEXP (x, 1)) >= 0)
5227 new = make_compound_operation (XEXP (x, 0), next_code);
5228 new = gen_rtx_combine (MULT, mode, new,
5229 GEN_INT ((HOST_WIDE_INT) 1
5230 << INTVAL (XEXP (x, 1))));
5235 /* If the second operand is not a constant, we can't do anything
5237 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5240 /* If the constant is a power of two minus one and the first operand
5241 is a logical right shift, make an extraction. */
5242 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5243 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5245 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5246 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5247 0, in_code == COMPARE);
5250 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5251 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5252 && subreg_lowpart_p (XEXP (x, 0))
5253 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5254 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5256 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5258 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5259 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5260 0, in_code == COMPARE);
5263 /* If we are have (and (rotate X C) M) and C is larger than the number
5264 of bits in M, this is an extraction. */
5266 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5267 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5268 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5269 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5271 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5272 new = make_extraction (mode, new,
5273 (GET_MODE_BITSIZE (mode)
5274 - INTVAL (XEXP (XEXP (x, 0), 1))),
5275 NULL_RTX, i, 1, 0, in_code == COMPARE);
5278 /* On machines without logical shifts, if the operand of the AND is
5279 a logical shift and our mask turns off all the propagated sign
5280 bits, we can replace the logical shift with an arithmetic shift. */
5281 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5282 && (lshr_optab->handlers[(int) mode].insn_code
5283 == CODE_FOR_nothing)
5284 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5285 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5286 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5287 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5288 && mode_width <= HOST_BITS_PER_WIDE_INT)
5290 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5292 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5293 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5295 gen_rtx_combine (ASHIFTRT, mode,
5296 make_compound_operation (XEXP (XEXP (x, 0), 0),
5298 XEXP (XEXP (x, 0), 1)));
5301 /* If the constant is one less than a power of two, this might be
5302 representable by an extraction even if no shift is present.
5303 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5304 we are in a COMPARE. */
5305 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5306 new = make_extraction (mode,
5307 make_compound_operation (XEXP (x, 0),
5309 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5311 /* If we are in a comparison and this is an AND with a power of two,
5312 convert this into the appropriate bit extract. */
5313 else if (in_code == COMPARE
5314 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5315 new = make_extraction (mode,
5316 make_compound_operation (XEXP (x, 0),
5318 i, NULL_RTX, 1, 1, 0, 1);
5323 /* If the sign bit is known to be zero, replace this with an
5324 arithmetic shift. */
5325 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5326 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5327 && mode_width <= HOST_BITS_PER_WIDE_INT
5328 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5330 new = gen_rtx_combine (ASHIFTRT, mode,
5331 make_compound_operation (XEXP (x, 0),
5337 /* ... fall through ... */
5340 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5341 this is a SIGN_EXTRACT. */
5342 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5343 && GET_CODE (XEXP (x, 0)) == ASHIFT
5344 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5345 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
5347 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5348 new = make_extraction (mode, new,
5349 (INTVAL (XEXP (x, 1))
5350 - INTVAL (XEXP (XEXP (x, 0), 1))),
5351 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5352 code == LSHIFTRT, 0, in_code == COMPARE);
5355 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
5356 cases, we are better off returning a SIGN_EXTEND of the operation. */
5358 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5359 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
5360 || GET_CODE (XEXP (x, 0)) == XOR
5361 || GET_CODE (XEXP (x, 0)) == PLUS)
5362 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5363 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5364 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
5365 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5366 && 0 == (INTVAL (XEXP (XEXP (x, 0), 1))
5367 & (((HOST_WIDE_INT) 1
5368 << (MIN (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)),
5369 INTVAL (XEXP (x, 1)))
5372 rtx c1 = XEXP (XEXP (XEXP (x, 0), 0), 1);
5373 rtx c2 = XEXP (x, 1);
5374 rtx c3 = XEXP (XEXP (x, 0), 1);
5375 HOST_WIDE_INT newop1;
5376 rtx inner = XEXP (XEXP (XEXP (x, 0), 0), 0);
5378 /* If C1 > C2, INNER needs to have the shift performed on it
5380 if (INTVAL (c1) > INTVAL (c2))
5382 inner = gen_binary (ASHIFT, mode, inner,
5383 GEN_INT (INTVAL (c1) - INTVAL (c2)));
5387 newop1 = INTVAL (c3) >> INTVAL (c1);
5388 new = make_compound_operation (inner,
5389 GET_CODE (XEXP (x, 0)) == PLUS
5390 ? MEM : GET_CODE (XEXP (x, 0)));
5391 new = make_extraction (mode,
5392 gen_binary (GET_CODE (XEXP (x, 0)), mode, new,
5394 INTVAL (c2) - INTVAL (c1),
5395 NULL_RTX, mode_width - INTVAL (c2),
5396 code == LSHIFTRT, 0, in_code == COMPARE);
5399 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5400 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5401 && GET_CODE (XEXP (x, 0)) == NEG
5402 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5403 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5404 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5406 new = make_compound_operation (XEXP (XEXP (XEXP (x, 0), 0), 0),
5408 new = make_extraction (mode,
5409 gen_unary (GET_CODE (XEXP (x, 0)), mode, new),
5410 (INTVAL (XEXP (x, 1))
5411 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5412 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5413 code == LSHIFTRT, 0, in_code == COMPARE);
5418 /* Call ourselves recursively on the inner expression. If we are
5419 narrowing the object and it has a different RTL code from
5420 what it originally did, do this SUBREG as a force_to_mode. */
5422 tem = make_compound_operation (SUBREG_REG (x), in_code);
5423 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5424 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5425 && subreg_lowpart_p (x))
5427 rtx newer = force_to_mode (tem, mode,
5428 GET_MODE_BITSIZE (mode), NULL_RTX);
5430 /* If we have something other than a SUBREG, we might have
5431 done an expansion, so rerun outselves. */
5432 if (GET_CODE (newer) != SUBREG)
5433 newer = make_compound_operation (newer, in_code);
5441 x = gen_lowpart_for_combine (mode, new);
5442 code = GET_CODE (x);
5445 /* Now recursively process each operand of this operation. */
5446 fmt = GET_RTX_FORMAT (code);
5447 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5450 new = make_compound_operation (XEXP (x, i), next_code);
5451 SUBST (XEXP (x, i), new);
5457 /* Given M see if it is a value that would select a field of bits
5458 within an item, but not the entire word. Return -1 if not.
5459 Otherwise, return the starting position of the field, where 0 is the
5462 *PLEN is set to the length of the field. */
5465 get_pos_from_mask (m, plen)
5466 unsigned HOST_WIDE_INT m;
5469 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5470 int pos = exact_log2 (m & - m);
5475 /* Now shift off the low-order zero bits and see if we have a power of
5477 *plen = exact_log2 ((m >> pos) + 1);
5485 /* Rewrite X so that it is an expression in MODE. We only care about the
5486 low-order BITS bits so we can ignore AND operations that just clear
5489 Also, if REG is non-zero and X is a register equal in value to REG,
5490 replace X with REG. */
5493 force_to_mode (x, mode, bits, reg)
5495 enum machine_mode mode;
5499 enum rtx_code code = GET_CODE (x);
5500 enum machine_mode op_mode = mode;
5502 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5503 just get X in the proper mode. */
5505 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5506 || bits > GET_MODE_BITSIZE (mode))
5507 return gen_lowpart_for_combine (mode, x);
5515 x = expand_compound_operation (x);
5516 if (GET_CODE (x) != code)
5517 return force_to_mode (x, mode, bits, reg);
5521 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5522 || rtx_equal_p (reg, get_last_value (x))))
5527 if (bits < HOST_BITS_PER_WIDE_INT)
5528 x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
5532 /* Ignore low-order SUBREGs. */
5533 if (subreg_lowpart_p (x))
5534 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5538 /* If this is an AND with a constant. Otherwise, we fall through to
5539 do the general binary case. */
5541 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5543 HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
5544 int len = exact_log2 (mask + 1);
5545 rtx op = XEXP (x, 0);
5547 /* If this is masking some low-order bits, we may be able to
5548 impose a stricter constraint on what bits of the operand are
5551 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5554 if (bits < HOST_BITS_PER_WIDE_INT)
5555 mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
5557 /* If we have no AND in MODE, use the original mode for the
5560 if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5561 op_mode = GET_MODE (x);
5563 x = simplify_and_const_int (x, op_mode, op, mask);
5565 /* If X is still an AND, see if it is an AND with a mask that
5566 is just some low-order bits. If so, and it is BITS wide (it
5567 can't be wider), we don't need it. */
5569 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5570 && bits < HOST_BITS_PER_WIDE_INT
5571 && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
5577 /* ... fall through ... */
5584 /* For most binary operations, just propagate into the operation and
5585 change the mode if we have an operation of that mode. */
5588 && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5590 && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5591 || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
5592 == CODE_FOR_nothing))
5594 && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5596 && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5597 || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
5598 == CODE_FOR_nothing)))
5599 op_mode = GET_MODE (x);
5601 x = gen_binary (code, op_mode,
5602 gen_lowpart_for_combine (op_mode,
5603 force_to_mode (XEXP (x, 0),
5606 gen_lowpart_for_combine (op_mode,
5607 force_to_mode (XEXP (x, 1),
5614 /* For left shifts, do the same, but just for the first operand.
5615 However, we cannot do anything with shifts where we cannot
5616 guarantee that the counts are smaller than the size of the mode
5617 because such a count will have a different meaning in a
5620 If we can narrow the shift and know the count, we need even fewer
5621 bits of the first operand. */
5623 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
5624 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
5625 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
5626 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
5627 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
5630 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5631 bits -= INTVAL (XEXP (x, 1));
5634 && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5635 || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
5636 == CODE_FOR_nothing)))
5637 op_mode = GET_MODE (x);
5639 x = gen_binary (code, op_mode,
5640 gen_lowpart_for_combine (op_mode,
5641 force_to_mode (XEXP (x, 0),
5648 /* Here we can only do something if the shift count is a constant and
5649 the count plus BITS is no larger than the width of MODE. In that
5650 case, we can do the shift in MODE. */
5652 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5653 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
5655 rtx inner = force_to_mode (XEXP (x, 0), mode,
5656 bits + INTVAL (XEXP (x, 1)), reg);
5658 if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5659 op_mode = GET_MODE (x);
5661 x = gen_binary (LSHIFTRT, op_mode,
5662 gen_lowpart_for_combine (op_mode, inner),
5668 /* If this is a sign-extension operation that just affects bits
5669 we don't care about, remove it. */
5671 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5672 && INTVAL (XEXP (x, 1)) >= 0
5673 && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
5674 && GET_CODE (XEXP (x, 0)) == ASHIFT
5675 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5676 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5677 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
5683 && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5684 || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
5685 == CODE_FOR_nothing)))
5686 op_mode = GET_MODE (x);
5688 /* Handle these similarly to the way we handle most binary operations. */
5689 x = gen_unary (code, op_mode,
5690 gen_lowpart_for_combine (op_mode,
5691 force_to_mode (XEXP (x, 0), mode,
5696 /* We have no way of knowing if the IF_THEN_ELSE can itself be
5697 written in a narrower mode. We play it safe and do not do so. */
5700 gen_lowpart_for_combine (GET_MODE (x),
5701 force_to_mode (XEXP (x, 1), mode,
5704 gen_lowpart_for_combine (GET_MODE (x),
5705 force_to_mode (XEXP (x, 2), mode,
5710 /* Ensure we return a value of the proper mode. */
5711 return gen_lowpart_for_combine (mode, x);
5714 /* Return the value of expression X given the fact that condition COND
5715 is known to be true when applied to REG as its first operand and VAL
5716 as its second. X is known to not be shared and so can be modified in
5719 We only handle the simplest cases, and specifically those cases that
5720 arise with IF_THEN_ELSE expressions. */
5723 known_cond (x, cond, reg, val)
5728 enum rtx_code code = GET_CODE (x);
5733 if (side_effects_p (x))
5736 if (cond == EQ && rtx_equal_p (x, reg))
5739 /* If X is (abs REG) and we know something about REG's relationship
5740 with zero, we may be able to simplify this. */
5742 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
5745 case GE: case GT: case EQ:
5748 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
5751 /* The only other cases we handle are MIN, MAX, and comparisons if the
5752 operands are the same as REG and VAL. */
5754 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
5756 if (rtx_equal_p (XEXP (x, 0), val))
5757 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
5759 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
5761 if (GET_RTX_CLASS (code) == '<')
5762 return (comparison_dominates_p (cond, code) ? const_true_rtx
5763 : (comparison_dominates_p (cond,
5764 reverse_condition (code))
5767 else if (code == SMAX || code == SMIN
5768 || code == UMIN || code == UMAX)
5770 int unsignedp = (code == UMIN || code == UMAX);
5772 if (code == SMAX || code == UMAX)
5773 cond = reverse_condition (cond);
5778 return unsignedp ? x : XEXP (x, 1);
5780 return unsignedp ? x : XEXP (x, 0);
5782 return unsignedp ? XEXP (x, 1) : x;
5784 return unsignedp ? XEXP (x, 0) : x;
5790 fmt = GET_RTX_FORMAT (code);
5791 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5794 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
5795 else if (fmt[i] == 'E')
5796 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5797 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
5804 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5805 Return that assignment if so.
5807 We only handle the most common cases. */
5810 make_field_assignment (x)
5813 rtx dest = SET_DEST (x);
5814 rtx src = SET_SRC (x);
5820 enum machine_mode mode;
5822 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5823 a clear of a one-bit field. We will have changed it to
5824 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5827 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5828 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5829 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
5830 && (rtx_equal_p (dest, XEXP (src, 1))
5831 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5832 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5834 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5836 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5839 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5840 && subreg_lowpart_p (XEXP (src, 0))
5841 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5842 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5843 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5844 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
5845 && (rtx_equal_p (dest, XEXP (src, 1))
5846 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5847 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5849 assign = make_extraction (VOIDmode, dest, 0,
5850 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5852 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5855 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5857 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5858 && XEXP (XEXP (src, 0), 0) == const1_rtx
5859 && (rtx_equal_p (dest, XEXP (src, 1))
5860 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5861 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5863 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5865 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
5868 /* The other case we handle is assignments into a constant-position
5869 field. They look like (ior (and DEST C1) OTHER). If C1 represents
5870 a mask that has all one bits except for a group of zero bits and
5871 OTHER is known to have zeros where C1 has ones, this is such an
5872 assignment. Compute the position and length from C1. Shift OTHER
5873 to the appropriate position, force it to the required mode, and
5874 make the extraction. Check for the AND in both operands. */
5876 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5877 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5878 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5879 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5880 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5881 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5882 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5883 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5884 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5885 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5886 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5888 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5892 pos = get_pos_from_mask (~c1, &len);
5893 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
5894 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
5895 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
5898 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
5900 /* The mode to use for the source is the mode of the assignment, or of
5901 what is inside a possible STRICT_LOW_PART. */
5902 mode = (GET_CODE (assign) == STRICT_LOW_PART
5903 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
5905 /* Shift OTHER right POS places and make it the source, restricting it
5906 to the proper length and mode. */
5908 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
5909 GET_MODE (src), other, pos),
5912 return gen_rtx_combine (SET, VOIDmode, assign, src);
5915 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5919 apply_distributive_law (x)
5922 enum rtx_code code = GET_CODE (x);
5923 rtx lhs, rhs, other;
5925 enum rtx_code inner_code;
5927 /* Distributivity is not true for floating point.
5928 It can change the value. So don't do it.
5929 -- rms and moshier@world.std.com. */
5930 if (FLOAT_MODE_P (GET_MODE (x)))
5933 /* The outer operation can only be one of the following: */
5934 if (code != IOR && code != AND && code != XOR
5935 && code != PLUS && code != MINUS)
5938 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5940 /* If either operand is a primitive we can't do anything, so get out fast. */
5941 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
5942 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
5945 lhs = expand_compound_operation (lhs);
5946 rhs = expand_compound_operation (rhs);
5947 inner_code = GET_CODE (lhs);
5948 if (inner_code != GET_CODE (rhs))
5951 /* See if the inner and outer operations distribute. */
5958 /* These all distribute except over PLUS. */
5959 if (code == PLUS || code == MINUS)
5964 if (code != PLUS && code != MINUS)
5970 /* These are also multiplies, so they distribute over everything. */
5974 /* Non-paradoxical SUBREGs distributes over all operations, provided
5975 the inner modes and word numbers are the same, this is an extraction
5976 of a low-order part, we don't convert an fp operation to int or
5977 vice versa, and we would not be converting a single-word
5978 operation into a multi-word operation. The latter test is not
5979 required, but it prevents generating unneeded multi-word operations.
5980 Some of the previous tests are redundant given the latter test, but
5981 are retained because they are required for correctness.
5983 We produce the result slightly differently in this case. */
5985 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5986 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5987 || ! subreg_lowpart_p (lhs)
5988 || (GET_MODE_CLASS (GET_MODE (lhs))
5989 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
5990 || (GET_MODE_SIZE (GET_MODE (lhs))
5991 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5992 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
5995 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5996 SUBREG_REG (lhs), SUBREG_REG (rhs));
5997 return gen_lowpart_for_combine (GET_MODE (x), tem);
6003 /* Set LHS and RHS to the inner operands (A and B in the example
6004 above) and set OTHER to the common operand (C in the example).
6005 These is only one way to do this unless the inner operation is
6007 if (GET_RTX_CLASS (inner_code) == 'c'
6008 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6009 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6010 else if (GET_RTX_CLASS (inner_code) == 'c'
6011 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6012 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6013 else if (GET_RTX_CLASS (inner_code) == 'c'
6014 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6015 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6016 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6017 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
6021 /* Form the new inner operation, seeing if it simplifies first. */
6022 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
6024 /* There is one exception to the general way of distributing:
6025 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6026 if (code == XOR && inner_code == IOR)
6029 other = gen_unary (NOT, GET_MODE (x), other);
6032 /* We may be able to continuing distributing the result, so call
6033 ourselves recursively on the inner operation before forming the
6034 outer operation, which we return. */
6035 return gen_binary (inner_code, GET_MODE (x),
6036 apply_distributive_law (tem), other);
6039 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6042 Return an equivalent form, if different from X. Otherwise, return X. If
6043 X is zero, we are to always construct the equivalent form. */
6046 simplify_and_const_int (x, mode, varop, constop)
6048 enum machine_mode mode;
6050 unsigned HOST_WIDE_INT constop;
6052 register enum machine_mode tmode;
6054 unsigned HOST_WIDE_INT nonzero;
6056 /* There is a large class of optimizations based on the principle that
6057 some operations produce results where certain bits are known to be zero,
6058 and hence are not significant to the AND. For example, if we have just
6059 done a left shift of one bit, the low-order bit is known to be zero and
6060 hence an AND with a mask of ~1 would not do anything.
6062 At the end of the following loop, we set:
6064 VAROP to be the item to be AND'ed with;
6065 CONSTOP to the constant value to AND it with. */
6069 /* If we ever encounter a mode wider than the host machine's widest
6070 integer size, we can't compute the masks accurately, so give up. */
6071 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
6074 /* Unless one of the cases below does a `continue',
6075 a `break' will be executed to exit the loop. */
6077 switch (GET_CODE (varop))
6080 /* If VAROP is a (clobber (const_int)), return it since we know
6081 we are generating something that won't match. */
6084 #if ! BITS_BIG_ENDIAN
6086 /* VAROP is a (use (mem ..)) that was made from a bit-field
6087 extraction that spanned the boundary of the MEM. If we are
6088 now masking so it is within that boundary, we don't need the
6090 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
6092 varop = XEXP (varop, 0);
6099 if (subreg_lowpart_p (varop)
6100 /* We can ignore the effect this SUBREG if it narrows the mode
6101 or, on machines where byte operations extend, if the
6102 constant masks to zero all the bits the mode doesn't have. */
6103 && ((GET_MODE_SIZE (GET_MODE (varop))
6104 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
6105 #ifdef BYTE_LOADS_EXTEND
6107 & GET_MODE_MASK (GET_MODE (varop))
6108 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
6112 varop = SUBREG_REG (varop);
6121 /* Try to expand these into a series of shifts and then work
6122 with that result. If we can't, for example, if the extract
6123 isn't at a fixed position, give up. */
6124 temp = expand_compound_operation (varop);
6133 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
6135 constop &= INTVAL (XEXP (varop, 1));
6136 varop = XEXP (varop, 0);
6143 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6144 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6145 operation which may be a bitfield extraction. Ensure
6146 that the constant we form is not wider than the mode of
6149 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
6150 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6151 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
6152 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
6153 && GET_CODE (XEXP (varop, 1)) == CONST_INT
6154 && ((INTVAL (XEXP (XEXP (varop, 0), 1))
6155 + floor_log2 (INTVAL (XEXP (varop, 1))))
6156 < GET_MODE_BITSIZE (GET_MODE (varop)))
6157 && (INTVAL (XEXP (varop, 1))
6158 & ~ nonzero_bits (XEXP (varop, 0), GET_MODE (varop)) == 0))
6160 temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
6161 << INTVAL (XEXP (XEXP (varop, 0), 1)));
6162 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
6163 XEXP (XEXP (varop, 0), 0), temp);
6164 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
6165 temp, XEXP (varop, 1));
6169 /* Apply the AND to both branches of the IOR or XOR, then try to
6170 apply the distributive law. This may eliminate operations
6171 if either branch can be simplified because of the AND.
6172 It may also make some cases more complex, but those cases
6173 probably won't match a pattern either with or without this. */
6175 gen_lowpart_for_combine
6176 (mode, apply_distributive_law
6178 (GET_CODE (varop), GET_MODE (varop),
6179 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6180 XEXP (varop, 0), constop),
6181 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6182 XEXP (varop, 1), constop))));
6185 /* (and (not FOO)) is (and (xor FOO CONST)), so if FOO is an
6186 LSHIFTRT, we can do the same as above. Ensure that the constant
6187 we form is not wider than the mode of VAROP. */
6189 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
6190 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6191 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
6192 && (INTVAL (XEXP (XEXP (varop, 0), 1)) + floor_log2 (constop)
6193 < GET_MODE_BITSIZE (GET_MODE (varop)))
6194 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6196 temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
6197 temp = gen_binary (XOR, GET_MODE (varop),
6198 XEXP (XEXP (varop, 0), 0), temp);
6199 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
6200 temp, XEXP (XEXP (varop, 0), 1));
6206 /* If we are just looking for the sign bit, we don't need this
6207 shift at all, even if it has a variable count. */
6208 if (constop == ((HOST_WIDE_INT) 1
6209 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
6211 varop = XEXP (varop, 0);
6215 /* If this is a shift by a constant, get a mask that contains
6216 those bits that are not copies of the sign bit. We then have
6217 two cases: If CONSTOP only includes those bits, this can be
6218 a logical shift, which may allow simplifications. If CONSTOP
6219 is a single-bit field not within those bits, we are requesting
6220 a copy of the sign bit and hence can shift the sign bit to
6221 the appropriate location. */
6222 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6223 && INTVAL (XEXP (varop, 1)) >= 0
6224 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
6228 nonzero = GET_MODE_MASK (GET_MODE (varop));
6229 nonzero >>= INTVAL (XEXP (varop, 1));
6231 if ((constop & ~ nonzero) == 0
6232 || (i = exact_log2 (constop)) >= 0)
6234 varop = simplify_shift_const
6235 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6236 i < 0 ? INTVAL (XEXP (varop, 1))
6237 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
6238 if (GET_CODE (varop) != ASHIFTRT)
6243 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
6244 even if the shift count isn't a constant. */
6246 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
6247 XEXP (varop, 0), XEXP (varop, 1));
6251 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6252 shift and AND produces only copies of the sign bit (C2 is one less
6253 than a power of two), we can do this with just a shift. */
6255 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6256 && ((INTVAL (XEXP (varop, 1))
6257 + num_sign_bit_copies (XEXP (varop, 0),
6258 GET_MODE (XEXP (varop, 0))))
6259 >= GET_MODE_BITSIZE (GET_MODE (varop)))
6260 && exact_log2 (constop + 1) >= 0
6261 && (num_sign_bit_copies (XEXP (varop, 0),
6262 GET_MODE (XEXP (varop, 0)))
6263 >= exact_log2 (constop + 1)))
6265 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6266 GEN_INT (GET_MODE_BITSIZE (GET_MODE (varop))
6267 - exact_log2 (constop + 1)));
6271 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
6272 included in STORE_FLAG_VALUE and FOO has no bits that might be
6273 nonzero not in CONST. */
6274 if ((constop & ~ STORE_FLAG_VALUE) == 0
6275 && XEXP (varop, 0) == const0_rtx
6276 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
6278 varop = XEXP (varop, 0);
6284 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6285 low-order bits (as in an alignment operation) and FOO is already
6286 aligned to that boundary, we can convert remove this AND
6287 and possibly the PLUS if it is now adding zero. */
6288 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6289 && exact_log2 (-constop) >= 0
6290 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
6292 varop = plus_constant (XEXP (varop, 0),
6293 INTVAL (XEXP (varop, 1)) & constop);
6298 /* ... fall through ... */
6301 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
6302 less than powers of two and M2 is narrower than M1, we can
6303 eliminate the inner AND. This occurs when incrementing
6306 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
6307 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
6308 SUBST (XEXP (varop, 0),
6309 expand_compound_operation (XEXP (varop, 0)));
6311 if (GET_CODE (XEXP (varop, 0)) == AND
6312 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6313 && exact_log2 (constop + 1) >= 0
6314 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
6315 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
6316 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
6323 /* If we have reached a constant, this whole thing is constant. */
6324 if (GET_CODE (varop) == CONST_INT)
6325 return GEN_INT (constop & INTVAL (varop));
6327 /* See what bits may be nonzero in VAROP. Unlike the general case of
6328 a call to nonzero_bits, here we don't care about bits outside
6331 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6333 /* Turn off all bits in the constant that are known to already be zero.
6334 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6335 which is tested below. */
6339 /* If we don't have any bits left, return zero. */
6343 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6344 if we already had one (just check for the simplest cases). */
6345 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6346 && GET_MODE (XEXP (x, 0)) == mode
6347 && SUBREG_REG (XEXP (x, 0)) == varop)
6348 varop = XEXP (x, 0);
6350 varop = gen_lowpart_for_combine (mode, varop);
6352 /* If we can't make the SUBREG, try to return what we were given. */
6353 if (GET_CODE (varop) == CLOBBER)
6354 return x ? x : varop;
6356 /* If we are only masking insignificant bits, return VAROP. */
6357 if (constop == nonzero)
6360 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6361 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6362 x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
6366 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6367 || INTVAL (XEXP (x, 1)) != constop)
6368 SUBST (XEXP (x, 1), GEN_INT (constop));
6370 SUBST (XEXP (x, 0), varop);
6376 /* Given an expression, X, compute which bits in X can be non-zero.
6377 We don't care about bits outside of those defined in MODE.
6379 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6380 a shift, AND, or zero_extract, we can do better. */
6382 static unsigned HOST_WIDE_INT
6383 nonzero_bits (x, mode)
6385 enum machine_mode mode;
6387 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6388 unsigned HOST_WIDE_INT inner_nz;
6390 int mode_width = GET_MODE_BITSIZE (mode);
6393 /* If X is wider than MODE, use its mode instead. */
6394 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6396 mode = GET_MODE (x);
6397 nonzero = GET_MODE_MASK (mode);
6398 mode_width = GET_MODE_BITSIZE (mode);
6401 if (mode_width > HOST_BITS_PER_WIDE_INT)
6402 /* Our only callers in this case look for single bit values. So
6403 just return the mode mask. Those tests will then be false. */
6406 code = GET_CODE (x);
6410 #ifdef STACK_BOUNDARY
6411 /* If this is the stack pointer, we may know something about its
6412 alignment. If PUSH_ROUNDING is defined, it is possible for the
6413 stack to be momentarily aligned only to that amount, so we pick
6414 the least alignment. */
6416 if (x == stack_pointer_rtx)
6418 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6420 #ifdef PUSH_ROUNDING
6421 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6424 return nonzero & ~ (sp_alignment - 1);
6428 /* If X is a register whose nonzero bits value is current, use it.
6429 Otherwise, if X is a register whose value we can find, use that
6430 value. Otherwise, use the previously-computed global nonzero bits
6431 for this register. */
6433 if (reg_last_set_value[REGNO (x)] != 0
6434 && reg_last_set_mode[REGNO (x)] == mode
6435 && (reg_n_sets[REGNO (x)] == 1
6436 || reg_last_set_label[REGNO (x)] == label_tick)
6437 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6438 return reg_last_set_nonzero_bits[REGNO (x)];
6440 tem = get_last_value (x);
6444 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6445 /* If X is narrower than MODE and TEM is a non-negative
6446 constant that would appear negative in the mode of X,
6447 sign-extend it for use in reg_nonzero_bits because some
6448 machines (maybe most) will actually do the sign-extension
6449 and this is the conservative approach.
6451 ??? For 2.5, try to tighten up the MD files in this regard
6452 instead of this kludge. */
6454 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
6455 && GET_CODE (tem) == CONST_INT
6457 && 0 != (INTVAL (tem)
6458 & ((HOST_WIDE_INT) 1
6459 << GET_MODE_BITSIZE (GET_MODE (x)))))
6460 tem = GEN_INT (INTVAL (tem)
6461 | ((HOST_WIDE_INT) (-1)
6462 << GET_MODE_BITSIZE (GET_MODE (x))));
6464 return nonzero_bits (tem, mode);
6466 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
6467 return reg_nonzero_bits[REGNO (x)] & nonzero;
6472 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6473 /* If X is negative in MODE, sign-extend the value. */
6476 & ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (GET_MODE (x)))))
6478 | ((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (GET_MODE (x))));
6483 #ifdef BYTE_LOADS_ZERO_EXTEND
6485 /* In many, if not most, RISC machines, reading a byte from memory
6486 zeros the rest of the register. Noticing that fact saves a lot
6487 of extra zero-extends. */
6488 nonzero &= GET_MODE_MASK (GET_MODE (x));
6492 #if STORE_FLAG_VALUE == 1
6499 if (GET_MODE_CLASS (mode) == MODE_INT)
6502 /* A comparison operation only sets the bits given by its mode. The
6503 rest are set undefined. */
6504 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6505 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6510 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6511 == GET_MODE_BITSIZE (GET_MODE (x)))
6514 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6515 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6519 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6520 == GET_MODE_BITSIZE (GET_MODE (x)))
6525 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6529 nonzero &= nonzero_bits (XEXP (x, 0), mode);
6530 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6531 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6535 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6536 Otherwise, show all the bits in the outer mode but not the inner
6538 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6539 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6541 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6544 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6545 inner_nz |= (GET_MODE_MASK (mode)
6546 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6549 nonzero &= inner_nz;
6553 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6554 & nonzero_bits (XEXP (x, 1), mode));
6558 case UMIN: case UMAX: case SMIN: case SMAX:
6559 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6560 | nonzero_bits (XEXP (x, 1), mode));
6563 case PLUS: case MINUS:
6565 case DIV: case UDIV:
6566 case MOD: case UMOD:
6567 /* We can apply the rules of arithmetic to compute the number of
6568 high- and low-order zero bits of these operations. We start by
6569 computing the width (position of the highest-order non-zero bit)
6570 and the number of low-order zero bits for each value. */
6572 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
6573 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
6574 int width0 = floor_log2 (nz0) + 1;
6575 int width1 = floor_log2 (nz1) + 1;
6576 int low0 = floor_log2 (nz0 & -nz0);
6577 int low1 = floor_log2 (nz1 & -nz1);
6578 int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6579 int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6580 int result_width = mode_width;
6586 result_width = MAX (width0, width1) + 1;
6587 result_low = MIN (low0, low1);
6590 result_low = MIN (low0, low1);
6593 result_width = width0 + width1;
6594 result_low = low0 + low1;
6597 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6598 result_width = width0;
6601 result_width = width0;
6604 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6605 result_width = MIN (width0, width1);
6606 result_low = MIN (low0, low1);
6609 result_width = MIN (width0, width1);
6610 result_low = MIN (low0, low1);
6614 if (result_width < mode_width)
6615 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6618 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6623 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6624 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6625 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6629 /* If this is a SUBREG formed for a promoted variable that has
6630 been zero-extended, we know that at least the high-order bits
6631 are zero, though others might be too. */
6633 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6634 nonzero = (GET_MODE_MASK (GET_MODE (x))
6635 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
6637 /* If the inner mode is a single word for both the host and target
6638 machines, we can compute this from which bits of the inner
6639 object might be nonzero. */
6640 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6641 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6642 <= HOST_BITS_PER_WIDE_INT))
6644 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
6645 #ifndef BYTE_LOADS_EXTEND
6646 /* On many CISC machines, accessing an object in a wider mode
6647 causes the high-order bits to become undefined. So they are
6648 not known to be zero. */
6649 if (GET_MODE_SIZE (GET_MODE (x))
6650 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6651 nonzero |= (GET_MODE_MASK (GET_MODE (x))
6652 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6662 /* The nonzero bits are in two classes: any bits within MODE
6663 that aren't in GET_MODE (x) are always significant. The rest of the
6664 nonzero bits are those that are significant in the operand of
6665 the shift when shifted the appropriate number of bits. This
6666 shows that high-order bits are cleared by the right shift and
6667 low-order bits by left shifts. */
6668 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6669 && INTVAL (XEXP (x, 1)) >= 0
6670 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6672 enum machine_mode inner_mode = GET_MODE (x);
6673 int width = GET_MODE_BITSIZE (inner_mode);
6674 int count = INTVAL (XEXP (x, 1));
6675 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6676 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
6677 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
6678 unsigned HOST_WIDE_INT outer = 0;
6680 if (mode_width > width)
6681 outer = (op_nonzero & nonzero & ~ mode_mask);
6683 if (code == LSHIFTRT)
6685 else if (code == ASHIFTRT)
6689 /* If the sign bit may have been nonzero before the shift, we
6690 need to mark all the places it could have been copied to
6691 by the shift as possibly nonzero. */
6692 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6693 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6695 else if (code == LSHIFT || code == ASHIFT)
6698 inner = ((inner << (count % width)
6699 | (inner >> (width - (count % width)))) & mode_mask);
6701 nonzero &= (outer | inner);
6706 /* This is at most the number of bits in the mode. */
6707 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6711 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
6712 | nonzero_bits (XEXP (x, 2), mode));
6719 /* Return the number of bits at the high-order end of X that are known to
6720 be equal to the sign bit. X will be used in mode MODE; if MODE is
6721 VOIDmode, X will be used in its own mode. The returned value will always
6722 be between 1 and the number of bits in MODE. */
6725 num_sign_bit_copies (x, mode)
6727 enum machine_mode mode;
6729 enum rtx_code code = GET_CODE (x);
6731 int num0, num1, result;
6732 unsigned HOST_WIDE_INT nonzero;
6735 /* If we weren't given a mode, use the mode of X. If the mode is still
6736 VOIDmode, we don't know anything. */
6738 if (mode == VOIDmode)
6739 mode = GET_MODE (x);
6741 if (mode == VOIDmode)
6744 bitwidth = GET_MODE_BITSIZE (mode);
6750 if (reg_last_set_value[REGNO (x)] != 0
6751 && reg_last_set_mode[REGNO (x)] == mode
6752 && (reg_n_sets[REGNO (x)] == 1
6753 || reg_last_set_label[REGNO (x)] == label_tick)
6754 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6755 return reg_last_set_sign_bit_copies[REGNO (x)];
6757 tem = get_last_value (x);
6759 return num_sign_bit_copies (tem, mode);
6761 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6762 return reg_sign_bit_copies[REGNO (x)];
6765 #ifdef BYTE_LOADS_SIGN_EXTEND
6767 /* Some RISC machines sign-extend all loads of smaller than a word. */
6768 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6772 /* If the constant is negative, take its 1's complement and remask.
6773 Then see how many zero bits we have. */
6774 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
6775 if (bitwidth <= HOST_BITS_PER_WIDE_INT
6776 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6777 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
6779 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
6782 /* If this is a SUBREG for a promoted object that is sign-extended
6783 and we are looking at it in a wider mode, we know that at least the
6784 high-order bits are known to be sign bit copies. */
6786 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6787 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
6788 num_sign_bit_copies (SUBREG_REG (x), mode));
6790 /* For a smaller object, just ignore the high bits. */
6791 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6793 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6794 return MAX (1, (num0
6795 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6799 #ifdef BYTE_LOADS_EXTEND
6800 /* For paradoxical SUBREGs, just look inside since, on machines with
6801 one of these defined, we assume that operations are actually
6802 performed on the full register. Note that we are passing MODE
6803 to the recursive call, so the number of sign bit copies will
6804 remain relative to that mode, not the inner mode. */
6806 if (GET_MODE_SIZE (GET_MODE (x))
6807 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6808 return num_sign_bit_copies (SUBREG_REG (x), mode);
6814 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6815 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6819 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6820 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6823 /* For a smaller object, just ignore the high bits. */
6824 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6825 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6829 return num_sign_bit_copies (XEXP (x, 0), mode);
6831 case ROTATE: case ROTATERT:
6832 /* If we are rotating left by a number of bits less than the number
6833 of sign bit copies, we can just subtract that amount from the
6835 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6836 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6838 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6839 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6840 : bitwidth - INTVAL (XEXP (x, 1))));
6845 /* In general, this subtracts one sign bit copy. But if the value
6846 is known to be positive, the number of sign bit copies is the
6847 same as that of the input. Finally, if the input has just one bit
6848 that might be nonzero, all the bits are copies of the sign bit. */
6849 nonzero = nonzero_bits (XEXP (x, 0), mode);
6853 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6855 && bitwidth <= HOST_BITS_PER_WIDE_INT
6856 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
6861 case IOR: case AND: case XOR:
6862 case SMIN: case SMAX: case UMIN: case UMAX:
6863 /* Logical operations will preserve the number of sign-bit copies.
6864 MIN and MAX operations always return one of the operands. */
6865 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6866 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6867 return MIN (num0, num1);
6869 case PLUS: case MINUS:
6870 /* For addition and subtraction, we can have a 1-bit carry. However,
6871 if we are subtracting 1 from a positive number, there will not
6872 be such a carry. Furthermore, if the positive number is known to
6873 be 0 or 1, we know the result is either -1 or 0. */
6875 if (code == PLUS && XEXP (x, 1) == constm1_rtx
6876 && bitwidth <= HOST_BITS_PER_WIDE_INT)
6878 nonzero = nonzero_bits (XEXP (x, 0), mode);
6879 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
6880 return (nonzero == 1 || nonzero == 0 ? bitwidth
6881 : bitwidth - floor_log2 (nonzero) - 1);
6884 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6885 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6886 return MAX (1, MIN (num0, num1) - 1);
6889 /* The number of bits of the product is the sum of the number of
6890 bits of both terms. However, unless one of the terms if known
6891 to be positive, we must allow for an additional bit since negating
6892 a negative number can remove one sign bit copy. */
6894 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6895 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6897 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
6899 && bitwidth <= HOST_BITS_PER_WIDE_INT
6900 && ((nonzero_bits (XEXP (x, 0), mode)
6901 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6902 && (nonzero_bits (XEXP (x, 1), mode)
6903 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
6906 return MAX (1, result);
6909 /* The result must be <= the first operand. */
6910 return num_sign_bit_copies (XEXP (x, 0), mode);
6913 /* The result must be <= the scond operand. */
6914 return num_sign_bit_copies (XEXP (x, 1), mode);
6917 /* Similar to unsigned division, except that we have to worry about
6918 the case where the divisor is negative, in which case we have
6920 result = num_sign_bit_copies (XEXP (x, 0), mode);
6922 && bitwidth <= HOST_BITS_PER_WIDE_INT
6923 && (nonzero_bits (XEXP (x, 1), mode)
6924 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6930 result = num_sign_bit_copies (XEXP (x, 1), mode);
6932 && bitwidth <= HOST_BITS_PER_WIDE_INT
6933 && (nonzero_bits (XEXP (x, 1), mode)
6934 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6940 /* Shifts by a constant add to the number of bits equal to the
6942 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6943 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6944 && INTVAL (XEXP (x, 1)) > 0)
6945 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
6951 /* Left shifts destroy copies. */
6952 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6953 || INTVAL (XEXP (x, 1)) < 0
6954 || INTVAL (XEXP (x, 1)) >= bitwidth)
6957 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6958 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
6961 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
6962 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
6963 return MIN (num0, num1);
6965 #if STORE_FLAG_VALUE == -1
6966 case EQ: case NE: case GE: case GT: case LE: case LT:
6967 case GEU: case GTU: case LEU: case LTU:
6972 /* If we haven't been able to figure it out by one of the above rules,
6973 see if some of the high-order bits are known to be zero. If so,
6974 count those bits and return one less than that amount. If we can't
6975 safely compute the mask for this mode, always return BITWIDTH. */
6977 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6980 nonzero = nonzero_bits (x, mode);
6981 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
6982 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
6985 /* Return the number of "extended" bits there are in X, when interpreted
6986 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
6987 unsigned quantities, this is the number of high-order zero bits.
6988 For signed quantities, this is the number of copies of the sign bit
6989 minus 1. In both case, this function returns the number of "spare"
6990 bits. For example, if two quantities for which this function returns
6991 at least 1 are added, the addition is known not to overflow.
6993 This function will always return 0 unless called during combine, which
6994 implies that it must be called from a define_split. */
6997 extended_count (x, mode, unsignedp)
6999 enum machine_mode mode;
7002 if (nonzero_sign_valid == 0)
7006 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7007 && (GET_MODE_BITSIZE (mode) - 1
7008 - floor_log2 (nonzero_bits (x, mode))))
7009 : num_sign_bit_copies (x, mode) - 1);
7012 /* This function is called from `simplify_shift_const' to merge two
7013 outer operations. Specifically, we have already found that we need
7014 to perform operation *POP0 with constant *PCONST0 at the outermost
7015 position. We would now like to also perform OP1 with constant CONST1
7016 (with *POP0 being done last).
7018 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7019 the resulting operation. *PCOMP_P is set to 1 if we would need to
7020 complement the innermost operand, otherwise it is unchanged.
7022 MODE is the mode in which the operation will be done. No bits outside
7023 the width of this mode matter. It is assumed that the width of this mode
7024 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7026 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7027 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7028 result is simply *PCONST0.
7030 If the resulting operation cannot be expressed as one operation, we
7031 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7034 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7035 enum rtx_code *pop0;
7036 HOST_WIDE_INT *pconst0;
7038 HOST_WIDE_INT const1;
7039 enum machine_mode mode;
7042 enum rtx_code op0 = *pop0;
7043 HOST_WIDE_INT const0 = *pconst0;
7045 const0 &= GET_MODE_MASK (mode);
7046 const1 &= GET_MODE_MASK (mode);
7048 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7052 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7055 if (op1 == NIL || op0 == SET)
7058 else if (op0 == NIL)
7059 op0 = op1, const0 = const1;
7061 else if (op0 == op1)
7083 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7084 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7087 /* If the two constants aren't the same, we can't do anything. The
7088 remaining six cases can all be done. */
7089 else if (const0 != const1)
7097 /* (a & b) | b == b */
7099 else /* op1 == XOR */
7100 /* (a ^ b) | b == a | b */
7106 /* (a & b) ^ b == (~a) & b */
7107 op0 = AND, *pcomp_p = 1;
7108 else /* op1 == IOR */
7109 /* (a | b) ^ b == a & ~b */
7110 op0 = AND, *pconst0 = ~ const0;
7115 /* (a | b) & b == b */
7117 else /* op1 == XOR */
7118 /* (a ^ b) & b) == (~a) & b */
7123 /* Check for NO-OP cases. */
7124 const0 &= GET_MODE_MASK (mode);
7126 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7128 else if (const0 == 0 && op0 == AND)
7130 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7139 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7140 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7141 that we started with.
7143 The shift is normally computed in the widest mode we find in VAROP, as
7144 long as it isn't a different number of words than RESULT_MODE. Exceptions
7145 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7148 simplify_shift_const (x, code, result_mode, varop, count)
7151 enum machine_mode result_mode;
7155 enum rtx_code orig_code = code;
7156 int orig_count = count;
7157 enum machine_mode mode = result_mode;
7158 enum machine_mode shift_mode, tmode;
7160 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7161 /* We form (outer_op (code varop count) (outer_const)). */
7162 enum rtx_code outer_op = NIL;
7163 HOST_WIDE_INT outer_const;
7165 int complement_p = 0;
7168 /* If we were given an invalid count, don't do anything except exactly
7169 what was requested. */
7171 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7176 return gen_rtx (code, mode, varop, GEN_INT (count));
7179 /* Unless one of the branches of the `if' in this loop does a `continue',
7180 we will `break' the loop after the `if'. */
7184 /* If we have an operand of (clobber (const_int 0)), just return that
7186 if (GET_CODE (varop) == CLOBBER)
7189 /* If we discovered we had to complement VAROP, leave. Making a NOT
7190 here would cause an infinite loop. */
7194 /* Convert ROTATETRT to ROTATE. */
7195 if (code == ROTATERT)
7196 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7198 /* Canonicalize LSHIFT to ASHIFT. */
7202 /* We need to determine what mode we will do the shift in. If the
7203 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
7204 was originally done in. Otherwise, we can do it in MODE, the widest
7205 mode encountered. */
7206 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7208 /* Handle cases where the count is greater than the size of the mode
7209 minus 1. For ASHIFT, use the size minus one as the count (this can
7210 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7211 take the count modulo the size. For other shifts, the result is
7214 Since these shifts are being produced by the compiler by combining
7215 multiple operations, each of which are defined, we know what the
7216 result is supposed to be. */
7218 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
7220 if (code == ASHIFTRT)
7221 count = GET_MODE_BITSIZE (shift_mode) - 1;
7222 else if (code == ROTATE || code == ROTATERT)
7223 count %= GET_MODE_BITSIZE (shift_mode);
7226 /* We can't simply return zero because there may be an
7234 /* Negative counts are invalid and should not have been made (a
7235 programmer-specified negative count should have been handled
7240 /* If we have replaced VAROP with something wider
7241 (such as, the SUBREG_REG), then this won't work;
7242 num_sign_bit_copies will give the wrong answer in that case. */
7243 if (shift_mode == GET_MODE (varop))
7245 /* An arithmetic right shift of a quantity known to be -1 or 0
7247 if (code == ASHIFTRT
7248 && (num_sign_bit_copies (varop, shift_mode)
7249 == GET_MODE_BITSIZE (shift_mode)))
7255 /* If we are doing an arithmetic right shift and discarding all but
7256 the sign bit copies, this is equivalent to doing a shift by the
7257 bitsize minus one. Convert it into that shift because it will often
7258 allow other simplifications. */
7260 if (code == ASHIFTRT
7261 && (count + num_sign_bit_copies (varop, shift_mode)
7262 >= GET_MODE_BITSIZE (shift_mode)))
7263 count = GET_MODE_BITSIZE (shift_mode) - 1;
7266 /* We simplify the tests below and elsewhere by converting
7267 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7268 `make_compound_operation' will convert it to a ASHIFTRT for
7269 those machines (such as Vax) that don't have a LSHIFTRT. */
7270 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
7272 && ((nonzero_bits (varop, shift_mode)
7273 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
7277 switch (GET_CODE (varop))
7283 new = expand_compound_operation (varop);
7292 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7293 minus the width of a smaller mode, we can do this with a
7294 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7295 if ((code == ASHIFTRT || code == LSHIFTRT)
7296 && ! mode_dependent_address_p (XEXP (varop, 0))
7297 && ! MEM_VOLATILE_P (varop)
7298 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7299 MODE_INT, 1)) != BLKmode)
7301 #if BYTES_BIG_ENDIAN
7302 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
7304 new = gen_rtx (MEM, tmode,
7305 plus_constant (XEXP (varop, 0),
7306 count / BITS_PER_UNIT));
7307 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7308 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7309 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7311 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7312 : ZERO_EXTEND, mode, new);
7319 /* Similar to the case above, except that we can only do this if
7320 the resulting mode is the same as that of the underlying
7321 MEM and adjust the address depending on the *bits* endianness
7322 because of the way that bit-field extract insns are defined. */
7323 if ((code == ASHIFTRT || code == LSHIFTRT)
7324 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7325 MODE_INT, 1)) != BLKmode
7326 && tmode == GET_MODE (XEXP (varop, 0)))
7329 new = XEXP (varop, 0);
7331 new = copy_rtx (XEXP (varop, 0));
7332 SUBST (XEXP (new, 0),
7333 plus_constant (XEXP (new, 0),
7334 count / BITS_PER_UNIT));
7337 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7338 : ZERO_EXTEND, mode, new);
7345 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7346 the same number of words as what we've seen so far. Then store
7347 the widest mode in MODE. */
7348 if (subreg_lowpart_p (varop)
7349 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7350 > GET_MODE_SIZE (GET_MODE (varop)))
7351 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7352 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7355 varop = SUBREG_REG (varop);
7356 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
7357 mode = GET_MODE (varop);
7363 /* Some machines use MULT instead of ASHIFT because MULT
7364 is cheaper. But it is still better on those machines to
7365 merge two shifts into one. */
7366 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7367 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7369 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
7370 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
7376 /* Similar, for when divides are cheaper. */
7377 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7378 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7380 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
7381 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
7387 /* If we are extracting just the sign bit of an arithmetic right
7388 shift, that shift is not needed. */
7389 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
7391 varop = XEXP (varop, 0);
7395 /* ... fall through ... */
7401 /* Here we have two nested shifts. The result is usually the
7402 AND of a new shift with a mask. We compute the result below. */
7403 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7404 && INTVAL (XEXP (varop, 1)) >= 0
7405 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
7406 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7407 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
7409 enum rtx_code first_code = GET_CODE (varop);
7410 int first_count = INTVAL (XEXP (varop, 1));
7411 unsigned HOST_WIDE_INT mask;
7415 if (first_code == LSHIFT)
7416 first_code = ASHIFT;
7418 /* We have one common special case. We can't do any merging if
7419 the inner code is an ASHIFTRT of a smaller mode. However, if
7420 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
7421 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
7422 we can convert it to
7423 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
7424 This simplifies certain SIGN_EXTEND operations. */
7425 if (code == ASHIFT && first_code == ASHIFTRT
7426 && (GET_MODE_BITSIZE (result_mode)
7427 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
7429 /* C3 has the low-order C1 bits zero. */
7431 mask = (GET_MODE_MASK (mode)
7432 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
7434 varop = simplify_and_const_int (NULL_RTX, result_mode,
7435 XEXP (varop, 0), mask);
7436 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
7438 count = first_count;
7443 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
7444 than C1 high-order bits equal to the sign bit, we can convert
7445 this to either an ASHIFT or a ASHIFTRT depending on the
7448 We cannot do this if VAROP's mode is not SHIFT_MODE. */
7450 if (code == ASHIFTRT && first_code == ASHIFT
7451 && GET_MODE (varop) == shift_mode
7452 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
7455 count -= first_count;
7457 count = - count, code = ASHIFT;
7458 varop = XEXP (varop, 0);
7462 /* There are some cases we can't do. If CODE is ASHIFTRT,
7463 we can only do this if FIRST_CODE is also ASHIFTRT.
7465 We can't do the case when CODE is ROTATE and FIRST_CODE is
7468 If the mode of this shift is not the mode of the outer shift,
7469 we can't do this if either shift is ASHIFTRT or ROTATE.
7471 Finally, we can't do any of these if the mode is too wide
7472 unless the codes are the same.
7474 Handle the case where the shift codes are the same
7477 if (code == first_code)
7479 if (GET_MODE (varop) != result_mode
7480 && (code == ASHIFTRT || code == ROTATE))
7483 count += first_count;
7484 varop = XEXP (varop, 0);
7488 if (code == ASHIFTRT
7489 || (code == ROTATE && first_code == ASHIFTRT)
7490 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
7491 || (GET_MODE (varop) != result_mode
7492 && (first_code == ASHIFTRT || first_code == ROTATE
7493 || code == ROTATE)))
7496 /* To compute the mask to apply after the shift, shift the
7497 nonzero bits of the inner shift the same way the
7498 outer shift will. */
7500 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
7503 = simplify_binary_operation (code, result_mode, mask_rtx,
7506 /* Give up if we can't compute an outer operation to use. */
7508 || GET_CODE (mask_rtx) != CONST_INT
7509 || ! merge_outer_ops (&outer_op, &outer_const, AND,
7511 result_mode, &complement_p))
7514 /* If the shifts are in the same direction, we add the
7515 counts. Otherwise, we subtract them. */
7516 if ((code == ASHIFTRT || code == LSHIFTRT)
7517 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
7518 count += first_count;
7520 count -= first_count;
7522 /* If COUNT is positive, the new shift is usually CODE,
7523 except for the two exceptions below, in which case it is
7524 FIRST_CODE. If the count is negative, FIRST_CODE should
7527 && ((first_code == ROTATE && code == ASHIFT)
7528 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7531 code = first_code, count = - count;
7533 varop = XEXP (varop, 0);
7537 /* If we have (A << B << C) for any shift, we can convert this to
7538 (A << C << B). This wins if A is a constant. Only try this if
7539 B is not a constant. */
7541 else if (GET_CODE (varop) == code
7542 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7544 = simplify_binary_operation (code, mode,
7548 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7555 /* Make this fit the case below. */
7556 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7557 GEN_INT (GET_MODE_MASK (mode)));
7563 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7564 with C the size of VAROP - 1 and the shift is logical if
7565 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7566 we have an (le X 0) operation. If we have an arithmetic shift
7567 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7568 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7570 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7571 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7572 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7573 && (code == LSHIFTRT || code == ASHIFTRT)
7574 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7575 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7578 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7581 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7582 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7587 /* If we have (shift (logical)), move the logical to the outside
7588 to allow it to possibly combine with another logical and the
7589 shift to combine with another shift. This also canonicalizes to
7590 what a ZERO_EXTRACT looks like. Also, some machines have
7591 (and (shift)) insns. */
7593 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7594 && (new = simplify_binary_operation (code, result_mode,
7596 GEN_INT (count))) != 0
7597 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7598 INTVAL (new), result_mode, &complement_p))
7600 varop = XEXP (varop, 0);
7604 /* If we can't do that, try to simplify the shift in each arm of the
7605 logical expression, make a new logical expression, and apply
7606 the inverse distributive law. */
7608 rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
7609 XEXP (varop, 0), count);
7610 rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
7611 XEXP (varop, 1), count);
7613 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7614 varop = apply_distributive_law (varop);
7621 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7622 says that the sign bit can be tested, FOO has mode MODE, C is
7623 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7626 && XEXP (varop, 1) == const0_rtx
7627 && GET_MODE (XEXP (varop, 0)) == result_mode
7628 && count == GET_MODE_BITSIZE (result_mode) - 1
7629 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7630 && ((STORE_FLAG_VALUE
7631 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7632 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7633 && merge_outer_ops (&outer_op, &outer_const, XOR,
7634 (HOST_WIDE_INT) 1, result_mode,
7637 varop = XEXP (varop, 0);
7644 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7645 than the number of bits in the mode is equivalent to A. */
7646 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7647 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
7649 varop = XEXP (varop, 0);
7654 /* NEG commutes with ASHIFT since it is multiplication. Move the
7655 NEG outside to allow shifts to combine. */
7657 && merge_outer_ops (&outer_op, &outer_const, NEG,
7658 (HOST_WIDE_INT) 0, result_mode,
7661 varop = XEXP (varop, 0);
7667 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7668 is one less than the number of bits in the mode is
7669 equivalent to (xor A 1). */
7670 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7671 && XEXP (varop, 1) == constm1_rtx
7672 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7673 && merge_outer_ops (&outer_op, &outer_const, XOR,
7674 (HOST_WIDE_INT) 1, result_mode,
7678 varop = XEXP (varop, 0);
7682 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7683 that might be nonzero in BAR are those being shifted out and those
7684 bits are known zero in FOO, we can replace the PLUS with FOO.
7685 Similarly in the other operand order. This code occurs when
7686 we are computing the size of a variable-size array. */
7688 if ((code == ASHIFTRT || code == LSHIFTRT)
7689 && count < HOST_BITS_PER_WIDE_INT
7690 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
7691 && (nonzero_bits (XEXP (varop, 1), result_mode)
7692 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
7694 varop = XEXP (varop, 0);
7697 else if ((code == ASHIFTRT || code == LSHIFTRT)
7698 && count < HOST_BITS_PER_WIDE_INT
7699 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7700 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7702 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7703 & nonzero_bits (XEXP (varop, 1),
7706 varop = XEXP (varop, 1);
7710 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7712 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7713 && (new = simplify_binary_operation (ASHIFT, result_mode,
7715 GEN_INT (count))) != 0
7716 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7717 INTVAL (new), result_mode, &complement_p))
7719 varop = XEXP (varop, 0);
7725 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7726 with C the size of VAROP - 1 and the shift is logical if
7727 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7728 we have a (gt X 0) operation. If the shift is arithmetic with
7729 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7730 we have a (neg (gt X 0)) operation. */
7732 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7733 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7734 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7735 && (code == LSHIFTRT || code == ASHIFTRT)
7736 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7737 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7738 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7741 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7744 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7745 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7755 /* We need to determine what mode to do the shift in. If the shift is
7756 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7757 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7758 The code we care about is that of the shift that will actually be done,
7759 not the shift that was originally requested. */
7760 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7762 /* We have now finished analyzing the shift. The result should be
7763 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7764 OUTER_OP is non-NIL, it is an operation that needs to be applied
7765 to the result of the shift. OUTER_CONST is the relevant constant,
7766 but we must turn off all bits turned off in the shift.
7768 If we were passed a value for X, see if we can use any pieces of
7769 it. If not, make new rtx. */
7771 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7772 && GET_CODE (XEXP (x, 1)) == CONST_INT
7773 && INTVAL (XEXP (x, 1)) == count)
7774 const_rtx = XEXP (x, 1);
7776 const_rtx = GEN_INT (count);
7778 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7779 && GET_MODE (XEXP (x, 0)) == shift_mode
7780 && SUBREG_REG (XEXP (x, 0)) == varop)
7781 varop = XEXP (x, 0);
7782 else if (GET_MODE (varop) != shift_mode)
7783 varop = gen_lowpart_for_combine (shift_mode, varop);
7785 /* If we can't make the SUBREG, try to return what we were given. */
7786 if (GET_CODE (varop) == CLOBBER)
7787 return x ? x : varop;
7789 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7794 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7795 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7797 SUBST (XEXP (x, 0), varop);
7798 SUBST (XEXP (x, 1), const_rtx);
7801 /* If we have an outer operation and we just made a shift, it is
7802 possible that we could have simplified the shift were it not
7803 for the outer operation. So try to do the simplification
7806 if (outer_op != NIL && GET_CODE (x) == code
7807 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7808 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
7809 INTVAL (XEXP (x, 1)));
7811 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7812 turn off all the bits that the shift would have turned off. */
7813 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7814 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7815 GET_MODE_MASK (result_mode) >> orig_count);
7817 /* Do the remainder of the processing in RESULT_MODE. */
7818 x = gen_lowpart_for_combine (result_mode, x);
7820 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7823 x = gen_unary (NOT, result_mode, x);
7825 if (outer_op != NIL)
7827 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7828 outer_const &= GET_MODE_MASK (result_mode);
7830 if (outer_op == AND)
7831 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7832 else if (outer_op == SET)
7833 /* This means that we have determined that the result is
7834 equivalent to a constant. This should be rare. */
7835 x = GEN_INT (outer_const);
7836 else if (GET_RTX_CLASS (outer_op) == '1')
7837 x = gen_unary (outer_op, result_mode, x);
7839 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7845 /* Like recog, but we receive the address of a pointer to a new pattern.
7846 We try to match the rtx that the pointer points to.
7847 If that fails, we may try to modify or replace the pattern,
7848 storing the replacement into the same pointer object.
7850 Modifications include deletion or addition of CLOBBERs.
7852 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7853 the CLOBBERs are placed.
7855 The value is the final insn code from the pattern ultimately matched,
7859 recog_for_combine (pnewpat, insn, pnotes)
7864 register rtx pat = *pnewpat;
7865 int insn_code_number;
7866 int num_clobbers_to_add = 0;
7870 /* Is the result of combination a valid instruction? */
7871 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7873 /* If it isn't, there is the possibility that we previously had an insn
7874 that clobbered some register as a side effect, but the combined
7875 insn doesn't need to do that. So try once more without the clobbers
7876 unless this represents an ASM insn. */
7878 if (insn_code_number < 0 && ! check_asm_operands (pat)
7879 && GET_CODE (pat) == PARALLEL)
7883 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7884 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7887 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7891 SUBST_INT (XVECLEN (pat, 0), pos);
7894 pat = XVECEXP (pat, 0, 0);
7896 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7899 /* If we had any clobbers to add, make a new pattern than contains
7900 them. Then check to make sure that all of them are dead. */
7901 if (num_clobbers_to_add)
7903 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7904 gen_rtvec (GET_CODE (pat) == PARALLEL
7905 ? XVECLEN (pat, 0) + num_clobbers_to_add
7906 : num_clobbers_to_add + 1));
7908 if (GET_CODE (pat) == PARALLEL)
7909 for (i = 0; i < XVECLEN (pat, 0); i++)
7910 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7912 XVECEXP (newpat, 0, 0) = pat;
7914 add_clobbers (newpat, insn_code_number);
7916 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7917 i < XVECLEN (newpat, 0); i++)
7919 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7920 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7922 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7923 XEXP (XVECEXP (newpat, 0, i), 0), notes);
7931 return insn_code_number;
7934 /* Like gen_lowpart but for use by combine. In combine it is not possible
7935 to create any new pseudoregs. However, it is safe to create
7936 invalid memory addresses, because combine will try to recognize
7937 them and all they will do is make the combine attempt fail.
7939 If for some reason this cannot do its job, an rtx
7940 (clobber (const_int 0)) is returned.
7941 An insn containing that will not be recognized. */
7946 gen_lowpart_for_combine (mode, x)
7947 enum machine_mode mode;
7952 if (GET_MODE (x) == mode)
7955 /* We can only support MODE being wider than a word if X is a
7956 constant integer or has a mode the same size. */
7958 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
7959 && ! ((GET_MODE (x) == VOIDmode
7960 && (GET_CODE (x) == CONST_INT
7961 || GET_CODE (x) == CONST_DOUBLE))
7962 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
7963 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7965 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7966 won't know what to do. So we will strip off the SUBREG here and
7967 process normally. */
7968 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7971 if (GET_MODE (x) == mode)
7975 result = gen_lowpart_common (mode, x);
7979 if (GET_CODE (x) == MEM)
7981 register int offset = 0;
7984 /* Refuse to work on a volatile memory ref or one with a mode-dependent
7986 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7987 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7989 /* If we want to refer to something bigger than the original memref,
7990 generate a perverse subreg instead. That will force a reload
7991 of the original memref X. */
7992 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7993 return gen_rtx (SUBREG, mode, x, 0);
7995 #if WORDS_BIG_ENDIAN
7996 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7997 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7999 #if BYTES_BIG_ENDIAN
8000 /* Adjust the address so that the address-after-the-data
8002 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8003 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8005 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8006 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8007 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8008 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8012 /* If X is a comparison operator, rewrite it in a new mode. This
8013 probably won't match, but may allow further simplifications. */
8014 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8015 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8017 /* If we couldn't simplify X any other way, just enclose it in a
8018 SUBREG. Normally, this SUBREG won't match, but some patterns may
8019 include an explicit SUBREG or we may simplify it further in combine. */
8024 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8025 word = ((GET_MODE_SIZE (GET_MODE (x))
8026 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8028 return gen_rtx (SUBREG, mode, x, word);
8032 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8033 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8035 If the identical expression was previously in the insn (in the undobuf),
8036 it will be returned. Only if it is not found will a new expression
8041 gen_rtx_combine (va_alist)
8046 enum machine_mode mode;
8054 code = va_arg (p, enum rtx_code);
8055 mode = va_arg (p, enum machine_mode);
8056 n_args = GET_RTX_LENGTH (code);
8057 fmt = GET_RTX_FORMAT (code);
8059 if (n_args == 0 || n_args > 3)
8062 /* Get each arg and verify that it is supposed to be an expression. */
8063 for (j = 0; j < n_args; j++)
8068 args[j] = va_arg (p, rtx);
8071 /* See if this is in undobuf. Be sure we don't use objects that came
8072 from another insn; this could produce circular rtl structures. */
8074 for (i = previous_num_undos; i < undobuf.num_undo; i++)
8075 if (!undobuf.undo[i].is_int
8076 && GET_CODE (undobuf.undo[i].old_contents.r) == code
8077 && GET_MODE (undobuf.undo[i].old_contents.r) == mode)
8079 for (j = 0; j < n_args; j++)
8080 if (XEXP (undobuf.undo[i].old_contents.r, j) != args[j])
8084 return undobuf.undo[i].old_contents.r;
8087 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8088 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8089 rt = rtx_alloc (code);
8090 PUT_MODE (rt, mode);
8091 XEXP (rt, 0) = args[0];
8094 XEXP (rt, 1) = args[1];
8096 XEXP (rt, 2) = args[2];
8101 /* These routines make binary and unary operations by first seeing if they
8102 fold; if not, a new expression is allocated. */
8105 gen_binary (code, mode, op0, op1)
8107 enum machine_mode mode;
8113 if (GET_RTX_CLASS (code) == 'c'
8114 && (GET_CODE (op0) == CONST_INT
8115 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8116 tem = op0, op0 = op1, op1 = tem;
8118 if (GET_RTX_CLASS (code) == '<')
8120 enum machine_mode op_mode = GET_MODE (op0);
8121 if (op_mode == VOIDmode)
8122 op_mode = GET_MODE (op1);
8123 result = simplify_relational_operation (code, op_mode, op0, op1);
8126 result = simplify_binary_operation (code, mode, op0, op1);
8131 /* Put complex operands first and constants second. */
8132 if (GET_RTX_CLASS (code) == 'c'
8133 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8134 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8135 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8136 || (GET_CODE (op0) == SUBREG
8137 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8138 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8139 return gen_rtx_combine (code, mode, op1, op0);
8141 return gen_rtx_combine (code, mode, op0, op1);
8145 gen_unary (code, mode, op0)
8147 enum machine_mode mode;
8150 rtx result = simplify_unary_operation (code, mode, op0, mode);
8155 return gen_rtx_combine (code, mode, op0);
8158 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8159 comparison code that will be tested.
8161 The result is a possibly different comparison code to use. *POP0 and
8162 *POP1 may be updated.
8164 It is possible that we might detect that a comparison is either always
8165 true or always false. However, we do not perform general constant
8166 folding in combine, so this knowledge isn't useful. Such tautologies
8167 should have been detected earlier. Hence we ignore all such cases. */
8169 static enum rtx_code
8170 simplify_comparison (code, pop0, pop1)
8179 enum machine_mode mode, tmode;
8181 /* Try a few ways of applying the same transformation to both operands. */
8184 /* If both operands are the same constant shift, see if we can ignore the
8185 shift. We can if the shift is a rotate or if the bits shifted out of
8186 this shift are known to be zero for both inputs and if the type of
8187 comparison is compatible with the shift. */
8188 if (GET_CODE (op0) == GET_CODE (op1)
8189 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8190 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
8191 || ((GET_CODE (op0) == LSHIFTRT
8192 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
8193 && (code != GT && code != LT && code != GE && code != LE))
8194 || (GET_CODE (op0) == ASHIFTRT
8195 && (code != GTU && code != LTU
8196 && code != GEU && code != GEU)))
8197 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8198 && INTVAL (XEXP (op0, 1)) >= 0
8199 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8200 && XEXP (op0, 1) == XEXP (op1, 1))
8202 enum machine_mode mode = GET_MODE (op0);
8203 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8204 int shift_count = INTVAL (XEXP (op0, 1));
8206 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
8207 mask &= (mask >> shift_count) << shift_count;
8208 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
8209 mask = (mask & (mask << shift_count)) >> shift_count;
8211 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
8212 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
8213 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
8218 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8219 SUBREGs are of the same mode, and, in both cases, the AND would
8220 be redundant if the comparison was done in the narrower mode,
8221 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8222 and the operand's possibly nonzero bits are 0xffffff01; in that case
8223 if we only care about QImode, we don't need the AND). This case
8224 occurs if the output mode of an scc insn is not SImode and
8225 STORE_FLAG_VALUE == 1 (e.g., the 386). */
8227 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
8228 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8229 && GET_CODE (XEXP (op1, 1)) == CONST_INT
8230 && GET_CODE (XEXP (op0, 0)) == SUBREG
8231 && GET_CODE (XEXP (op1, 0)) == SUBREG
8232 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
8233 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
8234 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
8235 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8236 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8237 <= HOST_BITS_PER_WIDE_INT)
8238 && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)),
8239 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8240 & ~ INTVAL (XEXP (op0, 1))) == 0
8241 && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)),
8242 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8243 & ~ INTVAL (XEXP (op1, 1))) == 0)
8245 op0 = SUBREG_REG (XEXP (op0, 0));
8246 op1 = SUBREG_REG (XEXP (op1, 0));
8248 /* the resulting comparison is always unsigned since we masked off
8249 the original sign bit. */
8250 code = unsigned_condition (code);
8256 /* If the first operand is a constant, swap the operands and adjust the
8257 comparison code appropriately. */
8258 if (CONSTANT_P (op0))
8260 tem = op0, op0 = op1, op1 = tem;
8261 code = swap_condition (code);
8264 /* We now enter a loop during which we will try to simplify the comparison.
8265 For the most part, we only are concerned with comparisons with zero,
8266 but some things may really be comparisons with zero but not start
8267 out looking that way. */
8269 while (GET_CODE (op1) == CONST_INT)
8271 enum machine_mode mode = GET_MODE (op0);
8272 int mode_width = GET_MODE_BITSIZE (mode);
8273 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8274 int equality_comparison_p;
8275 int sign_bit_comparison_p;
8276 int unsigned_comparison_p;
8277 HOST_WIDE_INT const_op;
8279 /* We only want to handle integral modes. This catches VOIDmode,
8280 CCmode, and the floating-point modes. An exception is that we
8281 can handle VOIDmode if OP0 is a COMPARE or a comparison
8284 if (GET_MODE_CLASS (mode) != MODE_INT
8285 && ! (mode == VOIDmode
8286 && (GET_CODE (op0) == COMPARE
8287 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
8290 /* Get the constant we are comparing against and turn off all bits
8291 not on in our mode. */
8292 const_op = INTVAL (op1);
8293 if (mode_width <= HOST_BITS_PER_WIDE_INT)
8296 /* If we are comparing against a constant power of two and the value
8297 being compared can only have that single bit nonzero (e.g., it was
8298 `and'ed with that bit), we can replace this with a comparison
8301 && (code == EQ || code == NE || code == GE || code == GEU
8302 || code == LT || code == LTU)
8303 && mode_width <= HOST_BITS_PER_WIDE_INT
8304 && exact_log2 (const_op) >= 0
8305 && nonzero_bits (op0, mode) == const_op)
8307 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
8308 op1 = const0_rtx, const_op = 0;
8311 /* Similarly, if we are comparing a value known to be either -1 or
8312 0 with -1, change it to the opposite comparison against zero. */
8315 && (code == EQ || code == NE || code == GT || code == LE
8316 || code == GEU || code == LTU)
8317 && num_sign_bit_copies (op0, mode) == mode_width)
8319 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
8320 op1 = const0_rtx, const_op = 0;
8323 /* Do some canonicalizations based on the comparison code. We prefer
8324 comparisons against zero and then prefer equality comparisons.
8325 If we can reduce the size of a constant, we will do that too. */
8330 /* < C is equivalent to <= (C - 1) */
8334 op1 = GEN_INT (const_op);
8336 /* ... fall through to LE case below. */
8342 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
8346 op1 = GEN_INT (const_op);
8350 /* If we are doing a <= 0 comparison on a value known to have
8351 a zero sign bit, we can replace this with == 0. */
8352 else if (const_op == 0
8353 && mode_width <= HOST_BITS_PER_WIDE_INT
8354 && (nonzero_bits (op0, mode)
8355 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8360 /* >= C is equivalent to > (C - 1). */
8364 op1 = GEN_INT (const_op);
8366 /* ... fall through to GT below. */
8372 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
8376 op1 = GEN_INT (const_op);
8380 /* If we are doing a > 0 comparison on a value known to have
8381 a zero sign bit, we can replace this with != 0. */
8382 else if (const_op == 0
8383 && mode_width <= HOST_BITS_PER_WIDE_INT
8384 && (nonzero_bits (op0, mode)
8385 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8390 /* < C is equivalent to <= (C - 1). */
8394 op1 = GEN_INT (const_op);
8396 /* ... fall through ... */
8399 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
8400 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8402 const_op = 0, op1 = const0_rtx;
8410 /* unsigned <= 0 is equivalent to == 0 */
8414 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
8415 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8417 const_op = 0, op1 = const0_rtx;
8423 /* >= C is equivalent to < (C - 1). */
8427 op1 = GEN_INT (const_op);
8429 /* ... fall through ... */
8432 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
8433 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8435 const_op = 0, op1 = const0_rtx;
8442 /* unsigned > 0 is equivalent to != 0 */
8446 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
8447 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8449 const_op = 0, op1 = const0_rtx;
8455 /* Compute some predicates to simplify code below. */
8457 equality_comparison_p = (code == EQ || code == NE);
8458 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
8459 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
8462 /* Now try cases based on the opcode of OP0. If none of the cases
8463 does a "continue", we exit this loop immediately after the
8466 switch (GET_CODE (op0))
8469 /* If we are extracting a single bit from a variable position in
8470 a constant that has only a single bit set and are comparing it
8471 with zero, we can convert this into an equality comparison
8472 between the position and the location of the single bit. We can't
8473 do this if bit endian and we don't have an extzv since we then
8474 can't know what mode to use for the endianness adjustment. */
8476 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
8477 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
8478 && XEXP (op0, 1) == const1_rtx
8479 && equality_comparison_p && const_op == 0
8480 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
8483 i = (GET_MODE_BITSIZE
8484 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
8487 op0 = XEXP (op0, 2);
8491 /* Result is nonzero iff shift count is equal to I. */
8492 code = reverse_condition (code);
8497 /* ... fall through ... */
8500 tem = expand_compound_operation (op0);
8509 /* If testing for equality, we can take the NOT of the constant. */
8510 if (equality_comparison_p
8511 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
8513 op0 = XEXP (op0, 0);
8518 /* If just looking at the sign bit, reverse the sense of the
8520 if (sign_bit_comparison_p)
8522 op0 = XEXP (op0, 0);
8523 code = (code == GE ? LT : GE);
8529 /* If testing for equality, we can take the NEG of the constant. */
8530 if (equality_comparison_p
8531 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
8533 op0 = XEXP (op0, 0);
8538 /* The remaining cases only apply to comparisons with zero. */
8542 /* When X is ABS or is known positive,
8543 (neg X) is < 0 if and only if X != 0. */
8545 if (sign_bit_comparison_p
8546 && (GET_CODE (XEXP (op0, 0)) == ABS
8547 || (mode_width <= HOST_BITS_PER_WIDE_INT
8548 && (nonzero_bits (XEXP (op0, 0), mode)
8549 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8551 op0 = XEXP (op0, 0);
8552 code = (code == LT ? NE : EQ);
8556 /* If we have NEG of something whose two high-order bits are the
8557 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8558 if (num_sign_bit_copies (op0, mode) >= 2)
8560 op0 = XEXP (op0, 0);
8561 code = swap_condition (code);
8567 /* If we are testing equality and our count is a constant, we
8568 can perform the inverse operation on our RHS. */
8569 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8570 && (tem = simplify_binary_operation (ROTATERT, mode,
8571 op1, XEXP (op0, 1))) != 0)
8573 op0 = XEXP (op0, 0);
8578 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8579 a particular bit. Convert it to an AND of a constant of that
8580 bit. This will be converted into a ZERO_EXTRACT. */
8581 if (const_op == 0 && sign_bit_comparison_p
8582 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8583 && mode_width <= HOST_BITS_PER_WIDE_INT)
8585 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8588 - INTVAL (XEXP (op0, 1)))));
8589 code = (code == LT ? NE : EQ);
8593 /* ... fall through ... */
8596 /* ABS is ignorable inside an equality comparison with zero. */
8597 if (const_op == 0 && equality_comparison_p)
8599 op0 = XEXP (op0, 0);
8606 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8607 to (compare FOO CONST) if CONST fits in FOO's mode and we
8608 are either testing inequality or have an unsigned comparison
8609 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8610 if (! unsigned_comparison_p
8611 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8612 <= HOST_BITS_PER_WIDE_INT)
8613 && ((unsigned HOST_WIDE_INT) const_op
8614 < (((HOST_WIDE_INT) 1
8615 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8617 op0 = XEXP (op0, 0);
8623 /* Check for the case where we are comparing A - C1 with C2,
8624 both constants are smaller than 1/2 the maxium positive
8625 value in MODE, and the comparison is equality or unsigned.
8626 In that case, if A is either zero-extended to MODE or has
8627 sufficient sign bits so that the high-order bit in MODE
8628 is a copy of the sign in the inner mode, we can prove that it is
8629 safe to do the operation in the wider mode. This simplifies
8630 many range checks. */
8632 if (mode_width <= HOST_BITS_PER_WIDE_INT
8633 && subreg_lowpart_p (op0)
8634 && GET_CODE (SUBREG_REG (op0)) == PLUS
8635 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8636 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8637 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8638 < GET_MODE_MASK (mode) / 2)
8639 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
8640 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
8641 GET_MODE (SUBREG_REG (op0)))
8642 & ~ GET_MODE_MASK (mode))
8643 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8644 GET_MODE (SUBREG_REG (op0)))
8645 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8646 - GET_MODE_BITSIZE (mode)))))
8648 op0 = SUBREG_REG (op0);
8652 /* If the inner mode is narrower and we are extracting the low part,
8653 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8654 if (subreg_lowpart_p (op0)
8655 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8656 /* Fall through */ ;
8660 /* ... fall through ... */
8663 if ((unsigned_comparison_p || equality_comparison_p)
8664 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8665 <= HOST_BITS_PER_WIDE_INT)
8666 && ((unsigned HOST_WIDE_INT) const_op
8667 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8669 op0 = XEXP (op0, 0);
8675 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
8676 this for equality comparisons due to pathological cases involving
8678 if (equality_comparison_p
8679 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8680 op1, XEXP (op0, 1))))
8682 op0 = XEXP (op0, 0);
8687 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8688 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8689 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8691 op0 = XEXP (XEXP (op0, 0), 0);
8692 code = (code == LT ? EQ : NE);
8698 /* (eq (minus A B) C) -> (eq A (plus B C)) or
8699 (eq B (minus A C)), whichever simplifies. We can only do
8700 this for equality comparisons due to pathological cases involving
8702 if (equality_comparison_p
8703 && 0 != (tem = simplify_binary_operation (PLUS, mode,
8704 XEXP (op0, 1), op1)))
8706 op0 = XEXP (op0, 0);
8711 if (equality_comparison_p
8712 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8713 XEXP (op0, 0), op1)))
8715 op0 = XEXP (op0, 1);
8720 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8721 of bits in X minus 1, is one iff X > 0. */
8722 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8723 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8724 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8725 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8727 op0 = XEXP (op0, 1);
8728 code = (code == GE ? LE : GT);
8734 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8735 if C is zero or B is a constant. */
8736 if (equality_comparison_p
8737 && 0 != (tem = simplify_binary_operation (XOR, mode,
8738 XEXP (op0, 1), op1)))
8740 op0 = XEXP (op0, 0);
8747 case LT: case LTU: case LE: case LEU:
8748 case GT: case GTU: case GE: case GEU:
8749 /* We can't do anything if OP0 is a condition code value, rather
8750 than an actual data value. */
8753 || XEXP (op0, 0) == cc0_rtx
8755 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8758 /* Get the two operands being compared. */
8759 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8760 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8762 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8764 /* Check for the cases where we simply want the result of the
8765 earlier test or the opposite of that result. */
8767 || (code == EQ && reversible_comparison_p (op0))
8768 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8769 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8770 && (STORE_FLAG_VALUE
8771 & (((HOST_WIDE_INT) 1
8772 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8774 || (code == GE && reversible_comparison_p (op0)))))
8776 code = (code == LT || code == NE
8777 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8778 op0 = tem, op1 = tem1;
8784 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8786 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8787 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8788 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8790 op0 = XEXP (op0, 1);
8791 code = (code == GE ? GT : LE);
8797 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8798 will be converted to a ZERO_EXTRACT later. */
8799 if (const_op == 0 && equality_comparison_p
8800 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8801 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8802 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8804 op0 = simplify_and_const_int
8805 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8807 XEXP (XEXP (op0, 0), 1)),
8812 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8813 zero and X is a comparison and C1 and C2 describe only bits set
8814 in STORE_FLAG_VALUE, we can compare with X. */
8815 if (const_op == 0 && equality_comparison_p
8816 && mode_width <= HOST_BITS_PER_WIDE_INT
8817 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8818 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8819 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8820 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8821 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8823 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8824 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8825 if ((~ STORE_FLAG_VALUE & mask) == 0
8826 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8827 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8828 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8830 op0 = XEXP (XEXP (op0, 0), 0);
8835 /* If we are doing an equality comparison of an AND of a bit equal
8836 to the sign bit, replace this with a LT or GE comparison of
8837 the underlying value. */
8838 if (equality_comparison_p
8840 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8841 && mode_width <= HOST_BITS_PER_WIDE_INT
8842 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8843 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8845 op0 = XEXP (op0, 0);
8846 code = (code == EQ ? GE : LT);
8850 /* If this AND operation is really a ZERO_EXTEND from a narrower
8851 mode, the constant fits within that mode, and this is either an
8852 equality or unsigned comparison, try to do this comparison in
8853 the narrower mode. */
8854 if ((equality_comparison_p || unsigned_comparison_p)
8855 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8856 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8857 & GET_MODE_MASK (mode))
8859 && const_op >> i == 0
8860 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8862 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8869 /* If we have (compare (xshift FOO N) (const_int C)) and
8870 the high order N bits of FOO (N+1 if an inequality comparison)
8871 are known to be zero, we can do this by comparing FOO with C
8872 shifted right N bits so long as the low-order N bits of C are
8874 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8875 && INTVAL (XEXP (op0, 1)) >= 0
8876 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
8877 < HOST_BITS_PER_WIDE_INT)
8879 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
8880 && mode_width <= HOST_BITS_PER_WIDE_INT
8881 && (nonzero_bits (XEXP (op0, 0), mode)
8882 & ~ (mask >> (INTVAL (XEXP (op0, 1))
8883 + ! equality_comparison_p))) == 0)
8885 const_op >>= INTVAL (XEXP (op0, 1));
8886 op1 = GEN_INT (const_op);
8887 op0 = XEXP (op0, 0);
8891 /* If we are doing a sign bit comparison, it means we are testing
8892 a particular bit. Convert it to the appropriate AND. */
8893 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8894 && mode_width <= HOST_BITS_PER_WIDE_INT)
8896 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8899 - INTVAL (XEXP (op0, 1)))));
8900 code = (code == LT ? NE : EQ);
8904 /* If this an equality comparison with zero and we are shifting
8905 the low bit to the sign bit, we can convert this to an AND of the
8907 if (const_op == 0 && equality_comparison_p
8908 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8909 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8911 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8918 /* If this is an equality comparison with zero, we can do this
8919 as a logical shift, which might be much simpler. */
8920 if (equality_comparison_p && const_op == 0
8921 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
8923 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
8925 INTVAL (XEXP (op0, 1)));
8929 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8930 do the comparison in a narrower mode. */
8931 if (! unsigned_comparison_p
8932 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8933 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8934 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8935 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
8936 MODE_INT, 1)) != BLKmode
8937 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
8938 || ((unsigned HOST_WIDE_INT) - const_op
8939 <= GET_MODE_MASK (tmode))))
8941 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8945 /* ... fall through ... */
8947 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8948 the low order N bits of FOO are known to be zero, we can do this
8949 by comparing FOO with C shifted left N bits so long as no
8951 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8952 && INTVAL (XEXP (op0, 1)) >= 0
8953 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8954 && mode_width <= HOST_BITS_PER_WIDE_INT
8955 && (nonzero_bits (XEXP (op0, 0), mode)
8956 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
8958 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8961 const_op <<= INTVAL (XEXP (op0, 1));
8962 op1 = GEN_INT (const_op);
8963 op0 = XEXP (op0, 0);
8967 /* If we are using this shift to extract just the sign bit, we
8968 can replace this with an LT or GE comparison. */
8970 && (equality_comparison_p || sign_bit_comparison_p)
8971 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8972 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8974 op0 = XEXP (op0, 0);
8975 code = (code == NE || code == GT ? LT : GE);
8984 /* Now make any compound operations involved in this comparison. Then,
8985 check for an outmost SUBREG on OP0 that isn't doing anything or is
8986 paradoxical. The latter case can only occur when it is known that the
8987 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8988 We can never remove a SUBREG for a non-equality comparison because the
8989 sign bit is in a different place in the underlying object. */
8991 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8992 op1 = make_compound_operation (op1, SET);
8994 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8995 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8996 && (code == NE || code == EQ)
8997 && ((GET_MODE_SIZE (GET_MODE (op0))
8998 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9000 op0 = SUBREG_REG (op0);
9001 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9004 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9005 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9006 && (code == NE || code == EQ)
9007 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9008 <= HOST_BITS_PER_WIDE_INT)
9009 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9010 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9011 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9013 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9014 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9015 op0 = SUBREG_REG (op0), op1 = tem;
9017 /* We now do the opposite procedure: Some machines don't have compare
9018 insns in all modes. If OP0's mode is an integer mode smaller than a
9019 word and we can't do a compare in that mode, see if there is a larger
9020 mode for which we can do the compare. There are a number of cases in
9021 which we can use the wider mode. */
9023 mode = GET_MODE (op0);
9024 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9025 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
9026 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
9027 for (tmode = GET_MODE_WIDER_MODE (mode);
9029 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
9030 tmode = GET_MODE_WIDER_MODE (tmode))
9031 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
9033 /* If the only nonzero bits in OP0 and OP1 are those in the
9034 narrower mode and this is an equality or unsigned comparison,
9035 we can use the wider mode. Similarly for sign-extended
9036 values and equality or signed comparisons. */
9037 if (((code == EQ || code == NE
9038 || code == GEU || code == GTU || code == LEU || code == LTU)
9039 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
9040 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
9041 || ((code == EQ || code == NE
9042 || code == GE || code == GT || code == LE || code == LT)
9043 && (num_sign_bit_copies (op0, tmode)
9044 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
9045 && (num_sign_bit_copies (op1, tmode)
9046 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
9048 op0 = gen_lowpart_for_combine (tmode, op0);
9049 op1 = gen_lowpart_for_combine (tmode, op1);
9053 /* If this is a test for negative, we can make an explicit
9054 test of the sign bit. */
9056 if (op1 == const0_rtx && (code == LT || code == GE)
9057 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9059 op0 = gen_binary (AND, tmode,
9060 gen_lowpart_for_combine (tmode, op0),
9061 GEN_INT ((HOST_WIDE_INT) 1
9062 << (GET_MODE_BITSIZE (mode) - 1)));
9063 code = (code == LT) ? NE : EQ;
9074 /* Return 1 if we know that X, a comparison operation, is not operating
9075 on a floating-point value or is EQ or NE, meaning that we can safely
9079 reversible_comparison_p (x)
9082 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
9083 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
9086 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
9089 case MODE_PARTIAL_INT:
9090 case MODE_COMPLEX_INT:
9094 x = get_last_value (XEXP (x, 0));
9095 return (x && GET_CODE (x) == COMPARE
9096 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
9102 /* Utility function for following routine. Called when X is part of a value
9103 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9104 for each register mentioned. Similar to mention_regs in cse.c */
9107 update_table_tick (x)
9110 register enum rtx_code code = GET_CODE (x);
9111 register char *fmt = GET_RTX_FORMAT (code);
9116 int regno = REGNO (x);
9117 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9118 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9120 for (i = regno; i < endregno; i++)
9121 reg_last_set_table_tick[i] = label_tick;
9126 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9127 /* Note that we can't have an "E" in values stored; see
9128 get_last_value_validate. */
9130 update_table_tick (XEXP (x, i));
9133 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
9134 are saying that the register is clobbered and we no longer know its
9135 value. If INSN is zero, don't update reg_last_set; this is only permitted
9136 with VALUE also zero and is used to invalidate the register. */
9139 record_value_for_reg (reg, insn, value)
9144 int regno = REGNO (reg);
9145 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9146 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
9149 /* If VALUE contains REG and we have a previous value for REG, substitute
9150 the previous value. */
9151 if (value && insn && reg_overlap_mentioned_p (reg, value))
9155 /* Set things up so get_last_value is allowed to see anything set up to
9157 subst_low_cuid = INSN_CUID (insn);
9158 tem = get_last_value (reg);
9161 value = replace_rtx (copy_rtx (value), reg, tem);
9164 /* For each register modified, show we don't know its value, that
9165 its value has been updated, and that we don't know the location of
9166 the death of the register. */
9167 for (i = regno; i < endregno; i ++)
9170 reg_last_set[i] = insn;
9171 reg_last_set_value[i] = 0;
9172 reg_last_death[i] = 0;
9175 /* Mark registers that are being referenced in this value. */
9177 update_table_tick (value);
9179 /* Now update the status of each register being set.
9180 If someone is using this register in this block, set this register
9181 to invalid since we will get confused between the two lives in this
9182 basic block. This makes using this register always invalid. In cse, we
9183 scan the table to invalidate all entries using this register, but this
9184 is too much work for us. */
9186 for (i = regno; i < endregno; i++)
9188 reg_last_set_label[i] = label_tick;
9189 if (value && reg_last_set_table_tick[i] == label_tick)
9190 reg_last_set_invalid[i] = 1;
9192 reg_last_set_invalid[i] = 0;
9195 /* The value being assigned might refer to X (like in "x++;"). In that
9196 case, we must replace it with (clobber (const_int 0)) to prevent
9198 if (value && ! get_last_value_validate (&value,
9199 reg_last_set_label[regno], 0))
9201 value = copy_rtx (value);
9202 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
9206 /* For the main register being modified, update the value, the mode, the
9207 nonzero bits, and the number of sign bit copies. */
9209 reg_last_set_value[regno] = value;
9213 subst_low_cuid = INSN_CUID (insn);
9214 reg_last_set_mode[regno] = GET_MODE (reg);
9215 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
9216 reg_last_set_sign_bit_copies[regno]
9217 = num_sign_bit_copies (value, GET_MODE (reg));
9221 /* Used for communication between the following two routines. */
9222 static rtx record_dead_insn;
9224 /* Called via note_stores from record_dead_and_set_regs to handle one
9225 SET or CLOBBER in an insn. */
9228 record_dead_and_set_regs_1 (dest, setter)
9231 if (GET_CODE (dest) == REG)
9233 /* If we are setting the whole register, we know its value. Otherwise
9234 show that we don't know the value. We can handle SUBREG in
9236 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
9237 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
9238 else if (GET_CODE (setter) == SET
9239 && GET_CODE (SET_DEST (setter)) == SUBREG
9240 && SUBREG_REG (SET_DEST (setter)) == dest
9241 && subreg_lowpart_p (SET_DEST (setter)))
9242 record_value_for_reg (dest, record_dead_insn,
9243 gen_lowpart_for_combine (GET_MODE (dest),
9246 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
9248 else if (GET_CODE (dest) == MEM
9249 /* Ignore pushes, they clobber nothing. */
9250 && ! push_operand (dest, GET_MODE (dest)))
9251 mem_last_set = INSN_CUID (record_dead_insn);
9254 /* Update the records of when each REG was most recently set or killed
9255 for the things done by INSN. This is the last thing done in processing
9256 INSN in the combiner loop.
9258 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
9259 similar information mem_last_set (which insn most recently modified memory)
9260 and last_call_cuid (which insn was the most recent subroutine call). */
9263 record_dead_and_set_regs (insn)
9269 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
9271 if (REG_NOTE_KIND (link) == REG_DEAD
9272 && GET_CODE (XEXP (link, 0)) == REG)
9274 int regno = REGNO (XEXP (link, 0));
9276 = regno + (regno < FIRST_PSEUDO_REGISTER
9277 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
9280 for (i = regno; i < endregno; i++)
9281 reg_last_death[i] = insn;
9283 else if (REG_NOTE_KIND (link) == REG_INC)
9284 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
9287 if (GET_CODE (insn) == CALL_INSN)
9289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9290 if (call_used_regs[i])
9292 reg_last_set_value[i] = 0;
9293 reg_last_death[i] = 0;
9296 last_call_cuid = mem_last_set = INSN_CUID (insn);
9299 record_dead_insn = insn;
9300 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
9303 /* Utility routine for the following function. Verify that all the registers
9304 mentioned in *LOC are valid when *LOC was part of a value set when
9305 label_tick == TICK. Return 0 if some are not.
9307 If REPLACE is non-zero, replace the invalid reference with
9308 (clobber (const_int 0)) and return 1. This replacement is useful because
9309 we often can get useful information about the form of a value (e.g., if
9310 it was produced by a shift that always produces -1 or 0) even though
9311 we don't know exactly what registers it was produced from. */
9314 get_last_value_validate (loc, tick, replace)
9320 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
9321 int len = GET_RTX_LENGTH (GET_CODE (x));
9324 if (GET_CODE (x) == REG)
9326 int regno = REGNO (x);
9327 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9328 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9331 for (j = regno; j < endregno; j++)
9332 if (reg_last_set_invalid[j]
9333 /* If this is a pseudo-register that was only set once, it is
9335 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
9336 && reg_last_set_label[j] > tick))
9339 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9346 for (i = 0; i < len; i++)
9348 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
9349 /* Don't bother with these. They shouldn't occur anyway. */
9353 /* If we haven't found a reason for it to be invalid, it is valid. */
9357 /* Get the last value assigned to X, if known. Some registers
9358 in the value may be replaced with (clobber (const_int 0)) if their value
9359 is known longer known reliably. */
9368 /* If this is a non-paradoxical SUBREG, get the value of its operand and
9369 then convert it to the desired mode. If this is a paradoxical SUBREG,
9370 we cannot predict what values the "extra" bits might have. */
9371 if (GET_CODE (x) == SUBREG
9372 && subreg_lowpart_p (x)
9373 && (GET_MODE_SIZE (GET_MODE (x))
9374 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
9375 && (value = get_last_value (SUBREG_REG (x))) != 0)
9376 return gen_lowpart_for_combine (GET_MODE (x), value);
9378 if (GET_CODE (x) != REG)
9382 value = reg_last_set_value[regno];
9384 /* If we don't have a value or if it isn't for this basic block, return 0. */
9387 || (reg_n_sets[regno] != 1
9388 && reg_last_set_label[regno] != label_tick))
9391 /* If the value was set in a later insn that the ones we are processing,
9392 we can't use it even if the register was only set once, but make a quick
9393 check to see if the previous insn set it to something. This is commonly
9394 the case when the same pseudo is used by repeated insns. */
9396 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
9400 for (insn = prev_nonnote_insn (subst_insn);
9401 insn && INSN_CUID (insn) >= subst_low_cuid;
9402 insn = prev_nonnote_insn (insn))
9406 && (set = single_set (insn)) != 0
9407 && rtx_equal_p (SET_DEST (set), x))
9409 value = SET_SRC (set);
9411 /* Make sure that VALUE doesn't reference X. Replace any
9412 expliit references with a CLOBBER. If there are any remaining
9413 references (rare), don't use the value. */
9415 if (reg_mentioned_p (x, value))
9416 value = replace_rtx (copy_rtx (value), x,
9417 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
9419 if (reg_overlap_mentioned_p (x, value))
9426 /* If the value has all its registers valid, return it. */
9427 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
9430 /* Otherwise, make a copy and replace any invalid register with
9431 (clobber (const_int 0)). If that fails for some reason, return 0. */
9433 value = copy_rtx (value);
9434 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
9440 /* Return nonzero if expression X refers to a REG or to memory
9441 that is set in an instruction more recent than FROM_CUID. */
9444 use_crosses_set_p (x, from_cuid)
9450 register enum rtx_code code = GET_CODE (x);
9454 register int regno = REGNO (x);
9455 #ifdef PUSH_ROUNDING
9456 /* Don't allow uses of the stack pointer to be moved,
9457 because we don't know whether the move crosses a push insn. */
9458 if (regno == STACK_POINTER_REGNUM)
9461 return (reg_last_set[regno]
9462 && INSN_CUID (reg_last_set[regno]) > from_cuid);
9465 if (code == MEM && mem_last_set > from_cuid)
9468 fmt = GET_RTX_FORMAT (code);
9470 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9475 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9476 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
9479 else if (fmt[i] == 'e'
9480 && use_crosses_set_p (XEXP (x, i), from_cuid))
9486 /* Define three variables used for communication between the following
9489 static int reg_dead_regno, reg_dead_endregno;
9490 static int reg_dead_flag;
9492 /* Function called via note_stores from reg_dead_at_p.
9494 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
9495 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
9498 reg_dead_at_p_1 (dest, x)
9502 int regno, endregno;
9504 if (GET_CODE (dest) != REG)
9507 regno = REGNO (dest);
9508 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9509 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
9511 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
9512 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
9515 /* Return non-zero if REG is known to be dead at INSN.
9517 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
9518 referencing REG, it is dead. If we hit a SET referencing REG, it is
9519 live. Otherwise, see if it is live or dead at the start of the basic
9523 reg_dead_at_p (reg, insn)
9529 /* Set variables for reg_dead_at_p_1. */
9530 reg_dead_regno = REGNO (reg);
9531 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
9532 ? HARD_REGNO_NREGS (reg_dead_regno,
9538 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
9539 beginning of function. */
9540 for (; insn && GET_CODE (insn) != CODE_LABEL;
9541 insn = prev_nonnote_insn (insn))
9543 note_stores (PATTERN (insn), reg_dead_at_p_1);
9545 return reg_dead_flag == 1 ? 1 : 0;
9547 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
9551 /* Get the basic block number that we were in. */
9556 for (block = 0; block < n_basic_blocks; block++)
9557 if (insn == basic_block_head[block])
9560 if (block == n_basic_blocks)
9564 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
9565 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
9566 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
9572 /* Remove register number REGNO from the dead registers list of INSN.
9574 Return the note used to record the death, if there was one. */
9577 remove_death (regno, insn)
9581 register rtx note = find_regno_note (insn, REG_DEAD, regno);
9585 reg_n_deaths[regno]--;
9586 remove_note (insn, note);
9592 /* For each register (hardware or pseudo) used within expression X, if its
9593 death is in an instruction with cuid between FROM_CUID (inclusive) and
9594 TO_INSN (exclusive), put a REG_DEAD note for that register in the
9595 list headed by PNOTES.
9597 This is done when X is being merged by combination into TO_INSN. These
9598 notes will then be distributed as needed. */
9601 move_deaths (x, from_cuid, to_insn, pnotes)
9608 register int len, i;
9609 register enum rtx_code code = GET_CODE (x);
9613 register int regno = REGNO (x);
9614 register rtx where_dead = reg_last_death[regno];
9616 if (where_dead && INSN_CUID (where_dead) >= from_cuid
9617 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9619 rtx note = remove_death (regno, where_dead);
9621 /* It is possible for the call above to return 0. This can occur
9622 when reg_last_death points to I2 or I1 that we combined with.
9623 In that case make a new note.
9625 We must also check for the case where X is a hard register
9626 and NOTE is a death note for a range of hard registers
9627 including X. In that case, we must put REG_DEAD notes for
9628 the remaining registers in place of NOTE. */
9630 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
9631 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
9632 != GET_MODE_SIZE (GET_MODE (x))))
9634 int deadregno = REGNO (XEXP (note, 0));
9636 = (deadregno + HARD_REGNO_NREGS (deadregno,
9637 GET_MODE (XEXP (note, 0))));
9638 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9641 for (i = deadregno; i < deadend; i++)
9642 if (i < regno || i >= ourend)
9643 REG_NOTES (where_dead)
9644 = gen_rtx (EXPR_LIST, REG_DEAD,
9645 gen_rtx (REG, word_mode, i),
9646 REG_NOTES (where_dead));
9649 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
9651 XEXP (note, 1) = *pnotes;
9655 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9657 reg_n_deaths[regno]++;
9663 else if (GET_CODE (x) == SET)
9665 rtx dest = SET_DEST (x);
9667 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9669 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9670 that accesses one word of a multi-word item, some
9671 piece of everything register in the expression is used by
9672 this insn, so remove any old death. */
9674 if (GET_CODE (dest) == ZERO_EXTRACT
9675 || GET_CODE (dest) == STRICT_LOW_PART
9676 || (GET_CODE (dest) == SUBREG
9677 && (((GET_MODE_SIZE (GET_MODE (dest))
9678 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9679 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9680 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9682 move_deaths (dest, from_cuid, to_insn, pnotes);
9686 /* If this is some other SUBREG, we know it replaces the entire
9687 value, so use that as the destination. */
9688 if (GET_CODE (dest) == SUBREG)
9689 dest = SUBREG_REG (dest);
9691 /* If this is a MEM, adjust deaths of anything used in the address.
9692 For a REG (the only other possibility), the entire value is
9693 being replaced so the old value is not used in this insn. */
9695 if (GET_CODE (dest) == MEM)
9696 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9700 else if (GET_CODE (x) == CLOBBER)
9703 len = GET_RTX_LENGTH (code);
9704 fmt = GET_RTX_FORMAT (code);
9706 for (i = 0; i < len; i++)
9711 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9712 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9714 else if (fmt[i] == 'e')
9715 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9719 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9720 pattern of an insn. X must be a REG. */
9723 reg_bitfield_target_p (x, body)
9729 if (GET_CODE (body) == SET)
9731 rtx dest = SET_DEST (body);
9733 int regno, tregno, endregno, endtregno;
9735 if (GET_CODE (dest) == ZERO_EXTRACT)
9736 target = XEXP (dest, 0);
9737 else if (GET_CODE (dest) == STRICT_LOW_PART)
9738 target = SUBREG_REG (XEXP (dest, 0));
9742 if (GET_CODE (target) == SUBREG)
9743 target = SUBREG_REG (target);
9745 if (GET_CODE (target) != REG)
9748 tregno = REGNO (target), regno = REGNO (x);
9749 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9752 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9753 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9755 return endregno > tregno && regno < endtregno;
9758 else if (GET_CODE (body) == PARALLEL)
9759 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9760 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9766 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9767 as appropriate. I3 and I2 are the insns resulting from the combination
9768 insns including FROM (I2 may be zero).
9770 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9771 not need REG_DEAD notes because they are being substituted for. This
9772 saves searching in the most common cases.
9774 Each note in the list is either ignored or placed on some insns, depending
9775 on the type of note. */
9778 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9782 rtx elim_i2, elim_i1;
9784 rtx note, next_note;
9787 for (note = notes; note; note = next_note)
9789 rtx place = 0, place2 = 0;
9791 /* If this NOTE references a pseudo register, ensure it references
9792 the latest copy of that register. */
9793 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9794 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9795 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9797 next_note = XEXP (note, 1);
9798 switch (REG_NOTE_KIND (note))
9801 /* If this register is set or clobbered in I3, put the note there
9802 unless there is one already. */
9803 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9805 if (! (GET_CODE (XEXP (note, 0)) == REG
9806 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9807 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9810 /* Otherwise, if this register is used by I3, then this register
9811 now dies here, so we must put a REG_DEAD note here unless there
9813 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9814 && ! (GET_CODE (XEXP (note, 0)) == REG
9815 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9816 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9818 PUT_REG_NOTE_KIND (note, REG_DEAD);
9826 /* These notes say something about results of an insn. We can
9827 only support them if they used to be on I3 in which case they
9828 remain on I3. Otherwise they are ignored.
9830 If the note refers to an expression that is not a constant, we
9831 must also ignore the note since we cannot tell whether the
9832 equivalence is still true. It might be possible to do
9833 slightly better than this (we only have a problem if I2DEST
9834 or I1DEST is present in the expression), but it doesn't
9835 seem worth the trouble. */
9838 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
9843 case REG_NO_CONFLICT:
9845 /* These notes say something about how a register is used. They must
9846 be present on any use of the register in I2 or I3. */
9847 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9850 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9860 /* It is too much trouble to try to see if this note is still
9861 correct in all situations. It is better to simply delete it. */
9865 /* If the insn previously containing this note still exists,
9866 put it back where it was. Otherwise move it to the previous
9867 insn. Adjust the corresponding REG_LIBCALL note. */
9868 if (GET_CODE (from_insn) != NOTE)
9872 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
9873 place = prev_real_insn (from_insn);
9875 XEXP (tem, 0) = place;
9880 /* This is handled similarly to REG_RETVAL. */
9881 if (GET_CODE (from_insn) != NOTE)
9885 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
9886 place = next_real_insn (from_insn);
9888 XEXP (tem, 0) = place;
9893 /* If the register is used as an input in I3, it dies there.
9894 Similarly for I2, if it is non-zero and adjacent to I3.
9896 If the register is not used as an input in either I3 or I2
9897 and it is not one of the registers we were supposed to eliminate,
9898 there are two possibilities. We might have a non-adjacent I2
9899 or we might have somehow eliminated an additional register
9900 from a computation. For example, we might have had A & B where
9901 we discover that B will always be zero. In this case we will
9902 eliminate the reference to A.
9904 In both cases, we must search to see if we can find a previous
9905 use of A and put the death note there. */
9907 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9909 else if (i2 != 0 && next_nonnote_insn (i2) == i3
9910 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9913 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9916 /* If the register is used in both I2 and I3 and it dies in I3,
9917 we might have added another reference to it. If reg_n_refs
9918 was 2, bump it to 3. This has to be correct since the
9919 register must have been set somewhere. The reason this is
9920 done is because local-alloc.c treats 2 references as a
9923 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
9924 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
9925 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9926 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
9929 for (tem = prev_nonnote_insn (i3);
9930 tem && (GET_CODE (tem) == INSN
9931 || GET_CODE (tem) == CALL_INSN);
9932 tem = prev_nonnote_insn (tem))
9934 /* If the register is being set at TEM, see if that is all
9935 TEM is doing. If so, delete TEM. Otherwise, make this
9936 into a REG_UNUSED note instead. */
9937 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9939 rtx set = single_set (tem);
9941 /* Verify that it was the set, and not a clobber that
9942 modified the register. */
9944 if (set != 0 && ! side_effects_p (SET_SRC (set))
9945 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
9947 /* Move the notes and links of TEM elsewhere.
9948 This might delete other dead insns recursively.
9949 First set the pattern to something that won't use
9952 PATTERN (tem) = pc_rtx;
9954 distribute_notes (REG_NOTES (tem), tem, tem,
9955 NULL_RTX, NULL_RTX, NULL_RTX);
9956 distribute_links (LOG_LINKS (tem));
9958 PUT_CODE (tem, NOTE);
9959 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9960 NOTE_SOURCE_FILE (tem) = 0;
9964 PUT_REG_NOTE_KIND (note, REG_UNUSED);
9966 /* If there isn't already a REG_UNUSED note, put one
9968 if (! find_regno_note (tem, REG_UNUSED,
9969 REGNO (XEXP (note, 0))))
9974 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9981 /* If the register is set or already dead at PLACE, we needn't do
9982 anything with this note if it is still a REG_DEAD note.
9984 Note that we cannot use just `dead_or_set_p' here since we can
9985 convert an assignment to a register into a bit-field assignment.
9986 Therefore, we must also omit the note if the register is the
9987 target of a bitfield assignment. */
9989 if (place && REG_NOTE_KIND (note) == REG_DEAD)
9991 int regno = REGNO (XEXP (note, 0));
9993 if (dead_or_set_p (place, XEXP (note, 0))
9994 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9996 /* Unless the register previously died in PLACE, clear
9997 reg_last_death. [I no longer understand why this is
9999 if (reg_last_death[regno] != place)
10000 reg_last_death[regno] = 0;
10004 reg_last_death[regno] = place;
10006 /* If this is a death note for a hard reg that is occupying
10007 multiple registers, ensure that we are still using all
10008 parts of the object. If we find a piece of the object
10009 that is unused, we must add a USE for that piece before
10010 PLACE and put the appropriate REG_DEAD note on it.
10012 An alternative would be to put a REG_UNUSED for the pieces
10013 on the insn that set the register, but that can't be done if
10014 it is not in the same block. It is simpler, though less
10015 efficient, to add the USE insns. */
10017 if (place && regno < FIRST_PSEUDO_REGISTER
10018 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
10021 = regno + HARD_REGNO_NREGS (regno,
10022 GET_MODE (XEXP (note, 0)));
10026 for (i = regno; i < endregno; i++)
10027 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
10029 rtx piece = gen_rtx (REG, word_mode, i);
10032 /* See if we already placed a USE note for this
10033 register in front of PLACE. */
10035 GET_CODE (PREV_INSN (p)) == INSN
10036 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
10038 if (rtx_equal_p (piece,
10039 XEXP (PATTERN (PREV_INSN (p)), 0)))
10048 = emit_insn_before (gen_rtx (USE, VOIDmode,
10051 REG_NOTES (use_insn)
10052 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
10053 REG_NOTES (use_insn));
10059 /* Check for the case where the register dying partially
10060 overlaps the register set by this insn. */
10062 for (i = regno; i < endregno; i++)
10063 if (dead_or_set_regno_p (place, i))
10071 /* Put only REG_DEAD notes for pieces that are
10072 still used and that are not already dead or set. */
10074 for (i = regno; i < endregno; i++)
10076 rtx piece = gen_rtx (REG, word_mode, i);
10078 if (reg_referenced_p (piece, PATTERN (place))
10079 && ! dead_or_set_p (place, piece)
10080 && ! reg_bitfield_target_p (piece,
10082 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
10084 REG_NOTES (place));
10094 /* Any other notes should not be present at this point in the
10101 XEXP (note, 1) = REG_NOTES (place);
10102 REG_NOTES (place) = note;
10104 else if ((REG_NOTE_KIND (note) == REG_DEAD
10105 || REG_NOTE_KIND (note) == REG_UNUSED)
10106 && GET_CODE (XEXP (note, 0)) == REG)
10107 reg_n_deaths[REGNO (XEXP (note, 0))]--;
10111 if ((REG_NOTE_KIND (note) == REG_DEAD
10112 || REG_NOTE_KIND (note) == REG_UNUSED)
10113 && GET_CODE (XEXP (note, 0)) == REG)
10114 reg_n_deaths[REGNO (XEXP (note, 0))]++;
10116 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
10117 XEXP (note, 0), REG_NOTES (place2));
10122 /* Similarly to above, distribute the LOG_LINKS that used to be present on
10123 I3, I2, and I1 to new locations. This is also called in one case to
10124 add a link pointing at I3 when I3's destination is changed. */
10127 distribute_links (links)
10130 rtx link, next_link;
10132 for (link = links; link; link = next_link)
10138 next_link = XEXP (link, 1);
10140 /* If the insn that this link points to is a NOTE or isn't a single
10141 set, ignore it. In the latter case, it isn't clear what we
10142 can do other than ignore the link, since we can't tell which
10143 register it was for. Such links wouldn't be used by combine
10146 It is not possible for the destination of the target of the link to
10147 have been changed by combine. The only potential of this is if we
10148 replace I3, I2, and I1 by I3 and I2. But in that case the
10149 destination of I2 also remains unchanged. */
10151 if (GET_CODE (XEXP (link, 0)) == NOTE
10152 || (set = single_set (XEXP (link, 0))) == 0)
10155 reg = SET_DEST (set);
10156 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
10157 || GET_CODE (reg) == SIGN_EXTRACT
10158 || GET_CODE (reg) == STRICT_LOW_PART)
10159 reg = XEXP (reg, 0);
10161 /* A LOG_LINK is defined as being placed on the first insn that uses
10162 a register and points to the insn that sets the register. Start
10163 searching at the next insn after the target of the link and stop
10164 when we reach a set of the register or the end of the basic block.
10166 Note that this correctly handles the link that used to point from
10167 I3 to I2. Also note that not much searching is typically done here
10168 since most links don't point very far away. */
10170 for (insn = NEXT_INSN (XEXP (link, 0));
10171 (insn && (this_basic_block == n_basic_blocks - 1
10172 || basic_block_head[this_basic_block + 1] != insn));
10173 insn = NEXT_INSN (insn))
10174 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
10175 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
10177 if (reg_referenced_p (reg, PATTERN (insn)))
10182 /* If we found a place to put the link, place it there unless there
10183 is already a link to the same insn as LINK at that point. */
10189 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
10190 if (XEXP (link2, 0) == XEXP (link, 0))
10195 XEXP (link, 1) = LOG_LINKS (place);
10196 LOG_LINKS (place) = link;
10203 dump_combine_stats (file)
10208 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
10209 combine_attempts, combine_merges, combine_extras, combine_successes);
10213 dump_combine_total_stats (file)
10218 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
10219 total_attempts, total_merges, total_extras, total_successes);