1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
348 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
349 union { rtx r; int i; enum machine_mode m; } old_contents;
350 union { rtx *r; int *i; } where;
353 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
354 num_undo says how many are currently recorded.
356 other_insn is nonzero if we have modified some other insn in the process
357 of working on subst_insn. It must be verified too. */
366 static struct undobuf undobuf;
368 /* Number of times the pseudo being substituted for
369 was found and replaced. */
371 static int n_occurrences;
373 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
375 unsigned HOST_WIDE_INT,
376 unsigned HOST_WIDE_INT *);
377 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
379 unsigned int, unsigned int *);
380 static void do_SUBST (rtx *, rtx);
381 static void do_SUBST_INT (int *, int);
382 static void init_reg_last (void);
383 static void setup_incoming_promotions (rtx);
384 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
385 static int cant_combine_insn_p (rtx);
386 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
387 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
388 static int contains_muldiv (rtx);
389 static rtx try_combine (rtx, rtx, rtx, int *);
390 static void undo_all (void);
391 static void undo_commit (void);
392 static rtx *find_split_point (rtx *, rtx);
393 static rtx subst (rtx, rtx, rtx, int, int);
394 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
395 static rtx simplify_if_then_else (rtx);
396 static rtx simplify_set (rtx);
397 static rtx simplify_logical (rtx);
398 static rtx expand_compound_operation (rtx);
399 static const_rtx expand_field_assignment (const_rtx);
400 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
401 rtx, unsigned HOST_WIDE_INT, int, int, int);
402 static rtx extract_left_shift (rtx, int);
403 static rtx make_compound_operation (rtx, enum rtx_code);
404 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
405 unsigned HOST_WIDE_INT *);
406 static rtx canon_reg_for_combine (rtx, rtx);
407 static rtx force_to_mode (rtx, enum machine_mode,
408 unsigned HOST_WIDE_INT, int);
409 static rtx if_then_else_cond (rtx, rtx *, rtx *);
410 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
411 static int rtx_equal_for_field_assignment_p (rtx, rtx);
412 static rtx make_field_assignment (rtx);
413 static rtx apply_distributive_law (rtx);
414 static rtx distribute_and_simplify_rtx (rtx, int);
415 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
416 unsigned HOST_WIDE_INT);
417 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
420 HOST_WIDE_INT, enum machine_mode, int *);
421 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
422 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
424 static int recog_for_combine (rtx *, rtx, rtx *);
425 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
426 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
427 static void update_table_tick (rtx);
428 static void record_value_for_reg (rtx, rtx, rtx);
429 static void check_promoted_subreg (rtx, rtx);
430 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
431 static void record_dead_and_set_regs (rtx);
432 static int get_last_value_validate (rtx *, rtx, int, int);
433 static rtx get_last_value (const_rtx);
434 static int use_crosses_set_p (const_rtx, int);
435 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
436 static int reg_dead_at_p (rtx, rtx);
437 static void move_deaths (rtx, rtx, int, rtx, rtx *);
438 static int reg_bitfield_target_p (rtx, rtx);
439 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
440 static void distribute_links (rtx);
441 static void mark_used_regs_combine (rtx);
442 static void record_promoted_value (rtx, rtx);
443 static int unmentioned_reg_p_1 (rtx *, void *);
444 static bool unmentioned_reg_p (rtx, rtx);
445 static int record_truncated_value (rtx *, void *);
446 static void record_truncated_values (rtx *, void *);
447 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
448 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
451 /* It is not safe to use ordinary gen_lowpart in combine.
452 See comments in gen_lowpart_for_combine. */
453 #undef RTL_HOOKS_GEN_LOWPART
454 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
456 /* Our implementation of gen_lowpart never emits a new pseudo. */
457 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
458 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
460 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
461 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
463 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
464 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
466 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
467 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
469 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
472 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
473 PATTERN can not be split. Otherwise, it returns an insn sequence.
474 This is a wrapper around split_insns which ensures that the
475 reg_stat vector is made larger if the splitter creates a new
479 combine_split_insns (rtx pattern, rtx insn)
484 ret = split_insns (pattern, insn);
485 nregs = max_reg_num ();
486 if (nregs > VEC_length (reg_stat_type, reg_stat))
487 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
491 /* This is used by find_single_use to locate an rtx in LOC that
492 contains exactly one use of DEST, which is typically either a REG
493 or CC0. It returns a pointer to the innermost rtx expression
494 containing DEST. Appearances of DEST that are being used to
495 totally replace it are not counted. */
498 find_single_use_1 (rtx dest, rtx *loc)
501 enum rtx_code code = GET_CODE (x);
519 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
520 of a REG that occupies all of the REG, the insn uses DEST if
521 it is mentioned in the destination or the source. Otherwise, we
522 need just check the source. */
523 if (GET_CODE (SET_DEST (x)) != CC0
524 && GET_CODE (SET_DEST (x)) != PC
525 && !REG_P (SET_DEST (x))
526 && ! (GET_CODE (SET_DEST (x)) == SUBREG
527 && REG_P (SUBREG_REG (SET_DEST (x)))
528 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
529 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
530 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
534 return find_single_use_1 (dest, &SET_SRC (x));
538 return find_single_use_1 (dest, &XEXP (x, 0));
544 /* If it wasn't one of the common cases above, check each expression and
545 vector of this code. Look for a unique usage of DEST. */
547 fmt = GET_RTX_FORMAT (code);
548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
552 if (dest == XEXP (x, i)
553 || (REG_P (dest) && REG_P (XEXP (x, i))
554 && REGNO (dest) == REGNO (XEXP (x, i))))
557 this_result = find_single_use_1 (dest, &XEXP (x, i));
560 result = this_result;
561 else if (this_result)
562 /* Duplicate usage. */
565 else if (fmt[i] == 'E')
569 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
571 if (XVECEXP (x, i, j) == dest
573 && REG_P (XVECEXP (x, i, j))
574 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
577 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
580 result = this_result;
581 else if (this_result)
591 /* See if DEST, produced in INSN, is used only a single time in the
592 sequel. If so, return a pointer to the innermost rtx expression in which
595 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
597 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
598 care about REG_DEAD notes or LOG_LINKS.
600 Otherwise, we find the single use by finding an insn that has a
601 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
602 only referenced once in that insn, we know that it must be the first
603 and last insn referencing DEST. */
606 find_single_use (rtx dest, rtx insn, rtx *ploc)
615 next = NEXT_INSN (insn);
617 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
620 result = find_single_use_1 (dest, &PATTERN (next));
630 for (next = next_nonnote_insn (insn);
631 next != 0 && !LABEL_P (next);
632 next = next_nonnote_insn (next))
633 if (INSN_P (next) && dead_or_set_p (next, dest))
635 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
636 if (XEXP (link, 0) == insn)
641 result = find_single_use_1 (dest, &PATTERN (next));
651 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
652 insn. The substitution can be undone by undo_all. If INTO is already
653 set to NEWVAL, do not record this change. Because computing NEWVAL might
654 also call SUBST, we have to compute it before we put anything into
658 do_SUBST (rtx *into, rtx newval)
663 if (oldval == newval)
666 /* We'd like to catch as many invalid transformations here as
667 possible. Unfortunately, there are way too many mode changes
668 that are perfectly valid, so we'd waste too much effort for
669 little gain doing the checks here. Focus on catching invalid
670 transformations involving integer constants. */
671 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
672 && GET_CODE (newval) == CONST_INT)
674 /* Sanity check that we're replacing oldval with a CONST_INT
675 that is a valid sign-extension for the original mode. */
676 gcc_assert (INTVAL (newval)
677 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
679 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
680 CONST_INT is not valid, because after the replacement, the
681 original mode would be gone. Unfortunately, we can't tell
682 when do_SUBST is called to replace the operand thereof, so we
683 perform this test on oldval instead, checking whether an
684 invalid replacement took place before we got here. */
685 gcc_assert (!(GET_CODE (oldval) == SUBREG
686 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
687 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
688 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
692 buf = undobuf.frees, undobuf.frees = buf->next;
694 buf = XNEW (struct undo);
696 buf->kind = UNDO_RTX;
698 buf->old_contents.r = oldval;
701 buf->next = undobuf.undos, undobuf.undos = buf;
704 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
706 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
707 for the value of a HOST_WIDE_INT value (including CONST_INT) is
711 do_SUBST_INT (int *into, int newval)
716 if (oldval == newval)
720 buf = undobuf.frees, undobuf.frees = buf->next;
722 buf = XNEW (struct undo);
724 buf->kind = UNDO_INT;
726 buf->old_contents.i = oldval;
729 buf->next = undobuf.undos, undobuf.undos = buf;
732 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
734 /* Similar to SUBST, but just substitute the mode. This is used when
735 changing the mode of a pseudo-register, so that any other
736 references to the entry in the regno_reg_rtx array will change as
740 do_SUBST_MODE (rtx *into, enum machine_mode newval)
743 enum machine_mode oldval = GET_MODE (*into);
745 if (oldval == newval)
749 buf = undobuf.frees, undobuf.frees = buf->next;
751 buf = XNEW (struct undo);
753 buf->kind = UNDO_MODE;
755 buf->old_contents.m = oldval;
756 adjust_reg_mode (*into, newval);
758 buf->next = undobuf.undos, undobuf.undos = buf;
761 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
763 /* Subroutine of try_combine. Determine whether the combine replacement
764 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
765 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
766 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
767 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
768 function returns false, if the costs of all instructions can be
769 estimated, and the replacements are more expensive than the original
773 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
776 int i1_cost, i2_cost, i3_cost;
777 int new_i2_cost, new_i3_cost;
778 int old_cost, new_cost;
780 /* Lookup the original insn_rtx_costs. */
781 i2_cost = INSN_COST (i2);
782 i3_cost = INSN_COST (i3);
786 i1_cost = INSN_COST (i1);
787 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
788 ? i1_cost + i2_cost + i3_cost : 0;
792 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
796 /* Calculate the replacement insn_rtx_costs. */
797 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
800 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
801 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
802 ? new_i2_cost + new_i3_cost : 0;
806 new_cost = new_i3_cost;
810 if (undobuf.other_insn)
812 int old_other_cost, new_other_cost;
814 old_other_cost = INSN_COST (undobuf.other_insn);
815 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
816 if (old_other_cost > 0 && new_other_cost > 0)
818 old_cost += old_other_cost;
819 new_cost += new_other_cost;
825 /* Disallow this recombination if both new_cost and old_cost are
826 greater than zero, and new_cost is greater than old cost. */
828 && new_cost > old_cost)
835 "rejecting combination of insns %d, %d and %d\n",
836 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
837 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
838 i1_cost, i2_cost, i3_cost, old_cost);
843 "rejecting combination of insns %d and %d\n",
844 INSN_UID (i2), INSN_UID (i3));
845 fprintf (dump_file, "original costs %d + %d = %d\n",
846 i2_cost, i3_cost, old_cost);
851 fprintf (dump_file, "replacement costs %d + %d = %d\n",
852 new_i2_cost, new_i3_cost, new_cost);
855 fprintf (dump_file, "replacement cost %d\n", new_cost);
861 /* Update the uid_insn_cost array with the replacement costs. */
862 INSN_COST (i2) = new_i2_cost;
863 INSN_COST (i3) = new_i3_cost;
871 /* Delete any insns that copy a register to itself. */
874 delete_noop_moves (void)
881 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
883 next = NEXT_INSN (insn);
884 if (INSN_P (insn) && noop_move_p (insn))
887 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
889 delete_insn_and_edges (insn);
896 /* Fill in log links field for all insns. */
899 create_log_links (void)
903 df_ref *def_vec, *use_vec;
905 next_use = XCNEWVEC (rtx, max_reg_num ());
907 /* Pass through each block from the end, recording the uses of each
908 register and establishing log links when def is encountered.
909 Note that we do not clear next_use array in order to save time,
910 so we have to test whether the use is in the same basic block as def.
912 There are a few cases below when we do not consider the definition or
913 usage -- these are taken from original flow.c did. Don't ask me why it is
914 done this way; I don't know and if it works, I don't want to know. */
918 FOR_BB_INSNS_REVERSE (bb, insn)
923 /* Log links are created only once. */
924 gcc_assert (!LOG_LINKS (insn));
926 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
928 df_ref def = *def_vec;
929 int regno = DF_REF_REGNO (def);
932 if (!next_use[regno])
935 /* Do not consider if it is pre/post modification in MEM. */
936 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
939 /* Do not make the log link for frame pointer. */
940 if ((regno == FRAME_POINTER_REGNUM
941 && (! reload_completed || frame_pointer_needed))
942 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
943 || (regno == HARD_FRAME_POINTER_REGNUM
944 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
947 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
952 use_insn = next_use[regno];
953 if (BLOCK_FOR_INSN (use_insn) == bb)
957 We don't build a LOG_LINK for hard registers contained
958 in ASM_OPERANDs. If these registers get replaced,
959 we might wind up changing the semantics of the insn,
960 even if reload can make what appear to be valid
961 assignments later. */
962 if (regno >= FIRST_PSEUDO_REGISTER
963 || asm_noperands (PATTERN (use_insn)) < 0)
965 /* Don't add duplicate links between instructions. */
967 for (links = LOG_LINKS (use_insn); links;
968 links = XEXP (links, 1))
969 if (insn == XEXP (links, 0))
973 LOG_LINKS (use_insn) =
974 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
977 next_use[regno] = NULL_RTX;
980 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
982 df_ref use = *use_vec;
983 int regno = DF_REF_REGNO (use);
985 /* Do not consider the usage of the stack pointer
987 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
990 next_use[regno] = insn;
998 /* Clear LOG_LINKS fields of insns. */
1001 clear_log_links (void)
1005 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1007 free_INSN_LIST_list (&LOG_LINKS (insn));
1013 /* Main entry point for combiner. F is the first insn of the function.
1014 NREGS is the first unused pseudo-reg number.
1016 Return nonzero if the combiner has turned an indirect jump
1017 instruction into a direct jump. */
1019 combine_instructions (rtx f, unsigned int nregs)
1025 rtx links, nextlinks;
1028 int new_direct_jump_p = 0;
1030 for (first = f; first && !INSN_P (first); )
1031 first = NEXT_INSN (first);
1035 combine_attempts = 0;
1038 combine_successes = 0;
1040 rtl_hooks = combine_rtl_hooks;
1042 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1044 init_recog_no_volatile ();
1046 /* Allocate array for insn info. */
1047 max_uid_known = get_max_uid ();
1048 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1049 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1051 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1053 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1054 problems when, for example, we have j <<= 1 in a loop. */
1056 nonzero_sign_valid = 0;
1058 /* Scan all SETs and see if we can deduce anything about what
1059 bits are known to be zero for some registers and how many copies
1060 of the sign bit are known to exist for those registers.
1062 Also set any known values so that we can use it while searching
1063 for what bits are known to be set. */
1065 label_tick = label_tick_ebb_start = 1;
1067 setup_incoming_promotions (first);
1069 create_log_links ();
1070 FOR_EACH_BB (this_basic_block)
1072 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1076 FOR_BB_INSNS (this_basic_block, insn)
1077 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1079 subst_low_luid = DF_INSN_LUID (insn);
1082 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1084 record_dead_and_set_regs (insn);
1087 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1088 if (REG_NOTE_KIND (links) == REG_INC)
1089 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1093 /* Record the current insn_rtx_cost of this instruction. */
1094 if (NONJUMP_INSN_P (insn))
1095 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1096 optimize_this_for_speed_p);
1098 fprintf(dump_file, "insn_cost %d: %d\n",
1099 INSN_UID (insn), INSN_COST (insn));
1101 else if (LABEL_P (insn))
1102 label_tick_ebb_start = label_tick;
1105 nonzero_sign_valid = 1;
1107 /* Now scan all the insns in forward order. */
1109 label_tick = label_tick_ebb_start = 1;
1111 setup_incoming_promotions (first);
1113 FOR_EACH_BB (this_basic_block)
1118 rtl_profile_for_bb (this_basic_block);
1119 for (insn = BB_HEAD (this_basic_block);
1120 insn != NEXT_INSN (BB_END (this_basic_block));
1121 insn = next ? next : NEXT_INSN (insn))
1126 /* See if we know about function return values before this
1127 insn based upon SUBREG flags. */
1128 check_promoted_subreg (insn, PATTERN (insn));
1130 /* See if we can find hardregs and subreg of pseudos in
1131 narrower modes. This could help turning TRUNCATEs
1133 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1135 /* Try this insn with each insn it links back to. */
1137 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1138 if ((next = try_combine (insn, XEXP (links, 0),
1139 NULL_RTX, &new_direct_jump_p)) != 0)
1142 /* Try each sequence of three linked insns ending with this one. */
1144 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1146 rtx link = XEXP (links, 0);
1148 /* If the linked insn has been replaced by a note, then there
1149 is no point in pursuing this chain any further. */
1153 for (nextlinks = LOG_LINKS (link);
1155 nextlinks = XEXP (nextlinks, 1))
1156 if ((next = try_combine (insn, link,
1157 XEXP (nextlinks, 0),
1158 &new_direct_jump_p)) != 0)
1163 /* Try to combine a jump insn that uses CC0
1164 with a preceding insn that sets CC0, and maybe with its
1165 logical predecessor as well.
1166 This is how we make decrement-and-branch insns.
1167 We need this special code because data flow connections
1168 via CC0 do not get entered in LOG_LINKS. */
1171 && (prev = prev_nonnote_insn (insn)) != 0
1172 && NONJUMP_INSN_P (prev)
1173 && sets_cc0_p (PATTERN (prev)))
1175 if ((next = try_combine (insn, prev,
1176 NULL_RTX, &new_direct_jump_p)) != 0)
1179 for (nextlinks = LOG_LINKS (prev); nextlinks;
1180 nextlinks = XEXP (nextlinks, 1))
1181 if ((next = try_combine (insn, prev,
1182 XEXP (nextlinks, 0),
1183 &new_direct_jump_p)) != 0)
1187 /* Do the same for an insn that explicitly references CC0. */
1188 if (NONJUMP_INSN_P (insn)
1189 && (prev = prev_nonnote_insn (insn)) != 0
1190 && NONJUMP_INSN_P (prev)
1191 && sets_cc0_p (PATTERN (prev))
1192 && GET_CODE (PATTERN (insn)) == SET
1193 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1195 if ((next = try_combine (insn, prev,
1196 NULL_RTX, &new_direct_jump_p)) != 0)
1199 for (nextlinks = LOG_LINKS (prev); nextlinks;
1200 nextlinks = XEXP (nextlinks, 1))
1201 if ((next = try_combine (insn, prev,
1202 XEXP (nextlinks, 0),
1203 &new_direct_jump_p)) != 0)
1207 /* Finally, see if any of the insns that this insn links to
1208 explicitly references CC0. If so, try this insn, that insn,
1209 and its predecessor if it sets CC0. */
1210 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1211 if (NONJUMP_INSN_P (XEXP (links, 0))
1212 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1213 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1214 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1215 && NONJUMP_INSN_P (prev)
1216 && sets_cc0_p (PATTERN (prev))
1217 && (next = try_combine (insn, XEXP (links, 0),
1218 prev, &new_direct_jump_p)) != 0)
1222 /* Try combining an insn with two different insns whose results it
1224 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1225 for (nextlinks = XEXP (links, 1); nextlinks;
1226 nextlinks = XEXP (nextlinks, 1))
1227 if ((next = try_combine (insn, XEXP (links, 0),
1228 XEXP (nextlinks, 0),
1229 &new_direct_jump_p)) != 0)
1232 /* Try this insn with each REG_EQUAL note it links back to. */
1233 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1236 rtx temp = XEXP (links, 0);
1237 if ((set = single_set (temp)) != 0
1238 && (note = find_reg_equal_equiv_note (temp)) != 0
1239 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1240 /* Avoid using a register that may already been marked
1241 dead by an earlier instruction. */
1242 && ! unmentioned_reg_p (note, SET_SRC (set))
1243 && (GET_MODE (note) == VOIDmode
1244 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1245 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1247 /* Temporarily replace the set's source with the
1248 contents of the REG_EQUAL note. The insn will
1249 be deleted or recognized by try_combine. */
1250 rtx orig = SET_SRC (set);
1251 SET_SRC (set) = note;
1253 i2mod_old_rhs = copy_rtx (orig);
1254 i2mod_new_rhs = copy_rtx (note);
1255 next = try_combine (insn, i2mod, NULL_RTX,
1256 &new_direct_jump_p);
1260 SET_SRC (set) = orig;
1265 record_dead_and_set_regs (insn);
1270 else if (LABEL_P (insn))
1271 label_tick_ebb_start = label_tick;
1275 default_rtl_profile ();
1278 new_direct_jump_p |= purge_all_dead_edges ();
1279 delete_noop_moves ();
1282 free (uid_log_links);
1283 free (uid_insn_cost);
1284 VEC_free (reg_stat_type, heap, reg_stat);
1287 struct undo *undo, *next;
1288 for (undo = undobuf.frees; undo; undo = next)
1296 total_attempts += combine_attempts;
1297 total_merges += combine_merges;
1298 total_extras += combine_extras;
1299 total_successes += combine_successes;
1301 nonzero_sign_valid = 0;
1302 rtl_hooks = general_rtl_hooks;
1304 /* Make recognizer allow volatile MEMs again. */
1307 return new_direct_jump_p;
1310 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1313 init_reg_last (void)
1318 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1319 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1322 /* Set up any promoted values for incoming argument registers. */
1325 setup_incoming_promotions (rtx first)
1328 bool strictly_local = false;
1330 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1333 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1334 arg = TREE_CHAIN (arg))
1336 rtx reg = DECL_INCOMING_RTL (arg);
1338 enum machine_mode mode1, mode2, mode3, mode4;
1340 /* Only continue if the incoming argument is in a register. */
1344 /* Determine, if possible, whether all call sites of the current
1345 function lie within the current compilation unit. (This does
1346 take into account the exporting of a function via taking its
1347 address, and so forth.) */
1348 strictly_local = cgraph_local_info (current_function_decl)->local;
1350 /* The mode and signedness of the argument before any promotions happen
1351 (equal to the mode of the pseudo holding it at that stage). */
1352 mode1 = TYPE_MODE (TREE_TYPE (arg));
1353 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1355 /* The mode and signedness of the argument after any source language and
1356 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1357 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1358 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1360 /* The mode and signedness of the argument as it is actually passed,
1361 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1362 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1364 /* The mode of the register in which the argument is being passed. */
1365 mode4 = GET_MODE (reg);
1367 /* Eliminate sign extensions in the callee when possible. Only
1369 (a) a mode promotion has occurred;
1370 (b) the mode of the register is the same as the mode of
1371 the argument as it is passed; and
1372 (c) the signedness does not change across any of the promotions; and
1373 (d) when no language-level promotions (which we cannot guarantee
1374 will have been done by an external caller) are necessary,
1375 unless we know that this function is only ever called from
1376 the current compilation unit -- all of whose call sites will
1377 do the mode1 --> mode2 promotion. */
1381 && (mode1 == mode2 || strictly_local))
1383 /* Record that the value was promoted from mode1 to mode3,
1384 so that any sign extension at the head of the current
1385 function may be eliminated. */
1387 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1388 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1389 record_value_for_reg (reg, first, x);
1394 /* Called via note_stores. If X is a pseudo that is narrower than
1395 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1397 If we are setting only a portion of X and we can't figure out what
1398 portion, assume all bits will be used since we don't know what will
1401 Similarly, set how many bits of X are known to be copies of the sign bit
1402 at all locations in the function. This is the smallest number implied
1406 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1408 rtx insn = (rtx) data;
1412 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1413 /* If this register is undefined at the start of the file, we can't
1414 say what its contents were. */
1415 && ! REGNO_REG_SET_P
1416 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1417 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1419 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1421 if (set == 0 || GET_CODE (set) == CLOBBER)
1423 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1424 rsp->sign_bit_copies = 1;
1428 /* If this register is being initialized using itself, and the
1429 register is uninitialized in this basic block, and there are
1430 no LOG_LINKS which set the register, then part of the
1431 register is uninitialized. In that case we can't assume
1432 anything about the number of nonzero bits.
1434 ??? We could do better if we checked this in
1435 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1436 could avoid making assumptions about the insn which initially
1437 sets the register, while still using the information in other
1438 insns. We would have to be careful to check every insn
1439 involved in the combination. */
1442 && reg_referenced_p (x, PATTERN (insn))
1443 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1448 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1450 if (dead_or_set_p (XEXP (link, 0), x))
1455 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1456 rsp->sign_bit_copies = 1;
1461 /* If this is a complex assignment, see if we can convert it into a
1462 simple assignment. */
1463 set = expand_field_assignment (set);
1465 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1466 set what we know about X. */
1468 if (SET_DEST (set) == x
1469 || (GET_CODE (SET_DEST (set)) == SUBREG
1470 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1471 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1472 && SUBREG_REG (SET_DEST (set)) == x))
1474 rtx src = SET_SRC (set);
1476 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1477 /* If X is narrower than a word and SRC is a non-negative
1478 constant that would appear negative in the mode of X,
1479 sign-extend it for use in reg_stat[].nonzero_bits because some
1480 machines (maybe most) will actually do the sign-extension
1481 and this is the conservative approach.
1483 ??? For 2.5, try to tighten up the MD files in this regard
1484 instead of this kludge. */
1486 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1487 && GET_CODE (src) == CONST_INT
1489 && 0 != (INTVAL (src)
1490 & ((HOST_WIDE_INT) 1
1491 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1492 src = GEN_INT (INTVAL (src)
1493 | ((HOST_WIDE_INT) (-1)
1494 << GET_MODE_BITSIZE (GET_MODE (x))));
1497 /* Don't call nonzero_bits if it cannot change anything. */
1498 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1499 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1500 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1501 if (rsp->sign_bit_copies == 0
1502 || rsp->sign_bit_copies > num)
1503 rsp->sign_bit_copies = num;
1507 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1508 rsp->sign_bit_copies = 1;
1513 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1514 insns that were previously combined into I3 or that will be combined
1515 into the merger of INSN and I3.
1517 Return 0 if the combination is not allowed for any reason.
1519 If the combination is allowed, *PDEST will be set to the single
1520 destination of INSN and *PSRC to the single source, and this function
1524 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1525 rtx *pdest, rtx *psrc)
1534 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1535 && next_active_insn (succ) == i3)
1536 : next_active_insn (insn) == i3);
1538 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1539 or a PARALLEL consisting of such a SET and CLOBBERs.
1541 If INSN has CLOBBER parallel parts, ignore them for our processing.
1542 By definition, these happen during the execution of the insn. When it
1543 is merged with another insn, all bets are off. If they are, in fact,
1544 needed and aren't also supplied in I3, they may be added by
1545 recog_for_combine. Otherwise, it won't match.
1547 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1550 Get the source and destination of INSN. If more than one, can't
1553 if (GET_CODE (PATTERN (insn)) == SET)
1554 set = PATTERN (insn);
1555 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1556 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1558 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1560 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1563 switch (GET_CODE (elt))
1565 /* This is important to combine floating point insns
1566 for the SH4 port. */
1568 /* Combining an isolated USE doesn't make sense.
1569 We depend here on combinable_i3pat to reject them. */
1570 /* The code below this loop only verifies that the inputs of
1571 the SET in INSN do not change. We call reg_set_between_p
1572 to verify that the REG in the USE does not change between
1574 If the USE in INSN was for a pseudo register, the matching
1575 insn pattern will likely match any register; combining this
1576 with any other USE would only be safe if we knew that the
1577 used registers have identical values, or if there was
1578 something to tell them apart, e.g. different modes. For
1579 now, we forgo such complicated tests and simply disallow
1580 combining of USES of pseudo registers with any other USE. */
1581 if (REG_P (XEXP (elt, 0))
1582 && GET_CODE (PATTERN (i3)) == PARALLEL)
1584 rtx i3pat = PATTERN (i3);
1585 int i = XVECLEN (i3pat, 0) - 1;
1586 unsigned int regno = REGNO (XEXP (elt, 0));
1590 rtx i3elt = XVECEXP (i3pat, 0, i);
1592 if (GET_CODE (i3elt) == USE
1593 && REG_P (XEXP (i3elt, 0))
1594 && (REGNO (XEXP (i3elt, 0)) == regno
1595 ? reg_set_between_p (XEXP (elt, 0),
1596 PREV_INSN (insn), i3)
1597 : regno >= FIRST_PSEUDO_REGISTER))
1604 /* We can ignore CLOBBERs. */
1609 /* Ignore SETs whose result isn't used but not those that
1610 have side-effects. */
1611 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1612 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1613 || INTVAL (XEXP (note, 0)) <= 0)
1614 && ! side_effects_p (elt))
1617 /* If we have already found a SET, this is a second one and
1618 so we cannot combine with this insn. */
1626 /* Anything else means we can't combine. */
1632 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1633 so don't do anything with it. */
1634 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1643 set = expand_field_assignment (set);
1644 src = SET_SRC (set), dest = SET_DEST (set);
1646 /* Don't eliminate a store in the stack pointer. */
1647 if (dest == stack_pointer_rtx
1648 /* Don't combine with an insn that sets a register to itself if it has
1649 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1650 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1651 /* Can't merge an ASM_OPERANDS. */
1652 || GET_CODE (src) == ASM_OPERANDS
1653 /* Can't merge a function call. */
1654 || GET_CODE (src) == CALL
1655 /* Don't eliminate a function call argument. */
1657 && (find_reg_fusage (i3, USE, dest)
1659 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1660 && global_regs[REGNO (dest)])))
1661 /* Don't substitute into an incremented register. */
1662 || FIND_REG_INC_NOTE (i3, dest)
1663 || (succ && FIND_REG_INC_NOTE (succ, dest))
1664 /* Don't substitute into a non-local goto, this confuses CFG. */
1665 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1666 /* Make sure that DEST is not used after SUCC but before I3. */
1667 || (succ && ! all_adjacent
1668 && reg_used_between_p (dest, succ, i3))
1669 /* Make sure that the value that is to be substituted for the register
1670 does not use any registers whose values alter in between. However,
1671 If the insns are adjacent, a use can't cross a set even though we
1672 think it might (this can happen for a sequence of insns each setting
1673 the same destination; last_set of that register might point to
1674 a NOTE). If INSN has a REG_EQUIV note, the register is always
1675 equivalent to the memory so the substitution is valid even if there
1676 are intervening stores. Also, don't move a volatile asm or
1677 UNSPEC_VOLATILE across any other insns. */
1680 || ! find_reg_note (insn, REG_EQUIV, src))
1681 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1682 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1683 || GET_CODE (src) == UNSPEC_VOLATILE))
1684 /* Don't combine across a CALL_INSN, because that would possibly
1685 change whether the life span of some REGs crosses calls or not,
1686 and it is a pain to update that information.
1687 Exception: if source is a constant, moving it later can't hurt.
1688 Accept that as a special case. */
1689 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1692 /* DEST must either be a REG or CC0. */
1695 /* If register alignment is being enforced for multi-word items in all
1696 cases except for parameters, it is possible to have a register copy
1697 insn referencing a hard register that is not allowed to contain the
1698 mode being copied and which would not be valid as an operand of most
1699 insns. Eliminate this problem by not combining with such an insn.
1701 Also, on some machines we don't want to extend the life of a hard
1705 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1706 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1707 /* Don't extend the life of a hard register unless it is
1708 user variable (if we have few registers) or it can't
1709 fit into the desired register (meaning something special
1711 Also avoid substituting a return register into I3, because
1712 reload can't handle a conflict with constraints of other
1714 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1715 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1718 else if (GET_CODE (dest) != CC0)
1722 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1723 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1724 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1726 /* Don't substitute for a register intended as a clobberable
1728 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1729 if (rtx_equal_p (reg, dest))
1732 /* If the clobber represents an earlyclobber operand, we must not
1733 substitute an expression containing the clobbered register.
1734 As we do not analyze the constraint strings here, we have to
1735 make the conservative assumption. However, if the register is
1736 a fixed hard reg, the clobber cannot represent any operand;
1737 we leave it up to the machine description to either accept or
1738 reject use-and-clobber patterns. */
1740 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1741 || !fixed_regs[REGNO (reg)])
1742 if (reg_overlap_mentioned_p (reg, src))
1746 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1747 or not), reject, unless nothing volatile comes between it and I3 */
1749 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1751 /* Make sure succ doesn't contain a volatile reference. */
1752 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1755 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1756 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1760 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1761 to be an explicit register variable, and was chosen for a reason. */
1763 if (GET_CODE (src) == ASM_OPERANDS
1764 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1767 /* If there are any volatile insns between INSN and I3, reject, because
1768 they might affect machine state. */
1770 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1771 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1774 /* If INSN contains an autoincrement or autodecrement, make sure that
1775 register is not used between there and I3, and not already used in
1776 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1777 Also insist that I3 not be a jump; if it were one
1778 and the incremented register were spilled, we would lose. */
1781 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1782 if (REG_NOTE_KIND (link) == REG_INC
1784 || reg_used_between_p (XEXP (link, 0), insn, i3)
1785 || (pred != NULL_RTX
1786 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1787 || (succ != NULL_RTX
1788 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1789 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1794 /* Don't combine an insn that follows a CC0-setting insn.
1795 An insn that uses CC0 must not be separated from the one that sets it.
1796 We do, however, allow I2 to follow a CC0-setting insn if that insn
1797 is passed as I1; in that case it will be deleted also.
1798 We also allow combining in this case if all the insns are adjacent
1799 because that would leave the two CC0 insns adjacent as well.
1800 It would be more logical to test whether CC0 occurs inside I1 or I2,
1801 but that would be much slower, and this ought to be equivalent. */
1803 p = prev_nonnote_insn (insn);
1804 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1809 /* If we get here, we have passed all the tests and the combination is
1818 /* LOC is the location within I3 that contains its pattern or the component
1819 of a PARALLEL of the pattern. We validate that it is valid for combining.
1821 One problem is if I3 modifies its output, as opposed to replacing it
1822 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1823 so would produce an insn that is not equivalent to the original insns.
1827 (set (reg:DI 101) (reg:DI 100))
1828 (set (subreg:SI (reg:DI 101) 0) <foo>)
1830 This is NOT equivalent to:
1832 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1833 (set (reg:DI 101) (reg:DI 100))])
1835 Not only does this modify 100 (in which case it might still be valid
1836 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1838 We can also run into a problem if I2 sets a register that I1
1839 uses and I1 gets directly substituted into I3 (not via I2). In that
1840 case, we would be getting the wrong value of I2DEST into I3, so we
1841 must reject the combination. This case occurs when I2 and I1 both
1842 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1843 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1844 of a SET must prevent combination from occurring.
1846 Before doing the above check, we first try to expand a field assignment
1847 into a set of logical operations.
1849 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1850 we place a register that is both set and used within I3. If more than one
1851 such register is detected, we fail.
1853 Return 1 if the combination is valid, zero otherwise. */
1856 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1857 int i1_not_in_src, rtx *pi3dest_killed)
1861 if (GET_CODE (x) == SET)
1864 rtx dest = SET_DEST (set);
1865 rtx src = SET_SRC (set);
1866 rtx inner_dest = dest;
1869 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1870 || GET_CODE (inner_dest) == SUBREG
1871 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1872 inner_dest = XEXP (inner_dest, 0);
1874 /* Check for the case where I3 modifies its output, as discussed
1875 above. We don't want to prevent pseudos from being combined
1876 into the address of a MEM, so only prevent the combination if
1877 i1 or i2 set the same MEM. */
1878 if ((inner_dest != dest &&
1879 (!MEM_P (inner_dest)
1880 || rtx_equal_p (i2dest, inner_dest)
1881 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1882 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1883 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1885 /* This is the same test done in can_combine_p except we can't test
1886 all_adjacent; we don't have to, since this instruction will stay
1887 in place, thus we are not considering increasing the lifetime of
1890 Also, if this insn sets a function argument, combining it with
1891 something that might need a spill could clobber a previous
1892 function argument; the all_adjacent test in can_combine_p also
1893 checks this; here, we do a more specific test for this case. */
1895 || (REG_P (inner_dest)
1896 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1897 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1898 GET_MODE (inner_dest))))
1899 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1902 /* If DEST is used in I3, it is being killed in this insn, so
1903 record that for later. We have to consider paradoxical
1904 subregs here, since they kill the whole register, but we
1905 ignore partial subregs, STRICT_LOW_PART, etc.
1906 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1907 STACK_POINTER_REGNUM, since these are always considered to be
1908 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1910 if (GET_CODE (subdest) == SUBREG
1911 && (GET_MODE_SIZE (GET_MODE (subdest))
1912 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1913 subdest = SUBREG_REG (subdest);
1916 && reg_referenced_p (subdest, PATTERN (i3))
1917 && REGNO (subdest) != FRAME_POINTER_REGNUM
1918 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1919 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1921 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1922 && (REGNO (subdest) != ARG_POINTER_REGNUM
1923 || ! fixed_regs [REGNO (subdest)])
1925 && REGNO (subdest) != STACK_POINTER_REGNUM)
1927 if (*pi3dest_killed)
1930 *pi3dest_killed = subdest;
1934 else if (GET_CODE (x) == PARALLEL)
1938 for (i = 0; i < XVECLEN (x, 0); i++)
1939 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1940 i1_not_in_src, pi3dest_killed))
1947 /* Return 1 if X is an arithmetic expression that contains a multiplication
1948 and division. We don't count multiplications by powers of two here. */
1951 contains_muldiv (rtx x)
1953 switch (GET_CODE (x))
1955 case MOD: case DIV: case UMOD: case UDIV:
1959 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1960 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1963 return contains_muldiv (XEXP (x, 0))
1964 || contains_muldiv (XEXP (x, 1));
1967 return contains_muldiv (XEXP (x, 0));
1973 /* Determine whether INSN can be used in a combination. Return nonzero if
1974 not. This is used in try_combine to detect early some cases where we
1975 can't perform combinations. */
1978 cant_combine_insn_p (rtx insn)
1983 /* If this isn't really an insn, we can't do anything.
1984 This can occur when flow deletes an insn that it has merged into an
1985 auto-increment address. */
1986 if (! INSN_P (insn))
1989 /* Never combine loads and stores involving hard regs that are likely
1990 to be spilled. The register allocator can usually handle such
1991 reg-reg moves by tying. If we allow the combiner to make
1992 substitutions of likely-spilled regs, reload might die.
1993 As an exception, we allow combinations involving fixed regs; these are
1994 not available to the register allocator so there's no risk involved. */
1996 set = single_set (insn);
1999 src = SET_SRC (set);
2000 dest = SET_DEST (set);
2001 if (GET_CODE (src) == SUBREG)
2002 src = SUBREG_REG (src);
2003 if (GET_CODE (dest) == SUBREG)
2004 dest = SUBREG_REG (dest);
2005 if (REG_P (src) && REG_P (dest)
2006 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2007 && ! fixed_regs[REGNO (src)]
2008 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2009 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2010 && ! fixed_regs[REGNO (dest)]
2011 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2017 struct likely_spilled_retval_info
2019 unsigned regno, nregs;
2023 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2024 hard registers that are known to be written to / clobbered in full. */
2026 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2028 struct likely_spilled_retval_info *const info =
2029 (struct likely_spilled_retval_info *) data;
2030 unsigned regno, nregs;
2033 if (!REG_P (XEXP (set, 0)))
2036 if (regno >= info->regno + info->nregs)
2038 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2039 if (regno + nregs <= info->regno)
2041 new_mask = (2U << (nregs - 1)) - 1;
2042 if (regno < info->regno)
2043 new_mask >>= info->regno - regno;
2045 new_mask <<= regno - info->regno;
2046 info->mask &= ~new_mask;
2049 /* Return nonzero iff part of the return value is live during INSN, and
2050 it is likely spilled. This can happen when more than one insn is needed
2051 to copy the return value, e.g. when we consider to combine into the
2052 second copy insn for a complex value. */
2055 likely_spilled_retval_p (rtx insn)
2057 rtx use = BB_END (this_basic_block);
2059 unsigned regno, nregs;
2060 /* We assume here that no machine mode needs more than
2061 32 hard registers when the value overlaps with a register
2062 for which FUNCTION_VALUE_REGNO_P is true. */
2064 struct likely_spilled_retval_info info;
2066 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2068 reg = XEXP (PATTERN (use), 0);
2069 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2071 regno = REGNO (reg);
2072 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2075 mask = (2U << (nregs - 1)) - 1;
2077 /* Disregard parts of the return value that are set later. */
2081 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2083 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2086 /* Check if any of the (probably) live return value registers is
2091 if ((mask & 1 << nregs)
2092 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2098 /* Adjust INSN after we made a change to its destination.
2100 Changing the destination can invalidate notes that say something about
2101 the results of the insn and a LOG_LINK pointing to the insn. */
2104 adjust_for_new_dest (rtx insn)
2106 /* For notes, be conservative and simply remove them. */
2107 remove_reg_equal_equiv_notes (insn);
2109 /* The new insn will have a destination that was previously the destination
2110 of an insn just above it. Call distribute_links to make a LOG_LINK from
2111 the next use of that destination. */
2112 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2114 df_insn_rescan (insn);
2117 /* Return TRUE if combine can reuse reg X in mode MODE.
2118 ADDED_SETS is nonzero if the original set is still required. */
2120 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2128 /* Allow hard registers if the new mode is legal, and occupies no more
2129 registers than the old mode. */
2130 if (regno < FIRST_PSEUDO_REGISTER)
2131 return (HARD_REGNO_MODE_OK (regno, mode)
2132 && (hard_regno_nregs[regno][GET_MODE (x)]
2133 >= hard_regno_nregs[regno][mode]));
2135 /* Or a pseudo that is only used once. */
2136 return (REG_N_SETS (regno) == 1 && !added_sets
2137 && !REG_USERVAR_P (x));
2141 /* Check whether X, the destination of a set, refers to part of
2142 the register specified by REG. */
2145 reg_subword_p (rtx x, rtx reg)
2147 /* Check that reg is an integer mode register. */
2148 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2151 if (GET_CODE (x) == STRICT_LOW_PART
2152 || GET_CODE (x) == ZERO_EXTRACT)
2155 return GET_CODE (x) == SUBREG
2156 && SUBREG_REG (x) == reg
2157 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2161 /* Try to combine the insns I1 and I2 into I3.
2162 Here I1 and I2 appear earlier than I3.
2163 I1 can be zero; then we combine just I2 into I3.
2165 If we are combining three insns and the resulting insn is not recognized,
2166 try splitting it into two insns. If that happens, I2 and I3 are retained
2167 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2170 Return 0 if the combination does not work. Then nothing is changed.
2171 If we did the combination, return the insn at which combine should
2174 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2175 new direct jump instruction. */
2178 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2180 /* New patterns for I3 and I2, respectively. */
2181 rtx newpat, newi2pat = 0;
2182 rtvec newpat_vec_with_clobbers = 0;
2183 int substed_i2 = 0, substed_i1 = 0;
2184 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2185 int added_sets_1, added_sets_2;
2186 /* Total number of SETs to put into I3. */
2188 /* Nonzero if I2's body now appears in I3. */
2190 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2191 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2192 /* Contains I3 if the destination of I3 is used in its source, which means
2193 that the old life of I3 is being killed. If that usage is placed into
2194 I2 and not in I3, a REG_DEAD note must be made. */
2195 rtx i3dest_killed = 0;
2196 /* SET_DEST and SET_SRC of I2 and I1. */
2197 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2198 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2199 rtx i1pat = 0, i2pat = 0;
2200 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2201 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2202 int i2dest_killed = 0, i1dest_killed = 0;
2203 int i1_feeds_i3 = 0;
2204 /* Notes that must be added to REG_NOTES in I3 and I2. */
2205 rtx new_i3_notes, new_i2_notes;
2206 /* Notes that we substituted I3 into I2 instead of the normal case. */
2207 int i3_subst_into_i2 = 0;
2208 /* Notes that I1, I2 or I3 is a MULT operation. */
2216 rtx new_other_notes;
2219 /* Exit early if one of the insns involved can't be used for
2221 if (cant_combine_insn_p (i3)
2222 || cant_combine_insn_p (i2)
2223 || (i1 && cant_combine_insn_p (i1))
2224 || likely_spilled_retval_p (i3))
2228 undobuf.other_insn = 0;
2230 /* Reset the hard register usage information. */
2231 CLEAR_HARD_REG_SET (newpat_used_regs);
2233 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2234 code below, set I1 to be the earlier of the two insns. */
2235 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2236 temp = i1, i1 = i2, i2 = temp;
2238 added_links_insn = 0;
2240 /* First check for one important special-case that the code below will
2241 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2242 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2243 we may be able to replace that destination with the destination of I3.
2244 This occurs in the common code where we compute both a quotient and
2245 remainder into a structure, in which case we want to do the computation
2246 directly into the structure to avoid register-register copies.
2248 Note that this case handles both multiple sets in I2 and also
2249 cases where I2 has a number of CLOBBER or PARALLELs.
2251 We make very conservative checks below and only try to handle the
2252 most common cases of this. For example, we only handle the case
2253 where I2 and I3 are adjacent to avoid making difficult register
2256 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2257 && REG_P (SET_SRC (PATTERN (i3)))
2258 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2259 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2260 && GET_CODE (PATTERN (i2)) == PARALLEL
2261 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2262 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2263 below would need to check what is inside (and reg_overlap_mentioned_p
2264 doesn't support those codes anyway). Don't allow those destinations;
2265 the resulting insn isn't likely to be recognized anyway. */
2266 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2267 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2268 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2269 SET_DEST (PATTERN (i3)))
2270 && next_real_insn (i2) == i3)
2272 rtx p2 = PATTERN (i2);
2274 /* Make sure that the destination of I3,
2275 which we are going to substitute into one output of I2,
2276 is not used within another output of I2. We must avoid making this:
2277 (parallel [(set (mem (reg 69)) ...)
2278 (set (reg 69) ...)])
2279 which is not well-defined as to order of actions.
2280 (Besides, reload can't handle output reloads for this.)
2282 The problem can also happen if the dest of I3 is a memory ref,
2283 if another dest in I2 is an indirect memory ref. */
2284 for (i = 0; i < XVECLEN (p2, 0); i++)
2285 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2286 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2287 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2288 SET_DEST (XVECEXP (p2, 0, i))))
2291 if (i == XVECLEN (p2, 0))
2292 for (i = 0; i < XVECLEN (p2, 0); i++)
2293 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2294 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2295 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2300 subst_low_luid = DF_INSN_LUID (i2);
2302 added_sets_2 = added_sets_1 = 0;
2303 i2dest = SET_SRC (PATTERN (i3));
2304 i2dest_killed = dead_or_set_p (i2, i2dest);
2306 /* Replace the dest in I2 with our dest and make the resulting
2307 insn the new pattern for I3. Then skip to where we
2308 validate the pattern. Everything was set up above. */
2309 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2310 SET_DEST (PATTERN (i3)));
2313 i3_subst_into_i2 = 1;
2314 goto validate_replacement;
2318 /* If I2 is setting a pseudo to a constant and I3 is setting some
2319 sub-part of it to another constant, merge them by making a new
2322 && (temp = single_set (i2)) != 0
2323 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2324 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2325 && GET_CODE (PATTERN (i3)) == SET
2326 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2327 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2328 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2330 rtx dest = SET_DEST (PATTERN (i3));
2334 if (GET_CODE (dest) == ZERO_EXTRACT)
2336 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2337 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2339 width = INTVAL (XEXP (dest, 1));
2340 offset = INTVAL (XEXP (dest, 2));
2341 dest = XEXP (dest, 0);
2342 if (BITS_BIG_ENDIAN)
2343 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2348 if (GET_CODE (dest) == STRICT_LOW_PART)
2349 dest = XEXP (dest, 0);
2350 width = GET_MODE_BITSIZE (GET_MODE (dest));
2356 /* If this is the low part, we're done. */
2357 if (subreg_lowpart_p (dest))
2359 /* Handle the case where inner is twice the size of outer. */
2360 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2361 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2362 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2363 /* Otherwise give up for now. */
2369 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2370 <= HOST_BITS_PER_WIDE_INT * 2))
2372 HOST_WIDE_INT mhi, ohi, ihi;
2373 HOST_WIDE_INT mlo, olo, ilo;
2374 rtx inner = SET_SRC (PATTERN (i3));
2375 rtx outer = SET_SRC (temp);
2377 if (GET_CODE (outer) == CONST_INT)
2379 olo = INTVAL (outer);
2380 ohi = olo < 0 ? -1 : 0;
2384 olo = CONST_DOUBLE_LOW (outer);
2385 ohi = CONST_DOUBLE_HIGH (outer);
2388 if (GET_CODE (inner) == CONST_INT)
2390 ilo = INTVAL (inner);
2391 ihi = ilo < 0 ? -1 : 0;
2395 ilo = CONST_DOUBLE_LOW (inner);
2396 ihi = CONST_DOUBLE_HIGH (inner);
2399 if (width < HOST_BITS_PER_WIDE_INT)
2401 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2404 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2406 mhi = ((unsigned HOST_WIDE_INT) 1
2407 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2419 if (offset >= HOST_BITS_PER_WIDE_INT)
2421 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2423 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2426 else if (offset > 0)
2428 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2429 >> (HOST_BITS_PER_WIDE_INT - offset));
2430 mlo = mlo << offset;
2431 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2432 >> (HOST_BITS_PER_WIDE_INT - offset));
2433 ilo = ilo << offset;
2436 olo = (olo & ~mlo) | ilo;
2437 ohi = (ohi & ~mhi) | ihi;
2441 subst_low_luid = DF_INSN_LUID (i2);
2442 added_sets_2 = added_sets_1 = 0;
2443 i2dest = SET_DEST (temp);
2444 i2dest_killed = dead_or_set_p (i2, i2dest);
2446 SUBST (SET_SRC (temp),
2447 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2449 newpat = PATTERN (i2);
2450 goto validate_replacement;
2455 /* If we have no I1 and I2 looks like:
2456 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2458 make up a dummy I1 that is
2461 (set (reg:CC X) (compare:CC Y (const_int 0)))
2463 (We can ignore any trailing CLOBBERs.)
2465 This undoes a previous combination and allows us to match a branch-and-
2468 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2469 && XVECLEN (PATTERN (i2), 0) >= 2
2470 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2471 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2473 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2474 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2475 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2476 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2477 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2478 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2480 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2481 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2486 /* We make I1 with the same INSN_UID as I2. This gives it
2487 the same DF_INSN_LUID for value tracking. Our fake I1 will
2488 never appear in the insn stream so giving it the same INSN_UID
2489 as I2 will not cause a problem. */
2491 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2492 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2493 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2495 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2496 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2497 SET_DEST (PATTERN (i1)));
2502 /* Verify that I2 and I1 are valid for combining. */
2503 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2504 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2510 /* Record whether I2DEST is used in I2SRC and similarly for the other
2511 cases. Knowing this will help in register status updating below. */
2512 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2513 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2514 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2515 i2dest_killed = dead_or_set_p (i2, i2dest);
2516 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2518 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2520 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2522 /* Ensure that I3's pattern can be the destination of combines. */
2523 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2524 i1 && i2dest_in_i1src && i1_feeds_i3,
2531 /* See if any of the insns is a MULT operation. Unless one is, we will
2532 reject a combination that is, since it must be slower. Be conservative
2534 if (GET_CODE (i2src) == MULT
2535 || (i1 != 0 && GET_CODE (i1src) == MULT)
2536 || (GET_CODE (PATTERN (i3)) == SET
2537 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2540 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2541 We used to do this EXCEPT in one case: I3 has a post-inc in an
2542 output operand. However, that exception can give rise to insns like
2544 which is a famous insn on the PDP-11 where the value of r3 used as the
2545 source was model-dependent. Avoid this sort of thing. */
2548 if (!(GET_CODE (PATTERN (i3)) == SET
2549 && REG_P (SET_SRC (PATTERN (i3)))
2550 && MEM_P (SET_DEST (PATTERN (i3)))
2551 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2552 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2553 /* It's not the exception. */
2556 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2557 if (REG_NOTE_KIND (link) == REG_INC
2558 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2560 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2567 /* See if the SETs in I1 or I2 need to be kept around in the merged
2568 instruction: whenever the value set there is still needed past I3.
2569 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2571 For the SET in I1, we have two cases: If I1 and I2 independently
2572 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2573 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2574 in I1 needs to be kept around unless I1DEST dies or is set in either
2575 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2576 I1DEST. If so, we know I1 feeds into I2. */
2578 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2581 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2582 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2584 /* If the set in I2 needs to be kept around, we must make a copy of
2585 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2586 PATTERN (I2), we are only substituting for the original I1DEST, not into
2587 an already-substituted copy. This also prevents making self-referential
2588 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2593 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2594 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2596 i2pat = copy_rtx (PATTERN (i2));
2601 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2602 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2604 i1pat = copy_rtx (PATTERN (i1));
2609 /* Substitute in the latest insn for the regs set by the earlier ones. */
2611 maxreg = max_reg_num ();
2616 /* Many machines that don't use CC0 have insns that can both perform an
2617 arithmetic operation and set the condition code. These operations will
2618 be represented as a PARALLEL with the first element of the vector
2619 being a COMPARE of an arithmetic operation with the constant zero.
2620 The second element of the vector will set some pseudo to the result
2621 of the same arithmetic operation. If we simplify the COMPARE, we won't
2622 match such a pattern and so will generate an extra insn. Here we test
2623 for this case, where both the comparison and the operation result are
2624 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2625 I2SRC. Later we will make the PARALLEL that contains I2. */
2627 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2628 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2629 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2630 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2632 #ifdef SELECT_CC_MODE
2634 enum machine_mode compare_mode;
2637 newpat = PATTERN (i3);
2638 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2642 #ifdef SELECT_CC_MODE
2643 /* See if a COMPARE with the operand we substituted in should be done
2644 with the mode that is currently being used. If not, do the same
2645 processing we do in `subst' for a SET; namely, if the destination
2646 is used only once, try to replace it with a register of the proper
2647 mode and also replace the COMPARE. */
2648 if (undobuf.other_insn == 0
2649 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2650 &undobuf.other_insn))
2651 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2653 != GET_MODE (SET_DEST (newpat))))
2655 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2658 unsigned int regno = REGNO (SET_DEST (newpat));
2661 if (regno < FIRST_PSEUDO_REGISTER)
2662 new_dest = gen_rtx_REG (compare_mode, regno);
2665 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2666 new_dest = regno_reg_rtx[regno];
2669 SUBST (SET_DEST (newpat), new_dest);
2670 SUBST (XEXP (*cc_use, 0), new_dest);
2671 SUBST (SET_SRC (newpat),
2672 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2675 undobuf.other_insn = 0;
2682 /* It is possible that the source of I2 or I1 may be performing
2683 an unneeded operation, such as a ZERO_EXTEND of something
2684 that is known to have the high part zero. Handle that case
2685 by letting subst look at the innermost one of them.
2687 Another way to do this would be to have a function that tries
2688 to simplify a single insn instead of merging two or more
2689 insns. We don't do this because of the potential of infinite
2690 loops and because of the potential extra memory required.
2691 However, doing it the way we are is a bit of a kludge and
2692 doesn't catch all cases.
2694 But only do this if -fexpensive-optimizations since it slows
2695 things down and doesn't usually win.
2697 This is not done in the COMPARE case above because the
2698 unmodified I2PAT is used in the PARALLEL and so a pattern
2699 with a modified I2SRC would not match. */
2701 if (flag_expensive_optimizations)
2703 /* Pass pc_rtx so no substitutions are done, just
2707 subst_low_luid = DF_INSN_LUID (i1);
2708 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2712 subst_low_luid = DF_INSN_LUID (i2);
2713 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2717 n_occurrences = 0; /* `subst' counts here */
2719 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2720 need to make a unique copy of I2SRC each time we substitute it
2721 to avoid self-referential rtl. */
2723 subst_low_luid = DF_INSN_LUID (i2);
2724 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2725 ! i1_feeds_i3 && i1dest_in_i1src);
2728 /* Record whether i2's body now appears within i3's body. */
2729 i2_is_used = n_occurrences;
2732 /* If we already got a failure, don't try to do more. Otherwise,
2733 try to substitute in I1 if we have it. */
2735 if (i1 && GET_CODE (newpat) != CLOBBER)
2737 /* Check that an autoincrement side-effect on I1 has not been lost.
2738 This happens if I1DEST is mentioned in I2 and dies there, and
2739 has disappeared from the new pattern. */
2740 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2742 && dead_or_set_p (i2, i1dest)
2743 && !reg_overlap_mentioned_p (i1dest, newpat))
2744 /* Before we can do this substitution, we must redo the test done
2745 above (see detailed comments there) that ensures that I1DEST
2746 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2747 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2754 subst_low_luid = DF_INSN_LUID (i1);
2755 newpat = subst (newpat, i1dest, i1src, 0, 0);
2759 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2760 to count all the ways that I2SRC and I1SRC can be used. */
2761 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2762 && i2_is_used + added_sets_2 > 1)
2763 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2764 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2766 /* Fail if we tried to make a new register. */
2767 || max_reg_num () != maxreg
2768 /* Fail if we couldn't do something and have a CLOBBER. */
2769 || GET_CODE (newpat) == CLOBBER
2770 /* Fail if this new pattern is a MULT and we didn't have one before
2771 at the outer level. */
2772 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2779 /* If the actions of the earlier insns must be kept
2780 in addition to substituting them into the latest one,
2781 we must make a new PARALLEL for the latest insn
2782 to hold additional the SETs. */
2784 if (added_sets_1 || added_sets_2)
2788 if (GET_CODE (newpat) == PARALLEL)
2790 rtvec old = XVEC (newpat, 0);
2791 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2792 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2793 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2794 sizeof (old->elem[0]) * old->num_elem);
2799 total_sets = 1 + added_sets_1 + added_sets_2;
2800 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2801 XVECEXP (newpat, 0, 0) = old;
2805 XVECEXP (newpat, 0, --total_sets) = i1pat;
2809 /* If there is no I1, use I2's body as is. We used to also not do
2810 the subst call below if I2 was substituted into I3,
2811 but that could lose a simplification. */
2813 XVECEXP (newpat, 0, --total_sets) = i2pat;
2815 /* See comment where i2pat is assigned. */
2816 XVECEXP (newpat, 0, --total_sets)
2817 = subst (i2pat, i1dest, i1src, 0, 0);
2821 /* We come here when we are replacing a destination in I2 with the
2822 destination of I3. */
2823 validate_replacement:
2825 /* Note which hard regs this insn has as inputs. */
2826 mark_used_regs_combine (newpat);
2828 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2829 consider splitting this pattern, we might need these clobbers. */
2830 if (i1 && GET_CODE (newpat) == PARALLEL
2831 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2833 int len = XVECLEN (newpat, 0);
2835 newpat_vec_with_clobbers = rtvec_alloc (len);
2836 for (i = 0; i < len; i++)
2837 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2840 /* Is the result of combination a valid instruction? */
2841 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2843 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2844 the second SET's destination is a register that is unused and isn't
2845 marked as an instruction that might trap in an EH region. In that case,
2846 we just need the first SET. This can occur when simplifying a divmod
2847 insn. We *must* test for this case here because the code below that
2848 splits two independent SETs doesn't handle this case correctly when it
2849 updates the register status.
2851 It's pointless doing this if we originally had two sets, one from
2852 i3, and one from i2. Combining then splitting the parallel results
2853 in the original i2 again plus an invalid insn (which we delete).
2854 The net effect is only to move instructions around, which makes
2855 debug info less accurate.
2857 Also check the case where the first SET's destination is unused.
2858 That would not cause incorrect code, but does cause an unneeded
2861 if (insn_code_number < 0
2862 && !(added_sets_2 && i1 == 0)
2863 && GET_CODE (newpat) == PARALLEL
2864 && XVECLEN (newpat, 0) == 2
2865 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2866 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2867 && asm_noperands (newpat) < 0)
2869 rtx set0 = XVECEXP (newpat, 0, 0);
2870 rtx set1 = XVECEXP (newpat, 0, 1);
2873 if (((REG_P (SET_DEST (set1))
2874 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2875 || (GET_CODE (SET_DEST (set1)) == SUBREG
2876 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2877 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2878 || INTVAL (XEXP (note, 0)) <= 0)
2879 && ! side_effects_p (SET_SRC (set1)))
2882 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2885 else if (((REG_P (SET_DEST (set0))
2886 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2887 || (GET_CODE (SET_DEST (set0)) == SUBREG
2888 && find_reg_note (i3, REG_UNUSED,
2889 SUBREG_REG (SET_DEST (set0)))))
2890 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2891 || INTVAL (XEXP (note, 0)) <= 0)
2892 && ! side_effects_p (SET_SRC (set0)))
2895 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2897 if (insn_code_number >= 0)
2899 /* If we will be able to accept this, we have made a
2900 change to the destination of I3. This requires us to
2901 do a few adjustments. */
2903 PATTERN (i3) = newpat;
2904 adjust_for_new_dest (i3);
2909 /* If we were combining three insns and the result is a simple SET
2910 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2911 insns. There are two ways to do this. It can be split using a
2912 machine-specific method (like when you have an addition of a large
2913 constant) or by combine in the function find_split_point. */
2915 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2916 && asm_noperands (newpat) < 0)
2918 rtx parallel, m_split, *split;
2920 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2921 use I2DEST as a scratch register will help. In the latter case,
2922 convert I2DEST to the mode of the source of NEWPAT if we can. */
2924 m_split = combine_split_insns (newpat, i3);
2926 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2927 inputs of NEWPAT. */
2929 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2930 possible to try that as a scratch reg. This would require adding
2931 more code to make it work though. */
2933 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2935 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2937 /* First try to split using the original register as a
2938 scratch register. */
2939 parallel = gen_rtx_PARALLEL (VOIDmode,
2940 gen_rtvec (2, newpat,
2941 gen_rtx_CLOBBER (VOIDmode,
2943 m_split = combine_split_insns (parallel, i3);
2945 /* If that didn't work, try changing the mode of I2DEST if
2948 && new_mode != GET_MODE (i2dest)
2949 && new_mode != VOIDmode
2950 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2952 enum machine_mode old_mode = GET_MODE (i2dest);
2955 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2956 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2959 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2960 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2963 parallel = (gen_rtx_PARALLEL
2965 gen_rtvec (2, newpat,
2966 gen_rtx_CLOBBER (VOIDmode,
2968 m_split = combine_split_insns (parallel, i3);
2971 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2975 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
2976 buf = undobuf.undos;
2977 undobuf.undos = buf->next;
2978 buf->next = undobuf.frees;
2979 undobuf.frees = buf;
2984 /* If recog_for_combine has discarded clobbers, try to use them
2985 again for the split. */
2986 if (m_split == 0 && newpat_vec_with_clobbers)
2988 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
2989 m_split = combine_split_insns (parallel, i3);
2992 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2994 m_split = PATTERN (m_split);
2995 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2996 if (insn_code_number >= 0)
2999 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3000 && (next_real_insn (i2) == i3
3001 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3004 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3005 newi2pat = PATTERN (m_split);
3007 i3set = single_set (NEXT_INSN (m_split));
3008 i2set = single_set (m_split);
3010 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3012 /* If I2 or I3 has multiple SETs, we won't know how to track
3013 register status, so don't use these insns. If I2's destination
3014 is used between I2 and I3, we also can't use these insns. */
3016 if (i2_code_number >= 0 && i2set && i3set
3017 && (next_real_insn (i2) == i3
3018 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3019 insn_code_number = recog_for_combine (&newi3pat, i3,
3021 if (insn_code_number >= 0)
3024 /* It is possible that both insns now set the destination of I3.
3025 If so, we must show an extra use of it. */
3027 if (insn_code_number >= 0)
3029 rtx new_i3_dest = SET_DEST (i3set);
3030 rtx new_i2_dest = SET_DEST (i2set);
3032 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3033 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3034 || GET_CODE (new_i3_dest) == SUBREG)
3035 new_i3_dest = XEXP (new_i3_dest, 0);
3037 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3038 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3039 || GET_CODE (new_i2_dest) == SUBREG)
3040 new_i2_dest = XEXP (new_i2_dest, 0);
3042 if (REG_P (new_i3_dest)
3043 && REG_P (new_i2_dest)
3044 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3045 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3049 /* If we can split it and use I2DEST, go ahead and see if that
3050 helps things be recognized. Verify that none of the registers
3051 are set between I2 and I3. */
3052 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3056 /* We need I2DEST in the proper mode. If it is a hard register
3057 or the only use of a pseudo, we can change its mode.
3058 Make sure we don't change a hard register to have a mode that
3059 isn't valid for it, or change the number of registers. */
3060 && (GET_MODE (*split) == GET_MODE (i2dest)
3061 || GET_MODE (*split) == VOIDmode
3062 || can_change_dest_mode (i2dest, added_sets_2,
3064 && (next_real_insn (i2) == i3
3065 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3066 /* We can't overwrite I2DEST if its value is still used by
3068 && ! reg_referenced_p (i2dest, newpat))
3070 rtx newdest = i2dest;
3071 enum rtx_code split_code = GET_CODE (*split);
3072 enum machine_mode split_mode = GET_MODE (*split);
3073 bool subst_done = false;
3074 newi2pat = NULL_RTX;
3076 /* Get NEWDEST as a register in the proper mode. We have already
3077 validated that we can do this. */
3078 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3080 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3081 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3084 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3085 newdest = regno_reg_rtx[REGNO (i2dest)];
3089 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3090 an ASHIFT. This can occur if it was inside a PLUS and hence
3091 appeared to be a memory address. This is a kludge. */
3092 if (split_code == MULT
3093 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3094 && INTVAL (XEXP (*split, 1)) > 0
3095 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3097 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3098 XEXP (*split, 0), GEN_INT (i)));
3099 /* Update split_code because we may not have a multiply
3101 split_code = GET_CODE (*split);
3104 #ifdef INSN_SCHEDULING
3105 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3106 be written as a ZERO_EXTEND. */
3107 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3109 #ifdef LOAD_EXTEND_OP
3110 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3111 what it really is. */
3112 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3114 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3115 SUBREG_REG (*split)));
3118 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3119 SUBREG_REG (*split)));
3123 /* Attempt to split binary operators using arithmetic identities. */
3124 if (BINARY_P (SET_SRC (newpat))
3125 && split_mode == GET_MODE (SET_SRC (newpat))
3126 && ! side_effects_p (SET_SRC (newpat)))
3128 rtx setsrc = SET_SRC (newpat);
3129 enum machine_mode mode = GET_MODE (setsrc);
3130 enum rtx_code code = GET_CODE (setsrc);
3131 rtx src_op0 = XEXP (setsrc, 0);
3132 rtx src_op1 = XEXP (setsrc, 1);
3134 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3135 if (rtx_equal_p (src_op0, src_op1))
3137 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3138 SUBST (XEXP (setsrc, 0), newdest);
3139 SUBST (XEXP (setsrc, 1), newdest);
3142 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3143 else if ((code == PLUS || code == MULT)
3144 && GET_CODE (src_op0) == code
3145 && GET_CODE (XEXP (src_op0, 0)) == code
3146 && (INTEGRAL_MODE_P (mode)
3147 || (FLOAT_MODE_P (mode)
3148 && flag_unsafe_math_optimizations)))
3150 rtx p = XEXP (XEXP (src_op0, 0), 0);
3151 rtx q = XEXP (XEXP (src_op0, 0), 1);
3152 rtx r = XEXP (src_op0, 1);
3155 /* Split both "((X op Y) op X) op Y" and
3156 "((X op Y) op Y) op X" as "T op T" where T is
3158 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3159 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3161 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3163 SUBST (XEXP (setsrc, 0), newdest);
3164 SUBST (XEXP (setsrc, 1), newdest);
3167 /* Split "((X op X) op Y) op Y)" as "T op T" where
3169 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3171 rtx tmp = simplify_gen_binary (code, mode, p, r);
3172 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3173 SUBST (XEXP (setsrc, 0), newdest);
3174 SUBST (XEXP (setsrc, 1), newdest);
3182 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3183 SUBST (*split, newdest);
3186 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3188 /* recog_for_combine might have added CLOBBERs to newi2pat.
3189 Make sure NEWPAT does not depend on the clobbered regs. */
3190 if (GET_CODE (newi2pat) == PARALLEL)
3191 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3192 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3194 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3195 if (reg_overlap_mentioned_p (reg, newpat))
3202 /* If the split point was a MULT and we didn't have one before,
3203 don't use one now. */
3204 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3205 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3209 /* Check for a case where we loaded from memory in a narrow mode and
3210 then sign extended it, but we need both registers. In that case,
3211 we have a PARALLEL with both loads from the same memory location.
3212 We can split this into a load from memory followed by a register-register
3213 copy. This saves at least one insn, more if register allocation can
3216 We cannot do this if the destination of the first assignment is a
3217 condition code register or cc0. We eliminate this case by making sure
3218 the SET_DEST and SET_SRC have the same mode.
3220 We cannot do this if the destination of the second assignment is
3221 a register that we have already assumed is zero-extended. Similarly
3222 for a SUBREG of such a register. */
3224 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3225 && GET_CODE (newpat) == PARALLEL
3226 && XVECLEN (newpat, 0) == 2
3227 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3228 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3229 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3230 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3231 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3232 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3233 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3234 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3236 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3237 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3238 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3240 && VEC_index (reg_stat_type, reg_stat,
3241 REGNO (temp))->nonzero_bits != 0
3242 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3243 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3244 && (VEC_index (reg_stat_type, reg_stat,
3245 REGNO (temp))->nonzero_bits
3246 != GET_MODE_MASK (word_mode))))
3247 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3248 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3250 && VEC_index (reg_stat_type, reg_stat,
3251 REGNO (temp))->nonzero_bits != 0
3252 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3253 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3254 && (VEC_index (reg_stat_type, reg_stat,
3255 REGNO (temp))->nonzero_bits
3256 != GET_MODE_MASK (word_mode)))))
3257 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3258 SET_SRC (XVECEXP (newpat, 0, 1)))
3259 && ! find_reg_note (i3, REG_UNUSED,
3260 SET_DEST (XVECEXP (newpat, 0, 0))))
3264 newi2pat = XVECEXP (newpat, 0, 0);
3265 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3266 newpat = XVECEXP (newpat, 0, 1);
3267 SUBST (SET_SRC (newpat),
3268 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3269 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3271 if (i2_code_number >= 0)
3272 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3274 if (insn_code_number >= 0)
3278 /* Similarly, check for a case where we have a PARALLEL of two independent
3279 SETs but we started with three insns. In this case, we can do the sets
3280 as two separate insns. This case occurs when some SET allows two
3281 other insns to combine, but the destination of that SET is still live. */
3283 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3284 && GET_CODE (newpat) == PARALLEL
3285 && XVECLEN (newpat, 0) == 2
3286 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3287 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3288 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3289 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3290 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3291 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3292 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3294 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3295 XVECEXP (newpat, 0, 0))
3296 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3297 XVECEXP (newpat, 0, 1))
3298 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3299 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3301 /* We cannot split the parallel into two sets if both sets
3303 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3304 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3308 /* Normally, it doesn't matter which of the two is done first,
3309 but it does if one references cc0. In that case, it has to
3312 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3314 newi2pat = XVECEXP (newpat, 0, 0);
3315 newpat = XVECEXP (newpat, 0, 1);
3320 newi2pat = XVECEXP (newpat, 0, 1);
3321 newpat = XVECEXP (newpat, 0, 0);
3324 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3326 if (i2_code_number >= 0)
3327 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3330 /* If it still isn't recognized, fail and change things back the way they
3332 if ((insn_code_number < 0
3333 /* Is the result a reasonable ASM_OPERANDS? */
3334 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3340 /* If we had to change another insn, make sure it is valid also. */
3341 if (undobuf.other_insn)
3343 CLEAR_HARD_REG_SET (newpat_used_regs);
3345 other_pat = PATTERN (undobuf.other_insn);
3346 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3349 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3357 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3358 they are adjacent to each other or not. */
3360 rtx p = prev_nonnote_insn (i3);
3361 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3362 && sets_cc0_p (newi2pat))
3370 /* Only allow this combination if insn_rtx_costs reports that the
3371 replacement instructions are cheaper than the originals. */
3372 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3378 /* We now know that we can do this combination. Merge the insns and
3379 update the status of registers and LOG_LINKS. */
3381 if (undobuf.other_insn)
3385 PATTERN (undobuf.other_insn) = other_pat;
3387 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3388 are still valid. Then add any non-duplicate notes added by
3389 recog_for_combine. */
3390 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3392 next = XEXP (note, 1);
3394 if (REG_NOTE_KIND (note) == REG_UNUSED
3395 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3396 remove_note (undobuf.other_insn, note);
3399 distribute_notes (new_other_notes, undobuf.other_insn,
3400 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3409 /* I3 now uses what used to be its destination and which is now
3410 I2's destination. This requires us to do a few adjustments. */
3411 PATTERN (i3) = newpat;
3412 adjust_for_new_dest (i3);
3414 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3417 However, some later insn might be using I2's dest and have
3418 a LOG_LINK pointing at I3. We must remove this link.
3419 The simplest way to remove the link is to point it at I1,
3420 which we know will be a NOTE. */
3422 /* newi2pat is usually a SET here; however, recog_for_combine might
3423 have added some clobbers. */
3424 if (GET_CODE (newi2pat) == PARALLEL)
3425 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3427 ni2dest = SET_DEST (newi2pat);
3429 for (insn = NEXT_INSN (i3);
3430 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3431 || insn != BB_HEAD (this_basic_block->next_bb));
3432 insn = NEXT_INSN (insn))
3434 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3436 for (link = LOG_LINKS (insn); link;
3437 link = XEXP (link, 1))
3438 if (XEXP (link, 0) == i3)
3439 XEXP (link, 0) = i1;
3447 rtx i3notes, i2notes, i1notes = 0;
3448 rtx i3links, i2links, i1links = 0;
3451 /* Compute which registers we expect to eliminate. newi2pat may be setting
3452 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3453 same as i3dest, in which case newi2pat may be setting i1dest. */
3454 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3455 || i2dest_in_i2src || i2dest_in_i1src
3458 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3459 || (newi2pat && reg_set_p (i1dest, newi2pat))
3463 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3465 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3466 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3468 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3470 /* Ensure that we do not have something that should not be shared but
3471 occurs multiple times in the new insns. Check this by first
3472 resetting all the `used' flags and then copying anything is shared. */
3474 reset_used_flags (i3notes);
3475 reset_used_flags (i2notes);
3476 reset_used_flags (i1notes);
3477 reset_used_flags (newpat);
3478 reset_used_flags (newi2pat);
3479 if (undobuf.other_insn)
3480 reset_used_flags (PATTERN (undobuf.other_insn));
3482 i3notes = copy_rtx_if_shared (i3notes);
3483 i2notes = copy_rtx_if_shared (i2notes);
3484 i1notes = copy_rtx_if_shared (i1notes);
3485 newpat = copy_rtx_if_shared (newpat);
3486 newi2pat = copy_rtx_if_shared (newi2pat);
3487 if (undobuf.other_insn)
3488 reset_used_flags (PATTERN (undobuf.other_insn));
3490 INSN_CODE (i3) = insn_code_number;
3491 PATTERN (i3) = newpat;
3493 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3495 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3497 reset_used_flags (call_usage);
3498 call_usage = copy_rtx (call_usage);
3501 replace_rtx (call_usage, i2dest, i2src);
3504 replace_rtx (call_usage, i1dest, i1src);
3506 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3509 if (undobuf.other_insn)
3510 INSN_CODE (undobuf.other_insn) = other_code_number;
3512 /* We had one special case above where I2 had more than one set and
3513 we replaced a destination of one of those sets with the destination
3514 of I3. In that case, we have to update LOG_LINKS of insns later
3515 in this basic block. Note that this (expensive) case is rare.
3517 Also, in this case, we must pretend that all REG_NOTEs for I2
3518 actually came from I3, so that REG_UNUSED notes from I2 will be
3519 properly handled. */
3521 if (i3_subst_into_i2)
3523 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3524 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3525 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3526 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3527 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3528 && ! find_reg_note (i2, REG_UNUSED,
3529 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3530 for (temp = NEXT_INSN (i2);
3531 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3532 || BB_HEAD (this_basic_block) != temp);
3533 temp = NEXT_INSN (temp))
3534 if (temp != i3 && INSN_P (temp))
3535 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3536 if (XEXP (link, 0) == i2)
3537 XEXP (link, 0) = i3;
3542 while (XEXP (link, 1))
3543 link = XEXP (link, 1);
3544 XEXP (link, 1) = i2notes;
3558 INSN_CODE (i2) = i2_code_number;
3559 PATTERN (i2) = newi2pat;
3562 SET_INSN_DELETED (i2);
3568 SET_INSN_DELETED (i1);
3571 /* Get death notes for everything that is now used in either I3 or
3572 I2 and used to die in a previous insn. If we built two new
3573 patterns, move from I1 to I2 then I2 to I3 so that we get the
3574 proper movement on registers that I2 modifies. */
3578 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3579 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3582 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3585 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3587 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3590 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3593 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3596 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3599 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3600 know these are REG_UNUSED and want them to go to the desired insn,
3601 so we always pass it as i3. */
3603 if (newi2pat && new_i2_notes)
3604 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3607 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3609 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3610 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3611 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3612 in that case, it might delete I2. Similarly for I2 and I1.
3613 Show an additional death due to the REG_DEAD note we make here. If
3614 we discard it in distribute_notes, we will decrement it again. */
3618 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3619 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3621 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3623 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3625 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3629 if (i2dest_in_i2src)
3631 if (newi2pat && reg_set_p (i2dest, newi2pat))
3632 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3633 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3635 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3636 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3637 NULL_RTX, NULL_RTX);
3640 if (i1dest_in_i1src)
3642 if (newi2pat && reg_set_p (i1dest, newi2pat))
3643 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3644 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3646 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3647 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3648 NULL_RTX, NULL_RTX);
3651 distribute_links (i3links);
3652 distribute_links (i2links);
3653 distribute_links (i1links);
3658 rtx i2_insn = 0, i2_val = 0, set;
3660 /* The insn that used to set this register doesn't exist, and
3661 this life of the register may not exist either. See if one of
3662 I3's links points to an insn that sets I2DEST. If it does,
3663 that is now the last known value for I2DEST. If we don't update
3664 this and I2 set the register to a value that depended on its old
3665 contents, we will get confused. If this insn is used, thing
3666 will be set correctly in combine_instructions. */
3668 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3669 if ((set = single_set (XEXP (link, 0))) != 0
3670 && rtx_equal_p (i2dest, SET_DEST (set)))
3671 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3673 record_value_for_reg (i2dest, i2_insn, i2_val);
3675 /* If the reg formerly set in I2 died only once and that was in I3,
3676 zero its use count so it won't make `reload' do any work. */
3678 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3679 && ! i2dest_in_i2src)
3681 regno = REGNO (i2dest);
3682 INC_REG_N_SETS (regno, -1);
3686 if (i1 && REG_P (i1dest))
3689 rtx i1_insn = 0, i1_val = 0, set;
3691 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3692 if ((set = single_set (XEXP (link, 0))) != 0
3693 && rtx_equal_p (i1dest, SET_DEST (set)))
3694 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3696 record_value_for_reg (i1dest, i1_insn, i1_val);
3698 regno = REGNO (i1dest);
3699 if (! added_sets_1 && ! i1dest_in_i1src)
3700 INC_REG_N_SETS (regno, -1);
3703 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3704 been made to this insn. The order of
3705 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3706 can affect nonzero_bits of newpat */
3708 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3709 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3711 /* Set new_direct_jump_p if a new return or simple jump instruction
3714 If I3 is now an unconditional jump, ensure that it has a
3715 BARRIER following it since it may have initially been a
3716 conditional jump. It may also be the last nonnote insn. */
3718 if (returnjump_p (i3) || any_uncondjump_p (i3))
3720 *new_direct_jump_p = 1;
3721 mark_jump_label (PATTERN (i3), i3, 0);
3723 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3724 || !BARRIER_P (temp))
3725 emit_barrier_after (i3);
3728 if (undobuf.other_insn != NULL_RTX
3729 && (returnjump_p (undobuf.other_insn)
3730 || any_uncondjump_p (undobuf.other_insn)))
3732 *new_direct_jump_p = 1;
3734 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3735 || !BARRIER_P (temp))
3736 emit_barrier_after (undobuf.other_insn);
3739 /* An NOOP jump does not need barrier, but it does need cleaning up
3741 if (GET_CODE (newpat) == SET
3742 && SET_SRC (newpat) == pc_rtx
3743 && SET_DEST (newpat) == pc_rtx)
3744 *new_direct_jump_p = 1;
3747 if (undobuf.other_insn != NULL_RTX)
3751 fprintf (dump_file, "modifying other_insn ");
3752 dump_insn_slim (dump_file, undobuf.other_insn);
3754 df_insn_rescan (undobuf.other_insn);
3757 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3761 fprintf (dump_file, "modifying insn i1 ");
3762 dump_insn_slim (dump_file, i1);
3764 df_insn_rescan (i1);
3767 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3771 fprintf (dump_file, "modifying insn i2 ");
3772 dump_insn_slim (dump_file, i2);
3774 df_insn_rescan (i2);
3777 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3781 fprintf (dump_file, "modifying insn i3 ");
3782 dump_insn_slim (dump_file, i3);
3784 df_insn_rescan (i3);
3787 combine_successes++;
3790 if (added_links_insn
3791 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3792 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3793 return added_links_insn;
3795 return newi2pat ? i2 : i3;
3798 /* Undo all the modifications recorded in undobuf. */
3803 struct undo *undo, *next;
3805 for (undo = undobuf.undos; undo; undo = next)
3811 *undo->where.r = undo->old_contents.r;
3814 *undo->where.i = undo->old_contents.i;
3817 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3823 undo->next = undobuf.frees;
3824 undobuf.frees = undo;
3830 /* We've committed to accepting the changes we made. Move all
3831 of the undos to the free list. */
3836 struct undo *undo, *next;
3838 for (undo = undobuf.undos; undo; undo = next)
3841 undo->next = undobuf.frees;
3842 undobuf.frees = undo;
3847 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3848 where we have an arithmetic expression and return that point. LOC will
3851 try_combine will call this function to see if an insn can be split into
3855 find_split_point (rtx *loc, rtx insn)
3858 enum rtx_code code = GET_CODE (x);
3860 unsigned HOST_WIDE_INT len = 0;
3861 HOST_WIDE_INT pos = 0;
3863 rtx inner = NULL_RTX;
3865 /* First special-case some codes. */
3869 #ifdef INSN_SCHEDULING
3870 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3872 if (MEM_P (SUBREG_REG (x)))
3875 return find_split_point (&SUBREG_REG (x), insn);
3879 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3880 using LO_SUM and HIGH. */
3881 if (GET_CODE (XEXP (x, 0)) == CONST
3882 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3885 gen_rtx_LO_SUM (Pmode,
3886 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3888 return &XEXP (XEXP (x, 0), 0);
3892 /* If we have a PLUS whose second operand is a constant and the
3893 address is not valid, perhaps will can split it up using
3894 the machine-specific way to split large constants. We use
3895 the first pseudo-reg (one of the virtual regs) as a placeholder;
3896 it will not remain in the result. */
3897 if (GET_CODE (XEXP (x, 0)) == PLUS
3898 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3899 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3901 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3902 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3906 /* This should have produced two insns, each of which sets our
3907 placeholder. If the source of the second is a valid address,
3908 we can make put both sources together and make a split point
3912 && NEXT_INSN (seq) != NULL_RTX
3913 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3914 && NONJUMP_INSN_P (seq)
3915 && GET_CODE (PATTERN (seq)) == SET
3916 && SET_DEST (PATTERN (seq)) == reg
3917 && ! reg_mentioned_p (reg,
3918 SET_SRC (PATTERN (seq)))
3919 && NONJUMP_INSN_P (NEXT_INSN (seq))
3920 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3921 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3922 && memory_address_p (GET_MODE (x),
3923 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3925 rtx src1 = SET_SRC (PATTERN (seq));
3926 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3928 /* Replace the placeholder in SRC2 with SRC1. If we can
3929 find where in SRC2 it was placed, that can become our
3930 split point and we can replace this address with SRC2.
3931 Just try two obvious places. */
3933 src2 = replace_rtx (src2, reg, src1);
3935 if (XEXP (src2, 0) == src1)
3936 split = &XEXP (src2, 0);
3937 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3938 && XEXP (XEXP (src2, 0), 0) == src1)
3939 split = &XEXP (XEXP (src2, 0), 0);
3943 SUBST (XEXP (x, 0), src2);
3948 /* If that didn't work, perhaps the first operand is complex and
3949 needs to be computed separately, so make a split point there.
3950 This will occur on machines that just support REG + CONST
3951 and have a constant moved through some previous computation. */
3953 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3954 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3955 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3956 return &XEXP (XEXP (x, 0), 0);
3959 /* If we have a PLUS whose first operand is complex, try computing it
3960 separately by making a split there. */
3961 if (GET_CODE (XEXP (x, 0)) == PLUS
3962 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3963 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3964 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3965 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3966 return &XEXP (XEXP (x, 0), 0);
3971 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3972 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3973 we need to put the operand into a register. So split at that
3976 if (SET_DEST (x) == cc0_rtx
3977 && GET_CODE (SET_SRC (x)) != COMPARE
3978 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3979 && !OBJECT_P (SET_SRC (x))
3980 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3981 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3982 return &SET_SRC (x);
3985 /* See if we can split SET_SRC as it stands. */
3986 split = find_split_point (&SET_SRC (x), insn);
3987 if (split && split != &SET_SRC (x))
3990 /* See if we can split SET_DEST as it stands. */
3991 split = find_split_point (&SET_DEST (x), insn);
3992 if (split && split != &SET_DEST (x))
3995 /* See if this is a bitfield assignment with everything constant. If
3996 so, this is an IOR of an AND, so split it into that. */
3997 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3998 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3999 <= HOST_BITS_PER_WIDE_INT)
4000 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
4001 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
4002 && GET_CODE (SET_SRC (x)) == CONST_INT
4003 && ((INTVAL (XEXP (SET_DEST (x), 1))
4004 + INTVAL (XEXP (SET_DEST (x), 2)))
4005 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4006 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4008 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4009 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4010 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4011 rtx dest = XEXP (SET_DEST (x), 0);
4012 enum machine_mode mode = GET_MODE (dest);
4013 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4016 if (BITS_BIG_ENDIAN)
4017 pos = GET_MODE_BITSIZE (mode) - len - pos;
4019 or_mask = gen_int_mode (src << pos, mode);
4022 simplify_gen_binary (IOR, mode, dest, or_mask));
4025 rtx negmask = gen_int_mode (~(mask << pos), mode);
4027 simplify_gen_binary (IOR, mode,
4028 simplify_gen_binary (AND, mode,
4033 SUBST (SET_DEST (x), dest);
4035 split = find_split_point (&SET_SRC (x), insn);
4036 if (split && split != &SET_SRC (x))
4040 /* Otherwise, see if this is an operation that we can split into two.
4041 If so, try to split that. */
4042 code = GET_CODE (SET_SRC (x));
4047 /* If we are AND'ing with a large constant that is only a single
4048 bit and the result is only being used in a context where we
4049 need to know if it is zero or nonzero, replace it with a bit
4050 extraction. This will avoid the large constant, which might
4051 have taken more than one insn to make. If the constant were
4052 not a valid argument to the AND but took only one insn to make,
4053 this is no worse, but if it took more than one insn, it will
4056 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4057 && REG_P (XEXP (SET_SRC (x), 0))
4058 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4059 && REG_P (SET_DEST (x))
4060 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4061 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4062 && XEXP (*split, 0) == SET_DEST (x)
4063 && XEXP (*split, 1) == const0_rtx)
4065 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4066 XEXP (SET_SRC (x), 0),
4067 pos, NULL_RTX, 1, 1, 0, 0);
4068 if (extraction != 0)
4070 SUBST (SET_SRC (x), extraction);
4071 return find_split_point (loc, insn);
4077 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4078 is known to be on, this can be converted into a NEG of a shift. */
4079 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4080 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4081 && 1 <= (pos = exact_log2
4082 (nonzero_bits (XEXP (SET_SRC (x), 0),
4083 GET_MODE (XEXP (SET_SRC (x), 0))))))
4085 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4089 gen_rtx_LSHIFTRT (mode,
4090 XEXP (SET_SRC (x), 0),
4093 split = find_split_point (&SET_SRC (x), insn);
4094 if (split && split != &SET_SRC (x))
4100 inner = XEXP (SET_SRC (x), 0);
4102 /* We can't optimize if either mode is a partial integer
4103 mode as we don't know how many bits are significant
4105 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4106 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4110 len = GET_MODE_BITSIZE (GET_MODE (inner));
4116 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4117 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4119 inner = XEXP (SET_SRC (x), 0);
4120 len = INTVAL (XEXP (SET_SRC (x), 1));
4121 pos = INTVAL (XEXP (SET_SRC (x), 2));
4123 if (BITS_BIG_ENDIAN)
4124 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4125 unsignedp = (code == ZERO_EXTRACT);
4133 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4135 enum machine_mode mode = GET_MODE (SET_SRC (x));
4137 /* For unsigned, we have a choice of a shift followed by an
4138 AND or two shifts. Use two shifts for field sizes where the
4139 constant might be too large. We assume here that we can
4140 always at least get 8-bit constants in an AND insn, which is
4141 true for every current RISC. */
4143 if (unsignedp && len <= 8)
4148 (mode, gen_lowpart (mode, inner),
4150 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4152 split = find_split_point (&SET_SRC (x), insn);
4153 if (split && split != &SET_SRC (x))
4160 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4161 gen_rtx_ASHIFT (mode,
4162 gen_lowpart (mode, inner),
4163 GEN_INT (GET_MODE_BITSIZE (mode)
4165 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4167 split = find_split_point (&SET_SRC (x), insn);
4168 if (split && split != &SET_SRC (x))
4173 /* See if this is a simple operation with a constant as the second
4174 operand. It might be that this constant is out of range and hence
4175 could be used as a split point. */
4176 if (BINARY_P (SET_SRC (x))
4177 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4178 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4179 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4180 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4181 return &XEXP (SET_SRC (x), 1);
4183 /* Finally, see if this is a simple operation with its first operand
4184 not in a register. The operation might require this operand in a
4185 register, so return it as a split point. We can always do this
4186 because if the first operand were another operation, we would have
4187 already found it as a split point. */
4188 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4189 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4190 return &XEXP (SET_SRC (x), 0);
4196 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4197 it is better to write this as (not (ior A B)) so we can split it.
4198 Similarly for IOR. */
4199 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4202 gen_rtx_NOT (GET_MODE (x),
4203 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4205 XEXP (XEXP (x, 0), 0),
4206 XEXP (XEXP (x, 1), 0))));
4207 return find_split_point (loc, insn);
4210 /* Many RISC machines have a large set of logical insns. If the
4211 second operand is a NOT, put it first so we will try to split the
4212 other operand first. */
4213 if (GET_CODE (XEXP (x, 1)) == NOT)
4215 rtx tem = XEXP (x, 0);
4216 SUBST (XEXP (x, 0), XEXP (x, 1));
4217 SUBST (XEXP (x, 1), tem);
4225 /* Otherwise, select our actions depending on our rtx class. */
4226 switch (GET_RTX_CLASS (code))
4228 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4230 split = find_split_point (&XEXP (x, 2), insn);
4233 /* ... fall through ... */
4235 case RTX_COMM_ARITH:
4237 case RTX_COMM_COMPARE:
4238 split = find_split_point (&XEXP (x, 1), insn);
4241 /* ... fall through ... */
4243 /* Some machines have (and (shift ...) ...) insns. If X is not
4244 an AND, but XEXP (X, 0) is, use it as our split point. */
4245 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4246 return &XEXP (x, 0);
4248 split = find_split_point (&XEXP (x, 0), insn);
4254 /* Otherwise, we don't have a split point. */
4259 /* Throughout X, replace FROM with TO, and return the result.
4260 The result is TO if X is FROM;
4261 otherwise the result is X, but its contents may have been modified.
4262 If they were modified, a record was made in undobuf so that
4263 undo_all will (among other things) return X to its original state.
4265 If the number of changes necessary is too much to record to undo,
4266 the excess changes are not made, so the result is invalid.
4267 The changes already made can still be undone.
4268 undobuf.num_undo is incremented for such changes, so by testing that
4269 the caller can tell whether the result is valid.
4271 `n_occurrences' is incremented each time FROM is replaced.
4273 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4275 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4276 by copying if `n_occurrences' is nonzero. */
4279 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4281 enum rtx_code code = GET_CODE (x);
4282 enum machine_mode op0_mode = VOIDmode;
4287 /* Two expressions are equal if they are identical copies of a shared
4288 RTX or if they are both registers with the same register number
4291 #define COMBINE_RTX_EQUAL_P(X,Y) \
4293 || (REG_P (X) && REG_P (Y) \
4294 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4296 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4299 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4302 /* If X and FROM are the same register but different modes, they
4303 will not have been seen as equal above. However, the log links code
4304 will make a LOG_LINKS entry for that case. If we do nothing, we
4305 will try to rerecognize our original insn and, when it succeeds,
4306 we will delete the feeding insn, which is incorrect.
4308 So force this insn not to match in this (rare) case. */
4309 if (! in_dest && code == REG && REG_P (from)
4310 && reg_overlap_mentioned_p (x, from))
4311 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4313 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4314 of which may contain things that can be combined. */
4315 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4318 /* It is possible to have a subexpression appear twice in the insn.
4319 Suppose that FROM is a register that appears within TO.
4320 Then, after that subexpression has been scanned once by `subst',
4321 the second time it is scanned, TO may be found. If we were
4322 to scan TO here, we would find FROM within it and create a
4323 self-referent rtl structure which is completely wrong. */
4324 if (COMBINE_RTX_EQUAL_P (x, to))
4327 /* Parallel asm_operands need special attention because all of the
4328 inputs are shared across the arms. Furthermore, unsharing the
4329 rtl results in recognition failures. Failure to handle this case
4330 specially can result in circular rtl.
4332 Solve this by doing a normal pass across the first entry of the
4333 parallel, and only processing the SET_DESTs of the subsequent
4336 if (code == PARALLEL
4337 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4338 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4340 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4342 /* If this substitution failed, this whole thing fails. */
4343 if (GET_CODE (new_rtx) == CLOBBER
4344 && XEXP (new_rtx, 0) == const0_rtx)
4347 SUBST (XVECEXP (x, 0, 0), new_rtx);
4349 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4351 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4354 && GET_CODE (dest) != CC0
4355 && GET_CODE (dest) != PC)
4357 new_rtx = subst (dest, from, to, 0, unique_copy);
4359 /* If this substitution failed, this whole thing fails. */
4360 if (GET_CODE (new_rtx) == CLOBBER
4361 && XEXP (new_rtx, 0) == const0_rtx)
4364 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4370 len = GET_RTX_LENGTH (code);
4371 fmt = GET_RTX_FORMAT (code);
4373 /* We don't need to process a SET_DEST that is a register, CC0,
4374 or PC, so set up to skip this common case. All other cases
4375 where we want to suppress replacing something inside a
4376 SET_SRC are handled via the IN_DEST operand. */
4378 && (REG_P (SET_DEST (x))
4379 || GET_CODE (SET_DEST (x)) == CC0
4380 || GET_CODE (SET_DEST (x)) == PC))
4383 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4386 op0_mode = GET_MODE (XEXP (x, 0));
4388 for (i = 0; i < len; i++)
4393 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4395 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4397 new_rtx = (unique_copy && n_occurrences
4398 ? copy_rtx (to) : to);
4403 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4406 /* If this substitution failed, this whole thing
4408 if (GET_CODE (new_rtx) == CLOBBER
4409 && XEXP (new_rtx, 0) == const0_rtx)
4413 SUBST (XVECEXP (x, i, j), new_rtx);
4416 else if (fmt[i] == 'e')
4418 /* If this is a register being set, ignore it. */
4419 new_rtx = XEXP (x, i);
4422 && (((code == SUBREG || code == ZERO_EXTRACT)
4424 || code == STRICT_LOW_PART))
4427 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4429 /* In general, don't install a subreg involving two
4430 modes not tieable. It can worsen register
4431 allocation, and can even make invalid reload
4432 insns, since the reg inside may need to be copied
4433 from in the outside mode, and that may be invalid
4434 if it is an fp reg copied in integer mode.
4436 We allow two exceptions to this: It is valid if
4437 it is inside another SUBREG and the mode of that
4438 SUBREG and the mode of the inside of TO is
4439 tieable and it is valid if X is a SET that copies
4442 if (GET_CODE (to) == SUBREG
4443 && ! MODES_TIEABLE_P (GET_MODE (to),
4444 GET_MODE (SUBREG_REG (to)))
4445 && ! (code == SUBREG
4446 && MODES_TIEABLE_P (GET_MODE (x),
4447 GET_MODE (SUBREG_REG (to))))
4449 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4452 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4454 #ifdef CANNOT_CHANGE_MODE_CLASS
4457 && REGNO (to) < FIRST_PSEUDO_REGISTER
4458 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4461 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4464 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4468 /* If we are in a SET_DEST, suppress most cases unless we
4469 have gone inside a MEM, in which case we want to
4470 simplify the address. We assume here that things that
4471 are actually part of the destination have their inner
4472 parts in the first expression. This is true for SUBREG,
4473 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4474 things aside from REG and MEM that should appear in a
4476 new_rtx = subst (XEXP (x, i), from, to,
4478 && (code == SUBREG || code == STRICT_LOW_PART
4479 || code == ZERO_EXTRACT))
4481 && i == 0), unique_copy);
4483 /* If we found that we will have to reject this combination,
4484 indicate that by returning the CLOBBER ourselves, rather than
4485 an expression containing it. This will speed things up as
4486 well as prevent accidents where two CLOBBERs are considered
4487 to be equal, thus producing an incorrect simplification. */
4489 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4492 if (GET_CODE (x) == SUBREG
4493 && (GET_CODE (new_rtx) == CONST_INT
4494 || GET_CODE (new_rtx) == CONST_DOUBLE))
4496 enum machine_mode mode = GET_MODE (x);
4498 x = simplify_subreg (GET_MODE (x), new_rtx,
4499 GET_MODE (SUBREG_REG (x)),
4502 x = gen_rtx_CLOBBER (mode, const0_rtx);
4504 else if (GET_CODE (new_rtx) == CONST_INT
4505 && GET_CODE (x) == ZERO_EXTEND)
4507 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4508 new_rtx, GET_MODE (XEXP (x, 0)));
4512 SUBST (XEXP (x, i), new_rtx);
4517 /* Check if we are loading something from the constant pool via float
4518 extension; in this case we would undo compress_float_constant
4519 optimization and degenerate constant load to an immediate value. */
4520 if (GET_CODE (x) == FLOAT_EXTEND
4521 && MEM_P (XEXP (x, 0))
4522 && MEM_READONLY_P (XEXP (x, 0)))
4524 rtx tmp = avoid_constant_pool_reference (x);
4529 /* Try to simplify X. If the simplification changed the code, it is likely
4530 that further simplification will help, so loop, but limit the number
4531 of repetitions that will be performed. */
4533 for (i = 0; i < 4; i++)
4535 /* If X is sufficiently simple, don't bother trying to do anything
4537 if (code != CONST_INT && code != REG && code != CLOBBER)
4538 x = combine_simplify_rtx (x, op0_mode, in_dest);
4540 if (GET_CODE (x) == code)
4543 code = GET_CODE (x);
4545 /* We no longer know the original mode of operand 0 since we
4546 have changed the form of X) */
4547 op0_mode = VOIDmode;
4553 /* Simplify X, a piece of RTL. We just operate on the expression at the
4554 outer level; call `subst' to simplify recursively. Return the new
4557 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4558 if we are inside a SET_DEST. */
4561 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4563 enum rtx_code code = GET_CODE (x);
4564 enum machine_mode mode = GET_MODE (x);
4568 /* If this is a commutative operation, put a constant last and a complex
4569 expression first. We don't need to do this for comparisons here. */
4570 if (COMMUTATIVE_ARITH_P (x)
4571 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4574 SUBST (XEXP (x, 0), XEXP (x, 1));
4575 SUBST (XEXP (x, 1), temp);
4578 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4579 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4580 things. Check for cases where both arms are testing the same
4583 Don't do anything if all operands are very simple. */
4586 && ((!OBJECT_P (XEXP (x, 0))
4587 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4588 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4589 || (!OBJECT_P (XEXP (x, 1))
4590 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4591 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4593 && (!OBJECT_P (XEXP (x, 0))
4594 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4595 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4597 rtx cond, true_rtx, false_rtx;
4599 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4601 /* If everything is a comparison, what we have is highly unlikely
4602 to be simpler, so don't use it. */
4603 && ! (COMPARISON_P (x)
4604 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4606 rtx cop1 = const0_rtx;
4607 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4609 if (cond_code == NE && COMPARISON_P (cond))
4612 /* Simplify the alternative arms; this may collapse the true and
4613 false arms to store-flag values. Be careful to use copy_rtx
4614 here since true_rtx or false_rtx might share RTL with x as a
4615 result of the if_then_else_cond call above. */
4616 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4617 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4619 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4620 is unlikely to be simpler. */
4621 if (general_operand (true_rtx, VOIDmode)
4622 && general_operand (false_rtx, VOIDmode))
4624 enum rtx_code reversed;
4626 /* Restarting if we generate a store-flag expression will cause
4627 us to loop. Just drop through in this case. */
4629 /* If the result values are STORE_FLAG_VALUE and zero, we can
4630 just make the comparison operation. */
4631 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4632 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4634 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4635 && ((reversed = reversed_comparison_code_parts
4636 (cond_code, cond, cop1, NULL))
4638 x = simplify_gen_relational (reversed, mode, VOIDmode,
4641 /* Likewise, we can make the negate of a comparison operation
4642 if the result values are - STORE_FLAG_VALUE and zero. */
4643 else if (GET_CODE (true_rtx) == CONST_INT
4644 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4645 && false_rtx == const0_rtx)
4646 x = simplify_gen_unary (NEG, mode,
4647 simplify_gen_relational (cond_code,
4651 else if (GET_CODE (false_rtx) == CONST_INT
4652 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4653 && true_rtx == const0_rtx
4654 && ((reversed = reversed_comparison_code_parts
4655 (cond_code, cond, cop1, NULL))
4657 x = simplify_gen_unary (NEG, mode,
4658 simplify_gen_relational (reversed,
4663 return gen_rtx_IF_THEN_ELSE (mode,
4664 simplify_gen_relational (cond_code,
4669 true_rtx, false_rtx);
4671 code = GET_CODE (x);
4672 op0_mode = VOIDmode;
4677 /* Try to fold this expression in case we have constants that weren't
4680 switch (GET_RTX_CLASS (code))
4683 if (op0_mode == VOIDmode)
4684 op0_mode = GET_MODE (XEXP (x, 0));
4685 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4688 case RTX_COMM_COMPARE:
4690 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4691 if (cmp_mode == VOIDmode)
4693 cmp_mode = GET_MODE (XEXP (x, 1));
4694 if (cmp_mode == VOIDmode)
4695 cmp_mode = op0_mode;
4697 temp = simplify_relational_operation (code, mode, cmp_mode,
4698 XEXP (x, 0), XEXP (x, 1));
4701 case RTX_COMM_ARITH:
4703 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4705 case RTX_BITFIELD_OPS:
4707 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4708 XEXP (x, 1), XEXP (x, 2));
4717 code = GET_CODE (temp);
4718 op0_mode = VOIDmode;
4719 mode = GET_MODE (temp);
4722 /* First see if we can apply the inverse distributive law. */
4723 if (code == PLUS || code == MINUS
4724 || code == AND || code == IOR || code == XOR)
4726 x = apply_distributive_law (x);
4727 code = GET_CODE (x);
4728 op0_mode = VOIDmode;
4731 /* If CODE is an associative operation not otherwise handled, see if we
4732 can associate some operands. This can win if they are constants or
4733 if they are logically related (i.e. (a & b) & a). */
4734 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4735 || code == AND || code == IOR || code == XOR
4736 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4737 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4738 || (flag_associative_math && FLOAT_MODE_P (mode))))
4740 if (GET_CODE (XEXP (x, 0)) == code)
4742 rtx other = XEXP (XEXP (x, 0), 0);
4743 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4744 rtx inner_op1 = XEXP (x, 1);
4747 /* Make sure we pass the constant operand if any as the second
4748 one if this is a commutative operation. */
4749 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4751 rtx tem = inner_op0;
4752 inner_op0 = inner_op1;
4755 inner = simplify_binary_operation (code == MINUS ? PLUS
4756 : code == DIV ? MULT
4758 mode, inner_op0, inner_op1);
4760 /* For commutative operations, try the other pair if that one
4762 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4764 other = XEXP (XEXP (x, 0), 1);
4765 inner = simplify_binary_operation (code, mode,
4766 XEXP (XEXP (x, 0), 0),
4771 return simplify_gen_binary (code, mode, other, inner);
4775 /* A little bit of algebraic simplification here. */
4779 /* Ensure that our address has any ASHIFTs converted to MULT in case
4780 address-recognizing predicates are called later. */
4781 temp = make_compound_operation (XEXP (x, 0), MEM);
4782 SUBST (XEXP (x, 0), temp);
4786 if (op0_mode == VOIDmode)
4787 op0_mode = GET_MODE (SUBREG_REG (x));
4789 /* See if this can be moved to simplify_subreg. */
4790 if (CONSTANT_P (SUBREG_REG (x))
4791 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4792 /* Don't call gen_lowpart if the inner mode
4793 is VOIDmode and we cannot simplify it, as SUBREG without
4794 inner mode is invalid. */
4795 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4796 || gen_lowpart_common (mode, SUBREG_REG (x))))
4797 return gen_lowpart (mode, SUBREG_REG (x));
4799 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4803 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4809 /* Don't change the mode of the MEM if that would change the meaning
4811 if (MEM_P (SUBREG_REG (x))
4812 && (MEM_VOLATILE_P (SUBREG_REG (x))
4813 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4814 return gen_rtx_CLOBBER (mode, const0_rtx);
4816 /* Note that we cannot do any narrowing for non-constants since
4817 we might have been counting on using the fact that some bits were
4818 zero. We now do this in the SET. */
4823 temp = expand_compound_operation (XEXP (x, 0));
4825 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4826 replaced by (lshiftrt X C). This will convert
4827 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4829 if (GET_CODE (temp) == ASHIFTRT
4830 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4831 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4832 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4833 INTVAL (XEXP (temp, 1)));
4835 /* If X has only a single bit that might be nonzero, say, bit I, convert
4836 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4837 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4838 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4839 or a SUBREG of one since we'd be making the expression more
4840 complex if it was just a register. */
4843 && ! (GET_CODE (temp) == SUBREG
4844 && REG_P (SUBREG_REG (temp)))
4845 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4847 rtx temp1 = simplify_shift_const
4848 (NULL_RTX, ASHIFTRT, mode,
4849 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4850 GET_MODE_BITSIZE (mode) - 1 - i),
4851 GET_MODE_BITSIZE (mode) - 1 - i);
4853 /* If all we did was surround TEMP with the two shifts, we
4854 haven't improved anything, so don't use it. Otherwise,
4855 we are better off with TEMP1. */
4856 if (GET_CODE (temp1) != ASHIFTRT
4857 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4858 || XEXP (XEXP (temp1, 0), 0) != temp)
4864 /* We can't handle truncation to a partial integer mode here
4865 because we don't know the real bitsize of the partial
4867 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4870 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4871 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4872 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4874 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4875 GET_MODE_MASK (mode), 0));
4877 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4878 whose value is a comparison can be replaced with a subreg if
4879 STORE_FLAG_VALUE permits. */
4880 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4881 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4882 && (temp = get_last_value (XEXP (x, 0)))
4883 && COMPARISON_P (temp))
4884 return gen_lowpart (mode, XEXP (x, 0));
4889 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4890 using cc0, in which case we want to leave it as a COMPARE
4891 so we can distinguish it from a register-register-copy. */
4892 if (XEXP (x, 1) == const0_rtx)
4895 /* x - 0 is the same as x unless x's mode has signed zeros and
4896 allows rounding towards -infinity. Under those conditions,
4898 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4899 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4900 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4906 /* (const (const X)) can become (const X). Do it this way rather than
4907 returning the inner CONST since CONST can be shared with a
4909 if (GET_CODE (XEXP (x, 0)) == CONST)
4910 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4915 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4916 can add in an offset. find_split_point will split this address up
4917 again if it doesn't match. */
4918 if (GET_CODE (XEXP (x, 0)) == HIGH
4919 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4925 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4926 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4927 bit-field and can be replaced by either a sign_extend or a
4928 sign_extract. The `and' may be a zero_extend and the two
4929 <c>, -<c> constants may be reversed. */
4930 if (GET_CODE (XEXP (x, 0)) == XOR
4931 && GET_CODE (XEXP (x, 1)) == CONST_INT
4932 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4933 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4934 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4935 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4936 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4937 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4938 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4939 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4940 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4941 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4942 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4943 == (unsigned int) i + 1))))
4944 return simplify_shift_const
4945 (NULL_RTX, ASHIFTRT, mode,
4946 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4947 XEXP (XEXP (XEXP (x, 0), 0), 0),
4948 GET_MODE_BITSIZE (mode) - (i + 1)),
4949 GET_MODE_BITSIZE (mode) - (i + 1));
4951 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4952 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4953 the bitsize of the mode - 1. This allows simplification of
4954 "a = (b & 8) == 0;" */
4955 if (XEXP (x, 1) == constm1_rtx
4956 && !REG_P (XEXP (x, 0))
4957 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4958 && REG_P (SUBREG_REG (XEXP (x, 0))))
4959 && nonzero_bits (XEXP (x, 0), mode) == 1)
4960 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4961 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4962 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4963 GET_MODE_BITSIZE (mode) - 1),
4964 GET_MODE_BITSIZE (mode) - 1);
4966 /* If we are adding two things that have no bits in common, convert
4967 the addition into an IOR. This will often be further simplified,
4968 for example in cases like ((a & 1) + (a & 2)), which can
4971 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4972 && (nonzero_bits (XEXP (x, 0), mode)
4973 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4975 /* Try to simplify the expression further. */
4976 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4977 temp = combine_simplify_rtx (tor, mode, in_dest);
4979 /* If we could, great. If not, do not go ahead with the IOR
4980 replacement, since PLUS appears in many special purpose
4981 address arithmetic instructions. */
4982 if (GET_CODE (temp) != CLOBBER && temp != tor)
4988 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4989 (and <foo> (const_int pow2-1)) */
4990 if (GET_CODE (XEXP (x, 1)) == AND
4991 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4992 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4993 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4994 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4995 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4999 /* If we have (mult (plus A B) C), apply the distributive law and then
5000 the inverse distributive law to see if things simplify. This
5001 occurs mostly in addresses, often when unrolling loops. */
5003 if (GET_CODE (XEXP (x, 0)) == PLUS)
5005 rtx result = distribute_and_simplify_rtx (x, 0);
5010 /* Try simplify a*(b/c) as (a*b)/c. */
5011 if (FLOAT_MODE_P (mode) && flag_associative_math
5012 && GET_CODE (XEXP (x, 0)) == DIV)
5014 rtx tem = simplify_binary_operation (MULT, mode,
5015 XEXP (XEXP (x, 0), 0),
5018 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5023 /* If this is a divide by a power of two, treat it as a shift if
5024 its first operand is a shift. */
5025 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5026 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5027 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5028 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5029 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5030 || GET_CODE (XEXP (x, 0)) == ROTATE
5031 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5032 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5036 case GT: case GTU: case GE: case GEU:
5037 case LT: case LTU: case LE: case LEU:
5038 case UNEQ: case LTGT:
5039 case UNGT: case UNGE:
5040 case UNLT: case UNLE:
5041 case UNORDERED: case ORDERED:
5042 /* If the first operand is a condition code, we can't do anything
5044 if (GET_CODE (XEXP (x, 0)) == COMPARE
5045 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5046 && ! CC0_P (XEXP (x, 0))))
5048 rtx op0 = XEXP (x, 0);
5049 rtx op1 = XEXP (x, 1);
5050 enum rtx_code new_code;
5052 if (GET_CODE (op0) == COMPARE)
5053 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5055 /* Simplify our comparison, if possible. */
5056 new_code = simplify_comparison (code, &op0, &op1);
5058 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5059 if only the low-order bit is possibly nonzero in X (such as when
5060 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5061 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5062 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5065 Remove any ZERO_EXTRACT we made when thinking this was a
5066 comparison. It may now be simpler to use, e.g., an AND. If a
5067 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5068 the call to make_compound_operation in the SET case. */
5070 if (STORE_FLAG_VALUE == 1
5071 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5072 && op1 == const0_rtx
5073 && mode == GET_MODE (op0)
5074 && nonzero_bits (op0, mode) == 1)
5075 return gen_lowpart (mode,
5076 expand_compound_operation (op0));
5078 else if (STORE_FLAG_VALUE == 1
5079 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5080 && op1 == const0_rtx
5081 && mode == GET_MODE (op0)
5082 && (num_sign_bit_copies (op0, mode)
5083 == GET_MODE_BITSIZE (mode)))
5085 op0 = expand_compound_operation (op0);
5086 return simplify_gen_unary (NEG, mode,
5087 gen_lowpart (mode, op0),
5091 else if (STORE_FLAG_VALUE == 1
5092 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5093 && op1 == const0_rtx
5094 && mode == GET_MODE (op0)
5095 && nonzero_bits (op0, mode) == 1)
5097 op0 = expand_compound_operation (op0);
5098 return simplify_gen_binary (XOR, mode,
5099 gen_lowpart (mode, op0),
5103 else if (STORE_FLAG_VALUE == 1
5104 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5105 && op1 == const0_rtx
5106 && mode == GET_MODE (op0)
5107 && (num_sign_bit_copies (op0, mode)
5108 == GET_MODE_BITSIZE (mode)))
5110 op0 = expand_compound_operation (op0);
5111 return plus_constant (gen_lowpart (mode, op0), 1);
5114 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5116 if (STORE_FLAG_VALUE == -1
5117 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5118 && op1 == const0_rtx
5119 && (num_sign_bit_copies (op0, mode)
5120 == GET_MODE_BITSIZE (mode)))
5121 return gen_lowpart (mode,
5122 expand_compound_operation (op0));
5124 else if (STORE_FLAG_VALUE == -1
5125 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5126 && op1 == const0_rtx
5127 && mode == GET_MODE (op0)
5128 && nonzero_bits (op0, mode) == 1)
5130 op0 = expand_compound_operation (op0);
5131 return simplify_gen_unary (NEG, mode,
5132 gen_lowpart (mode, op0),
5136 else if (STORE_FLAG_VALUE == -1
5137 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5138 && op1 == const0_rtx
5139 && mode == GET_MODE (op0)
5140 && (num_sign_bit_copies (op0, mode)
5141 == GET_MODE_BITSIZE (mode)))
5143 op0 = expand_compound_operation (op0);
5144 return simplify_gen_unary (NOT, mode,
5145 gen_lowpart (mode, op0),
5149 /* If X is 0/1, (eq X 0) is X-1. */
5150 else if (STORE_FLAG_VALUE == -1
5151 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5152 && op1 == const0_rtx
5153 && mode == GET_MODE (op0)
5154 && nonzero_bits (op0, mode) == 1)
5156 op0 = expand_compound_operation (op0);
5157 return plus_constant (gen_lowpart (mode, op0), -1);
5160 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5161 one bit that might be nonzero, we can convert (ne x 0) to
5162 (ashift x c) where C puts the bit in the sign bit. Remove any
5163 AND with STORE_FLAG_VALUE when we are done, since we are only
5164 going to test the sign bit. */
5165 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5166 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5167 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5168 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5169 && op1 == const0_rtx
5170 && mode == GET_MODE (op0)
5171 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5173 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5174 expand_compound_operation (op0),
5175 GET_MODE_BITSIZE (mode) - 1 - i);
5176 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5182 /* If the code changed, return a whole new comparison. */
5183 if (new_code != code)
5184 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5186 /* Otherwise, keep this operation, but maybe change its operands.
5187 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5188 SUBST (XEXP (x, 0), op0);
5189 SUBST (XEXP (x, 1), op1);
5194 return simplify_if_then_else (x);
5200 /* If we are processing SET_DEST, we are done. */
5204 return expand_compound_operation (x);
5207 return simplify_set (x);
5211 return simplify_logical (x);
5218 /* If this is a shift by a constant amount, simplify it. */
5219 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5220 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5221 INTVAL (XEXP (x, 1)));
5223 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5225 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5227 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5239 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5242 simplify_if_then_else (rtx x)
5244 enum machine_mode mode = GET_MODE (x);
5245 rtx cond = XEXP (x, 0);
5246 rtx true_rtx = XEXP (x, 1);
5247 rtx false_rtx = XEXP (x, 2);
5248 enum rtx_code true_code = GET_CODE (cond);
5249 int comparison_p = COMPARISON_P (cond);
5252 enum rtx_code false_code;
5255 /* Simplify storing of the truth value. */
5256 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5257 return simplify_gen_relational (true_code, mode, VOIDmode,
5258 XEXP (cond, 0), XEXP (cond, 1));
5260 /* Also when the truth value has to be reversed. */
5262 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5263 && (reversed = reversed_comparison (cond, mode)))
5266 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5267 in it is being compared against certain values. Get the true and false
5268 comparisons and see if that says anything about the value of each arm. */
5271 && ((false_code = reversed_comparison_code (cond, NULL))
5273 && REG_P (XEXP (cond, 0)))
5276 rtx from = XEXP (cond, 0);
5277 rtx true_val = XEXP (cond, 1);
5278 rtx false_val = true_val;
5281 /* If FALSE_CODE is EQ, swap the codes and arms. */
5283 if (false_code == EQ)
5285 swapped = 1, true_code = EQ, false_code = NE;
5286 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5289 /* If we are comparing against zero and the expression being tested has
5290 only a single bit that might be nonzero, that is its value when it is
5291 not equal to zero. Similarly if it is known to be -1 or 0. */
5293 if (true_code == EQ && true_val == const0_rtx
5294 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5297 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5299 else if (true_code == EQ && true_val == const0_rtx
5300 && (num_sign_bit_copies (from, GET_MODE (from))
5301 == GET_MODE_BITSIZE (GET_MODE (from))))
5304 false_val = constm1_rtx;
5307 /* Now simplify an arm if we know the value of the register in the
5308 branch and it is used in the arm. Be careful due to the potential
5309 of locally-shared RTL. */
5311 if (reg_mentioned_p (from, true_rtx))
5312 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5314 pc_rtx, pc_rtx, 0, 0);
5315 if (reg_mentioned_p (from, false_rtx))
5316 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5318 pc_rtx, pc_rtx, 0, 0);
5320 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5321 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5323 true_rtx = XEXP (x, 1);
5324 false_rtx = XEXP (x, 2);
5325 true_code = GET_CODE (cond);
5328 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5329 reversed, do so to avoid needing two sets of patterns for
5330 subtract-and-branch insns. Similarly if we have a constant in the true
5331 arm, the false arm is the same as the first operand of the comparison, or
5332 the false arm is more complicated than the true arm. */
5335 && reversed_comparison_code (cond, NULL) != UNKNOWN
5336 && (true_rtx == pc_rtx
5337 || (CONSTANT_P (true_rtx)
5338 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5339 || true_rtx == const0_rtx
5340 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5341 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5342 && !OBJECT_P (false_rtx))
5343 || reg_mentioned_p (true_rtx, false_rtx)
5344 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5346 true_code = reversed_comparison_code (cond, NULL);
5347 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5348 SUBST (XEXP (x, 1), false_rtx);
5349 SUBST (XEXP (x, 2), true_rtx);
5351 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5354 /* It is possible that the conditional has been simplified out. */
5355 true_code = GET_CODE (cond);
5356 comparison_p = COMPARISON_P (cond);
5359 /* If the two arms are identical, we don't need the comparison. */
5361 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5364 /* Convert a == b ? b : a to "a". */
5365 if (true_code == EQ && ! side_effects_p (cond)
5366 && !HONOR_NANS (mode)
5367 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5368 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5370 else if (true_code == NE && ! side_effects_p (cond)
5371 && !HONOR_NANS (mode)
5372 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5373 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5376 /* Look for cases where we have (abs x) or (neg (abs X)). */
5378 if (GET_MODE_CLASS (mode) == MODE_INT
5380 && XEXP (cond, 1) == const0_rtx
5381 && GET_CODE (false_rtx) == NEG
5382 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5383 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5384 && ! side_effects_p (true_rtx))
5389 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5393 simplify_gen_unary (NEG, mode,
5394 simplify_gen_unary (ABS, mode, true_rtx, mode),
5400 /* Look for MIN or MAX. */
5402 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5404 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5405 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5406 && ! side_effects_p (cond))
5411 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5414 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5417 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5420 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5425 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5426 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5427 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5428 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5429 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5430 neither 1 or -1, but it isn't worth checking for. */
5432 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5434 && GET_MODE_CLASS (mode) == MODE_INT
5435 && ! side_effects_p (x))
5437 rtx t = make_compound_operation (true_rtx, SET);
5438 rtx f = make_compound_operation (false_rtx, SET);
5439 rtx cond_op0 = XEXP (cond, 0);
5440 rtx cond_op1 = XEXP (cond, 1);
5441 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5442 enum machine_mode m = mode;
5443 rtx z = 0, c1 = NULL_RTX;
5445 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5446 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5447 || GET_CODE (t) == ASHIFT
5448 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5449 && rtx_equal_p (XEXP (t, 0), f))
5450 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5452 /* If an identity-zero op is commutative, check whether there
5453 would be a match if we swapped the operands. */
5454 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5455 || GET_CODE (t) == XOR)
5456 && rtx_equal_p (XEXP (t, 1), f))
5457 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5458 else if (GET_CODE (t) == SIGN_EXTEND
5459 && (GET_CODE (XEXP (t, 0)) == PLUS
5460 || GET_CODE (XEXP (t, 0)) == MINUS
5461 || GET_CODE (XEXP (t, 0)) == IOR
5462 || GET_CODE (XEXP (t, 0)) == XOR
5463 || GET_CODE (XEXP (t, 0)) == ASHIFT
5464 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5465 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5466 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5467 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5468 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5469 && (num_sign_bit_copies (f, GET_MODE (f))
5471 (GET_MODE_BITSIZE (mode)
5472 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5474 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5475 extend_op = SIGN_EXTEND;
5476 m = GET_MODE (XEXP (t, 0));
5478 else if (GET_CODE (t) == SIGN_EXTEND
5479 && (GET_CODE (XEXP (t, 0)) == PLUS
5480 || GET_CODE (XEXP (t, 0)) == IOR
5481 || GET_CODE (XEXP (t, 0)) == XOR)
5482 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5483 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5484 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5485 && (num_sign_bit_copies (f, GET_MODE (f))
5487 (GET_MODE_BITSIZE (mode)
5488 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5490 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5491 extend_op = SIGN_EXTEND;
5492 m = GET_MODE (XEXP (t, 0));
5494 else if (GET_CODE (t) == ZERO_EXTEND
5495 && (GET_CODE (XEXP (t, 0)) == PLUS
5496 || GET_CODE (XEXP (t, 0)) == MINUS
5497 || GET_CODE (XEXP (t, 0)) == IOR
5498 || GET_CODE (XEXP (t, 0)) == XOR
5499 || GET_CODE (XEXP (t, 0)) == ASHIFT
5500 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5501 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5502 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5503 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5504 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5505 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5506 && ((nonzero_bits (f, GET_MODE (f))
5507 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5510 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5511 extend_op = ZERO_EXTEND;
5512 m = GET_MODE (XEXP (t, 0));
5514 else if (GET_CODE (t) == ZERO_EXTEND
5515 && (GET_CODE (XEXP (t, 0)) == PLUS
5516 || GET_CODE (XEXP (t, 0)) == IOR
5517 || GET_CODE (XEXP (t, 0)) == XOR)
5518 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5519 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5520 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5521 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5522 && ((nonzero_bits (f, GET_MODE (f))
5523 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5526 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5527 extend_op = ZERO_EXTEND;
5528 m = GET_MODE (XEXP (t, 0));
5533 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5534 cond_op0, cond_op1),
5535 pc_rtx, pc_rtx, 0, 0);
5536 temp = simplify_gen_binary (MULT, m, temp,
5537 simplify_gen_binary (MULT, m, c1,
5539 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5540 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5542 if (extend_op != UNKNOWN)
5543 temp = simplify_gen_unary (extend_op, mode, temp, m);
5549 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5550 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5551 negation of a single bit, we can convert this operation to a shift. We
5552 can actually do this more generally, but it doesn't seem worth it. */
5554 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5555 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5556 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5557 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5558 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5559 == GET_MODE_BITSIZE (mode))
5560 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5562 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5563 gen_lowpart (mode, XEXP (cond, 0)), i);
5565 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5566 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5567 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5568 && GET_MODE (XEXP (cond, 0)) == mode
5569 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5570 == nonzero_bits (XEXP (cond, 0), mode)
5571 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5572 return XEXP (cond, 0);
5577 /* Simplify X, a SET expression. Return the new expression. */
5580 simplify_set (rtx x)
5582 rtx src = SET_SRC (x);
5583 rtx dest = SET_DEST (x);
5584 enum machine_mode mode
5585 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5589 /* (set (pc) (return)) gets written as (return). */
5590 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5593 /* Now that we know for sure which bits of SRC we are using, see if we can
5594 simplify the expression for the object knowing that we only need the
5597 if (GET_MODE_CLASS (mode) == MODE_INT
5598 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5600 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5601 SUBST (SET_SRC (x), src);
5604 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5605 the comparison result and try to simplify it unless we already have used
5606 undobuf.other_insn. */
5607 if ((GET_MODE_CLASS (mode) == MODE_CC
5608 || GET_CODE (src) == COMPARE
5610 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5611 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5612 && COMPARISON_P (*cc_use)
5613 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5615 enum rtx_code old_code = GET_CODE (*cc_use);
5616 enum rtx_code new_code;
5618 int other_changed = 0;
5619 enum machine_mode compare_mode = GET_MODE (dest);
5621 if (GET_CODE (src) == COMPARE)
5622 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5624 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5626 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5629 new_code = old_code;
5630 else if (!CONSTANT_P (tmp))
5632 new_code = GET_CODE (tmp);
5633 op0 = XEXP (tmp, 0);
5634 op1 = XEXP (tmp, 1);
5638 rtx pat = PATTERN (other_insn);
5639 undobuf.other_insn = other_insn;
5640 SUBST (*cc_use, tmp);
5642 /* Attempt to simplify CC user. */
5643 if (GET_CODE (pat) == SET)
5645 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5646 if (new_rtx != NULL_RTX)
5647 SUBST (SET_SRC (pat), new_rtx);
5650 /* Convert X into a no-op move. */
5651 SUBST (SET_DEST (x), pc_rtx);
5652 SUBST (SET_SRC (x), pc_rtx);
5656 /* Simplify our comparison, if possible. */
5657 new_code = simplify_comparison (new_code, &op0, &op1);
5659 #ifdef SELECT_CC_MODE
5660 /* If this machine has CC modes other than CCmode, check to see if we
5661 need to use a different CC mode here. */
5662 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5663 compare_mode = GET_MODE (op0);
5665 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5668 /* If the mode changed, we have to change SET_DEST, the mode in the
5669 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5670 a hard register, just build new versions with the proper mode. If it
5671 is a pseudo, we lose unless it is only time we set the pseudo, in
5672 which case we can safely change its mode. */
5673 if (compare_mode != GET_MODE (dest))
5675 if (can_change_dest_mode (dest, 0, compare_mode))
5677 unsigned int regno = REGNO (dest);
5680 if (regno < FIRST_PSEUDO_REGISTER)
5681 new_dest = gen_rtx_REG (compare_mode, regno);
5684 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5685 new_dest = regno_reg_rtx[regno];
5688 SUBST (SET_DEST (x), new_dest);
5689 SUBST (XEXP (*cc_use, 0), new_dest);
5696 #endif /* SELECT_CC_MODE */
5698 /* If the code changed, we have to build a new comparison in
5699 undobuf.other_insn. */
5700 if (new_code != old_code)
5702 int other_changed_previously = other_changed;
5703 unsigned HOST_WIDE_INT mask;
5705 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5709 /* If the only change we made was to change an EQ into an NE or
5710 vice versa, OP0 has only one bit that might be nonzero, and OP1
5711 is zero, check if changing the user of the condition code will
5712 produce a valid insn. If it won't, we can keep the original code
5713 in that insn by surrounding our operation with an XOR. */
5715 if (((old_code == NE && new_code == EQ)
5716 || (old_code == EQ && new_code == NE))
5717 && ! other_changed_previously && op1 == const0_rtx
5718 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5719 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5721 rtx pat = PATTERN (other_insn), note = 0;
5723 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5724 && ! check_asm_operands (pat)))
5726 PUT_CODE (*cc_use, old_code);
5729 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5730 op0, GEN_INT (mask));
5736 undobuf.other_insn = other_insn;
5739 /* If we are now comparing against zero, change our source if
5740 needed. If we do not use cc0, we always have a COMPARE. */
5741 if (op1 == const0_rtx && dest == cc0_rtx)
5743 SUBST (SET_SRC (x), op0);
5749 /* Otherwise, if we didn't previously have a COMPARE in the
5750 correct mode, we need one. */
5751 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5753 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5756 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5758 SUBST (SET_SRC (x), op0);
5761 /* Otherwise, update the COMPARE if needed. */
5762 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5764 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5770 /* Get SET_SRC in a form where we have placed back any
5771 compound expressions. Then do the checks below. */
5772 src = make_compound_operation (src, SET);
5773 SUBST (SET_SRC (x), src);
5776 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5777 and X being a REG or (subreg (reg)), we may be able to convert this to
5778 (set (subreg:m2 x) (op)).
5780 We can always do this if M1 is narrower than M2 because that means that
5781 we only care about the low bits of the result.
5783 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5784 perform a narrower operation than requested since the high-order bits will
5785 be undefined. On machine where it is defined, this transformation is safe
5786 as long as M1 and M2 have the same number of words. */
5788 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5789 && !OBJECT_P (SUBREG_REG (src))
5790 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5792 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5793 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5794 #ifndef WORD_REGISTER_OPERATIONS
5795 && (GET_MODE_SIZE (GET_MODE (src))
5796 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5798 #ifdef CANNOT_CHANGE_MODE_CLASS
5799 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5800 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5801 GET_MODE (SUBREG_REG (src)),
5805 || (GET_CODE (dest) == SUBREG
5806 && REG_P (SUBREG_REG (dest)))))
5808 SUBST (SET_DEST (x),
5809 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5811 SUBST (SET_SRC (x), SUBREG_REG (src));
5813 src = SET_SRC (x), dest = SET_DEST (x);
5817 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5820 && GET_CODE (src) == SUBREG
5821 && subreg_lowpart_p (src)
5822 && (GET_MODE_BITSIZE (GET_MODE (src))
5823 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5825 rtx inner = SUBREG_REG (src);
5826 enum machine_mode inner_mode = GET_MODE (inner);
5828 /* Here we make sure that we don't have a sign bit on. */
5829 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5830 && (nonzero_bits (inner, inner_mode)
5831 < ((unsigned HOST_WIDE_INT) 1
5832 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5834 SUBST (SET_SRC (x), inner);
5840 #ifdef LOAD_EXTEND_OP
5841 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5842 would require a paradoxical subreg. Replace the subreg with a
5843 zero_extend to avoid the reload that would otherwise be required. */
5845 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5846 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
5847 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5848 && SUBREG_BYTE (src) == 0
5849 && (GET_MODE_SIZE (GET_MODE (src))
5850 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5851 && MEM_P (SUBREG_REG (src)))
5854 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5855 GET_MODE (src), SUBREG_REG (src)));
5861 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5862 are comparing an item known to be 0 or -1 against 0, use a logical
5863 operation instead. Check for one of the arms being an IOR of the other
5864 arm with some value. We compute three terms to be IOR'ed together. In
5865 practice, at most two will be nonzero. Then we do the IOR's. */
5867 if (GET_CODE (dest) != PC
5868 && GET_CODE (src) == IF_THEN_ELSE
5869 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5870 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5871 && XEXP (XEXP (src, 0), 1) == const0_rtx
5872 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5873 #ifdef HAVE_conditional_move
5874 && ! can_conditionally_move_p (GET_MODE (src))
5876 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5877 GET_MODE (XEXP (XEXP (src, 0), 0)))
5878 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5879 && ! side_effects_p (src))
5881 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5882 ? XEXP (src, 1) : XEXP (src, 2));
5883 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5884 ? XEXP (src, 2) : XEXP (src, 1));
5885 rtx term1 = const0_rtx, term2, term3;
5887 if (GET_CODE (true_rtx) == IOR
5888 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5889 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5890 else if (GET_CODE (true_rtx) == IOR
5891 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5892 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5893 else if (GET_CODE (false_rtx) == IOR
5894 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5895 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5896 else if (GET_CODE (false_rtx) == IOR
5897 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5898 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5900 term2 = simplify_gen_binary (AND, GET_MODE (src),
5901 XEXP (XEXP (src, 0), 0), true_rtx);
5902 term3 = simplify_gen_binary (AND, GET_MODE (src),
5903 simplify_gen_unary (NOT, GET_MODE (src),
5904 XEXP (XEXP (src, 0), 0),
5909 simplify_gen_binary (IOR, GET_MODE (src),
5910 simplify_gen_binary (IOR, GET_MODE (src),
5917 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5918 whole thing fail. */
5919 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5921 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5924 /* Convert this into a field assignment operation, if possible. */
5925 return make_field_assignment (x);
5928 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5932 simplify_logical (rtx x)
5934 enum machine_mode mode = GET_MODE (x);
5935 rtx op0 = XEXP (x, 0);
5936 rtx op1 = XEXP (x, 1);
5938 switch (GET_CODE (x))
5941 /* We can call simplify_and_const_int only if we don't lose
5942 any (sign) bits when converting INTVAL (op1) to
5943 "unsigned HOST_WIDE_INT". */
5944 if (GET_CODE (op1) == CONST_INT
5945 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5946 || INTVAL (op1) > 0))
5948 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5949 if (GET_CODE (x) != AND)
5956 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5957 apply the distributive law and then the inverse distributive
5958 law to see if things simplify. */
5959 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5961 rtx result = distribute_and_simplify_rtx (x, 0);
5965 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5967 rtx result = distribute_and_simplify_rtx (x, 1);
5974 /* If we have (ior (and A B) C), apply the distributive law and then
5975 the inverse distributive law to see if things simplify. */
5977 if (GET_CODE (op0) == AND)
5979 rtx result = distribute_and_simplify_rtx (x, 0);
5984 if (GET_CODE (op1) == AND)
5986 rtx result = distribute_and_simplify_rtx (x, 1);
5999 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6000 operations" because they can be replaced with two more basic operations.
6001 ZERO_EXTEND is also considered "compound" because it can be replaced with
6002 an AND operation, which is simpler, though only one operation.
6004 The function expand_compound_operation is called with an rtx expression
6005 and will convert it to the appropriate shifts and AND operations,
6006 simplifying at each stage.
6008 The function make_compound_operation is called to convert an expression
6009 consisting of shifts and ANDs into the equivalent compound expression.
6010 It is the inverse of this function, loosely speaking. */
6013 expand_compound_operation (rtx x)
6015 unsigned HOST_WIDE_INT pos = 0, len;
6017 unsigned int modewidth;
6020 switch (GET_CODE (x))
6025 /* We can't necessarily use a const_int for a multiword mode;
6026 it depends on implicitly extending the value.
6027 Since we don't know the right way to extend it,
6028 we can't tell whether the implicit way is right.
6030 Even for a mode that is no wider than a const_int,
6031 we can't win, because we need to sign extend one of its bits through
6032 the rest of it, and we don't know which bit. */
6033 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6036 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6037 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6038 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6039 reloaded. If not for that, MEM's would very rarely be safe.
6041 Reject MODEs bigger than a word, because we might not be able
6042 to reference a two-register group starting with an arbitrary register
6043 (and currently gen_lowpart might crash for a SUBREG). */
6045 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6048 /* Reject MODEs that aren't scalar integers because turning vector
6049 or complex modes into shifts causes problems. */
6051 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6054 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6055 /* If the inner object has VOIDmode (the only way this can happen
6056 is if it is an ASM_OPERANDS), we can't do anything since we don't
6057 know how much masking to do. */
6066 /* ... fall through ... */
6069 /* If the operand is a CLOBBER, just return it. */
6070 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6073 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6074 || GET_CODE (XEXP (x, 2)) != CONST_INT
6075 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6078 /* Reject MODEs that aren't scalar integers because turning vector
6079 or complex modes into shifts causes problems. */
6081 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6084 len = INTVAL (XEXP (x, 1));
6085 pos = INTVAL (XEXP (x, 2));
6087 /* This should stay within the object being extracted, fail otherwise. */
6088 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6091 if (BITS_BIG_ENDIAN)
6092 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6099 /* Convert sign extension to zero extension, if we know that the high
6100 bit is not set, as this is easier to optimize. It will be converted
6101 back to cheaper alternative in make_extraction. */
6102 if (GET_CODE (x) == SIGN_EXTEND
6103 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6104 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6105 & ~(((unsigned HOST_WIDE_INT)
6106 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6110 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6111 rtx temp2 = expand_compound_operation (temp);
6113 /* Make sure this is a profitable operation. */
6114 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6115 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6117 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6118 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6124 /* We can optimize some special cases of ZERO_EXTEND. */
6125 if (GET_CODE (x) == ZERO_EXTEND)
6127 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6128 know that the last value didn't have any inappropriate bits
6130 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6131 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6132 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6133 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6134 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6135 return XEXP (XEXP (x, 0), 0);
6137 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6138 if (GET_CODE (XEXP (x, 0)) == SUBREG
6139 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6140 && subreg_lowpart_p (XEXP (x, 0))
6141 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6142 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6143 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6144 return SUBREG_REG (XEXP (x, 0));
6146 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6147 is a comparison and STORE_FLAG_VALUE permits. This is like
6148 the first case, but it works even when GET_MODE (x) is larger
6149 than HOST_WIDE_INT. */
6150 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6151 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6152 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6153 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6154 <= HOST_BITS_PER_WIDE_INT)
6155 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6156 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6157 return XEXP (XEXP (x, 0), 0);
6159 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6160 if (GET_CODE (XEXP (x, 0)) == SUBREG
6161 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6162 && subreg_lowpart_p (XEXP (x, 0))
6163 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6164 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6165 <= HOST_BITS_PER_WIDE_INT)
6166 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6167 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6168 return SUBREG_REG (XEXP (x, 0));
6172 /* If we reach here, we want to return a pair of shifts. The inner
6173 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6174 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6175 logical depending on the value of UNSIGNEDP.
6177 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6178 converted into an AND of a shift.
6180 We must check for the case where the left shift would have a negative
6181 count. This can happen in a case like (x >> 31) & 255 on machines
6182 that can't shift by a constant. On those machines, we would first
6183 combine the shift with the AND to produce a variable-position
6184 extraction. Then the constant of 31 would be substituted in to produce
6185 a such a position. */
6187 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6188 if (modewidth + len >= pos)
6190 enum machine_mode mode = GET_MODE (x);
6191 tem = gen_lowpart (mode, XEXP (x, 0));
6192 if (!tem || GET_CODE (tem) == CLOBBER)
6194 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6195 tem, modewidth - pos - len);
6196 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6197 mode, tem, modewidth - len);
6199 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6200 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6201 simplify_shift_const (NULL_RTX, LSHIFTRT,
6204 ((HOST_WIDE_INT) 1 << len) - 1);
6206 /* Any other cases we can't handle. */
6209 /* If we couldn't do this for some reason, return the original
6211 if (GET_CODE (tem) == CLOBBER)
6217 /* X is a SET which contains an assignment of one object into
6218 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6219 or certain SUBREGS). If possible, convert it into a series of
6222 We half-heartedly support variable positions, but do not at all
6223 support variable lengths. */
6226 expand_field_assignment (const_rtx x)
6229 rtx pos; /* Always counts from low bit. */
6231 rtx mask, cleared, masked;
6232 enum machine_mode compute_mode;
6234 /* Loop until we find something we can't simplify. */
6237 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6238 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6240 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6241 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6242 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6244 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6245 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6247 inner = XEXP (SET_DEST (x), 0);
6248 len = INTVAL (XEXP (SET_DEST (x), 1));
6249 pos = XEXP (SET_DEST (x), 2);
6251 /* A constant position should stay within the width of INNER. */
6252 if (GET_CODE (pos) == CONST_INT
6253 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6256 if (BITS_BIG_ENDIAN)
6258 if (GET_CODE (pos) == CONST_INT)
6259 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6261 else if (GET_CODE (pos) == MINUS
6262 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6263 && (INTVAL (XEXP (pos, 1))
6264 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6265 /* If position is ADJUST - X, new position is X. */
6266 pos = XEXP (pos, 0);
6268 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6269 GEN_INT (GET_MODE_BITSIZE (
6276 /* A SUBREG between two modes that occupy the same numbers of words
6277 can be done by moving the SUBREG to the source. */
6278 else if (GET_CODE (SET_DEST (x)) == SUBREG
6279 /* We need SUBREGs to compute nonzero_bits properly. */
6280 && nonzero_sign_valid
6281 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6282 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6283 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6284 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6286 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6288 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6295 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6296 inner = SUBREG_REG (inner);
6298 compute_mode = GET_MODE (inner);
6300 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6301 if (! SCALAR_INT_MODE_P (compute_mode))
6303 enum machine_mode imode;
6305 /* Don't do anything for vector or complex integral types. */
6306 if (! FLOAT_MODE_P (compute_mode))
6309 /* Try to find an integral mode to pun with. */
6310 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6311 if (imode == BLKmode)
6314 compute_mode = imode;
6315 inner = gen_lowpart (imode, inner);
6318 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6319 if (len >= HOST_BITS_PER_WIDE_INT)
6322 /* Now compute the equivalent expression. Make a copy of INNER
6323 for the SET_DEST in case it is a MEM into which we will substitute;
6324 we don't want shared RTL in that case. */
6325 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6326 cleared = simplify_gen_binary (AND, compute_mode,
6327 simplify_gen_unary (NOT, compute_mode,
6328 simplify_gen_binary (ASHIFT,
6333 masked = simplify_gen_binary (ASHIFT, compute_mode,
6334 simplify_gen_binary (
6336 gen_lowpart (compute_mode, SET_SRC (x)),
6340 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6341 simplify_gen_binary (IOR, compute_mode,
6348 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6349 it is an RTX that represents a variable starting position; otherwise,
6350 POS is the (constant) starting bit position (counted from the LSB).
6352 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6355 IN_DEST is nonzero if this is a reference in the destination of a
6356 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6357 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6360 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6361 ZERO_EXTRACT should be built even for bits starting at bit 0.
6363 MODE is the desired mode of the result (if IN_DEST == 0).
6365 The result is an RTX for the extraction or NULL_RTX if the target
6369 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6370 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6371 int in_dest, int in_compare)
6373 /* This mode describes the size of the storage area
6374 to fetch the overall value from. Within that, we
6375 ignore the POS lowest bits, etc. */
6376 enum machine_mode is_mode = GET_MODE (inner);
6377 enum machine_mode inner_mode;
6378 enum machine_mode wanted_inner_mode;
6379 enum machine_mode wanted_inner_reg_mode = word_mode;
6380 enum machine_mode pos_mode = word_mode;
6381 enum machine_mode extraction_mode = word_mode;
6382 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6384 rtx orig_pos_rtx = pos_rtx;
6385 HOST_WIDE_INT orig_pos;
6387 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6389 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6390 consider just the QI as the memory to extract from.
6391 The subreg adds or removes high bits; its mode is
6392 irrelevant to the meaning of this extraction,
6393 since POS and LEN count from the lsb. */
6394 if (MEM_P (SUBREG_REG (inner)))
6395 is_mode = GET_MODE (SUBREG_REG (inner));
6396 inner = SUBREG_REG (inner);
6398 else if (GET_CODE (inner) == ASHIFT
6399 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6400 && pos_rtx == 0 && pos == 0
6401 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6403 /* We're extracting the least significant bits of an rtx
6404 (ashift X (const_int C)), where LEN > C. Extract the
6405 least significant (LEN - C) bits of X, giving an rtx
6406 whose mode is MODE, then shift it left C times. */
6407 new_rtx = make_extraction (mode, XEXP (inner, 0),
6408 0, 0, len - INTVAL (XEXP (inner, 1)),
6409 unsignedp, in_dest, in_compare);
6411 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6414 inner_mode = GET_MODE (inner);
6416 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6417 pos = INTVAL (pos_rtx), pos_rtx = 0;
6419 /* See if this can be done without an extraction. We never can if the
6420 width of the field is not the same as that of some integer mode. For
6421 registers, we can only avoid the extraction if the position is at the
6422 low-order bit and this is either not in the destination or we have the
6423 appropriate STRICT_LOW_PART operation available.
6425 For MEM, we can avoid an extract if the field starts on an appropriate
6426 boundary and we can change the mode of the memory reference. */
6428 if (tmode != BLKmode
6429 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6431 && (inner_mode == tmode
6433 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6434 GET_MODE_BITSIZE (inner_mode))
6435 || reg_truncated_to_mode (tmode, inner))
6438 && have_insn_for (STRICT_LOW_PART, tmode))))
6439 || (MEM_P (inner) && pos_rtx == 0
6441 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6442 : BITS_PER_UNIT)) == 0
6443 /* We can't do this if we are widening INNER_MODE (it
6444 may not be aligned, for one thing). */
6445 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6446 && (inner_mode == tmode
6447 || (! mode_dependent_address_p (XEXP (inner, 0))
6448 && ! MEM_VOLATILE_P (inner))))))
6450 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6451 field. If the original and current mode are the same, we need not
6452 adjust the offset. Otherwise, we do if bytes big endian.
6454 If INNER is not a MEM, get a piece consisting of just the field
6455 of interest (in this case POS % BITS_PER_WORD must be 0). */
6459 HOST_WIDE_INT offset;
6461 /* POS counts from lsb, but make OFFSET count in memory order. */
6462 if (BYTES_BIG_ENDIAN)
6463 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6465 offset = pos / BITS_PER_UNIT;
6467 new_rtx = adjust_address_nv (inner, tmode, offset);
6469 else if (REG_P (inner))
6471 if (tmode != inner_mode)
6473 /* We can't call gen_lowpart in a DEST since we
6474 always want a SUBREG (see below) and it would sometimes
6475 return a new hard register. */
6478 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6480 if (WORDS_BIG_ENDIAN
6481 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6482 final_word = ((GET_MODE_SIZE (inner_mode)
6483 - GET_MODE_SIZE (tmode))
6484 / UNITS_PER_WORD) - final_word;
6486 final_word *= UNITS_PER_WORD;
6487 if (BYTES_BIG_ENDIAN &&
6488 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6489 final_word += (GET_MODE_SIZE (inner_mode)
6490 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6492 /* Avoid creating invalid subregs, for example when
6493 simplifying (x>>32)&255. */
6494 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6497 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6500 new_rtx = gen_lowpart (tmode, inner);
6506 new_rtx = force_to_mode (inner, tmode,
6507 len >= HOST_BITS_PER_WIDE_INT
6508 ? ~(unsigned HOST_WIDE_INT) 0
6509 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6512 /* If this extraction is going into the destination of a SET,
6513 make a STRICT_LOW_PART unless we made a MEM. */
6516 return (MEM_P (new_rtx) ? new_rtx
6517 : (GET_CODE (new_rtx) != SUBREG
6518 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6519 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6524 if (GET_CODE (new_rtx) == CONST_INT)
6525 return gen_int_mode (INTVAL (new_rtx), mode);
6527 /* If we know that no extraneous bits are set, and that the high
6528 bit is not set, convert the extraction to the cheaper of
6529 sign and zero extension, that are equivalent in these cases. */
6530 if (flag_expensive_optimizations
6531 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6532 && ((nonzero_bits (new_rtx, tmode)
6533 & ~(((unsigned HOST_WIDE_INT)
6534 GET_MODE_MASK (tmode))
6538 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6539 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6541 /* Prefer ZERO_EXTENSION, since it gives more information to
6543 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6544 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6549 /* Otherwise, sign- or zero-extend unless we already are in the
6552 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6556 /* Unless this is a COMPARE or we have a funny memory reference,
6557 don't do anything with zero-extending field extracts starting at
6558 the low-order bit since they are simple AND operations. */
6559 if (pos_rtx == 0 && pos == 0 && ! in_dest
6560 && ! in_compare && unsignedp)
6563 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6564 if the position is not a constant and the length is not 1. In all
6565 other cases, we would only be going outside our object in cases when
6566 an original shift would have been undefined. */
6568 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6569 || (pos_rtx != 0 && len != 1)))
6572 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6573 and the mode for the result. */
6574 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6576 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6577 pos_mode = mode_for_extraction (EP_insv, 2);
6578 extraction_mode = mode_for_extraction (EP_insv, 3);
6581 if (! in_dest && unsignedp
6582 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6584 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6585 pos_mode = mode_for_extraction (EP_extzv, 3);
6586 extraction_mode = mode_for_extraction (EP_extzv, 0);
6589 if (! in_dest && ! unsignedp
6590 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6592 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6593 pos_mode = mode_for_extraction (EP_extv, 3);
6594 extraction_mode = mode_for_extraction (EP_extv, 0);
6597 /* Never narrow an object, since that might not be safe. */
6599 if (mode != VOIDmode
6600 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6601 extraction_mode = mode;
6603 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6604 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6605 pos_mode = GET_MODE (pos_rtx);
6607 /* If this is not from memory, the desired mode is the preferred mode
6608 for an extraction pattern's first input operand, or word_mode if there
6611 wanted_inner_mode = wanted_inner_reg_mode;
6614 /* Be careful not to go beyond the extracted object and maintain the
6615 natural alignment of the memory. */
6616 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6617 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6618 > GET_MODE_BITSIZE (wanted_inner_mode))
6620 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6621 gcc_assert (wanted_inner_mode != VOIDmode);
6624 /* If we have to change the mode of memory and cannot, the desired mode
6625 is EXTRACTION_MODE. */
6626 if (inner_mode != wanted_inner_mode
6627 && (mode_dependent_address_p (XEXP (inner, 0))
6628 || MEM_VOLATILE_P (inner)
6630 wanted_inner_mode = extraction_mode;
6635 if (BITS_BIG_ENDIAN)
6637 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6638 BITS_BIG_ENDIAN style. If position is constant, compute new
6639 position. Otherwise, build subtraction.
6640 Note that POS is relative to the mode of the original argument.
6641 If it's a MEM we need to recompute POS relative to that.
6642 However, if we're extracting from (or inserting into) a register,
6643 we want to recompute POS relative to wanted_inner_mode. */
6644 int width = (MEM_P (inner)
6645 ? GET_MODE_BITSIZE (is_mode)
6646 : GET_MODE_BITSIZE (wanted_inner_mode));
6649 pos = width - len - pos;
6652 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6653 /* POS may be less than 0 now, but we check for that below.
6654 Note that it can only be less than 0 if !MEM_P (inner). */
6657 /* If INNER has a wider mode, and this is a constant extraction, try to
6658 make it smaller and adjust the byte to point to the byte containing
6660 if (wanted_inner_mode != VOIDmode
6661 && inner_mode != wanted_inner_mode
6663 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6665 && ! mode_dependent_address_p (XEXP (inner, 0))
6666 && ! MEM_VOLATILE_P (inner))
6670 /* The computations below will be correct if the machine is big
6671 endian in both bits and bytes or little endian in bits and bytes.
6672 If it is mixed, we must adjust. */
6674 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6675 adjust OFFSET to compensate. */
6676 if (BYTES_BIG_ENDIAN
6677 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6678 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6680 /* We can now move to the desired byte. */
6681 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6682 * GET_MODE_SIZE (wanted_inner_mode);
6683 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6685 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6686 && is_mode != wanted_inner_mode)
6687 offset = (GET_MODE_SIZE (is_mode)
6688 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6690 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6693 /* If INNER is not memory, we can always get it into the proper mode. If we
6694 are changing its mode, POS must be a constant and smaller than the size
6696 else if (!MEM_P (inner))
6698 if (GET_MODE (inner) != wanted_inner_mode
6700 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6706 inner = force_to_mode (inner, wanted_inner_mode,
6708 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6709 ? ~(unsigned HOST_WIDE_INT) 0
6710 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6715 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6716 have to zero extend. Otherwise, we can just use a SUBREG. */
6718 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6720 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6722 /* If we know that no extraneous bits are set, and that the high
6723 bit is not set, convert extraction to cheaper one - either
6724 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6726 if (flag_expensive_optimizations
6727 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6728 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6729 & ~(((unsigned HOST_WIDE_INT)
6730 GET_MODE_MASK (GET_MODE (pos_rtx)))
6734 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6736 /* Prefer ZERO_EXTENSION, since it gives more information to
6738 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6739 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6744 else if (pos_rtx != 0
6745 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6746 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6748 /* Make POS_RTX unless we already have it and it is correct. If we don't
6749 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6751 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6752 pos_rtx = orig_pos_rtx;
6754 else if (pos_rtx == 0)
6755 pos_rtx = GEN_INT (pos);
6757 /* Make the required operation. See if we can use existing rtx. */
6758 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6759 extraction_mode, inner, GEN_INT (len), pos_rtx);
6761 new_rtx = gen_lowpart (mode, new_rtx);
6766 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6767 with any other operations in X. Return X without that shift if so. */
6770 extract_left_shift (rtx x, int count)
6772 enum rtx_code code = GET_CODE (x);
6773 enum machine_mode mode = GET_MODE (x);
6779 /* This is the shift itself. If it is wide enough, we will return
6780 either the value being shifted if the shift count is equal to
6781 COUNT or a shift for the difference. */
6782 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6783 && INTVAL (XEXP (x, 1)) >= count)
6784 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6785 INTVAL (XEXP (x, 1)) - count);
6789 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6790 return simplify_gen_unary (code, mode, tem, mode);
6794 case PLUS: case IOR: case XOR: case AND:
6795 /* If we can safely shift this constant and we find the inner shift,
6796 make a new operation. */
6797 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6798 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6799 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6800 return simplify_gen_binary (code, mode, tem,
6801 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6812 /* Look at the expression rooted at X. Look for expressions
6813 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6814 Form these expressions.
6816 Return the new rtx, usually just X.
6818 Also, for machines like the VAX that don't have logical shift insns,
6819 try to convert logical to arithmetic shift operations in cases where
6820 they are equivalent. This undoes the canonicalizations to logical
6821 shifts done elsewhere.
6823 We try, as much as possible, to re-use rtl expressions to save memory.
6825 IN_CODE says what kind of expression we are processing. Normally, it is
6826 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6827 being kludges), it is MEM. When processing the arguments of a comparison
6828 or a COMPARE against zero, it is COMPARE. */
6831 make_compound_operation (rtx x, enum rtx_code in_code)
6833 enum rtx_code code = GET_CODE (x);
6834 enum machine_mode mode = GET_MODE (x);
6835 int mode_width = GET_MODE_BITSIZE (mode);
6837 enum rtx_code next_code;
6843 /* Select the code to be used in recursive calls. Once we are inside an
6844 address, we stay there. If we have a comparison, set to COMPARE,
6845 but once inside, go back to our default of SET. */
6847 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6848 : ((code == COMPARE || COMPARISON_P (x))
6849 && XEXP (x, 1) == const0_rtx) ? COMPARE
6850 : in_code == COMPARE ? SET : in_code);
6852 /* Process depending on the code of this operation. If NEW is set
6853 nonzero, it will be returned. */
6858 /* Convert shifts by constants into multiplications if inside
6860 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6861 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6862 && INTVAL (XEXP (x, 1)) >= 0)
6864 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6865 new_rtx = gen_rtx_MULT (mode, new_rtx,
6866 GEN_INT ((HOST_WIDE_INT) 1
6867 << INTVAL (XEXP (x, 1))));
6872 /* If the second operand is not a constant, we can't do anything
6874 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6877 /* If the constant is a power of two minus one and the first operand
6878 is a logical right shift, make an extraction. */
6879 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6880 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6882 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6883 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6884 0, in_code == COMPARE);
6887 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6888 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6889 && subreg_lowpart_p (XEXP (x, 0))
6890 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6891 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6893 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6895 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6896 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6897 0, in_code == COMPARE);
6899 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6900 else if ((GET_CODE (XEXP (x, 0)) == XOR
6901 || GET_CODE (XEXP (x, 0)) == IOR)
6902 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6903 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6904 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6906 /* Apply the distributive law, and then try to make extractions. */
6907 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6908 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6910 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6912 new_rtx = make_compound_operation (new_rtx, in_code);
6915 /* If we are have (and (rotate X C) M) and C is larger than the number
6916 of bits in M, this is an extraction. */
6918 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6919 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6920 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6921 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6923 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6924 new_rtx = make_extraction (mode, new_rtx,
6925 (GET_MODE_BITSIZE (mode)
6926 - INTVAL (XEXP (XEXP (x, 0), 1))),
6927 NULL_RTX, i, 1, 0, in_code == COMPARE);
6930 /* On machines without logical shifts, if the operand of the AND is
6931 a logical shift and our mask turns off all the propagated sign
6932 bits, we can replace the logical shift with an arithmetic shift. */
6933 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6934 && !have_insn_for (LSHIFTRT, mode)
6935 && have_insn_for (ASHIFTRT, mode)
6936 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6937 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6938 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6939 && mode_width <= HOST_BITS_PER_WIDE_INT)
6941 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6943 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6944 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6946 gen_rtx_ASHIFTRT (mode,
6947 make_compound_operation
6948 (XEXP (XEXP (x, 0), 0), next_code),
6949 XEXP (XEXP (x, 0), 1)));
6952 /* If the constant is one less than a power of two, this might be
6953 representable by an extraction even if no shift is present.
6954 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6955 we are in a COMPARE. */
6956 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6957 new_rtx = make_extraction (mode,
6958 make_compound_operation (XEXP (x, 0),
6960 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6962 /* If we are in a comparison and this is an AND with a power of two,
6963 convert this into the appropriate bit extract. */
6964 else if (in_code == COMPARE
6965 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6966 new_rtx = make_extraction (mode,
6967 make_compound_operation (XEXP (x, 0),
6969 i, NULL_RTX, 1, 1, 0, 1);
6974 /* If the sign bit is known to be zero, replace this with an
6975 arithmetic shift. */
6976 if (have_insn_for (ASHIFTRT, mode)
6977 && ! have_insn_for (LSHIFTRT, mode)
6978 && mode_width <= HOST_BITS_PER_WIDE_INT
6979 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6981 new_rtx = gen_rtx_ASHIFTRT (mode,
6982 make_compound_operation (XEXP (x, 0),
6988 /* ... fall through ... */
6994 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6995 this is a SIGN_EXTRACT. */
6996 if (GET_CODE (rhs) == CONST_INT
6997 && GET_CODE (lhs) == ASHIFT
6998 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6999 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
7001 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7002 new_rtx = make_extraction (mode, new_rtx,
7003 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7004 NULL_RTX, mode_width - INTVAL (rhs),
7005 code == LSHIFTRT, 0, in_code == COMPARE);
7009 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7010 If so, try to merge the shifts into a SIGN_EXTEND. We could
7011 also do this for some cases of SIGN_EXTRACT, but it doesn't
7012 seem worth the effort; the case checked for occurs on Alpha. */
7015 && ! (GET_CODE (lhs) == SUBREG
7016 && (OBJECT_P (SUBREG_REG (lhs))))
7017 && GET_CODE (rhs) == CONST_INT
7018 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7019 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7020 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7021 0, NULL_RTX, mode_width - INTVAL (rhs),
7022 code == LSHIFTRT, 0, in_code == COMPARE);
7027 /* Call ourselves recursively on the inner expression. If we are
7028 narrowing the object and it has a different RTL code from
7029 what it originally did, do this SUBREG as a force_to_mode. */
7031 tem = make_compound_operation (SUBREG_REG (x), in_code);
7035 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7041 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7042 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7043 && subreg_lowpart_p (x))
7045 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7048 /* If we have something other than a SUBREG, we might have
7049 done an expansion, so rerun ourselves. */
7050 if (GET_CODE (newer) != SUBREG)
7051 newer = make_compound_operation (newer, in_code);
7067 x = gen_lowpart (mode, new_rtx);
7068 code = GET_CODE (x);
7071 /* Now recursively process each operand of this operation. */
7072 fmt = GET_RTX_FORMAT (code);
7073 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7076 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7077 SUBST (XEXP (x, i), new_rtx);
7079 else if (fmt[i] == 'E')
7080 for (j = 0; j < XVECLEN (x, i); j++)
7082 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7083 SUBST (XVECEXP (x, i, j), new_rtx);
7086 /* If this is a commutative operation, the changes to the operands
7087 may have made it noncanonical. */
7088 if (COMMUTATIVE_ARITH_P (x)
7089 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7092 SUBST (XEXP (x, 0), XEXP (x, 1));
7093 SUBST (XEXP (x, 1), tem);
7099 /* Given M see if it is a value that would select a field of bits
7100 within an item, but not the entire word. Return -1 if not.
7101 Otherwise, return the starting position of the field, where 0 is the
7104 *PLEN is set to the length of the field. */
7107 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7109 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7110 int pos = exact_log2 (m & -m);
7114 /* Now shift off the low-order zero bits and see if we have a
7115 power of two minus 1. */
7116 len = exact_log2 ((m >> pos) + 1);
7125 /* If X refers to a register that equals REG in value, replace these
7126 references with REG. */
7128 canon_reg_for_combine (rtx x, rtx reg)
7135 enum rtx_code code = GET_CODE (x);
7136 switch (GET_RTX_CLASS (code))
7139 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7140 if (op0 != XEXP (x, 0))
7141 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7146 case RTX_COMM_ARITH:
7147 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7148 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7149 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7150 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7154 case RTX_COMM_COMPARE:
7155 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7156 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7157 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7158 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7159 GET_MODE (op0), op0, op1);
7163 case RTX_BITFIELD_OPS:
7164 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7165 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7166 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7167 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7168 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7169 GET_MODE (op0), op0, op1, op2);
7174 if (rtx_equal_p (get_last_value (reg), x)
7175 || rtx_equal_p (reg, get_last_value (x)))
7184 fmt = GET_RTX_FORMAT (code);
7186 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7189 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7190 if (op != XEXP (x, i))
7200 else if (fmt[i] == 'E')
7203 for (j = 0; j < XVECLEN (x, i); j++)
7205 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7206 if (op != XVECEXP (x, i, j))
7213 XVECEXP (x, i, j) = op;
7224 /* Return X converted to MODE. If the value is already truncated to
7225 MODE we can just return a subreg even though in the general case we
7226 would need an explicit truncation. */
7229 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7231 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7232 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7233 GET_MODE_BITSIZE (GET_MODE (x)))
7234 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7235 return gen_lowpart (mode, x);
7237 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7240 /* See if X can be simplified knowing that we will only refer to it in
7241 MODE and will only refer to those bits that are nonzero in MASK.
7242 If other bits are being computed or if masking operations are done
7243 that select a superset of the bits in MASK, they can sometimes be
7246 Return a possibly simplified expression, but always convert X to
7247 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7249 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7250 are all off in X. This is used when X will be complemented, by either
7251 NOT, NEG, or XOR. */
7254 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7257 enum rtx_code code = GET_CODE (x);
7258 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7259 enum machine_mode op_mode;
7260 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7263 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7264 code below will do the wrong thing since the mode of such an
7265 expression is VOIDmode.
7267 Also do nothing if X is a CLOBBER; this can happen if X was
7268 the return value from a call to gen_lowpart. */
7269 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7272 /* We want to perform the operation is its present mode unless we know
7273 that the operation is valid in MODE, in which case we do the operation
7275 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7276 && have_insn_for (code, mode))
7277 ? mode : GET_MODE (x));
7279 /* It is not valid to do a right-shift in a narrower mode
7280 than the one it came in with. */
7281 if ((code == LSHIFTRT || code == ASHIFTRT)
7282 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7283 op_mode = GET_MODE (x);
7285 /* Truncate MASK to fit OP_MODE. */
7287 mask &= GET_MODE_MASK (op_mode);
7289 /* When we have an arithmetic operation, or a shift whose count we
7290 do not know, we need to assume that all bits up to the highest-order
7291 bit in MASK will be needed. This is how we form such a mask. */
7292 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7293 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7295 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7298 /* Determine what bits of X are guaranteed to be (non)zero. */
7299 nonzero = nonzero_bits (x, mode);
7301 /* If none of the bits in X are needed, return a zero. */
7302 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7305 /* If X is a CONST_INT, return a new one. Do this here since the
7306 test below will fail. */
7307 if (GET_CODE (x) == CONST_INT)
7309 if (SCALAR_INT_MODE_P (mode))
7310 return gen_int_mode (INTVAL (x) & mask, mode);
7313 x = GEN_INT (INTVAL (x) & mask);
7314 return gen_lowpart_common (mode, x);
7318 /* If X is narrower than MODE and we want all the bits in X's mode, just
7319 get X in the proper mode. */
7320 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7321 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7322 return gen_lowpart (mode, x);
7327 /* If X is a (clobber (const_int)), return it since we know we are
7328 generating something that won't match. */
7335 x = expand_compound_operation (x);
7336 if (GET_CODE (x) != code)
7337 return force_to_mode (x, mode, mask, next_select);
7341 if (subreg_lowpart_p (x)
7342 /* We can ignore the effect of this SUBREG if it narrows the mode or
7343 if the constant masks to zero all the bits the mode doesn't
7345 && ((GET_MODE_SIZE (GET_MODE (x))
7346 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7348 & GET_MODE_MASK (GET_MODE (x))
7349 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7350 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7354 /* If this is an AND with a constant, convert it into an AND
7355 whose constant is the AND of that constant with MASK. If it
7356 remains an AND of MASK, delete it since it is redundant. */
7358 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7360 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7361 mask & INTVAL (XEXP (x, 1)));
7363 /* If X is still an AND, see if it is an AND with a mask that
7364 is just some low-order bits. If so, and it is MASK, we don't
7367 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7368 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7372 /* If it remains an AND, try making another AND with the bits
7373 in the mode mask that aren't in MASK turned on. If the
7374 constant in the AND is wide enough, this might make a
7375 cheaper constant. */
7377 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7378 && GET_MODE_MASK (GET_MODE (x)) != mask
7379 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7381 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7382 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7383 int width = GET_MODE_BITSIZE (GET_MODE (x));
7386 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7387 number, sign extend it. */
7388 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7389 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7390 cval |= (HOST_WIDE_INT) -1 << width;
7392 y = simplify_gen_binary (AND, GET_MODE (x),
7393 XEXP (x, 0), GEN_INT (cval));
7394 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7395 < rtx_cost (x, SET, optimize_this_for_speed_p))
7405 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7406 low-order bits (as in an alignment operation) and FOO is already
7407 aligned to that boundary, mask C1 to that boundary as well.
7408 This may eliminate that PLUS and, later, the AND. */
7411 unsigned int width = GET_MODE_BITSIZE (mode);
7412 unsigned HOST_WIDE_INT smask = mask;
7414 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7415 number, sign extend it. */
7417 if (width < HOST_BITS_PER_WIDE_INT
7418 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7419 smask |= (HOST_WIDE_INT) -1 << width;
7421 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7422 && exact_log2 (- smask) >= 0
7423 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7424 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7425 return force_to_mode (plus_constant (XEXP (x, 0),
7426 (INTVAL (XEXP (x, 1)) & smask)),
7427 mode, smask, next_select);
7430 /* ... fall through ... */
7433 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7434 most significant bit in MASK since carries from those bits will
7435 affect the bits we are interested in. */
7440 /* If X is (minus C Y) where C's least set bit is larger than any bit
7441 in the mask, then we may replace with (neg Y). */
7442 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7443 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7444 & -INTVAL (XEXP (x, 0))))
7447 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7449 return force_to_mode (x, mode, mask, next_select);
7452 /* Similarly, if C contains every bit in the fuller_mask, then we may
7453 replace with (not Y). */
7454 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7455 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7456 == INTVAL (XEXP (x, 0))))
7458 x = simplify_gen_unary (NOT, GET_MODE (x),
7459 XEXP (x, 1), GET_MODE (x));
7460 return force_to_mode (x, mode, mask, next_select);
7468 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7469 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7470 operation which may be a bitfield extraction. Ensure that the
7471 constant we form is not wider than the mode of X. */
7473 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7474 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7475 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7476 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7477 && GET_CODE (XEXP (x, 1)) == CONST_INT
7478 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7479 + floor_log2 (INTVAL (XEXP (x, 1))))
7480 < GET_MODE_BITSIZE (GET_MODE (x)))
7481 && (INTVAL (XEXP (x, 1))
7482 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7484 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7485 << INTVAL (XEXP (XEXP (x, 0), 1)));
7486 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7487 XEXP (XEXP (x, 0), 0), temp);
7488 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7489 XEXP (XEXP (x, 0), 1));
7490 return force_to_mode (x, mode, mask, next_select);
7494 /* For most binary operations, just propagate into the operation and
7495 change the mode if we have an operation of that mode. */
7497 op0 = gen_lowpart_or_truncate (op_mode,
7498 force_to_mode (XEXP (x, 0), mode, mask,
7500 op1 = gen_lowpart_or_truncate (op_mode,
7501 force_to_mode (XEXP (x, 1), mode, mask,
7504 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7505 x = simplify_gen_binary (code, op_mode, op0, op1);
7509 /* For left shifts, do the same, but just for the first operand.
7510 However, we cannot do anything with shifts where we cannot
7511 guarantee that the counts are smaller than the size of the mode
7512 because such a count will have a different meaning in a
7515 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7516 && INTVAL (XEXP (x, 1)) >= 0
7517 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7518 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7519 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7520 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7523 /* If the shift count is a constant and we can do arithmetic in
7524 the mode of the shift, refine which bits we need. Otherwise, use the
7525 conservative form of the mask. */
7526 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7527 && INTVAL (XEXP (x, 1)) >= 0
7528 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7529 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7530 mask >>= INTVAL (XEXP (x, 1));
7534 op0 = gen_lowpart_or_truncate (op_mode,
7535 force_to_mode (XEXP (x, 0), op_mode,
7536 mask, next_select));
7538 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7539 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7543 /* Here we can only do something if the shift count is a constant,
7544 this shift constant is valid for the host, and we can do arithmetic
7547 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7548 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7549 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7551 rtx inner = XEXP (x, 0);
7552 unsigned HOST_WIDE_INT inner_mask;
7554 /* Select the mask of the bits we need for the shift operand. */
7555 inner_mask = mask << INTVAL (XEXP (x, 1));
7557 /* We can only change the mode of the shift if we can do arithmetic
7558 in the mode of the shift and INNER_MASK is no wider than the
7559 width of X's mode. */
7560 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7561 op_mode = GET_MODE (x);
7563 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7565 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7566 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7569 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7570 shift and AND produces only copies of the sign bit (C2 is one less
7571 than a power of two), we can do this with just a shift. */
7573 if (GET_CODE (x) == LSHIFTRT
7574 && GET_CODE (XEXP (x, 1)) == CONST_INT
7575 /* The shift puts one of the sign bit copies in the least significant
7577 && ((INTVAL (XEXP (x, 1))
7578 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7579 >= GET_MODE_BITSIZE (GET_MODE (x)))
7580 && exact_log2 (mask + 1) >= 0
7581 /* Number of bits left after the shift must be more than the mask
7583 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7584 <= GET_MODE_BITSIZE (GET_MODE (x)))
7585 /* Must be more sign bit copies than the mask needs. */
7586 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7587 >= exact_log2 (mask + 1)))
7588 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7589 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7590 - exact_log2 (mask + 1)));
7595 /* If we are just looking for the sign bit, we don't need this shift at
7596 all, even if it has a variable count. */
7597 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7598 && (mask == ((unsigned HOST_WIDE_INT) 1
7599 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7600 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7602 /* If this is a shift by a constant, get a mask that contains those bits
7603 that are not copies of the sign bit. We then have two cases: If
7604 MASK only includes those bits, this can be a logical shift, which may
7605 allow simplifications. If MASK is a single-bit field not within
7606 those bits, we are requesting a copy of the sign bit and hence can
7607 shift the sign bit to the appropriate location. */
7609 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7610 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7614 /* If the considered data is wider than HOST_WIDE_INT, we can't
7615 represent a mask for all its bits in a single scalar.
7616 But we only care about the lower bits, so calculate these. */
7618 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7620 nonzero = ~(HOST_WIDE_INT) 0;
7622 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7623 is the number of bits a full-width mask would have set.
7624 We need only shift if these are fewer than nonzero can
7625 hold. If not, we must keep all bits set in nonzero. */
7627 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7628 < HOST_BITS_PER_WIDE_INT)
7629 nonzero >>= INTVAL (XEXP (x, 1))
7630 + HOST_BITS_PER_WIDE_INT
7631 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7635 nonzero = GET_MODE_MASK (GET_MODE (x));
7636 nonzero >>= INTVAL (XEXP (x, 1));
7639 if ((mask & ~nonzero) == 0)
7641 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7642 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7643 if (GET_CODE (x) != ASHIFTRT)
7644 return force_to_mode (x, mode, mask, next_select);
7647 else if ((i = exact_log2 (mask)) >= 0)
7649 x = simplify_shift_const
7650 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7651 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7653 if (GET_CODE (x) != ASHIFTRT)
7654 return force_to_mode (x, mode, mask, next_select);
7658 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7659 even if the shift count isn't a constant. */
7661 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7662 XEXP (x, 0), XEXP (x, 1));
7666 /* If this is a zero- or sign-extension operation that just affects bits
7667 we don't care about, remove it. Be sure the call above returned
7668 something that is still a shift. */
7670 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7671 && GET_CODE (XEXP (x, 1)) == CONST_INT
7672 && INTVAL (XEXP (x, 1)) >= 0
7673 && (INTVAL (XEXP (x, 1))
7674 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7675 && GET_CODE (XEXP (x, 0)) == ASHIFT
7676 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7677 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7684 /* If the shift count is constant and we can do computations
7685 in the mode of X, compute where the bits we care about are.
7686 Otherwise, we can't do anything. Don't change the mode of
7687 the shift or propagate MODE into the shift, though. */
7688 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7689 && INTVAL (XEXP (x, 1)) >= 0)
7691 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7692 GET_MODE (x), GEN_INT (mask),
7694 if (temp && GET_CODE (temp) == CONST_INT)
7696 force_to_mode (XEXP (x, 0), GET_MODE (x),
7697 INTVAL (temp), next_select));
7702 /* If we just want the low-order bit, the NEG isn't needed since it
7703 won't change the low-order bit. */
7705 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7707 /* We need any bits less significant than the most significant bit in
7708 MASK since carries from those bits will affect the bits we are
7714 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7715 same as the XOR case above. Ensure that the constant we form is not
7716 wider than the mode of X. */
7718 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7719 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7720 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7721 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7722 < GET_MODE_BITSIZE (GET_MODE (x)))
7723 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7725 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7727 temp = simplify_gen_binary (XOR, GET_MODE (x),
7728 XEXP (XEXP (x, 0), 0), temp);
7729 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7730 temp, XEXP (XEXP (x, 0), 1));
7732 return force_to_mode (x, mode, mask, next_select);
7735 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7736 use the full mask inside the NOT. */
7740 op0 = gen_lowpart_or_truncate (op_mode,
7741 force_to_mode (XEXP (x, 0), mode, mask,
7743 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7744 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7748 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7749 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7750 which is equal to STORE_FLAG_VALUE. */
7751 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7752 && GET_MODE (XEXP (x, 0)) == mode
7753 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7754 && (nonzero_bits (XEXP (x, 0), mode)
7755 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7756 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7761 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7762 written in a narrower mode. We play it safe and do not do so. */
7765 gen_lowpart_or_truncate (GET_MODE (x),
7766 force_to_mode (XEXP (x, 1), mode,
7767 mask, next_select)));
7769 gen_lowpart_or_truncate (GET_MODE (x),
7770 force_to_mode (XEXP (x, 2), mode,
7771 mask, next_select)));
7778 /* Ensure we return a value of the proper mode. */
7779 return gen_lowpart_or_truncate (mode, x);
7782 /* Return nonzero if X is an expression that has one of two values depending on
7783 whether some other value is zero or nonzero. In that case, we return the
7784 value that is being tested, *PTRUE is set to the value if the rtx being
7785 returned has a nonzero value, and *PFALSE is set to the other alternative.
7787 If we return zero, we set *PTRUE and *PFALSE to X. */
7790 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7792 enum machine_mode mode = GET_MODE (x);
7793 enum rtx_code code = GET_CODE (x);
7794 rtx cond0, cond1, true0, true1, false0, false1;
7795 unsigned HOST_WIDE_INT nz;
7797 /* If we are comparing a value against zero, we are done. */
7798 if ((code == NE || code == EQ)
7799 && XEXP (x, 1) == const0_rtx)
7801 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7802 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7806 /* If this is a unary operation whose operand has one of two values, apply
7807 our opcode to compute those values. */
7808 else if (UNARY_P (x)
7809 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7811 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7812 *pfalse = simplify_gen_unary (code, mode, false0,
7813 GET_MODE (XEXP (x, 0)));
7817 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7818 make can't possibly match and would suppress other optimizations. */
7819 else if (code == COMPARE)
7822 /* If this is a binary operation, see if either side has only one of two
7823 values. If either one does or if both do and they are conditional on
7824 the same value, compute the new true and false values. */
7825 else if (BINARY_P (x))
7827 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7828 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7830 if ((cond0 != 0 || cond1 != 0)
7831 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7833 /* If if_then_else_cond returned zero, then true/false are the
7834 same rtl. We must copy one of them to prevent invalid rtl
7837 true0 = copy_rtx (true0);
7838 else if (cond1 == 0)
7839 true1 = copy_rtx (true1);
7841 if (COMPARISON_P (x))
7843 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7845 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7850 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7851 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7854 return cond0 ? cond0 : cond1;
7857 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7858 operands is zero when the other is nonzero, and vice-versa,
7859 and STORE_FLAG_VALUE is 1 or -1. */
7861 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7862 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7864 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7866 rtx op0 = XEXP (XEXP (x, 0), 1);
7867 rtx op1 = XEXP (XEXP (x, 1), 1);
7869 cond0 = XEXP (XEXP (x, 0), 0);
7870 cond1 = XEXP (XEXP (x, 1), 0);
7872 if (COMPARISON_P (cond0)
7873 && COMPARISON_P (cond1)
7874 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7875 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7876 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7877 || ((swap_condition (GET_CODE (cond0))
7878 == reversed_comparison_code (cond1, NULL))
7879 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7880 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7881 && ! side_effects_p (x))
7883 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7884 *pfalse = simplify_gen_binary (MULT, mode,
7886 ? simplify_gen_unary (NEG, mode,
7894 /* Similarly for MULT, AND and UMIN, except that for these the result
7896 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7897 && (code == MULT || code == AND || code == UMIN)
7898 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7900 cond0 = XEXP (XEXP (x, 0), 0);
7901 cond1 = XEXP (XEXP (x, 1), 0);
7903 if (COMPARISON_P (cond0)
7904 && COMPARISON_P (cond1)
7905 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7906 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7907 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7908 || ((swap_condition (GET_CODE (cond0))
7909 == reversed_comparison_code (cond1, NULL))
7910 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7911 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7912 && ! side_effects_p (x))
7914 *ptrue = *pfalse = const0_rtx;
7920 else if (code == IF_THEN_ELSE)
7922 /* If we have IF_THEN_ELSE already, extract the condition and
7923 canonicalize it if it is NE or EQ. */
7924 cond0 = XEXP (x, 0);
7925 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7926 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7927 return XEXP (cond0, 0);
7928 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7930 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7931 return XEXP (cond0, 0);
7937 /* If X is a SUBREG, we can narrow both the true and false values
7938 if the inner expression, if there is a condition. */
7939 else if (code == SUBREG
7940 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7943 true0 = simplify_gen_subreg (mode, true0,
7944 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7945 false0 = simplify_gen_subreg (mode, false0,
7946 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7947 if (true0 && false0)
7955 /* If X is a constant, this isn't special and will cause confusions
7956 if we treat it as such. Likewise if it is equivalent to a constant. */
7957 else if (CONSTANT_P (x)
7958 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7961 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7962 will be least confusing to the rest of the compiler. */
7963 else if (mode == BImode)
7965 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7969 /* If X is known to be either 0 or -1, those are the true and
7970 false values when testing X. */
7971 else if (x == constm1_rtx || x == const0_rtx
7972 || (mode != VOIDmode
7973 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7975 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7979 /* Likewise for 0 or a single bit. */
7980 else if (SCALAR_INT_MODE_P (mode)
7981 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7982 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7984 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7988 /* Otherwise fail; show no condition with true and false values the same. */
7989 *ptrue = *pfalse = x;
7993 /* Return the value of expression X given the fact that condition COND
7994 is known to be true when applied to REG as its first operand and VAL
7995 as its second. X is known to not be shared and so can be modified in
7998 We only handle the simplest cases, and specifically those cases that
7999 arise with IF_THEN_ELSE expressions. */
8002 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8004 enum rtx_code code = GET_CODE (x);
8009 if (side_effects_p (x))
8012 /* If either operand of the condition is a floating point value,
8013 then we have to avoid collapsing an EQ comparison. */
8015 && rtx_equal_p (x, reg)
8016 && ! FLOAT_MODE_P (GET_MODE (x))
8017 && ! FLOAT_MODE_P (GET_MODE (val)))
8020 if (cond == UNEQ && rtx_equal_p (x, reg))
8023 /* If X is (abs REG) and we know something about REG's relationship
8024 with zero, we may be able to simplify this. */
8026 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8029 case GE: case GT: case EQ:
8032 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8034 GET_MODE (XEXP (x, 0)));
8039 /* The only other cases we handle are MIN, MAX, and comparisons if the
8040 operands are the same as REG and VAL. */
8042 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8044 if (rtx_equal_p (XEXP (x, 0), val))
8045 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8047 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8049 if (COMPARISON_P (x))
8051 if (comparison_dominates_p (cond, code))
8052 return const_true_rtx;
8054 code = reversed_comparison_code (x, NULL);
8056 && comparison_dominates_p (cond, code))
8061 else if (code == SMAX || code == SMIN
8062 || code == UMIN || code == UMAX)
8064 int unsignedp = (code == UMIN || code == UMAX);
8066 /* Do not reverse the condition when it is NE or EQ.
8067 This is because we cannot conclude anything about
8068 the value of 'SMAX (x, y)' when x is not equal to y,
8069 but we can when x equals y. */
8070 if ((code == SMAX || code == UMAX)
8071 && ! (cond == EQ || cond == NE))
8072 cond = reverse_condition (cond);
8077 return unsignedp ? x : XEXP (x, 1);
8079 return unsignedp ? x : XEXP (x, 0);
8081 return unsignedp ? XEXP (x, 1) : x;
8083 return unsignedp ? XEXP (x, 0) : x;
8090 else if (code == SUBREG)
8092 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8093 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8095 if (SUBREG_REG (x) != r)
8097 /* We must simplify subreg here, before we lose track of the
8098 original inner_mode. */
8099 new_rtx = simplify_subreg (GET_MODE (x), r,
8100 inner_mode, SUBREG_BYTE (x));
8104 SUBST (SUBREG_REG (x), r);
8109 /* We don't have to handle SIGN_EXTEND here, because even in the
8110 case of replacing something with a modeless CONST_INT, a
8111 CONST_INT is already (supposed to be) a valid sign extension for
8112 its narrower mode, which implies it's already properly
8113 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8114 story is different. */
8115 else if (code == ZERO_EXTEND)
8117 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8118 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8120 if (XEXP (x, 0) != r)
8122 /* We must simplify the zero_extend here, before we lose
8123 track of the original inner_mode. */
8124 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8129 SUBST (XEXP (x, 0), r);
8135 fmt = GET_RTX_FORMAT (code);
8136 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8139 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8140 else if (fmt[i] == 'E')
8141 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8142 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8149 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8150 assignment as a field assignment. */
8153 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8155 if (x == y || rtx_equal_p (x, y))
8158 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8161 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8162 Note that all SUBREGs of MEM are paradoxical; otherwise they
8163 would have been rewritten. */
8164 if (MEM_P (x) && GET_CODE (y) == SUBREG
8165 && MEM_P (SUBREG_REG (y))
8166 && rtx_equal_p (SUBREG_REG (y),
8167 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8170 if (MEM_P (y) && GET_CODE (x) == SUBREG
8171 && MEM_P (SUBREG_REG (x))
8172 && rtx_equal_p (SUBREG_REG (x),
8173 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8176 /* We used to see if get_last_value of X and Y were the same but that's
8177 not correct. In one direction, we'll cause the assignment to have
8178 the wrong destination and in the case, we'll import a register into this
8179 insn that might have already have been dead. So fail if none of the
8180 above cases are true. */
8184 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8185 Return that assignment if so.
8187 We only handle the most common cases. */
8190 make_field_assignment (rtx x)
8192 rtx dest = SET_DEST (x);
8193 rtx src = SET_SRC (x);
8198 unsigned HOST_WIDE_INT len;
8200 enum machine_mode mode;
8202 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8203 a clear of a one-bit field. We will have changed it to
8204 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8207 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8208 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8209 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8210 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8212 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8215 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8219 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8220 && subreg_lowpart_p (XEXP (src, 0))
8221 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8222 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8223 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8224 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8225 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8226 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8228 assign = make_extraction (VOIDmode, dest, 0,
8229 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8232 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8236 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8238 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8239 && XEXP (XEXP (src, 0), 0) == const1_rtx
8240 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8242 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8245 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8249 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8250 SRC is an AND with all bits of that field set, then we can discard
8252 if (GET_CODE (dest) == ZERO_EXTRACT
8253 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8254 && GET_CODE (src) == AND
8255 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8257 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8258 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8259 unsigned HOST_WIDE_INT ze_mask;
8261 if (width >= HOST_BITS_PER_WIDE_INT)
8264 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8266 /* Complete overlap. We can remove the source AND. */
8267 if ((and_mask & ze_mask) == ze_mask)
8268 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8270 /* Partial overlap. We can reduce the source AND. */
8271 if ((and_mask & ze_mask) != and_mask)
8273 mode = GET_MODE (src);
8274 src = gen_rtx_AND (mode, XEXP (src, 0),
8275 gen_int_mode (and_mask & ze_mask, mode));
8276 return gen_rtx_SET (VOIDmode, dest, src);
8280 /* The other case we handle is assignments into a constant-position
8281 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8282 a mask that has all one bits except for a group of zero bits and
8283 OTHER is known to have zeros where C1 has ones, this is such an
8284 assignment. Compute the position and length from C1. Shift OTHER
8285 to the appropriate position, force it to the required mode, and
8286 make the extraction. Check for the AND in both operands. */
8288 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8291 rhs = expand_compound_operation (XEXP (src, 0));
8292 lhs = expand_compound_operation (XEXP (src, 1));
8294 if (GET_CODE (rhs) == AND
8295 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8296 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8297 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8298 else if (GET_CODE (lhs) == AND
8299 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8300 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8301 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8305 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8306 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8307 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8308 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8311 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8315 /* The mode to use for the source is the mode of the assignment, or of
8316 what is inside a possible STRICT_LOW_PART. */
8317 mode = (GET_CODE (assign) == STRICT_LOW_PART
8318 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8320 /* Shift OTHER right POS places and make it the source, restricting it
8321 to the proper length and mode. */
8323 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8327 src = force_to_mode (src, mode,
8328 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8329 ? ~(unsigned HOST_WIDE_INT) 0
8330 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8333 /* If SRC is masked by an AND that does not make a difference in
8334 the value being stored, strip it. */
8335 if (GET_CODE (assign) == ZERO_EXTRACT
8336 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8337 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8338 && GET_CODE (src) == AND
8339 && GET_CODE (XEXP (src, 1)) == CONST_INT
8340 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8341 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8342 src = XEXP (src, 0);
8344 return gen_rtx_SET (VOIDmode, assign, src);
8347 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8351 apply_distributive_law (rtx x)
8353 enum rtx_code code = GET_CODE (x);
8354 enum rtx_code inner_code;
8355 rtx lhs, rhs, other;
8358 /* Distributivity is not true for floating point as it can change the
8359 value. So we don't do it unless -funsafe-math-optimizations. */
8360 if (FLOAT_MODE_P (GET_MODE (x))
8361 && ! flag_unsafe_math_optimizations)
8364 /* The outer operation can only be one of the following: */
8365 if (code != IOR && code != AND && code != XOR
8366 && code != PLUS && code != MINUS)
8372 /* If either operand is a primitive we can't do anything, so get out
8374 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8377 lhs = expand_compound_operation (lhs);
8378 rhs = expand_compound_operation (rhs);
8379 inner_code = GET_CODE (lhs);
8380 if (inner_code != GET_CODE (rhs))
8383 /* See if the inner and outer operations distribute. */
8390 /* These all distribute except over PLUS. */
8391 if (code == PLUS || code == MINUS)
8396 if (code != PLUS && code != MINUS)
8401 /* This is also a multiply, so it distributes over everything. */
8405 /* Non-paradoxical SUBREGs distributes over all operations,
8406 provided the inner modes and byte offsets are the same, this
8407 is an extraction of a low-order part, we don't convert an fp
8408 operation to int or vice versa, this is not a vector mode,
8409 and we would not be converting a single-word operation into a
8410 multi-word operation. The latter test is not required, but
8411 it prevents generating unneeded multi-word operations. Some
8412 of the previous tests are redundant given the latter test,
8413 but are retained because they are required for correctness.
8415 We produce the result slightly differently in this case. */
8417 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8418 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8419 || ! subreg_lowpart_p (lhs)
8420 || (GET_MODE_CLASS (GET_MODE (lhs))
8421 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8422 || (GET_MODE_SIZE (GET_MODE (lhs))
8423 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8424 || VECTOR_MODE_P (GET_MODE (lhs))
8425 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8426 /* Result might need to be truncated. Don't change mode if
8427 explicit truncation is needed. */
8428 || !TRULY_NOOP_TRUNCATION
8429 (GET_MODE_BITSIZE (GET_MODE (x)),
8430 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8433 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8434 SUBREG_REG (lhs), SUBREG_REG (rhs));
8435 return gen_lowpart (GET_MODE (x), tem);
8441 /* Set LHS and RHS to the inner operands (A and B in the example
8442 above) and set OTHER to the common operand (C in the example).
8443 There is only one way to do this unless the inner operation is
8445 if (COMMUTATIVE_ARITH_P (lhs)
8446 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8447 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8448 else if (COMMUTATIVE_ARITH_P (lhs)
8449 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8450 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8451 else if (COMMUTATIVE_ARITH_P (lhs)
8452 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8453 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8454 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8455 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8459 /* Form the new inner operation, seeing if it simplifies first. */
8460 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8462 /* There is one exception to the general way of distributing:
8463 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8464 if (code == XOR && inner_code == IOR)
8467 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8470 /* We may be able to continuing distributing the result, so call
8471 ourselves recursively on the inner operation before forming the
8472 outer operation, which we return. */
8473 return simplify_gen_binary (inner_code, GET_MODE (x),
8474 apply_distributive_law (tem), other);
8477 /* See if X is of the form (* (+ A B) C), and if so convert to
8478 (+ (* A C) (* B C)) and try to simplify.
8480 Most of the time, this results in no change. However, if some of
8481 the operands are the same or inverses of each other, simplifications
8484 For example, (and (ior A B) (not B)) can occur as the result of
8485 expanding a bit field assignment. When we apply the distributive
8486 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8487 which then simplifies to (and (A (not B))).
8489 Note that no checks happen on the validity of applying the inverse
8490 distributive law. This is pointless since we can do it in the
8491 few places where this routine is called.
8493 N is the index of the term that is decomposed (the arithmetic operation,
8494 i.e. (+ A B) in the first example above). !N is the index of the term that
8495 is distributed, i.e. of C in the first example above. */
8497 distribute_and_simplify_rtx (rtx x, int n)
8499 enum machine_mode mode;
8500 enum rtx_code outer_code, inner_code;
8501 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8503 decomposed = XEXP (x, n);
8504 if (!ARITHMETIC_P (decomposed))
8507 mode = GET_MODE (x);
8508 outer_code = GET_CODE (x);
8509 distributed = XEXP (x, !n);
8511 inner_code = GET_CODE (decomposed);
8512 inner_op0 = XEXP (decomposed, 0);
8513 inner_op1 = XEXP (decomposed, 1);
8515 /* Special case (and (xor B C) (not A)), which is equivalent to
8516 (xor (ior A B) (ior A C)) */
8517 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8519 distributed = XEXP (distributed, 0);
8525 /* Distribute the second term. */
8526 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8527 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8531 /* Distribute the first term. */
8532 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8533 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8536 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8538 if (GET_CODE (tmp) != outer_code
8539 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8540 < rtx_cost (x, SET, optimize_this_for_speed_p))
8546 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8547 in MODE. Return an equivalent form, if different from (and VAROP
8548 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8551 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8552 unsigned HOST_WIDE_INT constop)
8554 unsigned HOST_WIDE_INT nonzero;
8555 unsigned HOST_WIDE_INT orig_constop;
8560 orig_constop = constop;
8561 if (GET_CODE (varop) == CLOBBER)
8564 /* Simplify VAROP knowing that we will be only looking at some of the
8567 Note by passing in CONSTOP, we guarantee that the bits not set in
8568 CONSTOP are not significant and will never be examined. We must
8569 ensure that is the case by explicitly masking out those bits
8570 before returning. */
8571 varop = force_to_mode (varop, mode, constop, 0);
8573 /* If VAROP is a CLOBBER, we will fail so return it. */
8574 if (GET_CODE (varop) == CLOBBER)
8577 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8578 to VAROP and return the new constant. */
8579 if (GET_CODE (varop) == CONST_INT)
8580 return gen_int_mode (INTVAL (varop) & constop, mode);
8582 /* See what bits may be nonzero in VAROP. Unlike the general case of
8583 a call to nonzero_bits, here we don't care about bits outside
8586 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8588 /* Turn off all bits in the constant that are known to already be zero.
8589 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8590 which is tested below. */
8594 /* If we don't have any bits left, return zero. */
8598 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8599 a power of two, we can replace this with an ASHIFT. */
8600 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8601 && (i = exact_log2 (constop)) >= 0)
8602 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8604 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8605 or XOR, then try to apply the distributive law. This may eliminate
8606 operations if either branch can be simplified because of the AND.
8607 It may also make some cases more complex, but those cases probably
8608 won't match a pattern either with or without this. */
8610 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8614 apply_distributive_law
8615 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8616 simplify_and_const_int (NULL_RTX,
8620 simplify_and_const_int (NULL_RTX,
8625 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8626 the AND and see if one of the operands simplifies to zero. If so, we
8627 may eliminate it. */
8629 if (GET_CODE (varop) == PLUS
8630 && exact_log2 (constop + 1) >= 0)
8634 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8635 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8636 if (o0 == const0_rtx)
8638 if (o1 == const0_rtx)
8642 /* Make a SUBREG if necessary. If we can't make it, fail. */
8643 varop = gen_lowpart (mode, varop);
8644 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8647 /* If we are only masking insignificant bits, return VAROP. */
8648 if (constop == nonzero)
8651 if (varop == orig_varop && constop == orig_constop)
8654 /* Otherwise, return an AND. */
8655 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8659 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8662 Return an equivalent form, if different from X. Otherwise, return X. If
8663 X is zero, we are to always construct the equivalent form. */
8666 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8667 unsigned HOST_WIDE_INT constop)
8669 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8674 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8675 gen_int_mode (constop, mode));
8676 if (GET_MODE (x) != mode)
8677 x = gen_lowpart (mode, x);
8681 /* Given a REG, X, compute which bits in X can be nonzero.
8682 We don't care about bits outside of those defined in MODE.
8684 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8685 a shift, AND, or zero_extract, we can do better. */
8688 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8689 const_rtx known_x ATTRIBUTE_UNUSED,
8690 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8691 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8692 unsigned HOST_WIDE_INT *nonzero)
8697 /* If X is a register whose nonzero bits value is current, use it.
8698 Otherwise, if X is a register whose value we can find, use that
8699 value. Otherwise, use the previously-computed global nonzero bits
8700 for this register. */
8702 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8703 if (rsp->last_set_value != 0
8704 && (rsp->last_set_mode == mode
8705 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8706 && GET_MODE_CLASS (mode) == MODE_INT))
8707 && ((rsp->last_set_label >= label_tick_ebb_start
8708 && rsp->last_set_label < label_tick)
8709 || (rsp->last_set_label == label_tick
8710 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8711 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8712 && REG_N_SETS (REGNO (x)) == 1
8714 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8716 *nonzero &= rsp->last_set_nonzero_bits;
8720 tem = get_last_value (x);
8724 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8725 /* If X is narrower than MODE and TEM is a non-negative
8726 constant that would appear negative in the mode of X,
8727 sign-extend it for use in reg_nonzero_bits because some
8728 machines (maybe most) will actually do the sign-extension
8729 and this is the conservative approach.
8731 ??? For 2.5, try to tighten up the MD files in this regard
8732 instead of this kludge. */
8734 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8735 && GET_CODE (tem) == CONST_INT
8737 && 0 != (INTVAL (tem)
8738 & ((HOST_WIDE_INT) 1
8739 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8740 tem = GEN_INT (INTVAL (tem)
8741 | ((HOST_WIDE_INT) (-1)
8742 << GET_MODE_BITSIZE (GET_MODE (x))));
8746 else if (nonzero_sign_valid && rsp->nonzero_bits)
8748 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8750 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8751 /* We don't know anything about the upper bits. */
8752 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8759 /* Return the number of bits at the high-order end of X that are known to
8760 be equal to the sign bit. X will be used in mode MODE; if MODE is
8761 VOIDmode, X will be used in its own mode. The returned value will always
8762 be between 1 and the number of bits in MODE. */
8765 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8766 const_rtx known_x ATTRIBUTE_UNUSED,
8767 enum machine_mode known_mode
8769 unsigned int known_ret ATTRIBUTE_UNUSED,
8770 unsigned int *result)
8775 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8776 if (rsp->last_set_value != 0
8777 && rsp->last_set_mode == mode
8778 && ((rsp->last_set_label >= label_tick_ebb_start
8779 && rsp->last_set_label < label_tick)
8780 || (rsp->last_set_label == label_tick
8781 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8782 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8783 && REG_N_SETS (REGNO (x)) == 1
8785 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8787 *result = rsp->last_set_sign_bit_copies;
8791 tem = get_last_value (x);
8795 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8796 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8797 *result = rsp->sign_bit_copies;
8802 /* Return the number of "extended" bits there are in X, when interpreted
8803 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8804 unsigned quantities, this is the number of high-order zero bits.
8805 For signed quantities, this is the number of copies of the sign bit
8806 minus 1. In both case, this function returns the number of "spare"
8807 bits. For example, if two quantities for which this function returns
8808 at least 1 are added, the addition is known not to overflow.
8810 This function will always return 0 unless called during combine, which
8811 implies that it must be called from a define_split. */
8814 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8816 if (nonzero_sign_valid == 0)
8820 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8821 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8822 - floor_log2 (nonzero_bits (x, mode)))
8824 : num_sign_bit_copies (x, mode) - 1);
8827 /* This function is called from `simplify_shift_const' to merge two
8828 outer operations. Specifically, we have already found that we need
8829 to perform operation *POP0 with constant *PCONST0 at the outermost
8830 position. We would now like to also perform OP1 with constant CONST1
8831 (with *POP0 being done last).
8833 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8834 the resulting operation. *PCOMP_P is set to 1 if we would need to
8835 complement the innermost operand, otherwise it is unchanged.
8837 MODE is the mode in which the operation will be done. No bits outside
8838 the width of this mode matter. It is assumed that the width of this mode
8839 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8841 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8842 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8843 result is simply *PCONST0.
8845 If the resulting operation cannot be expressed as one operation, we
8846 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8849 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8851 enum rtx_code op0 = *pop0;
8852 HOST_WIDE_INT const0 = *pconst0;
8854 const0 &= GET_MODE_MASK (mode);
8855 const1 &= GET_MODE_MASK (mode);
8857 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8861 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8864 if (op1 == UNKNOWN || op0 == SET)
8867 else if (op0 == UNKNOWN)
8868 op0 = op1, const0 = const1;
8870 else if (op0 == op1)
8894 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8895 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8898 /* If the two constants aren't the same, we can't do anything. The
8899 remaining six cases can all be done. */
8900 else if (const0 != const1)
8908 /* (a & b) | b == b */
8910 else /* op1 == XOR */
8911 /* (a ^ b) | b == a | b */
8917 /* (a & b) ^ b == (~a) & b */
8918 op0 = AND, *pcomp_p = 1;
8919 else /* op1 == IOR */
8920 /* (a | b) ^ b == a & ~b */
8921 op0 = AND, const0 = ~const0;
8926 /* (a | b) & b == b */
8928 else /* op1 == XOR */
8929 /* (a ^ b) & b) == (~a) & b */
8936 /* Check for NO-OP cases. */
8937 const0 &= GET_MODE_MASK (mode);
8939 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8941 else if (const0 == 0 && op0 == AND)
8943 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8947 /* ??? Slightly redundant with the above mask, but not entirely.
8948 Moving this above means we'd have to sign-extend the mode mask
8949 for the final test. */
8950 const0 = trunc_int_for_mode (const0, mode);
8958 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8959 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8960 simplify it. Otherwise, return a simplified value.
8962 The shift is normally computed in the widest mode we find in VAROP, as
8963 long as it isn't a different number of words than RESULT_MODE. Exceptions
8964 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8967 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8968 rtx varop, int orig_count)
8970 enum rtx_code orig_code = code;
8971 rtx orig_varop = varop;
8973 enum machine_mode mode = result_mode;
8974 enum machine_mode shift_mode, tmode;
8975 unsigned int mode_words
8976 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8977 /* We form (outer_op (code varop count) (outer_const)). */
8978 enum rtx_code outer_op = UNKNOWN;
8979 HOST_WIDE_INT outer_const = 0;
8980 int complement_p = 0;
8983 /* Make sure and truncate the "natural" shift on the way in. We don't
8984 want to do this inside the loop as it makes it more difficult to
8986 if (SHIFT_COUNT_TRUNCATED)
8987 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8989 /* If we were given an invalid count, don't do anything except exactly
8990 what was requested. */
8992 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8997 /* Unless one of the branches of the `if' in this loop does a `continue',
8998 we will `break' the loop after the `if'. */
9002 /* If we have an operand of (clobber (const_int 0)), fail. */
9003 if (GET_CODE (varop) == CLOBBER)
9006 /* If we discovered we had to complement VAROP, leave. Making a NOT
9007 here would cause an infinite loop. */
9011 /* Convert ROTATERT to ROTATE. */
9012 if (code == ROTATERT)
9014 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9016 if (VECTOR_MODE_P (result_mode))
9017 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9019 count = bitsize - count;
9022 /* We need to determine what mode we will do the shift in. If the
9023 shift is a right shift or a ROTATE, we must always do it in the mode
9024 it was originally done in. Otherwise, we can do it in MODE, the
9025 widest mode encountered. */
9027 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9028 ? result_mode : mode);
9030 /* Handle cases where the count is greater than the size of the mode
9031 minus 1. For ASHIFT, use the size minus one as the count (this can
9032 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9033 take the count modulo the size. For other shifts, the result is
9036 Since these shifts are being produced by the compiler by combining
9037 multiple operations, each of which are defined, we know what the
9038 result is supposed to be. */
9040 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9042 if (code == ASHIFTRT)
9043 count = GET_MODE_BITSIZE (shift_mode) - 1;
9044 else if (code == ROTATE || code == ROTATERT)
9045 count %= GET_MODE_BITSIZE (shift_mode);
9048 /* We can't simply return zero because there may be an
9056 /* An arithmetic right shift of a quantity known to be -1 or 0
9058 if (code == ASHIFTRT
9059 && (num_sign_bit_copies (varop, shift_mode)
9060 == GET_MODE_BITSIZE (shift_mode)))
9066 /* If we are doing an arithmetic right shift and discarding all but
9067 the sign bit copies, this is equivalent to doing a shift by the
9068 bitsize minus one. Convert it into that shift because it will often
9069 allow other simplifications. */
9071 if (code == ASHIFTRT
9072 && (count + num_sign_bit_copies (varop, shift_mode)
9073 >= GET_MODE_BITSIZE (shift_mode)))
9074 count = GET_MODE_BITSIZE (shift_mode) - 1;
9076 /* We simplify the tests below and elsewhere by converting
9077 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9078 `make_compound_operation' will convert it to an ASHIFTRT for
9079 those machines (such as VAX) that don't have an LSHIFTRT. */
9080 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9082 && ((nonzero_bits (varop, shift_mode)
9083 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9087 if (((code == LSHIFTRT
9088 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9089 && !(nonzero_bits (varop, shift_mode) >> count))
9091 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9092 && !((nonzero_bits (varop, shift_mode) << count)
9093 & GET_MODE_MASK (shift_mode))))
9094 && !side_effects_p (varop))
9097 switch (GET_CODE (varop))
9103 new_rtx = expand_compound_operation (varop);
9104 if (new_rtx != varop)
9112 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9113 minus the width of a smaller mode, we can do this with a
9114 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9115 if ((code == ASHIFTRT || code == LSHIFTRT)
9116 && ! mode_dependent_address_p (XEXP (varop, 0))
9117 && ! MEM_VOLATILE_P (varop)
9118 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9119 MODE_INT, 1)) != BLKmode)
9121 new_rtx = adjust_address_nv (varop, tmode,
9122 BYTES_BIG_ENDIAN ? 0
9123 : count / BITS_PER_UNIT);
9125 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9126 : ZERO_EXTEND, mode, new_rtx);
9133 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9134 the same number of words as what we've seen so far. Then store
9135 the widest mode in MODE. */
9136 if (subreg_lowpart_p (varop)
9137 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9138 > GET_MODE_SIZE (GET_MODE (varop)))
9139 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9140 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9143 varop = SUBREG_REG (varop);
9144 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9145 mode = GET_MODE (varop);
9151 /* Some machines use MULT instead of ASHIFT because MULT
9152 is cheaper. But it is still better on those machines to
9153 merge two shifts into one. */
9154 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9155 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9158 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9160 GEN_INT (exact_log2 (
9161 INTVAL (XEXP (varop, 1)))));
9167 /* Similar, for when divides are cheaper. */
9168 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9169 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9172 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9174 GEN_INT (exact_log2 (
9175 INTVAL (XEXP (varop, 1)))));
9181 /* If we are extracting just the sign bit of an arithmetic
9182 right shift, that shift is not needed. However, the sign
9183 bit of a wider mode may be different from what would be
9184 interpreted as the sign bit in a narrower mode, so, if
9185 the result is narrower, don't discard the shift. */
9186 if (code == LSHIFTRT
9187 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9188 && (GET_MODE_BITSIZE (result_mode)
9189 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9191 varop = XEXP (varop, 0);
9195 /* ... fall through ... */
9200 /* Here we have two nested shifts. The result is usually the
9201 AND of a new shift with a mask. We compute the result below. */
9202 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9203 && INTVAL (XEXP (varop, 1)) >= 0
9204 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9205 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9206 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9207 && !VECTOR_MODE_P (result_mode))
9209 enum rtx_code first_code = GET_CODE (varop);
9210 unsigned int first_count = INTVAL (XEXP (varop, 1));
9211 unsigned HOST_WIDE_INT mask;
9214 /* We have one common special case. We can't do any merging if
9215 the inner code is an ASHIFTRT of a smaller mode. However, if
9216 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9217 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9218 we can convert it to
9219 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9220 This simplifies certain SIGN_EXTEND operations. */
9221 if (code == ASHIFT && first_code == ASHIFTRT
9222 && count == (GET_MODE_BITSIZE (result_mode)
9223 - GET_MODE_BITSIZE (GET_MODE (varop))))
9225 /* C3 has the low-order C1 bits zero. */
9227 mask = (GET_MODE_MASK (mode)
9228 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9230 varop = simplify_and_const_int (NULL_RTX, result_mode,
9231 XEXP (varop, 0), mask);
9232 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9234 count = first_count;
9239 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9240 than C1 high-order bits equal to the sign bit, we can convert
9241 this to either an ASHIFT or an ASHIFTRT depending on the
9244 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9246 if (code == ASHIFTRT && first_code == ASHIFT
9247 && GET_MODE (varop) == shift_mode
9248 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9251 varop = XEXP (varop, 0);
9252 count -= first_count;
9262 /* There are some cases we can't do. If CODE is ASHIFTRT,
9263 we can only do this if FIRST_CODE is also ASHIFTRT.
9265 We can't do the case when CODE is ROTATE and FIRST_CODE is
9268 If the mode of this shift is not the mode of the outer shift,
9269 we can't do this if either shift is a right shift or ROTATE.
9271 Finally, we can't do any of these if the mode is too wide
9272 unless the codes are the same.
9274 Handle the case where the shift codes are the same
9277 if (code == first_code)
9279 if (GET_MODE (varop) != result_mode
9280 && (code == ASHIFTRT || code == LSHIFTRT
9284 count += first_count;
9285 varop = XEXP (varop, 0);
9289 if (code == ASHIFTRT
9290 || (code == ROTATE && first_code == ASHIFTRT)
9291 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9292 || (GET_MODE (varop) != result_mode
9293 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9294 || first_code == ROTATE
9295 || code == ROTATE)))
9298 /* To compute the mask to apply after the shift, shift the
9299 nonzero bits of the inner shift the same way the
9300 outer shift will. */
9302 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9305 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9308 /* Give up if we can't compute an outer operation to use. */
9310 || GET_CODE (mask_rtx) != CONST_INT
9311 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9313 result_mode, &complement_p))
9316 /* If the shifts are in the same direction, we add the
9317 counts. Otherwise, we subtract them. */
9318 if ((code == ASHIFTRT || code == LSHIFTRT)
9319 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9320 count += first_count;
9322 count -= first_count;
9324 /* If COUNT is positive, the new shift is usually CODE,
9325 except for the two exceptions below, in which case it is
9326 FIRST_CODE. If the count is negative, FIRST_CODE should
9329 && ((first_code == ROTATE && code == ASHIFT)
9330 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9333 code = first_code, count = -count;
9335 varop = XEXP (varop, 0);
9339 /* If we have (A << B << C) for any shift, we can convert this to
9340 (A << C << B). This wins if A is a constant. Only try this if
9341 B is not a constant. */
9343 else if (GET_CODE (varop) == code
9344 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9345 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9347 rtx new_rtx = simplify_const_binary_operation (code, mode,
9350 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9357 if (VECTOR_MODE_P (mode))
9360 /* Make this fit the case below. */
9361 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9362 GEN_INT (GET_MODE_MASK (mode)));
9368 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9369 with C the size of VAROP - 1 and the shift is logical if
9370 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9371 we have an (le X 0) operation. If we have an arithmetic shift
9372 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9373 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9375 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9376 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9377 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9378 && (code == LSHIFTRT || code == ASHIFTRT)
9379 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9380 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9383 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9386 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9387 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9392 /* If we have (shift (logical)), move the logical to the outside
9393 to allow it to possibly combine with another logical and the
9394 shift to combine with another shift. This also canonicalizes to
9395 what a ZERO_EXTRACT looks like. Also, some machines have
9396 (and (shift)) insns. */
9398 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9399 /* We can't do this if we have (ashiftrt (xor)) and the
9400 constant has its sign bit set in shift_mode. */
9401 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9402 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9404 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9406 GEN_INT (count))) != 0
9407 && GET_CODE (new_rtx) == CONST_INT
9408 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9409 INTVAL (new_rtx), result_mode, &complement_p))
9411 varop = XEXP (varop, 0);
9415 /* If we can't do that, try to simplify the shift in each arm of the
9416 logical expression, make a new logical expression, and apply
9417 the inverse distributive law. This also can't be done
9418 for some (ashiftrt (xor)). */
9419 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9420 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9421 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9424 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9425 XEXP (varop, 0), count);
9426 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9427 XEXP (varop, 1), count);
9429 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9431 varop = apply_distributive_law (varop);
9439 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9440 says that the sign bit can be tested, FOO has mode MODE, C is
9441 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9442 that may be nonzero. */
9443 if (code == LSHIFTRT
9444 && XEXP (varop, 1) == const0_rtx
9445 && GET_MODE (XEXP (varop, 0)) == result_mode
9446 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9447 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9448 && STORE_FLAG_VALUE == -1
9449 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9450 && merge_outer_ops (&outer_op, &outer_const, XOR,
9451 (HOST_WIDE_INT) 1, result_mode,
9454 varop = XEXP (varop, 0);
9461 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9462 than the number of bits in the mode is equivalent to A. */
9463 if (code == LSHIFTRT
9464 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9465 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9467 varop = XEXP (varop, 0);
9472 /* NEG commutes with ASHIFT since it is multiplication. Move the
9473 NEG outside to allow shifts to combine. */
9475 && merge_outer_ops (&outer_op, &outer_const, NEG,
9476 (HOST_WIDE_INT) 0, result_mode,
9479 varop = XEXP (varop, 0);
9485 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9486 is one less than the number of bits in the mode is
9487 equivalent to (xor A 1). */
9488 if (code == LSHIFTRT
9489 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9490 && XEXP (varop, 1) == constm1_rtx
9491 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9492 && merge_outer_ops (&outer_op, &outer_const, XOR,
9493 (HOST_WIDE_INT) 1, result_mode,
9497 varop = XEXP (varop, 0);
9501 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9502 that might be nonzero in BAR are those being shifted out and those
9503 bits are known zero in FOO, we can replace the PLUS with FOO.
9504 Similarly in the other operand order. This code occurs when
9505 we are computing the size of a variable-size array. */
9507 if ((code == ASHIFTRT || code == LSHIFTRT)
9508 && count < HOST_BITS_PER_WIDE_INT
9509 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9510 && (nonzero_bits (XEXP (varop, 1), result_mode)
9511 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9513 varop = XEXP (varop, 0);
9516 else if ((code == ASHIFTRT || code == LSHIFTRT)
9517 && count < HOST_BITS_PER_WIDE_INT
9518 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9519 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9521 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9522 & nonzero_bits (XEXP (varop, 1),
9525 varop = XEXP (varop, 1);
9529 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9531 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9532 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9534 GEN_INT (count))) != 0
9535 && GET_CODE (new_rtx) == CONST_INT
9536 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9537 INTVAL (new_rtx), result_mode, &complement_p))
9539 varop = XEXP (varop, 0);
9543 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9544 signbit', and attempt to change the PLUS to an XOR and move it to
9545 the outer operation as is done above in the AND/IOR/XOR case
9546 leg for shift(logical). See details in logical handling above
9547 for reasoning in doing so. */
9548 if (code == LSHIFTRT
9549 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9550 && mode_signbit_p (result_mode, XEXP (varop, 1))
9551 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9553 GEN_INT (count))) != 0
9554 && GET_CODE (new_rtx) == CONST_INT
9555 && merge_outer_ops (&outer_op, &outer_const, XOR,
9556 INTVAL (new_rtx), result_mode, &complement_p))
9558 varop = XEXP (varop, 0);
9565 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9566 with C the size of VAROP - 1 and the shift is logical if
9567 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9568 we have a (gt X 0) operation. If the shift is arithmetic with
9569 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9570 we have a (neg (gt X 0)) operation. */
9572 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9573 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9574 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9575 && (code == LSHIFTRT || code == ASHIFTRT)
9576 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9577 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9578 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9581 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9584 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9585 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9592 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9593 if the truncate does not affect the value. */
9594 if (code == LSHIFTRT
9595 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9596 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9597 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9598 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9599 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9601 rtx varop_inner = XEXP (varop, 0);
9604 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9605 XEXP (varop_inner, 0),
9607 (count + INTVAL (XEXP (varop_inner, 1))));
9608 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9621 /* We need to determine what mode to do the shift in. If the shift is
9622 a right shift or ROTATE, we must always do it in the mode it was
9623 originally done in. Otherwise, we can do it in MODE, the widest mode
9624 encountered. The code we care about is that of the shift that will
9625 actually be done, not the shift that was originally requested. */
9627 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9628 ? result_mode : mode);
9630 /* We have now finished analyzing the shift. The result should be
9631 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9632 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9633 to the result of the shift. OUTER_CONST is the relevant constant,
9634 but we must turn off all bits turned off in the shift. */
9636 if (outer_op == UNKNOWN
9637 && orig_code == code && orig_count == count
9638 && varop == orig_varop
9639 && shift_mode == GET_MODE (varop))
9642 /* Make a SUBREG if necessary. If we can't make it, fail. */
9643 varop = gen_lowpart (shift_mode, varop);
9644 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9647 /* If we have an outer operation and we just made a shift, it is
9648 possible that we could have simplified the shift were it not
9649 for the outer operation. So try to do the simplification
9652 if (outer_op != UNKNOWN)
9653 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9658 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9660 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9661 turn off all the bits that the shift would have turned off. */
9662 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9663 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9664 GET_MODE_MASK (result_mode) >> orig_count);
9666 /* Do the remainder of the processing in RESULT_MODE. */
9667 x = gen_lowpart_or_truncate (result_mode, x);
9669 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9672 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9674 if (outer_op != UNKNOWN)
9676 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9677 outer_const = trunc_int_for_mode (outer_const, result_mode);
9679 if (outer_op == AND)
9680 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9681 else if (outer_op == SET)
9683 /* This means that we have determined that the result is
9684 equivalent to a constant. This should be rare. */
9685 if (!side_effects_p (x))
9686 x = GEN_INT (outer_const);
9688 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9689 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9691 x = simplify_gen_binary (outer_op, result_mode, x,
9692 GEN_INT (outer_const));
9698 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9699 The result of the shift is RESULT_MODE. If we cannot simplify it,
9700 return X or, if it is NULL, synthesize the expression with
9701 simplify_gen_binary. Otherwise, return a simplified value.
9703 The shift is normally computed in the widest mode we find in VAROP, as
9704 long as it isn't a different number of words than RESULT_MODE. Exceptions
9705 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9708 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9709 rtx varop, int count)
9711 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9716 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9717 if (GET_MODE (x) != result_mode)
9718 x = gen_lowpart (result_mode, x);
9723 /* Like recog, but we receive the address of a pointer to a new pattern.
9724 We try to match the rtx that the pointer points to.
9725 If that fails, we may try to modify or replace the pattern,
9726 storing the replacement into the same pointer object.
9728 Modifications include deletion or addition of CLOBBERs.
9730 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9731 the CLOBBERs are placed.
9733 The value is the final insn code from the pattern ultimately matched,
9737 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9740 int insn_code_number;
9741 int num_clobbers_to_add = 0;
9744 rtx old_notes, old_pat;
9746 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9747 we use to indicate that something didn't match. If we find such a
9748 thing, force rejection. */
9749 if (GET_CODE (pat) == PARALLEL)
9750 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9751 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9752 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9755 old_pat = PATTERN (insn);
9756 old_notes = REG_NOTES (insn);
9757 PATTERN (insn) = pat;
9758 REG_NOTES (insn) = 0;
9760 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9761 if (dump_file && (dump_flags & TDF_DETAILS))
9763 if (insn_code_number < 0)
9764 fputs ("Failed to match this instruction:\n", dump_file);
9766 fputs ("Successfully matched this instruction:\n", dump_file);
9767 print_rtl_single (dump_file, pat);
9770 /* If it isn't, there is the possibility that we previously had an insn
9771 that clobbered some register as a side effect, but the combined
9772 insn doesn't need to do that. So try once more without the clobbers
9773 unless this represents an ASM insn. */
9775 if (insn_code_number < 0 && ! check_asm_operands (pat)
9776 && GET_CODE (pat) == PARALLEL)
9780 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9781 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9784 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9788 SUBST_INT (XVECLEN (pat, 0), pos);
9791 pat = XVECEXP (pat, 0, 0);
9793 PATTERN (insn) = pat;
9794 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9795 if (dump_file && (dump_flags & TDF_DETAILS))
9797 if (insn_code_number < 0)
9798 fputs ("Failed to match this instruction:\n", dump_file);
9800 fputs ("Successfully matched this instruction:\n", dump_file);
9801 print_rtl_single (dump_file, pat);
9804 PATTERN (insn) = old_pat;
9805 REG_NOTES (insn) = old_notes;
9807 /* Recognize all noop sets, these will be killed by followup pass. */
9808 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9809 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9811 /* If we had any clobbers to add, make a new pattern than contains
9812 them. Then check to make sure that all of them are dead. */
9813 if (num_clobbers_to_add)
9815 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9816 rtvec_alloc (GET_CODE (pat) == PARALLEL
9818 + num_clobbers_to_add)
9819 : num_clobbers_to_add + 1));
9821 if (GET_CODE (pat) == PARALLEL)
9822 for (i = 0; i < XVECLEN (pat, 0); i++)
9823 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9825 XVECEXP (newpat, 0, 0) = pat;
9827 add_clobbers (newpat, insn_code_number);
9829 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9830 i < XVECLEN (newpat, 0); i++)
9832 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9833 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9835 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9837 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9838 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9839 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9848 return insn_code_number;
9851 /* Like gen_lowpart_general but for use by combine. In combine it
9852 is not possible to create any new pseudoregs. However, it is
9853 safe to create invalid memory addresses, because combine will
9854 try to recognize them and all they will do is make the combine
9857 If for some reason this cannot do its job, an rtx
9858 (clobber (const_int 0)) is returned.
9859 An insn containing that will not be recognized. */
9862 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9864 enum machine_mode imode = GET_MODE (x);
9865 unsigned int osize = GET_MODE_SIZE (omode);
9866 unsigned int isize = GET_MODE_SIZE (imode);
9872 /* Return identity if this is a CONST or symbolic reference. */
9874 && (GET_CODE (x) == CONST
9875 || GET_CODE (x) == SYMBOL_REF
9876 || GET_CODE (x) == LABEL_REF))
9879 /* We can only support MODE being wider than a word if X is a
9880 constant integer or has a mode the same size. */
9881 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9882 && ! ((imode == VOIDmode
9883 && (GET_CODE (x) == CONST_INT
9884 || GET_CODE (x) == CONST_DOUBLE))
9888 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9889 won't know what to do. So we will strip off the SUBREG here and
9890 process normally. */
9891 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9895 /* For use in case we fall down into the address adjustments
9896 further below, we need to adjust the known mode and size of
9897 x; imode and isize, since we just adjusted x. */
9898 imode = GET_MODE (x);
9903 isize = GET_MODE_SIZE (imode);
9906 result = gen_lowpart_common (omode, x);
9915 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9917 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9920 /* If we want to refer to something bigger than the original memref,
9921 generate a paradoxical subreg instead. That will force a reload
9922 of the original memref X. */
9924 return gen_rtx_SUBREG (omode, x, 0);
9926 if (WORDS_BIG_ENDIAN)
9927 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9929 /* Adjust the address so that the address-after-the-data is
9931 if (BYTES_BIG_ENDIAN)
9932 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9934 return adjust_address_nv (x, omode, offset);
9937 /* If X is a comparison operator, rewrite it in a new mode. This
9938 probably won't match, but may allow further simplifications. */
9939 else if (COMPARISON_P (x))
9940 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9942 /* If we couldn't simplify X any other way, just enclose it in a
9943 SUBREG. Normally, this SUBREG won't match, but some patterns may
9944 include an explicit SUBREG or we may simplify it further in combine. */
9950 offset = subreg_lowpart_offset (omode, imode);
9951 if (imode == VOIDmode)
9953 imode = int_mode_for_mode (omode);
9954 x = gen_lowpart_common (imode, x);
9958 res = simplify_gen_subreg (omode, x, imode, offset);
9964 return gen_rtx_CLOBBER (imode, const0_rtx);
9967 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9968 comparison code that will be tested.
9970 The result is a possibly different comparison code to use. *POP0 and
9971 *POP1 may be updated.
9973 It is possible that we might detect that a comparison is either always
9974 true or always false. However, we do not perform general constant
9975 folding in combine, so this knowledge isn't useful. Such tautologies
9976 should have been detected earlier. Hence we ignore all such cases. */
9978 static enum rtx_code
9979 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9985 enum machine_mode mode, tmode;
9987 /* Try a few ways of applying the same transformation to both operands. */
9990 #ifndef WORD_REGISTER_OPERATIONS
9991 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9992 so check specially. */
9993 if (code != GTU && code != GEU && code != LTU && code != LEU
9994 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9995 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9996 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9997 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9998 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9999 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10000 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10001 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10002 && XEXP (op0, 1) == XEXP (op1, 1)
10003 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10004 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10005 && (INTVAL (XEXP (op0, 1))
10006 == (GET_MODE_BITSIZE (GET_MODE (op0))
10007 - (GET_MODE_BITSIZE
10008 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10010 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10011 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10015 /* If both operands are the same constant shift, see if we can ignore the
10016 shift. We can if the shift is a rotate or if the bits shifted out of
10017 this shift are known to be zero for both inputs and if the type of
10018 comparison is compatible with the shift. */
10019 if (GET_CODE (op0) == GET_CODE (op1)
10020 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10021 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10022 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10023 && (code != GT && code != LT && code != GE && code != LE))
10024 || (GET_CODE (op0) == ASHIFTRT
10025 && (code != GTU && code != LTU
10026 && code != GEU && code != LEU)))
10027 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10028 && INTVAL (XEXP (op0, 1)) >= 0
10029 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10030 && XEXP (op0, 1) == XEXP (op1, 1))
10032 enum machine_mode mode = GET_MODE (op0);
10033 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10034 int shift_count = INTVAL (XEXP (op0, 1));
10036 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10037 mask &= (mask >> shift_count) << shift_count;
10038 else if (GET_CODE (op0) == ASHIFT)
10039 mask = (mask & (mask << shift_count)) >> shift_count;
10041 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10042 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10043 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10048 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10049 SUBREGs are of the same mode, and, in both cases, the AND would
10050 be redundant if the comparison was done in the narrower mode,
10051 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10052 and the operand's possibly nonzero bits are 0xffffff01; in that case
10053 if we only care about QImode, we don't need the AND). This case
10054 occurs if the output mode of an scc insn is not SImode and
10055 STORE_FLAG_VALUE == 1 (e.g., the 386).
10057 Similarly, check for a case where the AND's are ZERO_EXTEND
10058 operations from some narrower mode even though a SUBREG is not
10061 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10062 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10063 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10065 rtx inner_op0 = XEXP (op0, 0);
10066 rtx inner_op1 = XEXP (op1, 0);
10067 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10068 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10071 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10072 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10073 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10074 && (GET_MODE (SUBREG_REG (inner_op0))
10075 == GET_MODE (SUBREG_REG (inner_op1)))
10076 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10077 <= HOST_BITS_PER_WIDE_INT)
10078 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10079 GET_MODE (SUBREG_REG (inner_op0)))))
10080 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10081 GET_MODE (SUBREG_REG (inner_op1))))))
10083 op0 = SUBREG_REG (inner_op0);
10084 op1 = SUBREG_REG (inner_op1);
10086 /* The resulting comparison is always unsigned since we masked
10087 off the original sign bit. */
10088 code = unsigned_condition (code);
10094 for (tmode = GET_CLASS_NARROWEST_MODE
10095 (GET_MODE_CLASS (GET_MODE (op0)));
10096 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10097 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10099 op0 = gen_lowpart (tmode, inner_op0);
10100 op1 = gen_lowpart (tmode, inner_op1);
10101 code = unsigned_condition (code);
10110 /* If both operands are NOT, we can strip off the outer operation
10111 and adjust the comparison code for swapped operands; similarly for
10112 NEG, except that this must be an equality comparison. */
10113 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10114 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10115 && (code == EQ || code == NE)))
10116 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10122 /* If the first operand is a constant, swap the operands and adjust the
10123 comparison code appropriately, but don't do this if the second operand
10124 is already a constant integer. */
10125 if (swap_commutative_operands_p (op0, op1))
10127 tem = op0, op0 = op1, op1 = tem;
10128 code = swap_condition (code);
10131 /* We now enter a loop during which we will try to simplify the comparison.
10132 For the most part, we only are concerned with comparisons with zero,
10133 but some things may really be comparisons with zero but not start
10134 out looking that way. */
10136 while (GET_CODE (op1) == CONST_INT)
10138 enum machine_mode mode = GET_MODE (op0);
10139 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10140 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10141 int equality_comparison_p;
10142 int sign_bit_comparison_p;
10143 int unsigned_comparison_p;
10144 HOST_WIDE_INT const_op;
10146 /* We only want to handle integral modes. This catches VOIDmode,
10147 CCmode, and the floating-point modes. An exception is that we
10148 can handle VOIDmode if OP0 is a COMPARE or a comparison
10151 if (GET_MODE_CLASS (mode) != MODE_INT
10152 && ! (mode == VOIDmode
10153 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10156 /* Get the constant we are comparing against and turn off all bits
10157 not on in our mode. */
10158 const_op = INTVAL (op1);
10159 if (mode != VOIDmode)
10160 const_op = trunc_int_for_mode (const_op, mode);
10161 op1 = GEN_INT (const_op);
10163 /* If we are comparing against a constant power of two and the value
10164 being compared can only have that single bit nonzero (e.g., it was
10165 `and'ed with that bit), we can replace this with a comparison
10168 && (code == EQ || code == NE || code == GE || code == GEU
10169 || code == LT || code == LTU)
10170 && mode_width <= HOST_BITS_PER_WIDE_INT
10171 && exact_log2 (const_op) >= 0
10172 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10174 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10175 op1 = const0_rtx, const_op = 0;
10178 /* Similarly, if we are comparing a value known to be either -1 or
10179 0 with -1, change it to the opposite comparison against zero. */
10182 && (code == EQ || code == NE || code == GT || code == LE
10183 || code == GEU || code == LTU)
10184 && num_sign_bit_copies (op0, mode) == mode_width)
10186 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10187 op1 = const0_rtx, const_op = 0;
10190 /* Do some canonicalizations based on the comparison code. We prefer
10191 comparisons against zero and then prefer equality comparisons.
10192 If we can reduce the size of a constant, we will do that too. */
10197 /* < C is equivalent to <= (C - 1) */
10201 op1 = GEN_INT (const_op);
10203 /* ... fall through to LE case below. */
10209 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10213 op1 = GEN_INT (const_op);
10217 /* If we are doing a <= 0 comparison on a value known to have
10218 a zero sign bit, we can replace this with == 0. */
10219 else if (const_op == 0
10220 && mode_width <= HOST_BITS_PER_WIDE_INT
10221 && (nonzero_bits (op0, mode)
10222 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10227 /* >= C is equivalent to > (C - 1). */
10231 op1 = GEN_INT (const_op);
10233 /* ... fall through to GT below. */
10239 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10243 op1 = GEN_INT (const_op);
10247 /* If we are doing a > 0 comparison on a value known to have
10248 a zero sign bit, we can replace this with != 0. */
10249 else if (const_op == 0
10250 && mode_width <= HOST_BITS_PER_WIDE_INT
10251 && (nonzero_bits (op0, mode)
10252 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10257 /* < C is equivalent to <= (C - 1). */
10261 op1 = GEN_INT (const_op);
10263 /* ... fall through ... */
10266 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10267 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10268 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10270 const_op = 0, op1 = const0_rtx;
10278 /* unsigned <= 0 is equivalent to == 0 */
10282 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10283 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10284 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10286 const_op = 0, op1 = const0_rtx;
10292 /* >= C is equivalent to > (C - 1). */
10296 op1 = GEN_INT (const_op);
10298 /* ... fall through ... */
10301 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10302 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10303 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10305 const_op = 0, op1 = const0_rtx;
10313 /* unsigned > 0 is equivalent to != 0 */
10317 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10318 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10319 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10321 const_op = 0, op1 = const0_rtx;
10330 /* Compute some predicates to simplify code below. */
10332 equality_comparison_p = (code == EQ || code == NE);
10333 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10334 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10337 /* If this is a sign bit comparison and we can do arithmetic in
10338 MODE, say that we will only be needing the sign bit of OP0. */
10339 if (sign_bit_comparison_p
10340 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10341 op0 = force_to_mode (op0, mode,
10343 << (GET_MODE_BITSIZE (mode) - 1)),
10346 /* Now try cases based on the opcode of OP0. If none of the cases
10347 does a "continue", we exit this loop immediately after the
10350 switch (GET_CODE (op0))
10353 /* If we are extracting a single bit from a variable position in
10354 a constant that has only a single bit set and are comparing it
10355 with zero, we can convert this into an equality comparison
10356 between the position and the location of the single bit. */
10357 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10358 have already reduced the shift count modulo the word size. */
10359 if (!SHIFT_COUNT_TRUNCATED
10360 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10361 && XEXP (op0, 1) == const1_rtx
10362 && equality_comparison_p && const_op == 0
10363 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10365 if (BITS_BIG_ENDIAN)
10367 enum machine_mode new_mode
10368 = mode_for_extraction (EP_extzv, 1);
10369 if (new_mode == MAX_MACHINE_MODE)
10370 i = BITS_PER_WORD - 1 - i;
10374 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10378 op0 = XEXP (op0, 2);
10382 /* Result is nonzero iff shift count is equal to I. */
10383 code = reverse_condition (code);
10387 /* ... fall through ... */
10390 tem = expand_compound_operation (op0);
10399 /* If testing for equality, we can take the NOT of the constant. */
10400 if (equality_comparison_p
10401 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10403 op0 = XEXP (op0, 0);
10408 /* If just looking at the sign bit, reverse the sense of the
10410 if (sign_bit_comparison_p)
10412 op0 = XEXP (op0, 0);
10413 code = (code == GE ? LT : GE);
10419 /* If testing for equality, we can take the NEG of the constant. */
10420 if (equality_comparison_p
10421 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10423 op0 = XEXP (op0, 0);
10428 /* The remaining cases only apply to comparisons with zero. */
10432 /* When X is ABS or is known positive,
10433 (neg X) is < 0 if and only if X != 0. */
10435 if (sign_bit_comparison_p
10436 && (GET_CODE (XEXP (op0, 0)) == ABS
10437 || (mode_width <= HOST_BITS_PER_WIDE_INT
10438 && (nonzero_bits (XEXP (op0, 0), mode)
10439 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10441 op0 = XEXP (op0, 0);
10442 code = (code == LT ? NE : EQ);
10446 /* If we have NEG of something whose two high-order bits are the
10447 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10448 if (num_sign_bit_copies (op0, mode) >= 2)
10450 op0 = XEXP (op0, 0);
10451 code = swap_condition (code);
10457 /* If we are testing equality and our count is a constant, we
10458 can perform the inverse operation on our RHS. */
10459 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10460 && (tem = simplify_binary_operation (ROTATERT, mode,
10461 op1, XEXP (op0, 1))) != 0)
10463 op0 = XEXP (op0, 0);
10468 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10469 a particular bit. Convert it to an AND of a constant of that
10470 bit. This will be converted into a ZERO_EXTRACT. */
10471 if (const_op == 0 && sign_bit_comparison_p
10472 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10473 && mode_width <= HOST_BITS_PER_WIDE_INT)
10475 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10478 - INTVAL (XEXP (op0, 1)))));
10479 code = (code == LT ? NE : EQ);
10483 /* Fall through. */
10486 /* ABS is ignorable inside an equality comparison with zero. */
10487 if (const_op == 0 && equality_comparison_p)
10489 op0 = XEXP (op0, 0);
10495 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10496 (compare FOO CONST) if CONST fits in FOO's mode and we
10497 are either testing inequality or have an unsigned
10498 comparison with ZERO_EXTEND or a signed comparison with
10499 SIGN_EXTEND. But don't do it if we don't have a compare
10500 insn of the given mode, since we'd have to revert it
10501 later on, and then we wouldn't know whether to sign- or
10503 mode = GET_MODE (XEXP (op0, 0));
10504 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10505 && ! unsigned_comparison_p
10506 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10507 && ((unsigned HOST_WIDE_INT) const_op
10508 < (((unsigned HOST_WIDE_INT) 1
10509 << (GET_MODE_BITSIZE (mode) - 1))))
10510 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10512 op0 = XEXP (op0, 0);
10518 /* Check for the case where we are comparing A - C1 with C2, that is
10520 (subreg:MODE (plus (A) (-C1))) op (C2)
10522 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10523 comparison in the wider mode. One of the following two conditions
10524 must be true in order for this to be valid:
10526 1. The mode extension results in the same bit pattern being added
10527 on both sides and the comparison is equality or unsigned. As
10528 C2 has been truncated to fit in MODE, the pattern can only be
10531 2. The mode extension results in the sign bit being copied on
10534 The difficulty here is that we have predicates for A but not for
10535 (A - C1) so we need to check that C1 is within proper bounds so
10536 as to perturbate A as little as possible. */
10538 if (mode_width <= HOST_BITS_PER_WIDE_INT
10539 && subreg_lowpart_p (op0)
10540 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10541 && GET_CODE (SUBREG_REG (op0)) == PLUS
10542 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10544 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10545 rtx a = XEXP (SUBREG_REG (op0), 0);
10546 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10549 && (unsigned HOST_WIDE_INT) c1
10550 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10551 && (equality_comparison_p || unsigned_comparison_p)
10552 /* (A - C1) zero-extends if it is positive and sign-extends
10553 if it is negative, C2 both zero- and sign-extends. */
10554 && ((0 == (nonzero_bits (a, inner_mode)
10555 & ~GET_MODE_MASK (mode))
10557 /* (A - C1) sign-extends if it is positive and 1-extends
10558 if it is negative, C2 both sign- and 1-extends. */
10559 || (num_sign_bit_copies (a, inner_mode)
10560 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10563 || ((unsigned HOST_WIDE_INT) c1
10564 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10565 /* (A - C1) always sign-extends, like C2. */
10566 && num_sign_bit_copies (a, inner_mode)
10567 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10568 - (mode_width - 1))))
10570 op0 = SUBREG_REG (op0);
10575 /* If the inner mode is narrower and we are extracting the low part,
10576 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10577 if (subreg_lowpart_p (op0)
10578 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10579 /* Fall through */ ;
10583 /* ... fall through ... */
10586 mode = GET_MODE (XEXP (op0, 0));
10587 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10588 && (unsigned_comparison_p || equality_comparison_p)
10589 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10590 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10591 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10593 op0 = XEXP (op0, 0);
10599 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10600 this for equality comparisons due to pathological cases involving
10602 if (equality_comparison_p
10603 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10604 op1, XEXP (op0, 1))))
10606 op0 = XEXP (op0, 0);
10611 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10612 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10613 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10615 op0 = XEXP (XEXP (op0, 0), 0);
10616 code = (code == LT ? EQ : NE);
10622 /* We used to optimize signed comparisons against zero, but that
10623 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10624 arrive here as equality comparisons, or (GEU, LTU) are
10625 optimized away. No need to special-case them. */
10627 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10628 (eq B (minus A C)), whichever simplifies. We can only do
10629 this for equality comparisons due to pathological cases involving
10631 if (equality_comparison_p
10632 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10633 XEXP (op0, 1), op1)))
10635 op0 = XEXP (op0, 0);
10640 if (equality_comparison_p
10641 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10642 XEXP (op0, 0), op1)))
10644 op0 = XEXP (op0, 1);
10649 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10650 of bits in X minus 1, is one iff X > 0. */
10651 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10652 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10653 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10655 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10657 op0 = XEXP (op0, 1);
10658 code = (code == GE ? LE : GT);
10664 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10665 if C is zero or B is a constant. */
10666 if (equality_comparison_p
10667 && 0 != (tem = simplify_binary_operation (XOR, mode,
10668 XEXP (op0, 1), op1)))
10670 op0 = XEXP (op0, 0);
10677 case UNEQ: case LTGT:
10678 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10679 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10680 case UNORDERED: case ORDERED:
10681 /* We can't do anything if OP0 is a condition code value, rather
10682 than an actual data value. */
10684 || CC0_P (XEXP (op0, 0))
10685 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10688 /* Get the two operands being compared. */
10689 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10690 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10692 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10694 /* Check for the cases where we simply want the result of the
10695 earlier test or the opposite of that result. */
10696 if (code == NE || code == EQ
10697 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10698 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10699 && (STORE_FLAG_VALUE
10700 & (((HOST_WIDE_INT) 1
10701 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10702 && (code == LT || code == GE)))
10704 enum rtx_code new_code;
10705 if (code == LT || code == NE)
10706 new_code = GET_CODE (op0);
10708 new_code = reversed_comparison_code (op0, NULL);
10710 if (new_code != UNKNOWN)
10721 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10723 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10724 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10725 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10727 op0 = XEXP (op0, 1);
10728 code = (code == GE ? GT : LE);
10734 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10735 will be converted to a ZERO_EXTRACT later. */
10736 if (const_op == 0 && equality_comparison_p
10737 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10738 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10740 op0 = simplify_and_const_int
10741 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10743 XEXP (XEXP (op0, 0), 1)),
10744 (HOST_WIDE_INT) 1);
10748 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10749 zero and X is a comparison and C1 and C2 describe only bits set
10750 in STORE_FLAG_VALUE, we can compare with X. */
10751 if (const_op == 0 && equality_comparison_p
10752 && mode_width <= HOST_BITS_PER_WIDE_INT
10753 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10754 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10755 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10756 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10757 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10759 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10760 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10761 if ((~STORE_FLAG_VALUE & mask) == 0
10762 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10763 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10764 && COMPARISON_P (tem))))
10766 op0 = XEXP (XEXP (op0, 0), 0);
10771 /* If we are doing an equality comparison of an AND of a bit equal
10772 to the sign bit, replace this with a LT or GE comparison of
10773 the underlying value. */
10774 if (equality_comparison_p
10776 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10777 && mode_width <= HOST_BITS_PER_WIDE_INT
10778 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10779 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10781 op0 = XEXP (op0, 0);
10782 code = (code == EQ ? GE : LT);
10786 /* If this AND operation is really a ZERO_EXTEND from a narrower
10787 mode, the constant fits within that mode, and this is either an
10788 equality or unsigned comparison, try to do this comparison in
10793 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10794 -> (ne:DI (reg:SI 4) (const_int 0))
10796 unless TRULY_NOOP_TRUNCATION allows it or the register is
10797 known to hold a value of the required mode the
10798 transformation is invalid. */
10799 if ((equality_comparison_p || unsigned_comparison_p)
10800 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10801 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10802 & GET_MODE_MASK (mode))
10804 && const_op >> i == 0
10805 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10806 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10807 GET_MODE_BITSIZE (GET_MODE (op0)))
10808 || (REG_P (XEXP (op0, 0))
10809 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10811 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10815 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10816 fits in both M1 and M2 and the SUBREG is either paradoxical
10817 or represents the low part, permute the SUBREG and the AND
10819 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10821 unsigned HOST_WIDE_INT c1;
10822 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10823 /* Require an integral mode, to avoid creating something like
10825 if (SCALAR_INT_MODE_P (tmode)
10826 /* It is unsafe to commute the AND into the SUBREG if the
10827 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10828 not defined. As originally written the upper bits
10829 have a defined value due to the AND operation.
10830 However, if we commute the AND inside the SUBREG then
10831 they no longer have defined values and the meaning of
10832 the code has been changed. */
10834 #ifdef WORD_REGISTER_OPERATIONS
10835 || (mode_width > GET_MODE_BITSIZE (tmode)
10836 && mode_width <= BITS_PER_WORD)
10838 || (mode_width <= GET_MODE_BITSIZE (tmode)
10839 && subreg_lowpart_p (XEXP (op0, 0))))
10840 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10841 && mode_width <= HOST_BITS_PER_WIDE_INT
10842 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10843 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10844 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10846 && c1 != GET_MODE_MASK (tmode))
10848 op0 = simplify_gen_binary (AND, tmode,
10849 SUBREG_REG (XEXP (op0, 0)),
10850 gen_int_mode (c1, tmode));
10851 op0 = gen_lowpart (mode, op0);
10856 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10857 if (const_op == 0 && equality_comparison_p
10858 && XEXP (op0, 1) == const1_rtx
10859 && GET_CODE (XEXP (op0, 0)) == NOT)
10861 op0 = simplify_and_const_int
10862 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10863 code = (code == NE ? EQ : NE);
10867 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10868 (eq (and (lshiftrt X) 1) 0).
10869 Also handle the case where (not X) is expressed using xor. */
10870 if (const_op == 0 && equality_comparison_p
10871 && XEXP (op0, 1) == const1_rtx
10872 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10874 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10875 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10877 if (GET_CODE (shift_op) == NOT
10878 || (GET_CODE (shift_op) == XOR
10879 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10880 && GET_CODE (shift_count) == CONST_INT
10881 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10882 && (INTVAL (XEXP (shift_op, 1))
10883 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10885 op0 = simplify_and_const_int
10887 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10888 (HOST_WIDE_INT) 1);
10889 code = (code == NE ? EQ : NE);
10896 /* If we have (compare (ashift FOO N) (const_int C)) and
10897 the high order N bits of FOO (N+1 if an inequality comparison)
10898 are known to be zero, we can do this by comparing FOO with C
10899 shifted right N bits so long as the low-order N bits of C are
10901 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10902 && INTVAL (XEXP (op0, 1)) >= 0
10903 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10904 < HOST_BITS_PER_WIDE_INT)
10906 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10907 && mode_width <= HOST_BITS_PER_WIDE_INT
10908 && (nonzero_bits (XEXP (op0, 0), mode)
10909 & ~(mask >> (INTVAL (XEXP (op0, 1))
10910 + ! equality_comparison_p))) == 0)
10912 /* We must perform a logical shift, not an arithmetic one,
10913 as we want the top N bits of C to be zero. */
10914 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10916 temp >>= INTVAL (XEXP (op0, 1));
10917 op1 = gen_int_mode (temp, mode);
10918 op0 = XEXP (op0, 0);
10922 /* If we are doing a sign bit comparison, it means we are testing
10923 a particular bit. Convert it to the appropriate AND. */
10924 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10925 && mode_width <= HOST_BITS_PER_WIDE_INT)
10927 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10930 - INTVAL (XEXP (op0, 1)))));
10931 code = (code == LT ? NE : EQ);
10935 /* If this an equality comparison with zero and we are shifting
10936 the low bit to the sign bit, we can convert this to an AND of the
10938 if (const_op == 0 && equality_comparison_p
10939 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10940 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10943 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10944 (HOST_WIDE_INT) 1);
10950 /* If this is an equality comparison with zero, we can do this
10951 as a logical shift, which might be much simpler. */
10952 if (equality_comparison_p && const_op == 0
10953 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10955 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10957 INTVAL (XEXP (op0, 1)));
10961 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10962 do the comparison in a narrower mode. */
10963 if (! unsigned_comparison_p
10964 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10965 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10966 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10967 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10968 MODE_INT, 1)) != BLKmode
10969 && (((unsigned HOST_WIDE_INT) const_op
10970 + (GET_MODE_MASK (tmode) >> 1) + 1)
10971 <= GET_MODE_MASK (tmode)))
10973 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10977 /* Likewise if OP0 is a PLUS of a sign extension with a
10978 constant, which is usually represented with the PLUS
10979 between the shifts. */
10980 if (! unsigned_comparison_p
10981 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10982 && GET_CODE (XEXP (op0, 0)) == PLUS
10983 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10984 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10985 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10986 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10987 MODE_INT, 1)) != BLKmode
10988 && (((unsigned HOST_WIDE_INT) const_op
10989 + (GET_MODE_MASK (tmode) >> 1) + 1)
10990 <= GET_MODE_MASK (tmode)))
10992 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10993 rtx add_const = XEXP (XEXP (op0, 0), 1);
10994 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10995 add_const, XEXP (op0, 1));
10997 op0 = simplify_gen_binary (PLUS, tmode,
10998 gen_lowpart (tmode, inner),
11003 /* ... fall through ... */
11005 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11006 the low order N bits of FOO are known to be zero, we can do this
11007 by comparing FOO with C shifted left N bits so long as no
11008 overflow occurs. */
11009 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11010 && INTVAL (XEXP (op0, 1)) >= 0
11011 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11012 && mode_width <= HOST_BITS_PER_WIDE_INT
11013 && (nonzero_bits (XEXP (op0, 0), mode)
11014 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11015 && (((unsigned HOST_WIDE_INT) const_op
11016 + (GET_CODE (op0) != LSHIFTRT
11017 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11020 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11022 /* If the shift was logical, then we must make the condition
11024 if (GET_CODE (op0) == LSHIFTRT)
11025 code = unsigned_condition (code);
11027 const_op <<= INTVAL (XEXP (op0, 1));
11028 op1 = GEN_INT (const_op);
11029 op0 = XEXP (op0, 0);
11033 /* If we are using this shift to extract just the sign bit, we
11034 can replace this with an LT or GE comparison. */
11036 && (equality_comparison_p || sign_bit_comparison_p)
11037 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11038 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11041 op0 = XEXP (op0, 0);
11042 code = (code == NE || code == GT ? LT : GE);
11054 /* Now make any compound operations involved in this comparison. Then,
11055 check for an outmost SUBREG on OP0 that is not doing anything or is
11056 paradoxical. The latter transformation must only be performed when
11057 it is known that the "extra" bits will be the same in op0 and op1 or
11058 that they don't matter. There are three cases to consider:
11060 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11061 care bits and we can assume they have any convenient value. So
11062 making the transformation is safe.
11064 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11065 In this case the upper bits of op0 are undefined. We should not make
11066 the simplification in that case as we do not know the contents of
11069 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11070 UNKNOWN. In that case we know those bits are zeros or ones. We must
11071 also be sure that they are the same as the upper bits of op1.
11073 We can never remove a SUBREG for a non-equality comparison because
11074 the sign bit is in a different place in the underlying object. */
11076 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11077 op1 = make_compound_operation (op1, SET);
11079 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11080 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11081 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11082 && (code == NE || code == EQ))
11084 if (GET_MODE_SIZE (GET_MODE (op0))
11085 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11087 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11089 if (REG_P (SUBREG_REG (op0)))
11091 op0 = SUBREG_REG (op0);
11092 op1 = gen_lowpart (GET_MODE (op0), op1);
11095 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11096 <= HOST_BITS_PER_WIDE_INT)
11097 && (nonzero_bits (SUBREG_REG (op0),
11098 GET_MODE (SUBREG_REG (op0)))
11099 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11101 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11103 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11104 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11105 op0 = SUBREG_REG (op0), op1 = tem;
11109 /* We now do the opposite procedure: Some machines don't have compare
11110 insns in all modes. If OP0's mode is an integer mode smaller than a
11111 word and we can't do a compare in that mode, see if there is a larger
11112 mode for which we can do the compare. There are a number of cases in
11113 which we can use the wider mode. */
11115 mode = GET_MODE (op0);
11116 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11117 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11118 && ! have_insn_for (COMPARE, mode))
11119 for (tmode = GET_MODE_WIDER_MODE (mode);
11121 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11122 tmode = GET_MODE_WIDER_MODE (tmode))
11123 if (have_insn_for (COMPARE, tmode))
11127 /* If the only nonzero bits in OP0 and OP1 are those in the
11128 narrower mode and this is an equality or unsigned comparison,
11129 we can use the wider mode. Similarly for sign-extended
11130 values, in which case it is true for all comparisons. */
11131 zero_extended = ((code == EQ || code == NE
11132 || code == GEU || code == GTU
11133 || code == LEU || code == LTU)
11134 && (nonzero_bits (op0, tmode)
11135 & ~GET_MODE_MASK (mode)) == 0
11136 && ((GET_CODE (op1) == CONST_INT
11137 || (nonzero_bits (op1, tmode)
11138 & ~GET_MODE_MASK (mode)) == 0)));
11141 || ((num_sign_bit_copies (op0, tmode)
11142 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11143 - GET_MODE_BITSIZE (mode)))
11144 && (num_sign_bit_copies (op1, tmode)
11145 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11146 - GET_MODE_BITSIZE (mode)))))
11148 /* If OP0 is an AND and we don't have an AND in MODE either,
11149 make a new AND in the proper mode. */
11150 if (GET_CODE (op0) == AND
11151 && !have_insn_for (AND, mode))
11152 op0 = simplify_gen_binary (AND, tmode,
11153 gen_lowpart (tmode,
11155 gen_lowpart (tmode,
11158 op0 = gen_lowpart (tmode, op0);
11159 if (zero_extended && GET_CODE (op1) == CONST_INT)
11160 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11161 op1 = gen_lowpart (tmode, op1);
11165 /* If this is a test for negative, we can make an explicit
11166 test of the sign bit. */
11168 if (op1 == const0_rtx && (code == LT || code == GE)
11169 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11171 op0 = simplify_gen_binary (AND, tmode,
11172 gen_lowpart (tmode, op0),
11173 GEN_INT ((HOST_WIDE_INT) 1
11174 << (GET_MODE_BITSIZE (mode)
11176 code = (code == LT) ? NE : EQ;
11181 #ifdef CANONICALIZE_COMPARISON
11182 /* If this machine only supports a subset of valid comparisons, see if we
11183 can convert an unsupported one into a supported one. */
11184 CANONICALIZE_COMPARISON (code, op0, op1);
11193 /* Utility function for record_value_for_reg. Count number of
11198 enum rtx_code code = GET_CODE (x);
11202 if (GET_RTX_CLASS (code) == '2'
11203 || GET_RTX_CLASS (code) == 'c')
11205 rtx x0 = XEXP (x, 0);
11206 rtx x1 = XEXP (x, 1);
11209 return 1 + 2 * count_rtxs (x0);
11211 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11212 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11213 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11214 return 2 + 2 * count_rtxs (x0)
11215 + count_rtxs (x == XEXP (x1, 0)
11216 ? XEXP (x1, 1) : XEXP (x1, 0));
11218 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11219 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11220 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11221 return 2 + 2 * count_rtxs (x1)
11222 + count_rtxs (x == XEXP (x0, 0)
11223 ? XEXP (x0, 1) : XEXP (x0, 0));
11226 fmt = GET_RTX_FORMAT (code);
11227 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11229 ret += count_rtxs (XEXP (x, i));
11230 else if (fmt[i] == 'E')
11231 for (j = 0; j < XVECLEN (x, i); j++)
11232 ret += count_rtxs (XVECEXP (x, i, j));
11237 /* Utility function for following routine. Called when X is part of a value
11238 being stored into last_set_value. Sets last_set_table_tick
11239 for each register mentioned. Similar to mention_regs in cse.c */
11242 update_table_tick (rtx x)
11244 enum rtx_code code = GET_CODE (x);
11245 const char *fmt = GET_RTX_FORMAT (code);
11250 unsigned int regno = REGNO (x);
11251 unsigned int endregno = END_REGNO (x);
11254 for (r = regno; r < endregno; r++)
11256 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11257 rsp->last_set_table_tick = label_tick;
11263 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11266 /* Check for identical subexpressions. If x contains
11267 identical subexpression we only have to traverse one of
11269 if (i == 0 && ARITHMETIC_P (x))
11271 /* Note that at this point x1 has already been
11273 rtx x0 = XEXP (x, 0);
11274 rtx x1 = XEXP (x, 1);
11276 /* If x0 and x1 are identical then there is no need to
11281 /* If x0 is identical to a subexpression of x1 then while
11282 processing x1, x0 has already been processed. Thus we
11283 are done with x. */
11284 if (ARITHMETIC_P (x1)
11285 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11288 /* If x1 is identical to a subexpression of x0 then we
11289 still have to process the rest of x0. */
11290 if (ARITHMETIC_P (x0)
11291 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11293 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11298 update_table_tick (XEXP (x, i));
11300 else if (fmt[i] == 'E')
11301 for (j = 0; j < XVECLEN (x, i); j++)
11302 update_table_tick (XVECEXP (x, i, j));
11305 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11306 are saying that the register is clobbered and we no longer know its
11307 value. If INSN is zero, don't update reg_stat[].last_set; this is
11308 only permitted with VALUE also zero and is used to invalidate the
11312 record_value_for_reg (rtx reg, rtx insn, rtx value)
11314 unsigned int regno = REGNO (reg);
11315 unsigned int endregno = END_REGNO (reg);
11317 reg_stat_type *rsp;
11319 /* If VALUE contains REG and we have a previous value for REG, substitute
11320 the previous value. */
11321 if (value && insn && reg_overlap_mentioned_p (reg, value))
11325 /* Set things up so get_last_value is allowed to see anything set up to
11327 subst_low_luid = DF_INSN_LUID (insn);
11328 tem = get_last_value (reg);
11330 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11331 it isn't going to be useful and will take a lot of time to process,
11332 so just use the CLOBBER. */
11336 if (ARITHMETIC_P (tem)
11337 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11338 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11339 tem = XEXP (tem, 0);
11340 else if (count_occurrences (value, reg, 1) >= 2)
11342 /* If there are two or more occurrences of REG in VALUE,
11343 prevent the value from growing too much. */
11344 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11345 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11348 value = replace_rtx (copy_rtx (value), reg, tem);
11352 /* For each register modified, show we don't know its value, that
11353 we don't know about its bitwise content, that its value has been
11354 updated, and that we don't know the location of the death of the
11356 for (i = regno; i < endregno; i++)
11358 rsp = VEC_index (reg_stat_type, reg_stat, i);
11361 rsp->last_set = insn;
11363 rsp->last_set_value = 0;
11364 rsp->last_set_mode = 0;
11365 rsp->last_set_nonzero_bits = 0;
11366 rsp->last_set_sign_bit_copies = 0;
11367 rsp->last_death = 0;
11368 rsp->truncated_to_mode = 0;
11371 /* Mark registers that are being referenced in this value. */
11373 update_table_tick (value);
11375 /* Now update the status of each register being set.
11376 If someone is using this register in this block, set this register
11377 to invalid since we will get confused between the two lives in this
11378 basic block. This makes using this register always invalid. In cse, we
11379 scan the table to invalidate all entries using this register, but this
11380 is too much work for us. */
11382 for (i = regno; i < endregno; i++)
11384 rsp = VEC_index (reg_stat_type, reg_stat, i);
11385 rsp->last_set_label = label_tick;
11387 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11388 rsp->last_set_invalid = 1;
11390 rsp->last_set_invalid = 0;
11393 /* The value being assigned might refer to X (like in "x++;"). In that
11394 case, we must replace it with (clobber (const_int 0)) to prevent
11396 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11397 if (value && ! get_last_value_validate (&value, insn,
11398 rsp->last_set_label, 0))
11400 value = copy_rtx (value);
11401 if (! get_last_value_validate (&value, insn,
11402 rsp->last_set_label, 1))
11406 /* For the main register being modified, update the value, the mode, the
11407 nonzero bits, and the number of sign bit copies. */
11409 rsp->last_set_value = value;
11413 enum machine_mode mode = GET_MODE (reg);
11414 subst_low_luid = DF_INSN_LUID (insn);
11415 rsp->last_set_mode = mode;
11416 if (GET_MODE_CLASS (mode) == MODE_INT
11417 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11418 mode = nonzero_bits_mode;
11419 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11420 rsp->last_set_sign_bit_copies
11421 = num_sign_bit_copies (value, GET_MODE (reg));
11425 /* Called via note_stores from record_dead_and_set_regs to handle one
11426 SET or CLOBBER in an insn. DATA is the instruction in which the
11427 set is occurring. */
11430 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11432 rtx record_dead_insn = (rtx) data;
11434 if (GET_CODE (dest) == SUBREG)
11435 dest = SUBREG_REG (dest);
11437 if (!record_dead_insn)
11440 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11446 /* If we are setting the whole register, we know its value. Otherwise
11447 show that we don't know the value. We can handle SUBREG in
11449 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11450 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11451 else if (GET_CODE (setter) == SET
11452 && GET_CODE (SET_DEST (setter)) == SUBREG
11453 && SUBREG_REG (SET_DEST (setter)) == dest
11454 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11455 && subreg_lowpart_p (SET_DEST (setter)))
11456 record_value_for_reg (dest, record_dead_insn,
11457 gen_lowpart (GET_MODE (dest),
11458 SET_SRC (setter)));
11460 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11462 else if (MEM_P (dest)
11463 /* Ignore pushes, they clobber nothing. */
11464 && ! push_operand (dest, GET_MODE (dest)))
11465 mem_last_set = DF_INSN_LUID (record_dead_insn);
11468 /* Update the records of when each REG was most recently set or killed
11469 for the things done by INSN. This is the last thing done in processing
11470 INSN in the combiner loop.
11472 We update reg_stat[], in particular fields last_set, last_set_value,
11473 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11474 last_death, and also the similar information mem_last_set (which insn
11475 most recently modified memory) and last_call_luid (which insn was the
11476 most recent subroutine call). */
11479 record_dead_and_set_regs (rtx insn)
11484 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11486 if (REG_NOTE_KIND (link) == REG_DEAD
11487 && REG_P (XEXP (link, 0)))
11489 unsigned int regno = REGNO (XEXP (link, 0));
11490 unsigned int endregno = END_REGNO (XEXP (link, 0));
11492 for (i = regno; i < endregno; i++)
11494 reg_stat_type *rsp;
11496 rsp = VEC_index (reg_stat_type, reg_stat, i);
11497 rsp->last_death = insn;
11500 else if (REG_NOTE_KIND (link) == REG_INC)
11501 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11506 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11507 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11509 reg_stat_type *rsp;
11511 rsp = VEC_index (reg_stat_type, reg_stat, i);
11512 rsp->last_set_invalid = 1;
11513 rsp->last_set = insn;
11514 rsp->last_set_value = 0;
11515 rsp->last_set_mode = 0;
11516 rsp->last_set_nonzero_bits = 0;
11517 rsp->last_set_sign_bit_copies = 0;
11518 rsp->last_death = 0;
11519 rsp->truncated_to_mode = 0;
11522 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11524 /* We can't combine into a call pattern. Remember, though, that
11525 the return value register is set at this LUID. We could
11526 still replace a register with the return value from the
11527 wrong subroutine call! */
11528 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11531 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11534 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11535 register present in the SUBREG, so for each such SUBREG go back and
11536 adjust nonzero and sign bit information of the registers that are
11537 known to have some zero/sign bits set.
11539 This is needed because when combine blows the SUBREGs away, the
11540 information on zero/sign bits is lost and further combines can be
11541 missed because of that. */
11544 record_promoted_value (rtx insn, rtx subreg)
11547 unsigned int regno = REGNO (SUBREG_REG (subreg));
11548 enum machine_mode mode = GET_MODE (subreg);
11550 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11553 for (links = LOG_LINKS (insn); links;)
11555 reg_stat_type *rsp;
11557 insn = XEXP (links, 0);
11558 set = single_set (insn);
11560 if (! set || !REG_P (SET_DEST (set))
11561 || REGNO (SET_DEST (set)) != regno
11562 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11564 links = XEXP (links, 1);
11568 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11569 if (rsp->last_set == insn)
11571 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11572 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11575 if (REG_P (SET_SRC (set)))
11577 regno = REGNO (SET_SRC (set));
11578 links = LOG_LINKS (insn);
11585 /* Check if X, a register, is known to contain a value already
11586 truncated to MODE. In this case we can use a subreg to refer to
11587 the truncated value even though in the generic case we would need
11588 an explicit truncation. */
11591 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11593 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11594 enum machine_mode truncated = rsp->truncated_to_mode;
11597 || rsp->truncation_label < label_tick_ebb_start)
11599 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11601 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11602 GET_MODE_BITSIZE (truncated)))
11607 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11608 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11609 might be able to turn a truncate into a subreg using this information.
11610 Return -1 if traversing *P is complete or 0 otherwise. */
11613 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11616 enum machine_mode truncated_mode;
11617 reg_stat_type *rsp;
11619 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11621 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11622 truncated_mode = GET_MODE (x);
11624 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11627 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11628 GET_MODE_BITSIZE (original_mode)))
11631 x = SUBREG_REG (x);
11633 /* ??? For hard-regs we now record everything. We might be able to
11634 optimize this using last_set_mode. */
11635 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11636 truncated_mode = GET_MODE (x);
11640 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11641 if (rsp->truncated_to_mode == 0
11642 || rsp->truncation_label < label_tick_ebb_start
11643 || (GET_MODE_SIZE (truncated_mode)
11644 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11646 rsp->truncated_to_mode = truncated_mode;
11647 rsp->truncation_label = label_tick;
11653 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11654 the modes they are used in. This can help truning TRUNCATEs into
11658 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11660 for_each_rtx (x, record_truncated_value, NULL);
11663 /* Scan X for promoted SUBREGs. For each one found,
11664 note what it implies to the registers used in it. */
11667 check_promoted_subreg (rtx insn, rtx x)
11669 if (GET_CODE (x) == SUBREG
11670 && SUBREG_PROMOTED_VAR_P (x)
11671 && REG_P (SUBREG_REG (x)))
11672 record_promoted_value (insn, x);
11675 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11678 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11682 check_promoted_subreg (insn, XEXP (x, i));
11686 if (XVEC (x, i) != 0)
11687 for (j = 0; j < XVECLEN (x, i); j++)
11688 check_promoted_subreg (insn, XVECEXP (x, i, j));
11694 /* Utility routine for the following function. Verify that all the registers
11695 mentioned in *LOC are valid when *LOC was part of a value set when
11696 label_tick == TICK. Return 0 if some are not.
11698 If REPLACE is nonzero, replace the invalid reference with
11699 (clobber (const_int 0)) and return 1. This replacement is useful because
11700 we often can get useful information about the form of a value (e.g., if
11701 it was produced by a shift that always produces -1 or 0) even though
11702 we don't know exactly what registers it was produced from. */
11705 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11708 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11709 int len = GET_RTX_LENGTH (GET_CODE (x));
11714 unsigned int regno = REGNO (x);
11715 unsigned int endregno = END_REGNO (x);
11718 for (j = regno; j < endregno; j++)
11720 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11721 if (rsp->last_set_invalid
11722 /* If this is a pseudo-register that was only set once and not
11723 live at the beginning of the function, it is always valid. */
11724 || (! (regno >= FIRST_PSEUDO_REGISTER
11725 && REG_N_SETS (regno) == 1
11726 && (!REGNO_REG_SET_P
11727 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11728 && rsp->last_set_label > tick))
11731 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11738 /* If this is a memory reference, make sure that there were
11739 no stores after it that might have clobbered the value. We don't
11740 have alias info, so we assume any store invalidates it. */
11741 else if (MEM_P (x) && !MEM_READONLY_P (x)
11742 && DF_INSN_LUID (insn) <= mem_last_set)
11745 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11749 for (i = 0; i < len; i++)
11753 /* Check for identical subexpressions. If x contains
11754 identical subexpression we only have to traverse one of
11756 if (i == 1 && ARITHMETIC_P (x))
11758 /* Note that at this point x0 has already been checked
11759 and found valid. */
11760 rtx x0 = XEXP (x, 0);
11761 rtx x1 = XEXP (x, 1);
11763 /* If x0 and x1 are identical then x is also valid. */
11767 /* If x1 is identical to a subexpression of x0 then
11768 while checking x0, x1 has already been checked. Thus
11769 it is valid and so as x. */
11770 if (ARITHMETIC_P (x0)
11771 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11774 /* If x0 is identical to a subexpression of x1 then x is
11775 valid iff the rest of x1 is valid. */
11776 if (ARITHMETIC_P (x1)
11777 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11779 get_last_value_validate (&XEXP (x1,
11780 x0 == XEXP (x1, 0) ? 1 : 0),
11781 insn, tick, replace);
11784 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11788 else if (fmt[i] == 'E')
11789 for (j = 0; j < XVECLEN (x, i); j++)
11790 if (get_last_value_validate (&XVECEXP (x, i, j),
11791 insn, tick, replace) == 0)
11795 /* If we haven't found a reason for it to be invalid, it is valid. */
11799 /* Get the last value assigned to X, if known. Some registers
11800 in the value may be replaced with (clobber (const_int 0)) if their value
11801 is known longer known reliably. */
11804 get_last_value (const_rtx x)
11806 unsigned int regno;
11808 reg_stat_type *rsp;
11810 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11811 then convert it to the desired mode. If this is a paradoxical SUBREG,
11812 we cannot predict what values the "extra" bits might have. */
11813 if (GET_CODE (x) == SUBREG
11814 && subreg_lowpart_p (x)
11815 && (GET_MODE_SIZE (GET_MODE (x))
11816 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11817 && (value = get_last_value (SUBREG_REG (x))) != 0)
11818 return gen_lowpart (GET_MODE (x), value);
11824 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11825 value = rsp->last_set_value;
11827 /* If we don't have a value, or if it isn't for this basic block and
11828 it's either a hard register, set more than once, or it's a live
11829 at the beginning of the function, return 0.
11831 Because if it's not live at the beginning of the function then the reg
11832 is always set before being used (is never used without being set).
11833 And, if it's set only once, and it's always set before use, then all
11834 uses must have the same last value, even if it's not from this basic
11838 || (rsp->last_set_label < label_tick_ebb_start
11839 && (regno < FIRST_PSEUDO_REGISTER
11840 || REG_N_SETS (regno) != 1
11842 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11845 /* If the value was set in a later insn than the ones we are processing,
11846 we can't use it even if the register was only set once. */
11847 if (rsp->last_set_label == label_tick
11848 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11851 /* If the value has all its registers valid, return it. */
11852 if (get_last_value_validate (&value, rsp->last_set,
11853 rsp->last_set_label, 0))
11856 /* Otherwise, make a copy and replace any invalid register with
11857 (clobber (const_int 0)). If that fails for some reason, return 0. */
11859 value = copy_rtx (value);
11860 if (get_last_value_validate (&value, rsp->last_set,
11861 rsp->last_set_label, 1))
11867 /* Return nonzero if expression X refers to a REG or to memory
11868 that is set in an instruction more recent than FROM_LUID. */
11871 use_crosses_set_p (const_rtx x, int from_luid)
11875 enum rtx_code code = GET_CODE (x);
11879 unsigned int regno = REGNO (x);
11880 unsigned endreg = END_REGNO (x);
11882 #ifdef PUSH_ROUNDING
11883 /* Don't allow uses of the stack pointer to be moved,
11884 because we don't know whether the move crosses a push insn. */
11885 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11888 for (; regno < endreg; regno++)
11890 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11892 && rsp->last_set_label == label_tick
11893 && DF_INSN_LUID (rsp->last_set) > from_luid)
11899 if (code == MEM && mem_last_set > from_luid)
11902 fmt = GET_RTX_FORMAT (code);
11904 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11909 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11910 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11913 else if (fmt[i] == 'e'
11914 && use_crosses_set_p (XEXP (x, i), from_luid))
11920 /* Define three variables used for communication between the following
11923 static unsigned int reg_dead_regno, reg_dead_endregno;
11924 static int reg_dead_flag;
11926 /* Function called via note_stores from reg_dead_at_p.
11928 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11929 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11932 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11934 unsigned int regno, endregno;
11939 regno = REGNO (dest);
11940 endregno = END_REGNO (dest);
11941 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11942 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11945 /* Return nonzero if REG is known to be dead at INSN.
11947 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11948 referencing REG, it is dead. If we hit a SET referencing REG, it is
11949 live. Otherwise, see if it is live or dead at the start of the basic
11950 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11951 must be assumed to be always live. */
11954 reg_dead_at_p (rtx reg, rtx insn)
11959 /* Set variables for reg_dead_at_p_1. */
11960 reg_dead_regno = REGNO (reg);
11961 reg_dead_endregno = END_REGNO (reg);
11965 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11966 we allow the machine description to decide whether use-and-clobber
11967 patterns are OK. */
11968 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11970 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11971 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11975 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11976 beginning of function. */
11977 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11978 insn = prev_nonnote_insn (insn))
11980 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11982 return reg_dead_flag == 1 ? 1 : 0;
11984 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11988 /* Get the basic block that we were in. */
11990 block = ENTRY_BLOCK_PTR->next_bb;
11993 FOR_EACH_BB (block)
11994 if (insn == BB_HEAD (block))
11997 if (block == EXIT_BLOCK_PTR)
12001 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12002 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12008 /* Note hard registers in X that are used. */
12011 mark_used_regs_combine (rtx x)
12013 RTX_CODE code = GET_CODE (x);
12014 unsigned int regno;
12027 case ADDR_DIFF_VEC:
12030 /* CC0 must die in the insn after it is set, so we don't need to take
12031 special note of it here. */
12037 /* If we are clobbering a MEM, mark any hard registers inside the
12038 address as used. */
12039 if (MEM_P (XEXP (x, 0)))
12040 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12045 /* A hard reg in a wide mode may really be multiple registers.
12046 If so, mark all of them just like the first. */
12047 if (regno < FIRST_PSEUDO_REGISTER)
12049 /* None of this applies to the stack, frame or arg pointers. */
12050 if (regno == STACK_POINTER_REGNUM
12051 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12052 || regno == HARD_FRAME_POINTER_REGNUM
12054 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12055 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12057 || regno == FRAME_POINTER_REGNUM)
12060 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12066 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12068 rtx testreg = SET_DEST (x);
12070 while (GET_CODE (testreg) == SUBREG
12071 || GET_CODE (testreg) == ZERO_EXTRACT
12072 || GET_CODE (testreg) == STRICT_LOW_PART)
12073 testreg = XEXP (testreg, 0);
12075 if (MEM_P (testreg))
12076 mark_used_regs_combine (XEXP (testreg, 0));
12078 mark_used_regs_combine (SET_SRC (x));
12086 /* Recursively scan the operands of this expression. */
12089 const char *fmt = GET_RTX_FORMAT (code);
12091 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12094 mark_used_regs_combine (XEXP (x, i));
12095 else if (fmt[i] == 'E')
12099 for (j = 0; j < XVECLEN (x, i); j++)
12100 mark_used_regs_combine (XVECEXP (x, i, j));
12106 /* Remove register number REGNO from the dead registers list of INSN.
12108 Return the note used to record the death, if there was one. */
12111 remove_death (unsigned int regno, rtx insn)
12113 rtx note = find_regno_note (insn, REG_DEAD, regno);
12116 remove_note (insn, note);
12121 /* For each register (hardware or pseudo) used within expression X, if its
12122 death is in an instruction with luid between FROM_LUID (inclusive) and
12123 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12124 list headed by PNOTES.
12126 That said, don't move registers killed by maybe_kill_insn.
12128 This is done when X is being merged by combination into TO_INSN. These
12129 notes will then be distributed as needed. */
12132 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12137 enum rtx_code code = GET_CODE (x);
12141 unsigned int regno = REGNO (x);
12142 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12144 /* Don't move the register if it gets killed in between from and to. */
12145 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12146 && ! reg_referenced_p (x, maybe_kill_insn))
12150 && DF_INSN_LUID (where_dead) >= from_luid
12151 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12153 rtx note = remove_death (regno, where_dead);
12155 /* It is possible for the call above to return 0. This can occur
12156 when last_death points to I2 or I1 that we combined with.
12157 In that case make a new note.
12159 We must also check for the case where X is a hard register
12160 and NOTE is a death note for a range of hard registers
12161 including X. In that case, we must put REG_DEAD notes for
12162 the remaining registers in place of NOTE. */
12164 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12165 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12166 > GET_MODE_SIZE (GET_MODE (x))))
12168 unsigned int deadregno = REGNO (XEXP (note, 0));
12169 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12170 unsigned int ourend = END_HARD_REGNO (x);
12173 for (i = deadregno; i < deadend; i++)
12174 if (i < regno || i >= ourend)
12175 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12178 /* If we didn't find any note, or if we found a REG_DEAD note that
12179 covers only part of the given reg, and we have a multi-reg hard
12180 register, then to be safe we must check for REG_DEAD notes
12181 for each register other than the first. They could have
12182 their own REG_DEAD notes lying around. */
12183 else if ((note == 0
12185 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12186 < GET_MODE_SIZE (GET_MODE (x)))))
12187 && regno < FIRST_PSEUDO_REGISTER
12188 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12190 unsigned int ourend = END_HARD_REGNO (x);
12191 unsigned int i, offset;
12195 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12199 for (i = regno + offset; i < ourend; i++)
12200 move_deaths (regno_reg_rtx[i],
12201 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12204 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12206 XEXP (note, 1) = *pnotes;
12210 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12216 else if (GET_CODE (x) == SET)
12218 rtx dest = SET_DEST (x);
12220 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12222 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12223 that accesses one word of a multi-word item, some
12224 piece of everything register in the expression is used by
12225 this insn, so remove any old death. */
12226 /* ??? So why do we test for equality of the sizes? */
12228 if (GET_CODE (dest) == ZERO_EXTRACT
12229 || GET_CODE (dest) == STRICT_LOW_PART
12230 || (GET_CODE (dest) == SUBREG
12231 && (((GET_MODE_SIZE (GET_MODE (dest))
12232 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12233 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12234 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12236 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12240 /* If this is some other SUBREG, we know it replaces the entire
12241 value, so use that as the destination. */
12242 if (GET_CODE (dest) == SUBREG)
12243 dest = SUBREG_REG (dest);
12245 /* If this is a MEM, adjust deaths of anything used in the address.
12246 For a REG (the only other possibility), the entire value is
12247 being replaced so the old value is not used in this insn. */
12250 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12255 else if (GET_CODE (x) == CLOBBER)
12258 len = GET_RTX_LENGTH (code);
12259 fmt = GET_RTX_FORMAT (code);
12261 for (i = 0; i < len; i++)
12266 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12267 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12270 else if (fmt[i] == 'e')
12271 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12275 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12276 pattern of an insn. X must be a REG. */
12279 reg_bitfield_target_p (rtx x, rtx body)
12283 if (GET_CODE (body) == SET)
12285 rtx dest = SET_DEST (body);
12287 unsigned int regno, tregno, endregno, endtregno;
12289 if (GET_CODE (dest) == ZERO_EXTRACT)
12290 target = XEXP (dest, 0);
12291 else if (GET_CODE (dest) == STRICT_LOW_PART)
12292 target = SUBREG_REG (XEXP (dest, 0));
12296 if (GET_CODE (target) == SUBREG)
12297 target = SUBREG_REG (target);
12299 if (!REG_P (target))
12302 tregno = REGNO (target), regno = REGNO (x);
12303 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12304 return target == x;
12306 endtregno = end_hard_regno (GET_MODE (target), tregno);
12307 endregno = end_hard_regno (GET_MODE (x), regno);
12309 return endregno > tregno && regno < endtregno;
12312 else if (GET_CODE (body) == PARALLEL)
12313 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12314 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12320 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12321 as appropriate. I3 and I2 are the insns resulting from the combination
12322 insns including FROM (I2 may be zero).
12324 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12325 not need REG_DEAD notes because they are being substituted for. This
12326 saves searching in the most common cases.
12328 Each note in the list is either ignored or placed on some insns, depending
12329 on the type of note. */
12332 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12335 rtx note, next_note;
12338 for (note = notes; note; note = next_note)
12340 rtx place = 0, place2 = 0;
12342 next_note = XEXP (note, 1);
12343 switch (REG_NOTE_KIND (note))
12347 /* Doesn't matter much where we put this, as long as it's somewhere.
12348 It is preferable to keep these notes on branches, which is most
12349 likely to be i3. */
12353 case REG_VALUE_PROFILE:
12354 /* Just get rid of this note, as it is unused later anyway. */
12357 case REG_NON_LOCAL_GOTO:
12362 gcc_assert (i2 && JUMP_P (i2));
12367 case REG_EH_REGION:
12368 /* These notes must remain with the call or trapping instruction. */
12371 else if (i2 && CALL_P (i2))
12375 gcc_assert (flag_non_call_exceptions);
12376 if (may_trap_p (i3))
12378 else if (i2 && may_trap_p (i2))
12380 /* ??? Otherwise assume we've combined things such that we
12381 can now prove that the instructions can't trap. Drop the
12382 note in this case. */
12388 /* These notes must remain with the call. It should not be
12389 possible for both I2 and I3 to be a call. */
12394 gcc_assert (i2 && CALL_P (i2));
12400 /* Any clobbers for i3 may still exist, and so we must process
12401 REG_UNUSED notes from that insn.
12403 Any clobbers from i2 or i1 can only exist if they were added by
12404 recog_for_combine. In that case, recog_for_combine created the
12405 necessary REG_UNUSED notes. Trying to keep any original
12406 REG_UNUSED notes from these insns can cause incorrect output
12407 if it is for the same register as the original i3 dest.
12408 In that case, we will notice that the register is set in i3,
12409 and then add a REG_UNUSED note for the destination of i3, which
12410 is wrong. However, it is possible to have REG_UNUSED notes from
12411 i2 or i1 for register which were both used and clobbered, so
12412 we keep notes from i2 or i1 if they will turn into REG_DEAD
12415 /* If this register is set or clobbered in I3, put the note there
12416 unless there is one already. */
12417 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12419 if (from_insn != i3)
12422 if (! (REG_P (XEXP (note, 0))
12423 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12424 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12427 /* Otherwise, if this register is used by I3, then this register
12428 now dies here, so we must put a REG_DEAD note here unless there
12430 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12431 && ! (REG_P (XEXP (note, 0))
12432 ? find_regno_note (i3, REG_DEAD,
12433 REGNO (XEXP (note, 0)))
12434 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12436 PUT_REG_NOTE_KIND (note, REG_DEAD);
12444 /* These notes say something about results of an insn. We can
12445 only support them if they used to be on I3 in which case they
12446 remain on I3. Otherwise they are ignored.
12448 If the note refers to an expression that is not a constant, we
12449 must also ignore the note since we cannot tell whether the
12450 equivalence is still true. It might be possible to do
12451 slightly better than this (we only have a problem if I2DEST
12452 or I1DEST is present in the expression), but it doesn't
12453 seem worth the trouble. */
12455 if (from_insn == i3
12456 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12461 /* These notes say something about how a register is used. They must
12462 be present on any use of the register in I2 or I3. */
12463 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12466 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12475 case REG_LABEL_TARGET:
12476 case REG_LABEL_OPERAND:
12477 /* This can show up in several ways -- either directly in the
12478 pattern, or hidden off in the constant pool with (or without?)
12479 a REG_EQUAL note. */
12480 /* ??? Ignore the without-reg_equal-note problem for now. */
12481 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12482 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12483 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12484 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12488 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12489 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12490 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12491 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12499 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12500 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12502 if (place && JUMP_P (place)
12503 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12504 && (JUMP_LABEL (place) == NULL
12505 || JUMP_LABEL (place) == XEXP (note, 0)))
12507 rtx label = JUMP_LABEL (place);
12510 JUMP_LABEL (place) = XEXP (note, 0);
12511 else if (LABEL_P (label))
12512 LABEL_NUSES (label)--;
12515 if (place2 && JUMP_P (place2)
12516 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12517 && (JUMP_LABEL (place2) == NULL
12518 || JUMP_LABEL (place2) == XEXP (note, 0)))
12520 rtx label = JUMP_LABEL (place2);
12523 JUMP_LABEL (place2) = XEXP (note, 0);
12524 else if (LABEL_P (label))
12525 LABEL_NUSES (label)--;
12531 /* This note says something about the value of a register prior
12532 to the execution of an insn. It is too much trouble to see
12533 if the note is still correct in all situations. It is better
12534 to simply delete it. */
12538 /* If we replaced the right hand side of FROM_INSN with a
12539 REG_EQUAL note, the original use of the dying register
12540 will not have been combined into I3 and I2. In such cases,
12541 FROM_INSN is guaranteed to be the first of the combined
12542 instructions, so we simply need to search back before
12543 FROM_INSN for the previous use or set of this register,
12544 then alter the notes there appropriately.
12546 If the register is used as an input in I3, it dies there.
12547 Similarly for I2, if it is nonzero and adjacent to I3.
12549 If the register is not used as an input in either I3 or I2
12550 and it is not one of the registers we were supposed to eliminate,
12551 there are two possibilities. We might have a non-adjacent I2
12552 or we might have somehow eliminated an additional register
12553 from a computation. For example, we might have had A & B where
12554 we discover that B will always be zero. In this case we will
12555 eliminate the reference to A.
12557 In both cases, we must search to see if we can find a previous
12558 use of A and put the death note there. */
12561 && from_insn == i2mod
12562 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12567 && CALL_P (from_insn)
12568 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12570 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12572 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12573 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12575 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12577 && reg_overlap_mentioned_p (XEXP (note, 0),
12579 || rtx_equal_p (XEXP (note, 0), elim_i1))
12586 basic_block bb = this_basic_block;
12588 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12590 if (! INSN_P (tem))
12592 if (tem == BB_HEAD (bb))
12597 /* If the register is being set at TEM, see if that is all
12598 TEM is doing. If so, delete TEM. Otherwise, make this
12599 into a REG_UNUSED note instead. Don't delete sets to
12600 global register vars. */
12601 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12602 || !global_regs[REGNO (XEXP (note, 0))])
12603 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12605 rtx set = single_set (tem);
12606 rtx inner_dest = 0;
12608 rtx cc0_setter = NULL_RTX;
12612 for (inner_dest = SET_DEST (set);
12613 (GET_CODE (inner_dest) == STRICT_LOW_PART
12614 || GET_CODE (inner_dest) == SUBREG
12615 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12616 inner_dest = XEXP (inner_dest, 0))
12619 /* Verify that it was the set, and not a clobber that
12620 modified the register.
12622 CC0 targets must be careful to maintain setter/user
12623 pairs. If we cannot delete the setter due to side
12624 effects, mark the user with an UNUSED note instead
12627 if (set != 0 && ! side_effects_p (SET_SRC (set))
12628 && rtx_equal_p (XEXP (note, 0), inner_dest)
12630 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12631 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12632 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12636 /* Move the notes and links of TEM elsewhere.
12637 This might delete other dead insns recursively.
12638 First set the pattern to something that won't use
12640 rtx old_notes = REG_NOTES (tem);
12642 PATTERN (tem) = pc_rtx;
12643 REG_NOTES (tem) = NULL;
12645 distribute_notes (old_notes, tem, tem, NULL_RTX,
12646 NULL_RTX, NULL_RTX);
12647 distribute_links (LOG_LINKS (tem));
12649 SET_INSN_DELETED (tem);
12652 /* Delete the setter too. */
12655 PATTERN (cc0_setter) = pc_rtx;
12656 old_notes = REG_NOTES (cc0_setter);
12657 REG_NOTES (cc0_setter) = NULL;
12659 distribute_notes (old_notes, cc0_setter,
12660 cc0_setter, NULL_RTX,
12661 NULL_RTX, NULL_RTX);
12662 distribute_links (LOG_LINKS (cc0_setter));
12664 SET_INSN_DELETED (cc0_setter);
12670 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12672 /* If there isn't already a REG_UNUSED note, put one
12673 here. Do not place a REG_DEAD note, even if
12674 the register is also used here; that would not
12675 match the algorithm used in lifetime analysis
12676 and can cause the consistency check in the
12677 scheduler to fail. */
12678 if (! find_regno_note (tem, REG_UNUSED,
12679 REGNO (XEXP (note, 0))))
12684 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12686 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12690 /* If we are doing a 3->2 combination, and we have a
12691 register which formerly died in i3 and was not used
12692 by i2, which now no longer dies in i3 and is used in
12693 i2 but does not die in i2, and place is between i2
12694 and i3, then we may need to move a link from place to
12696 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12698 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12699 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12701 rtx links = LOG_LINKS (place);
12702 LOG_LINKS (place) = 0;
12703 distribute_links (links);
12708 if (tem == BB_HEAD (bb))
12714 /* If the register is set or already dead at PLACE, we needn't do
12715 anything with this note if it is still a REG_DEAD note.
12716 We check here if it is set at all, not if is it totally replaced,
12717 which is what `dead_or_set_p' checks, so also check for it being
12720 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12722 unsigned int regno = REGNO (XEXP (note, 0));
12723 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12725 if (dead_or_set_p (place, XEXP (note, 0))
12726 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12728 /* Unless the register previously died in PLACE, clear
12729 last_death. [I no longer understand why this is
12731 if (rsp->last_death != place)
12732 rsp->last_death = 0;
12736 rsp->last_death = place;
12738 /* If this is a death note for a hard reg that is occupying
12739 multiple registers, ensure that we are still using all
12740 parts of the object. If we find a piece of the object
12741 that is unused, we must arrange for an appropriate REG_DEAD
12742 note to be added for it. However, we can't just emit a USE
12743 and tag the note to it, since the register might actually
12744 be dead; so we recourse, and the recursive call then finds
12745 the previous insn that used this register. */
12747 if (place && regno < FIRST_PSEUDO_REGISTER
12748 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12750 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12754 for (i = regno; i < endregno; i++)
12755 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12756 && ! find_regno_fusage (place, USE, i))
12757 || dead_or_set_regno_p (place, i))
12762 /* Put only REG_DEAD notes for pieces that are
12763 not already dead or set. */
12765 for (i = regno; i < endregno;
12766 i += hard_regno_nregs[i][reg_raw_mode[i]])
12768 rtx piece = regno_reg_rtx[i];
12769 basic_block bb = this_basic_block;
12771 if (! dead_or_set_p (place, piece)
12772 && ! reg_bitfield_target_p (piece,
12776 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12778 distribute_notes (new_note, place, place,
12779 NULL_RTX, NULL_RTX, NULL_RTX);
12781 else if (! refers_to_regno_p (i, i + 1,
12782 PATTERN (place), 0)
12783 && ! find_regno_fusage (place, USE, i))
12784 for (tem = PREV_INSN (place); ;
12785 tem = PREV_INSN (tem))
12787 if (! INSN_P (tem))
12789 if (tem == BB_HEAD (bb))
12793 if (dead_or_set_p (tem, piece)
12794 || reg_bitfield_target_p (piece,
12797 add_reg_note (tem, REG_UNUSED, piece);
12811 /* Any other notes should not be present at this point in the
12813 gcc_unreachable ();
12818 XEXP (note, 1) = REG_NOTES (place);
12819 REG_NOTES (place) = note;
12824 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12825 XEXP (note, 0), REG_NOTES (place2));
12829 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12830 I3, I2, and I1 to new locations. This is also called to add a link
12831 pointing at I3 when I3's destination is changed. */
12834 distribute_links (rtx links)
12836 rtx link, next_link;
12838 for (link = links; link; link = next_link)
12844 next_link = XEXP (link, 1);
12846 /* If the insn that this link points to is a NOTE or isn't a single
12847 set, ignore it. In the latter case, it isn't clear what we
12848 can do other than ignore the link, since we can't tell which
12849 register it was for. Such links wouldn't be used by combine
12852 It is not possible for the destination of the target of the link to
12853 have been changed by combine. The only potential of this is if we
12854 replace I3, I2, and I1 by I3 and I2. But in that case the
12855 destination of I2 also remains unchanged. */
12857 if (NOTE_P (XEXP (link, 0))
12858 || (set = single_set (XEXP (link, 0))) == 0)
12861 reg = SET_DEST (set);
12862 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12863 || GET_CODE (reg) == STRICT_LOW_PART)
12864 reg = XEXP (reg, 0);
12866 /* A LOG_LINK is defined as being placed on the first insn that uses
12867 a register and points to the insn that sets the register. Start
12868 searching at the next insn after the target of the link and stop
12869 when we reach a set of the register or the end of the basic block.
12871 Note that this correctly handles the link that used to point from
12872 I3 to I2. Also note that not much searching is typically done here
12873 since most links don't point very far away. */
12875 for (insn = NEXT_INSN (XEXP (link, 0));
12876 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12877 || BB_HEAD (this_basic_block->next_bb) != insn));
12878 insn = NEXT_INSN (insn))
12879 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12881 if (reg_referenced_p (reg, PATTERN (insn)))
12885 else if (CALL_P (insn)
12886 && find_reg_fusage (insn, USE, reg))
12891 else if (INSN_P (insn) && reg_set_p (reg, insn))
12894 /* If we found a place to put the link, place it there unless there
12895 is already a link to the same insn as LINK at that point. */
12901 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12902 if (XEXP (link2, 0) == XEXP (link, 0))
12907 XEXP (link, 1) = LOG_LINKS (place);
12908 LOG_LINKS (place) = link;
12910 /* Set added_links_insn to the earliest insn we added a
12912 if (added_links_insn == 0
12913 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12914 added_links_insn = place;
12920 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12921 Check whether the expression pointer to by LOC is a register or
12922 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12923 Otherwise return zero. */
12926 unmentioned_reg_p_1 (rtx *loc, void *expr)
12931 && (REG_P (x) || MEM_P (x))
12932 && ! reg_mentioned_p (x, (rtx) expr))
12937 /* Check for any register or memory mentioned in EQUIV that is not
12938 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12939 of EXPR where some registers may have been replaced by constants. */
12942 unmentioned_reg_p (rtx equiv, rtx expr)
12944 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12948 dump_combine_stats (FILE *file)
12952 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12953 combine_attempts, combine_merges, combine_extras, combine_successes);
12957 dump_combine_total_stats (FILE *file)
12961 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12962 total_attempts, total_merges, total_extras, total_successes);
12966 gate_handle_combine (void)
12968 return (optimize > 0);
12971 /* Try combining insns through substitution. */
12972 static unsigned int
12973 rest_of_handle_combine (void)
12975 int rebuild_jump_labels_after_combine;
12977 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
12978 df_note_add_problem ();
12981 regstat_init_n_sets_and_refs ();
12983 rebuild_jump_labels_after_combine
12984 = combine_instructions (get_insns (), max_reg_num ());
12986 /* Combining insns may have turned an indirect jump into a
12987 direct jump. Rebuild the JUMP_LABEL fields of jumping
12989 if (rebuild_jump_labels_after_combine)
12991 timevar_push (TV_JUMP);
12992 rebuild_jump_labels (get_insns ());
12994 timevar_pop (TV_JUMP);
12997 regstat_free_n_sets_and_refs ();
13001 struct rtl_opt_pass pass_combine =
13005 "combine", /* name */
13006 gate_handle_combine, /* gate */
13007 rest_of_handle_combine, /* execute */
13010 0, /* static_pass_number */
13011 TV_COMBINE, /* tv_id */
13012 0, /* properties_required */
13013 0, /* properties_provided */
13014 0, /* properties_destroyed */
13015 0, /* todo_flags_start */
13017 TODO_df_finish | TODO_verify_rtl_sharing |
13018 TODO_ggc_collect, /* todo_flags_finish */
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