1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
79 /* Must precede rtl.h for FFS. */
85 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
95 /* It is not safe to use ordinary gen_lowpart in combine.
96 Use gen_lowpart_for_combine instead. See comments there. */
97 #define gen_lowpart dont_use_gen_lowpart_you_dummy
99 /* Number of attempts to combine instructions in this function. */
101 static int combine_attempts;
103 /* Number of attempts that got as far as substitution in this function. */
105 static int combine_merges;
107 /* Number of instructions combined with added SETs in this function. */
109 static int combine_extras;
111 /* Number of instructions combined in this function. */
113 static int combine_successes;
115 /* Totals over entire compilation. */
117 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
128 /* Get the cuid of an insn. */
130 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
132 /* Maximum register number, which is the size of the tables below. */
134 static int combine_max_regno;
136 /* Record last point of death of (hard or pseudo) register n. */
138 static rtx *reg_last_death;
140 /* Record last point of modification of (hard or pseudo) register n. */
142 static rtx *reg_last_set;
144 /* Record the cuid of the last insn that invalidated memory
145 (anything that writes memory, and subroutine calls, but not pushes). */
147 static int mem_last_set;
149 /* Record the cuid of the last CALL_INSN
150 so we can tell whether a potential combination crosses any calls. */
152 static int last_call_cuid;
154 /* When `subst' is called, this is the insn that is being modified
155 (by combining in a previous insn). The PATTERN of this insn
156 is still the old pattern partially modified and it should not be
157 looked at, but this may be used to examine the successors of the insn
158 to judge whether a simplification is valid. */
160 static rtx subst_insn;
162 /* If nonzero, this is the insn that should be presumed to be
163 immediately in front of `subst_insn'. */
165 static rtx subst_prev_insn;
167 /* This is the lowest CUID that `subst' is currently dealing with.
168 get_last_value will not return a value if the register was set at or
169 after this CUID. If not for this mechanism, we could get confused if
170 I2 or I1 in try_combine were an insn that used the old value of a register
171 to obtain a new value. In that case, we might erroneously get the
172 new value of the register when we wanted the old one. */
174 static int subst_low_cuid;
176 /* This is the value of undobuf.num_undo when we started processing this
177 substitution. This will prevent gen_rtx_combine from re-used a piece
178 from the previous expression. Doing so can produce circular rtl
181 static int previous_num_undos;
183 /* Basic block number of the block in which we are performing combines. */
184 static int this_basic_block;
186 /* The next group of arrays allows the recording of the last value assigned
187 to (hard or pseudo) register n. We use this information to see if a
188 operation being processed is redundant given a prior operation performed
189 on the register. For example, an `and' with a constant is redundant if
190 all the zero bits are already known to be turned off.
192 We use an approach similar to that used by cse, but change it in the
195 (1) We do not want to reinitialize at each label.
196 (2) It is useful, but not critical, to know the actual value assigned
197 to a register. Often just its form is helpful.
199 Therefore, we maintain the following arrays:
201 reg_last_set_value the last value assigned
202 reg_last_set_label records the value of label_tick when the
203 register was assigned
204 reg_last_set_table_tick records the value of label_tick when a
205 value using the register is assigned
206 reg_last_set_invalid set to non-zero when it is not valid
207 to use the value of this register in some
210 To understand the usage of these tables, it is important to understand
211 the distinction between the value in reg_last_set_value being valid
212 and the register being validly contained in some other expression in the
215 Entry I in reg_last_set_value is valid if it is non-zero, and either
216 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
218 Register I may validly appear in any expression returned for the value
219 of another register if reg_n_sets[i] is 1. It may also appear in the
220 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
221 reg_last_set_invalid[j] is zero.
223 If an expression is found in the table containing a register which may
224 not validly appear in an expression, the register is replaced by
225 something that won't match, (clobber (const_int 0)).
227 reg_last_set_invalid[i] is set non-zero when register I is being assigned
228 to and reg_last_set_table_tick[i] == label_tick. */
230 /* Record last value assigned to (hard or pseudo) register n. */
232 static rtx *reg_last_set_value;
234 /* Record the value of label_tick when the value for register n is placed in
235 reg_last_set_value[n]. */
237 static int *reg_last_set_label;
239 /* Record the value of label_tick when an expression involving register n
240 is placed in reg_last_set_value. */
242 static int *reg_last_set_table_tick;
244 /* Set non-zero if references to register n in expressions should not be
247 static char *reg_last_set_invalid;
249 /* Incremented for each label. */
251 static int label_tick;
253 /* Some registers that are set more than once and used in more than one
254 basic block are nevertheless always set in similar ways. For example,
255 a QImode register may be loaded from memory in two places on a machine
256 where byte loads zero extend.
258 We record in the following array what we know about the nonzero
259 bits of a register, specifically which bits are known to be zero.
261 If an entry is zero, it means that we don't know anything special. */
263 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
265 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
266 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
268 static enum machine_mode nonzero_bits_mode;
270 /* Nonzero if we know that a register has some leading bits that are always
271 equal to the sign bit. */
273 static char *reg_sign_bit_copies;
275 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
276 It is zero while computing them and after combine has completed. This
277 former test prevents propagating values based on previously set values,
278 which can be incorrect if a variable is modified in a loop. */
280 static int nonzero_sign_valid;
282 /* These arrays are maintained in parallel with reg_last_set_value
283 and are used to store the mode in which the register was last set,
284 the bits that were known to be zero when it was last set, and the
285 number of sign bits copies it was known to have when it was last set. */
287 static enum machine_mode *reg_last_set_mode;
288 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
289 static char *reg_last_set_sign_bit_copies;
291 /* Record one modification to rtl structure
292 to be undone by storing old_contents into *where.
293 is_int is 1 if the contents are an int. */
298 union {rtx r; int i;} old_contents;
299 union {rtx *r; int *i;} where;
302 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
303 num_undo says how many are currently recorded.
305 storage is nonzero if we must undo the allocation of new storage.
306 The value of storage is what to pass to obfree.
308 other_insn is nonzero if we have modified some other insn in the process
309 of working on subst_insn. It must be verified too. */
317 struct undo undo[MAX_UNDO];
321 static struct undobuf undobuf;
323 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
324 insn. The substitution can be undone by undo_all. If INTO is already
325 set to NEWVAL, do not record this change. Because computing NEWVAL might
326 also call SUBST, we have to compute it before we put anything into
329 #define SUBST(INTO, NEWVAL) \
330 do { rtx _new = (NEWVAL); \
331 if (undobuf.num_undo < MAX_UNDO) \
333 undobuf.undo[undobuf.num_undo].is_int = 0; \
334 undobuf.undo[undobuf.num_undo].where.r = &INTO; \
335 undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \
337 if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \
338 undobuf.num_undo++; \
342 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
344 Note that substitution for the value of a CONST_INT is not safe. */
346 #define SUBST_INT(INTO, NEWVAL) \
347 do { if (undobuf.num_undo < MAX_UNDO) \
349 undobuf.undo[undobuf.num_undo].is_int = 1; \
350 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
351 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
353 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
354 undobuf.num_undo++; \
358 /* Number of times the pseudo being substituted for
359 was found and replaced. */
361 static int n_occurrences;
363 static void init_reg_last_arrays PROTO(());
364 static void setup_incoming_promotions PROTO(());
365 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
366 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
367 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
368 static rtx try_combine PROTO((rtx, rtx, rtx));
369 static void undo_all PROTO((void));
370 static rtx *find_split_point PROTO((rtx *, rtx));
371 static rtx subst PROTO((rtx, rtx, rtx, int, int));
372 static rtx expand_compound_operation PROTO((rtx));
373 static rtx expand_field_assignment PROTO((rtx));
374 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
376 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
377 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
378 static rtx force_to_mode PROTO((rtx, enum machine_mode,
379 unsigned HOST_WIDE_INT, rtx, int));
380 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
381 static rtx make_field_assignment PROTO((rtx));
382 static rtx apply_distributive_law PROTO((rtx));
383 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
384 unsigned HOST_WIDE_INT));
385 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
386 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
387 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
388 enum rtx_code, HOST_WIDE_INT,
389 enum machine_mode, int *));
390 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
392 static int recog_for_combine PROTO((rtx *, rtx, rtx *));
393 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
394 static rtx gen_rtx_combine (); /* This is varargs. */
395 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
397 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode, rtx));
398 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
399 static int reversible_comparison_p PROTO((rtx));
400 static void update_table_tick PROTO((rtx));
401 static void record_value_for_reg PROTO((rtx, rtx, rtx));
402 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
403 static void record_dead_and_set_regs PROTO((rtx));
404 static int get_last_value_validate PROTO((rtx *, int, int));
405 static rtx get_last_value PROTO((rtx));
406 static int use_crosses_set_p PROTO((rtx, int));
407 static void reg_dead_at_p_1 PROTO((rtx, rtx));
408 static int reg_dead_at_p PROTO((rtx, rtx));
409 static void move_deaths PROTO((rtx, int, rtx, rtx *));
410 static int reg_bitfield_target_p PROTO((rtx, rtx));
411 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
412 static void distribute_links PROTO((rtx));
414 /* Main entry point for combiner. F is the first insn of the function.
415 NREGS is the first unused pseudo-reg number. */
418 combine_instructions (f, nregs)
422 register rtx insn, next, prev;
424 register rtx links, nextlinks;
426 combine_attempts = 0;
429 combine_successes = 0;
430 undobuf.num_undo = previous_num_undos = 0;
432 combine_max_regno = nregs;
435 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
436 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
438 bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
439 bzero (reg_sign_bit_copies, nregs * sizeof (char));
441 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
442 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
443 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
444 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
445 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
446 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
448 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
449 reg_last_set_nonzero_bits
450 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
451 reg_last_set_sign_bit_copies
452 = (char *) alloca (nregs * sizeof (char));
454 init_reg_last_arrays ();
456 init_recog_no_volatile ();
458 /* Compute maximum uid value so uid_cuid can be allocated. */
460 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
461 if (INSN_UID (insn) > i)
464 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
466 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
468 /* Don't use reg_nonzero_bits when computing it. This can cause problems
469 when, for example, we have j <<= 1 in a loop. */
471 nonzero_sign_valid = 0;
473 /* Compute the mapping from uids to cuids.
474 Cuids are numbers assigned to insns, like uids,
475 except that cuids increase monotonically through the code.
477 Scan all SETs and see if we can deduce anything about what
478 bits are known to be zero for some registers and how many copies
479 of the sign bit are known to exist for those registers.
481 Also set any known values so that we can use it while searching
482 for what bits are known to be set. */
486 setup_incoming_promotions ();
488 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
490 INSN_CUID (insn) = ++i;
494 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
496 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
497 record_dead_and_set_regs (insn);
500 if (GET_CODE (insn) == CODE_LABEL)
504 nonzero_sign_valid = 1;
506 /* Now scan all the insns in forward order. */
508 this_basic_block = -1;
512 init_reg_last_arrays ();
513 setup_incoming_promotions ();
515 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
519 /* If INSN starts a new basic block, update our basic block number. */
520 if (this_basic_block + 1 < n_basic_blocks
521 && basic_block_head[this_basic_block + 1] == insn)
524 if (GET_CODE (insn) == CODE_LABEL)
527 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
529 /* Try this insn with each insn it links back to. */
531 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
532 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
535 /* Try each sequence of three linked insns ending with this one. */
537 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
538 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
539 nextlinks = XEXP (nextlinks, 1))
540 if ((next = try_combine (insn, XEXP (links, 0),
541 XEXP (nextlinks, 0))) != 0)
545 /* Try to combine a jump insn that uses CC0
546 with a preceding insn that sets CC0, and maybe with its
547 logical predecessor as well.
548 This is how we make decrement-and-branch insns.
549 We need this special code because data flow connections
550 via CC0 do not get entered in LOG_LINKS. */
552 if (GET_CODE (insn) == JUMP_INSN
553 && (prev = prev_nonnote_insn (insn)) != 0
554 && GET_CODE (prev) == INSN
555 && sets_cc0_p (PATTERN (prev)))
557 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
560 for (nextlinks = LOG_LINKS (prev); nextlinks;
561 nextlinks = XEXP (nextlinks, 1))
562 if ((next = try_combine (insn, prev,
563 XEXP (nextlinks, 0))) != 0)
567 /* Do the same for an insn that explicitly references CC0. */
568 if (GET_CODE (insn) == INSN
569 && (prev = prev_nonnote_insn (insn)) != 0
570 && GET_CODE (prev) == INSN
571 && sets_cc0_p (PATTERN (prev))
572 && GET_CODE (PATTERN (insn)) == SET
573 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
575 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
578 for (nextlinks = LOG_LINKS (prev); nextlinks;
579 nextlinks = XEXP (nextlinks, 1))
580 if ((next = try_combine (insn, prev,
581 XEXP (nextlinks, 0))) != 0)
585 /* Finally, see if any of the insns that this insn links to
586 explicitly references CC0. If so, try this insn, that insn,
587 and its predecessor if it sets CC0. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if (GET_CODE (XEXP (links, 0)) == INSN
590 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
591 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
592 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
593 && GET_CODE (prev) == INSN
594 && sets_cc0_p (PATTERN (prev))
595 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
599 /* Try combining an insn with two different insns whose results it
601 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
602 for (nextlinks = XEXP (links, 1); nextlinks;
603 nextlinks = XEXP (nextlinks, 1))
604 if ((next = try_combine (insn, XEXP (links, 0),
605 XEXP (nextlinks, 0))) != 0)
608 if (GET_CODE (insn) != NOTE)
609 record_dead_and_set_regs (insn);
616 total_attempts += combine_attempts;
617 total_merges += combine_merges;
618 total_extras += combine_extras;
619 total_successes += combine_successes;
621 nonzero_sign_valid = 0;
624 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
627 init_reg_last_arrays ()
629 int nregs = combine_max_regno;
631 bzero (reg_last_death, nregs * sizeof (rtx));
632 bzero (reg_last_set, nregs * sizeof (rtx));
633 bzero (reg_last_set_value, nregs * sizeof (rtx));
634 bzero (reg_last_set_table_tick, nregs * sizeof (int));
635 bzero (reg_last_set_label, nregs * sizeof (int));
636 bzero (reg_last_set_invalid, nregs * sizeof (char));
637 bzero (reg_last_set_mode, nregs * sizeof (enum machine_mode));
638 bzero (reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
639 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
642 /* Set up any promoted values for incoming argument registers. */
645 setup_incoming_promotions ()
647 #ifdef PROMOTE_FUNCTION_ARGS
650 enum machine_mode mode;
652 rtx first = get_insns ();
654 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
655 if (FUNCTION_ARG_REGNO_P (regno)
656 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
657 record_value_for_reg (reg, first,
658 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
660 gen_rtx (CLOBBER, mode, const0_rtx)));
664 /* Called via note_stores. If X is a pseudo that is used in more than
665 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
666 set, record what bits are known zero. If we are clobbering X,
667 ignore this "set" because the clobbered value won't be used.
669 If we are setting only a portion of X and we can't figure out what
670 portion, assume all bits will be used since we don't know what will
673 Similarly, set how many bits of X are known to be copies of the sign bit
674 at all locations in the function. This is the smallest number implied
678 set_nonzero_bits_and_sign_copies (x, set)
684 if (GET_CODE (x) == REG
685 && REGNO (x) >= FIRST_PSEUDO_REGISTER
686 && reg_n_sets[REGNO (x)] > 1
687 && reg_basic_block[REGNO (x)] < 0
688 /* If this register is undefined at the start of the file, we can't
689 say what its contents were. */
690 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
691 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
692 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
694 if (GET_CODE (set) == CLOBBER)
696 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
697 reg_sign_bit_copies[REGNO (x)] = 0;
701 /* If this is a complex assignment, see if we can convert it into a
702 simple assignment. */
703 set = expand_field_assignment (set);
705 /* If this is a simple assignment, or we have a paradoxical SUBREG,
706 set what we know about X. */
708 if (SET_DEST (set) == x
709 || (GET_CODE (SET_DEST (set)) == SUBREG
710 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
711 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
712 && SUBREG_REG (SET_DEST (set)) == x))
714 rtx src = SET_SRC (set);
716 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
717 /* If X is narrower than a word and SRC is a non-negative
718 constant that would appear negative in the mode of X,
719 sign-extend it for use in reg_nonzero_bits because some
720 machines (maybe most) will actually do the sign-extension
721 and this is the conservative approach.
723 ??? For 2.5, try to tighten up the MD files in this regard
724 instead of this kludge. */
726 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
727 && GET_CODE (src) == CONST_INT
729 && 0 != (INTVAL (src)
731 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
732 src = GEN_INT (INTVAL (src)
733 | ((HOST_WIDE_INT) (-1)
734 << GET_MODE_BITSIZE (GET_MODE (x))));
737 reg_nonzero_bits[REGNO (x)]
738 |= nonzero_bits (src, nonzero_bits_mode);
739 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
740 if (reg_sign_bit_copies[REGNO (x)] == 0
741 || reg_sign_bit_copies[REGNO (x)] > num)
742 reg_sign_bit_copies[REGNO (x)] = num;
746 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
747 reg_sign_bit_copies[REGNO (x)] = 0;
752 /* See if INSN can be combined into I3. PRED and SUCC are optionally
753 insns that were previously combined into I3 or that will be combined
754 into the merger of INSN and I3.
756 Return 0 if the combination is not allowed for any reason.
758 If the combination is allowed, *PDEST will be set to the single
759 destination of INSN and *PSRC to the single source, and this function
763 can_combine_p (insn, i3, pred, succ, pdest, psrc)
770 rtx set = 0, src, dest;
772 int all_adjacent = (succ ? (next_active_insn (insn) == succ
773 && next_active_insn (succ) == i3)
774 : next_active_insn (insn) == i3);
776 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
777 or a PARALLEL consisting of such a SET and CLOBBERs.
779 If INSN has CLOBBER parallel parts, ignore them for our processing.
780 By definition, these happen during the execution of the insn. When it
781 is merged with another insn, all bets are off. If they are, in fact,
782 needed and aren't also supplied in I3, they may be added by
783 recog_for_combine. Otherwise, it won't match.
785 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
788 Get the source and destination of INSN. If more than one, can't
791 if (GET_CODE (PATTERN (insn)) == SET)
792 set = PATTERN (insn);
793 else if (GET_CODE (PATTERN (insn)) == PARALLEL
794 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
796 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
798 rtx elt = XVECEXP (PATTERN (insn), 0, i);
800 switch (GET_CODE (elt))
802 /* We can ignore CLOBBERs. */
807 /* Ignore SETs whose result isn't used but not those that
808 have side-effects. */
809 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
810 && ! side_effects_p (elt))
813 /* If we have already found a SET, this is a second one and
814 so we cannot combine with this insn. */
822 /* Anything else means we can't combine. */
828 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
829 so don't do anything with it. */
830 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
839 set = expand_field_assignment (set);
840 src = SET_SRC (set), dest = SET_DEST (set);
842 /* Don't eliminate a store in the stack pointer. */
843 if (dest == stack_pointer_rtx
844 /* If we couldn't eliminate a field assignment, we can't combine. */
845 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
846 /* Don't combine with an insn that sets a register to itself if it has
847 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
848 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
849 /* Can't merge a function call. */
850 || GET_CODE (src) == CALL
851 /* Don't substitute into an incremented register. */
852 || FIND_REG_INC_NOTE (i3, dest)
853 || (succ && FIND_REG_INC_NOTE (succ, dest))
854 /* Don't combine the end of a libcall into anything. */
855 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
856 /* Make sure that DEST is not used after SUCC but before I3. */
857 || (succ && ! all_adjacent
858 && reg_used_between_p (dest, succ, i3))
859 /* Make sure that the value that is to be substituted for the register
860 does not use any registers whose values alter in between. However,
861 If the insns are adjacent, a use can't cross a set even though we
862 think it might (this can happen for a sequence of insns each setting
863 the same destination; reg_last_set of that register might point to
864 a NOTE). If INSN has a REG_EQUIV note, the register is always
865 equivalent to the memory so the substitution is valid even if there
866 are intervening stores. Also, don't move a volatile asm or
867 UNSPEC_VOLATILE across any other insns. */
869 && (((GET_CODE (src) != MEM
870 || ! find_reg_note (insn, REG_EQUIV, src))
871 && use_crosses_set_p (src, INSN_CUID (insn)))
872 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
873 || GET_CODE (src) == UNSPEC_VOLATILE))
874 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
875 better register allocation by not doing the combine. */
876 || find_reg_note (i3, REG_NO_CONFLICT, dest)
877 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
878 /* Don't combine across a CALL_INSN, because that would possibly
879 change whether the life span of some REGs crosses calls or not,
880 and it is a pain to update that information.
881 Exception: if source is a constant, moving it later can't hurt.
882 Accept that special case, because it helps -fforce-addr a lot. */
883 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
886 /* DEST must either be a REG or CC0. */
887 if (GET_CODE (dest) == REG)
889 /* If register alignment is being enforced for multi-word items in all
890 cases except for parameters, it is possible to have a register copy
891 insn referencing a hard register that is not allowed to contain the
892 mode being copied and which would not be valid as an operand of most
893 insns. Eliminate this problem by not combining with such an insn.
895 Also, on some machines we don't want to extend the life of a hard
898 if (GET_CODE (src) == REG
899 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
900 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
901 #ifdef SMALL_REGISTER_CLASSES
902 /* Don't extend the life of a hard register. */
903 || REGNO (src) < FIRST_PSEUDO_REGISTER
905 || (REGNO (src) < FIRST_PSEUDO_REGISTER
906 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
911 else if (GET_CODE (dest) != CC0)
914 /* Don't substitute for a register intended as a clobberable operand.
915 Similarly, don't substitute an expression containing a register that
916 will be clobbered in I3. */
917 if (GET_CODE (PATTERN (i3)) == PARALLEL)
918 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
919 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
920 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
922 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
925 /* If INSN contains anything volatile, or is an `asm' (whether volatile
926 or not), reject, unless nothing volatile comes between it and I3,
927 with the exception of SUCC. */
929 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
930 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
931 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
932 && p != succ && volatile_refs_p (PATTERN (p)))
935 /* If there are any volatile insns between INSN and I3, reject, because
936 they might affect machine state. */
938 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
939 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
940 && p != succ && volatile_insn_p (PATTERN (p)))
943 /* If INSN or I2 contains an autoincrement or autodecrement,
944 make sure that register is not used between there and I3,
945 and not already used in I3 either.
946 Also insist that I3 not be a jump; if it were one
947 and the incremented register were spilled, we would lose. */
950 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
951 if (REG_NOTE_KIND (link) == REG_INC
952 && (GET_CODE (i3) == JUMP_INSN
953 || reg_used_between_p (XEXP (link, 0), insn, i3)
954 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
959 /* Don't combine an insn that follows a CC0-setting insn.
960 An insn that uses CC0 must not be separated from the one that sets it.
961 We do, however, allow I2 to follow a CC0-setting insn if that insn
962 is passed as I1; in that case it will be deleted also.
963 We also allow combining in this case if all the insns are adjacent
964 because that would leave the two CC0 insns adjacent as well.
965 It would be more logical to test whether CC0 occurs inside I1 or I2,
966 but that would be much slower, and this ought to be equivalent. */
968 p = prev_nonnote_insn (insn);
969 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
974 /* If we get here, we have passed all the tests and the combination is
983 /* LOC is the location within I3 that contains its pattern or the component
984 of a PARALLEL of the pattern. We validate that it is valid for combining.
986 One problem is if I3 modifies its output, as opposed to replacing it
987 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
988 so would produce an insn that is not equivalent to the original insns.
992 (set (reg:DI 101) (reg:DI 100))
993 (set (subreg:SI (reg:DI 101) 0) <foo>)
995 This is NOT equivalent to:
997 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
998 (set (reg:DI 101) (reg:DI 100))])
1000 Not only does this modify 100 (in which case it might still be valid
1001 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1003 We can also run into a problem if I2 sets a register that I1
1004 uses and I1 gets directly substituted into I3 (not via I2). In that
1005 case, we would be getting the wrong value of I2DEST into I3, so we
1006 must reject the combination. This case occurs when I2 and I1 both
1007 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1008 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1009 of a SET must prevent combination from occurring.
1011 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1012 if the destination of a SET is a hard register.
1014 Before doing the above check, we first try to expand a field assignment
1015 into a set of logical operations.
1017 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1018 we place a register that is both set and used within I3. If more than one
1019 such register is detected, we fail.
1021 Return 1 if the combination is valid, zero otherwise. */
1024 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1030 rtx *pi3dest_killed;
1034 if (GET_CODE (x) == SET)
1036 rtx set = expand_field_assignment (x);
1037 rtx dest = SET_DEST (set);
1038 rtx src = SET_SRC (set);
1039 rtx inner_dest = dest, inner_src = src;
1043 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1044 || GET_CODE (inner_dest) == SUBREG
1045 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1046 inner_dest = XEXP (inner_dest, 0);
1048 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1051 while (GET_CODE (inner_src) == STRICT_LOW_PART
1052 || GET_CODE (inner_src) == SUBREG
1053 || GET_CODE (inner_src) == ZERO_EXTRACT)
1054 inner_src = XEXP (inner_src, 0);
1056 /* If it is better that two different modes keep two different pseudos,
1057 avoid combining them. This avoids producing the following pattern
1059 (set (subreg:SI (reg/v:QI 21) 0)
1060 (lshiftrt:SI (reg/v:SI 20)
1062 If that were made, reload could not handle the pair of
1063 reg 20/21, since it would try to get any GENERAL_REGS
1064 but some of them don't handle QImode. */
1066 if (rtx_equal_p (inner_src, i2dest)
1067 && GET_CODE (inner_dest) == REG
1068 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1072 /* Check for the case where I3 modifies its output, as
1074 if ((inner_dest != dest
1075 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1076 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1077 /* This is the same test done in can_combine_p except that we
1078 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1080 || (GET_CODE (inner_dest) == REG
1081 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1082 #ifdef SMALL_REGISTER_CLASSES
1083 && GET_CODE (src) != CALL
1085 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1086 GET_MODE (inner_dest))
1090 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1093 /* If DEST is used in I3, it is being killed in this insn,
1094 so record that for later.
1095 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1096 STACK_POINTER_REGNUM, since these are always considered to be
1097 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1098 if (pi3dest_killed && GET_CODE (dest) == REG
1099 && reg_referenced_p (dest, PATTERN (i3))
1100 && REGNO (dest) != FRAME_POINTER_REGNUM
1101 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1102 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1104 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1105 && (REGNO (dest) != ARG_POINTER_REGNUM
1106 || ! fixed_regs [REGNO (dest)])
1108 && REGNO (dest) != STACK_POINTER_REGNUM)
1110 if (*pi3dest_killed)
1113 *pi3dest_killed = dest;
1117 else if (GET_CODE (x) == PARALLEL)
1121 for (i = 0; i < XVECLEN (x, 0); i++)
1122 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1123 i1_not_in_src, pi3dest_killed))
1130 /* Try to combine the insns I1 and I2 into I3.
1131 Here I1 and I2 appear earlier than I3.
1132 I1 can be zero; then we combine just I2 into I3.
1134 It we are combining three insns and the resulting insn is not recognized,
1135 try splitting it into two insns. If that happens, I2 and I3 are retained
1136 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1139 If we created two insns, return I2; otherwise return I3.
1140 Return 0 if the combination does not work. Then nothing is changed. */
1143 try_combine (i3, i2, i1)
1144 register rtx i3, i2, i1;
1146 /* New patterns for I3 and I3, respectively. */
1147 rtx newpat, newi2pat = 0;
1148 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1149 int added_sets_1, added_sets_2;
1150 /* Total number of SETs to put into I3. */
1152 /* Nonzero is I2's body now appears in I3. */
1154 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1155 int insn_code_number, i2_code_number, other_code_number;
1156 /* Contains I3 if the destination of I3 is used in its source, which means
1157 that the old life of I3 is being killed. If that usage is placed into
1158 I2 and not in I3, a REG_DEAD note must be made. */
1159 rtx i3dest_killed = 0;
1160 /* SET_DEST and SET_SRC of I2 and I1. */
1161 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1162 /* PATTERN (I2), or a copy of it in certain cases. */
1164 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1165 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1166 int i1_feeds_i3 = 0;
1167 /* Notes that must be added to REG_NOTES in I3 and I2. */
1168 rtx new_i3_notes, new_i2_notes;
1169 /* Notes that we substituted I3 into I2 instead of the normal case. */
1170 int i3_subst_into_i2 = 0;
1177 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1178 This can occur when flow deletes an insn that it has merged into an
1179 auto-increment address. We also can't do anything if I3 has a
1180 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1183 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1184 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1185 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1186 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1191 undobuf.num_undo = previous_num_undos = 0;
1192 undobuf.other_insn = 0;
1194 /* Save the current high-water-mark so we can free storage if we didn't
1195 accept this combination. */
1196 undobuf.storage = (char *) oballoc (0);
1198 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1199 code below, set I1 to be the earlier of the two insns. */
1200 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1201 temp = i1, i1 = i2, i2 = temp;
1203 subst_prev_insn = 0;
1205 /* First check for one important special-case that the code below will
1206 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1207 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1208 we may be able to replace that destination with the destination of I3.
1209 This occurs in the common code where we compute both a quotient and
1210 remainder into a structure, in which case we want to do the computation
1211 directly into the structure to avoid register-register copies.
1213 We make very conservative checks below and only try to handle the
1214 most common cases of this. For example, we only handle the case
1215 where I2 and I3 are adjacent to avoid making difficult register
1218 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1219 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1220 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1221 #ifdef SMALL_REGISTER_CLASSES
1222 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1223 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1225 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1226 && GET_CODE (PATTERN (i2)) == PARALLEL
1227 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1228 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1229 below would need to check what is inside (and reg_overlap_mentioned_p
1230 doesn't support those codes anyway). Don't allow those destinations;
1231 the resulting insn isn't likely to be recognized anyway. */
1232 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1233 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1234 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1235 SET_DEST (PATTERN (i3)))
1236 && next_real_insn (i2) == i3)
1238 rtx p2 = PATTERN (i2);
1240 /* Make sure that the destination of I3,
1241 which we are going to substitute into one output of I2,
1242 is not used within another output of I2. We must avoid making this:
1243 (parallel [(set (mem (reg 69)) ...)
1244 (set (reg 69) ...)])
1245 which is not well-defined as to order of actions.
1246 (Besides, reload can't handle output reloads for this.)
1248 The problem can also happen if the dest of I3 is a memory ref,
1249 if another dest in I2 is an indirect memory ref. */
1250 for (i = 0; i < XVECLEN (p2, 0); i++)
1251 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1252 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1253 SET_DEST (XVECEXP (p2, 0, i))))
1256 if (i == XVECLEN (p2, 0))
1257 for (i = 0; i < XVECLEN (p2, 0); i++)
1258 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1263 subst_low_cuid = INSN_CUID (i2);
1265 added_sets_2 = added_sets_1 = 0;
1266 i2dest = SET_SRC (PATTERN (i3));
1268 /* Replace the dest in I2 with our dest and make the resulting
1269 insn the new pattern for I3. Then skip to where we
1270 validate the pattern. Everything was set up above. */
1271 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1272 SET_DEST (PATTERN (i3)));
1275 i3_subst_into_i2 = 1;
1276 goto validate_replacement;
1281 /* If we have no I1 and I2 looks like:
1282 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1284 make up a dummy I1 that is
1287 (set (reg:CC X) (compare:CC Y (const_int 0)))
1289 (We can ignore any trailing CLOBBERs.)
1291 This undoes a previous combination and allows us to match a branch-and-
1294 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1295 && XVECLEN (PATTERN (i2), 0) >= 2
1296 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1297 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1299 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1300 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1301 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1302 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1303 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1304 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1306 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1307 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1312 /* We make I1 with the same INSN_UID as I2. This gives it
1313 the same INSN_CUID for value tracking. Our fake I1 will
1314 never appear in the insn stream so giving it the same INSN_UID
1315 as I2 will not cause a problem. */
1317 subst_prev_insn = i1
1318 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1319 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1321 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1322 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1323 SET_DEST (PATTERN (i1)));
1328 /* Verify that I2 and I1 are valid for combining. */
1329 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1330 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1336 /* Record whether I2DEST is used in I2SRC and similarly for the other
1337 cases. Knowing this will help in register status updating below. */
1338 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1339 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1340 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1342 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1344 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1346 /* Ensure that I3's pattern can be the destination of combines. */
1347 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1348 i1 && i2dest_in_i1src && i1_feeds_i3,
1355 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1356 We used to do this EXCEPT in one case: I3 has a post-inc in an
1357 output operand. However, that exception can give rise to insns like
1359 which is a famous insn on the PDP-11 where the value of r3 used as the
1360 source was model-dependent. Avoid this sort of thing. */
1363 if (!(GET_CODE (PATTERN (i3)) == SET
1364 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1365 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1366 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1367 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1368 /* It's not the exception. */
1371 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1372 if (REG_NOTE_KIND (link) == REG_INC
1373 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1375 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1382 /* See if the SETs in I1 or I2 need to be kept around in the merged
1383 instruction: whenever the value set there is still needed past I3.
1384 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1386 For the SET in I1, we have two cases: If I1 and I2 independently
1387 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1388 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1389 in I1 needs to be kept around unless I1DEST dies or is set in either
1390 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1391 I1DEST. If so, we know I1 feeds into I2. */
1393 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1396 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1397 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1399 /* If the set in I2 needs to be kept around, we must make a copy of
1400 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1401 PATTERN (I2), we are only substituting for the original I1DEST, not into
1402 an already-substituted copy. This also prevents making self-referential
1403 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1406 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1407 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1411 i2pat = copy_rtx (i2pat);
1415 /* Substitute in the latest insn for the regs set by the earlier ones. */
1417 maxreg = max_reg_num ();
1421 /* It is possible that the source of I2 or I1 may be performing an
1422 unneeded operation, such as a ZERO_EXTEND of something that is known
1423 to have the high part zero. Handle that case by letting subst look at
1424 the innermost one of them.
1426 Another way to do this would be to have a function that tries to
1427 simplify a single insn instead of merging two or more insns. We don't
1428 do this because of the potential of infinite loops and because
1429 of the potential extra memory required. However, doing it the way
1430 we are is a bit of a kludge and doesn't catch all cases.
1432 But only do this if -fexpensive-optimizations since it slows things down
1433 and doesn't usually win. */
1435 if (flag_expensive_optimizations)
1437 /* Pass pc_rtx so no substitutions are done, just simplifications.
1438 The cases that we are interested in here do not involve the few
1439 cases were is_replaced is checked. */
1442 subst_low_cuid = INSN_CUID (i1);
1443 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1447 subst_low_cuid = INSN_CUID (i2);
1448 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1451 previous_num_undos = undobuf.num_undo;
1455 /* Many machines that don't use CC0 have insns that can both perform an
1456 arithmetic operation and set the condition code. These operations will
1457 be represented as a PARALLEL with the first element of the vector
1458 being a COMPARE of an arithmetic operation with the constant zero.
1459 The second element of the vector will set some pseudo to the result
1460 of the same arithmetic operation. If we simplify the COMPARE, we won't
1461 match such a pattern and so will generate an extra insn. Here we test
1462 for this case, where both the comparison and the operation result are
1463 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1464 I2SRC. Later we will make the PARALLEL that contains I2. */
1466 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1467 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1468 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1469 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1472 enum machine_mode compare_mode;
1474 newpat = PATTERN (i3);
1475 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1479 #ifdef EXTRA_CC_MODES
1480 /* See if a COMPARE with the operand we substituted in should be done
1481 with the mode that is currently being used. If not, do the same
1482 processing we do in `subst' for a SET; namely, if the destination
1483 is used only once, try to replace it with a register of the proper
1484 mode and also replace the COMPARE. */
1485 if (undobuf.other_insn == 0
1486 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1487 &undobuf.other_insn))
1488 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1490 != GET_MODE (SET_DEST (newpat))))
1492 int regno = REGNO (SET_DEST (newpat));
1493 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1495 if (regno < FIRST_PSEUDO_REGISTER
1496 || (reg_n_sets[regno] == 1 && ! added_sets_2
1497 && ! REG_USERVAR_P (SET_DEST (newpat))))
1499 if (regno >= FIRST_PSEUDO_REGISTER)
1500 SUBST (regno_reg_rtx[regno], new_dest);
1502 SUBST (SET_DEST (newpat), new_dest);
1503 SUBST (XEXP (*cc_use, 0), new_dest);
1504 SUBST (SET_SRC (newpat),
1505 gen_rtx_combine (COMPARE, compare_mode,
1506 i2src, const0_rtx));
1509 undobuf.other_insn = 0;
1516 n_occurrences = 0; /* `subst' counts here */
1518 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1519 need to make a unique copy of I2SRC each time we substitute it
1520 to avoid self-referential rtl. */
1522 subst_low_cuid = INSN_CUID (i2);
1523 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1524 ! i1_feeds_i3 && i1dest_in_i1src);
1525 previous_num_undos = undobuf.num_undo;
1527 /* Record whether i2's body now appears within i3's body. */
1528 i2_is_used = n_occurrences;
1531 /* If we already got a failure, don't try to do more. Otherwise,
1532 try to substitute in I1 if we have it. */
1534 if (i1 && GET_CODE (newpat) != CLOBBER)
1536 /* Before we can do this substitution, we must redo the test done
1537 above (see detailed comments there) that ensures that I1DEST
1538 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1540 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1548 subst_low_cuid = INSN_CUID (i1);
1549 newpat = subst (newpat, i1dest, i1src, 0, 0);
1550 previous_num_undos = undobuf.num_undo;
1553 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1554 to count all the ways that I2SRC and I1SRC can be used. */
1555 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1556 && i2_is_used + added_sets_2 > 1)
1557 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1558 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1560 /* Fail if we tried to make a new register (we used to abort, but there's
1561 really no reason to). */
1562 || max_reg_num () != maxreg
1563 /* Fail if we couldn't do something and have a CLOBBER. */
1564 || GET_CODE (newpat) == CLOBBER)
1570 /* If the actions of the earlier insns must be kept
1571 in addition to substituting them into the latest one,
1572 we must make a new PARALLEL for the latest insn
1573 to hold additional the SETs. */
1575 if (added_sets_1 || added_sets_2)
1579 if (GET_CODE (newpat) == PARALLEL)
1581 rtvec old = XVEC (newpat, 0);
1582 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1583 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1584 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1585 sizeof (old->elem[0]) * old->num_elem);
1590 total_sets = 1 + added_sets_1 + added_sets_2;
1591 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1592 XVECEXP (newpat, 0, 0) = old;
1596 XVECEXP (newpat, 0, --total_sets)
1597 = (GET_CODE (PATTERN (i1)) == PARALLEL
1598 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1602 /* If there is no I1, use I2's body as is. We used to also not do
1603 the subst call below if I2 was substituted into I3,
1604 but that could lose a simplification. */
1606 XVECEXP (newpat, 0, --total_sets) = i2pat;
1608 /* See comment where i2pat is assigned. */
1609 XVECEXP (newpat, 0, --total_sets)
1610 = subst (i2pat, i1dest, i1src, 0, 0);
1614 /* We come here when we are replacing a destination in I2 with the
1615 destination of I3. */
1616 validate_replacement:
1618 /* Is the result of combination a valid instruction? */
1619 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1621 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1622 the second SET's destination is a register that is unused. In that case,
1623 we just need the first SET. This can occur when simplifying a divmod
1624 insn. We *must* test for this case here because the code below that
1625 splits two independent SETs doesn't handle this case correctly when it
1626 updates the register status. Also check the case where the first
1627 SET's destination is unused. That would not cause incorrect code, but
1628 does cause an unneeded insn to remain. */
1630 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1631 && XVECLEN (newpat, 0) == 2
1632 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1633 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1634 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1635 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1636 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1637 && asm_noperands (newpat) < 0)
1639 newpat = XVECEXP (newpat, 0, 0);
1640 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1643 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1644 && XVECLEN (newpat, 0) == 2
1645 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1646 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1647 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1648 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1649 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1650 && asm_noperands (newpat) < 0)
1652 newpat = XVECEXP (newpat, 0, 1);
1653 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1656 /* See if this is an XOR. If so, perhaps the problem is that the
1657 constant is out of range. Replace it with a complemented XOR with
1658 a complemented constant; it might be in range. */
1660 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1661 && GET_CODE (SET_SRC (newpat)) == XOR
1662 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1663 && ((temp = simplify_unary_operation (NOT,
1664 GET_MODE (SET_SRC (newpat)),
1665 XEXP (SET_SRC (newpat), 1),
1666 GET_MODE (SET_SRC (newpat))))
1669 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1671 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1672 gen_unary (NOT, i_mode,
1673 gen_binary (XOR, i_mode,
1674 XEXP (SET_SRC (newpat), 0),
1677 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1678 if (insn_code_number >= 0)
1682 /* If we were combining three insns and the result is a simple SET
1683 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1684 insns. There are two ways to do this. It can be split using a
1685 machine-specific method (like when you have an addition of a large
1686 constant) or by combine in the function find_split_point. */
1688 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1689 && asm_noperands (newpat) < 0)
1691 rtx m_split, *split;
1692 rtx ni2dest = i2dest;
1694 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1695 use I2DEST as a scratch register will help. In the latter case,
1696 convert I2DEST to the mode of the source of NEWPAT if we can. */
1698 m_split = split_insns (newpat, i3);
1700 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1701 inputs of NEWPAT. */
1703 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1704 possible to try that as a scratch reg. This would require adding
1705 more code to make it work though. */
1707 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1709 /* If I2DEST is a hard register or the only use of a pseudo,
1710 we can change its mode. */
1711 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1712 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1713 && GET_CODE (i2dest) == REG
1714 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1715 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1716 && ! REG_USERVAR_P (i2dest))))
1717 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1720 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1721 gen_rtvec (2, newpat,
1728 if (m_split && GET_CODE (m_split) == SEQUENCE
1729 && XVECLEN (m_split, 0) == 2
1730 && (next_real_insn (i2) == i3
1731 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1735 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1736 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1738 i3set = single_set (XVECEXP (m_split, 0, 1));
1739 i2set = single_set (XVECEXP (m_split, 0, 0));
1741 /* In case we changed the mode of I2DEST, replace it in the
1742 pseudo-register table here. We can't do it above in case this
1743 code doesn't get executed and we do a split the other way. */
1745 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1746 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1748 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1750 /* If I2 or I3 has multiple SETs, we won't know how to track
1751 register status, so don't use these insns. */
1753 if (i2_code_number >= 0 && i2set && i3set)
1754 insn_code_number = recog_for_combine (&newi3pat, i3,
1757 if (insn_code_number >= 0)
1760 /* It is possible that both insns now set the destination of I3.
1761 If so, we must show an extra use of it. */
1763 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1764 && GET_CODE (SET_DEST (i2set)) == REG
1765 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1766 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1769 /* If we can split it and use I2DEST, go ahead and see if that
1770 helps things be recognized. Verify that none of the registers
1771 are set between I2 and I3. */
1772 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1774 && GET_CODE (i2dest) == REG
1776 /* We need I2DEST in the proper mode. If it is a hard register
1777 or the only use of a pseudo, we can change its mode. */
1778 && (GET_MODE (*split) == GET_MODE (i2dest)
1779 || GET_MODE (*split) == VOIDmode
1780 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1781 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1782 && ! REG_USERVAR_P (i2dest)))
1783 && (next_real_insn (i2) == i3
1784 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1785 /* We can't overwrite I2DEST if its value is still used by
1787 && ! reg_referenced_p (i2dest, newpat))
1789 rtx newdest = i2dest;
1791 /* Get NEWDEST as a register in the proper mode. We have already
1792 validated that we can do this. */
1793 if (GET_MODE (i2dest) != GET_MODE (*split)
1794 && GET_MODE (*split) != VOIDmode)
1796 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1798 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1799 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1802 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1803 an ASHIFT. This can occur if it was inside a PLUS and hence
1804 appeared to be a memory address. This is a kludge. */
1805 if (GET_CODE (*split) == MULT
1806 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1807 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1808 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1809 XEXP (*split, 0), GEN_INT (i)));
1811 #ifdef INSN_SCHEDULING
1812 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1813 be written as a ZERO_EXTEND. */
1814 if (GET_CODE (*split) == SUBREG
1815 && GET_CODE (SUBREG_REG (*split)) == MEM)
1816 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1820 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1821 SUBST (*split, newdest);
1822 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1823 if (i2_code_number >= 0)
1824 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1828 /* Check for a case where we loaded from memory in a narrow mode and
1829 then sign extended it, but we need both registers. In that case,
1830 we have a PARALLEL with both loads from the same memory location.
1831 We can split this into a load from memory followed by a register-register
1832 copy. This saves at least one insn, more if register allocation can
1835 We cannot do this if the destination of the second assignment is
1836 a register that we have already assumed is zero-extended. Similarly
1837 for a SUBREG of such a register. */
1839 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1840 && GET_CODE (newpat) == PARALLEL
1841 && XVECLEN (newpat, 0) == 2
1842 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1843 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1844 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1845 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1846 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1847 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1849 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1850 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1851 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1852 (GET_CODE (temp) == REG
1853 && reg_nonzero_bits[REGNO (temp)] != 0
1854 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1855 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1856 && (reg_nonzero_bits[REGNO (temp)]
1857 != GET_MODE_MASK (word_mode))))
1858 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1859 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1860 (GET_CODE (temp) == REG
1861 && reg_nonzero_bits[REGNO (temp)] != 0
1862 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1863 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1864 && (reg_nonzero_bits[REGNO (temp)]
1865 != GET_MODE_MASK (word_mode)))))
1866 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1867 SET_SRC (XVECEXP (newpat, 0, 1)))
1868 && ! find_reg_note (i3, REG_UNUSED,
1869 SET_DEST (XVECEXP (newpat, 0, 0))))
1873 newi2pat = XVECEXP (newpat, 0, 0);
1874 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1875 newpat = XVECEXP (newpat, 0, 1);
1876 SUBST (SET_SRC (newpat),
1877 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1878 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1879 if (i2_code_number >= 0)
1880 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1882 if (insn_code_number >= 0)
1887 /* If we will be able to accept this, we have made a change to the
1888 destination of I3. This can invalidate a LOG_LINKS pointing
1889 to I3. No other part of combine.c makes such a transformation.
1891 The new I3 will have a destination that was previously the
1892 destination of I1 or I2 and which was used in i2 or I3. Call
1893 distribute_links to make a LOG_LINK from the next use of
1894 that destination. */
1896 PATTERN (i3) = newpat;
1897 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1899 /* I3 now uses what used to be its destination and which is
1900 now I2's destination. That means we need a LOG_LINK from
1901 I3 to I2. But we used to have one, so we still will.
1903 However, some later insn might be using I2's dest and have
1904 a LOG_LINK pointing at I3. We must remove this link.
1905 The simplest way to remove the link is to point it at I1,
1906 which we know will be a NOTE. */
1908 for (insn = NEXT_INSN (i3);
1909 insn && (this_basic_block == n_basic_blocks - 1
1910 || insn != basic_block_head[this_basic_block + 1]);
1911 insn = NEXT_INSN (insn))
1913 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1914 && reg_referenced_p (ni2dest, PATTERN (insn)))
1916 for (link = LOG_LINKS (insn); link;
1917 link = XEXP (link, 1))
1918 if (XEXP (link, 0) == i3)
1919 XEXP (link, 0) = i1;
1927 /* Similarly, check for a case where we have a PARALLEL of two independent
1928 SETs but we started with three insns. In this case, we can do the sets
1929 as two separate insns. This case occurs when some SET allows two
1930 other insns to combine, but the destination of that SET is still live. */
1932 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1933 && GET_CODE (newpat) == PARALLEL
1934 && XVECLEN (newpat, 0) == 2
1935 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1936 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1937 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1938 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1939 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1940 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1941 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1943 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1944 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1945 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1946 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1947 XVECEXP (newpat, 0, 0))
1948 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1949 XVECEXP (newpat, 0, 1)))
1951 newi2pat = XVECEXP (newpat, 0, 1);
1952 newpat = XVECEXP (newpat, 0, 0);
1954 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1955 if (i2_code_number >= 0)
1956 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1959 /* If it still isn't recognized, fail and change things back the way they
1961 if ((insn_code_number < 0
1962 /* Is the result a reasonable ASM_OPERANDS? */
1963 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1969 /* If we had to change another insn, make sure it is valid also. */
1970 if (undobuf.other_insn)
1972 rtx other_notes = REG_NOTES (undobuf.other_insn);
1973 rtx other_pat = PATTERN (undobuf.other_insn);
1974 rtx new_other_notes;
1977 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1980 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1986 PATTERN (undobuf.other_insn) = other_pat;
1988 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1989 are still valid. Then add any non-duplicate notes added by
1990 recog_for_combine. */
1991 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1993 next = XEXP (note, 1);
1995 if (REG_NOTE_KIND (note) == REG_UNUSED
1996 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1998 if (GET_CODE (XEXP (note, 0)) == REG)
1999 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2001 remove_note (undobuf.other_insn, note);
2005 for (note = new_other_notes; note; note = XEXP (note, 1))
2006 if (GET_CODE (XEXP (note, 0)) == REG)
2007 reg_n_deaths[REGNO (XEXP (note, 0))]++;
2009 distribute_notes (new_other_notes, undobuf.other_insn,
2010 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2013 /* We now know that we can do this combination. Merge the insns and
2014 update the status of registers and LOG_LINKS. */
2017 rtx i3notes, i2notes, i1notes = 0;
2018 rtx i3links, i2links, i1links = 0;
2020 int all_adjacent = (next_real_insn (i2) == i3
2021 && (i1 == 0 || next_real_insn (i1) == i2));
2023 /* Compute which registers we expect to eliminate. */
2024 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2026 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2028 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2030 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2031 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2033 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2035 /* Ensure that we do not have something that should not be shared but
2036 occurs multiple times in the new insns. Check this by first
2037 resetting all the `used' flags and then copying anything is shared. */
2039 reset_used_flags (i3notes);
2040 reset_used_flags (i2notes);
2041 reset_used_flags (i1notes);
2042 reset_used_flags (newpat);
2043 reset_used_flags (newi2pat);
2044 if (undobuf.other_insn)
2045 reset_used_flags (PATTERN (undobuf.other_insn));
2047 i3notes = copy_rtx_if_shared (i3notes);
2048 i2notes = copy_rtx_if_shared (i2notes);
2049 i1notes = copy_rtx_if_shared (i1notes);
2050 newpat = copy_rtx_if_shared (newpat);
2051 newi2pat = copy_rtx_if_shared (newi2pat);
2052 if (undobuf.other_insn)
2053 reset_used_flags (PATTERN (undobuf.other_insn));
2055 INSN_CODE (i3) = insn_code_number;
2056 PATTERN (i3) = newpat;
2057 if (undobuf.other_insn)
2058 INSN_CODE (undobuf.other_insn) = other_code_number;
2060 /* We had one special case above where I2 had more than one set and
2061 we replaced a destination of one of those sets with the destination
2062 of I3. In that case, we have to update LOG_LINKS of insns later
2063 in this basic block. Note that this (expensive) case is rare.
2065 Also, in this case, we must pretend that all REG_NOTEs for I2
2066 actually came from I3, so that REG_UNUSED notes from I2 will be
2067 properly handled. */
2069 if (i3_subst_into_i2)
2071 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2072 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2073 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2074 && ! find_reg_note (i2, REG_UNUSED,
2075 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2076 for (temp = NEXT_INSN (i2);
2077 temp && (this_basic_block == n_basic_blocks - 1
2078 || basic_block_head[this_basic_block] != temp);
2079 temp = NEXT_INSN (temp))
2080 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2081 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2082 if (XEXP (link, 0) == i2)
2083 XEXP (link, 0) = i3;
2088 while (XEXP (link, 1))
2089 link = XEXP (link, 1);
2090 XEXP (link, 1) = i2notes;
2104 INSN_CODE (i2) = i2_code_number;
2105 PATTERN (i2) = newi2pat;
2109 PUT_CODE (i2, NOTE);
2110 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2111 NOTE_SOURCE_FILE (i2) = 0;
2118 PUT_CODE (i1, NOTE);
2119 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2120 NOTE_SOURCE_FILE (i1) = 0;
2123 /* Get death notes for everything that is now used in either I3 or
2124 I2 and used to die in a previous insn. */
2126 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2128 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2130 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2132 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2135 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2138 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2141 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2144 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2145 know these are REG_UNUSED and want them to go to the desired insn,
2146 so we always pass it as i3. We have not counted the notes in
2147 reg_n_deaths yet, so we need to do so now. */
2149 if (newi2pat && new_i2_notes)
2151 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2152 if (GET_CODE (XEXP (temp, 0)) == REG)
2153 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2155 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2160 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2161 if (GET_CODE (XEXP (temp, 0)) == REG)
2162 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2164 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2167 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2168 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2169 Show an additional death due to the REG_DEAD note we make here. If
2170 we discard it in distribute_notes, we will decrement it again. */
2174 if (GET_CODE (i3dest_killed) == REG)
2175 reg_n_deaths[REGNO (i3dest_killed)]++;
2177 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2179 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2180 NULL_RTX, NULL_RTX);
2183 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2184 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2185 we passed I3 in that case, it might delete I2. */
2187 if (i2dest_in_i2src)
2189 if (GET_CODE (i2dest) == REG)
2190 reg_n_deaths[REGNO (i2dest)]++;
2192 if (newi2pat && reg_set_p (i2dest, newi2pat))
2193 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2194 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2196 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2197 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2198 NULL_RTX, NULL_RTX);
2201 if (i1dest_in_i1src)
2203 if (GET_CODE (i1dest) == REG)
2204 reg_n_deaths[REGNO (i1dest)]++;
2206 if (newi2pat && reg_set_p (i1dest, newi2pat))
2207 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2208 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2210 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2211 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2212 NULL_RTX, NULL_RTX);
2215 distribute_links (i3links);
2216 distribute_links (i2links);
2217 distribute_links (i1links);
2219 if (GET_CODE (i2dest) == REG)
2222 rtx i2_insn = 0, i2_val = 0, set;
2224 /* The insn that used to set this register doesn't exist, and
2225 this life of the register may not exist either. See if one of
2226 I3's links points to an insn that sets I2DEST. If it does,
2227 that is now the last known value for I2DEST. If we don't update
2228 this and I2 set the register to a value that depended on its old
2229 contents, we will get confused. If this insn is used, thing
2230 will be set correctly in combine_instructions. */
2232 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2233 if ((set = single_set (XEXP (link, 0))) != 0
2234 && rtx_equal_p (i2dest, SET_DEST (set)))
2235 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2237 record_value_for_reg (i2dest, i2_insn, i2_val);
2239 /* If the reg formerly set in I2 died only once and that was in I3,
2240 zero its use count so it won't make `reload' do any work. */
2241 if (! added_sets_2 && newi2pat == 0)
2243 regno = REGNO (i2dest);
2244 reg_n_sets[regno]--;
2245 if (reg_n_sets[regno] == 0
2246 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2247 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2248 reg_n_refs[regno] = 0;
2252 if (i1 && GET_CODE (i1dest) == REG)
2255 rtx i1_insn = 0, i1_val = 0, set;
2257 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2258 if ((set = single_set (XEXP (link, 0))) != 0
2259 && rtx_equal_p (i1dest, SET_DEST (set)))
2260 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2262 record_value_for_reg (i1dest, i1_insn, i1_val);
2264 regno = REGNO (i1dest);
2267 reg_n_sets[regno]--;
2268 if (reg_n_sets[regno] == 0
2269 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2270 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2271 reg_n_refs[regno] = 0;
2275 /* Update reg_nonzero_bits et al for any changes that may have been made
2278 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2280 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2282 /* If I3 is now an unconditional jump, ensure that it has a
2283 BARRIER following it since it may have initially been a
2284 conditional jump. It may also be the last nonnote insn. */
2286 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2287 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2288 || GET_CODE (temp) != BARRIER))
2289 emit_barrier_after (i3);
2292 combine_successes++;
2294 return newi2pat ? i2 : i3;
2297 /* Undo all the modifications recorded in undobuf. */
2303 if (undobuf.num_undo > MAX_UNDO)
2304 undobuf.num_undo = MAX_UNDO;
2305 for (i = undobuf.num_undo - 1; i >= 0; i--)
2307 if (undobuf.undo[i].is_int)
2308 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2310 *undobuf.undo[i].where.r = undobuf.undo[i].old_contents.r;
2314 obfree (undobuf.storage);
2315 undobuf.num_undo = 0;
2318 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2319 where we have an arithmetic expression and return that point. LOC will
2322 try_combine will call this function to see if an insn can be split into
2326 find_split_point (loc, insn)
2331 enum rtx_code code = GET_CODE (x);
2333 int len = 0, pos, unsignedp;
2336 /* First special-case some codes. */
2340 #ifdef INSN_SCHEDULING
2341 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2343 if (GET_CODE (SUBREG_REG (x)) == MEM)
2346 return find_split_point (&SUBREG_REG (x), insn);
2350 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2351 using LO_SUM and HIGH. */
2352 if (GET_CODE (XEXP (x, 0)) == CONST
2353 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2356 gen_rtx_combine (LO_SUM, Pmode,
2357 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2359 return &XEXP (XEXP (x, 0), 0);
2363 /* If we have a PLUS whose second operand is a constant and the
2364 address is not valid, perhaps will can split it up using
2365 the machine-specific way to split large constants. We use
2366 the first psuedo-reg (one of the virtual regs) as a placeholder;
2367 it will not remain in the result. */
2368 if (GET_CODE (XEXP (x, 0)) == PLUS
2369 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2370 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2372 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2373 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2376 /* This should have produced two insns, each of which sets our
2377 placeholder. If the source of the second is a valid address,
2378 we can make put both sources together and make a split point
2381 if (seq && XVECLEN (seq, 0) == 2
2382 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2383 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2384 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2385 && ! reg_mentioned_p (reg,
2386 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2387 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2388 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2389 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2390 && memory_address_p (GET_MODE (x),
2391 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2393 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2394 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2396 /* Replace the placeholder in SRC2 with SRC1. If we can
2397 find where in SRC2 it was placed, that can become our
2398 split point and we can replace this address with SRC2.
2399 Just try two obvious places. */
2401 src2 = replace_rtx (src2, reg, src1);
2403 if (XEXP (src2, 0) == src1)
2404 split = &XEXP (src2, 0);
2405 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2406 && XEXP (XEXP (src2, 0), 0) == src1)
2407 split = &XEXP (XEXP (src2, 0), 0);
2411 SUBST (XEXP (x, 0), src2);
2416 /* If that didn't work, perhaps the first operand is complex and
2417 needs to be computed separately, so make a split point there.
2418 This will occur on machines that just support REG + CONST
2419 and have a constant moved through some previous computation. */
2421 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2422 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2423 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2425 return &XEXP (XEXP (x, 0), 0);
2431 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2432 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2433 we need to put the operand into a register. So split at that
2436 if (SET_DEST (x) == cc0_rtx
2437 && GET_CODE (SET_SRC (x)) != COMPARE
2438 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2439 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2440 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2441 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2442 return &SET_SRC (x);
2445 /* See if we can split SET_SRC as it stands. */
2446 split = find_split_point (&SET_SRC (x), insn);
2447 if (split && split != &SET_SRC (x))
2450 /* See if this is a bitfield assignment with everything constant. If
2451 so, this is an IOR of an AND, so split it into that. */
2452 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2453 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2454 <= HOST_BITS_PER_WIDE_INT)
2455 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2456 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2457 && GET_CODE (SET_SRC (x)) == CONST_INT
2458 && ((INTVAL (XEXP (SET_DEST (x), 1))
2459 + INTVAL (XEXP (SET_DEST (x), 2)))
2460 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2461 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2463 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2464 int len = INTVAL (XEXP (SET_DEST (x), 1));
2465 int src = INTVAL (SET_SRC (x));
2466 rtx dest = XEXP (SET_DEST (x), 0);
2467 enum machine_mode mode = GET_MODE (dest);
2468 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2471 pos = GET_MODE_BITSIZE (mode) - len - pos;
2476 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2479 gen_binary (IOR, mode,
2480 gen_binary (AND, mode, dest,
2481 GEN_INT (~ (mask << pos)
2482 & GET_MODE_MASK (mode))),
2483 GEN_INT (src << pos)));
2485 SUBST (SET_DEST (x), dest);
2487 split = find_split_point (&SET_SRC (x), insn);
2488 if (split && split != &SET_SRC (x))
2492 /* Otherwise, see if this is an operation that we can split into two.
2493 If so, try to split that. */
2494 code = GET_CODE (SET_SRC (x));
2499 /* If we are AND'ing with a large constant that is only a single
2500 bit and the result is only being used in a context where we
2501 need to know if it is zero or non-zero, replace it with a bit
2502 extraction. This will avoid the large constant, which might
2503 have taken more than one insn to make. If the constant were
2504 not a valid argument to the AND but took only one insn to make,
2505 this is no worse, but if it took more than one insn, it will
2508 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2509 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2510 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2511 && GET_CODE (SET_DEST (x)) == REG
2512 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2513 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2514 && XEXP (*split, 0) == SET_DEST (x)
2515 && XEXP (*split, 1) == const0_rtx)
2518 make_extraction (GET_MODE (SET_DEST (x)),
2519 XEXP (SET_SRC (x), 0),
2520 pos, NULL_RTX, 1, 1, 0, 0));
2521 return find_split_point (loc, insn);
2526 inner = XEXP (SET_SRC (x), 0);
2528 len = GET_MODE_BITSIZE (GET_MODE (inner));
2534 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2535 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2537 inner = XEXP (SET_SRC (x), 0);
2538 len = INTVAL (XEXP (SET_SRC (x), 1));
2539 pos = INTVAL (XEXP (SET_SRC (x), 2));
2542 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2544 unsignedp = (code == ZERO_EXTRACT);
2549 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2551 enum machine_mode mode = GET_MODE (SET_SRC (x));
2553 /* For unsigned, we have a choice of a shift followed by an
2554 AND or two shifts. Use two shifts for field sizes where the
2555 constant might be too large. We assume here that we can
2556 always at least get 8-bit constants in an AND insn, which is
2557 true for every current RISC. */
2559 if (unsignedp && len <= 8)
2564 gen_rtx_combine (LSHIFTRT, mode,
2565 gen_lowpart_for_combine (mode, inner),
2567 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2569 split = find_split_point (&SET_SRC (x), insn);
2570 if (split && split != &SET_SRC (x))
2577 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2578 gen_rtx_combine (ASHIFT, mode,
2579 gen_lowpart_for_combine (mode, inner),
2580 GEN_INT (GET_MODE_BITSIZE (mode)
2582 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2584 split = find_split_point (&SET_SRC (x), insn);
2585 if (split && split != &SET_SRC (x))
2590 /* See if this is a simple operation with a constant as the second
2591 operand. It might be that this constant is out of range and hence
2592 could be used as a split point. */
2593 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2594 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2595 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2596 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2597 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2598 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2599 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2601 return &XEXP (SET_SRC (x), 1);
2603 /* Finally, see if this is a simple operation with its first operand
2604 not in a register. The operation might require this operand in a
2605 register, so return it as a split point. We can always do this
2606 because if the first operand were another operation, we would have
2607 already found it as a split point. */
2608 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2609 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2610 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2611 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2612 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2613 return &XEXP (SET_SRC (x), 0);
2619 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2620 it is better to write this as (not (ior A B)) so we can split it.
2621 Similarly for IOR. */
2622 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2625 gen_rtx_combine (NOT, GET_MODE (x),
2626 gen_rtx_combine (code == IOR ? AND : IOR,
2628 XEXP (XEXP (x, 0), 0),
2629 XEXP (XEXP (x, 1), 0))));
2630 return find_split_point (loc, insn);
2633 /* Many RISC machines have a large set of logical insns. If the
2634 second operand is a NOT, put it first so we will try to split the
2635 other operand first. */
2636 if (GET_CODE (XEXP (x, 1)) == NOT)
2638 rtx tem = XEXP (x, 0);
2639 SUBST (XEXP (x, 0), XEXP (x, 1));
2640 SUBST (XEXP (x, 1), tem);
2645 /* Otherwise, select our actions depending on our rtx class. */
2646 switch (GET_RTX_CLASS (code))
2648 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2650 split = find_split_point (&XEXP (x, 2), insn);
2653 /* ... fall through ... */
2657 split = find_split_point (&XEXP (x, 1), insn);
2660 /* ... fall through ... */
2662 /* Some machines have (and (shift ...) ...) insns. If X is not
2663 an AND, but XEXP (X, 0) is, use it as our split point. */
2664 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2665 return &XEXP (x, 0);
2667 split = find_split_point (&XEXP (x, 0), insn);
2673 /* Otherwise, we don't have a split point. */
2677 /* Throughout X, replace FROM with TO, and return the result.
2678 The result is TO if X is FROM;
2679 otherwise the result is X, but its contents may have been modified.
2680 If they were modified, a record was made in undobuf so that
2681 undo_all will (among other things) return X to its original state.
2683 If the number of changes necessary is too much to record to undo,
2684 the excess changes are not made, so the result is invalid.
2685 The changes already made can still be undone.
2686 undobuf.num_undo is incremented for such changes, so by testing that
2687 the caller can tell whether the result is valid.
2689 `n_occurrences' is incremented each time FROM is replaced.
2691 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2693 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2694 by copying if `n_occurrences' is non-zero. */
2697 subst (x, from, to, in_dest, unique_copy)
2698 register rtx x, from, to;
2703 register int len, i;
2704 register enum rtx_code code = GET_CODE (x), orig_code = code;
2706 enum machine_mode mode = GET_MODE (x);
2707 enum machine_mode op0_mode = VOIDmode;
2712 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2713 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2714 If it is 0, that cannot be done. We can now do this for any MEM
2715 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2716 If not for that, MEM's would very rarely be safe. */
2718 /* Reject MODEs bigger than a word, because we might not be able
2719 to reference a two-register group starting with an arbitrary register
2720 (and currently gen_lowpart might crash for a SUBREG). */
2722 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2723 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2725 /* Two expressions are equal if they are identical copies of a shared
2726 RTX or if they are both registers with the same register number
2729 #define COMBINE_RTX_EQUAL_P(X,Y) \
2731 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2732 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2734 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2737 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2740 /* If X and FROM are the same register but different modes, they will
2741 not have been seen as equal above. However, flow.c will make a
2742 LOG_LINKS entry for that case. If we do nothing, we will try to
2743 rerecognize our original insn and, when it succeeds, we will
2744 delete the feeding insn, which is incorrect.
2746 So force this insn not to match in this (rare) case. */
2747 if (! in_dest && code == REG && GET_CODE (from) == REG
2748 && REGNO (x) == REGNO (from))
2749 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2751 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2752 of which may contain things that can be combined. */
2753 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2756 /* It is possible to have a subexpression appear twice in the insn.
2757 Suppose that FROM is a register that appears within TO.
2758 Then, after that subexpression has been scanned once by `subst',
2759 the second time it is scanned, TO may be found. If we were
2760 to scan TO here, we would find FROM within it and create a
2761 self-referent rtl structure which is completely wrong. */
2762 if (COMBINE_RTX_EQUAL_P (x, to))
2765 len = GET_RTX_LENGTH (code);
2766 fmt = GET_RTX_FORMAT (code);
2768 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2769 set up to skip this common case. All other cases where we want to
2770 suppress replacing something inside a SET_SRC are handled via the
2773 && (GET_CODE (SET_DEST (x)) == REG
2774 || GET_CODE (SET_DEST (x)) == CC0
2775 || GET_CODE (SET_DEST (x)) == PC))
2778 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2780 op0_mode = GET_MODE (XEXP (x, 0));
2782 for (i = 0; i < len; i++)
2787 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2790 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2792 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2797 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2799 /* If this substitution failed, this whole thing fails. */
2800 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2804 SUBST (XVECEXP (x, i, j), new);
2807 else if (fmt[i] == 'e')
2811 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2813 /* In general, don't install a subreg involving two modes not
2814 tieable. It can worsen register allocation, and can even
2815 make invalid reload insns, since the reg inside may need to
2816 be copied from in the outside mode, and that may be invalid
2817 if it is an fp reg copied in integer mode.
2819 We allow two exceptions to this: It is valid if it is inside
2820 another SUBREG and the mode of that SUBREG and the mode of
2821 the inside of TO is tieable and it is valid if X is a SET
2822 that copies FROM to CC0. */
2823 if (GET_CODE (to) == SUBREG
2824 && ! MODES_TIEABLE_P (GET_MODE (to),
2825 GET_MODE (SUBREG_REG (to)))
2826 && ! (code == SUBREG
2827 && MODES_TIEABLE_P (mode, GET_MODE (SUBREG_REG (to))))
2829 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2832 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2834 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2838 /* If we are in a SET_DEST, suppress most cases unless we
2839 have gone inside a MEM, in which case we want to
2840 simplify the address. We assume here that things that
2841 are actually part of the destination have their inner
2842 parts in the first expression. This is true for SUBREG,
2843 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2844 things aside from REG and MEM that should appear in a
2846 new = subst (XEXP (x, i), from, to,
2848 && (code == SUBREG || code == STRICT_LOW_PART
2849 || code == ZERO_EXTRACT))
2851 && i == 0), unique_copy);
2853 /* If we found that we will have to reject this combination,
2854 indicate that by returning the CLOBBER ourselves, rather than
2855 an expression containing it. This will speed things up as
2856 well as prevent accidents where two CLOBBERs are considered
2857 to be equal, thus producing an incorrect simplification. */
2859 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2862 SUBST (XEXP (x, i), new);
2866 /* We come back to here if we have replaced the expression with one of
2867 a different code and it is likely that further simplification will be
2872 /* If we have restarted more than 4 times, we are probably looping, so
2874 if (++n_restarts > 4)
2877 /* If we are restarting at all, it means that we no longer know the
2878 original mode of operand 0 (since we have probably changed the
2882 op0_mode = VOIDmode;
2884 code = GET_CODE (x);
2886 /* If this is a commutative operation, put a constant last and a complex
2887 expression first. We don't need to do this for comparisons here. */
2888 if (GET_RTX_CLASS (code) == 'c'
2889 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2890 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2891 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2892 || (GET_CODE (XEXP (x, 0)) == SUBREG
2893 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2894 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2897 SUBST (XEXP (x, 0), XEXP (x, 1));
2898 SUBST (XEXP (x, 1), temp);
2901 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2902 sign extension of a PLUS with a constant, reverse the order of the sign
2903 extension and the addition. Note that this not the same as the original
2904 code, but overflow is undefined for signed values. Also note that the
2905 PLUS will have been partially moved "inside" the sign-extension, so that
2906 the first operand of X will really look like:
2907 (ashiftrt (plus (ashift A C4) C5) C4).
2909 (plus (ashiftrt (ashift A C4) C2) C4)
2910 and replace the first operand of X with that expression. Later parts
2911 of this function may simplify the expression further.
2913 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2914 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2915 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2917 We do this to simplify address expressions. */
2919 if ((code == PLUS || code == MINUS || code == MULT)
2920 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2921 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2922 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2923 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2924 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2925 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2926 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2927 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2928 XEXP (XEXP (XEXP (x, 0), 0), 1),
2929 XEXP (XEXP (x, 0), 1))) != 0)
2932 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2933 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2934 INTVAL (XEXP (XEXP (x, 0), 1)));
2936 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2937 INTVAL (XEXP (XEXP (x, 0), 1)));
2939 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2942 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2943 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2944 things. Don't deal with operations that change modes here. */
2946 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2947 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2949 /* Don't do this by using SUBST inside X since we might be messing
2950 up a shared expression. */
2951 rtx cond = XEXP (XEXP (x, 0), 0);
2952 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2954 pc_rtx, pc_rtx, 0, 0);
2955 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2957 pc_rtx, pc_rtx, 0, 0);
2960 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2964 else if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2965 && GET_CODE (XEXP (x, 1)) == IF_THEN_ELSE)
2967 /* Don't do this by using SUBST inside X since we might be messing
2968 up a shared expression. */
2969 rtx cond = XEXP (XEXP (x, 1), 0);
2970 rtx t_arm = subst (gen_binary (code, mode, XEXP (x, 0),
2971 XEXP (XEXP (x, 1), 1)),
2972 pc_rtx, pc_rtx, 0, 0);
2973 rtx f_arm = subst (gen_binary (code, mode, XEXP (x, 0),
2974 XEXP (XEXP (x, 1), 2)),
2975 pc_rtx, pc_rtx, 0, 0);
2977 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2981 else if (GET_RTX_CLASS (code) == '1'
2982 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2983 && GET_MODE (XEXP (x, 0)) == mode)
2985 rtx cond = XEXP (XEXP (x, 0), 0);
2986 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2987 pc_rtx, pc_rtx, 0, 0);
2988 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2989 pc_rtx, pc_rtx, 0, 0);
2991 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2995 /* Try to fold this expression in case we have constants that weren't
2998 switch (GET_RTX_CLASS (code))
3001 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3004 temp = simplify_relational_operation (code, op0_mode,
3005 XEXP (x, 0), XEXP (x, 1));
3006 #ifdef FLOAT_STORE_FLAG_VALUE
3007 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3008 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3009 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3014 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3018 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3019 XEXP (x, 1), XEXP (x, 2));
3024 x = temp, code = GET_CODE (temp);
3026 /* First see if we can apply the inverse distributive law. */
3027 if (code == PLUS || code == MINUS
3028 || code == AND || code == IOR || code == XOR)
3030 x = apply_distributive_law (x);
3031 code = GET_CODE (x);
3034 /* If CODE is an associative operation not otherwise handled, see if we
3035 can associate some operands. This can win if they are constants or
3036 if they are logically related (i.e. (a & b) & a. */
3037 if ((code == PLUS || code == MINUS
3038 || code == MULT || code == AND || code == IOR || code == XOR
3039 || code == DIV || code == UDIV
3040 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3041 && INTEGRAL_MODE_P (mode))
3043 if (GET_CODE (XEXP (x, 0)) == code)
3045 rtx other = XEXP (XEXP (x, 0), 0);
3046 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3047 rtx inner_op1 = XEXP (x, 1);
3050 /* Make sure we pass the constant operand if any as the second
3051 one if this is a commutative operation. */
3052 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3054 rtx tem = inner_op0;
3055 inner_op0 = inner_op1;
3058 inner = simplify_binary_operation (code == MINUS ? PLUS
3059 : code == DIV ? MULT
3060 : code == UDIV ? MULT
3062 mode, inner_op0, inner_op1);
3064 /* For commutative operations, try the other pair if that one
3066 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3068 other = XEXP (XEXP (x, 0), 1);
3069 inner = simplify_binary_operation (code, mode,
3070 XEXP (XEXP (x, 0), 0),
3076 x = gen_binary (code, mode, other, inner);
3083 /* A little bit of algebraic simplification here. */
3087 /* Ensure that our address has any ASHIFTs converted to MULT in case
3088 address-recognizing predicates are called later. */
3089 temp = make_compound_operation (XEXP (x, 0), MEM);
3090 SUBST (XEXP (x, 0), temp);
3094 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3095 is paradoxical. If we can't do that safely, then it becomes
3096 something nonsensical so that this combination won't take place. */
3098 if (GET_CODE (SUBREG_REG (x)) == MEM
3099 && (GET_MODE_SIZE (mode)
3100 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3102 rtx inner = SUBREG_REG (x);
3103 int endian_offset = 0;
3104 /* Don't change the mode of the MEM
3105 if that would change the meaning of the address. */
3106 if (MEM_VOLATILE_P (SUBREG_REG (x))
3107 || mode_dependent_address_p (XEXP (inner, 0)))
3108 return gen_rtx (CLOBBER, mode, const0_rtx);
3110 #if BYTES_BIG_ENDIAN
3111 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3112 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3113 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3114 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
3116 /* Note if the plus_constant doesn't make a valid address
3117 then this combination won't be accepted. */
3118 x = gen_rtx (MEM, mode,
3119 plus_constant (XEXP (inner, 0),
3120 (SUBREG_WORD (x) * UNITS_PER_WORD
3122 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3123 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3124 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3128 /* If we are in a SET_DEST, these other cases can't apply. */
3132 /* Changing mode twice with SUBREG => just change it once,
3133 or not at all if changing back to starting mode. */
3134 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3136 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3137 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3138 return SUBREG_REG (SUBREG_REG (x));
3140 SUBST_INT (SUBREG_WORD (x),
3141 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3142 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3145 /* SUBREG of a hard register => just change the register number
3146 and/or mode. If the hard register is not valid in that mode,
3147 suppress this combination. If the hard register is the stack,
3148 frame, or argument pointer, leave this as a SUBREG. */
3150 if (GET_CODE (SUBREG_REG (x)) == REG
3151 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3152 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3153 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3154 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3156 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3157 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3159 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3161 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3163 return gen_rtx (REG, mode,
3164 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3166 return gen_rtx (CLOBBER, mode, const0_rtx);
3169 /* For a constant, try to pick up the part we want. Handle a full
3170 word and low-order part. Only do this if we are narrowing
3171 the constant; if it is being widened, we have no idea what
3172 the extra bits will have been set to. */
3174 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3175 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3176 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3177 && GET_MODE_CLASS (mode) == MODE_INT)
3179 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3185 /* If we want a subreg of a constant, at offset 0,
3186 take the low bits. On a little-endian machine, that's
3187 always valid. On a big-endian machine, it's valid
3188 only if the constant's mode fits in one word. */
3189 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3190 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode)
3191 #if WORDS_BIG_ENDIAN
3192 && GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD
3195 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3197 /* If we are narrowing an integral object, we need to see if we can
3198 simplify the expression for the object knowing that we only need the
3201 if (GET_MODE_CLASS (mode) == MODE_INT
3202 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
3203 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
3204 && subreg_lowpart_p (x))
3205 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_MASK (mode),
3210 /* (not (plus X -1)) can become (neg X). */
3211 if (GET_CODE (XEXP (x, 0)) == PLUS
3212 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3214 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3218 /* Similarly, (not (neg X)) is (plus X -1). */
3219 if (GET_CODE (XEXP (x, 0)) == NEG)
3221 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3225 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3226 if (GET_CODE (XEXP (x, 0)) == XOR
3227 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3228 && (temp = simplify_unary_operation (NOT, mode,
3229 XEXP (XEXP (x, 0), 1),
3232 SUBST (XEXP (XEXP (x, 0), 1), temp);
3236 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3237 other than 1, but that is not valid. We could do a similar
3238 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3239 but this doesn't seem common enough to bother with. */
3240 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3241 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3243 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3244 XEXP (XEXP (x, 0), 1));
3248 if (GET_CODE (XEXP (x, 0)) == SUBREG
3249 && subreg_lowpart_p (XEXP (x, 0))
3250 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3251 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3252 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3253 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3255 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3257 x = gen_rtx (ROTATE, inner_mode,
3258 gen_unary (NOT, inner_mode, const1_rtx),
3259 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3260 x = gen_lowpart_for_combine (mode, x);
3264 #if STORE_FLAG_VALUE == -1
3265 /* (not (comparison foo bar)) can be done by reversing the comparison
3267 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3268 && reversible_comparison_p (XEXP (x, 0)))
3269 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3270 mode, XEXP (XEXP (x, 0), 0),
3271 XEXP (XEXP (x, 0), 1));
3273 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3274 is (lt foo (const_int 0)), so we can perform the above
3277 if (XEXP (x, 1) == const1_rtx
3278 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3279 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3280 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3281 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3284 /* Apply De Morgan's laws to reduce number of patterns for machines
3285 with negating logical insns (and-not, nand, etc.). If result has
3286 only one NOT, put it first, since that is how the patterns are
3289 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3291 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3293 if (GET_CODE (in1) == NOT)
3294 in1 = XEXP (in1, 0);
3296 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3298 if (GET_CODE (in2) == NOT)
3299 in2 = XEXP (in2, 0);
3300 else if (GET_CODE (in2) == CONST_INT
3301 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3302 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3304 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3306 if (GET_CODE (in2) == NOT)
3309 in2 = in1; in1 = tem;
3312 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3319 /* (neg (plus X 1)) can become (not X). */
3320 if (GET_CODE (XEXP (x, 0)) == PLUS
3321 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3323 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3327 /* Similarly, (neg (not X)) is (plus X 1). */
3328 if (GET_CODE (XEXP (x, 0)) == NOT)
3330 x = plus_constant (XEXP (XEXP (x, 0), 0), 1);
3334 /* (neg (minus X Y)) can become (minus Y X). */
3335 if (GET_CODE (XEXP (x, 0)) == MINUS
3336 && (! FLOAT_MODE_P (mode)
3337 /* x-y != -(y-x) with IEEE floating point. */
3338 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3341 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3342 XEXP (XEXP (x, 0), 0));
3346 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3347 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3348 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3350 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3354 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3355 if we can then eliminate the NEG (e.g.,
3356 if the operand is a constant). */
3358 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3360 temp = simplify_unary_operation (NEG, mode,
3361 XEXP (XEXP (x, 0), 0), mode);
3364 SUBST (XEXP (XEXP (x, 0), 0), temp);
3369 temp = expand_compound_operation (XEXP (x, 0));
3371 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3372 replaced by (lshiftrt X C). This will convert
3373 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3375 if (GET_CODE (temp) == ASHIFTRT
3376 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3377 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3379 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3380 INTVAL (XEXP (temp, 1)));
3384 /* If X has only a single bit that might be nonzero, say, bit I, convert
3385 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3386 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3387 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3388 or a SUBREG of one since we'd be making the expression more
3389 complex if it was just a register. */
3391 if (GET_CODE (temp) != REG
3392 && ! (GET_CODE (temp) == SUBREG
3393 && GET_CODE (SUBREG_REG (temp)) == REG)
3394 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3396 rtx temp1 = simplify_shift_const
3397 (NULL_RTX, ASHIFTRT, mode,
3398 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3399 GET_MODE_BITSIZE (mode) - 1 - i),
3400 GET_MODE_BITSIZE (mode) - 1 - i);
3402 /* If all we did was surround TEMP with the two shifts, we
3403 haven't improved anything, so don't use it. Otherwise,
3404 we are better off with TEMP1. */
3405 if (GET_CODE (temp1) != ASHIFTRT
3406 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3407 || XEXP (XEXP (temp1, 0), 0) != temp)
3415 case FLOAT_TRUNCATE:
3416 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3417 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3418 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3419 return XEXP (XEXP (x, 0), 0);
3424 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3425 using cc0, in which case we want to leave it as a COMPARE
3426 so we can distinguish it from a register-register-copy. */
3427 if (XEXP (x, 1) == const0_rtx)
3430 /* In IEEE floating point, x-0 is not the same as x. */
3431 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3432 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3434 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3440 /* (const (const X)) can become (const X). Do it this way rather than
3441 returning the inner CONST since CONST can be shared with a
3443 if (GET_CODE (XEXP (x, 0)) == CONST)
3444 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3449 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3450 can add in an offset. find_split_point will split this address up
3451 again if it doesn't match. */
3452 if (GET_CODE (XEXP (x, 0)) == HIGH
3453 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3459 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3460 outermost. That's because that's the way indexed addresses are
3461 supposed to appear. This code used to check many more cases, but
3462 they are now checked elsewhere. */
3463 if (GET_CODE (XEXP (x, 0)) == PLUS
3464 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3465 return gen_binary (PLUS, mode,
3466 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3468 XEXP (XEXP (x, 0), 1));
3470 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3471 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3472 bit-field and can be replaced by either a sign_extend or a
3473 sign_extract. The `and' may be a zero_extend. */
3474 if (GET_CODE (XEXP (x, 0)) == XOR
3475 && GET_CODE (XEXP (x, 1)) == CONST_INT
3476 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3477 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3478 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3479 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3480 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3481 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3482 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3483 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3484 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3485 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3488 x = simplify_shift_const
3489 (NULL_RTX, ASHIFTRT, mode,
3490 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3491 XEXP (XEXP (XEXP (x, 0), 0), 0),
3492 GET_MODE_BITSIZE (mode) - (i + 1)),
3493 GET_MODE_BITSIZE (mode) - (i + 1));
3497 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3498 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3499 is 1. This produces better code than the alternative immediately
3501 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3502 && reversible_comparison_p (XEXP (x, 0))
3503 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3504 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3506 x = gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3507 mode, XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1));
3508 x = gen_unary (NEG, mode, x);
3512 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3513 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3514 the bitsize of the mode - 1. This allows simplification of
3515 "a = (b & 8) == 0;" */
3516 if (XEXP (x, 1) == constm1_rtx
3517 && GET_CODE (XEXP (x, 0)) != REG
3518 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3519 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3520 && nonzero_bits (XEXP (x, 0), mode) == 1)
3522 x = simplify_shift_const
3523 (NULL_RTX, ASHIFTRT, mode,
3524 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3525 gen_rtx_combine (XOR, mode,
3526 XEXP (x, 0), const1_rtx),
3527 GET_MODE_BITSIZE (mode) - 1),
3528 GET_MODE_BITSIZE (mode) - 1);
3532 /* If we are adding two things that have no bits in common, convert
3533 the addition into an IOR. This will often be further simplified,
3534 for example in cases like ((a & 1) + (a & 2)), which can
3537 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3538 && (nonzero_bits (XEXP (x, 0), mode)
3539 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3541 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3547 #if STORE_FLAG_VALUE == 1
3548 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3550 if (XEXP (x, 0) == const1_rtx
3551 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3552 && reversible_comparison_p (XEXP (x, 1)))
3553 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3554 mode, XEXP (XEXP (x, 1), 0),
3555 XEXP (XEXP (x, 1), 1));
3558 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3559 (and <foo> (const_int pow2-1)) */
3560 if (GET_CODE (XEXP (x, 1)) == AND
3561 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3562 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3563 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3565 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3566 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3570 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3572 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3574 x = gen_binary (MINUS, mode,
3575 gen_binary (MINUS, mode, XEXP (x, 0),
3576 XEXP (XEXP (x, 1), 0)),
3577 XEXP (XEXP (x, 1), 1));
3583 /* If we have (mult (plus A B) C), apply the distributive law and then
3584 the inverse distributive law to see if things simplify. This
3585 occurs mostly in addresses, often when unrolling loops. */
3587 if (GET_CODE (XEXP (x, 0)) == PLUS)
3589 x = apply_distributive_law
3590 (gen_binary (PLUS, mode,
3591 gen_binary (MULT, mode,
3592 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3593 gen_binary (MULT, mode,
3594 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3596 if (GET_CODE (x) != MULT)
3600 /* If this is multiplication by a power of two and its first operand is
3601 a shift, treat the multiply as a shift to allow the shifts to
3602 possibly combine. */
3603 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3604 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3605 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3606 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3607 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3608 || GET_CODE (XEXP (x, 0)) == ROTATE
3609 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3611 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3615 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3616 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3617 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3618 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3619 XEXP (XEXP (x, 0), 1));
3623 /* If this is a divide by a power of two, treat it as a shift if
3624 its first operand is a shift. */
3625 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3626 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3627 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3628 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3629 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3630 || GET_CODE (XEXP (x, 0)) == ROTATE
3631 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3633 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3639 case GT: case GTU: case GE: case GEU:
3640 case LT: case LTU: case LE: case LEU:
3641 /* If the first operand is a condition code, we can't do anything
3643 if (GET_CODE (XEXP (x, 0)) == COMPARE
3644 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3646 && XEXP (x, 0) != cc0_rtx
3650 rtx op0 = XEXP (x, 0);
3651 rtx op1 = XEXP (x, 1);
3652 enum rtx_code new_code;
3654 if (GET_CODE (op0) == COMPARE)
3655 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3657 /* Simplify our comparison, if possible. */
3658 new_code = simplify_comparison (code, &op0, &op1);
3660 #if STORE_FLAG_VALUE == 1
3661 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3662 if only the low-order bit is possibly nonzero in X (such as when
3663 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3664 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3665 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3668 Remove any ZERO_EXTRACT we made when thinking this was a
3669 comparison. It may now be simpler to use, e.g., an AND. If a
3670 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3671 the call to make_compound_operation in the SET case. */
3673 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3674 && op1 == const0_rtx
3675 && nonzero_bits (op0, mode) == 1)
3676 return gen_lowpart_for_combine (mode,
3677 expand_compound_operation (op0));
3679 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3680 && op1 == const0_rtx
3681 && (num_sign_bit_copies (op0, mode)
3682 == GET_MODE_BITSIZE (mode)))
3684 op0 = expand_compound_operation (op0);
3685 x = gen_unary (NEG, mode, gen_lowpart_for_combine (mode, op0));
3689 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3690 && op1 == const0_rtx
3691 && nonzero_bits (op0, mode) == 1)
3693 op0 = expand_compound_operation (op0);
3694 x = gen_binary (XOR, mode,
3695 gen_lowpart_for_combine (mode, op0),
3700 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3701 && op1 == const0_rtx
3702 && (num_sign_bit_copies (op0, mode)
3703 == GET_MODE_BITSIZE (mode)))
3705 op0 = expand_compound_operation (op0);
3706 x = plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3711 #if STORE_FLAG_VALUE == -1
3712 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3714 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3715 && op1 == const0_rtx
3716 && (num_sign_bit_copies (op0, mode)
3717 == GET_MODE_BITSIZE (mode)))
3718 return gen_lowpart_for_combine (mode,
3719 expand_compound_operation (op0));
3721 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3722 && op1 == const0_rtx
3723 && nonzero_bits (op0, mode) == 1)
3725 op0 = expand_compound_operation (op0);
3726 x = gen_unary (NEG, mode, gen_lowpart_for_combine (mode, op0));
3730 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3731 && op1 == const0_rtx
3732 && (num_sign_bit_copies (op0, mode)
3733 == GET_MODE_BITSIZE (mode)))
3735 op0 = expand_compound_operation (op0);
3736 x = gen_unary (NOT, mode, gen_lowpart_for_combine (mode, op0));
3740 /* If X is 0/1, (eq X 0) is X-1. */
3741 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3742 && op1 == const0_rtx
3743 && nonzero_bits (op0, mode) == 1)
3745 op0 = expand_compound_operation (op0);
3746 x = plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3751 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3752 one bit that might be nonzero, we can convert (ne x 0) to
3753 (ashift x c) where C puts the bit in the sign bit. Remove any
3754 AND with STORE_FLAG_VALUE when we are done, since we are only
3755 going to test the sign bit. */
3756 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3757 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3758 && (STORE_FLAG_VALUE
3759 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3760 && op1 == const0_rtx
3761 && mode == GET_MODE (op0)
3762 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3764 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3765 expand_compound_operation (op0),
3766 GET_MODE_BITSIZE (mode) - 1 - i);
3767 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3773 /* If the code changed, return a whole new comparison. */
3774 if (new_code != code)
3775 return gen_rtx_combine (new_code, mode, op0, op1);
3777 /* Otherwise, keep this operation, but maybe change its operands.
3778 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3779 SUBST (XEXP (x, 0), op0);
3780 SUBST (XEXP (x, 1), op1);
3785 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3786 used in it is being compared against certain values. Get the
3787 true and false comparisons and see if that says anything about the
3788 value of each arm. */
3790 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3791 && reversible_comparison_p (XEXP (x, 0))
3792 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3795 rtx from = XEXP (XEXP (x, 0), 0);
3796 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3797 enum rtx_code false_code = reverse_condition (true_code);
3798 rtx true_val = XEXP (XEXP (x, 0), 1);
3799 rtx false_val = true_val;
3800 rtx true_arm = XEXP (x, 1);
3801 rtx false_arm = XEXP (x, 2);
3804 /* If FALSE_CODE is EQ, swap the codes and arms. */
3806 if (false_code == EQ)
3808 swapped = 1, true_code = EQ, false_code = NE;
3809 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3812 /* If we are comparing against zero and the expression being tested
3813 has only a single bit that might be nonzero, that is its value
3814 when it is not equal to zero. Similarly if it is known to be
3817 if (true_code == EQ && true_val == const0_rtx
3818 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3819 false_code = EQ, false_val = GEN_INT (nzb);
3820 else if (true_code == EQ && true_val == const0_rtx
3821 && (num_sign_bit_copies (from, GET_MODE (from))
3822 == GET_MODE_BITSIZE (GET_MODE (from))))
3823 false_code = EQ, false_val = constm1_rtx;
3825 /* Now simplify an arm if we know the value of the register
3826 in the branch and it is used in the arm. Be carefull due to
3827 the potential of locally-shared RTL. */
3829 if (reg_mentioned_p (from, true_arm))
3830 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3832 pc_rtx, pc_rtx, 0, 0);
3833 if (reg_mentioned_p (from, false_arm))
3834 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3836 pc_rtx, pc_rtx, 0, 0);
3838 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3839 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3842 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3843 reversed, do so to avoid needing two sets of patterns for
3844 subtract-and-branch insns. Similarly if we have a constant in that
3845 position or if the third operand is the same as the first operand
3846 of the comparison. */
3848 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3849 && reversible_comparison_p (XEXP (x, 0))
3850 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3851 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3854 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3855 GET_MODE (XEXP (x, 0)),
3856 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3859 SUBST (XEXP (x, 1), XEXP (x, 2));
3860 SUBST (XEXP (x, 2), temp);
3863 /* If the two arms are identical, we don't need the comparison. */
3865 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3866 && ! side_effects_p (XEXP (x, 0)))
3869 /* Look for cases where we have (abs x) or (neg (abs X)). */
3871 if (GET_MODE_CLASS (mode) == MODE_INT
3872 && GET_CODE (XEXP (x, 2)) == NEG
3873 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3874 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3875 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3876 && ! side_effects_p (XEXP (x, 1)))
3877 switch (GET_CODE (XEXP (x, 0)))
3881 x = gen_unary (ABS, mode, XEXP (x, 1));
3885 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3889 /* Look for MIN or MAX. */
3891 if (! FLOAT_MODE_P (mode)
3892 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3893 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3894 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3895 && ! side_effects_p (XEXP (x, 0)))
3896 switch (GET_CODE (XEXP (x, 0)))
3900 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3904 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3908 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3912 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3916 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
3918 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when
3919 its second operand is zero, this can be done as (OP Z (mult COND C2))
3920 where C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer
3921 ZERO_EXTEND or SIGN_EXTEND as long as Z is already extended (so
3922 we don't destroy it). We can do this kind of thing in some
3923 cases when STORE_FLAG_VALUE is neither of the above, but it isn't
3924 worth checking for. */
3926 if (mode != VOIDmode && ! side_effects_p (x))
3928 rtx t = make_compound_operation (XEXP (x, 1), SET);
3929 rtx f = make_compound_operation (XEXP (x, 2), SET);
3930 rtx cond_op0 = XEXP (XEXP (x, 0), 0);
3931 rtx cond_op1 = XEXP (XEXP (x, 0), 1);
3932 enum rtx_code cond_op = GET_CODE (XEXP (x, 0));
3933 enum rtx_code op, extend_op = NIL;
3934 enum machine_mode m = mode;
3937 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
3938 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
3939 || GET_CODE (t) == ASHIFT
3940 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
3941 && rtx_equal_p (XEXP (t, 0), f))
3942 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
3943 else if (GET_CODE (t) == SIGN_EXTEND
3944 && (GET_CODE (XEXP (t, 0)) == PLUS
3945 || GET_CODE (XEXP (t, 0)) == MINUS
3946 || GET_CODE (XEXP (t, 0)) == IOR
3947 || GET_CODE (XEXP (t, 0)) == XOR
3948 || GET_CODE (XEXP (t, 0)) == ASHIFT
3949 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
3950 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
3951 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
3952 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
3953 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
3954 && (num_sign_bit_copies (f, GET_MODE (f))
3955 > (GET_MODE_BITSIZE (mode)
3956 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
3958 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
3959 extend_op = SIGN_EXTEND;
3960 m = GET_MODE (XEXP (t, 0));
3962 else if (GET_CODE (t) == ZERO_EXTEND
3963 && (GET_CODE (XEXP (t, 0)) == PLUS
3964 || GET_CODE (XEXP (t, 0)) == MINUS
3965 || GET_CODE (XEXP (t, 0)) == IOR
3966 || GET_CODE (XEXP (t, 0)) == XOR
3967 || GET_CODE (XEXP (t, 0)) == ASHIFT
3968 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
3969 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
3970 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
3971 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3972 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
3973 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
3974 && ((nonzero_bits (f, GET_MODE (f))
3975 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
3978 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
3979 extend_op = ZERO_EXTEND;
3980 m = GET_MODE (XEXP (t, 0));
3983 if (reversible_comparison_p (XEXP (x, 0))
3984 && (GET_CODE (f) == PLUS || GET_CODE (f) == MINUS
3985 || GET_CODE (f) == IOR || GET_CODE (f) == XOR
3986 || GET_CODE (f) == ASHIFT
3987 || GET_CODE (f) == LSHIFTRT || GET_CODE (f) == ASHIFTRT)
3988 && rtx_equal_p (XEXP (f, 0), t))
3990 c1 = XEXP (f, 1), op = GET_CODE (f), z = t;
3991 cond_op = reverse_condition (cond_op);
3993 else if (GET_CODE (f) == SIGN_EXTEND
3994 && (GET_CODE (XEXP (f, 0)) == PLUS
3995 || GET_CODE (XEXP (f, 0)) == MINUS
3996 || GET_CODE (XEXP (f, 0)) == IOR
3997 || GET_CODE (XEXP (f, 0)) == XOR
3998 || GET_CODE (XEXP (f, 0)) == ASHIFT
3999 || GET_CODE (XEXP (f, 0)) == LSHIFTRT
4000 || GET_CODE (XEXP (f, 0)) == ASHIFTRT)
4001 && GET_CODE (XEXP (XEXP (f, 0), 0)) == SUBREG
4002 && subreg_lowpart_p (XEXP (XEXP (f, 0), 0))
4003 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (f, 0), 0)), f)
4004 && (num_sign_bit_copies (t, GET_MODE (t))
4005 > (GET_MODE_BITSIZE (mode)
4006 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (f, 0), 0))))))
4008 c1 = XEXP (XEXP (f, 0), 1); z = t; op = GET_CODE (XEXP (f, 0));
4009 extend_op = SIGN_EXTEND;
4010 m = GET_MODE (XEXP (f, 0));
4011 cond_op = reverse_condition (cond_op);
4013 else if (GET_CODE (f) == ZERO_EXTEND
4014 && (GET_CODE (XEXP (f, 0)) == PLUS
4015 || GET_CODE (XEXP (f, 0)) == MINUS
4016 || GET_CODE (XEXP (f, 0)) == IOR
4017 || GET_CODE (XEXP (f, 0)) == XOR
4018 || GET_CODE (XEXP (f, 0)) == ASHIFT
4019 || GET_CODE (XEXP (f, 0)) == LSHIFTRT
4020 || GET_CODE (XEXP (f, 0)) == ASHIFTRT)
4021 && GET_CODE (XEXP (XEXP (f, 0), 0)) == SUBREG
4022 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4023 && subreg_lowpart_p (XEXP (XEXP (f, 0), 0))
4024 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (f, 0), 0)), t)
4025 && ((nonzero_bits (t, GET_MODE (t))
4026 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (f, 0), 0))))
4029 c1 = XEXP (XEXP (f, 0), 1); z = t; op = GET_CODE (XEXP (f, 0));
4030 extend_op = ZERO_EXTEND;
4031 m = GET_MODE (XEXP (f, 0));
4032 cond_op = reverse_condition (cond_op);
4037 temp = subst (gen_binary (cond_op, m, cond_op0, cond_op1),
4038 pc_rtx, pc_rtx, 0, 0);
4041 temp = gen_binary (MULT, m, temp,
4042 gen_binary (MULT, m, c1,
4043 GEN_INT (STORE_FLAG_VALUE)));
4045 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4047 if (extend_op != NIL)
4048 temp = gen_unary (extend_op, mode, temp);
4055 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to
4056 be 0 or 1 and C1 is a single bit or A is known to be 0 or -1 and
4057 C1 is the negation of a single bit, we can convert this operation
4058 to a shift. We can actually do this in more general cases, but it
4059 doesn't seem worth it. */
4061 if (GET_CODE (XEXP (x, 0)) == NE && XEXP (XEXP (x, 0), 1) == const0_rtx
4062 && XEXP (x, 2) == const0_rtx && GET_CODE (XEXP (x, 1)) == CONST_INT
4063 && ((1 == nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
4064 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4065 || ((num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
4066 == GET_MODE_BITSIZE (mode))
4067 && (i = exact_log2 (- INTVAL (XEXP (x, 1)))) >= 0)))
4069 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4070 gen_lowpart_for_combine (mode,
4071 XEXP (XEXP (x, 0), 0)),
4079 /* If we are processing SET_DEST, we are done. */
4083 x = expand_compound_operation (x);
4084 if (GET_CODE (x) != code)
4089 /* (set (pc) (return)) gets written as (return). */
4090 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
4093 /* Convert this into a field assignment operation, if possible. */
4094 x = make_field_assignment (x);
4096 /* If we are setting CC0 or if the source is a COMPARE, look for the
4097 use of the comparison result and try to simplify it unless we already
4098 have used undobuf.other_insn. */
4099 if ((GET_CODE (SET_SRC (x)) == COMPARE
4101 || SET_DEST (x) == cc0_rtx
4104 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
4106 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4107 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4108 && XEXP (*cc_use, 0) == SET_DEST (x))
4110 enum rtx_code old_code = GET_CODE (*cc_use);
4111 enum rtx_code new_code;
4113 int other_changed = 0;
4114 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
4116 if (GET_CODE (SET_SRC (x)) == COMPARE)
4117 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
4119 op0 = SET_SRC (x), op1 = const0_rtx;
4121 /* Simplify our comparison, if possible. */
4122 new_code = simplify_comparison (old_code, &op0, &op1);
4124 #ifdef EXTRA_CC_MODES
4125 /* If this machine has CC modes other than CCmode, check to see
4126 if we need to use a different CC mode here. */
4127 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4128 #endif /* EXTRA_CC_MODES */
4130 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4131 /* If the mode changed, we have to change SET_DEST, the mode
4132 in the compare, and the mode in the place SET_DEST is used.
4133 If SET_DEST is a hard register, just build new versions with
4134 the proper mode. If it is a pseudo, we lose unless it is only
4135 time we set the pseudo, in which case we can safely change
4137 if (compare_mode != GET_MODE (SET_DEST (x)))
4139 int regno = REGNO (SET_DEST (x));
4140 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4142 if (regno < FIRST_PSEUDO_REGISTER
4143 || (reg_n_sets[regno] == 1
4144 && ! REG_USERVAR_P (SET_DEST (x))))
4146 if (regno >= FIRST_PSEUDO_REGISTER)
4147 SUBST (regno_reg_rtx[regno], new_dest);
4149 SUBST (SET_DEST (x), new_dest);
4150 SUBST (XEXP (*cc_use, 0), new_dest);
4156 /* If the code changed, we have to build a new comparison
4157 in undobuf.other_insn. */
4158 if (new_code != old_code)
4160 unsigned HOST_WIDE_INT mask;
4162 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4163 SET_DEST (x), const0_rtx));
4165 /* If the only change we made was to change an EQ into an
4166 NE or vice versa, OP0 has only one bit that might be nonzero,
4167 and OP1 is zero, check if changing the user of the condition
4168 code will produce a valid insn. If it won't, we can keep
4169 the original code in that insn by surrounding our operation
4172 if (((old_code == NE && new_code == EQ)
4173 || (old_code == EQ && new_code == NE))
4174 && ! other_changed && op1 == const0_rtx
4175 && (GET_MODE_BITSIZE (GET_MODE (op0))
4176 <= HOST_BITS_PER_WIDE_INT)
4177 && (exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0)))
4180 rtx pat = PATTERN (other_insn), note = 0;
4182 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4183 && ! check_asm_operands (pat)))
4185 PUT_CODE (*cc_use, old_code);
4188 op0 = gen_binary (XOR, GET_MODE (op0), op0,
4197 undobuf.other_insn = other_insn;
4200 /* If we are now comparing against zero, change our source if
4201 needed. If we do not use cc0, we always have a COMPARE. */
4202 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
4203 SUBST (SET_SRC (x), op0);
4207 /* Otherwise, if we didn't previously have a COMPARE in the
4208 correct mode, we need one. */
4209 if (GET_CODE (SET_SRC (x)) != COMPARE
4210 || GET_MODE (SET_SRC (x)) != compare_mode)
4211 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
4215 /* Otherwise, update the COMPARE if needed. */
4216 SUBST (XEXP (SET_SRC (x), 0), op0);
4217 SUBST (XEXP (SET_SRC (x), 1), op1);
4222 /* Get SET_SRC in a form where we have placed back any
4223 compound expressions. Then do the checks below. */
4224 temp = make_compound_operation (SET_SRC (x), SET);
4225 SUBST (SET_SRC (x), temp);
4228 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
4229 operation, and X being a REG or (subreg (reg)), we may be able to
4230 convert this to (set (subreg:m2 x) (op)).
4232 We can always do this if M1 is narrower than M2 because that
4233 means that we only care about the low bits of the result.
4235 However, on machines without WORD_REGISTER_OPERATIONS defined,
4236 we cannot perform a narrower operation that requested since the
4237 high-order bits will be undefined. On machine where it is defined,
4238 this transformation is safe as long as M1 and M2 have the same
4241 if (GET_CODE (SET_SRC (x)) == SUBREG
4242 && subreg_lowpart_p (SET_SRC (x))
4243 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
4244 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
4246 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
4247 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4248 #ifndef WORD_REGISTER_OPERATIONS
4249 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
4250 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
4252 && (GET_CODE (SET_DEST (x)) == REG
4253 || (GET_CODE (SET_DEST (x)) == SUBREG
4254 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
4256 SUBST (SET_DEST (x),
4257 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
4259 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
4262 #ifdef LOAD_EXTEND_OP
4263 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
4264 M wider than N, this would require a paradoxical subreg.
4265 Replace the subreg with a zero_extend to avoid the reload that
4266 would otherwise be required. */
4268 if (GET_CODE (SET_SRC (x)) == SUBREG
4269 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (SET_SRC (x)))) != NIL
4270 && subreg_lowpart_p (SET_SRC (x))
4271 && SUBREG_WORD (SET_SRC (x)) == 0
4272 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
4273 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
4274 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
4276 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE
4277 (SUBREG_REG (SET_SRC (x)))),
4278 GET_MODE (SET_SRC (x)),
4279 XEXP (SET_SRC (x), 0)));
4282 #ifndef HAVE_conditional_move
4284 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
4285 and we are comparing an item known to be 0 or -1 against 0, use a
4286 logical operation instead. Check for one of the arms being an IOR
4287 of the other arm with some value. We compute three terms to be
4288 IOR'ed together. In practice, at most two will be nonzero. Then
4291 if (GET_CODE (SET_DEST (x)) != PC
4292 && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
4293 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
4294 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
4295 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
4296 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
4297 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
4298 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
4299 && ! side_effects_p (SET_SRC (x)))
4301 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
4302 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
4303 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
4304 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
4305 rtx term1 = const0_rtx, term2, term3;
4307 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4308 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4309 else if (GET_CODE (true) == IOR
4310 && rtx_equal_p (XEXP (true, 1), false))
4311 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4312 else if (GET_CODE (false) == IOR
4313 && rtx_equal_p (XEXP (false, 0), true))
4314 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4315 else if (GET_CODE (false) == IOR
4316 && rtx_equal_p (XEXP (false, 1), true))
4317 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4319 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4320 XEXP (XEXP (SET_SRC (x), 0), 0), true);
4321 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4322 gen_unary (NOT, GET_MODE (SET_SRC (x)),
4323 XEXP (XEXP (SET_SRC (x), 0), 0)),
4327 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4328 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4336 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4338 x = simplify_and_const_int (x, mode, XEXP (x, 0),
4339 INTVAL (XEXP (x, 1)));
4341 /* If we have (ior (and (X C1) C2)) and the next restart would be
4342 the last, simplify this by making C1 as small as possible
4344 if (n_restarts >= 3 && GET_CODE (x) == IOR
4345 && GET_CODE (XEXP (x, 0)) == AND
4346 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4347 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4349 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
4350 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
4351 & ~ INTVAL (XEXP (x, 1))));
4352 return gen_binary (IOR, mode, temp, XEXP (x, 1));
4355 if (GET_CODE (x) != AND)
4359 /* Convert (A | B) & A to A. */
4360 if (GET_CODE (XEXP (x, 0)) == IOR
4361 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4362 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4363 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4364 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4367 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4368 insn (and may simplify more). */
4369 else if (GET_CODE (XEXP (x, 0)) == XOR
4370 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4371 && ! side_effects_p (XEXP (x, 1)))
4373 x = gen_binary (AND, mode,
4374 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4378 else if (GET_CODE (XEXP (x, 0)) == XOR
4379 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4380 && ! side_effects_p (XEXP (x, 1)))
4382 x = gen_binary (AND, mode,
4383 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4388 /* Similarly for (~ (A ^ B)) & A. */
4389 else if (GET_CODE (XEXP (x, 0)) == NOT
4390 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4391 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
4392 && ! side_effects_p (XEXP (x, 1)))
4394 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
4398 else if (GET_CODE (XEXP (x, 0)) == NOT
4399 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4400 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
4401 && ! side_effects_p (XEXP (x, 1)))
4403 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
4408 /* If we have (and A B) with A not an object but that is known to
4409 be -1 or 0, this is equivalent to the expression
4410 (if_then_else (ne A (const_int 0)) B (const_int 0))
4411 We make this conversion because it may allow further
4412 simplifications and then allow use of conditional move insns.
4413 If the machine doesn't have condition moves, code in case SET
4414 will convert the IF_THEN_ELSE back to the logical operation.
4415 We build the IF_THEN_ELSE here in case further simplification
4416 is possible (e.g., we can convert it to ABS). */
4418 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
4419 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4420 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
4421 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4422 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4424 rtx op0 = XEXP (x, 0);
4425 rtx op1 = const0_rtx;
4426 enum rtx_code comp_code
4427 = simplify_comparison (NE, &op0, &op1);
4429 x = gen_rtx_combine (IF_THEN_ELSE, mode,
4430 gen_binary (comp_code, VOIDmode, op0, op1),
4431 XEXP (x, 1), const0_rtx);
4435 /* In the following group of tests (and those in case IOR below),
4436 we start with some combination of logical operations and apply
4437 the distributive law followed by the inverse distributive law.
4438 Most of the time, this results in no change. However, if some of
4439 the operands are the same or inverses of each other, simplifications
4442 For example, (and (ior A B) (not B)) can occur as the result of
4443 expanding a bit field assignment. When we apply the distributive
4444 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4445 which then simplifies to (and (A (not B))). */
4447 /* If we have (and (ior A B) C), apply the distributive law and then
4448 the inverse distributive law to see if things simplify. */
4450 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4452 x = apply_distributive_law
4453 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4454 gen_binary (AND, mode,
4455 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4456 gen_binary (AND, mode,
4457 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4458 if (GET_CODE (x) != AND)
4462 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4464 x = apply_distributive_law
4465 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4466 gen_binary (AND, mode,
4467 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4468 gen_binary (AND, mode,
4469 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4470 if (GET_CODE (x) != AND)
4474 /* Similarly, taking advantage of the fact that
4475 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4477 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4479 x = apply_distributive_law
4480 (gen_binary (XOR, mode,
4481 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4482 XEXP (XEXP (x, 1), 0)),
4483 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4484 XEXP (XEXP (x, 1), 1))));
4485 if (GET_CODE (x) != AND)
4489 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4491 x = apply_distributive_law
4492 (gen_binary (XOR, mode,
4493 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4494 XEXP (XEXP (x, 0), 0)),
4495 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4496 XEXP (XEXP (x, 0), 1))));
4497 if (GET_CODE (x) != AND)
4503 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4504 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4505 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4506 && (nonzero_bits (XEXP (x, 0), mode) & ~ INTVAL (XEXP (x, 1))) == 0)
4509 /* Convert (A & B) | A to A. */
4510 if (GET_CODE (XEXP (x, 0)) == AND
4511 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4512 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4513 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4514 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4517 /* If we have (ior (and A B) C), apply the distributive law and then
4518 the inverse distributive law to see if things simplify. */
4520 if (GET_CODE (XEXP (x, 0)) == AND)
4522 x = apply_distributive_law
4523 (gen_binary (AND, mode,
4524 gen_binary (IOR, mode,
4525 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4526 gen_binary (IOR, mode,
4527 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4529 if (GET_CODE (x) != IOR)
4533 if (GET_CODE (XEXP (x, 1)) == AND)
4535 x = apply_distributive_law
4536 (gen_binary (AND, mode,
4537 gen_binary (IOR, mode,
4538 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4539 gen_binary (IOR, mode,
4540 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4542 if (GET_CODE (x) != IOR)
4546 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4547 mode size to (rotate A CX). */
4549 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4550 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4551 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4552 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4553 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4554 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4555 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4556 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4557 == GET_MODE_BITSIZE (mode)))
4561 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4562 shift_count = XEXP (XEXP (x, 0), 1);
4564 shift_count = XEXP (XEXP (x, 1), 1);
4565 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4571 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4572 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4575 int num_negated = 0;
4576 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4578 if (GET_CODE (in1) == NOT)
4579 num_negated++, in1 = XEXP (in1, 0);
4580 if (GET_CODE (in2) == NOT)
4581 num_negated++, in2 = XEXP (in2, 0);
4583 if (num_negated == 2)
4585 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4586 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4588 else if (num_negated == 1)
4590 x = gen_unary (NOT, mode,
4591 gen_binary (XOR, mode, in1, in2));
4596 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4597 correspond to a machine insn or result in further simplifications
4598 if B is a constant. */
4600 if (GET_CODE (XEXP (x, 0)) == AND
4601 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4602 && ! side_effects_p (XEXP (x, 1)))
4604 x = gen_binary (AND, mode,
4605 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4609 else if (GET_CODE (XEXP (x, 0)) == AND
4610 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4611 && ! side_effects_p (XEXP (x, 1)))
4613 x = gen_binary (AND, mode,
4614 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4620 #if STORE_FLAG_VALUE == 1
4621 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4623 if (XEXP (x, 1) == const1_rtx
4624 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4625 && reversible_comparison_p (XEXP (x, 0)))
4626 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4627 mode, XEXP (XEXP (x, 0), 0),
4628 XEXP (XEXP (x, 0), 1));
4630 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4631 is (lt foo (const_int 0)), so we can perform the above
4634 if (XEXP (x, 1) == const1_rtx
4635 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4636 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4637 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
4638 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
4641 /* (xor (comparison foo bar) (const_int sign-bit))
4642 when STORE_FLAG_VALUE is the sign bit. */
4643 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4644 && (STORE_FLAG_VALUE
4645 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4646 && XEXP (x, 1) == const_true_rtx
4647 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4648 && reversible_comparison_p (XEXP (x, 0)))
4649 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4650 mode, XEXP (XEXP (x, 0), 0),
4651 XEXP (XEXP (x, 0), 1));
4655 /* (abs (neg <foo>)) -> (abs <foo>) */
4656 if (GET_CODE (XEXP (x, 0)) == NEG)
4657 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4659 /* If operand is something known to be positive, ignore the ABS. */
4660 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4661 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4662 <= HOST_BITS_PER_WIDE_INT)
4663 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4664 & ((HOST_WIDE_INT) 1
4665 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4670 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4671 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4673 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4679 /* (ffs (*_extend <X>)) = (ffs <X>) */
4680 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4681 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4682 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4686 /* (float (sign_extend <X>)) = (float <X>). */
4687 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4688 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4697 /* If this is a shift by a constant amount, simplify it. */
4698 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4700 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4701 INTVAL (XEXP (x, 1)));
4702 if (GET_CODE (x) != code)
4706 #ifdef SHIFT_COUNT_TRUNCATED
4707 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4709 force_to_mode (XEXP (x, 1), GET_MODE (x),
4711 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4722 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4723 operations" because they can be replaced with two more basic operations.
4724 ZERO_EXTEND is also considered "compound" because it can be replaced with
4725 an AND operation, which is simpler, though only one operation.
4727 The function expand_compound_operation is called with an rtx expression
4728 and will convert it to the appropriate shifts and AND operations,
4729 simplifying at each stage.
4731 The function make_compound_operation is called to convert an expression
4732 consisting of shifts and ANDs into the equivalent compound expression.
4733 It is the inverse of this function, loosely speaking. */
4736 expand_compound_operation (x)
4744 switch (GET_CODE (x))
4749 /* We can't necessarily use a const_int for a multiword mode;
4750 it depends on implicitly extending the value.
4751 Since we don't know the right way to extend it,
4752 we can't tell whether the implicit way is right.
4754 Even for a mode that is no wider than a const_int,
4755 we can't win, because we need to sign extend one of its bits through
4756 the rest of it, and we don't know which bit. */
4757 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4760 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4763 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4764 /* If the inner object has VOIDmode (the only way this can happen
4765 is if it is a ASM_OPERANDS), we can't do anything since we don't
4766 know how much masking to do. */
4775 /* If the operand is a CLOBBER, just return it. */
4776 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4779 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4780 || GET_CODE (XEXP (x, 2)) != CONST_INT
4781 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4784 len = INTVAL (XEXP (x, 1));
4785 pos = INTVAL (XEXP (x, 2));
4787 /* If this goes outside the object being extracted, replace the object
4788 with a (use (mem ...)) construct that only combine understands
4789 and is used only for this purpose. */
4790 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4791 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4794 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4802 /* If we reach here, we want to return a pair of shifts. The inner
4803 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4804 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4805 logical depending on the value of UNSIGNEDP.
4807 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4808 converted into an AND of a shift.
4810 We must check for the case where the left shift would have a negative
4811 count. This can happen in a case like (x >> 31) & 255 on machines
4812 that can't shift by a constant. On those machines, we would first
4813 combine the shift with the AND to produce a variable-position
4814 extraction. Then the constant of 31 would be substituted in to produce
4815 a such a position. */
4817 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4818 if (modewidth >= pos - len)
4819 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4821 simplify_shift_const (NULL_RTX, ASHIFT,
4824 modewidth - pos - len),
4827 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4828 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4829 simplify_shift_const (NULL_RTX, LSHIFTRT,
4832 ((HOST_WIDE_INT) 1 << len) - 1);
4834 /* Any other cases we can't handle. */
4838 /* If we couldn't do this for some reason, return the original
4840 if (GET_CODE (tem) == CLOBBER)
4846 /* X is a SET which contains an assignment of one object into
4847 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4848 or certain SUBREGS). If possible, convert it into a series of
4851 We half-heartedly support variable positions, but do not at all
4852 support variable lengths. */
4855 expand_field_assignment (x)
4859 rtx pos; /* Always counts from low bit. */
4862 enum machine_mode compute_mode;
4864 /* Loop until we find something we can't simplify. */
4867 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4868 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4870 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4871 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4874 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4875 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4877 inner = XEXP (SET_DEST (x), 0);
4878 len = INTVAL (XEXP (SET_DEST (x), 1));
4879 pos = XEXP (SET_DEST (x), 2);
4881 /* If the position is constant and spans the width of INNER,
4882 surround INNER with a USE to indicate this. */
4883 if (GET_CODE (pos) == CONST_INT
4884 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4885 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4888 if (GET_CODE (pos) == CONST_INT)
4889 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4891 else if (GET_CODE (pos) == MINUS
4892 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4893 && (INTVAL (XEXP (pos, 1))
4894 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4895 /* If position is ADJUST - X, new position is X. */
4896 pos = XEXP (pos, 0);
4898 pos = gen_binary (MINUS, GET_MODE (pos),
4899 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4905 /* A SUBREG between two modes that occupy the same numbers of words
4906 can be done by moving the SUBREG to the source. */
4907 else if (GET_CODE (SET_DEST (x)) == SUBREG
4908 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4909 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4910 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4911 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4913 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4914 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4921 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4922 inner = SUBREG_REG (inner);
4924 compute_mode = GET_MODE (inner);
4926 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4927 if (len < HOST_BITS_PER_WIDE_INT)
4928 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4932 /* Now compute the equivalent expression. Make a copy of INNER
4933 for the SET_DEST in case it is a MEM into which we will substitute;
4934 we don't want shared RTL in that case. */
4935 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4936 gen_binary (IOR, compute_mode,
4937 gen_binary (AND, compute_mode,
4938 gen_unary (NOT, compute_mode,
4943 gen_binary (ASHIFT, compute_mode,
4944 gen_binary (AND, compute_mode,
4945 gen_lowpart_for_combine
4955 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
4956 it is an RTX that represents a variable starting position; otherwise,
4957 POS is the (constant) starting bit position (counted from the LSB).
4959 INNER may be a USE. This will occur when we started with a bitfield
4960 that went outside the boundary of the object in memory, which is
4961 allowed on most machines. To isolate this case, we produce a USE
4962 whose mode is wide enough and surround the MEM with it. The only
4963 code that understands the USE is this routine. If it is not removed,
4964 it will cause the resulting insn not to match.
4966 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4969 IN_DEST is non-zero if this is a reference in the destination of a
4970 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4971 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4974 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4975 ZERO_EXTRACT should be built even for bits starting at bit 0.
4977 MODE is the desired mode of the result (if IN_DEST == 0). */
4980 make_extraction (mode, inner, pos, pos_rtx, len,
4981 unsignedp, in_dest, in_compare)
4982 enum machine_mode mode;
4988 int in_dest, in_compare;
4990 /* This mode describes the size of the storage area
4991 to fetch the overall value from. Within that, we
4992 ignore the POS lowest bits, etc. */
4993 enum machine_mode is_mode = GET_MODE (inner);
4994 enum machine_mode inner_mode;
4995 enum machine_mode wanted_mem_mode = byte_mode;
4996 enum machine_mode pos_mode = word_mode;
4997 enum machine_mode extraction_mode = word_mode;
4998 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5001 rtx orig_pos_rtx = pos_rtx;
5004 /* Get some information about INNER and get the innermost object. */
5005 if (GET_CODE (inner) == USE)
5006 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5007 /* We don't need to adjust the position because we set up the USE
5008 to pretend that it was a full-word object. */
5009 spans_byte = 1, inner = XEXP (inner, 0);
5010 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5012 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5013 consider just the QI as the memory to extract from.
5014 The subreg adds or removes high bits; its mode is
5015 irrelevant to the meaning of this extraction,
5016 since POS and LEN count from the lsb. */
5017 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5018 is_mode = GET_MODE (SUBREG_REG (inner));
5019 inner = SUBREG_REG (inner);
5022 inner_mode = GET_MODE (inner);
5024 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5025 pos = INTVAL (pos_rtx), pos_rtx = 0;
5027 /* See if this can be done without an extraction. We never can if the
5028 width of the field is not the same as that of some integer mode. For
5029 registers, we can only avoid the extraction if the position is at the
5030 low-order bit and this is either not in the destination or we have the
5031 appropriate STRICT_LOW_PART operation available.
5033 For MEM, we can avoid an extract if the field starts on an appropriate
5034 boundary and we can change the mode of the memory reference. However,
5035 we cannot directly access the MEM if we have a USE and the underlying
5036 MEM is not TMODE. This combination means that MEM was being used in a
5037 context where bits outside its mode were being referenced; that is only
5038 valid in bit-field insns. */
5040 if (tmode != BLKmode
5041 && ! (spans_byte && inner_mode != tmode)
5042 && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM
5044 || (GET_CODE (inner) == REG
5045 && (movstrict_optab->handlers[(int) tmode].insn_code
5046 != CODE_FOR_nothing))))
5047 || (GET_CODE (inner) == MEM && pos_rtx == 0
5049 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5050 : BITS_PER_UNIT)) == 0
5051 /* We can't do this if we are widening INNER_MODE (it
5052 may not be aligned, for one thing). */
5053 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5054 && (inner_mode == tmode
5055 || (! mode_dependent_address_p (XEXP (inner, 0))
5056 && ! MEM_VOLATILE_P (inner))))))
5058 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5059 field. If the original and current mode are the same, we need not
5060 adjust the offset. Otherwise, we do if bytes big endian.
5062 If INNER is not a MEM, get a piece consisting of the just the field
5063 of interest (in this case POS must be 0). */
5065 if (GET_CODE (inner) == MEM)
5068 /* POS counts from lsb, but make OFFSET count in memory order. */
5069 if (BYTES_BIG_ENDIAN)
5070 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5072 offset = pos / BITS_PER_UNIT;
5074 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5075 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5076 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5077 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5079 else if (GET_CODE (inner) == REG)
5080 /* We can't call gen_lowpart_for_combine here since we always want
5081 a SUBREG and it would sometimes return a new hard register. */
5082 new = gen_rtx (SUBREG, tmode, inner,
5084 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5085 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
5089 new = force_to_mode (inner, tmode,
5090 len >= HOST_BITS_PER_WIDE_INT
5091 ? GET_MODE_MASK (tmode)
5092 : ((HOST_WIDE_INT) 1 << len) - 1,
5095 /* If this extraction is going into the destination of a SET,
5096 make a STRICT_LOW_PART unless we made a MEM. */
5099 return (GET_CODE (new) == MEM ? new
5100 : (GET_CODE (new) != SUBREG
5101 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5102 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5104 /* Otherwise, sign- or zero-extend unless we already are in the
5107 return (mode == tmode ? new
5108 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5112 /* Unless this is a COMPARE or we have a funny memory reference,
5113 don't do anything with zero-extending field extracts starting at
5114 the low-order bit since they are simple AND operations. */
5115 if (pos_rtx == 0 && pos == 0 && ! in_dest
5116 && ! in_compare && ! spans_byte && unsignedp)
5119 /* Get the mode to use should INNER be a MEM, the mode for the position,
5120 and the mode for the result. */
5124 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5125 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5126 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5131 if (! in_dest && unsignedp)
5133 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5134 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5135 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5140 if (! in_dest && ! unsignedp)
5142 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5143 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5144 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5148 /* Never narrow an object, since that might not be safe. */
5150 if (mode != VOIDmode
5151 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5152 extraction_mode = mode;
5154 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5155 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5156 pos_mode = GET_MODE (pos_rtx);
5158 /* If this is not from memory or we have to change the mode of memory and
5159 cannot, the desired mode is EXTRACTION_MODE. */
5160 if (GET_CODE (inner) != MEM
5161 || (inner_mode != wanted_mem_mode
5162 && (mode_dependent_address_p (XEXP (inner, 0))
5163 || MEM_VOLATILE_P (inner))))
5164 wanted_mem_mode = extraction_mode;
5169 /* If position is constant, compute new position. Otherwise, build
5172 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
5176 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5177 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
5178 GET_MODE_BITSIZE (wanted_mem_mode))
5183 /* If INNER has a wider mode, make it smaller. If this is a constant
5184 extract, try to adjust the byte to point to the byte containing
5186 if (wanted_mem_mode != VOIDmode
5187 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
5188 && ((GET_CODE (inner) == MEM
5189 && (inner_mode == wanted_mem_mode
5190 || (! mode_dependent_address_p (XEXP (inner, 0))
5191 && ! MEM_VOLATILE_P (inner))))))
5195 /* The computations below will be correct if the machine is big
5196 endian in both bits and bytes or little endian in bits and bytes.
5197 If it is mixed, we must adjust. */
5199 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5200 adjust OFFSET to compensate. */
5201 #if BYTES_BIG_ENDIAN
5203 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5204 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5207 /* If this is a constant position, we can move to the desired byte. */
5210 offset += pos / BITS_PER_UNIT;
5211 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
5214 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5215 if (! spans_byte && is_mode != wanted_mem_mode)
5216 offset = (GET_MODE_SIZE (is_mode)
5217 - GET_MODE_SIZE (wanted_mem_mode) - offset);
5220 if (offset != 0 || inner_mode != wanted_mem_mode)
5222 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
5223 plus_constant (XEXP (inner, 0), offset));
5224 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5225 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5226 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5231 /* If INNER is not memory, we can always get it into the proper mode. */
5232 else if (GET_CODE (inner) != MEM)
5233 inner = force_to_mode (inner, extraction_mode,
5234 pos_rtx || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5235 ? GET_MODE_MASK (extraction_mode)
5236 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5239 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5240 have to zero extend. Otherwise, we can just use a SUBREG. */
5242 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5243 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5244 else if (pos_rtx != 0
5245 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5246 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5248 /* Make POS_RTX unless we already have it and it is correct. If we don't
5249 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5251 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5252 pos_rtx = orig_pos_rtx;
5254 else if (pos_rtx == 0)
5255 pos_rtx = GEN_INT (pos);
5257 /* Make the required operation. See if we can use existing rtx. */
5258 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5259 extraction_mode, inner, GEN_INT (len), pos_rtx);
5261 new = gen_lowpart_for_combine (mode, new);
5266 /* Look at the expression rooted at X. Look for expressions
5267 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5268 Form these expressions.
5270 Return the new rtx, usually just X.
5272 Also, for machines like the Vax that don't have logical shift insns,
5273 try to convert logical to arithmetic shift operations in cases where
5274 they are equivalent. This undoes the canonicalizations to logical
5275 shifts done elsewhere.
5277 We try, as much as possible, to re-use rtl expressions to save memory.
5279 IN_CODE says what kind of expression we are processing. Normally, it is
5280 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5281 being kludges), it is MEM. When processing the arguments of a comparison
5282 or a COMPARE against zero, it is COMPARE. */
5285 make_compound_operation (x, in_code)
5287 enum rtx_code in_code;
5289 enum rtx_code code = GET_CODE (x);
5290 enum machine_mode mode = GET_MODE (x);
5291 int mode_width = GET_MODE_BITSIZE (mode);
5292 enum rtx_code next_code;
5298 /* Select the code to be used in recursive calls. Once we are inside an
5299 address, we stay there. If we have a comparison, set to COMPARE,
5300 but once inside, go back to our default of SET. */
5302 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5303 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5304 && XEXP (x, 1) == const0_rtx) ? COMPARE
5305 : in_code == COMPARE ? SET : in_code);
5307 /* Process depending on the code of this operation. If NEW is set
5308 non-zero, it will be returned. */
5314 /* Convert shifts by constants into multiplications if inside
5316 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5317 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5318 && INTVAL (XEXP (x, 1)) >= 0)
5320 new = make_compound_operation (XEXP (x, 0), next_code);
5321 new = gen_rtx_combine (MULT, mode, new,
5322 GEN_INT ((HOST_WIDE_INT) 1
5323 << INTVAL (XEXP (x, 1))));
5328 /* If the second operand is not a constant, we can't do anything
5330 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5333 /* If the constant is a power of two minus one and the first operand
5334 is a logical right shift, make an extraction. */
5335 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5336 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5338 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5339 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5340 0, in_code == COMPARE);
5343 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5344 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5345 && subreg_lowpart_p (XEXP (x, 0))
5346 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5347 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5349 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5351 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5352 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5353 0, in_code == COMPARE);
5355 /* Same as previous, but for (xor/ior (lshift...) (lshift...)). */
5356 else if ((GET_CODE (XEXP (x, 0)) == XOR
5357 || GET_CODE (XEXP (x, 0)) == IOR)
5358 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5359 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5360 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5362 /* Apply the distributive law, and then try to make extractions. */
5363 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5364 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5366 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5368 new = make_compound_operation (new, in_code);
5371 /* If we are have (and (rotate X C) M) and C is larger than the number
5372 of bits in M, this is an extraction. */
5374 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5375 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5376 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5377 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5379 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5380 new = make_extraction (mode, new,
5381 (GET_MODE_BITSIZE (mode)
5382 - INTVAL (XEXP (XEXP (x, 0), 1))),
5383 NULL_RTX, i, 1, 0, in_code == COMPARE);
5386 /* On machines without logical shifts, if the operand of the AND is
5387 a logical shift and our mask turns off all the propagated sign
5388 bits, we can replace the logical shift with an arithmetic shift. */
5389 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5390 && (lshr_optab->handlers[(int) mode].insn_code
5391 == CODE_FOR_nothing)
5392 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5393 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5394 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5395 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5396 && mode_width <= HOST_BITS_PER_WIDE_INT)
5398 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5400 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5401 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5403 gen_rtx_combine (ASHIFTRT, mode,
5404 make_compound_operation (XEXP (XEXP (x, 0), 0),
5406 XEXP (XEXP (x, 0), 1)));
5409 /* If the constant is one less than a power of two, this might be
5410 representable by an extraction even if no shift is present.
5411 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5412 we are in a COMPARE. */
5413 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5414 new = make_extraction (mode,
5415 make_compound_operation (XEXP (x, 0),
5417 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5419 /* If we are in a comparison and this is an AND with a power of two,
5420 convert this into the appropriate bit extract. */
5421 else if (in_code == COMPARE
5422 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5423 new = make_extraction (mode,
5424 make_compound_operation (XEXP (x, 0),
5426 i, NULL_RTX, 1, 1, 0, 1);
5431 /* If the sign bit is known to be zero, replace this with an
5432 arithmetic shift. */
5433 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5434 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5435 && mode_width <= HOST_BITS_PER_WIDE_INT
5436 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5438 new = gen_rtx_combine (ASHIFTRT, mode,
5439 make_compound_operation (XEXP (x, 0),
5445 /* ... fall through ... */
5448 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5449 this is a SIGN_EXTRACT. */
5450 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5451 && GET_CODE (XEXP (x, 0)) == ASHIFT
5452 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5453 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
5455 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5456 new = make_extraction (mode, new,
5457 (INTVAL (XEXP (x, 1))
5458 - INTVAL (XEXP (XEXP (x, 0), 1))),
5459 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5460 code == LSHIFTRT, 0, in_code == COMPARE);
5463 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
5464 cases, we are better off returning a SIGN_EXTEND of the operation. */
5466 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5467 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
5468 || GET_CODE (XEXP (x, 0)) == XOR
5469 || GET_CODE (XEXP (x, 0)) == PLUS)
5470 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5471 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5472 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
5473 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5474 && 0 == (INTVAL (XEXP (XEXP (x, 0), 1))
5475 & (((HOST_WIDE_INT) 1
5476 << (MIN (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)),
5477 INTVAL (XEXP (x, 1)))
5480 rtx c1 = XEXP (XEXP (XEXP (x, 0), 0), 1);
5481 rtx c2 = XEXP (x, 1);
5482 rtx c3 = XEXP (XEXP (x, 0), 1);
5483 HOST_WIDE_INT newop1;
5484 rtx inner = XEXP (XEXP (XEXP (x, 0), 0), 0);
5486 /* If C1 > C2, INNER needs to have the shift performed on it
5488 if (INTVAL (c1) > INTVAL (c2))
5490 inner = gen_binary (ASHIFT, mode, inner,
5491 GEN_INT (INTVAL (c1) - INTVAL (c2)));
5495 newop1 = INTVAL (c3) >> INTVAL (c1);
5496 new = make_compound_operation (inner,
5497 GET_CODE (XEXP (x, 0)) == PLUS
5498 ? MEM : GET_CODE (XEXP (x, 0)));
5499 new = make_extraction (mode,
5500 gen_binary (GET_CODE (XEXP (x, 0)), mode, new,
5502 INTVAL (c2) - INTVAL (c1),
5503 NULL_RTX, mode_width - INTVAL (c2),
5504 code == LSHIFTRT, 0, in_code == COMPARE);
5507 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5508 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5509 && GET_CODE (XEXP (x, 0)) == NEG
5510 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5511 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5512 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5514 new = make_compound_operation (XEXP (XEXP (XEXP (x, 0), 0), 0),
5516 new = make_extraction (mode,
5517 gen_unary (GET_CODE (XEXP (x, 0)), mode, new),
5518 (INTVAL (XEXP (x, 1))
5519 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5520 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5521 code == LSHIFTRT, 0, in_code == COMPARE);
5526 /* Call ourselves recursively on the inner expression. If we are
5527 narrowing the object and it has a different RTL code from
5528 what it originally did, do this SUBREG as a force_to_mode. */
5530 tem = make_compound_operation (SUBREG_REG (x), in_code);
5531 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5532 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5533 && subreg_lowpart_p (x))
5535 rtx newer = force_to_mode (tem, mode,
5536 GET_MODE_MASK (mode), NULL_RTX, 0);
5538 /* If we have something other than a SUBREG, we might have
5539 done an expansion, so rerun outselves. */
5540 if (GET_CODE (newer) != SUBREG)
5541 newer = make_compound_operation (newer, in_code);
5549 x = gen_lowpart_for_combine (mode, new);
5550 code = GET_CODE (x);
5553 /* Now recursively process each operand of this operation. */
5554 fmt = GET_RTX_FORMAT (code);
5555 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5558 new = make_compound_operation (XEXP (x, i), next_code);
5559 SUBST (XEXP (x, i), new);
5565 /* Given M see if it is a value that would select a field of bits
5566 within an item, but not the entire word. Return -1 if not.
5567 Otherwise, return the starting position of the field, where 0 is the
5570 *PLEN is set to the length of the field. */
5573 get_pos_from_mask (m, plen)
5574 unsigned HOST_WIDE_INT m;
5577 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5578 int pos = exact_log2 (m & - m);
5583 /* Now shift off the low-order zero bits and see if we have a power of
5585 *plen = exact_log2 ((m >> pos) + 1);
5593 /* See if X can be simplified knowing that we will only refer to it in
5594 MODE and will only refer to those bits that are nonzero in MASK.
5595 If other bits are being computed or if masking operations are done
5596 that select a superset of the bits in MASK, they can sometimes be
5599 Return a possibly simplified expression, but always convert X to
5600 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5602 Also, if REG is non-zero and X is a register equal in value to REG,
5605 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5606 are all off in X. This is used when X will be complemented, by either
5610 force_to_mode (x, mode, mask, reg, just_select)
5612 enum machine_mode mode;
5613 unsigned HOST_WIDE_INT mask;
5617 enum rtx_code code = GET_CODE (x);
5618 int next_select = just_select || code == XOR || code == NOT;
5619 enum machine_mode op_mode;
5620 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5623 /* We want to perform the operation is its present mode unless we know
5624 that the operation is valid in MODE, in which case we do the operation
5626 op_mode = ((code_to_optab[(int) code] != 0
5627 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5628 != CODE_FOR_nothing))
5629 ? mode : GET_MODE (x));
5631 /* It is not valid to do a right-shift in a narrower mode
5632 than the one it came in with. */
5633 if ((code == LSHIFTRT || code == ASHIFTRT)
5634 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5635 op_mode = GET_MODE (x);
5637 /* Truncate MASK to fit OP_MODE. */
5639 mask &= GET_MODE_MASK (op_mode);
5641 /* When we have an arithmetic operation, or a shift whose count we
5642 do not know, we need to assume that all bit the up to the highest-order
5643 bit in MASK will be needed. This is how we form such a mask. */
5645 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
5646 ? GET_MODE_MASK (op_mode)
5647 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
5649 fuller_mask = ~ (HOST_WIDE_INT) 0;
5651 /* Determine what bits of X are guaranteed to be (non)zero. */
5652 nonzero = nonzero_bits (x, mode);
5654 /* If none of the bits in X are needed, return a zero. */
5655 if (! just_select && (nonzero & mask) == 0)
5658 /* If X is a CONST_INT, return a new one. Do this here since the
5659 test below will fail. */
5660 if (GET_CODE (x) == CONST_INT)
5662 HOST_WIDE_INT cval = INTVAL (x) & mask;
5663 int width = GET_MODE_BITSIZE (mode);
5665 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5666 number, sign extend it. */
5667 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5668 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5669 cval |= (HOST_WIDE_INT) -1 << width;
5671 return GEN_INT (cval);
5674 /* If X is narrower than MODE, just get X in the proper mode. */
5675 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
5676 return gen_lowpart_for_combine (mode, x);
5678 /* If we aren't changing the mode and all zero bits in MASK are already
5679 known to be zero in X, we need not do anything. */
5680 if (GET_MODE (x) == mode && (~ mask & nonzero) == 0)
5686 /* If X is a (clobber (const_int)), return it since we know we are
5687 generating something that won't match. */
5690 #if ! BITS_BIG_ENDIAN
5692 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5693 spanned the boundary of the MEM. If we are now masking so it is
5694 within that boundary, we don't need the USE any more. */
5695 if ((mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5696 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
5703 x = expand_compound_operation (x);
5704 if (GET_CODE (x) != code)
5705 return force_to_mode (x, mode, mask, reg, next_select);
5709 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5710 || rtx_equal_p (reg, get_last_value (x))))
5715 if (subreg_lowpart_p (x)
5716 /* We can ignore the effect this SUBREG if it narrows the mode or,
5717 on machines where register operations are performed on the full
5718 word, if the constant masks to zero all the bits the mode
5720 && ((GET_MODE_SIZE (GET_MODE (x))
5721 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5722 #ifdef WORD_REGISTER_OPERATIONS
5724 & GET_MODE_MASK (GET_MODE (x))
5725 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))
5728 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
5732 /* If this is an AND with a constant, convert it into an AND
5733 whose constant is the AND of that constant with MASK. If it
5734 remains an AND of MASK, delete it since it is redundant. */
5736 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5737 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
5739 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
5740 mask & INTVAL (XEXP (x, 1)));
5742 /* If X is still an AND, see if it is an AND with a mask that
5743 is just some low-order bits. If so, and it is BITS wide (it
5744 can't be wider), we don't need it. */
5746 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5747 && INTVAL (XEXP (x, 1)) == mask)
5756 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5757 low-order bits (as in an alignment operation) and FOO is already
5758 aligned to that boundary, mask C1 to that boundary as well.
5759 This may eliminate that PLUS and, later, the AND. */
5760 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5761 && exact_log2 (- mask) >= 0
5762 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
5763 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
5764 return force_to_mode (plus_constant (XEXP (x, 0),
5765 INTVAL (XEXP (x, 1)) & mask),
5766 mode, mask, reg, next_select);
5768 /* ... fall through ... */
5772 /* For PLUS, MINUS and MULT, we need any bits less significant than the
5773 most significant bit in MASK since carries from those bits will
5774 affect the bits we are interested in. */
5780 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5781 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5782 operation which may be a bitfield extraction. Ensure that the
5783 constant we form is not wider than the mode of X. */
5785 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5786 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5787 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5788 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5789 && GET_CODE (XEXP (x, 1)) == CONST_INT
5790 && ((INTVAL (XEXP (XEXP (x, 0), 1))
5791 + floor_log2 (INTVAL (XEXP (x, 1))))
5792 < GET_MODE_BITSIZE (GET_MODE (x)))
5793 && (INTVAL (XEXP (x, 1))
5794 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x)) == 0))
5796 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
5797 << INTVAL (XEXP (XEXP (x, 0), 1)));
5798 temp = gen_binary (GET_CODE (x), GET_MODE (x),
5799 XEXP (XEXP (x, 0), 0), temp);
5800 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (x, 1));
5801 return force_to_mode (x, mode, mask, reg, next_select);
5805 /* For most binary operations, just propagate into the operation and
5806 change the mode if we have an operation of that mode. */
5808 op0 = gen_lowpart_for_combine (op_mode,
5809 force_to_mode (XEXP (x, 0), mode, mask,
5811 op1 = gen_lowpart_for_combine (op_mode,
5812 force_to_mode (XEXP (x, 1), mode, mask,
5815 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
5816 MASK since OP1 might have been sign-extended but we never want
5817 to turn on extra bits, since combine might have previously relied
5818 on them being off. */
5819 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
5820 && (INTVAL (op1) & mask) != 0)
5821 op1 = GEN_INT (INTVAL (op1) & mask);
5823 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
5824 x = gen_binary (code, op_mode, op0, op1);
5829 /* For left shifts, do the same, but just for the first operand.
5830 However, we cannot do anything with shifts where we cannot
5831 guarantee that the counts are smaller than the size of the mode
5832 because such a count will have a different meaning in a
5835 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
5836 && INTVAL (XEXP (x, 1)) >= 0
5837 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
5838 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
5839 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
5840 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
5843 /* If the shift count is a constant and we can do arithmetic in
5844 the mode of the shift, refine which bits we need. Otherwise, use the
5845 conservative form of the mask. */
5846 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5847 && INTVAL (XEXP (x, 1)) >= 0
5848 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
5849 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
5850 mask >>= INTVAL (XEXP (x, 1));
5854 op0 = gen_lowpart_for_combine (op_mode,
5855 force_to_mode (XEXP (x, 0), op_mode,
5856 mask, reg, next_select));
5858 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
5859 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
5863 /* Here we can only do something if the shift count is a constant,
5864 this shift constant is valid for the host, and we can do arithmetic
5867 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5868 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5869 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
5871 rtx inner = XEXP (x, 0);
5873 /* Select the mask of the bits we need for the shift operand. */
5874 mask <<= INTVAL (XEXP (x, 1));
5876 /* We can only change the mode of the shift if we can do arithmetic
5877 in the mode of the shift and MASK is no wider than the width of
5879 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
5880 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
5881 op_mode = GET_MODE (x);
5883 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
5885 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
5886 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
5889 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
5890 shift and AND produces only copies of the sign bit (C2 is one less
5891 than a power of two), we can do this with just a shift. */
5893 if (GET_CODE (x) == LSHIFTRT
5894 && GET_CODE (XEXP (x, 1)) == CONST_INT
5895 && ((INTVAL (XEXP (x, 1))
5896 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
5897 >= GET_MODE_BITSIZE (GET_MODE (x)))
5898 && exact_log2 (mask + 1) >= 0
5899 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5900 >= exact_log2 (mask + 1)))
5901 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
5902 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
5903 - exact_log2 (mask + 1)));
5907 /* If we are just looking for the sign bit, we don't need this shift at
5908 all, even if it has a variable count. */
5909 if (mask == ((HOST_WIDE_INT) 1
5910 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))
5911 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
5913 /* If this is a shift by a constant, get a mask that contains those bits
5914 that are not copies of the sign bit. We then have two cases: If
5915 MASK only includes those bits, this can be a logical shift, which may
5916 allow simplifications. If MASK is a single-bit field not within
5917 those bits, we are requesting a copy of the sign bit and hence can
5918 shift the sign bit to the appropriate location. */
5920 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
5921 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
5925 nonzero = GET_MODE_MASK (GET_MODE (x));
5926 nonzero >>= INTVAL (XEXP (x, 1));
5928 if ((mask & ~ nonzero) == 0
5929 || (i = exact_log2 (mask)) >= 0)
5931 x = simplify_shift_const
5932 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
5933 i < 0 ? INTVAL (XEXP (x, 1))
5934 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
5936 if (GET_CODE (x) != ASHIFTRT)
5937 return force_to_mode (x, mode, mask, reg, next_select);
5941 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
5942 even if the shift count isn't a constant. */
5944 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
5946 /* If this is a sign-extension operation that just affects bits
5947 we don't care about, remove it. Be sure the call above returned
5948 something that is still a shift. */
5950 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
5951 && GET_CODE (XEXP (x, 1)) == CONST_INT
5952 && INTVAL (XEXP (x, 1)) >= 0
5953 && (INTVAL (XEXP (x, 1))
5954 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
5955 && GET_CODE (XEXP (x, 0)) == ASHIFT
5956 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5957 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5958 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
5965 /* If the shift count is constant and we can do computations
5966 in the mode of X, compute where the bits we care about are.
5967 Otherwise, we can't do anything. Don't change the mode of
5968 the shift or propagate MODE into the shift, though. */
5969 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5970 && INTVAL (XEXP (x, 1)) >= 0)
5972 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
5973 GET_MODE (x), GEN_INT (mask),
5977 force_to_mode (XEXP (x, 0), GET_MODE (x),
5978 INTVAL (temp), reg, next_select));
5983 /* We need any bits less significant than the most significant bit in
5984 MASK since carries from those bits will affect the bits we are
5990 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
5991 same as the XOR case above. Ensure that the constant we form is not
5992 wider than the mode of X. */
5994 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5995 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5996 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5997 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
5998 < GET_MODE_BITSIZE (GET_MODE (x)))
5999 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6001 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6002 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6003 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6005 return force_to_mode (x, mode, mask, reg, next_select);
6009 op0 = gen_lowpart_for_combine (op_mode,
6010 force_to_mode (XEXP (x, 0), mode, mask,
6012 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6013 x = gen_unary (code, op_mode, op0);
6017 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6018 in STORE_FLAG_VALUE and FOO has no bits that might be nonzero not
6020 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 0) == const0_rtx
6021 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0)
6022 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6027 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6028 written in a narrower mode. We play it safe and do not do so. */
6031 gen_lowpart_for_combine (GET_MODE (x),
6032 force_to_mode (XEXP (x, 1), mode,
6033 mask, reg, next_select)));
6035 gen_lowpart_for_combine (GET_MODE (x),
6036 force_to_mode (XEXP (x, 2), mode,
6037 mask, reg,next_select)));
6041 /* Ensure we return a value of the proper mode. */
6042 return gen_lowpart_for_combine (mode, x);
6045 /* Return the value of expression X given the fact that condition COND
6046 is known to be true when applied to REG as its first operand and VAL
6047 as its second. X is known to not be shared and so can be modified in
6050 We only handle the simplest cases, and specifically those cases that
6051 arise with IF_THEN_ELSE expressions. */
6054 known_cond (x, cond, reg, val)
6059 enum rtx_code code = GET_CODE (x);
6064 if (side_effects_p (x))
6067 if (cond == EQ && rtx_equal_p (x, reg))
6070 /* If X is (abs REG) and we know something about REG's relationship
6071 with zero, we may be able to simplify this. */
6073 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6076 case GE: case GT: case EQ:
6079 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
6082 /* The only other cases we handle are MIN, MAX, and comparisons if the
6083 operands are the same as REG and VAL. */
6085 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6087 if (rtx_equal_p (XEXP (x, 0), val))
6088 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6090 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6092 if (GET_RTX_CLASS (code) == '<')
6093 return (comparison_dominates_p (cond, code) ? const_true_rtx
6094 : (comparison_dominates_p (cond,
6095 reverse_condition (code))
6098 else if (code == SMAX || code == SMIN
6099 || code == UMIN || code == UMAX)
6101 int unsignedp = (code == UMIN || code == UMAX);
6103 if (code == SMAX || code == UMAX)
6104 cond = reverse_condition (cond);
6109 return unsignedp ? x : XEXP (x, 1);
6111 return unsignedp ? x : XEXP (x, 0);
6113 return unsignedp ? XEXP (x, 1) : x;
6115 return unsignedp ? XEXP (x, 0) : x;
6121 fmt = GET_RTX_FORMAT (code);
6122 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6125 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6126 else if (fmt[i] == 'E')
6127 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6128 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6135 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6136 Return that assignment if so.
6138 We only handle the most common cases. */
6141 make_field_assignment (x)
6144 rtx dest = SET_DEST (x);
6145 rtx src = SET_SRC (x);
6151 enum machine_mode mode;
6153 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6154 a clear of a one-bit field. We will have changed it to
6155 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6158 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6159 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6160 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6161 && (rtx_equal_p (dest, XEXP (src, 1))
6162 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6163 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
6165 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6167 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6170 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6171 && subreg_lowpart_p (XEXP (src, 0))
6172 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6173 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6174 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6175 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6176 && (rtx_equal_p (dest, XEXP (src, 1))
6177 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6178 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
6180 assign = make_extraction (VOIDmode, dest, 0,
6181 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6183 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6186 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
6188 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6189 && XEXP (XEXP (src, 0), 0) == const1_rtx
6190 && (rtx_equal_p (dest, XEXP (src, 1))
6191 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6192 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
6194 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6196 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6199 /* The other case we handle is assignments into a constant-position
6200 field. They look like (ior (and DEST C1) OTHER). If C1 represents
6201 a mask that has all one bits except for a group of zero bits and
6202 OTHER is known to have zeros where C1 has ones, this is such an
6203 assignment. Compute the position and length from C1. Shift OTHER
6204 to the appropriate position, force it to the required mode, and
6205 make the extraction. Check for the AND in both operands. */
6207 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
6208 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
6209 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
6210 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
6211 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
6212 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
6213 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
6214 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
6215 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
6216 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
6217 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
6219 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
6223 pos = get_pos_from_mask (c1 ^ GET_MODE_MASK (GET_MODE (dest)), &len);
6224 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6225 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6226 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6229 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6231 /* The mode to use for the source is the mode of the assignment, or of
6232 what is inside a possible STRICT_LOW_PART. */
6233 mode = (GET_CODE (assign) == STRICT_LOW_PART
6234 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6236 /* Shift OTHER right POS places and make it the source, restricting it
6237 to the proper length and mode. */
6239 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6240 GET_MODE (src), other, pos),
6242 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6243 ? GET_MODE_MASK (mode)
6244 : ((HOST_WIDE_INT) 1 << len) - 1,
6247 return gen_rtx_combine (SET, VOIDmode, assign, src);
6250 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6254 apply_distributive_law (x)
6257 enum rtx_code code = GET_CODE (x);
6258 rtx lhs, rhs, other;
6260 enum rtx_code inner_code;
6262 /* Distributivity is not true for floating point.
6263 It can change the value. So don't do it.
6264 -- rms and moshier@world.std.com. */
6265 if (FLOAT_MODE_P (GET_MODE (x)))
6268 /* The outer operation can only be one of the following: */
6269 if (code != IOR && code != AND && code != XOR
6270 && code != PLUS && code != MINUS)
6273 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6275 /* If either operand is a primitive we can't do anything, so get out fast. */
6276 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6277 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6280 lhs = expand_compound_operation (lhs);
6281 rhs = expand_compound_operation (rhs);
6282 inner_code = GET_CODE (lhs);
6283 if (inner_code != GET_CODE (rhs))
6286 /* See if the inner and outer operations distribute. */
6293 /* These all distribute except over PLUS. */
6294 if (code == PLUS || code == MINUS)
6299 if (code != PLUS && code != MINUS)
6305 /* These are also multiplies, so they distribute over everything. */
6309 /* Non-paradoxical SUBREGs distributes over all operations, provided
6310 the inner modes and word numbers are the same, this is an extraction
6311 of a low-order part, we don't convert an fp operation to int or
6312 vice versa, and we would not be converting a single-word
6313 operation into a multi-word operation. The latter test is not
6314 required, but it prevents generating unneeded multi-word operations.
6315 Some of the previous tests are redundant given the latter test, but
6316 are retained because they are required for correctness.
6318 We produce the result slightly differently in this case. */
6320 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6321 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6322 || ! subreg_lowpart_p (lhs)
6323 || (GET_MODE_CLASS (GET_MODE (lhs))
6324 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6325 || (GET_MODE_SIZE (GET_MODE (lhs))
6326 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6327 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6330 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6331 SUBREG_REG (lhs), SUBREG_REG (rhs));
6332 return gen_lowpart_for_combine (GET_MODE (x), tem);
6338 /* Set LHS and RHS to the inner operands (A and B in the example
6339 above) and set OTHER to the common operand (C in the example).
6340 These is only one way to do this unless the inner operation is
6342 if (GET_RTX_CLASS (inner_code) == 'c'
6343 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6344 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6345 else if (GET_RTX_CLASS (inner_code) == 'c'
6346 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6347 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6348 else if (GET_RTX_CLASS (inner_code) == 'c'
6349 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6350 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6351 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6352 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
6356 /* Form the new inner operation, seeing if it simplifies first. */
6357 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
6359 /* There is one exception to the general way of distributing:
6360 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6361 if (code == XOR && inner_code == IOR)
6364 other = gen_unary (NOT, GET_MODE (x), other);
6367 /* We may be able to continuing distributing the result, so call
6368 ourselves recursively on the inner operation before forming the
6369 outer operation, which we return. */
6370 return gen_binary (inner_code, GET_MODE (x),
6371 apply_distributive_law (tem), other);
6374 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6377 Return an equivalent form, if different from X. Otherwise, return X. If
6378 X is zero, we are to always construct the equivalent form. */
6381 simplify_and_const_int (x, mode, varop, constop)
6383 enum machine_mode mode;
6385 unsigned HOST_WIDE_INT constop;
6387 register enum machine_mode tmode;
6389 unsigned HOST_WIDE_INT nonzero;
6392 /* Simplify VAROP knowing that we will be only looking at some of the
6394 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
6396 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6397 CONST_INT, we are done. */
6398 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
6401 /* See what bits may be nonzero in VAROP. Unlike the general case of
6402 a call to nonzero_bits, here we don't care about bits outside
6405 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6407 /* Turn off all bits in the constant that are known to already be zero.
6408 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6409 which is tested below. */
6413 /* If we don't have any bits left, return zero. */
6417 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
6418 a power of two, we can replace this with a ASHIFT. */
6419 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
6420 && (i = exact_log2 (constop)) >= 0)
6421 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
6423 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
6424 or XOR, then try to apply the distributive law. This may eliminate
6425 operations if either branch can be simplified because of the AND.
6426 It may also make some cases more complex, but those cases probably
6427 won't match a pattern either with or without this. */
6429 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
6431 gen_lowpart_for_combine
6433 apply_distributive_law
6434 (gen_binary (GET_CODE (varop), GET_MODE (varop),
6435 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6436 XEXP (varop, 0), constop),
6437 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6438 XEXP (varop, 1), constop))));
6440 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6441 if we already had one (just check for the simplest cases). */
6442 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6443 && GET_MODE (XEXP (x, 0)) == mode
6444 && SUBREG_REG (XEXP (x, 0)) == varop)
6445 varop = XEXP (x, 0);
6447 varop = gen_lowpart_for_combine (mode, varop);
6449 /* If we can't make the SUBREG, try to return what we were given. */
6450 if (GET_CODE (varop) == CLOBBER)
6451 return x ? x : varop;
6453 /* If we are only masking insignificant bits, return VAROP. */
6454 if (constop == nonzero)
6457 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6458 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6459 x = gen_binary (AND, mode, varop, GEN_INT (constop));
6463 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6464 || INTVAL (XEXP (x, 1)) != constop)
6465 SUBST (XEXP (x, 1), GEN_INT (constop));
6467 SUBST (XEXP (x, 0), varop);
6473 /* Given an expression, X, compute which bits in X can be non-zero.
6474 We don't care about bits outside of those defined in MODE.
6476 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6477 a shift, AND, or zero_extract, we can do better. */
6479 static unsigned HOST_WIDE_INT
6480 nonzero_bits (x, mode)
6482 enum machine_mode mode;
6484 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6485 unsigned HOST_WIDE_INT inner_nz;
6487 int mode_width = GET_MODE_BITSIZE (mode);
6490 /* If X is wider than MODE, use its mode instead. */
6491 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6493 mode = GET_MODE (x);
6494 nonzero = GET_MODE_MASK (mode);
6495 mode_width = GET_MODE_BITSIZE (mode);
6498 if (mode_width > HOST_BITS_PER_WIDE_INT)
6499 /* Our only callers in this case look for single bit values. So
6500 just return the mode mask. Those tests will then be false. */
6503 #ifndef WORD_REGISTER_OPERATIONS
6504 /* If MODE is wider than X, but both are a single word for both the host
6505 and target machines, we can compute this from which bits of the
6506 object might be nonzero in its own mode, taking into account the fact
6507 that on many CISC machines, accessing an object in a wider mode
6508 causes the high-order bits to become undefined. So they are
6509 not known to be zero. */
6511 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
6512 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
6513 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6514 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
6516 nonzero &= nonzero_bits (x, GET_MODE (x));
6517 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
6522 code = GET_CODE (x);
6526 #ifdef STACK_BOUNDARY
6527 /* If this is the stack pointer, we may know something about its
6528 alignment. If PUSH_ROUNDING is defined, it is possible for the
6529 stack to be momentarily aligned only to that amount, so we pick
6530 the least alignment. */
6532 if (x == stack_pointer_rtx)
6534 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6536 #ifdef PUSH_ROUNDING
6537 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6540 return nonzero & ~ (sp_alignment - 1);
6544 /* If X is a register whose nonzero bits value is current, use it.
6545 Otherwise, if X is a register whose value we can find, use that
6546 value. Otherwise, use the previously-computed global nonzero bits
6547 for this register. */
6549 if (reg_last_set_value[REGNO (x)] != 0
6550 && reg_last_set_mode[REGNO (x)] == mode
6551 && (reg_n_sets[REGNO (x)] == 1
6552 || reg_last_set_label[REGNO (x)] == label_tick)
6553 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6554 return reg_last_set_nonzero_bits[REGNO (x)];
6556 tem = get_last_value (x);
6560 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6561 /* If X is narrower than MODE and TEM is a non-negative
6562 constant that would appear negative in the mode of X,
6563 sign-extend it for use in reg_nonzero_bits because some
6564 machines (maybe most) will actually do the sign-extension
6565 and this is the conservative approach.
6567 ??? For 2.5, try to tighten up the MD files in this regard
6568 instead of this kludge. */
6570 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
6571 && GET_CODE (tem) == CONST_INT
6573 && 0 != (INTVAL (tem)
6574 & ((HOST_WIDE_INT) 1
6575 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6576 tem = GEN_INT (INTVAL (tem)
6577 | ((HOST_WIDE_INT) (-1)
6578 << GET_MODE_BITSIZE (GET_MODE (x))));
6580 return nonzero_bits (tem, mode);
6582 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
6583 return reg_nonzero_bits[REGNO (x)] & nonzero;
6588 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6589 /* If X is negative in MODE, sign-extend the value. */
6590 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
6591 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
6592 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
6598 #ifdef LOAD_EXTEND_OP
6599 /* In many, if not most, RISC machines, reading a byte from memory
6600 zeros the rest of the register. Noticing that fact saves a lot
6601 of extra zero-extends. */
6602 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
6603 nonzero &= GET_MODE_MASK (GET_MODE (x));
6613 /* If this produces an integer result, we know which bits are set.
6614 Code here used to clear bits outside the mode of X, but that is
6617 if (GET_MODE_CLASS (mode) == MODE_INT
6618 && mode_width <= HOST_BITS_PER_WIDE_INT)
6619 nonzero = STORE_FLAG_VALUE;
6623 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6624 == GET_MODE_BITSIZE (GET_MODE (x)))
6627 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6628 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6632 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6633 == GET_MODE_BITSIZE (GET_MODE (x)))
6638 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6642 nonzero &= nonzero_bits (XEXP (x, 0), mode);
6643 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6644 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6648 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6649 Otherwise, show all the bits in the outer mode but not the inner
6651 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6652 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6654 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6657 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6658 inner_nz |= (GET_MODE_MASK (mode)
6659 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6662 nonzero &= inner_nz;
6666 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6667 & nonzero_bits (XEXP (x, 1), mode));
6671 case UMIN: case UMAX: case SMIN: case SMAX:
6672 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6673 | nonzero_bits (XEXP (x, 1), mode));
6676 case PLUS: case MINUS:
6678 case DIV: case UDIV:
6679 case MOD: case UMOD:
6680 /* We can apply the rules of arithmetic to compute the number of
6681 high- and low-order zero bits of these operations. We start by
6682 computing the width (position of the highest-order non-zero bit)
6683 and the number of low-order zero bits for each value. */
6685 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
6686 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
6687 int width0 = floor_log2 (nz0) + 1;
6688 int width1 = floor_log2 (nz1) + 1;
6689 int low0 = floor_log2 (nz0 & -nz0);
6690 int low1 = floor_log2 (nz1 & -nz1);
6691 int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6692 int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6693 int result_width = mode_width;
6699 result_width = MAX (width0, width1) + 1;
6700 result_low = MIN (low0, low1);
6703 result_low = MIN (low0, low1);
6706 result_width = width0 + width1;
6707 result_low = low0 + low1;
6710 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6711 result_width = width0;
6714 result_width = width0;
6717 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6718 result_width = MIN (width0, width1);
6719 result_low = MIN (low0, low1);
6722 result_width = MIN (width0, width1);
6723 result_low = MIN (low0, low1);
6727 if (result_width < mode_width)
6728 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6731 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6736 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6737 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6738 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6742 /* If this is a SUBREG formed for a promoted variable that has
6743 been zero-extended, we know that at least the high-order bits
6744 are zero, though others might be too. */
6746 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6747 nonzero = (GET_MODE_MASK (GET_MODE (x))
6748 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
6750 /* If the inner mode is a single word for both the host and target
6751 machines, we can compute this from which bits of the inner
6752 object might be nonzero. */
6753 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6754 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6755 <= HOST_BITS_PER_WIDE_INT))
6757 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
6759 #ifndef WORD_REGISTER_OPERATIONS
6760 /* On many CISC machines, accessing an object in a wider mode
6761 causes the high-order bits to become undefined. So they are
6762 not known to be zero. */
6763 if (GET_MODE_SIZE (GET_MODE (x))
6764 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6765 nonzero |= (GET_MODE_MASK (GET_MODE (x))
6766 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6776 /* The nonzero bits are in two classes: any bits within MODE
6777 that aren't in GET_MODE (x) are always significant. The rest of the
6778 nonzero bits are those that are significant in the operand of
6779 the shift when shifted the appropriate number of bits. This
6780 shows that high-order bits are cleared by the right shift and
6781 low-order bits by left shifts. */
6782 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6783 && INTVAL (XEXP (x, 1)) >= 0
6784 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6786 enum machine_mode inner_mode = GET_MODE (x);
6787 int width = GET_MODE_BITSIZE (inner_mode);
6788 int count = INTVAL (XEXP (x, 1));
6789 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6790 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
6791 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
6792 unsigned HOST_WIDE_INT outer = 0;
6794 if (mode_width > width)
6795 outer = (op_nonzero & nonzero & ~ mode_mask);
6797 if (code == LSHIFTRT)
6799 else if (code == ASHIFTRT)
6803 /* If the sign bit may have been nonzero before the shift, we
6804 need to mark all the places it could have been copied to
6805 by the shift as possibly nonzero. */
6806 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6807 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6809 else if (code == LSHIFT || code == ASHIFT)
6812 inner = ((inner << (count % width)
6813 | (inner >> (width - (count % width)))) & mode_mask);
6815 nonzero &= (outer | inner);
6820 /* This is at most the number of bits in the mode. */
6821 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6825 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
6826 | nonzero_bits (XEXP (x, 2), mode));
6833 /* Return the number of bits at the high-order end of X that are known to
6834 be equal to the sign bit. X will be used in mode MODE; if MODE is
6835 VOIDmode, X will be used in its own mode. The returned value will always
6836 be between 1 and the number of bits in MODE. */
6839 num_sign_bit_copies (x, mode)
6841 enum machine_mode mode;
6843 enum rtx_code code = GET_CODE (x);
6845 int num0, num1, result;
6846 unsigned HOST_WIDE_INT nonzero;
6849 /* If we weren't given a mode, use the mode of X. If the mode is still
6850 VOIDmode, we don't know anything. */
6852 if (mode == VOIDmode)
6853 mode = GET_MODE (x);
6855 if (mode == VOIDmode)
6858 bitwidth = GET_MODE_BITSIZE (mode);
6860 /* For a smaller object, just ignore the high bits. */
6861 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
6862 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
6863 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
6869 if (reg_last_set_value[REGNO (x)] != 0
6870 && reg_last_set_mode[REGNO (x)] == mode
6871 && (reg_n_sets[REGNO (x)] == 1
6872 || reg_last_set_label[REGNO (x)] == label_tick)
6873 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6874 return reg_last_set_sign_bit_copies[REGNO (x)];
6876 tem = get_last_value (x);
6878 return num_sign_bit_copies (tem, mode);
6880 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6881 return reg_sign_bit_copies[REGNO (x)];
6885 #ifdef LOAD_EXTEND_OP
6886 /* Some RISC machines sign-extend all loads of smaller than a word. */
6887 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
6888 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6893 /* If the constant is negative, take its 1's complement and remask.
6894 Then see how many zero bits we have. */
6895 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
6896 if (bitwidth <= HOST_BITS_PER_WIDE_INT
6897 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6898 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
6900 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
6903 /* If this is a SUBREG for a promoted object that is sign-extended
6904 and we are looking at it in a wider mode, we know that at least the
6905 high-order bits are known to be sign bit copies. */
6907 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6908 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
6909 num_sign_bit_copies (SUBREG_REG (x), mode));
6911 /* For a smaller object, just ignore the high bits. */
6912 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6914 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6915 return MAX (1, (num0
6916 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6920 #ifdef WORD_REGISTER_OPERATIONS
6921 /* For paradoxical SUBREGs on machines where all register operations
6922 affect the entire register, just look inside. Note that we are
6923 passing MODE to the recursive call, so the number of sign bit copies
6924 will remain relative to that mode, not the inner mode. */
6926 if (GET_MODE_SIZE (GET_MODE (x))
6927 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6928 return num_sign_bit_copies (SUBREG_REG (x), mode);
6933 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6934 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6938 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6939 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6942 /* For a smaller object, just ignore the high bits. */
6943 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6944 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6948 return num_sign_bit_copies (XEXP (x, 0), mode);
6950 case ROTATE: case ROTATERT:
6951 /* If we are rotating left by a number of bits less than the number
6952 of sign bit copies, we can just subtract that amount from the
6954 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6955 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6957 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6958 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6959 : bitwidth - INTVAL (XEXP (x, 1))));
6964 /* In general, this subtracts one sign bit copy. But if the value
6965 is known to be positive, the number of sign bit copies is the
6966 same as that of the input. Finally, if the input has just one bit
6967 that might be nonzero, all the bits are copies of the sign bit. */
6968 nonzero = nonzero_bits (XEXP (x, 0), mode);
6972 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6974 && bitwidth <= HOST_BITS_PER_WIDE_INT
6975 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
6980 case IOR: case AND: case XOR:
6981 case SMIN: case SMAX: case UMIN: case UMAX:
6982 /* Logical operations will preserve the number of sign-bit copies.
6983 MIN and MAX operations always return one of the operands. */
6984 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6985 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6986 return MIN (num0, num1);
6988 case PLUS: case MINUS:
6989 /* For addition and subtraction, we can have a 1-bit carry. However,
6990 if we are subtracting 1 from a positive number, there will not
6991 be such a carry. Furthermore, if the positive number is known to
6992 be 0 or 1, we know the result is either -1 or 0. */
6994 if (code == PLUS && XEXP (x, 1) == constm1_rtx
6995 && bitwidth <= HOST_BITS_PER_WIDE_INT)
6997 nonzero = nonzero_bits (XEXP (x, 0), mode);
6998 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
6999 return (nonzero == 1 || nonzero == 0 ? bitwidth
7000 : bitwidth - floor_log2 (nonzero) - 1);
7003 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7004 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7005 return MAX (1, MIN (num0, num1) - 1);
7008 /* The number of bits of the product is the sum of the number of
7009 bits of both terms. However, unless one of the terms if known
7010 to be positive, we must allow for an additional bit since negating
7011 a negative number can remove one sign bit copy. */
7013 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7014 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7016 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7018 && bitwidth <= HOST_BITS_PER_WIDE_INT
7019 && ((nonzero_bits (XEXP (x, 0), mode)
7020 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7021 && (nonzero_bits (XEXP (x, 1), mode)
7022 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
7025 return MAX (1, result);
7028 /* The result must be <= the first operand. */
7029 return num_sign_bit_copies (XEXP (x, 0), mode);
7032 /* The result must be <= the scond operand. */
7033 return num_sign_bit_copies (XEXP (x, 1), mode);
7036 /* Similar to unsigned division, except that we have to worry about
7037 the case where the divisor is negative, in which case we have
7039 result = num_sign_bit_copies (XEXP (x, 0), mode);
7041 && bitwidth <= HOST_BITS_PER_WIDE_INT
7042 && (nonzero_bits (XEXP (x, 1), mode)
7043 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7049 result = num_sign_bit_copies (XEXP (x, 1), mode);
7051 && bitwidth <= HOST_BITS_PER_WIDE_INT
7052 && (nonzero_bits (XEXP (x, 1), mode)
7053 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7059 /* Shifts by a constant add to the number of bits equal to the
7061 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7062 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7063 && INTVAL (XEXP (x, 1)) > 0)
7064 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7070 /* Left shifts destroy copies. */
7071 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7072 || INTVAL (XEXP (x, 1)) < 0
7073 || INTVAL (XEXP (x, 1)) >= bitwidth)
7076 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7077 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7080 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7081 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7082 return MIN (num0, num1);
7084 #if STORE_FLAG_VALUE == -1
7085 case EQ: case NE: case GE: case GT: case LE: case LT:
7086 case GEU: case GTU: case LEU: case LTU:
7091 /* If we haven't been able to figure it out by one of the above rules,
7092 see if some of the high-order bits are known to be zero. If so,
7093 count those bits and return one less than that amount. If we can't
7094 safely compute the mask for this mode, always return BITWIDTH. */
7096 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7099 nonzero = nonzero_bits (x, mode);
7100 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7101 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7104 /* Return the number of "extended" bits there are in X, when interpreted
7105 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7106 unsigned quantities, this is the number of high-order zero bits.
7107 For signed quantities, this is the number of copies of the sign bit
7108 minus 1. In both case, this function returns the number of "spare"
7109 bits. For example, if two quantities for which this function returns
7110 at least 1 are added, the addition is known not to overflow.
7112 This function will always return 0 unless called during combine, which
7113 implies that it must be called from a define_split. */
7116 extended_count (x, mode, unsignedp)
7118 enum machine_mode mode;
7121 if (nonzero_sign_valid == 0)
7125 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7126 && (GET_MODE_BITSIZE (mode) - 1
7127 - floor_log2 (nonzero_bits (x, mode))))
7128 : num_sign_bit_copies (x, mode) - 1);
7131 /* This function is called from `simplify_shift_const' to merge two
7132 outer operations. Specifically, we have already found that we need
7133 to perform operation *POP0 with constant *PCONST0 at the outermost
7134 position. We would now like to also perform OP1 with constant CONST1
7135 (with *POP0 being done last).
7137 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7138 the resulting operation. *PCOMP_P is set to 1 if we would need to
7139 complement the innermost operand, otherwise it is unchanged.
7141 MODE is the mode in which the operation will be done. No bits outside
7142 the width of this mode matter. It is assumed that the width of this mode
7143 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7145 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7146 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7147 result is simply *PCONST0.
7149 If the resulting operation cannot be expressed as one operation, we
7150 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7153 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7154 enum rtx_code *pop0;
7155 HOST_WIDE_INT *pconst0;
7157 HOST_WIDE_INT const1;
7158 enum machine_mode mode;
7161 enum rtx_code op0 = *pop0;
7162 HOST_WIDE_INT const0 = *pconst0;
7164 const0 &= GET_MODE_MASK (mode);
7165 const1 &= GET_MODE_MASK (mode);
7167 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7171 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7174 if (op1 == NIL || op0 == SET)
7177 else if (op0 == NIL)
7178 op0 = op1, const0 = const1;
7180 else if (op0 == op1)
7202 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7203 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7206 /* If the two constants aren't the same, we can't do anything. The
7207 remaining six cases can all be done. */
7208 else if (const0 != const1)
7216 /* (a & b) | b == b */
7218 else /* op1 == XOR */
7219 /* (a ^ b) | b == a | b */
7225 /* (a & b) ^ b == (~a) & b */
7226 op0 = AND, *pcomp_p = 1;
7227 else /* op1 == IOR */
7228 /* (a | b) ^ b == a & ~b */
7229 op0 = AND, *pconst0 = ~ const0;
7234 /* (a | b) & b == b */
7236 else /* op1 == XOR */
7237 /* (a ^ b) & b) == (~a) & b */
7242 /* Check for NO-OP cases. */
7243 const0 &= GET_MODE_MASK (mode);
7245 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7247 else if (const0 == 0 && op0 == AND)
7249 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7258 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7259 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7260 that we started with.
7262 The shift is normally computed in the widest mode we find in VAROP, as
7263 long as it isn't a different number of words than RESULT_MODE. Exceptions
7264 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7267 simplify_shift_const (x, code, result_mode, varop, count)
7270 enum machine_mode result_mode;
7274 enum rtx_code orig_code = code;
7275 int orig_count = count;
7276 enum machine_mode mode = result_mode;
7277 enum machine_mode shift_mode, tmode;
7279 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7280 /* We form (outer_op (code varop count) (outer_const)). */
7281 enum rtx_code outer_op = NIL;
7282 HOST_WIDE_INT outer_const = 0;
7284 int complement_p = 0;
7287 /* If we were given an invalid count, don't do anything except exactly
7288 what was requested. */
7290 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7295 return gen_rtx (code, mode, varop, GEN_INT (count));
7298 /* Unless one of the branches of the `if' in this loop does a `continue',
7299 we will `break' the loop after the `if'. */
7303 /* If we have an operand of (clobber (const_int 0)), just return that
7305 if (GET_CODE (varop) == CLOBBER)
7308 /* If we discovered we had to complement VAROP, leave. Making a NOT
7309 here would cause an infinite loop. */
7313 /* Convert ROTATETRT to ROTATE. */
7314 if (code == ROTATERT)
7315 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7317 /* Canonicalize LSHIFT to ASHIFT. */
7321 /* We need to determine what mode we will do the shift in. If the
7322 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
7323 was originally done in. Otherwise, we can do it in MODE, the widest
7324 mode encountered. */
7325 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7327 /* Handle cases where the count is greater than the size of the mode
7328 minus 1. For ASHIFT, use the size minus one as the count (this can
7329 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7330 take the count modulo the size. For other shifts, the result is
7333 Since these shifts are being produced by the compiler by combining
7334 multiple operations, each of which are defined, we know what the
7335 result is supposed to be. */
7337 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
7339 if (code == ASHIFTRT)
7340 count = GET_MODE_BITSIZE (shift_mode) - 1;
7341 else if (code == ROTATE || code == ROTATERT)
7342 count %= GET_MODE_BITSIZE (shift_mode);
7345 /* We can't simply return zero because there may be an
7353 /* Negative counts are invalid and should not have been made (a
7354 programmer-specified negative count should have been handled
7359 /* An arithmetic right shift of a quantity known to be -1 or 0
7361 if (code == ASHIFTRT
7362 && (num_sign_bit_copies (varop, shift_mode)
7363 == GET_MODE_BITSIZE (shift_mode)))
7369 /* If we are doing an arithmetic right shift and discarding all but
7370 the sign bit copies, this is equivalent to doing a shift by the
7371 bitsize minus one. Convert it into that shift because it will often
7372 allow other simplifications. */
7374 if (code == ASHIFTRT
7375 && (count + num_sign_bit_copies (varop, shift_mode)
7376 >= GET_MODE_BITSIZE (shift_mode)))
7377 count = GET_MODE_BITSIZE (shift_mode) - 1;
7379 /* We simplify the tests below and elsewhere by converting
7380 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7381 `make_compound_operation' will convert it to a ASHIFTRT for
7382 those machines (such as Vax) that don't have a LSHIFTRT. */
7383 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
7385 && ((nonzero_bits (varop, shift_mode)
7386 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
7390 switch (GET_CODE (varop))
7396 new = expand_compound_operation (varop);
7405 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7406 minus the width of a smaller mode, we can do this with a
7407 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7408 if ((code == ASHIFTRT || code == LSHIFTRT)
7409 && ! mode_dependent_address_p (XEXP (varop, 0))
7410 && ! MEM_VOLATILE_P (varop)
7411 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7412 MODE_INT, 1)) != BLKmode)
7414 #if BYTES_BIG_ENDIAN
7415 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
7417 new = gen_rtx (MEM, tmode,
7418 plus_constant (XEXP (varop, 0),
7419 count / BITS_PER_UNIT));
7420 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7421 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7422 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7424 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7425 : ZERO_EXTEND, mode, new);
7432 /* Similar to the case above, except that we can only do this if
7433 the resulting mode is the same as that of the underlying
7434 MEM and adjust the address depending on the *bits* endianness
7435 because of the way that bit-field extract insns are defined. */
7436 if ((code == ASHIFTRT || code == LSHIFTRT)
7437 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7438 MODE_INT, 1)) != BLKmode
7439 && tmode == GET_MODE (XEXP (varop, 0)))
7442 new = XEXP (varop, 0);
7444 new = copy_rtx (XEXP (varop, 0));
7445 SUBST (XEXP (new, 0),
7446 plus_constant (XEXP (new, 0),
7447 count / BITS_PER_UNIT));
7450 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7451 : ZERO_EXTEND, mode, new);
7458 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7459 the same number of words as what we've seen so far. Then store
7460 the widest mode in MODE. */
7461 if (subreg_lowpart_p (varop)
7462 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7463 > GET_MODE_SIZE (GET_MODE (varop)))
7464 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7465 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7468 varop = SUBREG_REG (varop);
7469 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
7470 mode = GET_MODE (varop);
7476 /* Some machines use MULT instead of ASHIFT because MULT
7477 is cheaper. But it is still better on those machines to
7478 merge two shifts into one. */
7479 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7480 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7482 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
7483 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
7489 /* Similar, for when divides are cheaper. */
7490 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7491 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7493 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
7494 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
7500 /* If we are extracting just the sign bit of an arithmetic right
7501 shift, that shift is not needed. */
7502 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
7504 varop = XEXP (varop, 0);
7508 /* ... fall through ... */
7514 /* Here we have two nested shifts. The result is usually the
7515 AND of a new shift with a mask. We compute the result below. */
7516 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7517 && INTVAL (XEXP (varop, 1)) >= 0
7518 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
7519 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7520 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
7522 enum rtx_code first_code = GET_CODE (varop);
7523 int first_count = INTVAL (XEXP (varop, 1));
7524 unsigned HOST_WIDE_INT mask;
7528 if (first_code == LSHIFT)
7529 first_code = ASHIFT;
7531 /* We have one common special case. We can't do any merging if
7532 the inner code is an ASHIFTRT of a smaller mode. However, if
7533 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
7534 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
7535 we can convert it to
7536 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
7537 This simplifies certain SIGN_EXTEND operations. */
7538 if (code == ASHIFT && first_code == ASHIFTRT
7539 && (GET_MODE_BITSIZE (result_mode)
7540 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
7542 /* C3 has the low-order C1 bits zero. */
7544 mask = (GET_MODE_MASK (mode)
7545 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
7547 varop = simplify_and_const_int (NULL_RTX, result_mode,
7548 XEXP (varop, 0), mask);
7549 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
7551 count = first_count;
7556 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
7557 than C1 high-order bits equal to the sign bit, we can convert
7558 this to either an ASHIFT or a ASHIFTRT depending on the
7561 We cannot do this if VAROP's mode is not SHIFT_MODE. */
7563 if (code == ASHIFTRT && first_code == ASHIFT
7564 && GET_MODE (varop) == shift_mode
7565 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
7568 count -= first_count;
7570 count = - count, code = ASHIFT;
7571 varop = XEXP (varop, 0);
7575 /* There are some cases we can't do. If CODE is ASHIFTRT,
7576 we can only do this if FIRST_CODE is also ASHIFTRT.
7578 We can't do the case when CODE is ROTATE and FIRST_CODE is
7581 If the mode of this shift is not the mode of the outer shift,
7582 we can't do this if either shift is ASHIFTRT or ROTATE.
7584 Finally, we can't do any of these if the mode is too wide
7585 unless the codes are the same.
7587 Handle the case where the shift codes are the same
7590 if (code == first_code)
7592 if (GET_MODE (varop) != result_mode
7593 && (code == ASHIFTRT || code == ROTATE))
7596 count += first_count;
7597 varop = XEXP (varop, 0);
7601 if (code == ASHIFTRT
7602 || (code == ROTATE && first_code == ASHIFTRT)
7603 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
7604 || (GET_MODE (varop) != result_mode
7605 && (first_code == ASHIFTRT || first_code == ROTATE
7606 || code == ROTATE)))
7609 /* To compute the mask to apply after the shift, shift the
7610 nonzero bits of the inner shift the same way the
7611 outer shift will. */
7613 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
7616 = simplify_binary_operation (code, result_mode, mask_rtx,
7619 /* Give up if we can't compute an outer operation to use. */
7621 || GET_CODE (mask_rtx) != CONST_INT
7622 || ! merge_outer_ops (&outer_op, &outer_const, AND,
7624 result_mode, &complement_p))
7627 /* If the shifts are in the same direction, we add the
7628 counts. Otherwise, we subtract them. */
7629 if ((code == ASHIFTRT || code == LSHIFTRT)
7630 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
7631 count += first_count;
7633 count -= first_count;
7635 /* If COUNT is positive, the new shift is usually CODE,
7636 except for the two exceptions below, in which case it is
7637 FIRST_CODE. If the count is negative, FIRST_CODE should
7640 && ((first_code == ROTATE && code == ASHIFT)
7641 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7644 code = first_code, count = - count;
7646 varop = XEXP (varop, 0);
7650 /* If we have (A << B << C) for any shift, we can convert this to
7651 (A << C << B). This wins if A is a constant. Only try this if
7652 B is not a constant. */
7654 else if (GET_CODE (varop) == code
7655 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7657 = simplify_binary_operation (code, mode,
7661 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7668 /* Make this fit the case below. */
7669 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7670 GEN_INT (GET_MODE_MASK (mode)));
7676 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7677 with C the size of VAROP - 1 and the shift is logical if
7678 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7679 we have an (le X 0) operation. If we have an arithmetic shift
7680 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7681 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7683 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7684 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7685 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7686 && (code == LSHIFTRT || code == ASHIFTRT)
7687 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7688 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7691 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7694 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7695 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7700 /* If we have (shift (logical)), move the logical to the outside
7701 to allow it to possibly combine with another logical and the
7702 shift to combine with another shift. This also canonicalizes to
7703 what a ZERO_EXTRACT looks like. Also, some machines have
7704 (and (shift)) insns. */
7706 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7707 && (new = simplify_binary_operation (code, result_mode,
7709 GEN_INT (count))) != 0
7710 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7711 INTVAL (new), result_mode, &complement_p))
7713 varop = XEXP (varop, 0);
7717 /* If we can't do that, try to simplify the shift in each arm of the
7718 logical expression, make a new logical expression, and apply
7719 the inverse distributive law. */
7721 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
7722 XEXP (varop, 0), count);
7723 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
7724 XEXP (varop, 1), count);
7726 varop = gen_binary (GET_CODE (varop), GET_MODE (varop), lhs, rhs);
7727 varop = apply_distributive_law (varop);
7734 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7735 says that the sign bit can be tested, FOO has mode MODE, C is
7736 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7739 && XEXP (varop, 1) == const0_rtx
7740 && GET_MODE (XEXP (varop, 0)) == result_mode
7741 && count == GET_MODE_BITSIZE (result_mode) - 1
7742 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7743 && ((STORE_FLAG_VALUE
7744 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7745 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7746 && merge_outer_ops (&outer_op, &outer_const, XOR,
7747 (HOST_WIDE_INT) 1, result_mode,
7750 varop = XEXP (varop, 0);
7757 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7758 than the number of bits in the mode is equivalent to A. */
7759 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7760 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
7762 varop = XEXP (varop, 0);
7767 /* NEG commutes with ASHIFT since it is multiplication. Move the
7768 NEG outside to allow shifts to combine. */
7770 && merge_outer_ops (&outer_op, &outer_const, NEG,
7771 (HOST_WIDE_INT) 0, result_mode,
7774 varop = XEXP (varop, 0);
7780 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7781 is one less than the number of bits in the mode is
7782 equivalent to (xor A 1). */
7783 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7784 && XEXP (varop, 1) == constm1_rtx
7785 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7786 && merge_outer_ops (&outer_op, &outer_const, XOR,
7787 (HOST_WIDE_INT) 1, result_mode,
7791 varop = XEXP (varop, 0);
7795 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7796 that might be nonzero in BAR are those being shifted out and those
7797 bits are known zero in FOO, we can replace the PLUS with FOO.
7798 Similarly in the other operand order. This code occurs when
7799 we are computing the size of a variable-size array. */
7801 if ((code == ASHIFTRT || code == LSHIFTRT)
7802 && count < HOST_BITS_PER_WIDE_INT
7803 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
7804 && (nonzero_bits (XEXP (varop, 1), result_mode)
7805 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
7807 varop = XEXP (varop, 0);
7810 else if ((code == ASHIFTRT || code == LSHIFTRT)
7811 && count < HOST_BITS_PER_WIDE_INT
7812 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7813 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7815 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7816 & nonzero_bits (XEXP (varop, 1),
7819 varop = XEXP (varop, 1);
7823 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7825 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7826 && (new = simplify_binary_operation (ASHIFT, result_mode,
7828 GEN_INT (count))) != 0
7829 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7830 INTVAL (new), result_mode, &complement_p))
7832 varop = XEXP (varop, 0);
7838 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7839 with C the size of VAROP - 1 and the shift is logical if
7840 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7841 we have a (gt X 0) operation. If the shift is arithmetic with
7842 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7843 we have a (neg (gt X 0)) operation. */
7845 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7846 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7847 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7848 && (code == LSHIFTRT || code == ASHIFTRT)
7849 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7850 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7851 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7854 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7857 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7858 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7868 /* We need to determine what mode to do the shift in. If the shift is
7869 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7870 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7871 The code we care about is that of the shift that will actually be done,
7872 not the shift that was originally requested. */
7873 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7875 /* We have now finished analyzing the shift. The result should be
7876 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7877 OUTER_OP is non-NIL, it is an operation that needs to be applied
7878 to the result of the shift. OUTER_CONST is the relevant constant,
7879 but we must turn off all bits turned off in the shift.
7881 If we were passed a value for X, see if we can use any pieces of
7882 it. If not, make new rtx. */
7884 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7885 && GET_CODE (XEXP (x, 1)) == CONST_INT
7886 && INTVAL (XEXP (x, 1)) == count)
7887 const_rtx = XEXP (x, 1);
7889 const_rtx = GEN_INT (count);
7891 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7892 && GET_MODE (XEXP (x, 0)) == shift_mode
7893 && SUBREG_REG (XEXP (x, 0)) == varop)
7894 varop = XEXP (x, 0);
7895 else if (GET_MODE (varop) != shift_mode)
7896 varop = gen_lowpart_for_combine (shift_mode, varop);
7898 /* If we can't make the SUBREG, try to return what we were given. */
7899 if (GET_CODE (varop) == CLOBBER)
7900 return x ? x : varop;
7902 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7907 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7908 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7910 SUBST (XEXP (x, 0), varop);
7911 SUBST (XEXP (x, 1), const_rtx);
7914 /* If we have an outer operation and we just made a shift, it is
7915 possible that we could have simplified the shift were it not
7916 for the outer operation. So try to do the simplification
7919 if (outer_op != NIL && GET_CODE (x) == code
7920 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7921 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
7922 INTVAL (XEXP (x, 1)));
7924 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7925 turn off all the bits that the shift would have turned off. */
7926 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7927 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7928 GET_MODE_MASK (result_mode) >> orig_count);
7930 /* Do the remainder of the processing in RESULT_MODE. */
7931 x = gen_lowpart_for_combine (result_mode, x);
7933 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7936 x = gen_unary (NOT, result_mode, x);
7938 if (outer_op != NIL)
7940 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7941 outer_const &= GET_MODE_MASK (result_mode);
7943 if (outer_op == AND)
7944 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7945 else if (outer_op == SET)
7946 /* This means that we have determined that the result is
7947 equivalent to a constant. This should be rare. */
7948 x = GEN_INT (outer_const);
7949 else if (GET_RTX_CLASS (outer_op) == '1')
7950 x = gen_unary (outer_op, result_mode, x);
7952 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7958 /* Like recog, but we receive the address of a pointer to a new pattern.
7959 We try to match the rtx that the pointer points to.
7960 If that fails, we may try to modify or replace the pattern,
7961 storing the replacement into the same pointer object.
7963 Modifications include deletion or addition of CLOBBERs.
7965 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7966 the CLOBBERs are placed.
7968 The value is the final insn code from the pattern ultimately matched,
7972 recog_for_combine (pnewpat, insn, pnotes)
7977 register rtx pat = *pnewpat;
7978 int insn_code_number;
7979 int num_clobbers_to_add = 0;
7983 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
7984 we use to indicate that something didn't match. If we find such a
7985 thing, force rejection. */
7986 if (GET_CODE (pat) == PARALLEL)
7987 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
7988 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
7989 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
7992 /* Is the result of combination a valid instruction? */
7993 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7995 /* If it isn't, there is the possibility that we previously had an insn
7996 that clobbered some register as a side effect, but the combined
7997 insn doesn't need to do that. So try once more without the clobbers
7998 unless this represents an ASM insn. */
8000 if (insn_code_number < 0 && ! check_asm_operands (pat)
8001 && GET_CODE (pat) == PARALLEL)
8005 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8006 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8009 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8013 SUBST_INT (XVECLEN (pat, 0), pos);
8016 pat = XVECEXP (pat, 0, 0);
8018 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8021 /* If we had any clobbers to add, make a new pattern than contains
8022 them. Then check to make sure that all of them are dead. */
8023 if (num_clobbers_to_add)
8025 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8026 gen_rtvec (GET_CODE (pat) == PARALLEL
8027 ? XVECLEN (pat, 0) + num_clobbers_to_add
8028 : num_clobbers_to_add + 1));
8030 if (GET_CODE (pat) == PARALLEL)
8031 for (i = 0; i < XVECLEN (pat, 0); i++)
8032 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8034 XVECEXP (newpat, 0, 0) = pat;
8036 add_clobbers (newpat, insn_code_number);
8038 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8039 i < XVECLEN (newpat, 0); i++)
8041 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8042 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8044 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8045 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8053 return insn_code_number;
8056 /* Like gen_lowpart but for use by combine. In combine it is not possible
8057 to create any new pseudoregs. However, it is safe to create
8058 invalid memory addresses, because combine will try to recognize
8059 them and all they will do is make the combine attempt fail.
8061 If for some reason this cannot do its job, an rtx
8062 (clobber (const_int 0)) is returned.
8063 An insn containing that will not be recognized. */
8068 gen_lowpart_for_combine (mode, x)
8069 enum machine_mode mode;
8074 if (GET_MODE (x) == mode)
8077 /* We can only support MODE being wider than a word if X is a
8078 constant integer or has a mode the same size. */
8080 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8081 && ! ((GET_MODE (x) == VOIDmode
8082 && (GET_CODE (x) == CONST_INT
8083 || GET_CODE (x) == CONST_DOUBLE))
8084 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8085 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8087 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8088 won't know what to do. So we will strip off the SUBREG here and
8089 process normally. */
8090 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8093 if (GET_MODE (x) == mode)
8097 result = gen_lowpart_common (mode, x);
8101 if (GET_CODE (x) == MEM)
8103 register int offset = 0;
8106 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8108 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8109 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8111 /* If we want to refer to something bigger than the original memref,
8112 generate a perverse subreg instead. That will force a reload
8113 of the original memref X. */
8114 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8115 return gen_rtx (SUBREG, mode, x, 0);
8117 #if WORDS_BIG_ENDIAN
8118 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8119 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8121 #if BYTES_BIG_ENDIAN
8122 /* Adjust the address so that the address-after-the-data
8124 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8125 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8127 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8128 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8129 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8130 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8134 /* If X is a comparison operator, rewrite it in a new mode. This
8135 probably won't match, but may allow further simplifications. */
8136 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8137 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8139 /* If we couldn't simplify X any other way, just enclose it in a
8140 SUBREG. Normally, this SUBREG won't match, but some patterns may
8141 include an explicit SUBREG or we may simplify it further in combine. */
8146 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8147 word = ((GET_MODE_SIZE (GET_MODE (x))
8148 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8150 return gen_rtx (SUBREG, mode, x, word);
8154 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8155 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8157 If the identical expression was previously in the insn (in the undobuf),
8158 it will be returned. Only if it is not found will a new expression
8163 gen_rtx_combine (va_alist)
8168 enum machine_mode mode;
8176 code = va_arg (p, enum rtx_code);
8177 mode = va_arg (p, enum machine_mode);
8178 n_args = GET_RTX_LENGTH (code);
8179 fmt = GET_RTX_FORMAT (code);
8181 if (n_args == 0 || n_args > 3)
8184 /* Get each arg and verify that it is supposed to be an expression. */
8185 for (j = 0; j < n_args; j++)
8190 args[j] = va_arg (p, rtx);
8193 /* See if this is in undobuf. Be sure we don't use objects that came
8194 from another insn; this could produce circular rtl structures. */
8196 for (i = previous_num_undos; i < undobuf.num_undo; i++)
8197 if (!undobuf.undo[i].is_int
8198 && GET_CODE (undobuf.undo[i].old_contents.r) == code
8199 && GET_MODE (undobuf.undo[i].old_contents.r) == mode)
8201 for (j = 0; j < n_args; j++)
8202 if (XEXP (undobuf.undo[i].old_contents.r, j) != args[j])
8206 return undobuf.undo[i].old_contents.r;
8209 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8210 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8211 rt = rtx_alloc (code);
8212 PUT_MODE (rt, mode);
8213 XEXP (rt, 0) = args[0];
8216 XEXP (rt, 1) = args[1];
8218 XEXP (rt, 2) = args[2];
8223 /* These routines make binary and unary operations by first seeing if they
8224 fold; if not, a new expression is allocated. */
8227 gen_binary (code, mode, op0, op1)
8229 enum machine_mode mode;
8235 if (GET_RTX_CLASS (code) == 'c'
8236 && (GET_CODE (op0) == CONST_INT
8237 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8238 tem = op0, op0 = op1, op1 = tem;
8240 if (GET_RTX_CLASS (code) == '<')
8242 enum machine_mode op_mode = GET_MODE (op0);
8243 if (op_mode == VOIDmode)
8244 op_mode = GET_MODE (op1);
8245 result = simplify_relational_operation (code, op_mode, op0, op1);
8248 result = simplify_binary_operation (code, mode, op0, op1);
8253 /* Put complex operands first and constants second. */
8254 if (GET_RTX_CLASS (code) == 'c'
8255 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8256 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8257 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8258 || (GET_CODE (op0) == SUBREG
8259 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8260 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8261 return gen_rtx_combine (code, mode, op1, op0);
8263 return gen_rtx_combine (code, mode, op0, op1);
8267 gen_unary (code, mode, op0)
8269 enum machine_mode mode;
8272 rtx result = simplify_unary_operation (code, mode, op0, mode);
8277 return gen_rtx_combine (code, mode, op0);
8280 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8281 comparison code that will be tested.
8283 The result is a possibly different comparison code to use. *POP0 and
8284 *POP1 may be updated.
8286 It is possible that we might detect that a comparison is either always
8287 true or always false. However, we do not perform general constant
8288 folding in combine, so this knowledge isn't useful. Such tautologies
8289 should have been detected earlier. Hence we ignore all such cases. */
8291 static enum rtx_code
8292 simplify_comparison (code, pop0, pop1)
8301 enum machine_mode mode, tmode;
8303 /* Try a few ways of applying the same transformation to both operands. */
8306 /* If both operands are the same constant shift, see if we can ignore the
8307 shift. We can if the shift is a rotate or if the bits shifted out of
8308 this shift are known to be zero for both inputs and if the type of
8309 comparison is compatible with the shift. */
8310 if (GET_CODE (op0) == GET_CODE (op1)
8311 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8312 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
8313 || ((GET_CODE (op0) == LSHIFTRT
8314 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
8315 && (code != GT && code != LT && code != GE && code != LE))
8316 || (GET_CODE (op0) == ASHIFTRT
8317 && (code != GTU && code != LTU
8318 && code != GEU && code != GEU)))
8319 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8320 && INTVAL (XEXP (op0, 1)) >= 0
8321 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8322 && XEXP (op0, 1) == XEXP (op1, 1))
8324 enum machine_mode mode = GET_MODE (op0);
8325 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8326 int shift_count = INTVAL (XEXP (op0, 1));
8328 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
8329 mask &= (mask >> shift_count) << shift_count;
8330 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
8331 mask = (mask & (mask << shift_count)) >> shift_count;
8333 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
8334 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
8335 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
8340 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8341 SUBREGs are of the same mode, and, in both cases, the AND would
8342 be redundant if the comparison was done in the narrower mode,
8343 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8344 and the operand's possibly nonzero bits are 0xffffff01; in that case
8345 if we only care about QImode, we don't need the AND). This case
8346 occurs if the output mode of an scc insn is not SImode and
8347 STORE_FLAG_VALUE == 1 (e.g., the 386). */
8349 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
8350 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8351 && GET_CODE (XEXP (op1, 1)) == CONST_INT
8352 && GET_CODE (XEXP (op0, 0)) == SUBREG
8353 && GET_CODE (XEXP (op1, 0)) == SUBREG
8354 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
8355 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
8356 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
8357 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8358 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8359 <= HOST_BITS_PER_WIDE_INT)
8360 && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)),
8361 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8362 & ~ INTVAL (XEXP (op0, 1))) == 0
8363 && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)),
8364 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8365 & ~ INTVAL (XEXP (op1, 1))) == 0)
8367 op0 = SUBREG_REG (XEXP (op0, 0));
8368 op1 = SUBREG_REG (XEXP (op1, 0));
8370 /* the resulting comparison is always unsigned since we masked off
8371 the original sign bit. */
8372 code = unsigned_condition (code);
8378 /* If the first operand is a constant, swap the operands and adjust the
8379 comparison code appropriately. */
8380 if (CONSTANT_P (op0))
8382 tem = op0, op0 = op1, op1 = tem;
8383 code = swap_condition (code);
8386 /* We now enter a loop during which we will try to simplify the comparison.
8387 For the most part, we only are concerned with comparisons with zero,
8388 but some things may really be comparisons with zero but not start
8389 out looking that way. */
8391 while (GET_CODE (op1) == CONST_INT)
8393 enum machine_mode mode = GET_MODE (op0);
8394 int mode_width = GET_MODE_BITSIZE (mode);
8395 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8396 int equality_comparison_p;
8397 int sign_bit_comparison_p;
8398 int unsigned_comparison_p;
8399 HOST_WIDE_INT const_op;
8401 /* We only want to handle integral modes. This catches VOIDmode,
8402 CCmode, and the floating-point modes. An exception is that we
8403 can handle VOIDmode if OP0 is a COMPARE or a comparison
8406 if (GET_MODE_CLASS (mode) != MODE_INT
8407 && ! (mode == VOIDmode
8408 && (GET_CODE (op0) == COMPARE
8409 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
8412 /* Get the constant we are comparing against and turn off all bits
8413 not on in our mode. */
8414 const_op = INTVAL (op1);
8415 if (mode_width <= HOST_BITS_PER_WIDE_INT)
8418 /* If we are comparing against a constant power of two and the value
8419 being compared can only have that single bit nonzero (e.g., it was
8420 `and'ed with that bit), we can replace this with a comparison
8423 && (code == EQ || code == NE || code == GE || code == GEU
8424 || code == LT || code == LTU)
8425 && mode_width <= HOST_BITS_PER_WIDE_INT
8426 && exact_log2 (const_op) >= 0
8427 && nonzero_bits (op0, mode) == const_op)
8429 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
8430 op1 = const0_rtx, const_op = 0;
8433 /* Similarly, if we are comparing a value known to be either -1 or
8434 0 with -1, change it to the opposite comparison against zero. */
8437 && (code == EQ || code == NE || code == GT || code == LE
8438 || code == GEU || code == LTU)
8439 && num_sign_bit_copies (op0, mode) == mode_width)
8441 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
8442 op1 = const0_rtx, const_op = 0;
8445 /* Do some canonicalizations based on the comparison code. We prefer
8446 comparisons against zero and then prefer equality comparisons.
8447 If we can reduce the size of a constant, we will do that too. */
8452 /* < C is equivalent to <= (C - 1) */
8456 op1 = GEN_INT (const_op);
8458 /* ... fall through to LE case below. */
8464 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
8468 op1 = GEN_INT (const_op);
8472 /* If we are doing a <= 0 comparison on a value known to have
8473 a zero sign bit, we can replace this with == 0. */
8474 else if (const_op == 0
8475 && mode_width <= HOST_BITS_PER_WIDE_INT
8476 && (nonzero_bits (op0, mode)
8477 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8482 /* >= C is equivalent to > (C - 1). */
8486 op1 = GEN_INT (const_op);
8488 /* ... fall through to GT below. */
8494 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
8498 op1 = GEN_INT (const_op);
8502 /* If we are doing a > 0 comparison on a value known to have
8503 a zero sign bit, we can replace this with != 0. */
8504 else if (const_op == 0
8505 && mode_width <= HOST_BITS_PER_WIDE_INT
8506 && (nonzero_bits (op0, mode)
8507 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8512 /* < C is equivalent to <= (C - 1). */
8516 op1 = GEN_INT (const_op);
8518 /* ... fall through ... */
8521 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
8522 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8524 const_op = 0, op1 = const0_rtx;
8532 /* unsigned <= 0 is equivalent to == 0 */
8536 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
8537 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8539 const_op = 0, op1 = const0_rtx;
8545 /* >= C is equivalent to < (C - 1). */
8549 op1 = GEN_INT (const_op);
8551 /* ... fall through ... */
8554 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
8555 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8557 const_op = 0, op1 = const0_rtx;
8564 /* unsigned > 0 is equivalent to != 0 */
8568 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
8569 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8571 const_op = 0, op1 = const0_rtx;
8577 /* Compute some predicates to simplify code below. */
8579 equality_comparison_p = (code == EQ || code == NE);
8580 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
8581 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
8584 /* If this is a sign bit comparison and we can do arithmetic in
8585 MODE, say that we will only be needing the sign bit of OP0. */
8586 if (sign_bit_comparison_p
8587 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8588 op0 = force_to_mode (op0, mode,
8590 << (GET_MODE_BITSIZE (mode) - 1)),
8593 /* Now try cases based on the opcode of OP0. If none of the cases
8594 does a "continue", we exit this loop immediately after the
8597 switch (GET_CODE (op0))
8600 /* If we are extracting a single bit from a variable position in
8601 a constant that has only a single bit set and are comparing it
8602 with zero, we can convert this into an equality comparison
8603 between the position and the location of the single bit. We can't
8604 do this if bit endian and we don't have an extzv since we then
8605 can't know what mode to use for the endianness adjustment. */
8607 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
8608 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
8609 && XEXP (op0, 1) == const1_rtx
8610 && equality_comparison_p && const_op == 0
8611 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
8614 i = (GET_MODE_BITSIZE
8615 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
8618 op0 = XEXP (op0, 2);
8622 /* Result is nonzero iff shift count is equal to I. */
8623 code = reverse_condition (code);
8628 /* ... fall through ... */
8631 tem = expand_compound_operation (op0);
8640 /* If testing for equality, we can take the NOT of the constant. */
8641 if (equality_comparison_p
8642 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
8644 op0 = XEXP (op0, 0);
8649 /* If just looking at the sign bit, reverse the sense of the
8651 if (sign_bit_comparison_p)
8653 op0 = XEXP (op0, 0);
8654 code = (code == GE ? LT : GE);
8660 /* If testing for equality, we can take the NEG of the constant. */
8661 if (equality_comparison_p
8662 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
8664 op0 = XEXP (op0, 0);
8669 /* The remaining cases only apply to comparisons with zero. */
8673 /* When X is ABS or is known positive,
8674 (neg X) is < 0 if and only if X != 0. */
8676 if (sign_bit_comparison_p
8677 && (GET_CODE (XEXP (op0, 0)) == ABS
8678 || (mode_width <= HOST_BITS_PER_WIDE_INT
8679 && (nonzero_bits (XEXP (op0, 0), mode)
8680 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8682 op0 = XEXP (op0, 0);
8683 code = (code == LT ? NE : EQ);
8687 /* If we have NEG of something whose two high-order bits are the
8688 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8689 if (num_sign_bit_copies (op0, mode) >= 2)
8691 op0 = XEXP (op0, 0);
8692 code = swap_condition (code);
8698 /* If we are testing equality and our count is a constant, we
8699 can perform the inverse operation on our RHS. */
8700 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8701 && (tem = simplify_binary_operation (ROTATERT, mode,
8702 op1, XEXP (op0, 1))) != 0)
8704 op0 = XEXP (op0, 0);
8709 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8710 a particular bit. Convert it to an AND of a constant of that
8711 bit. This will be converted into a ZERO_EXTRACT. */
8712 if (const_op == 0 && sign_bit_comparison_p
8713 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8714 && mode_width <= HOST_BITS_PER_WIDE_INT)
8716 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8719 - INTVAL (XEXP (op0, 1)))));
8720 code = (code == LT ? NE : EQ);
8724 /* ... fall through ... */
8727 /* ABS is ignorable inside an equality comparison with zero. */
8728 if (const_op == 0 && equality_comparison_p)
8730 op0 = XEXP (op0, 0);
8737 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8738 to (compare FOO CONST) if CONST fits in FOO's mode and we
8739 are either testing inequality or have an unsigned comparison
8740 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8741 if (! unsigned_comparison_p
8742 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8743 <= HOST_BITS_PER_WIDE_INT)
8744 && ((unsigned HOST_WIDE_INT) const_op
8745 < (((HOST_WIDE_INT) 1
8746 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8748 op0 = XEXP (op0, 0);
8754 /* Check for the case where we are comparing A - C1 with C2,
8755 both constants are smaller than 1/2 the maxium positive
8756 value in MODE, and the comparison is equality or unsigned.
8757 In that case, if A is either zero-extended to MODE or has
8758 sufficient sign bits so that the high-order bit in MODE
8759 is a copy of the sign in the inner mode, we can prove that it is
8760 safe to do the operation in the wider mode. This simplifies
8761 many range checks. */
8763 if (mode_width <= HOST_BITS_PER_WIDE_INT
8764 && subreg_lowpart_p (op0)
8765 && GET_CODE (SUBREG_REG (op0)) == PLUS
8766 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8767 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8768 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8769 < GET_MODE_MASK (mode) / 2)
8770 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
8771 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
8772 GET_MODE (SUBREG_REG (op0)))
8773 & ~ GET_MODE_MASK (mode))
8774 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8775 GET_MODE (SUBREG_REG (op0)))
8776 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8777 - GET_MODE_BITSIZE (mode)))))
8779 op0 = SUBREG_REG (op0);
8783 /* If the inner mode is narrower and we are extracting the low part,
8784 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8785 if (subreg_lowpart_p (op0)
8786 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8787 /* Fall through */ ;
8791 /* ... fall through ... */
8794 if ((unsigned_comparison_p || equality_comparison_p)
8795 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8796 <= HOST_BITS_PER_WIDE_INT)
8797 && ((unsigned HOST_WIDE_INT) const_op
8798 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8800 op0 = XEXP (op0, 0);
8806 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
8807 this for equality comparisons due to pathological cases involving
8809 if (equality_comparison_p
8810 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8811 op1, XEXP (op0, 1))))
8813 op0 = XEXP (op0, 0);
8818 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8819 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8820 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8822 op0 = XEXP (XEXP (op0, 0), 0);
8823 code = (code == LT ? EQ : NE);
8829 /* (eq (minus A B) C) -> (eq A (plus B C)) or
8830 (eq B (minus A C)), whichever simplifies. We can only do
8831 this for equality comparisons due to pathological cases involving
8833 if (equality_comparison_p
8834 && 0 != (tem = simplify_binary_operation (PLUS, mode,
8835 XEXP (op0, 1), op1)))
8837 op0 = XEXP (op0, 0);
8842 if (equality_comparison_p
8843 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8844 XEXP (op0, 0), op1)))
8846 op0 = XEXP (op0, 1);
8851 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8852 of bits in X minus 1, is one iff X > 0. */
8853 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8854 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8855 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8856 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8858 op0 = XEXP (op0, 1);
8859 code = (code == GE ? LE : GT);
8865 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8866 if C is zero or B is a constant. */
8867 if (equality_comparison_p
8868 && 0 != (tem = simplify_binary_operation (XOR, mode,
8869 XEXP (op0, 1), op1)))
8871 op0 = XEXP (op0, 0);
8878 case LT: case LTU: case LE: case LEU:
8879 case GT: case GTU: case GE: case GEU:
8880 /* We can't do anything if OP0 is a condition code value, rather
8881 than an actual data value. */
8884 || XEXP (op0, 0) == cc0_rtx
8886 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8889 /* Get the two operands being compared. */
8890 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8891 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8893 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8895 /* Check for the cases where we simply want the result of the
8896 earlier test or the opposite of that result. */
8898 || (code == EQ && reversible_comparison_p (op0))
8899 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8900 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8901 && (STORE_FLAG_VALUE
8902 & (((HOST_WIDE_INT) 1
8903 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8905 || (code == GE && reversible_comparison_p (op0)))))
8907 code = (code == LT || code == NE
8908 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8909 op0 = tem, op1 = tem1;
8915 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8917 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8918 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8919 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8921 op0 = XEXP (op0, 1);
8922 code = (code == GE ? GT : LE);
8928 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8929 will be converted to a ZERO_EXTRACT later. */
8930 if (const_op == 0 && equality_comparison_p
8931 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8932 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8933 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8935 op0 = simplify_and_const_int
8936 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8938 XEXP (XEXP (op0, 0), 1)),
8943 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8944 zero and X is a comparison and C1 and C2 describe only bits set
8945 in STORE_FLAG_VALUE, we can compare with X. */
8946 if (const_op == 0 && equality_comparison_p
8947 && mode_width <= HOST_BITS_PER_WIDE_INT
8948 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8949 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8950 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8951 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8952 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8954 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8955 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8956 if ((~ STORE_FLAG_VALUE & mask) == 0
8957 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8958 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8959 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8961 op0 = XEXP (XEXP (op0, 0), 0);
8966 /* If we are doing an equality comparison of an AND of a bit equal
8967 to the sign bit, replace this with a LT or GE comparison of
8968 the underlying value. */
8969 if (equality_comparison_p
8971 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8972 && mode_width <= HOST_BITS_PER_WIDE_INT
8973 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8974 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8976 op0 = XEXP (op0, 0);
8977 code = (code == EQ ? GE : LT);
8981 /* If this AND operation is really a ZERO_EXTEND from a narrower
8982 mode, the constant fits within that mode, and this is either an
8983 equality or unsigned comparison, try to do this comparison in
8984 the narrower mode. */
8985 if ((equality_comparison_p || unsigned_comparison_p)
8986 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8987 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8988 & GET_MODE_MASK (mode))
8990 && const_op >> i == 0
8991 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8993 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9000 /* If we have (compare (xshift FOO N) (const_int C)) and
9001 the high order N bits of FOO (N+1 if an inequality comparison)
9002 are known to be zero, we can do this by comparing FOO with C
9003 shifted right N bits so long as the low-order N bits of C are
9005 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9006 && INTVAL (XEXP (op0, 1)) >= 0
9007 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9008 < HOST_BITS_PER_WIDE_INT)
9010 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9011 && mode_width <= HOST_BITS_PER_WIDE_INT
9012 && (nonzero_bits (XEXP (op0, 0), mode)
9013 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9014 + ! equality_comparison_p))) == 0)
9016 const_op >>= INTVAL (XEXP (op0, 1));
9017 op1 = GEN_INT (const_op);
9018 op0 = XEXP (op0, 0);
9022 /* If we are doing a sign bit comparison, it means we are testing
9023 a particular bit. Convert it to the appropriate AND. */
9024 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9025 && mode_width <= HOST_BITS_PER_WIDE_INT)
9027 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9030 - INTVAL (XEXP (op0, 1)))));
9031 code = (code == LT ? NE : EQ);
9035 /* If this an equality comparison with zero and we are shifting
9036 the low bit to the sign bit, we can convert this to an AND of the
9038 if (const_op == 0 && equality_comparison_p
9039 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9040 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9042 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9049 /* If this is an equality comparison with zero, we can do this
9050 as a logical shift, which might be much simpler. */
9051 if (equality_comparison_p && const_op == 0
9052 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9054 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9056 INTVAL (XEXP (op0, 1)));
9060 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9061 do the comparison in a narrower mode. */
9062 if (! unsigned_comparison_p
9063 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9064 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9065 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9066 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9067 MODE_INT, 1)) != BLKmode
9068 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9069 || ((unsigned HOST_WIDE_INT) - const_op
9070 <= GET_MODE_MASK (tmode))))
9072 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9076 /* ... fall through ... */
9078 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9079 the low order N bits of FOO are known to be zero, we can do this
9080 by comparing FOO with C shifted left N bits so long as no
9082 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9083 && INTVAL (XEXP (op0, 1)) >= 0
9084 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9085 && mode_width <= HOST_BITS_PER_WIDE_INT
9086 && (nonzero_bits (XEXP (op0, 0), mode)
9087 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9089 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9092 const_op <<= INTVAL (XEXP (op0, 1));
9093 op1 = GEN_INT (const_op);
9094 op0 = XEXP (op0, 0);
9098 /* If we are using this shift to extract just the sign bit, we
9099 can replace this with an LT or GE comparison. */
9101 && (equality_comparison_p || sign_bit_comparison_p)
9102 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9103 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9105 op0 = XEXP (op0, 0);
9106 code = (code == NE || code == GT ? LT : GE);
9115 /* Now make any compound operations involved in this comparison. Then,
9116 check for an outmost SUBREG on OP0 that isn't doing anything or is
9117 paradoxical. The latter case can only occur when it is known that the
9118 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9119 We can never remove a SUBREG for a non-equality comparison because the
9120 sign bit is in a different place in the underlying object. */
9122 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9123 op1 = make_compound_operation (op1, SET);
9125 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9126 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9127 && (code == NE || code == EQ)
9128 && ((GET_MODE_SIZE (GET_MODE (op0))
9129 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9131 op0 = SUBREG_REG (op0);
9132 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9135 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9136 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9137 && (code == NE || code == EQ)
9138 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9139 <= HOST_BITS_PER_WIDE_INT)
9140 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9141 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9142 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9144 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9145 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9146 op0 = SUBREG_REG (op0), op1 = tem;
9148 /* We now do the opposite procedure: Some machines don't have compare
9149 insns in all modes. If OP0's mode is an integer mode smaller than a
9150 word and we can't do a compare in that mode, see if there is a larger
9151 mode for which we can do the compare. There are a number of cases in
9152 which we can use the wider mode. */
9154 mode = GET_MODE (op0);
9155 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9156 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
9157 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
9158 for (tmode = GET_MODE_WIDER_MODE (mode);
9160 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
9161 tmode = GET_MODE_WIDER_MODE (tmode))
9162 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
9164 /* If the only nonzero bits in OP0 and OP1 are those in the
9165 narrower mode and this is an equality or unsigned comparison,
9166 we can use the wider mode. Similarly for sign-extended
9167 values and equality or signed comparisons. */
9168 if (((code == EQ || code == NE
9169 || code == GEU || code == GTU || code == LEU || code == LTU)
9170 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
9171 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
9172 || ((code == EQ || code == NE
9173 || code == GE || code == GT || code == LE || code == LT)
9174 && (num_sign_bit_copies (op0, tmode)
9175 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
9176 && (num_sign_bit_copies (op1, tmode)
9177 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
9179 op0 = gen_lowpart_for_combine (tmode, op0);
9180 op1 = gen_lowpart_for_combine (tmode, op1);
9184 /* If this is a test for negative, we can make an explicit
9185 test of the sign bit. */
9187 if (op1 == const0_rtx && (code == LT || code == GE)
9188 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9190 op0 = gen_binary (AND, tmode,
9191 gen_lowpart_for_combine (tmode, op0),
9192 GEN_INT ((HOST_WIDE_INT) 1
9193 << (GET_MODE_BITSIZE (mode) - 1)));
9194 code = (code == LT) ? NE : EQ;
9205 /* Return 1 if we know that X, a comparison operation, is not operating
9206 on a floating-point value or is EQ or NE, meaning that we can safely
9210 reversible_comparison_p (x)
9213 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
9215 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
9218 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
9221 case MODE_PARTIAL_INT:
9222 case MODE_COMPLEX_INT:
9226 x = get_last_value (XEXP (x, 0));
9227 return (x && GET_CODE (x) == COMPARE
9228 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
9234 /* Utility function for following routine. Called when X is part of a value
9235 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9236 for each register mentioned. Similar to mention_regs in cse.c */
9239 update_table_tick (x)
9242 register enum rtx_code code = GET_CODE (x);
9243 register char *fmt = GET_RTX_FORMAT (code);
9248 int regno = REGNO (x);
9249 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9250 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9252 for (i = regno; i < endregno; i++)
9253 reg_last_set_table_tick[i] = label_tick;
9258 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9259 /* Note that we can't have an "E" in values stored; see
9260 get_last_value_validate. */
9262 update_table_tick (XEXP (x, i));
9265 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
9266 are saying that the register is clobbered and we no longer know its
9267 value. If INSN is zero, don't update reg_last_set; this is only permitted
9268 with VALUE also zero and is used to invalidate the register. */
9271 record_value_for_reg (reg, insn, value)
9276 int regno = REGNO (reg);
9277 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9278 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
9281 /* If VALUE contains REG and we have a previous value for REG, substitute
9282 the previous value. */
9283 if (value && insn && reg_overlap_mentioned_p (reg, value))
9287 /* Set things up so get_last_value is allowed to see anything set up to
9289 subst_low_cuid = INSN_CUID (insn);
9290 tem = get_last_value (reg);
9293 value = replace_rtx (copy_rtx (value), reg, tem);
9296 /* For each register modified, show we don't know its value, that
9297 we don't know about its bitwise content, that its value has been
9298 updated, and that we don't know the location of the death of the
9300 for (i = regno; i < endregno; i ++)
9303 reg_last_set[i] = insn;
9304 reg_last_set_value[i] = 0;
9305 reg_last_set_mode[i] = 0;
9306 reg_last_set_nonzero_bits[i] = 0;
9307 reg_last_set_sign_bit_copies[i] = 0;
9308 reg_last_death[i] = 0;
9311 /* Mark registers that are being referenced in this value. */
9313 update_table_tick (value);
9315 /* Now update the status of each register being set.
9316 If someone is using this register in this block, set this register
9317 to invalid since we will get confused between the two lives in this
9318 basic block. This makes using this register always invalid. In cse, we
9319 scan the table to invalidate all entries using this register, but this
9320 is too much work for us. */
9322 for (i = regno; i < endregno; i++)
9324 reg_last_set_label[i] = label_tick;
9325 if (value && reg_last_set_table_tick[i] == label_tick)
9326 reg_last_set_invalid[i] = 1;
9328 reg_last_set_invalid[i] = 0;
9331 /* The value being assigned might refer to X (like in "x++;"). In that
9332 case, we must replace it with (clobber (const_int 0)) to prevent
9334 if (value && ! get_last_value_validate (&value,
9335 reg_last_set_label[regno], 0))
9337 value = copy_rtx (value);
9338 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
9342 /* For the main register being modified, update the value, the mode, the
9343 nonzero bits, and the number of sign bit copies. */
9345 reg_last_set_value[regno] = value;
9349 subst_low_cuid = INSN_CUID (insn);
9350 reg_last_set_mode[regno] = GET_MODE (reg);
9351 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
9352 reg_last_set_sign_bit_copies[regno]
9353 = num_sign_bit_copies (value, GET_MODE (reg));
9357 /* Used for communication between the following two routines. */
9358 static rtx record_dead_insn;
9360 /* Called via note_stores from record_dead_and_set_regs to handle one
9361 SET or CLOBBER in an insn. */
9364 record_dead_and_set_regs_1 (dest, setter)
9367 if (GET_CODE (dest) == REG)
9369 /* If we are setting the whole register, we know its value. Otherwise
9370 show that we don't know the value. We can handle SUBREG in
9372 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
9373 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
9374 else if (GET_CODE (setter) == SET
9375 && GET_CODE (SET_DEST (setter)) == SUBREG
9376 && SUBREG_REG (SET_DEST (setter)) == dest
9377 && subreg_lowpart_p (SET_DEST (setter)))
9378 record_value_for_reg (dest, record_dead_insn,
9379 gen_lowpart_for_combine (GET_MODE (dest),
9382 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
9384 else if (GET_CODE (dest) == MEM
9385 /* Ignore pushes, they clobber nothing. */
9386 && ! push_operand (dest, GET_MODE (dest)))
9387 mem_last_set = INSN_CUID (record_dead_insn);
9390 /* Update the records of when each REG was most recently set or killed
9391 for the things done by INSN. This is the last thing done in processing
9392 INSN in the combiner loop.
9394 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
9395 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
9396 and also the similar information mem_last_set (which insn most recently
9397 modified memory) and last_call_cuid (which insn was the most recent
9398 subroutine call). */
9401 record_dead_and_set_regs (insn)
9407 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
9409 if (REG_NOTE_KIND (link) == REG_DEAD
9410 && GET_CODE (XEXP (link, 0)) == REG)
9412 int regno = REGNO (XEXP (link, 0));
9414 = regno + (regno < FIRST_PSEUDO_REGISTER
9415 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
9418 for (i = regno; i < endregno; i++)
9419 reg_last_death[i] = insn;
9421 else if (REG_NOTE_KIND (link) == REG_INC)
9422 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
9425 if (GET_CODE (insn) == CALL_INSN)
9427 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9428 if (call_used_regs[i])
9430 reg_last_set_value[i] = 0;
9431 reg_last_set_mode[i] = 0;
9432 reg_last_set_nonzero_bits[i] = 0;
9433 reg_last_set_sign_bit_copies[i] = 0;
9434 reg_last_death[i] = 0;
9437 last_call_cuid = mem_last_set = INSN_CUID (insn);
9440 record_dead_insn = insn;
9441 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
9444 /* Utility routine for the following function. Verify that all the registers
9445 mentioned in *LOC are valid when *LOC was part of a value set when
9446 label_tick == TICK. Return 0 if some are not.
9448 If REPLACE is non-zero, replace the invalid reference with
9449 (clobber (const_int 0)) and return 1. This replacement is useful because
9450 we often can get useful information about the form of a value (e.g., if
9451 it was produced by a shift that always produces -1 or 0) even though
9452 we don't know exactly what registers it was produced from. */
9455 get_last_value_validate (loc, tick, replace)
9461 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
9462 int len = GET_RTX_LENGTH (GET_CODE (x));
9465 if (GET_CODE (x) == REG)
9467 int regno = REGNO (x);
9468 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9469 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9472 for (j = regno; j < endregno; j++)
9473 if (reg_last_set_invalid[j]
9474 /* If this is a pseudo-register that was only set once, it is
9476 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
9477 && reg_last_set_label[j] > tick))
9480 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9487 for (i = 0; i < len; i++)
9489 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
9490 /* Don't bother with these. They shouldn't occur anyway. */
9494 /* If we haven't found a reason for it to be invalid, it is valid. */
9498 /* Get the last value assigned to X, if known. Some registers
9499 in the value may be replaced with (clobber (const_int 0)) if their value
9500 is known longer known reliably. */
9509 /* If this is a non-paradoxical SUBREG, get the value of its operand and
9510 then convert it to the desired mode. If this is a paradoxical SUBREG,
9511 we cannot predict what values the "extra" bits might have. */
9512 if (GET_CODE (x) == SUBREG
9513 && subreg_lowpart_p (x)
9514 && (GET_MODE_SIZE (GET_MODE (x))
9515 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
9516 && (value = get_last_value (SUBREG_REG (x))) != 0)
9517 return gen_lowpart_for_combine (GET_MODE (x), value);
9519 if (GET_CODE (x) != REG)
9523 value = reg_last_set_value[regno];
9525 /* If we don't have a value or if it isn't for this basic block, return 0. */
9528 || (reg_n_sets[regno] != 1
9529 && reg_last_set_label[regno] != label_tick))
9532 /* If the value was set in a later insn that the ones we are processing,
9533 we can't use it even if the register was only set once, but make a quick
9534 check to see if the previous insn set it to something. This is commonly
9535 the case when the same pseudo is used by repeated insns. */
9537 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
9541 /* If there is an insn that is supposed to be immediately
9542 in front of subst_insn, use it. */
9543 if (subst_prev_insn != 0)
9544 insn = subst_prev_insn;
9546 for (insn = prev_nonnote_insn (subst_insn);
9547 insn && INSN_CUID (insn) >= subst_low_cuid;
9548 insn = prev_nonnote_insn (insn))
9552 && (set = single_set (insn)) != 0
9553 && rtx_equal_p (SET_DEST (set), x))
9555 value = SET_SRC (set);
9557 /* Make sure that VALUE doesn't reference X. Replace any
9558 expliit references with a CLOBBER. If there are any remaining
9559 references (rare), don't use the value. */
9561 if (reg_mentioned_p (x, value))
9562 value = replace_rtx (copy_rtx (value), x,
9563 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
9565 if (reg_overlap_mentioned_p (x, value))
9572 /* If the value has all its registers valid, return it. */
9573 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
9576 /* Otherwise, make a copy and replace any invalid register with
9577 (clobber (const_int 0)). If that fails for some reason, return 0. */
9579 value = copy_rtx (value);
9580 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
9586 /* Return nonzero if expression X refers to a REG or to memory
9587 that is set in an instruction more recent than FROM_CUID. */
9590 use_crosses_set_p (x, from_cuid)
9596 register enum rtx_code code = GET_CODE (x);
9600 register int regno = REGNO (x);
9601 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
9602 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9604 #ifdef PUSH_ROUNDING
9605 /* Don't allow uses of the stack pointer to be moved,
9606 because we don't know whether the move crosses a push insn. */
9607 if (regno == STACK_POINTER_REGNUM)
9610 for (;regno < endreg; regno++)
9611 if (reg_last_set[regno]
9612 && INSN_CUID (reg_last_set[regno]) > from_cuid)
9617 if (code == MEM && mem_last_set > from_cuid)
9620 fmt = GET_RTX_FORMAT (code);
9622 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9627 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9628 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
9631 else if (fmt[i] == 'e'
9632 && use_crosses_set_p (XEXP (x, i), from_cuid))
9638 /* Define three variables used for communication between the following
9641 static int reg_dead_regno, reg_dead_endregno;
9642 static int reg_dead_flag;
9644 /* Function called via note_stores from reg_dead_at_p.
9646 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
9647 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
9650 reg_dead_at_p_1 (dest, x)
9654 int regno, endregno;
9656 if (GET_CODE (dest) != REG)
9659 regno = REGNO (dest);
9660 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9661 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
9663 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
9664 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
9667 /* Return non-zero if REG is known to be dead at INSN.
9669 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
9670 referencing REG, it is dead. If we hit a SET referencing REG, it is
9671 live. Otherwise, see if it is live or dead at the start of the basic
9675 reg_dead_at_p (reg, insn)
9681 /* Set variables for reg_dead_at_p_1. */
9682 reg_dead_regno = REGNO (reg);
9683 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
9684 ? HARD_REGNO_NREGS (reg_dead_regno,
9690 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
9691 beginning of function. */
9692 for (; insn && GET_CODE (insn) != CODE_LABEL;
9693 insn = prev_nonnote_insn (insn))
9695 note_stores (PATTERN (insn), reg_dead_at_p_1);
9697 return reg_dead_flag == 1 ? 1 : 0;
9699 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
9703 /* Get the basic block number that we were in. */
9708 for (block = 0; block < n_basic_blocks; block++)
9709 if (insn == basic_block_head[block])
9712 if (block == n_basic_blocks)
9716 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
9717 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
9718 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
9724 /* Remove register number REGNO from the dead registers list of INSN.
9726 Return the note used to record the death, if there was one. */
9729 remove_death (regno, insn)
9733 register rtx note = find_regno_note (insn, REG_DEAD, regno);
9737 reg_n_deaths[regno]--;
9738 remove_note (insn, note);
9744 /* For each register (hardware or pseudo) used within expression X, if its
9745 death is in an instruction with cuid between FROM_CUID (inclusive) and
9746 TO_INSN (exclusive), put a REG_DEAD note for that register in the
9747 list headed by PNOTES.
9749 This is done when X is being merged by combination into TO_INSN. These
9750 notes will then be distributed as needed. */
9753 move_deaths (x, from_cuid, to_insn, pnotes)
9760 register int len, i;
9761 register enum rtx_code code = GET_CODE (x);
9765 register int regno = REGNO (x);
9766 register rtx where_dead = reg_last_death[regno];
9768 if (where_dead && INSN_CUID (where_dead) >= from_cuid
9769 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9771 rtx note = remove_death (regno, where_dead);
9773 /* It is possible for the call above to return 0. This can occur
9774 when reg_last_death points to I2 or I1 that we combined with.
9775 In that case make a new note.
9777 We must also check for the case where X is a hard register
9778 and NOTE is a death note for a range of hard registers
9779 including X. In that case, we must put REG_DEAD notes for
9780 the remaining registers in place of NOTE. */
9782 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
9783 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
9784 != GET_MODE_SIZE (GET_MODE (x))))
9786 int deadregno = REGNO (XEXP (note, 0));
9788 = (deadregno + HARD_REGNO_NREGS (deadregno,
9789 GET_MODE (XEXP (note, 0))));
9790 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9793 for (i = deadregno; i < deadend; i++)
9794 if (i < regno || i >= ourend)
9795 REG_NOTES (where_dead)
9796 = gen_rtx (EXPR_LIST, REG_DEAD,
9797 gen_rtx (REG, word_mode, i),
9798 REG_NOTES (where_dead));
9801 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
9803 XEXP (note, 1) = *pnotes;
9807 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9809 reg_n_deaths[regno]++;
9815 else if (GET_CODE (x) == SET)
9817 rtx dest = SET_DEST (x);
9819 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9821 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9822 that accesses one word of a multi-word item, some
9823 piece of everything register in the expression is used by
9824 this insn, so remove any old death. */
9826 if (GET_CODE (dest) == ZERO_EXTRACT
9827 || GET_CODE (dest) == STRICT_LOW_PART
9828 || (GET_CODE (dest) == SUBREG
9829 && (((GET_MODE_SIZE (GET_MODE (dest))
9830 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9831 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9832 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9834 move_deaths (dest, from_cuid, to_insn, pnotes);
9838 /* If this is some other SUBREG, we know it replaces the entire
9839 value, so use that as the destination. */
9840 if (GET_CODE (dest) == SUBREG)
9841 dest = SUBREG_REG (dest);
9843 /* If this is a MEM, adjust deaths of anything used in the address.
9844 For a REG (the only other possibility), the entire value is
9845 being replaced so the old value is not used in this insn. */
9847 if (GET_CODE (dest) == MEM)
9848 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9852 else if (GET_CODE (x) == CLOBBER)
9855 len = GET_RTX_LENGTH (code);
9856 fmt = GET_RTX_FORMAT (code);
9858 for (i = 0; i < len; i++)
9863 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9864 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9866 else if (fmt[i] == 'e')
9867 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9871 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9872 pattern of an insn. X must be a REG. */
9875 reg_bitfield_target_p (x, body)
9881 if (GET_CODE (body) == SET)
9883 rtx dest = SET_DEST (body);
9885 int regno, tregno, endregno, endtregno;
9887 if (GET_CODE (dest) == ZERO_EXTRACT)
9888 target = XEXP (dest, 0);
9889 else if (GET_CODE (dest) == STRICT_LOW_PART)
9890 target = SUBREG_REG (XEXP (dest, 0));
9894 if (GET_CODE (target) == SUBREG)
9895 target = SUBREG_REG (target);
9897 if (GET_CODE (target) != REG)
9900 tregno = REGNO (target), regno = REGNO (x);
9901 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9904 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9905 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9907 return endregno > tregno && regno < endtregno;
9910 else if (GET_CODE (body) == PARALLEL)
9911 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9912 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9918 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9919 as appropriate. I3 and I2 are the insns resulting from the combination
9920 insns including FROM (I2 may be zero).
9922 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9923 not need REG_DEAD notes because they are being substituted for. This
9924 saves searching in the most common cases.
9926 Each note in the list is either ignored or placed on some insns, depending
9927 on the type of note. */
9930 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9934 rtx elim_i2, elim_i1;
9936 rtx note, next_note;
9939 for (note = notes; note; note = next_note)
9941 rtx place = 0, place2 = 0;
9943 /* If this NOTE references a pseudo register, ensure it references
9944 the latest copy of that register. */
9945 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9946 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9947 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9949 next_note = XEXP (note, 1);
9950 switch (REG_NOTE_KIND (note))
9953 /* If this note is from any insn other than i3, then we have no
9954 use for it, and must ignore it.
9956 Any clobbers for i3 may still exist, and so we must process
9957 REG_UNUSED notes from that insn.
9959 Any clobbers from i2 or i1 can only exist if they were added by
9960 recog_for_combine. In that case, recog_for_combine created the
9961 necessary REG_UNUSED notes. Trying to keep any original
9962 REG_UNUSED notes from these insns can cause incorrect output
9963 if it is for the same register as the original i3 dest.
9964 In that case, we will notice that the register is set in i3,
9965 and then add a REG_UNUSED note for the destination of i3, which
9967 if (from_insn != i3)
9970 /* If this register is set or clobbered in I3, put the note there
9971 unless there is one already. */
9972 else if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9974 if (! (GET_CODE (XEXP (note, 0)) == REG
9975 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9976 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9979 /* Otherwise, if this register is used by I3, then this register
9980 now dies here, so we must put a REG_DEAD note here unless there
9982 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9983 && ! (GET_CODE (XEXP (note, 0)) == REG
9984 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9985 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9987 PUT_REG_NOTE_KIND (note, REG_DEAD);
9995 /* These notes say something about results of an insn. We can
9996 only support them if they used to be on I3 in which case they
9997 remain on I3. Otherwise they are ignored.
9999 If the note refers to an expression that is not a constant, we
10000 must also ignore the note since we cannot tell whether the
10001 equivalence is still true. It might be possible to do
10002 slightly better than this (we only have a problem if I2DEST
10003 or I1DEST is present in the expression), but it doesn't
10004 seem worth the trouble. */
10006 if (from_insn == i3
10007 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
10012 case REG_NO_CONFLICT:
10014 /* These notes say something about how a register is used. They must
10015 be present on any use of the register in I2 or I3. */
10016 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
10019 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
10029 /* It is too much trouble to try to see if this note is still
10030 correct in all situations. It is better to simply delete it. */
10034 /* If the insn previously containing this note still exists,
10035 put it back where it was. Otherwise move it to the previous
10036 insn. Adjust the corresponding REG_LIBCALL note. */
10037 if (GET_CODE (from_insn) != NOTE)
10041 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
10042 place = prev_real_insn (from_insn);
10044 XEXP (tem, 0) = place;
10049 /* This is handled similarly to REG_RETVAL. */
10050 if (GET_CODE (from_insn) != NOTE)
10054 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
10055 place = next_real_insn (from_insn);
10057 XEXP (tem, 0) = place;
10062 /* If the register is used as an input in I3, it dies there.
10063 Similarly for I2, if it is non-zero and adjacent to I3.
10065 If the register is not used as an input in either I3 or I2
10066 and it is not one of the registers we were supposed to eliminate,
10067 there are two possibilities. We might have a non-adjacent I2
10068 or we might have somehow eliminated an additional register
10069 from a computation. For example, we might have had A & B where
10070 we discover that B will always be zero. In this case we will
10071 eliminate the reference to A.
10073 In both cases, we must search to see if we can find a previous
10074 use of A and put the death note there. */
10076 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
10078 else if (i2 != 0 && next_nonnote_insn (i2) == i3
10079 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10082 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
10085 /* If the register is used in both I2 and I3 and it dies in I3,
10086 we might have added another reference to it. If reg_n_refs
10087 was 2, bump it to 3. This has to be correct since the
10088 register must have been set somewhere. The reason this is
10089 done is because local-alloc.c treats 2 references as a
10092 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
10093 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
10094 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10095 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
10098 for (tem = prev_nonnote_insn (i3);
10099 tem && (GET_CODE (tem) == INSN
10100 || GET_CODE (tem) == CALL_INSN);
10101 tem = prev_nonnote_insn (tem))
10103 /* If the register is being set at TEM, see if that is all
10104 TEM is doing. If so, delete TEM. Otherwise, make this
10105 into a REG_UNUSED note instead. */
10106 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
10108 rtx set = single_set (tem);
10110 /* Verify that it was the set, and not a clobber that
10111 modified the register. */
10113 if (set != 0 && ! side_effects_p (SET_SRC (set))
10114 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
10116 /* Move the notes and links of TEM elsewhere.
10117 This might delete other dead insns recursively.
10118 First set the pattern to something that won't use
10121 PATTERN (tem) = pc_rtx;
10123 distribute_notes (REG_NOTES (tem), tem, tem,
10124 NULL_RTX, NULL_RTX, NULL_RTX);
10125 distribute_links (LOG_LINKS (tem));
10127 PUT_CODE (tem, NOTE);
10128 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
10129 NOTE_SOURCE_FILE (tem) = 0;
10133 PUT_REG_NOTE_KIND (note, REG_UNUSED);
10135 /* If there isn't already a REG_UNUSED note, put one
10137 if (! find_regno_note (tem, REG_UNUSED,
10138 REGNO (XEXP (note, 0))))
10143 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
10150 /* If the register is set or already dead at PLACE, we needn't do
10151 anything with this note if it is still a REG_DEAD note.
10153 Note that we cannot use just `dead_or_set_p' here since we can
10154 convert an assignment to a register into a bit-field assignment.
10155 Therefore, we must also omit the note if the register is the
10156 target of a bitfield assignment. */
10158 if (place && REG_NOTE_KIND (note) == REG_DEAD)
10160 int regno = REGNO (XEXP (note, 0));
10162 if (dead_or_set_p (place, XEXP (note, 0))
10163 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
10165 /* Unless the register previously died in PLACE, clear
10166 reg_last_death. [I no longer understand why this is
10168 if (reg_last_death[regno] != place)
10169 reg_last_death[regno] = 0;
10173 reg_last_death[regno] = place;
10175 /* If this is a death note for a hard reg that is occupying
10176 multiple registers, ensure that we are still using all
10177 parts of the object. If we find a piece of the object
10178 that is unused, we must add a USE for that piece before
10179 PLACE and put the appropriate REG_DEAD note on it.
10181 An alternative would be to put a REG_UNUSED for the pieces
10182 on the insn that set the register, but that can't be done if
10183 it is not in the same block. It is simpler, though less
10184 efficient, to add the USE insns. */
10186 if (place && regno < FIRST_PSEUDO_REGISTER
10187 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
10190 = regno + HARD_REGNO_NREGS (regno,
10191 GET_MODE (XEXP (note, 0)));
10195 for (i = regno; i < endregno; i++)
10196 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
10198 rtx piece = gen_rtx (REG, word_mode, i);
10201 /* See if we already placed a USE note for this
10202 register in front of PLACE. */
10204 GET_CODE (PREV_INSN (p)) == INSN
10205 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
10207 if (rtx_equal_p (piece,
10208 XEXP (PATTERN (PREV_INSN (p)), 0)))
10217 = emit_insn_before (gen_rtx (USE, VOIDmode,
10220 REG_NOTES (use_insn)
10221 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
10222 REG_NOTES (use_insn));
10228 /* Check for the case where the register dying partially
10229 overlaps the register set by this insn. */
10231 for (i = regno; i < endregno; i++)
10232 if (dead_or_set_regno_p (place, i))
10240 /* Put only REG_DEAD notes for pieces that are
10241 still used and that are not already dead or set. */
10243 for (i = regno; i < endregno; i++)
10245 rtx piece = gen_rtx (REG, word_mode, i);
10247 if (reg_referenced_p (piece, PATTERN (place))
10248 && ! dead_or_set_p (place, piece)
10249 && ! reg_bitfield_target_p (piece,
10251 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
10253 REG_NOTES (place));
10263 /* Any other notes should not be present at this point in the
10270 XEXP (note, 1) = REG_NOTES (place);
10271 REG_NOTES (place) = note;
10273 else if ((REG_NOTE_KIND (note) == REG_DEAD
10274 || REG_NOTE_KIND (note) == REG_UNUSED)
10275 && GET_CODE (XEXP (note, 0)) == REG)
10276 reg_n_deaths[REGNO (XEXP (note, 0))]--;
10280 if ((REG_NOTE_KIND (note) == REG_DEAD
10281 || REG_NOTE_KIND (note) == REG_UNUSED)
10282 && GET_CODE (XEXP (note, 0)) == REG)
10283 reg_n_deaths[REGNO (XEXP (note, 0))]++;
10285 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
10286 XEXP (note, 0), REG_NOTES (place2));
10291 /* Similarly to above, distribute the LOG_LINKS that used to be present on
10292 I3, I2, and I1 to new locations. This is also called in one case to
10293 add a link pointing at I3 when I3's destination is changed. */
10296 distribute_links (links)
10299 rtx link, next_link;
10301 for (link = links; link; link = next_link)
10307 next_link = XEXP (link, 1);
10309 /* If the insn that this link points to is a NOTE or isn't a single
10310 set, ignore it. In the latter case, it isn't clear what we
10311 can do other than ignore the link, since we can't tell which
10312 register it was for. Such links wouldn't be used by combine
10315 It is not possible for the destination of the target of the link to
10316 have been changed by combine. The only potential of this is if we
10317 replace I3, I2, and I1 by I3 and I2. But in that case the
10318 destination of I2 also remains unchanged. */
10320 if (GET_CODE (XEXP (link, 0)) == NOTE
10321 || (set = single_set (XEXP (link, 0))) == 0)
10324 reg = SET_DEST (set);
10325 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
10326 || GET_CODE (reg) == SIGN_EXTRACT
10327 || GET_CODE (reg) == STRICT_LOW_PART)
10328 reg = XEXP (reg, 0);
10330 /* A LOG_LINK is defined as being placed on the first insn that uses
10331 a register and points to the insn that sets the register. Start
10332 searching at the next insn after the target of the link and stop
10333 when we reach a set of the register or the end of the basic block.
10335 Note that this correctly handles the link that used to point from
10336 I3 to I2. Also note that not much searching is typically done here
10337 since most links don't point very far away. */
10339 for (insn = NEXT_INSN (XEXP (link, 0));
10340 (insn && (this_basic_block == n_basic_blocks - 1
10341 || basic_block_head[this_basic_block + 1] != insn));
10342 insn = NEXT_INSN (insn))
10343 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
10344 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
10346 if (reg_referenced_p (reg, PATTERN (insn)))
10351 /* If we found a place to put the link, place it there unless there
10352 is already a link to the same insn as LINK at that point. */
10358 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
10359 if (XEXP (link2, 0) == XEXP (link, 0))
10364 XEXP (link, 1) = LOG_LINKS (place);
10365 LOG_LINKS (place) = link;
10372 dump_combine_stats (file)
10377 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
10378 combine_attempts, combine_merges, combine_extras, combine_successes);
10382 dump_combine_total_stats (file)
10387 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
10388 total_attempts, total_merges, total_extras, total_successes);