1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
83 /* Must precede rtl.h for FFS. */
89 #include "hard-reg-set.h"
91 #include "basic-block.h"
92 #include "insn-config.h"
93 #include "insn-flags.h"
94 #include "insn-codes.h"
95 #include "insn-attr.h"
99 /* It is not safe to use ordinary gen_lowpart in combine.
100 Use gen_lowpart_for_combine instead. See comments there. */
101 #define gen_lowpart dont_use_gen_lowpart_you_dummy
103 /* Number of attempts to combine instructions in this function. */
105 static int combine_attempts;
107 /* Number of attempts that got as far as substitution in this function. */
109 static int combine_merges;
111 /* Number of instructions combined with added SETs in this function. */
113 static int combine_extras;
115 /* Number of instructions combined in this function. */
117 static int combine_successes;
119 /* Totals over entire compilation. */
121 static int total_attempts, total_merges, total_extras, total_successes;
123 /* Define a defulat value for REVERSIBLE_CC_MODE.
124 We can never assume that a condition code mode is safe to reverse unless
125 the md tells us so. */
126 #ifndef REVERSIBLE_CC_MODE
127 #define REVERSIBLE_CC_MODE(MODE) 0
130 /* Vector mapping INSN_UIDs to cuids.
131 The cuids are like uids but increase monotonically always.
132 Combine always uses cuids so that it can compare them.
133 But actually renumbering the uids, which we used to do,
134 proves to be a bad idea because it makes it hard to compare
135 the dumps produced by earlier passes with those from later passes. */
137 static int *uid_cuid;
139 /* Get the cuid of an insn. */
141 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
143 /* Maximum register number, which is the size of the tables below. */
145 static int combine_max_regno;
147 /* Record last point of death of (hard or pseudo) register n. */
149 static rtx *reg_last_death;
151 /* Record last point of modification of (hard or pseudo) register n. */
153 static rtx *reg_last_set;
155 /* Record the cuid of the last insn that invalidated memory
156 (anything that writes memory, and subroutine calls, but not pushes). */
158 static int mem_last_set;
160 /* Record the cuid of the last CALL_INSN
161 so we can tell whether a potential combination crosses any calls. */
163 static int last_call_cuid;
165 /* When `subst' is called, this is the insn that is being modified
166 (by combining in a previous insn). The PATTERN of this insn
167 is still the old pattern partially modified and it should not be
168 looked at, but this may be used to examine the successors of the insn
169 to judge whether a simplification is valid. */
171 static rtx subst_insn;
173 /* If nonzero, this is the insn that should be presumed to be
174 immediately in front of `subst_insn'. */
176 static rtx subst_prev_insn;
178 /* This is the lowest CUID that `subst' is currently dealing with.
179 get_last_value will not return a value if the register was set at or
180 after this CUID. If not for this mechanism, we could get confused if
181 I2 or I1 in try_combine were an insn that used the old value of a register
182 to obtain a new value. In that case, we might erroneously get the
183 new value of the register when we wanted the old one. */
185 static int subst_low_cuid;
187 /* This contains any hard registers that are used in newpat; reg_dead_at_p
188 must consider all these registers to be always live. */
190 static HARD_REG_SET newpat_used_regs;
192 /* This is an insn to which a LOG_LINKS entry has been added. If this
193 insn is the earlier than I2 or I3, combine should rescan starting at
196 static rtx added_links_insn;
198 /* This is the value of undobuf.num_undo when we started processing this
199 substitution. This will prevent gen_rtx_combine from re-used a piece
200 from the previous expression. Doing so can produce circular rtl
203 static int previous_num_undos;
205 /* Basic block number of the block in which we are performing combines. */
206 static int this_basic_block;
208 /* The next group of arrays allows the recording of the last value assigned
209 to (hard or pseudo) register n. We use this information to see if a
210 operation being processed is redundant given a prior operation performed
211 on the register. For example, an `and' with a constant is redundant if
212 all the zero bits are already known to be turned off.
214 We use an approach similar to that used by cse, but change it in the
217 (1) We do not want to reinitialize at each label.
218 (2) It is useful, but not critical, to know the actual value assigned
219 to a register. Often just its form is helpful.
221 Therefore, we maintain the following arrays:
223 reg_last_set_value the last value assigned
224 reg_last_set_label records the value of label_tick when the
225 register was assigned
226 reg_last_set_table_tick records the value of label_tick when a
227 value using the register is assigned
228 reg_last_set_invalid set to non-zero when it is not valid
229 to use the value of this register in some
232 To understand the usage of these tables, it is important to understand
233 the distinction between the value in reg_last_set_value being valid
234 and the register being validly contained in some other expression in the
237 Entry I in reg_last_set_value is valid if it is non-zero, and either
238 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
240 Register I may validly appear in any expression returned for the value
241 of another register if reg_n_sets[i] is 1. It may also appear in the
242 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
243 reg_last_set_invalid[j] is zero.
245 If an expression is found in the table containing a register which may
246 not validly appear in an expression, the register is replaced by
247 something that won't match, (clobber (const_int 0)).
249 reg_last_set_invalid[i] is set non-zero when register I is being assigned
250 to and reg_last_set_table_tick[i] == label_tick. */
252 /* Record last value assigned to (hard or pseudo) register n. */
254 static rtx *reg_last_set_value;
256 /* Record the value of label_tick when the value for register n is placed in
257 reg_last_set_value[n]. */
259 static int *reg_last_set_label;
261 /* Record the value of label_tick when an expression involving register n
262 is placed in reg_last_set_value. */
264 static int *reg_last_set_table_tick;
266 /* Set non-zero if references to register n in expressions should not be
269 static char *reg_last_set_invalid;
271 /* Incremented for each label. */
273 static int label_tick;
275 /* Some registers that are set more than once and used in more than one
276 basic block are nevertheless always set in similar ways. For example,
277 a QImode register may be loaded from memory in two places on a machine
278 where byte loads zero extend.
280 We record in the following array what we know about the nonzero
281 bits of a register, specifically which bits are known to be zero.
283 If an entry is zero, it means that we don't know anything special. */
285 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
287 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
288 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
290 static enum machine_mode nonzero_bits_mode;
292 /* Nonzero if we know that a register has some leading bits that are always
293 equal to the sign bit. */
295 static char *reg_sign_bit_copies;
297 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
298 It is zero while computing them and after combine has completed. This
299 former test prevents propagating values based on previously set values,
300 which can be incorrect if a variable is modified in a loop. */
302 static int nonzero_sign_valid;
304 /* These arrays are maintained in parallel with reg_last_set_value
305 and are used to store the mode in which the register was last set,
306 the bits that were known to be zero when it was last set, and the
307 number of sign bits copies it was known to have when it was last set. */
309 static enum machine_mode *reg_last_set_mode;
310 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
311 static char *reg_last_set_sign_bit_copies;
313 /* Record one modification to rtl structure
314 to be undone by storing old_contents into *where.
315 is_int is 1 if the contents are an int. */
320 union {rtx r; int i;} old_contents;
321 union {rtx *r; int *i;} where;
324 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
325 num_undo says how many are currently recorded.
327 storage is nonzero if we must undo the allocation of new storage.
328 The value of storage is what to pass to obfree.
330 other_insn is nonzero if we have modified some other insn in the process
331 of working on subst_insn. It must be verified too. */
339 struct undo undo[MAX_UNDO];
343 static struct undobuf undobuf;
345 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
346 insn. The substitution can be undone by undo_all. If INTO is already
347 set to NEWVAL, do not record this change. Because computing NEWVAL might
348 also call SUBST, we have to compute it before we put anything into
351 #define SUBST(INTO, NEWVAL) \
352 do { rtx _new = (NEWVAL); \
353 if (undobuf.num_undo < MAX_UNDO) \
355 undobuf.undo[undobuf.num_undo].is_int = 0; \
356 undobuf.undo[undobuf.num_undo].where.r = &INTO; \
357 undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \
359 if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \
360 undobuf.num_undo++; \
364 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
366 Note that substitution for the value of a CONST_INT is not safe. */
368 #define SUBST_INT(INTO, NEWVAL) \
369 do { if (undobuf.num_undo < MAX_UNDO) \
371 undobuf.undo[undobuf.num_undo].is_int = 1; \
372 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
373 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
375 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
376 undobuf.num_undo++; \
380 /* Number of times the pseudo being substituted for
381 was found and replaced. */
383 static int n_occurrences;
385 static void init_reg_last_arrays PROTO(());
386 static void setup_incoming_promotions PROTO(());
387 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
388 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
389 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
390 static rtx try_combine PROTO((rtx, rtx, rtx));
391 static void undo_all PROTO((void));
392 static rtx *find_split_point PROTO((rtx *, rtx));
393 static rtx subst PROTO((rtx, rtx, rtx, int, int));
394 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
395 static rtx simplify_if_then_else PROTO((rtx));
396 static rtx simplify_set PROTO((rtx));
397 static rtx simplify_logical PROTO((rtx, int));
398 static rtx expand_compound_operation PROTO((rtx));
399 static rtx expand_field_assignment PROTO((rtx));
400 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
402 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
403 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
404 static rtx force_to_mode PROTO((rtx, enum machine_mode,
405 unsigned HOST_WIDE_INT, rtx, int));
406 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
407 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
408 static rtx make_field_assignment PROTO((rtx));
409 static rtx apply_distributive_law PROTO((rtx));
410 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
411 unsigned HOST_WIDE_INT));
412 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
413 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
414 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
415 enum rtx_code, HOST_WIDE_INT,
416 enum machine_mode, int *));
417 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
419 static int recog_for_combine PROTO((rtx *, rtx, rtx *));
420 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
421 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
423 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
425 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode, rtx));
426 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
427 static int reversible_comparison_p PROTO((rtx));
428 static void update_table_tick PROTO((rtx));
429 static void record_value_for_reg PROTO((rtx, rtx, rtx));
430 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
431 static void record_dead_and_set_regs PROTO((rtx));
432 static int get_last_value_validate PROTO((rtx *, int, int));
433 static rtx get_last_value PROTO((rtx));
434 static int use_crosses_set_p PROTO((rtx, int));
435 static void reg_dead_at_p_1 PROTO((rtx, rtx));
436 static int reg_dead_at_p PROTO((rtx, rtx));
437 static void move_deaths PROTO((rtx, int, rtx, rtx *));
438 static int reg_bitfield_target_p PROTO((rtx, rtx));
439 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
440 static void distribute_links PROTO((rtx));
441 static void mark_used_regs_combine PROTO((rtx));
443 /* Main entry point for combiner. F is the first insn of the function.
444 NREGS is the first unused pseudo-reg number. */
447 combine_instructions (f, nregs)
451 register rtx insn, next, prev;
453 register rtx links, nextlinks;
455 combine_attempts = 0;
458 combine_successes = 0;
459 undobuf.num_undo = previous_num_undos = 0;
461 combine_max_regno = nregs;
464 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
465 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
467 bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
468 bzero (reg_sign_bit_copies, nregs * sizeof (char));
470 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
471 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
472 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
473 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
474 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
475 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
477 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
478 reg_last_set_nonzero_bits
479 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
480 reg_last_set_sign_bit_copies
481 = (char *) alloca (nregs * sizeof (char));
483 init_reg_last_arrays ();
485 init_recog_no_volatile ();
487 /* Compute maximum uid value so uid_cuid can be allocated. */
489 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
490 if (INSN_UID (insn) > i)
493 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
495 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
497 /* Don't use reg_nonzero_bits when computing it. This can cause problems
498 when, for example, we have j <<= 1 in a loop. */
500 nonzero_sign_valid = 0;
502 /* Compute the mapping from uids to cuids.
503 Cuids are numbers assigned to insns, like uids,
504 except that cuids increase monotonically through the code.
506 Scan all SETs and see if we can deduce anything about what
507 bits are known to be zero for some registers and how many copies
508 of the sign bit are known to exist for those registers.
510 Also set any known values so that we can use it while searching
511 for what bits are known to be set. */
515 setup_incoming_promotions ();
517 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
519 INSN_CUID (insn) = ++i;
523 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
525 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
526 record_dead_and_set_regs (insn);
529 if (GET_CODE (insn) == CODE_LABEL)
533 nonzero_sign_valid = 1;
535 /* Now scan all the insns in forward order. */
537 this_basic_block = -1;
541 init_reg_last_arrays ();
542 setup_incoming_promotions ();
544 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
548 /* If INSN starts a new basic block, update our basic block number. */
549 if (this_basic_block + 1 < n_basic_blocks
550 && basic_block_head[this_basic_block + 1] == insn)
553 if (GET_CODE (insn) == CODE_LABEL)
556 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
558 /* Try this insn with each insn it links back to. */
560 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
561 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
564 /* Try each sequence of three linked insns ending with this one. */
566 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
567 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
568 nextlinks = XEXP (nextlinks, 1))
569 if ((next = try_combine (insn, XEXP (links, 0),
570 XEXP (nextlinks, 0))) != 0)
574 /* Try to combine a jump insn that uses CC0
575 with a preceding insn that sets CC0, and maybe with its
576 logical predecessor as well.
577 This is how we make decrement-and-branch insns.
578 We need this special code because data flow connections
579 via CC0 do not get entered in LOG_LINKS. */
581 if (GET_CODE (insn) == JUMP_INSN
582 && (prev = prev_nonnote_insn (insn)) != 0
583 && GET_CODE (prev) == INSN
584 && sets_cc0_p (PATTERN (prev)))
586 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
589 for (nextlinks = LOG_LINKS (prev); nextlinks;
590 nextlinks = XEXP (nextlinks, 1))
591 if ((next = try_combine (insn, prev,
592 XEXP (nextlinks, 0))) != 0)
596 /* Do the same for an insn that explicitly references CC0. */
597 if (GET_CODE (insn) == INSN
598 && (prev = prev_nonnote_insn (insn)) != 0
599 && GET_CODE (prev) == INSN
600 && sets_cc0_p (PATTERN (prev))
601 && GET_CODE (PATTERN (insn)) == SET
602 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
604 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
607 for (nextlinks = LOG_LINKS (prev); nextlinks;
608 nextlinks = XEXP (nextlinks, 1))
609 if ((next = try_combine (insn, prev,
610 XEXP (nextlinks, 0))) != 0)
614 /* Finally, see if any of the insns that this insn links to
615 explicitly references CC0. If so, try this insn, that insn,
616 and its predecessor if it sets CC0. */
617 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
618 if (GET_CODE (XEXP (links, 0)) == INSN
619 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
620 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
621 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
622 && GET_CODE (prev) == INSN
623 && sets_cc0_p (PATTERN (prev))
624 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
628 /* Try combining an insn with two different insns whose results it
630 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
631 for (nextlinks = XEXP (links, 1); nextlinks;
632 nextlinks = XEXP (nextlinks, 1))
633 if ((next = try_combine (insn, XEXP (links, 0),
634 XEXP (nextlinks, 0))) != 0)
637 if (GET_CODE (insn) != NOTE)
638 record_dead_and_set_regs (insn);
645 total_attempts += combine_attempts;
646 total_merges += combine_merges;
647 total_extras += combine_extras;
648 total_successes += combine_successes;
650 nonzero_sign_valid = 0;
653 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
656 init_reg_last_arrays ()
658 int nregs = combine_max_regno;
660 bzero (reg_last_death, nregs * sizeof (rtx));
661 bzero (reg_last_set, nregs * sizeof (rtx));
662 bzero (reg_last_set_value, nregs * sizeof (rtx));
663 bzero (reg_last_set_table_tick, nregs * sizeof (int));
664 bzero (reg_last_set_label, nregs * sizeof (int));
665 bzero (reg_last_set_invalid, nregs * sizeof (char));
666 bzero (reg_last_set_mode, nregs * sizeof (enum machine_mode));
667 bzero (reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
668 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
671 /* Set up any promoted values for incoming argument registers. */
674 setup_incoming_promotions ()
676 #ifdef PROMOTE_FUNCTION_ARGS
679 enum machine_mode mode;
681 rtx first = get_insns ();
683 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
684 if (FUNCTION_ARG_REGNO_P (regno)
685 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
686 record_value_for_reg (reg, first,
687 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
689 gen_rtx (CLOBBER, mode, const0_rtx)));
693 /* Called via note_stores. If X is a pseudo that is used in more than
694 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
695 set, record what bits are known zero. If we are clobbering X,
696 ignore this "set" because the clobbered value won't be used.
698 If we are setting only a portion of X and we can't figure out what
699 portion, assume all bits will be used since we don't know what will
702 Similarly, set how many bits of X are known to be copies of the sign bit
703 at all locations in the function. This is the smallest number implied
707 set_nonzero_bits_and_sign_copies (x, set)
713 if (GET_CODE (x) == REG
714 && REGNO (x) >= FIRST_PSEUDO_REGISTER
715 && reg_n_sets[REGNO (x)] > 1
716 && reg_basic_block[REGNO (x)] < 0
717 /* If this register is undefined at the start of the file, we can't
718 say what its contents were. */
719 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
720 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
721 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
723 if (GET_CODE (set) == CLOBBER)
725 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
726 reg_sign_bit_copies[REGNO (x)] = 0;
730 /* If this is a complex assignment, see if we can convert it into a
731 simple assignment. */
732 set = expand_field_assignment (set);
734 /* If this is a simple assignment, or we have a paradoxical SUBREG,
735 set what we know about X. */
737 if (SET_DEST (set) == x
738 || (GET_CODE (SET_DEST (set)) == SUBREG
739 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
740 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
741 && SUBREG_REG (SET_DEST (set)) == x))
743 rtx src = SET_SRC (set);
745 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
746 /* If X is narrower than a word and SRC is a non-negative
747 constant that would appear negative in the mode of X,
748 sign-extend it for use in reg_nonzero_bits because some
749 machines (maybe most) will actually do the sign-extension
750 and this is the conservative approach.
752 ??? For 2.5, try to tighten up the MD files in this regard
753 instead of this kludge. */
755 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
756 && GET_CODE (src) == CONST_INT
758 && 0 != (INTVAL (src)
760 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
761 src = GEN_INT (INTVAL (src)
762 | ((HOST_WIDE_INT) (-1)
763 << GET_MODE_BITSIZE (GET_MODE (x))));
766 reg_nonzero_bits[REGNO (x)]
767 |= nonzero_bits (src, nonzero_bits_mode);
768 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
769 if (reg_sign_bit_copies[REGNO (x)] == 0
770 || reg_sign_bit_copies[REGNO (x)] > num)
771 reg_sign_bit_copies[REGNO (x)] = num;
775 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
776 reg_sign_bit_copies[REGNO (x)] = 0;
781 /* See if INSN can be combined into I3. PRED and SUCC are optionally
782 insns that were previously combined into I3 or that will be combined
783 into the merger of INSN and I3.
785 Return 0 if the combination is not allowed for any reason.
787 If the combination is allowed, *PDEST will be set to the single
788 destination of INSN and *PSRC to the single source, and this function
792 can_combine_p (insn, i3, pred, succ, pdest, psrc)
799 rtx set = 0, src, dest;
801 int all_adjacent = (succ ? (next_active_insn (insn) == succ
802 && next_active_insn (succ) == i3)
803 : next_active_insn (insn) == i3);
805 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
806 or a PARALLEL consisting of such a SET and CLOBBERs.
808 If INSN has CLOBBER parallel parts, ignore them for our processing.
809 By definition, these happen during the execution of the insn. When it
810 is merged with another insn, all bets are off. If they are, in fact,
811 needed and aren't also supplied in I3, they may be added by
812 recog_for_combine. Otherwise, it won't match.
814 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
817 Get the source and destination of INSN. If more than one, can't
820 if (GET_CODE (PATTERN (insn)) == SET)
821 set = PATTERN (insn);
822 else if (GET_CODE (PATTERN (insn)) == PARALLEL
823 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
825 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
827 rtx elt = XVECEXP (PATTERN (insn), 0, i);
829 switch (GET_CODE (elt))
831 /* We can ignore CLOBBERs. */
836 /* Ignore SETs whose result isn't used but not those that
837 have side-effects. */
838 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
839 && ! side_effects_p (elt))
842 /* If we have already found a SET, this is a second one and
843 so we cannot combine with this insn. */
851 /* Anything else means we can't combine. */
857 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
858 so don't do anything with it. */
859 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
868 set = expand_field_assignment (set);
869 src = SET_SRC (set), dest = SET_DEST (set);
871 /* Don't eliminate a store in the stack pointer. */
872 if (dest == stack_pointer_rtx
873 /* If we couldn't eliminate a field assignment, we can't combine. */
874 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
875 /* Don't combine with an insn that sets a register to itself if it has
876 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
877 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
878 /* Can't merge a function call. */
879 || GET_CODE (src) == CALL
880 /* Don't substitute into an incremented register. */
881 || FIND_REG_INC_NOTE (i3, dest)
882 || (succ && FIND_REG_INC_NOTE (succ, dest))
883 /* Don't combine the end of a libcall into anything. */
884 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
885 /* Make sure that DEST is not used after SUCC but before I3. */
886 || (succ && ! all_adjacent
887 && reg_used_between_p (dest, succ, i3))
888 /* Make sure that the value that is to be substituted for the register
889 does not use any registers whose values alter in between. However,
890 If the insns are adjacent, a use can't cross a set even though we
891 think it might (this can happen for a sequence of insns each setting
892 the same destination; reg_last_set of that register might point to
893 a NOTE). If INSN has a REG_EQUIV note, the register is always
894 equivalent to the memory so the substitution is valid even if there
895 are intervening stores. Also, don't move a volatile asm or
896 UNSPEC_VOLATILE across any other insns. */
898 && (((GET_CODE (src) != MEM
899 || ! find_reg_note (insn, REG_EQUIV, src))
900 && use_crosses_set_p (src, INSN_CUID (insn)))
901 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
902 || GET_CODE (src) == UNSPEC_VOLATILE))
903 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
904 better register allocation by not doing the combine. */
905 || find_reg_note (i3, REG_NO_CONFLICT, dest)
906 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
907 /* Don't combine across a CALL_INSN, because that would possibly
908 change whether the life span of some REGs crosses calls or not,
909 and it is a pain to update that information.
910 Exception: if source is a constant, moving it later can't hurt.
911 Accept that special case, because it helps -fforce-addr a lot. */
912 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
915 /* DEST must either be a REG or CC0. */
916 if (GET_CODE (dest) == REG)
918 /* If register alignment is being enforced for multi-word items in all
919 cases except for parameters, it is possible to have a register copy
920 insn referencing a hard register that is not allowed to contain the
921 mode being copied and which would not be valid as an operand of most
922 insns. Eliminate this problem by not combining with such an insn.
924 Also, on some machines we don't want to extend the life of a hard
927 if (GET_CODE (src) == REG
928 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
929 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
930 /* Don't extend the life of a hard register unless it is
931 user variable (if we have few registers) or it can't
932 fit into the desired register (meaning something special
934 || (REGNO (src) < FIRST_PSEUDO_REGISTER
935 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
936 #ifdef SMALL_REGISTER_CLASSES
937 || ! REG_USERVAR_P (src)
942 else if (GET_CODE (dest) != CC0)
945 /* Don't substitute for a register intended as a clobberable operand.
946 Similarly, don't substitute an expression containing a register that
947 will be clobbered in I3. */
948 if (GET_CODE (PATTERN (i3)) == PARALLEL)
949 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
950 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
951 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
953 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
956 /* If INSN contains anything volatile, or is an `asm' (whether volatile
957 or not), reject, unless nothing volatile comes between it and I3,
958 with the exception of SUCC. */
960 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
961 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
962 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
963 && p != succ && volatile_refs_p (PATTERN (p)))
966 /* If there are any volatile insns between INSN and I3, reject, because
967 they might affect machine state. */
969 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
970 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
971 && p != succ && volatile_insn_p (PATTERN (p)))
974 /* If INSN or I2 contains an autoincrement or autodecrement,
975 make sure that register is not used between there and I3,
976 and not already used in I3 either.
977 Also insist that I3 not be a jump; if it were one
978 and the incremented register were spilled, we would lose. */
981 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
982 if (REG_NOTE_KIND (link) == REG_INC
983 && (GET_CODE (i3) == JUMP_INSN
984 || reg_used_between_p (XEXP (link, 0), insn, i3)
985 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
990 /* Don't combine an insn that follows a CC0-setting insn.
991 An insn that uses CC0 must not be separated from the one that sets it.
992 We do, however, allow I2 to follow a CC0-setting insn if that insn
993 is passed as I1; in that case it will be deleted also.
994 We also allow combining in this case if all the insns are adjacent
995 because that would leave the two CC0 insns adjacent as well.
996 It would be more logical to test whether CC0 occurs inside I1 or I2,
997 but that would be much slower, and this ought to be equivalent. */
999 p = prev_nonnote_insn (insn);
1000 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1005 /* If we get here, we have passed all the tests and the combination is
1014 /* LOC is the location within I3 that contains its pattern or the component
1015 of a PARALLEL of the pattern. We validate that it is valid for combining.
1017 One problem is if I3 modifies its output, as opposed to replacing it
1018 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1019 so would produce an insn that is not equivalent to the original insns.
1023 (set (reg:DI 101) (reg:DI 100))
1024 (set (subreg:SI (reg:DI 101) 0) <foo>)
1026 This is NOT equivalent to:
1028 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1029 (set (reg:DI 101) (reg:DI 100))])
1031 Not only does this modify 100 (in which case it might still be valid
1032 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1034 We can also run into a problem if I2 sets a register that I1
1035 uses and I1 gets directly substituted into I3 (not via I2). In that
1036 case, we would be getting the wrong value of I2DEST into I3, so we
1037 must reject the combination. This case occurs when I2 and I1 both
1038 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1039 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1040 of a SET must prevent combination from occurring.
1042 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1043 if the destination of a SET is a hard register that isn't a user
1046 Before doing the above check, we first try to expand a field assignment
1047 into a set of logical operations.
1049 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1050 we place a register that is both set and used within I3. If more than one
1051 such register is detected, we fail.
1053 Return 1 if the combination is valid, zero otherwise. */
1056 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1062 rtx *pi3dest_killed;
1066 if (GET_CODE (x) == SET)
1068 rtx set = expand_field_assignment (x);
1069 rtx dest = SET_DEST (set);
1070 rtx src = SET_SRC (set);
1071 rtx inner_dest = dest, inner_src = src;
1075 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1076 || GET_CODE (inner_dest) == SUBREG
1077 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1078 inner_dest = XEXP (inner_dest, 0);
1080 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1083 while (GET_CODE (inner_src) == STRICT_LOW_PART
1084 || GET_CODE (inner_src) == SUBREG
1085 || GET_CODE (inner_src) == ZERO_EXTRACT)
1086 inner_src = XEXP (inner_src, 0);
1088 /* If it is better that two different modes keep two different pseudos,
1089 avoid combining them. This avoids producing the following pattern
1091 (set (subreg:SI (reg/v:QI 21) 0)
1092 (lshiftrt:SI (reg/v:SI 20)
1094 If that were made, reload could not handle the pair of
1095 reg 20/21, since it would try to get any GENERAL_REGS
1096 but some of them don't handle QImode. */
1098 if (rtx_equal_p (inner_src, i2dest)
1099 && GET_CODE (inner_dest) == REG
1100 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1104 /* Check for the case where I3 modifies its output, as
1106 if ((inner_dest != dest
1107 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1108 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1109 /* This is the same test done in can_combine_p except that we
1110 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1112 || (GET_CODE (inner_dest) == REG
1113 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1114 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1115 GET_MODE (inner_dest))
1116 #ifdef SMALL_REGISTER_CLASSES
1117 || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest))
1120 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1123 /* If DEST is used in I3, it is being killed in this insn,
1124 so record that for later.
1125 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1126 STACK_POINTER_REGNUM, since these are always considered to be
1127 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1128 if (pi3dest_killed && GET_CODE (dest) == REG
1129 && reg_referenced_p (dest, PATTERN (i3))
1130 && REGNO (dest) != FRAME_POINTER_REGNUM
1131 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1132 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1134 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1135 && (REGNO (dest) != ARG_POINTER_REGNUM
1136 || ! fixed_regs [REGNO (dest)])
1138 && REGNO (dest) != STACK_POINTER_REGNUM)
1140 if (*pi3dest_killed)
1143 *pi3dest_killed = dest;
1147 else if (GET_CODE (x) == PARALLEL)
1151 for (i = 0; i < XVECLEN (x, 0); i++)
1152 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1153 i1_not_in_src, pi3dest_killed))
1160 /* Try to combine the insns I1 and I2 into I3.
1161 Here I1 and I2 appear earlier than I3.
1162 I1 can be zero; then we combine just I2 into I3.
1164 It we are combining three insns and the resulting insn is not recognized,
1165 try splitting it into two insns. If that happens, I2 and I3 are retained
1166 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1169 Return 0 if the combination does not work. Then nothing is changed.
1170 If we did the combination, return the insn at which combine should
1174 try_combine (i3, i2, i1)
1175 register rtx i3, i2, i1;
1177 /* New patterns for I3 and I3, respectively. */
1178 rtx newpat, newi2pat = 0;
1179 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1180 int added_sets_1, added_sets_2;
1181 /* Total number of SETs to put into I3. */
1183 /* Nonzero is I2's body now appears in I3. */
1185 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1186 int insn_code_number, i2_code_number, other_code_number;
1187 /* Contains I3 if the destination of I3 is used in its source, which means
1188 that the old life of I3 is being killed. If that usage is placed into
1189 I2 and not in I3, a REG_DEAD note must be made. */
1190 rtx i3dest_killed = 0;
1191 /* SET_DEST and SET_SRC of I2 and I1. */
1192 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1193 /* PATTERN (I2), or a copy of it in certain cases. */
1195 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1196 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1197 int i1_feeds_i3 = 0;
1198 /* Notes that must be added to REG_NOTES in I3 and I2. */
1199 rtx new_i3_notes, new_i2_notes;
1200 /* Notes that we substituted I3 into I2 instead of the normal case. */
1201 int i3_subst_into_i2 = 0;
1208 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1209 This can occur when flow deletes an insn that it has merged into an
1210 auto-increment address. We also can't do anything if I3 has a
1211 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1214 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1215 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1216 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1217 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1222 undobuf.num_undo = previous_num_undos = 0;
1223 undobuf.other_insn = 0;
1225 /* Save the current high-water-mark so we can free storage if we didn't
1226 accept this combination. */
1227 undobuf.storage = (char *) oballoc (0);
1229 /* Reset the hard register usage information. */
1230 CLEAR_HARD_REG_SET (newpat_used_regs);
1232 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1233 code below, set I1 to be the earlier of the two insns. */
1234 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1235 temp = i1, i1 = i2, i2 = temp;
1237 subst_prev_insn = 0;
1238 added_links_insn = 0;
1240 /* First check for one important special-case that the code below will
1241 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1242 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1243 we may be able to replace that destination with the destination of I3.
1244 This occurs in the common code where we compute both a quotient and
1245 remainder into a structure, in which case we want to do the computation
1246 directly into the structure to avoid register-register copies.
1248 We make very conservative checks below and only try to handle the
1249 most common cases of this. For example, we only handle the case
1250 where I2 and I3 are adjacent to avoid making difficult register
1253 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1254 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1255 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1256 #ifdef SMALL_REGISTER_CLASSES
1257 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1258 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1259 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1261 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1262 && GET_CODE (PATTERN (i2)) == PARALLEL
1263 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1264 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1265 below would need to check what is inside (and reg_overlap_mentioned_p
1266 doesn't support those codes anyway). Don't allow those destinations;
1267 the resulting insn isn't likely to be recognized anyway. */
1268 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1269 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1270 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1271 SET_DEST (PATTERN (i3)))
1272 && next_real_insn (i2) == i3)
1274 rtx p2 = PATTERN (i2);
1276 /* Make sure that the destination of I3,
1277 which we are going to substitute into one output of I2,
1278 is not used within another output of I2. We must avoid making this:
1279 (parallel [(set (mem (reg 69)) ...)
1280 (set (reg 69) ...)])
1281 which is not well-defined as to order of actions.
1282 (Besides, reload can't handle output reloads for this.)
1284 The problem can also happen if the dest of I3 is a memory ref,
1285 if another dest in I2 is an indirect memory ref. */
1286 for (i = 0; i < XVECLEN (p2, 0); i++)
1287 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1288 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1289 SET_DEST (XVECEXP (p2, 0, i))))
1292 if (i == XVECLEN (p2, 0))
1293 for (i = 0; i < XVECLEN (p2, 0); i++)
1294 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1299 subst_low_cuid = INSN_CUID (i2);
1301 added_sets_2 = added_sets_1 = 0;
1302 i2dest = SET_SRC (PATTERN (i3));
1304 /* Replace the dest in I2 with our dest and make the resulting
1305 insn the new pattern for I3. Then skip to where we
1306 validate the pattern. Everything was set up above. */
1307 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1308 SET_DEST (PATTERN (i3)));
1311 i3_subst_into_i2 = 1;
1312 goto validate_replacement;
1317 /* If we have no I1 and I2 looks like:
1318 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1320 make up a dummy I1 that is
1323 (set (reg:CC X) (compare:CC Y (const_int 0)))
1325 (We can ignore any trailing CLOBBERs.)
1327 This undoes a previous combination and allows us to match a branch-and-
1330 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1331 && XVECLEN (PATTERN (i2), 0) >= 2
1332 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1333 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1335 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1336 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1337 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1338 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1339 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1340 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1342 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1343 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1348 /* We make I1 with the same INSN_UID as I2. This gives it
1349 the same INSN_CUID for value tracking. Our fake I1 will
1350 never appear in the insn stream so giving it the same INSN_UID
1351 as I2 will not cause a problem. */
1353 subst_prev_insn = i1
1354 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1355 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1357 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1358 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1359 SET_DEST (PATTERN (i1)));
1364 /* Verify that I2 and I1 are valid for combining. */
1365 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1366 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1372 /* Record whether I2DEST is used in I2SRC and similarly for the other
1373 cases. Knowing this will help in register status updating below. */
1374 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1375 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1376 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1378 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1380 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1382 /* Ensure that I3's pattern can be the destination of combines. */
1383 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1384 i1 && i2dest_in_i1src && i1_feeds_i3,
1391 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1392 We used to do this EXCEPT in one case: I3 has a post-inc in an
1393 output operand. However, that exception can give rise to insns like
1395 which is a famous insn on the PDP-11 where the value of r3 used as the
1396 source was model-dependent. Avoid this sort of thing. */
1399 if (!(GET_CODE (PATTERN (i3)) == SET
1400 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1401 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1402 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1403 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1404 /* It's not the exception. */
1407 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1408 if (REG_NOTE_KIND (link) == REG_INC
1409 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1411 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1418 /* See if the SETs in I1 or I2 need to be kept around in the merged
1419 instruction: whenever the value set there is still needed past I3.
1420 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1422 For the SET in I1, we have two cases: If I1 and I2 independently
1423 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1424 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1425 in I1 needs to be kept around unless I1DEST dies or is set in either
1426 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1427 I1DEST. If so, we know I1 feeds into I2. */
1429 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1432 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1433 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1435 /* If the set in I2 needs to be kept around, we must make a copy of
1436 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1437 PATTERN (I2), we are only substituting for the original I1DEST, not into
1438 an already-substituted copy. This also prevents making self-referential
1439 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1442 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1443 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1447 i2pat = copy_rtx (i2pat);
1451 /* Substitute in the latest insn for the regs set by the earlier ones. */
1453 maxreg = max_reg_num ();
1457 /* It is possible that the source of I2 or I1 may be performing an
1458 unneeded operation, such as a ZERO_EXTEND of something that is known
1459 to have the high part zero. Handle that case by letting subst look at
1460 the innermost one of them.
1462 Another way to do this would be to have a function that tries to
1463 simplify a single insn instead of merging two or more insns. We don't
1464 do this because of the potential of infinite loops and because
1465 of the potential extra memory required. However, doing it the way
1466 we are is a bit of a kludge and doesn't catch all cases.
1468 But only do this if -fexpensive-optimizations since it slows things down
1469 and doesn't usually win. */
1471 if (flag_expensive_optimizations)
1473 /* Pass pc_rtx so no substitutions are done, just simplifications.
1474 The cases that we are interested in here do not involve the few
1475 cases were is_replaced is checked. */
1478 subst_low_cuid = INSN_CUID (i1);
1479 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1483 subst_low_cuid = INSN_CUID (i2);
1484 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1487 previous_num_undos = undobuf.num_undo;
1491 /* Many machines that don't use CC0 have insns that can both perform an
1492 arithmetic operation and set the condition code. These operations will
1493 be represented as a PARALLEL with the first element of the vector
1494 being a COMPARE of an arithmetic operation with the constant zero.
1495 The second element of the vector will set some pseudo to the result
1496 of the same arithmetic operation. If we simplify the COMPARE, we won't
1497 match such a pattern and so will generate an extra insn. Here we test
1498 for this case, where both the comparison and the operation result are
1499 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1500 I2SRC. Later we will make the PARALLEL that contains I2. */
1502 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1503 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1504 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1505 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1508 enum machine_mode compare_mode;
1510 newpat = PATTERN (i3);
1511 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1515 #ifdef EXTRA_CC_MODES
1516 /* See if a COMPARE with the operand we substituted in should be done
1517 with the mode that is currently being used. If not, do the same
1518 processing we do in `subst' for a SET; namely, if the destination
1519 is used only once, try to replace it with a register of the proper
1520 mode and also replace the COMPARE. */
1521 if (undobuf.other_insn == 0
1522 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1523 &undobuf.other_insn))
1524 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1526 != GET_MODE (SET_DEST (newpat))))
1528 int regno = REGNO (SET_DEST (newpat));
1529 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1531 if (regno < FIRST_PSEUDO_REGISTER
1532 || (reg_n_sets[regno] == 1 && ! added_sets_2
1533 && ! REG_USERVAR_P (SET_DEST (newpat))))
1535 if (regno >= FIRST_PSEUDO_REGISTER)
1536 SUBST (regno_reg_rtx[regno], new_dest);
1538 SUBST (SET_DEST (newpat), new_dest);
1539 SUBST (XEXP (*cc_use, 0), new_dest);
1540 SUBST (SET_SRC (newpat),
1541 gen_rtx_combine (COMPARE, compare_mode,
1542 i2src, const0_rtx));
1545 undobuf.other_insn = 0;
1552 n_occurrences = 0; /* `subst' counts here */
1554 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1555 need to make a unique copy of I2SRC each time we substitute it
1556 to avoid self-referential rtl. */
1558 subst_low_cuid = INSN_CUID (i2);
1559 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1560 ! i1_feeds_i3 && i1dest_in_i1src);
1561 previous_num_undos = undobuf.num_undo;
1563 /* Record whether i2's body now appears within i3's body. */
1564 i2_is_used = n_occurrences;
1567 /* If we already got a failure, don't try to do more. Otherwise,
1568 try to substitute in I1 if we have it. */
1570 if (i1 && GET_CODE (newpat) != CLOBBER)
1572 /* Before we can do this substitution, we must redo the test done
1573 above (see detailed comments there) that ensures that I1DEST
1574 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1576 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1584 subst_low_cuid = INSN_CUID (i1);
1585 newpat = subst (newpat, i1dest, i1src, 0, 0);
1586 previous_num_undos = undobuf.num_undo;
1589 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1590 to count all the ways that I2SRC and I1SRC can be used. */
1591 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1592 && i2_is_used + added_sets_2 > 1)
1593 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1594 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1596 /* Fail if we tried to make a new register (we used to abort, but there's
1597 really no reason to). */
1598 || max_reg_num () != maxreg
1599 /* Fail if we couldn't do something and have a CLOBBER. */
1600 || GET_CODE (newpat) == CLOBBER)
1606 /* If the actions of the earlier insns must be kept
1607 in addition to substituting them into the latest one,
1608 we must make a new PARALLEL for the latest insn
1609 to hold additional the SETs. */
1611 if (added_sets_1 || added_sets_2)
1615 if (GET_CODE (newpat) == PARALLEL)
1617 rtvec old = XVEC (newpat, 0);
1618 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1619 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1620 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1621 sizeof (old->elem[0]) * old->num_elem);
1626 total_sets = 1 + added_sets_1 + added_sets_2;
1627 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1628 XVECEXP (newpat, 0, 0) = old;
1632 XVECEXP (newpat, 0, --total_sets)
1633 = (GET_CODE (PATTERN (i1)) == PARALLEL
1634 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1638 /* If there is no I1, use I2's body as is. We used to also not do
1639 the subst call below if I2 was substituted into I3,
1640 but that could lose a simplification. */
1642 XVECEXP (newpat, 0, --total_sets) = i2pat;
1644 /* See comment where i2pat is assigned. */
1645 XVECEXP (newpat, 0, --total_sets)
1646 = subst (i2pat, i1dest, i1src, 0, 0);
1650 /* We come here when we are replacing a destination in I2 with the
1651 destination of I3. */
1652 validate_replacement:
1654 /* Note which hard regs this insn has as inputs. */
1655 mark_used_regs_combine (newpat);
1657 /* Is the result of combination a valid instruction? */
1658 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1660 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1661 the second SET's destination is a register that is unused. In that case,
1662 we just need the first SET. This can occur when simplifying a divmod
1663 insn. We *must* test for this case here because the code below that
1664 splits two independent SETs doesn't handle this case correctly when it
1665 updates the register status. Also check the case where the first
1666 SET's destination is unused. That would not cause incorrect code, but
1667 does cause an unneeded insn to remain. */
1669 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1670 && XVECLEN (newpat, 0) == 2
1671 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1672 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1673 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1674 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1675 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1676 && asm_noperands (newpat) < 0)
1678 newpat = XVECEXP (newpat, 0, 0);
1679 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1682 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1683 && XVECLEN (newpat, 0) == 2
1684 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1685 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1686 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1687 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1688 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1689 && asm_noperands (newpat) < 0)
1691 newpat = XVECEXP (newpat, 0, 1);
1692 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1695 /* See if this is an XOR. If so, perhaps the problem is that the
1696 constant is out of range. Replace it with a complemented XOR with
1697 a complemented constant; it might be in range. */
1699 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1700 && GET_CODE (SET_SRC (newpat)) == XOR
1701 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1702 && ((temp = simplify_unary_operation (NOT,
1703 GET_MODE (SET_SRC (newpat)),
1704 XEXP (SET_SRC (newpat), 1),
1705 GET_MODE (SET_SRC (newpat))))
1708 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1710 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1711 gen_unary (NOT, i_mode,
1712 gen_binary (XOR, i_mode,
1713 XEXP (SET_SRC (newpat), 0),
1716 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1717 if (insn_code_number >= 0)
1721 /* If we were combining three insns and the result is a simple SET
1722 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1723 insns. There are two ways to do this. It can be split using a
1724 machine-specific method (like when you have an addition of a large
1725 constant) or by combine in the function find_split_point. */
1727 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1728 && asm_noperands (newpat) < 0)
1730 rtx m_split, *split;
1731 rtx ni2dest = i2dest;
1733 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1734 use I2DEST as a scratch register will help. In the latter case,
1735 convert I2DEST to the mode of the source of NEWPAT if we can. */
1737 m_split = split_insns (newpat, i3);
1739 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1740 inputs of NEWPAT. */
1742 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1743 possible to try that as a scratch reg. This would require adding
1744 more code to make it work though. */
1746 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1748 /* If I2DEST is a hard register or the only use of a pseudo,
1749 we can change its mode. */
1750 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1751 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1752 && GET_CODE (i2dest) == REG
1753 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1754 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1755 && ! REG_USERVAR_P (i2dest))))
1756 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1759 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1760 gen_rtvec (2, newpat,
1767 if (m_split && GET_CODE (m_split) == SEQUENCE
1768 && XVECLEN (m_split, 0) == 2
1769 && (next_real_insn (i2) == i3
1770 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1774 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1775 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1777 i3set = single_set (XVECEXP (m_split, 0, 1));
1778 i2set = single_set (XVECEXP (m_split, 0, 0));
1780 /* In case we changed the mode of I2DEST, replace it in the
1781 pseudo-register table here. We can't do it above in case this
1782 code doesn't get executed and we do a split the other way. */
1784 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1785 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1787 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1789 /* If I2 or I3 has multiple SETs, we won't know how to track
1790 register status, so don't use these insns. */
1792 if (i2_code_number >= 0 && i2set && i3set)
1793 insn_code_number = recog_for_combine (&newi3pat, i3,
1796 if (insn_code_number >= 0)
1799 /* It is possible that both insns now set the destination of I3.
1800 If so, we must show an extra use of it. */
1802 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1803 && GET_CODE (SET_DEST (i2set)) == REG
1804 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1805 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1808 /* If we can split it and use I2DEST, go ahead and see if that
1809 helps things be recognized. Verify that none of the registers
1810 are set between I2 and I3. */
1811 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1813 && GET_CODE (i2dest) == REG
1815 /* We need I2DEST in the proper mode. If it is a hard register
1816 or the only use of a pseudo, we can change its mode. */
1817 && (GET_MODE (*split) == GET_MODE (i2dest)
1818 || GET_MODE (*split) == VOIDmode
1819 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1820 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1821 && ! REG_USERVAR_P (i2dest)))
1822 && (next_real_insn (i2) == i3
1823 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1824 /* We can't overwrite I2DEST if its value is still used by
1826 && ! reg_referenced_p (i2dest, newpat))
1828 rtx newdest = i2dest;
1830 /* Get NEWDEST as a register in the proper mode. We have already
1831 validated that we can do this. */
1832 if (GET_MODE (i2dest) != GET_MODE (*split)
1833 && GET_MODE (*split) != VOIDmode)
1835 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1837 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1838 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1841 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1842 an ASHIFT. This can occur if it was inside a PLUS and hence
1843 appeared to be a memory address. This is a kludge. */
1844 if (GET_CODE (*split) == MULT
1845 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1846 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1847 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1848 XEXP (*split, 0), GEN_INT (i)));
1850 #ifdef INSN_SCHEDULING
1851 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1852 be written as a ZERO_EXTEND. */
1853 if (GET_CODE (*split) == SUBREG
1854 && GET_CODE (SUBREG_REG (*split)) == MEM)
1855 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1859 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1860 SUBST (*split, newdest);
1861 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1862 if (i2_code_number >= 0)
1863 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1867 /* Check for a case where we loaded from memory in a narrow mode and
1868 then sign extended it, but we need both registers. In that case,
1869 we have a PARALLEL with both loads from the same memory location.
1870 We can split this into a load from memory followed by a register-register
1871 copy. This saves at least one insn, more if register allocation can
1874 We cannot do this if the destination of the second assignment is
1875 a register that we have already assumed is zero-extended. Similarly
1876 for a SUBREG of such a register. */
1878 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1879 && GET_CODE (newpat) == PARALLEL
1880 && XVECLEN (newpat, 0) == 2
1881 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1882 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1883 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1884 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1885 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1886 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1888 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1889 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1890 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1891 (GET_CODE (temp) == REG
1892 && reg_nonzero_bits[REGNO (temp)] != 0
1893 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1894 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1895 && (reg_nonzero_bits[REGNO (temp)]
1896 != GET_MODE_MASK (word_mode))))
1897 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1898 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1899 (GET_CODE (temp) == REG
1900 && reg_nonzero_bits[REGNO (temp)] != 0
1901 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1902 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1903 && (reg_nonzero_bits[REGNO (temp)]
1904 != GET_MODE_MASK (word_mode)))))
1905 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1906 SET_SRC (XVECEXP (newpat, 0, 1)))
1907 && ! find_reg_note (i3, REG_UNUSED,
1908 SET_DEST (XVECEXP (newpat, 0, 0))))
1912 newi2pat = XVECEXP (newpat, 0, 0);
1913 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1914 newpat = XVECEXP (newpat, 0, 1);
1915 SUBST (SET_SRC (newpat),
1916 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1917 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1918 if (i2_code_number >= 0)
1919 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1921 if (insn_code_number >= 0)
1926 /* If we will be able to accept this, we have made a change to the
1927 destination of I3. This can invalidate a LOG_LINKS pointing
1928 to I3. No other part of combine.c makes such a transformation.
1930 The new I3 will have a destination that was previously the
1931 destination of I1 or I2 and which was used in i2 or I3. Call
1932 distribute_links to make a LOG_LINK from the next use of
1933 that destination. */
1935 PATTERN (i3) = newpat;
1936 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1938 /* I3 now uses what used to be its destination and which is
1939 now I2's destination. That means we need a LOG_LINK from
1940 I3 to I2. But we used to have one, so we still will.
1942 However, some later insn might be using I2's dest and have
1943 a LOG_LINK pointing at I3. We must remove this link.
1944 The simplest way to remove the link is to point it at I1,
1945 which we know will be a NOTE. */
1947 for (insn = NEXT_INSN (i3);
1948 insn && (this_basic_block == n_basic_blocks - 1
1949 || insn != basic_block_head[this_basic_block + 1]);
1950 insn = NEXT_INSN (insn))
1952 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1953 && reg_referenced_p (ni2dest, PATTERN (insn)))
1955 for (link = LOG_LINKS (insn); link;
1956 link = XEXP (link, 1))
1957 if (XEXP (link, 0) == i3)
1958 XEXP (link, 0) = i1;
1966 /* Similarly, check for a case where we have a PARALLEL of two independent
1967 SETs but we started with three insns. In this case, we can do the sets
1968 as two separate insns. This case occurs when some SET allows two
1969 other insns to combine, but the destination of that SET is still live. */
1971 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1972 && GET_CODE (newpat) == PARALLEL
1973 && XVECLEN (newpat, 0) == 2
1974 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1975 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1976 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1977 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1978 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1979 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1980 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1982 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1983 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1984 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1985 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1986 XVECEXP (newpat, 0, 0))
1987 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1988 XVECEXP (newpat, 0, 1)))
1990 newi2pat = XVECEXP (newpat, 0, 1);
1991 newpat = XVECEXP (newpat, 0, 0);
1993 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1994 if (i2_code_number >= 0)
1995 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1998 /* If it still isn't recognized, fail and change things back the way they
2000 if ((insn_code_number < 0
2001 /* Is the result a reasonable ASM_OPERANDS? */
2002 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2008 /* If we had to change another insn, make sure it is valid also. */
2009 if (undobuf.other_insn)
2011 rtx other_pat = PATTERN (undobuf.other_insn);
2012 rtx new_other_notes;
2015 CLEAR_HARD_REG_SET (newpat_used_regs);
2017 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2020 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2026 PATTERN (undobuf.other_insn) = other_pat;
2028 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2029 are still valid. Then add any non-duplicate notes added by
2030 recog_for_combine. */
2031 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2033 next = XEXP (note, 1);
2035 if (REG_NOTE_KIND (note) == REG_UNUSED
2036 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2038 if (GET_CODE (XEXP (note, 0)) == REG)
2039 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2041 remove_note (undobuf.other_insn, note);
2045 for (note = new_other_notes; note; note = XEXP (note, 1))
2046 if (GET_CODE (XEXP (note, 0)) == REG)
2047 reg_n_deaths[REGNO (XEXP (note, 0))]++;
2049 distribute_notes (new_other_notes, undobuf.other_insn,
2050 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2053 /* We now know that we can do this combination. Merge the insns and
2054 update the status of registers and LOG_LINKS. */
2057 rtx i3notes, i2notes, i1notes = 0;
2058 rtx i3links, i2links, i1links = 0;
2061 /* Compute which registers we expect to eliminate. */
2062 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2064 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2066 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2068 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2069 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2071 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2073 /* Ensure that we do not have something that should not be shared but
2074 occurs multiple times in the new insns. Check this by first
2075 resetting all the `used' flags and then copying anything is shared. */
2077 reset_used_flags (i3notes);
2078 reset_used_flags (i2notes);
2079 reset_used_flags (i1notes);
2080 reset_used_flags (newpat);
2081 reset_used_flags (newi2pat);
2082 if (undobuf.other_insn)
2083 reset_used_flags (PATTERN (undobuf.other_insn));
2085 i3notes = copy_rtx_if_shared (i3notes);
2086 i2notes = copy_rtx_if_shared (i2notes);
2087 i1notes = copy_rtx_if_shared (i1notes);
2088 newpat = copy_rtx_if_shared (newpat);
2089 newi2pat = copy_rtx_if_shared (newi2pat);
2090 if (undobuf.other_insn)
2091 reset_used_flags (PATTERN (undobuf.other_insn));
2093 INSN_CODE (i3) = insn_code_number;
2094 PATTERN (i3) = newpat;
2095 if (undobuf.other_insn)
2096 INSN_CODE (undobuf.other_insn) = other_code_number;
2098 /* We had one special case above where I2 had more than one set and
2099 we replaced a destination of one of those sets with the destination
2100 of I3. In that case, we have to update LOG_LINKS of insns later
2101 in this basic block. Note that this (expensive) case is rare.
2103 Also, in this case, we must pretend that all REG_NOTEs for I2
2104 actually came from I3, so that REG_UNUSED notes from I2 will be
2105 properly handled. */
2107 if (i3_subst_into_i2)
2109 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2110 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2111 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2112 && ! find_reg_note (i2, REG_UNUSED,
2113 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2114 for (temp = NEXT_INSN (i2);
2115 temp && (this_basic_block == n_basic_blocks - 1
2116 || basic_block_head[this_basic_block] != temp);
2117 temp = NEXT_INSN (temp))
2118 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2119 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2120 if (XEXP (link, 0) == i2)
2121 XEXP (link, 0) = i3;
2126 while (XEXP (link, 1))
2127 link = XEXP (link, 1);
2128 XEXP (link, 1) = i2notes;
2142 INSN_CODE (i2) = i2_code_number;
2143 PATTERN (i2) = newi2pat;
2147 PUT_CODE (i2, NOTE);
2148 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2149 NOTE_SOURCE_FILE (i2) = 0;
2156 PUT_CODE (i1, NOTE);
2157 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2158 NOTE_SOURCE_FILE (i1) = 0;
2161 /* Get death notes for everything that is now used in either I3 or
2162 I2 and used to die in a previous insn. */
2164 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2166 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2168 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2170 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2173 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2176 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2179 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2182 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2183 know these are REG_UNUSED and want them to go to the desired insn,
2184 so we always pass it as i3. We have not counted the notes in
2185 reg_n_deaths yet, so we need to do so now. */
2187 if (newi2pat && new_i2_notes)
2189 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2190 if (GET_CODE (XEXP (temp, 0)) == REG)
2191 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2193 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2198 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2199 if (GET_CODE (XEXP (temp, 0)) == REG)
2200 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2202 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2205 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2206 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2207 Show an additional death due to the REG_DEAD note we make here. If
2208 we discard it in distribute_notes, we will decrement it again. */
2212 if (GET_CODE (i3dest_killed) == REG)
2213 reg_n_deaths[REGNO (i3dest_killed)]++;
2215 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2217 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2218 NULL_RTX, NULL_RTX);
2221 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2222 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2223 we passed I3 in that case, it might delete I2. */
2225 if (i2dest_in_i2src)
2227 if (GET_CODE (i2dest) == REG)
2228 reg_n_deaths[REGNO (i2dest)]++;
2230 if (newi2pat && reg_set_p (i2dest, newi2pat))
2231 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2232 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2234 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2235 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2236 NULL_RTX, NULL_RTX);
2239 if (i1dest_in_i1src)
2241 if (GET_CODE (i1dest) == REG)
2242 reg_n_deaths[REGNO (i1dest)]++;
2244 if (newi2pat && reg_set_p (i1dest, newi2pat))
2245 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2246 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2248 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2249 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2250 NULL_RTX, NULL_RTX);
2253 distribute_links (i3links);
2254 distribute_links (i2links);
2255 distribute_links (i1links);
2257 if (GET_CODE (i2dest) == REG)
2260 rtx i2_insn = 0, i2_val = 0, set;
2262 /* The insn that used to set this register doesn't exist, and
2263 this life of the register may not exist either. See if one of
2264 I3's links points to an insn that sets I2DEST. If it does,
2265 that is now the last known value for I2DEST. If we don't update
2266 this and I2 set the register to a value that depended on its old
2267 contents, we will get confused. If this insn is used, thing
2268 will be set correctly in combine_instructions. */
2270 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2271 if ((set = single_set (XEXP (link, 0))) != 0
2272 && rtx_equal_p (i2dest, SET_DEST (set)))
2273 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2275 record_value_for_reg (i2dest, i2_insn, i2_val);
2277 /* If the reg formerly set in I2 died only once and that was in I3,
2278 zero its use count so it won't make `reload' do any work. */
2279 if (! added_sets_2 && newi2pat == 0)
2281 regno = REGNO (i2dest);
2282 reg_n_sets[regno]--;
2283 if (reg_n_sets[regno] == 0
2284 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2285 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2286 reg_n_refs[regno] = 0;
2290 if (i1 && GET_CODE (i1dest) == REG)
2293 rtx i1_insn = 0, i1_val = 0, set;
2295 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2296 if ((set = single_set (XEXP (link, 0))) != 0
2297 && rtx_equal_p (i1dest, SET_DEST (set)))
2298 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2300 record_value_for_reg (i1dest, i1_insn, i1_val);
2302 regno = REGNO (i1dest);
2305 reg_n_sets[regno]--;
2306 if (reg_n_sets[regno] == 0
2307 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2308 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2309 reg_n_refs[regno] = 0;
2313 /* Update reg_nonzero_bits et al for any changes that may have been made
2316 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2318 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2320 /* If I3 is now an unconditional jump, ensure that it has a
2321 BARRIER following it since it may have initially been a
2322 conditional jump. It may also be the last nonnote insn. */
2324 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2325 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2326 || GET_CODE (temp) != BARRIER))
2327 emit_barrier_after (i3);
2330 combine_successes++;
2332 if (added_links_insn
2333 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2334 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2335 return added_links_insn;
2337 return newi2pat ? i2 : i3;
2340 /* Undo all the modifications recorded in undobuf. */
2346 if (undobuf.num_undo > MAX_UNDO)
2347 undobuf.num_undo = MAX_UNDO;
2348 for (i = undobuf.num_undo - 1; i >= 0; i--)
2350 if (undobuf.undo[i].is_int)
2351 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2353 *undobuf.undo[i].where.r = undobuf.undo[i].old_contents.r;
2357 obfree (undobuf.storage);
2358 undobuf.num_undo = 0;
2361 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2362 where we have an arithmetic expression and return that point. LOC will
2365 try_combine will call this function to see if an insn can be split into
2369 find_split_point (loc, insn)
2374 enum rtx_code code = GET_CODE (x);
2376 int len = 0, pos, unsignedp;
2379 /* First special-case some codes. */
2383 #ifdef INSN_SCHEDULING
2384 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2386 if (GET_CODE (SUBREG_REG (x)) == MEM)
2389 return find_split_point (&SUBREG_REG (x), insn);
2393 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2394 using LO_SUM and HIGH. */
2395 if (GET_CODE (XEXP (x, 0)) == CONST
2396 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2399 gen_rtx_combine (LO_SUM, Pmode,
2400 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2402 return &XEXP (XEXP (x, 0), 0);
2406 /* If we have a PLUS whose second operand is a constant and the
2407 address is not valid, perhaps will can split it up using
2408 the machine-specific way to split large constants. We use
2409 the first psuedo-reg (one of the virtual regs) as a placeholder;
2410 it will not remain in the result. */
2411 if (GET_CODE (XEXP (x, 0)) == PLUS
2412 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2413 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2415 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2416 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2419 /* This should have produced two insns, each of which sets our
2420 placeholder. If the source of the second is a valid address,
2421 we can make put both sources together and make a split point
2424 if (seq && XVECLEN (seq, 0) == 2
2425 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2426 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2427 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2428 && ! reg_mentioned_p (reg,
2429 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2430 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2431 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2432 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2433 && memory_address_p (GET_MODE (x),
2434 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2436 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2437 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2439 /* Replace the placeholder in SRC2 with SRC1. If we can
2440 find where in SRC2 it was placed, that can become our
2441 split point and we can replace this address with SRC2.
2442 Just try two obvious places. */
2444 src2 = replace_rtx (src2, reg, src1);
2446 if (XEXP (src2, 0) == src1)
2447 split = &XEXP (src2, 0);
2448 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2449 && XEXP (XEXP (src2, 0), 0) == src1)
2450 split = &XEXP (XEXP (src2, 0), 0);
2454 SUBST (XEXP (x, 0), src2);
2459 /* If that didn't work, perhaps the first operand is complex and
2460 needs to be computed separately, so make a split point there.
2461 This will occur on machines that just support REG + CONST
2462 and have a constant moved through some previous computation. */
2464 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2465 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2466 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2468 return &XEXP (XEXP (x, 0), 0);
2474 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2475 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2476 we need to put the operand into a register. So split at that
2479 if (SET_DEST (x) == cc0_rtx
2480 && GET_CODE (SET_SRC (x)) != COMPARE
2481 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2482 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2483 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2484 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2485 return &SET_SRC (x);
2488 /* See if we can split SET_SRC as it stands. */
2489 split = find_split_point (&SET_SRC (x), insn);
2490 if (split && split != &SET_SRC (x))
2493 /* See if this is a bitfield assignment with everything constant. If
2494 so, this is an IOR of an AND, so split it into that. */
2495 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2496 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2497 <= HOST_BITS_PER_WIDE_INT)
2498 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2499 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2500 && GET_CODE (SET_SRC (x)) == CONST_INT
2501 && ((INTVAL (XEXP (SET_DEST (x), 1))
2502 + INTVAL (XEXP (SET_DEST (x), 2)))
2503 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2504 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2506 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2507 int len = INTVAL (XEXP (SET_DEST (x), 1));
2508 int src = INTVAL (SET_SRC (x));
2509 rtx dest = XEXP (SET_DEST (x), 0);
2510 enum machine_mode mode = GET_MODE (dest);
2511 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2514 pos = GET_MODE_BITSIZE (mode) - len - pos;
2519 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2522 gen_binary (IOR, mode,
2523 gen_binary (AND, mode, dest,
2524 GEN_INT (~ (mask << pos)
2525 & GET_MODE_MASK (mode))),
2526 GEN_INT (src << pos)));
2528 SUBST (SET_DEST (x), dest);
2530 split = find_split_point (&SET_SRC (x), insn);
2531 if (split && split != &SET_SRC (x))
2535 /* Otherwise, see if this is an operation that we can split into two.
2536 If so, try to split that. */
2537 code = GET_CODE (SET_SRC (x));
2542 /* If we are AND'ing with a large constant that is only a single
2543 bit and the result is only being used in a context where we
2544 need to know if it is zero or non-zero, replace it with a bit
2545 extraction. This will avoid the large constant, which might
2546 have taken more than one insn to make. If the constant were
2547 not a valid argument to the AND but took only one insn to make,
2548 this is no worse, but if it took more than one insn, it will
2551 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2552 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2553 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2554 && GET_CODE (SET_DEST (x)) == REG
2555 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2556 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2557 && XEXP (*split, 0) == SET_DEST (x)
2558 && XEXP (*split, 1) == const0_rtx)
2561 make_extraction (GET_MODE (SET_DEST (x)),
2562 XEXP (SET_SRC (x), 0),
2563 pos, NULL_RTX, 1, 1, 0, 0));
2564 return find_split_point (loc, insn);
2569 inner = XEXP (SET_SRC (x), 0);
2571 len = GET_MODE_BITSIZE (GET_MODE (inner));
2577 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2578 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2580 inner = XEXP (SET_SRC (x), 0);
2581 len = INTVAL (XEXP (SET_SRC (x), 1));
2582 pos = INTVAL (XEXP (SET_SRC (x), 2));
2585 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2587 unsignedp = (code == ZERO_EXTRACT);
2592 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2594 enum machine_mode mode = GET_MODE (SET_SRC (x));
2596 /* For unsigned, we have a choice of a shift followed by an
2597 AND or two shifts. Use two shifts for field sizes where the
2598 constant might be too large. We assume here that we can
2599 always at least get 8-bit constants in an AND insn, which is
2600 true for every current RISC. */
2602 if (unsignedp && len <= 8)
2607 gen_rtx_combine (LSHIFTRT, mode,
2608 gen_lowpart_for_combine (mode, inner),
2610 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2612 split = find_split_point (&SET_SRC (x), insn);
2613 if (split && split != &SET_SRC (x))
2620 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2621 gen_rtx_combine (ASHIFT, mode,
2622 gen_lowpart_for_combine (mode, inner),
2623 GEN_INT (GET_MODE_BITSIZE (mode)
2625 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2627 split = find_split_point (&SET_SRC (x), insn);
2628 if (split && split != &SET_SRC (x))
2633 /* See if this is a simple operation with a constant as the second
2634 operand. It might be that this constant is out of range and hence
2635 could be used as a split point. */
2636 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2637 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2638 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2639 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2640 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2641 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2642 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2644 return &XEXP (SET_SRC (x), 1);
2646 /* Finally, see if this is a simple operation with its first operand
2647 not in a register. The operation might require this operand in a
2648 register, so return it as a split point. We can always do this
2649 because if the first operand were another operation, we would have
2650 already found it as a split point. */
2651 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2652 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2653 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2654 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2655 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2656 return &XEXP (SET_SRC (x), 0);
2662 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2663 it is better to write this as (not (ior A B)) so we can split it.
2664 Similarly for IOR. */
2665 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2668 gen_rtx_combine (NOT, GET_MODE (x),
2669 gen_rtx_combine (code == IOR ? AND : IOR,
2671 XEXP (XEXP (x, 0), 0),
2672 XEXP (XEXP (x, 1), 0))));
2673 return find_split_point (loc, insn);
2676 /* Many RISC machines have a large set of logical insns. If the
2677 second operand is a NOT, put it first so we will try to split the
2678 other operand first. */
2679 if (GET_CODE (XEXP (x, 1)) == NOT)
2681 rtx tem = XEXP (x, 0);
2682 SUBST (XEXP (x, 0), XEXP (x, 1));
2683 SUBST (XEXP (x, 1), tem);
2688 /* Otherwise, select our actions depending on our rtx class. */
2689 switch (GET_RTX_CLASS (code))
2691 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2693 split = find_split_point (&XEXP (x, 2), insn);
2696 /* ... fall through ... */
2700 split = find_split_point (&XEXP (x, 1), insn);
2703 /* ... fall through ... */
2705 /* Some machines have (and (shift ...) ...) insns. If X is not
2706 an AND, but XEXP (X, 0) is, use it as our split point. */
2707 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2708 return &XEXP (x, 0);
2710 split = find_split_point (&XEXP (x, 0), insn);
2716 /* Otherwise, we don't have a split point. */
2720 /* Throughout X, replace FROM with TO, and return the result.
2721 The result is TO if X is FROM;
2722 otherwise the result is X, but its contents may have been modified.
2723 If they were modified, a record was made in undobuf so that
2724 undo_all will (among other things) return X to its original state.
2726 If the number of changes necessary is too much to record to undo,
2727 the excess changes are not made, so the result is invalid.
2728 The changes already made can still be undone.
2729 undobuf.num_undo is incremented for such changes, so by testing that
2730 the caller can tell whether the result is valid.
2732 `n_occurrences' is incremented each time FROM is replaced.
2734 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2736 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2737 by copying if `n_occurrences' is non-zero. */
2740 subst (x, from, to, in_dest, unique_copy)
2741 register rtx x, from, to;
2745 register enum rtx_code code = GET_CODE (x);
2746 enum machine_mode op0_mode = VOIDmode;
2748 register int len, i;
2751 /* Two expressions are equal if they are identical copies of a shared
2752 RTX or if they are both registers with the same register number
2755 #define COMBINE_RTX_EQUAL_P(X,Y) \
2757 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2758 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2760 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2763 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2766 /* If X and FROM are the same register but different modes, they will
2767 not have been seen as equal above. However, flow.c will make a
2768 LOG_LINKS entry for that case. If we do nothing, we will try to
2769 rerecognize our original insn and, when it succeeds, we will
2770 delete the feeding insn, which is incorrect.
2772 So force this insn not to match in this (rare) case. */
2773 if (! in_dest && code == REG && GET_CODE (from) == REG
2774 && REGNO (x) == REGNO (from))
2775 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2777 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2778 of which may contain things that can be combined. */
2779 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2782 /* It is possible to have a subexpression appear twice in the insn.
2783 Suppose that FROM is a register that appears within TO.
2784 Then, after that subexpression has been scanned once by `subst',
2785 the second time it is scanned, TO may be found. If we were
2786 to scan TO here, we would find FROM within it and create a
2787 self-referent rtl structure which is completely wrong. */
2788 if (COMBINE_RTX_EQUAL_P (x, to))
2791 len = GET_RTX_LENGTH (code);
2792 fmt = GET_RTX_FORMAT (code);
2794 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2795 set up to skip this common case. All other cases where we want to
2796 suppress replacing something inside a SET_SRC are handled via the
2799 && (GET_CODE (SET_DEST (x)) == REG
2800 || GET_CODE (SET_DEST (x)) == CC0
2801 || GET_CODE (SET_DEST (x)) == PC))
2804 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2806 op0_mode = GET_MODE (XEXP (x, 0));
2808 for (i = 0; i < len; i++)
2813 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2815 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2817 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2822 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2824 /* If this substitution failed, this whole thing fails. */
2825 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2829 SUBST (XVECEXP (x, i, j), new);
2832 else if (fmt[i] == 'e')
2834 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2836 /* In general, don't install a subreg involving two modes not
2837 tieable. It can worsen register allocation, and can even
2838 make invalid reload insns, since the reg inside may need to
2839 be copied from in the outside mode, and that may be invalid
2840 if it is an fp reg copied in integer mode.
2842 We allow two exceptions to this: It is valid if it is inside
2843 another SUBREG and the mode of that SUBREG and the mode of
2844 the inside of TO is tieable and it is valid if X is a SET
2845 that copies FROM to CC0. */
2846 if (GET_CODE (to) == SUBREG
2847 && ! MODES_TIEABLE_P (GET_MODE (to),
2848 GET_MODE (SUBREG_REG (to)))
2849 && ! (code == SUBREG
2850 && MODES_TIEABLE_P (GET_MODE (x),
2851 GET_MODE (SUBREG_REG (to))))
2853 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2856 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2858 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2862 /* If we are in a SET_DEST, suppress most cases unless we
2863 have gone inside a MEM, in which case we want to
2864 simplify the address. We assume here that things that
2865 are actually part of the destination have their inner
2866 parts in the first expression. This is true for SUBREG,
2867 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2868 things aside from REG and MEM that should appear in a
2870 new = subst (XEXP (x, i), from, to,
2872 && (code == SUBREG || code == STRICT_LOW_PART
2873 || code == ZERO_EXTRACT))
2875 && i == 0), unique_copy);
2877 /* If we found that we will have to reject this combination,
2878 indicate that by returning the CLOBBER ourselves, rather than
2879 an expression containing it. This will speed things up as
2880 well as prevent accidents where two CLOBBERs are considered
2881 to be equal, thus producing an incorrect simplification. */
2883 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2886 SUBST (XEXP (x, i), new);
2890 /* Try to simplify X. If the simplification changed the code, it is likely
2891 that further simplification will help, so loop, but limit the number
2892 of repetitions that will be performed. */
2894 for (i = 0; i < 4; i++)
2896 /* If X is sufficiently simple, don't bother trying to do anything
2898 if (code != CONST_INT && code != REG && code != CLOBBER)
2899 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
2901 if (GET_CODE (x) == code)
2904 code = GET_CODE (x);
2906 /* We no longer know the original mode of operand 0 since we
2907 have changed the form of X) */
2908 op0_mode = VOIDmode;
2914 /* Simplify X, a piece of RTL. We just operate on the expression at the
2915 outer level; call `subst' to simplify recursively. Return the new
2918 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
2919 will be the iteration even if an expression with a code different from
2920 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
2923 simplify_rtx (x, op0_mode, last, in_dest)
2925 enum machine_mode op0_mode;
2929 enum rtx_code code = GET_CODE (x);
2930 enum machine_mode mode = GET_MODE (x);
2934 /* If this is a commutative operation, put a constant last and a complex
2935 expression first. We don't need to do this for comparisons here. */
2936 if (GET_RTX_CLASS (code) == 'c'
2937 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2938 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2939 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2940 || (GET_CODE (XEXP (x, 0)) == SUBREG
2941 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2942 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2945 SUBST (XEXP (x, 0), XEXP (x, 1));
2946 SUBST (XEXP (x, 1), temp);
2949 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2950 sign extension of a PLUS with a constant, reverse the order of the sign
2951 extension and the addition. Note that this not the same as the original
2952 code, but overflow is undefined for signed values. Also note that the
2953 PLUS will have been partially moved "inside" the sign-extension, so that
2954 the first operand of X will really look like:
2955 (ashiftrt (plus (ashift A C4) C5) C4).
2957 (plus (ashiftrt (ashift A C4) C2) C4)
2958 and replace the first operand of X with that expression. Later parts
2959 of this function may simplify the expression further.
2961 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2962 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2963 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2965 We do this to simplify address expressions. */
2967 if ((code == PLUS || code == MINUS || code == MULT)
2968 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2969 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2970 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2971 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2972 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2973 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2974 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2975 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2976 XEXP (XEXP (XEXP (x, 0), 0), 1),
2977 XEXP (XEXP (x, 0), 1))) != 0)
2980 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2981 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2982 INTVAL (XEXP (XEXP (x, 0), 1)));
2984 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2985 INTVAL (XEXP (XEXP (x, 0), 1)));
2987 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2990 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2991 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2992 things. Check for cases where both arms are testing the same
2995 Don't do anything if all operands are very simple. */
2997 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
2998 || GET_RTX_CLASS (code) == '<')
2999 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3000 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3001 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3003 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3004 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3005 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3007 || (GET_RTX_CLASS (code) == '1'
3008 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3009 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3010 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3013 rtx cond, true, false;
3015 cond = if_then_else_cond (x, &true, &false);
3018 rtx cop1 = const0_rtx;
3019 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3021 /* Simplify the alternative arms; this may collapse the true and
3022 false arms to store-flag values. */
3023 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3024 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3026 /* Restarting if we generate a store-flag expression will cause
3027 us to loop. Just drop through in this case. */
3029 /* If the result values are STORE_FLAG_VALUE and zero, we can
3030 just make the comparison operation. */
3031 if (true == const_true_rtx && false == const0_rtx)
3032 x = gen_binary (cond_code, mode, cond, cop1);
3033 else if (true == const0_rtx && false == const_true_rtx)
3034 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3036 /* Likewise, we can make the negate of a comparison operation
3037 if the result values are - STORE_FLAG_VALUE and zero. */
3038 else if (GET_CODE (true) == CONST_INT
3039 && INTVAL (true) == - STORE_FLAG_VALUE
3040 && false == const0_rtx)
3041 x = gen_unary (NEG, mode,
3042 gen_binary (cond_code, mode, cond, cop1));
3043 else if (GET_CODE (false) == CONST_INT
3044 && INTVAL (false) == - STORE_FLAG_VALUE
3045 && true == const0_rtx)
3046 x = gen_unary (NEG, mode,
3047 gen_binary (reverse_condition (cond_code),
3050 return gen_rtx (IF_THEN_ELSE, mode,
3051 gen_binary (cond_code, VOIDmode, cond, cop1),
3054 code = GET_CODE (x);
3055 op0_mode = VOIDmode;
3059 /* Try to fold this expression in case we have constants that weren't
3062 switch (GET_RTX_CLASS (code))
3065 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3068 temp = simplify_relational_operation (code, op0_mode,
3069 XEXP (x, 0), XEXP (x, 1));
3070 #ifdef FLOAT_STORE_FLAG_VALUE
3071 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3072 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3073 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3078 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3082 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3083 XEXP (x, 1), XEXP (x, 2));
3088 x = temp, code = GET_CODE (temp);
3090 /* First see if we can apply the inverse distributive law. */
3091 if (code == PLUS || code == MINUS
3092 || code == AND || code == IOR || code == XOR)
3094 x = apply_distributive_law (x);
3095 code = GET_CODE (x);
3098 /* If CODE is an associative operation not otherwise handled, see if we
3099 can associate some operands. This can win if they are constants or
3100 if they are logically related (i.e. (a & b) & a. */
3101 if ((code == PLUS || code == MINUS
3102 || code == MULT || code == AND || code == IOR || code == XOR
3103 || code == DIV || code == UDIV
3104 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3105 && INTEGRAL_MODE_P (mode))
3107 if (GET_CODE (XEXP (x, 0)) == code)
3109 rtx other = XEXP (XEXP (x, 0), 0);
3110 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3111 rtx inner_op1 = XEXP (x, 1);
3114 /* Make sure we pass the constant operand if any as the second
3115 one if this is a commutative operation. */
3116 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3118 rtx tem = inner_op0;
3119 inner_op0 = inner_op1;
3122 inner = simplify_binary_operation (code == MINUS ? PLUS
3123 : code == DIV ? MULT
3124 : code == UDIV ? MULT
3126 mode, inner_op0, inner_op1);
3128 /* For commutative operations, try the other pair if that one
3130 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3132 other = XEXP (XEXP (x, 0), 1);
3133 inner = simplify_binary_operation (code, mode,
3134 XEXP (XEXP (x, 0), 0),
3139 return gen_binary (code, mode, other, inner);
3143 /* A little bit of algebraic simplification here. */
3147 /* Ensure that our address has any ASHIFTs converted to MULT in case
3148 address-recognizing predicates are called later. */
3149 temp = make_compound_operation (XEXP (x, 0), MEM);
3150 SUBST (XEXP (x, 0), temp);
3154 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3155 is paradoxical. If we can't do that safely, then it becomes
3156 something nonsensical so that this combination won't take place. */
3158 if (GET_CODE (SUBREG_REG (x)) == MEM
3159 && (GET_MODE_SIZE (mode)
3160 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3162 rtx inner = SUBREG_REG (x);
3163 int endian_offset = 0;
3164 /* Don't change the mode of the MEM
3165 if that would change the meaning of the address. */
3166 if (MEM_VOLATILE_P (SUBREG_REG (x))
3167 || mode_dependent_address_p (XEXP (inner, 0)))
3168 return gen_rtx (CLOBBER, mode, const0_rtx);
3170 #if BYTES_BIG_ENDIAN
3171 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3172 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3173 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3174 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
3176 /* Note if the plus_constant doesn't make a valid address
3177 then this combination won't be accepted. */
3178 x = gen_rtx (MEM, mode,
3179 plus_constant (XEXP (inner, 0),
3180 (SUBREG_WORD (x) * UNITS_PER_WORD
3182 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3183 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3184 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3188 /* If we are in a SET_DEST, these other cases can't apply. */
3192 /* Changing mode twice with SUBREG => just change it once,
3193 or not at all if changing back to starting mode. */
3194 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3196 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3197 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3198 return SUBREG_REG (SUBREG_REG (x));
3200 SUBST_INT (SUBREG_WORD (x),
3201 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3202 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3205 /* SUBREG of a hard register => just change the register number
3206 and/or mode. If the hard register is not valid in that mode,
3207 suppress this combination. If the hard register is the stack,
3208 frame, or argument pointer, leave this as a SUBREG. */
3210 if (GET_CODE (SUBREG_REG (x)) == REG
3211 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3212 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3213 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3214 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3216 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3217 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3219 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3221 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3223 return gen_rtx (REG, mode,
3224 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3226 return gen_rtx (CLOBBER, mode, const0_rtx);
3229 /* For a constant, try to pick up the part we want. Handle a full
3230 word and low-order part. Only do this if we are narrowing
3231 the constant; if it is being widened, we have no idea what
3232 the extra bits will have been set to. */
3234 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3235 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3236 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3237 && GET_MODE_CLASS (mode) == MODE_INT)
3239 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3245 /* If we want a subreg of a constant, at offset 0,
3246 take the low bits. On a little-endian machine, that's
3247 always valid. On a big-endian machine, it's valid
3248 only if the constant's mode fits in one word. */
3249 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3250 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode)
3251 #if WORDS_BIG_ENDIAN
3252 && GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD
3255 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3257 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3258 since we are saying that the high bits don't matter. */
3259 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3260 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3261 return SUBREG_REG (x);
3263 /* If we are narrowing an integral object, we need to see if we can
3264 simplify the expression for the object knowing that we only need the
3267 if (GET_MODE_CLASS (mode) == MODE_INT
3268 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
3269 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
3270 && subreg_lowpart_p (x))
3271 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_MASK (mode),
3276 /* (not (plus X -1)) can become (neg X). */
3277 if (GET_CODE (XEXP (x, 0)) == PLUS
3278 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3279 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3281 /* Similarly, (not (neg X)) is (plus X -1). */
3282 if (GET_CODE (XEXP (x, 0)) == NEG)
3283 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3286 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3287 if (GET_CODE (XEXP (x, 0)) == XOR
3288 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3289 && (temp = simplify_unary_operation (NOT, mode,
3290 XEXP (XEXP (x, 0), 1),
3293 SUBST (XEXP (XEXP (x, 0), 1), temp);
3297 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3298 other than 1, but that is not valid. We could do a similar
3299 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3300 but this doesn't seem common enough to bother with. */
3301 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3302 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3303 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3304 XEXP (XEXP (x, 0), 1));
3306 if (GET_CODE (XEXP (x, 0)) == SUBREG
3307 && subreg_lowpart_p (XEXP (x, 0))
3308 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3309 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3310 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3311 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3313 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3315 x = gen_rtx (ROTATE, inner_mode,
3316 gen_unary (NOT, inner_mode, const1_rtx),
3317 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3318 return gen_lowpart_for_combine (mode, x);
3321 #if STORE_FLAG_VALUE == -1
3322 /* (not (comparison foo bar)) can be done by reversing the comparison
3324 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3325 && reversible_comparison_p (XEXP (x, 0)))
3326 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3327 mode, XEXP (XEXP (x, 0), 0),
3328 XEXP (XEXP (x, 0), 1));
3330 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3331 is (lt foo (const_int 0)), so we can perform the above
3334 if (XEXP (x, 1) == const1_rtx
3335 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3336 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3337 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3338 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3341 /* Apply De Morgan's laws to reduce number of patterns for machines
3342 with negating logical insns (and-not, nand, etc.). If result has
3343 only one NOT, put it first, since that is how the patterns are
3346 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3348 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3350 if (GET_CODE (in1) == NOT)
3351 in1 = XEXP (in1, 0);
3353 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3355 if (GET_CODE (in2) == NOT)
3356 in2 = XEXP (in2, 0);
3357 else if (GET_CODE (in2) == CONST_INT
3358 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3359 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3361 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3363 if (GET_CODE (in2) == NOT)
3366 in2 = in1; in1 = tem;
3369 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3375 /* (neg (plus X 1)) can become (not X). */
3376 if (GET_CODE (XEXP (x, 0)) == PLUS
3377 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3378 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3380 /* Similarly, (neg (not X)) is (plus X 1). */
3381 if (GET_CODE (XEXP (x, 0)) == NOT)
3382 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3384 /* (neg (minus X Y)) can become (minus Y X). */
3385 if (GET_CODE (XEXP (x, 0)) == MINUS
3386 && (! FLOAT_MODE_P (mode)
3387 /* x-y != -(y-x) with IEEE floating point. */
3388 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3390 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3391 XEXP (XEXP (x, 0), 0));
3393 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3394 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3395 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3396 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3398 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3399 if we can then eliminate the NEG (e.g.,
3400 if the operand is a constant). */
3402 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3404 temp = simplify_unary_operation (NEG, mode,
3405 XEXP (XEXP (x, 0), 0), mode);
3408 SUBST (XEXP (XEXP (x, 0), 0), temp);
3413 temp = expand_compound_operation (XEXP (x, 0));
3415 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3416 replaced by (lshiftrt X C). This will convert
3417 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3419 if (GET_CODE (temp) == ASHIFTRT
3420 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3421 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3422 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3423 INTVAL (XEXP (temp, 1)));
3425 /* If X has only a single bit that might be nonzero, say, bit I, convert
3426 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3427 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3428 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3429 or a SUBREG of one since we'd be making the expression more
3430 complex if it was just a register. */
3432 if (GET_CODE (temp) != REG
3433 && ! (GET_CODE (temp) == SUBREG
3434 && GET_CODE (SUBREG_REG (temp)) == REG)
3435 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3437 rtx temp1 = simplify_shift_const
3438 (NULL_RTX, ASHIFTRT, mode,
3439 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3440 GET_MODE_BITSIZE (mode) - 1 - i),
3441 GET_MODE_BITSIZE (mode) - 1 - i);
3443 /* If all we did was surround TEMP with the two shifts, we
3444 haven't improved anything, so don't use it. Otherwise,
3445 we are better off with TEMP1. */
3446 if (GET_CODE (temp1) != ASHIFTRT
3447 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3448 || XEXP (XEXP (temp1, 0), 0) != temp)
3453 case FLOAT_TRUNCATE:
3454 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3455 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3456 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3457 return XEXP (XEXP (x, 0), 0);
3459 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3460 (OP:SF foo:SF) if OP is NEG or ABS. */
3461 if ((GET_CODE (XEXP (x, 0)) == ABS
3462 || GET_CODE (XEXP (x, 0)) == NEG)
3463 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3464 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3465 return gen_unary (GET_CODE (XEXP (x, 0)),
3466 mode, XEXP (XEXP (XEXP (x, 0), 0), 0));
3471 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3472 using cc0, in which case we want to leave it as a COMPARE
3473 so we can distinguish it from a register-register-copy. */
3474 if (XEXP (x, 1) == const0_rtx)
3477 /* In IEEE floating point, x-0 is not the same as x. */
3478 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3479 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3481 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3487 /* (const (const X)) can become (const X). Do it this way rather than
3488 returning the inner CONST since CONST can be shared with a
3490 if (GET_CODE (XEXP (x, 0)) == CONST)
3491 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3496 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3497 can add in an offset. find_split_point will split this address up
3498 again if it doesn't match. */
3499 if (GET_CODE (XEXP (x, 0)) == HIGH
3500 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3506 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3507 outermost. That's because that's the way indexed addresses are
3508 supposed to appear. This code used to check many more cases, but
3509 they are now checked elsewhere. */
3510 if (GET_CODE (XEXP (x, 0)) == PLUS
3511 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3512 return gen_binary (PLUS, mode,
3513 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3515 XEXP (XEXP (x, 0), 1));
3517 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3518 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3519 bit-field and can be replaced by either a sign_extend or a
3520 sign_extract. The `and' may be a zero_extend. */
3521 if (GET_CODE (XEXP (x, 0)) == XOR
3522 && GET_CODE (XEXP (x, 1)) == CONST_INT
3523 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3524 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3525 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3526 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3527 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3528 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3529 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3530 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3531 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3532 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3534 return simplify_shift_const
3535 (NULL_RTX, ASHIFTRT, mode,
3536 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3537 XEXP (XEXP (XEXP (x, 0), 0), 0),
3538 GET_MODE_BITSIZE (mode) - (i + 1)),
3539 GET_MODE_BITSIZE (mode) - (i + 1));
3541 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3542 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3543 is 1. This produces better code than the alternative immediately
3545 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3546 && reversible_comparison_p (XEXP (x, 0))
3547 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3548 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3550 gen_unary (NEG, mode,
3551 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3552 mode, XEXP (XEXP (x, 0), 0),
3553 XEXP (XEXP (x, 0), 1)));
3555 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3556 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3557 the bitsize of the mode - 1. This allows simplification of
3558 "a = (b & 8) == 0;" */
3559 if (XEXP (x, 1) == constm1_rtx
3560 && GET_CODE (XEXP (x, 0)) != REG
3561 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3562 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3563 && nonzero_bits (XEXP (x, 0), mode) == 1)
3564 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3565 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3566 gen_rtx_combine (XOR, mode,
3567 XEXP (x, 0), const1_rtx),
3568 GET_MODE_BITSIZE (mode) - 1),
3569 GET_MODE_BITSIZE (mode) - 1);
3571 /* If we are adding two things that have no bits in common, convert
3572 the addition into an IOR. This will often be further simplified,
3573 for example in cases like ((a & 1) + (a & 2)), which can
3576 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3577 && (nonzero_bits (XEXP (x, 0), mode)
3578 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3579 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3583 #if STORE_FLAG_VALUE == 1
3584 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3586 if (XEXP (x, 0) == const1_rtx
3587 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3588 && reversible_comparison_p (XEXP (x, 1)))
3589 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3590 mode, XEXP (XEXP (x, 1), 0),
3591 XEXP (XEXP (x, 1), 1));
3594 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3595 (and <foo> (const_int pow2-1)) */
3596 if (GET_CODE (XEXP (x, 1)) == AND
3597 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3598 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3599 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3600 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3601 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3603 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3605 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3606 return gen_binary (MINUS, mode,
3607 gen_binary (MINUS, mode, XEXP (x, 0),
3608 XEXP (XEXP (x, 1), 0)),
3609 XEXP (XEXP (x, 1), 1));
3613 /* If we have (mult (plus A B) C), apply the distributive law and then
3614 the inverse distributive law to see if things simplify. This
3615 occurs mostly in addresses, often when unrolling loops. */
3617 if (GET_CODE (XEXP (x, 0)) == PLUS)
3619 x = apply_distributive_law
3620 (gen_binary (PLUS, mode,
3621 gen_binary (MULT, mode,
3622 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3623 gen_binary (MULT, mode,
3624 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3626 if (GET_CODE (x) != MULT)
3630 /* If this is multiplication by a power of two and its first operand is
3631 a shift, treat the multiply as a shift to allow the shifts to
3632 possibly combine. */
3633 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3634 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3635 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3636 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3637 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3638 || GET_CODE (XEXP (x, 0)) == ROTATE
3639 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3640 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3642 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3643 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3644 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3645 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3646 XEXP (XEXP (x, 0), 1));
3650 /* If this is a divide by a power of two, treat it as a shift if
3651 its first operand is a shift. */
3652 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3653 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3654 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3655 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3656 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3657 || GET_CODE (XEXP (x, 0)) == ROTATE
3658 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3659 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3663 case GT: case GTU: case GE: case GEU:
3664 case LT: case LTU: case LE: case LEU:
3665 /* If the first operand is a condition code, we can't do anything
3667 if (GET_CODE (XEXP (x, 0)) == COMPARE
3668 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3670 && XEXP (x, 0) != cc0_rtx
3674 rtx op0 = XEXP (x, 0);
3675 rtx op1 = XEXP (x, 1);
3676 enum rtx_code new_code;
3678 if (GET_CODE (op0) == COMPARE)
3679 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3681 /* Simplify our comparison, if possible. */
3682 new_code = simplify_comparison (code, &op0, &op1);
3684 #if STORE_FLAG_VALUE == 1
3685 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3686 if only the low-order bit is possibly nonzero in X (such as when
3687 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3688 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3689 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3692 Remove any ZERO_EXTRACT we made when thinking this was a
3693 comparison. It may now be simpler to use, e.g., an AND. If a
3694 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3695 the call to make_compound_operation in the SET case. */
3697 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3698 && op1 == const0_rtx
3699 && nonzero_bits (op0, mode) == 1)
3700 return gen_lowpart_for_combine (mode,
3701 expand_compound_operation (op0));
3703 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3704 && op1 == const0_rtx
3705 && (num_sign_bit_copies (op0, mode)
3706 == GET_MODE_BITSIZE (mode)))
3708 op0 = expand_compound_operation (op0);
3709 return gen_unary (NEG, mode,
3710 gen_lowpart_for_combine (mode, op0));
3713 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3714 && op1 == const0_rtx
3715 && nonzero_bits (op0, mode) == 1)
3717 op0 = expand_compound_operation (op0);
3718 return gen_binary (XOR, mode,
3719 gen_lowpart_for_combine (mode, op0),
3723 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3724 && op1 == const0_rtx
3725 && (num_sign_bit_copies (op0, mode)
3726 == GET_MODE_BITSIZE (mode)))
3728 op0 = expand_compound_operation (op0);
3729 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3733 #if STORE_FLAG_VALUE == -1
3734 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3736 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3737 && op1 == const0_rtx
3738 && (num_sign_bit_copies (op0, mode)
3739 == GET_MODE_BITSIZE (mode)))
3740 return gen_lowpart_for_combine (mode,
3741 expand_compound_operation (op0));
3743 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3744 && op1 == const0_rtx
3745 && nonzero_bits (op0, mode) == 1)
3747 op0 = expand_compound_operation (op0);
3748 return gen_unary (NEG, mode,
3749 gen_lowpart_for_combine (mode, op0));
3752 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3753 && op1 == const0_rtx
3754 && (num_sign_bit_copies (op0, mode)
3755 == GET_MODE_BITSIZE (mode)))
3757 op0 = expand_compound_operation (op0);
3758 return gen_unary (NOT, mode,
3759 gen_lowpart_for_combine (mode, op0));
3762 /* If X is 0/1, (eq X 0) is X-1. */
3763 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3764 && op1 == const0_rtx
3765 && nonzero_bits (op0, mode) == 1)
3767 op0 = expand_compound_operation (op0);
3768 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3772 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3773 one bit that might be nonzero, we can convert (ne x 0) to
3774 (ashift x c) where C puts the bit in the sign bit. Remove any
3775 AND with STORE_FLAG_VALUE when we are done, since we are only
3776 going to test the sign bit. */
3777 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3778 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3779 && (STORE_FLAG_VALUE
3780 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3781 && op1 == const0_rtx
3782 && mode == GET_MODE (op0)
3783 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3785 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3786 expand_compound_operation (op0),
3787 GET_MODE_BITSIZE (mode) - 1 - i);
3788 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3794 /* If the code changed, return a whole new comparison. */
3795 if (new_code != code)
3796 return gen_rtx_combine (new_code, mode, op0, op1);
3798 /* Otherwise, keep this operation, but maybe change its operands.
3799 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3800 SUBST (XEXP (x, 0), op0);
3801 SUBST (XEXP (x, 1), op1);
3806 return simplify_if_then_else (x);
3812 /* If we are processing SET_DEST, we are done. */
3816 return expand_compound_operation (x);
3819 return simplify_set (x);
3824 return simplify_logical (x, last);
3827 /* (abs (neg <foo>)) -> (abs <foo>) */
3828 if (GET_CODE (XEXP (x, 0)) == NEG)
3829 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3831 /* If operand is something known to be positive, ignore the ABS. */
3832 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3833 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
3834 <= HOST_BITS_PER_WIDE_INT)
3835 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3836 & ((HOST_WIDE_INT) 1
3837 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3842 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3843 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
3844 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
3849 /* (ffs (*_extend <X>)) = (ffs <X>) */
3850 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3851 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3852 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3856 /* (float (sign_extend <X>)) = (float <X>). */
3857 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3858 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3866 /* If this is a shift by a constant amount, simplify it. */
3867 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3868 return simplify_shift_const (x, code, mode, XEXP (x, 0),
3869 INTVAL (XEXP (x, 1)));
3871 #ifdef SHIFT_COUNT_TRUNCATED
3872 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
3874 force_to_mode (XEXP (x, 1), GET_MODE (x),
3876 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
3887 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
3890 simplify_if_then_else (x)
3893 enum machine_mode mode = GET_MODE (x);
3894 rtx cond = XEXP (x, 0);
3895 rtx true = XEXP (x, 1);
3896 rtx false = XEXP (x, 2);
3897 enum rtx_code true_code = GET_CODE (cond);
3898 int comparison_p = GET_RTX_CLASS (true_code) == '<';
3902 /* Simplify storing of the truth value. */
3903 if (comparison_p && true == const_true_rtx && false == const0_rtx)
3904 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
3906 /* Also when the truth value has to be reversed. */
3907 if (comparison_p && reversible_comparison_p (cond)
3908 && true == const0_rtx && false == const_true_rtx)
3909 return gen_binary (reverse_condition (true_code),
3910 mode, XEXP (cond, 0), XEXP (cond, 1));
3912 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
3913 in it is being compared against certain values. Get the true and false
3914 comparisons and see if that says anything about the value of each arm. */
3916 if (comparison_p && reversible_comparison_p (cond)
3917 && GET_CODE (XEXP (cond, 0)) == REG)
3920 rtx from = XEXP (cond, 0);
3921 enum rtx_code false_code = reverse_condition (true_code);
3922 rtx true_val = XEXP (cond, 1);
3923 rtx false_val = true_val;
3926 /* If FALSE_CODE is EQ, swap the codes and arms. */
3928 if (false_code == EQ)
3930 swapped = 1, true_code = EQ, false_code = NE;
3931 temp = true, true = false, false = temp;
3934 /* If we are comparing against zero and the expression being tested has
3935 only a single bit that might be nonzero, that is its value when it is
3936 not equal to zero. Similarly if it is known to be -1 or 0. */
3938 if (true_code == EQ && true_val == const0_rtx
3939 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3940 false_code = EQ, false_val = GEN_INT (nzb);
3941 else if (true_code == EQ && true_val == const0_rtx
3942 && (num_sign_bit_copies (from, GET_MODE (from))
3943 == GET_MODE_BITSIZE (GET_MODE (from))))
3944 false_code = EQ, false_val = constm1_rtx;
3946 /* Now simplify an arm if we know the value of the register in the
3947 branch and it is used in the arm. Be careful due to the potential
3948 of locally-shared RTL. */
3950 if (reg_mentioned_p (from, true))
3951 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
3952 pc_rtx, pc_rtx, 0, 0);
3953 if (reg_mentioned_p (from, false))
3954 false = subst (known_cond (copy_rtx (false), false_code,
3956 pc_rtx, pc_rtx, 0, 0);
3958 SUBST (XEXP (x, 1), swapped ? false : true);
3959 SUBST (XEXP (x, 2), swapped ? true : false);
3961 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
3964 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3965 reversed, do so to avoid needing two sets of patterns for
3966 subtract-and-branch insns. Similarly if we have a constant in the true
3967 arm, the false arm is the same as the first operand of the comparison, or
3968 the false arm is more complicated than the true arm. */
3970 if (comparison_p && reversible_comparison_p (cond)
3972 || (CONSTANT_P (true)
3973 && GET_CODE (false) != CONST_INT && false != pc_rtx)
3974 || true == const0_rtx
3975 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
3976 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
3977 || (GET_CODE (true) == SUBREG
3978 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
3979 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
3980 || reg_mentioned_p (true, false)
3981 || rtx_equal_p (false, XEXP (cond, 0))))
3983 true_code = reverse_condition (true_code);
3985 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
3988 SUBST (XEXP (x, 1), false);
3989 SUBST (XEXP (x, 2), true);
3991 temp = true, true = false, false = temp, cond = XEXP (x, 0);
3994 /* If the two arms are identical, we don't need the comparison. */
3996 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
3999 /* Look for cases where we have (abs x) or (neg (abs X)). */
4001 if (GET_MODE_CLASS (mode) == MODE_INT
4002 && GET_CODE (false) == NEG
4003 && rtx_equal_p (true, XEXP (false, 0))
4005 && rtx_equal_p (true, XEXP (cond, 0))
4006 && ! side_effects_p (true))
4011 return gen_unary (ABS, mode, true);
4014 return gen_unary (NEG, mode, gen_unary (ABS, mode, true));
4017 /* Look for MIN or MAX. */
4019 if ((! FLOAT_MODE_P (mode) | flag_fast_math)
4021 && rtx_equal_p (XEXP (cond, 0), true)
4022 && rtx_equal_p (XEXP (cond, 1), false)
4023 && ! side_effects_p (cond))
4028 return gen_binary (SMAX, mode, true, false);
4031 return gen_binary (SMIN, mode, true, false);
4034 return gen_binary (UMAX, mode, true, false);
4037 return gen_binary (UMIN, mode, true, false);
4040 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4042 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4043 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4044 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4045 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4046 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4047 neither of the above, but it isn't worth checking for.
4049 Similarly, (if_then_else COND Z 0) can be replaced by
4050 (mult COND (mult Z STORE_FLAG_VALUE)). */
4052 if (comparison_p && mode != VOIDmode && ! side_effects_p (x))
4054 rtx t = make_compound_operation (true, SET);
4055 rtx f = make_compound_operation (false, SET);
4056 rtx cond_op0 = XEXP (cond, 0);
4057 rtx cond_op1 = XEXP (cond, 1);
4058 enum rtx_code op, extend_op = NIL;
4059 enum machine_mode m = mode;
4062 if (f == const0_rtx)
4063 return gen_binary (MULT, mode, gen_binary (true_code, mode, cond_op0,
4065 gen_binary (MULT, mode, t, const_true_rtx));
4067 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4068 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4069 || GET_CODE (t) == ASHIFT
4070 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4071 && rtx_equal_p (XEXP (t, 0), f))
4072 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4074 /* If an identity-zero op is commutative, check whether there
4075 would be a match if we swapped the operands. */
4076 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4077 || GET_CODE (t) == XOR)
4078 && rtx_equal_p (XEXP (t, 1), f))
4079 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4080 else if (GET_CODE (t) == SIGN_EXTEND
4081 && (GET_CODE (XEXP (t, 0)) == PLUS
4082 || GET_CODE (XEXP (t, 0)) == MINUS
4083 || GET_CODE (XEXP (t, 0)) == IOR
4084 || GET_CODE (XEXP (t, 0)) == XOR
4085 || GET_CODE (XEXP (t, 0)) == ASHIFT
4086 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4087 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4088 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4089 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4090 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4091 && (num_sign_bit_copies (f, GET_MODE (f))
4092 > (GET_MODE_BITSIZE (mode)
4093 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4095 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4096 extend_op = SIGN_EXTEND;
4097 m = GET_MODE (XEXP (t, 0));
4099 else if (GET_CODE (t) == SIGN_EXTEND
4100 && (GET_CODE (XEXP (t, 0)) == PLUS
4101 || GET_CODE (XEXP (t, 0)) == IOR
4102 || GET_CODE (XEXP (t, 0)) == XOR)
4103 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4104 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4105 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4106 && (num_sign_bit_copies (f, GET_MODE (f))
4107 > (GET_MODE_BITSIZE (mode)
4108 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4110 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4111 extend_op = SIGN_EXTEND;
4112 m = GET_MODE (XEXP (t, 0));
4114 else if (GET_CODE (t) == ZERO_EXTEND
4115 && (GET_CODE (XEXP (t, 0)) == PLUS
4116 || GET_CODE (XEXP (t, 0)) == MINUS
4117 || GET_CODE (XEXP (t, 0)) == IOR
4118 || GET_CODE (XEXP (t, 0)) == XOR
4119 || GET_CODE (XEXP (t, 0)) == ASHIFT
4120 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4121 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4122 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4123 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4124 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4125 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4126 && ((nonzero_bits (f, GET_MODE (f))
4127 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4130 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4131 extend_op = ZERO_EXTEND;
4132 m = GET_MODE (XEXP (t, 0));
4134 else if (GET_CODE (t) == ZERO_EXTEND
4135 && (GET_CODE (XEXP (t, 0)) == PLUS
4136 || GET_CODE (XEXP (t, 0)) == IOR
4137 || GET_CODE (XEXP (t, 0)) == XOR)
4138 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4139 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4140 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4141 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4142 && ((nonzero_bits (f, GET_MODE (f))
4143 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4146 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4147 extend_op = ZERO_EXTEND;
4148 m = GET_MODE (XEXP (t, 0));
4153 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4154 pc_rtx, pc_rtx, 0, 0);
4155 temp = gen_binary (MULT, m, temp,
4156 gen_binary (MULT, m, c1, const_true_rtx));
4157 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4158 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4160 if (extend_op != NIL)
4161 temp = gen_unary (extend_op, mode, temp);
4168 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4169 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4170 negation of a single bit, we can convert this operation to a shift. We
4171 can actually do this more generally, but it doesn't seem worth it. */
4173 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4174 && false == const0_rtx && GET_CODE (true) == CONST_INT
4175 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4176 && (i = exact_log2 (INTVAL (true))) >= 0)
4177 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4178 == GET_MODE_BITSIZE (mode))
4179 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4181 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4182 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4187 /* Simplify X, a SET expression. Return the new expression. */
4193 rtx src = SET_SRC (x);
4194 rtx dest = SET_DEST (x);
4195 enum machine_mode mode
4196 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4200 /* (set (pc) (return)) gets written as (return). */
4201 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4204 /* Convert this into a field assignment operation, if possible. */
4205 x = make_field_assignment (x);
4207 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4208 the comparison result and try to simplify it unless we already have used
4209 undobuf.other_insn. */
4210 if ((GET_CODE (src) == COMPARE
4215 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4216 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4217 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4218 && XEXP (*cc_use, 0) == dest)
4220 enum rtx_code old_code = GET_CODE (*cc_use);
4221 enum rtx_code new_code;
4223 int other_changed = 0;
4224 enum machine_mode compare_mode = GET_MODE (dest);
4226 if (GET_CODE (src) == COMPARE)
4227 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4229 op0 = src, op1 = const0_rtx;
4231 /* Simplify our comparison, if possible. */
4232 new_code = simplify_comparison (old_code, &op0, &op1);
4234 #ifdef EXTRA_CC_MODES
4235 /* If this machine has CC modes other than CCmode, check to see if we
4236 need to use a different CC mode here. */
4237 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4238 #endif /* EXTRA_CC_MODES */
4240 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4241 /* If the mode changed, we have to change SET_DEST, the mode in the
4242 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4243 a hard register, just build new versions with the proper mode. If it
4244 is a pseudo, we lose unless it is only time we set the pseudo, in
4245 which case we can safely change its mode. */
4246 if (compare_mode != GET_MODE (dest))
4248 int regno = REGNO (dest);
4249 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4251 if (regno < FIRST_PSEUDO_REGISTER
4252 || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest)))
4254 if (regno >= FIRST_PSEUDO_REGISTER)
4255 SUBST (regno_reg_rtx[regno], new_dest);
4257 SUBST (SET_DEST (x), new_dest);
4258 SUBST (XEXP (*cc_use, 0), new_dest);
4266 /* If the code changed, we have to build a new comparison in
4267 undobuf.other_insn. */
4268 if (new_code != old_code)
4270 unsigned HOST_WIDE_INT mask;
4272 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4275 /* If the only change we made was to change an EQ into an NE or
4276 vice versa, OP0 has only one bit that might be nonzero, and OP1
4277 is zero, check if changing the user of the condition code will
4278 produce a valid insn. If it won't, we can keep the original code
4279 in that insn by surrounding our operation with an XOR. */
4281 if (((old_code == NE && new_code == EQ)
4282 || (old_code == EQ && new_code == NE))
4283 && ! other_changed && op1 == const0_rtx
4284 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4285 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4287 rtx pat = PATTERN (other_insn), note = 0;
4289 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4290 && ! check_asm_operands (pat)))
4292 PUT_CODE (*cc_use, old_code);
4295 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4303 undobuf.other_insn = other_insn;
4306 /* If we are now comparing against zero, change our source if
4307 needed. If we do not use cc0, we always have a COMPARE. */
4308 if (op1 == const0_rtx && dest == cc0_rtx)
4310 SUBST (SET_SRC (x), op0);
4316 /* Otherwise, if we didn't previously have a COMPARE in the
4317 correct mode, we need one. */
4318 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4321 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4326 /* Otherwise, update the COMPARE if needed. */
4327 SUBST (XEXP (src, 0), op0);
4328 SUBST (XEXP (src, 1), op1);
4333 /* Get SET_SRC in a form where we have placed back any
4334 compound expressions. Then do the checks below. */
4335 src = make_compound_operation (src, SET);
4336 SUBST (SET_SRC (x), src);
4339 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4340 and X being a REG or (subreg (reg)), we may be able to convert this to
4341 (set (subreg:m2 x) (op)).
4343 We can always do this if M1 is narrower than M2 because that means that
4344 we only care about the low bits of the result.
4346 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4347 perform a narrower operation that requested since the high-order bits will
4348 be undefined. On machine where it is defined, this transformation is safe
4349 as long as M1 and M2 have the same number of words. */
4351 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4352 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4353 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4355 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4356 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4357 #ifndef WORD_REGISTER_OPERATIONS
4358 && (GET_MODE_SIZE (GET_MODE (src))
4359 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4361 && (GET_CODE (dest) == REG
4362 || (GET_CODE (dest) == SUBREG
4363 && GET_CODE (SUBREG_REG (dest)) == REG)))
4365 SUBST (SET_DEST (x),
4366 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4368 SUBST (SET_SRC (x), SUBREG_REG (src));
4370 src = SET_SRC (x), dest = SET_DEST (x);
4373 #ifdef LOAD_EXTEND_OP
4374 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4375 would require a paradoxical subreg. Replace the subreg with a
4376 zero_extend to avoid the reload that would otherwise be required. */
4378 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4379 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4380 && SUBREG_WORD (src) == 0
4381 && (GET_MODE_SIZE (GET_MODE (src))
4382 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4383 && GET_CODE (SUBREG_REG (src)) == MEM)
4386 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4387 GET_MODE (src), XEXP (src, 0)));
4393 #ifndef HAVE_conditional_move
4395 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4396 are comparing an item known to be 0 or -1 against 0, use a logical
4397 operation instead. Check for one of the arms being an IOR of the other
4398 arm with some value. We compute three terms to be IOR'ed together. In
4399 practice, at most two will be nonzero. Then we do the IOR's. */
4401 if (GET_CODE (dest) != PC
4402 && GET_CODE (src) == IF_THEN_ELSE
4403 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4404 && XEXP (XEXP (src, 0), 1) == const0_rtx
4405 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4406 GET_MODE (XEXP (XEXP (src, 0), 0)))
4407 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4408 && ! side_effects_p (src))
4410 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4411 ? XEXP (src, 1) : XEXP (src, 2));
4412 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4413 ? XEXP (src, 2) : XEXP (src, 1));
4414 rtx term1 = const0_rtx, term2, term3;
4416 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4417 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4418 else if (GET_CODE (true) == IOR
4419 && rtx_equal_p (XEXP (true, 1), false))
4420 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4421 else if (GET_CODE (false) == IOR
4422 && rtx_equal_p (XEXP (false, 0), true))
4423 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4424 else if (GET_CODE (false) == IOR
4425 && rtx_equal_p (XEXP (false, 1), true))
4426 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4428 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4429 term3 = gen_binary (AND, GET_MODE (src),
4430 gen_unary (NOT, GET_MODE (src),
4431 XEXP (XEXP (src, 0), 0)),
4435 gen_binary (IOR, GET_MODE (src),
4436 gen_binary (IOR, GET_MODE (src), term1, term2),
4446 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4447 result. LAST is nonzero if this is the last retry. */
4450 simplify_logical (x, last)
4454 enum machine_mode mode = GET_MODE (x);
4455 rtx op0 = XEXP (x, 0);
4456 rtx op1 = XEXP (x, 1);
4458 switch (GET_CODE (x))
4461 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4462 insn (and may simplify more). */
4463 if (GET_CODE (op0) == XOR
4464 && rtx_equal_p (XEXP (op0, 0), op1)
4465 && ! side_effects_p (op1))
4466 x = gen_binary (AND, mode, gen_unary (NOT, mode, XEXP (op0, 1)), op1);
4468 if (GET_CODE (op0) == XOR
4469 && rtx_equal_p (XEXP (op0, 1), op1)
4470 && ! side_effects_p (op1))
4471 x = gen_binary (AND, mode, gen_unary (NOT, mode, XEXP (op0, 0)), op1);
4473 /* Similarly for (~ (A ^ B)) & A. */
4474 if (GET_CODE (op0) == NOT
4475 && GET_CODE (XEXP (op0, 0)) == XOR
4476 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4477 && ! side_effects_p (op1))
4478 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4480 if (GET_CODE (op0) == NOT
4481 && GET_CODE (XEXP (op0, 0)) == XOR
4482 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4483 && ! side_effects_p (op1))
4484 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4486 if (GET_CODE (op1) == CONST_INT)
4488 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4490 /* If we have (ior (and (X C1) C2)) and the next restart would be
4491 the last, simplify this by making C1 as small as possible
4494 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4495 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4496 && GET_CODE (op1) == CONST_INT)
4497 return gen_binary (IOR, mode,
4498 gen_binary (AND, mode, XEXP (op0, 0),
4499 GEN_INT (INTVAL (XEXP (op0, 1))
4500 & ~ INTVAL (op1))), op1);
4502 if (GET_CODE (x) != AND)
4506 /* Convert (A | B) & A to A. */
4507 if (GET_CODE (op0) == IOR
4508 && (rtx_equal_p (XEXP (op0, 0), op1)
4509 || rtx_equal_p (XEXP (op0, 1), op1))
4510 && ! side_effects_p (XEXP (op0, 0))
4511 && ! side_effects_p (XEXP (op0, 1)))
4514 /* In the following group of tests (and those in case IOR below),
4515 we start with some combination of logical operations and apply
4516 the distributive law followed by the inverse distributive law.
4517 Most of the time, this results in no change. However, if some of
4518 the operands are the same or inverses of each other, simplifications
4521 For example, (and (ior A B) (not B)) can occur as the result of
4522 expanding a bit field assignment. When we apply the distributive
4523 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4524 which then simplifies to (and (A (not B))).
4526 If we have (and (ior A B) C), apply the distributive law and then
4527 the inverse distributive law to see if things simplify. */
4529 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4531 x = apply_distributive_law
4532 (gen_binary (GET_CODE (op0), mode,
4533 gen_binary (AND, mode, XEXP (op0, 0), op1),
4534 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4535 if (GET_CODE (x) != AND)
4539 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4540 return apply_distributive_law
4541 (gen_binary (GET_CODE (op1), mode,
4542 gen_binary (AND, mode, XEXP (op1, 0), op0),
4543 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4545 /* Similarly, taking advantage of the fact that
4546 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4548 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4549 return apply_distributive_law
4550 (gen_binary (XOR, mode,
4551 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4552 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4554 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4555 return apply_distributive_law
4556 (gen_binary (XOR, mode,
4557 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4558 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4562 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4563 if (GET_CODE (op1) == CONST_INT
4564 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4565 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4568 /* Convert (A & B) | A to A. */
4569 if (GET_CODE (op0) == AND
4570 && (rtx_equal_p (XEXP (op0, 0), op1)
4571 || rtx_equal_p (XEXP (op0, 1), op1))
4572 && ! side_effects_p (XEXP (op0, 0))
4573 && ! side_effects_p (XEXP (op0, 1)))
4576 /* If we have (ior (and A B) C), apply the distributive law and then
4577 the inverse distributive law to see if things simplify. */
4579 if (GET_CODE (op0) == AND)
4581 x = apply_distributive_law
4582 (gen_binary (AND, mode,
4583 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4584 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4586 if (GET_CODE (x) != IOR)
4590 if (GET_CODE (op1) == AND)
4592 x = apply_distributive_law
4593 (gen_binary (AND, mode,
4594 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4595 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4597 if (GET_CODE (x) != IOR)
4601 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4602 mode size to (rotate A CX). */
4604 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4605 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4606 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4607 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4608 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4609 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4610 == GET_MODE_BITSIZE (mode)))
4611 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4612 (GET_CODE (op0) == ASHIFT
4613 ? XEXP (op0, 1) : XEXP (op1, 1)));
4618 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4619 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4622 int num_negated = 0;
4624 if (GET_CODE (op0) == NOT)
4625 num_negated++, op0 = XEXP (op0, 0);
4626 if (GET_CODE (op1) == NOT)
4627 num_negated++, op1 = XEXP (op1, 0);
4629 if (num_negated == 2)
4631 SUBST (XEXP (x, 0), op0);
4632 SUBST (XEXP (x, 1), op1);
4634 else if (num_negated == 1)
4635 return gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1));
4638 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4639 correspond to a machine insn or result in further simplifications
4640 if B is a constant. */
4642 if (GET_CODE (op0) == AND
4643 && rtx_equal_p (XEXP (op0, 1), op1)
4644 && ! side_effects_p (op1))
4645 return gen_binary (AND, mode, gen_unary (NOT, mode, XEXP (op0, 0)),
4648 else if (GET_CODE (op0) == AND
4649 && rtx_equal_p (XEXP (op0, 0), op1)
4650 && ! side_effects_p (op1))
4651 return gen_binary (AND, mode, gen_unary (NOT, mode, XEXP (op0, 1)),
4654 #if STORE_FLAG_VALUE == 1
4655 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4657 if (op1 == const1_rtx
4658 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4659 && reversible_comparison_p (op0))
4660 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4661 mode, XEXP (op0, 0), XEXP (op0, 1));
4663 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4664 is (lt foo (const_int 0)), so we can perform the above
4667 if (op1 == const1_rtx
4668 && GET_CODE (op0) == LSHIFTRT
4669 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4670 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4671 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4674 /* (xor (comparison foo bar) (const_int sign-bit))
4675 when STORE_FLAG_VALUE is the sign bit. */
4676 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4677 && (STORE_FLAG_VALUE
4678 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4679 && op1 == const_true_rtx
4680 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4681 && reversible_comparison_p (op0))
4682 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4683 mode, XEXP (op0, 0), XEXP (op0, 1));
4690 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4691 operations" because they can be replaced with two more basic operations.
4692 ZERO_EXTEND is also considered "compound" because it can be replaced with
4693 an AND operation, which is simpler, though only one operation.
4695 The function expand_compound_operation is called with an rtx expression
4696 and will convert it to the appropriate shifts and AND operations,
4697 simplifying at each stage.
4699 The function make_compound_operation is called to convert an expression
4700 consisting of shifts and ANDs into the equivalent compound expression.
4701 It is the inverse of this function, loosely speaking. */
4704 expand_compound_operation (x)
4712 switch (GET_CODE (x))
4717 /* We can't necessarily use a const_int for a multiword mode;
4718 it depends on implicitly extending the value.
4719 Since we don't know the right way to extend it,
4720 we can't tell whether the implicit way is right.
4722 Even for a mode that is no wider than a const_int,
4723 we can't win, because we need to sign extend one of its bits through
4724 the rest of it, and we don't know which bit. */
4725 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4728 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4729 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4730 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4731 reloaded. If not for that, MEM's would very rarely be safe.
4733 Reject MODEs bigger than a word, because we might not be able
4734 to reference a two-register group starting with an arbitrary register
4735 (and currently gen_lowpart might crash for a SUBREG). */
4737 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
4740 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4741 /* If the inner object has VOIDmode (the only way this can happen
4742 is if it is a ASM_OPERANDS), we can't do anything since we don't
4743 know how much masking to do. */
4752 /* If the operand is a CLOBBER, just return it. */
4753 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4756 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4757 || GET_CODE (XEXP (x, 2)) != CONST_INT
4758 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4761 len = INTVAL (XEXP (x, 1));
4762 pos = INTVAL (XEXP (x, 2));
4764 /* If this goes outside the object being extracted, replace the object
4765 with a (use (mem ...)) construct that only combine understands
4766 and is used only for this purpose. */
4767 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4768 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4771 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4779 /* If we reach here, we want to return a pair of shifts. The inner
4780 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4781 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4782 logical depending on the value of UNSIGNEDP.
4784 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4785 converted into an AND of a shift.
4787 We must check for the case where the left shift would have a negative
4788 count. This can happen in a case like (x >> 31) & 255 on machines
4789 that can't shift by a constant. On those machines, we would first
4790 combine the shift with the AND to produce a variable-position
4791 extraction. Then the constant of 31 would be substituted in to produce
4792 a such a position. */
4794 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4795 if (modewidth >= pos - len)
4796 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4798 simplify_shift_const (NULL_RTX, ASHIFT,
4801 modewidth - pos - len),
4804 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4805 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4806 simplify_shift_const (NULL_RTX, LSHIFTRT,
4809 ((HOST_WIDE_INT) 1 << len) - 1);
4811 /* Any other cases we can't handle. */
4815 /* If we couldn't do this for some reason, return the original
4817 if (GET_CODE (tem) == CLOBBER)
4823 /* X is a SET which contains an assignment of one object into
4824 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4825 or certain SUBREGS). If possible, convert it into a series of
4828 We half-heartedly support variable positions, but do not at all
4829 support variable lengths. */
4832 expand_field_assignment (x)
4836 rtx pos; /* Always counts from low bit. */
4839 enum machine_mode compute_mode;
4841 /* Loop until we find something we can't simplify. */
4844 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4845 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4847 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4848 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4851 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4852 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4854 inner = XEXP (SET_DEST (x), 0);
4855 len = INTVAL (XEXP (SET_DEST (x), 1));
4856 pos = XEXP (SET_DEST (x), 2);
4858 /* If the position is constant and spans the width of INNER,
4859 surround INNER with a USE to indicate this. */
4860 if (GET_CODE (pos) == CONST_INT
4861 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4862 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4865 if (GET_CODE (pos) == CONST_INT)
4866 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4868 else if (GET_CODE (pos) == MINUS
4869 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4870 && (INTVAL (XEXP (pos, 1))
4871 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4872 /* If position is ADJUST - X, new position is X. */
4873 pos = XEXP (pos, 0);
4875 pos = gen_binary (MINUS, GET_MODE (pos),
4876 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4882 /* A SUBREG between two modes that occupy the same numbers of words
4883 can be done by moving the SUBREG to the source. */
4884 else if (GET_CODE (SET_DEST (x)) == SUBREG
4885 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4886 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4887 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4888 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4890 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4891 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4898 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4899 inner = SUBREG_REG (inner);
4901 compute_mode = GET_MODE (inner);
4903 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4904 if (len < HOST_BITS_PER_WIDE_INT)
4905 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4909 /* Now compute the equivalent expression. Make a copy of INNER
4910 for the SET_DEST in case it is a MEM into which we will substitute;
4911 we don't want shared RTL in that case. */
4912 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4913 gen_binary (IOR, compute_mode,
4914 gen_binary (AND, compute_mode,
4915 gen_unary (NOT, compute_mode,
4920 gen_binary (ASHIFT, compute_mode,
4921 gen_binary (AND, compute_mode,
4922 gen_lowpart_for_combine
4932 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
4933 it is an RTX that represents a variable starting position; otherwise,
4934 POS is the (constant) starting bit position (counted from the LSB).
4936 INNER may be a USE. This will occur when we started with a bitfield
4937 that went outside the boundary of the object in memory, which is
4938 allowed on most machines. To isolate this case, we produce a USE
4939 whose mode is wide enough and surround the MEM with it. The only
4940 code that understands the USE is this routine. If it is not removed,
4941 it will cause the resulting insn not to match.
4943 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4946 IN_DEST is non-zero if this is a reference in the destination of a
4947 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4948 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4951 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4952 ZERO_EXTRACT should be built even for bits starting at bit 0.
4954 MODE is the desired mode of the result (if IN_DEST == 0). */
4957 make_extraction (mode, inner, pos, pos_rtx, len,
4958 unsignedp, in_dest, in_compare)
4959 enum machine_mode mode;
4965 int in_dest, in_compare;
4967 /* This mode describes the size of the storage area
4968 to fetch the overall value from. Within that, we
4969 ignore the POS lowest bits, etc. */
4970 enum machine_mode is_mode = GET_MODE (inner);
4971 enum machine_mode inner_mode;
4972 enum machine_mode wanted_mem_mode = byte_mode;
4973 enum machine_mode pos_mode = word_mode;
4974 enum machine_mode extraction_mode = word_mode;
4975 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4978 rtx orig_pos_rtx = pos_rtx;
4981 /* Get some information about INNER and get the innermost object. */
4982 if (GET_CODE (inner) == USE)
4983 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4984 /* We don't need to adjust the position because we set up the USE
4985 to pretend that it was a full-word object. */
4986 spans_byte = 1, inner = XEXP (inner, 0);
4987 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4989 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
4990 consider just the QI as the memory to extract from.
4991 The subreg adds or removes high bits; its mode is
4992 irrelevant to the meaning of this extraction,
4993 since POS and LEN count from the lsb. */
4994 if (GET_CODE (SUBREG_REG (inner)) == MEM)
4995 is_mode = GET_MODE (SUBREG_REG (inner));
4996 inner = SUBREG_REG (inner);
4999 inner_mode = GET_MODE (inner);
5001 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5002 pos = INTVAL (pos_rtx), pos_rtx = 0;
5004 /* See if this can be done without an extraction. We never can if the
5005 width of the field is not the same as that of some integer mode. For
5006 registers, we can only avoid the extraction if the position is at the
5007 low-order bit and this is either not in the destination or we have the
5008 appropriate STRICT_LOW_PART operation available.
5010 For MEM, we can avoid an extract if the field starts on an appropriate
5011 boundary and we can change the mode of the memory reference. However,
5012 we cannot directly access the MEM if we have a USE and the underlying
5013 MEM is not TMODE. This combination means that MEM was being used in a
5014 context where bits outside its mode were being referenced; that is only
5015 valid in bit-field insns. */
5017 if (tmode != BLKmode
5018 && ! (spans_byte && inner_mode != tmode)
5019 && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM
5021 || (GET_CODE (inner) == REG
5022 && (movstrict_optab->handlers[(int) tmode].insn_code
5023 != CODE_FOR_nothing))))
5024 || (GET_CODE (inner) == MEM && pos_rtx == 0
5026 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5027 : BITS_PER_UNIT)) == 0
5028 /* We can't do this if we are widening INNER_MODE (it
5029 may not be aligned, for one thing). */
5030 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5031 && (inner_mode == tmode
5032 || (! mode_dependent_address_p (XEXP (inner, 0))
5033 && ! MEM_VOLATILE_P (inner))))))
5035 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5036 field. If the original and current mode are the same, we need not
5037 adjust the offset. Otherwise, we do if bytes big endian.
5039 If INNER is not a MEM, get a piece consisting of the just the field
5040 of interest (in this case POS must be 0). */
5042 if (GET_CODE (inner) == MEM)
5045 /* POS counts from lsb, but make OFFSET count in memory order. */
5046 if (BYTES_BIG_ENDIAN)
5047 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5049 offset = pos / BITS_PER_UNIT;
5051 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5052 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5053 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5054 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5056 else if (GET_CODE (inner) == REG)
5057 /* We can't call gen_lowpart_for_combine here since we always want
5058 a SUBREG and it would sometimes return a new hard register. */
5059 new = gen_rtx (SUBREG, tmode, inner,
5061 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5062 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
5066 new = force_to_mode (inner, tmode,
5067 len >= HOST_BITS_PER_WIDE_INT
5068 ? GET_MODE_MASK (tmode)
5069 : ((HOST_WIDE_INT) 1 << len) - 1,
5072 /* If this extraction is going into the destination of a SET,
5073 make a STRICT_LOW_PART unless we made a MEM. */
5076 return (GET_CODE (new) == MEM ? new
5077 : (GET_CODE (new) != SUBREG
5078 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5079 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5081 /* Otherwise, sign- or zero-extend unless we already are in the
5084 return (mode == tmode ? new
5085 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5089 /* Unless this is a COMPARE or we have a funny memory reference,
5090 don't do anything with zero-extending field extracts starting at
5091 the low-order bit since they are simple AND operations. */
5092 if (pos_rtx == 0 && pos == 0 && ! in_dest
5093 && ! in_compare && ! spans_byte && unsignedp)
5096 /* Unless we are allowed to span bytes, reject this if we would be
5097 spanning bytes or if the position is not a constant and the length
5098 is not 1. In all other cases, we would only be going outside
5099 out object in cases when an original shift would have been
5102 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5103 || (pos_rtx != 0 && len != 1)))
5106 /* Get the mode to use should INNER be a MEM, the mode for the position,
5107 and the mode for the result. */
5111 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5112 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5113 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5118 if (! in_dest && unsignedp)
5120 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5121 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5122 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5127 if (! in_dest && ! unsignedp)
5129 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5130 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5131 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5135 /* Never narrow an object, since that might not be safe. */
5137 if (mode != VOIDmode
5138 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5139 extraction_mode = mode;
5141 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5142 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5143 pos_mode = GET_MODE (pos_rtx);
5145 /* If this is not from memory or we have to change the mode of memory and
5146 cannot, the desired mode is EXTRACTION_MODE. */
5147 if (GET_CODE (inner) != MEM
5148 || (inner_mode != wanted_mem_mode
5149 && (mode_dependent_address_p (XEXP (inner, 0))
5150 || MEM_VOLATILE_P (inner))))
5151 wanted_mem_mode = extraction_mode;
5156 /* If position is constant, compute new position. Otherwise, build
5159 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
5163 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5164 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
5165 GET_MODE_BITSIZE (wanted_mem_mode))
5170 /* If INNER has a wider mode, make it smaller. If this is a constant
5171 extract, try to adjust the byte to point to the byte containing
5173 if (wanted_mem_mode != VOIDmode
5174 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
5175 && ((GET_CODE (inner) == MEM
5176 && (inner_mode == wanted_mem_mode
5177 || (! mode_dependent_address_p (XEXP (inner, 0))
5178 && ! MEM_VOLATILE_P (inner))))))
5182 /* The computations below will be correct if the machine is big
5183 endian in both bits and bytes or little endian in bits and bytes.
5184 If it is mixed, we must adjust. */
5186 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5187 adjust OFFSET to compensate. */
5188 #if BYTES_BIG_ENDIAN
5190 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5191 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5194 /* If this is a constant position, we can move to the desired byte. */
5197 offset += pos / BITS_PER_UNIT;
5198 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
5201 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5202 if (! spans_byte && is_mode != wanted_mem_mode)
5203 offset = (GET_MODE_SIZE (is_mode)
5204 - GET_MODE_SIZE (wanted_mem_mode) - offset);
5207 if (offset != 0 || inner_mode != wanted_mem_mode)
5209 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
5210 plus_constant (XEXP (inner, 0), offset));
5211 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5212 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5213 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5218 /* If INNER is not memory, we can always get it into the proper mode. */
5219 else if (GET_CODE (inner) != MEM)
5220 inner = force_to_mode (inner, extraction_mode,
5221 pos_rtx || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5222 ? GET_MODE_MASK (extraction_mode)
5223 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5226 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5227 have to zero extend. Otherwise, we can just use a SUBREG. */
5229 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5230 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5231 else if (pos_rtx != 0
5232 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5233 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5235 /* Make POS_RTX unless we already have it and it is correct. If we don't
5236 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5238 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5239 pos_rtx = orig_pos_rtx;
5241 else if (pos_rtx == 0)
5242 pos_rtx = GEN_INT (pos);
5244 /* Make the required operation. See if we can use existing rtx. */
5245 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5246 extraction_mode, inner, GEN_INT (len), pos_rtx);
5248 new = gen_lowpart_for_combine (mode, new);
5253 /* Look at the expression rooted at X. Look for expressions
5254 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5255 Form these expressions.
5257 Return the new rtx, usually just X.
5259 Also, for machines like the Vax that don't have logical shift insns,
5260 try to convert logical to arithmetic shift operations in cases where
5261 they are equivalent. This undoes the canonicalizations to logical
5262 shifts done elsewhere.
5264 We try, as much as possible, to re-use rtl expressions to save memory.
5266 IN_CODE says what kind of expression we are processing. Normally, it is
5267 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5268 being kludges), it is MEM. When processing the arguments of a comparison
5269 or a COMPARE against zero, it is COMPARE. */
5272 make_compound_operation (x, in_code)
5274 enum rtx_code in_code;
5276 enum rtx_code code = GET_CODE (x);
5277 enum machine_mode mode = GET_MODE (x);
5278 int mode_width = GET_MODE_BITSIZE (mode);
5279 enum rtx_code next_code;
5285 /* Select the code to be used in recursive calls. Once we are inside an
5286 address, we stay there. If we have a comparison, set to COMPARE,
5287 but once inside, go back to our default of SET. */
5289 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5290 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5291 && XEXP (x, 1) == const0_rtx) ? COMPARE
5292 : in_code == COMPARE ? SET : in_code);
5294 /* Process depending on the code of this operation. If NEW is set
5295 non-zero, it will be returned. */
5300 /* Convert shifts by constants into multiplications if inside
5302 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5303 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5304 && INTVAL (XEXP (x, 1)) >= 0)
5306 new = make_compound_operation (XEXP (x, 0), next_code);
5307 new = gen_rtx_combine (MULT, mode, new,
5308 GEN_INT ((HOST_WIDE_INT) 1
5309 << INTVAL (XEXP (x, 1))));
5314 /* If the second operand is not a constant, we can't do anything
5316 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5319 /* If the constant is a power of two minus one and the first operand
5320 is a logical right shift, make an extraction. */
5321 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5322 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5324 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5325 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5326 0, in_code == COMPARE);
5329 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5330 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5331 && subreg_lowpart_p (XEXP (x, 0))
5332 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5333 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5335 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5337 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5338 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5339 0, in_code == COMPARE);
5341 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5342 else if ((GET_CODE (XEXP (x, 0)) == XOR
5343 || GET_CODE (XEXP (x, 0)) == IOR)
5344 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5345 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5346 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5348 /* Apply the distributive law, and then try to make extractions. */
5349 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5350 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5352 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5354 new = make_compound_operation (new, in_code);
5357 /* If we are have (and (rotate X C) M) and C is larger than the number
5358 of bits in M, this is an extraction. */
5360 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5361 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5362 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5363 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5365 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5366 new = make_extraction (mode, new,
5367 (GET_MODE_BITSIZE (mode)
5368 - INTVAL (XEXP (XEXP (x, 0), 1))),
5369 NULL_RTX, i, 1, 0, in_code == COMPARE);
5372 /* On machines without logical shifts, if the operand of the AND is
5373 a logical shift and our mask turns off all the propagated sign
5374 bits, we can replace the logical shift with an arithmetic shift. */
5375 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5376 && (lshr_optab->handlers[(int) mode].insn_code
5377 == CODE_FOR_nothing)
5378 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5379 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5380 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5381 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5382 && mode_width <= HOST_BITS_PER_WIDE_INT)
5384 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5386 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5387 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5389 gen_rtx_combine (ASHIFTRT, mode,
5390 make_compound_operation (XEXP (XEXP (x, 0), 0),
5392 XEXP (XEXP (x, 0), 1)));
5395 /* If the constant is one less than a power of two, this might be
5396 representable by an extraction even if no shift is present.
5397 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5398 we are in a COMPARE. */
5399 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5400 new = make_extraction (mode,
5401 make_compound_operation (XEXP (x, 0),
5403 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5405 /* If we are in a comparison and this is an AND with a power of two,
5406 convert this into the appropriate bit extract. */
5407 else if (in_code == COMPARE
5408 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5409 new = make_extraction (mode,
5410 make_compound_operation (XEXP (x, 0),
5412 i, NULL_RTX, 1, 1, 0, 1);
5417 /* If the sign bit is known to be zero, replace this with an
5418 arithmetic shift. */
5419 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5420 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5421 && mode_width <= HOST_BITS_PER_WIDE_INT
5422 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5424 new = gen_rtx_combine (ASHIFTRT, mode,
5425 make_compound_operation (XEXP (x, 0),
5431 /* ... fall through ... */
5434 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5435 this is a SIGN_EXTRACT. */
5436 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5437 && GET_CODE (XEXP (x, 0)) == ASHIFT
5438 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5439 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
5441 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5442 new = make_extraction (mode, new,
5443 (INTVAL (XEXP (x, 1))
5444 - INTVAL (XEXP (XEXP (x, 0), 1))),
5445 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5446 code == LSHIFTRT, 0, in_code == COMPARE);
5449 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
5450 cases, we are better off returning a SIGN_EXTEND of the operation. */
5452 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5453 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
5454 || GET_CODE (XEXP (x, 0)) == XOR
5455 || GET_CODE (XEXP (x, 0)) == PLUS)
5456 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5457 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5458 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
5459 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5460 && 0 == (INTVAL (XEXP (XEXP (x, 0), 1))
5461 & (((HOST_WIDE_INT) 1
5462 << (MIN (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)),
5463 INTVAL (XEXP (x, 1)))
5466 rtx c1 = XEXP (XEXP (XEXP (x, 0), 0), 1);
5467 rtx c2 = XEXP (x, 1);
5468 rtx c3 = XEXP (XEXP (x, 0), 1);
5469 HOST_WIDE_INT newop1;
5470 rtx inner = XEXP (XEXP (XEXP (x, 0), 0), 0);
5472 /* If C1 > C2, INNER needs to have the shift performed on it
5474 if (INTVAL (c1) > INTVAL (c2))
5476 inner = gen_binary (ASHIFT, mode, inner,
5477 GEN_INT (INTVAL (c1) - INTVAL (c2)));
5481 newop1 = INTVAL (c3) >> INTVAL (c1);
5482 new = make_compound_operation (inner,
5483 GET_CODE (XEXP (x, 0)) == PLUS
5484 ? MEM : GET_CODE (XEXP (x, 0)));
5485 new = make_extraction (mode,
5486 gen_binary (GET_CODE (XEXP (x, 0)), mode, new,
5488 INTVAL (c2) - INTVAL (c1),
5489 NULL_RTX, mode_width - INTVAL (c2),
5490 code == LSHIFTRT, 0, in_code == COMPARE);
5493 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5494 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5495 && GET_CODE (XEXP (x, 0)) == NEG
5496 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5497 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5498 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5500 new = make_compound_operation (XEXP (XEXP (XEXP (x, 0), 0), 0),
5502 new = make_extraction (mode,
5503 gen_unary (GET_CODE (XEXP (x, 0)), mode, new),
5504 (INTVAL (XEXP (x, 1))
5505 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5506 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5507 code == LSHIFTRT, 0, in_code == COMPARE);
5512 /* Call ourselves recursively on the inner expression. If we are
5513 narrowing the object and it has a different RTL code from
5514 what it originally did, do this SUBREG as a force_to_mode. */
5516 tem = make_compound_operation (SUBREG_REG (x), in_code);
5517 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5518 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5519 && subreg_lowpart_p (x))
5521 rtx newer = force_to_mode (tem, mode,
5522 GET_MODE_MASK (mode), NULL_RTX, 0);
5524 /* If we have something other than a SUBREG, we might have
5525 done an expansion, so rerun outselves. */
5526 if (GET_CODE (newer) != SUBREG)
5527 newer = make_compound_operation (newer, in_code);
5535 x = gen_lowpart_for_combine (mode, new);
5536 code = GET_CODE (x);
5539 /* Now recursively process each operand of this operation. */
5540 fmt = GET_RTX_FORMAT (code);
5541 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5544 new = make_compound_operation (XEXP (x, i), next_code);
5545 SUBST (XEXP (x, i), new);
5551 /* Given M see if it is a value that would select a field of bits
5552 within an item, but not the entire word. Return -1 if not.
5553 Otherwise, return the starting position of the field, where 0 is the
5556 *PLEN is set to the length of the field. */
5559 get_pos_from_mask (m, plen)
5560 unsigned HOST_WIDE_INT m;
5563 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5564 int pos = exact_log2 (m & - m);
5569 /* Now shift off the low-order zero bits and see if we have a power of
5571 *plen = exact_log2 ((m >> pos) + 1);
5579 /* See if X can be simplified knowing that we will only refer to it in
5580 MODE and will only refer to those bits that are nonzero in MASK.
5581 If other bits are being computed or if masking operations are done
5582 that select a superset of the bits in MASK, they can sometimes be
5585 Return a possibly simplified expression, but always convert X to
5586 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5588 Also, if REG is non-zero and X is a register equal in value to REG,
5591 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5592 are all off in X. This is used when X will be complemented, by either
5596 force_to_mode (x, mode, mask, reg, just_select)
5598 enum machine_mode mode;
5599 unsigned HOST_WIDE_INT mask;
5603 enum rtx_code code = GET_CODE (x);
5604 int next_select = just_select || code == XOR || code == NOT;
5605 enum machine_mode op_mode;
5606 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5609 /* We want to perform the operation is its present mode unless we know
5610 that the operation is valid in MODE, in which case we do the operation
5612 op_mode = ((code_to_optab[(int) code] != 0
5613 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5614 != CODE_FOR_nothing))
5615 ? mode : GET_MODE (x));
5617 /* It is not valid to do a right-shift in a narrower mode
5618 than the one it came in with. */
5619 if ((code == LSHIFTRT || code == ASHIFTRT)
5620 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5621 op_mode = GET_MODE (x);
5623 /* Truncate MASK to fit OP_MODE. */
5625 mask &= GET_MODE_MASK (op_mode);
5627 /* When we have an arithmetic operation, or a shift whose count we
5628 do not know, we need to assume that all bit the up to the highest-order
5629 bit in MASK will be needed. This is how we form such a mask. */
5631 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
5632 ? GET_MODE_MASK (op_mode)
5633 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
5635 fuller_mask = ~ (HOST_WIDE_INT) 0;
5637 /* Determine what bits of X are guaranteed to be (non)zero. */
5638 nonzero = nonzero_bits (x, mode);
5640 /* If none of the bits in X are needed, return a zero. */
5641 if (! just_select && (nonzero & mask) == 0)
5644 /* If X is a CONST_INT, return a new one. Do this here since the
5645 test below will fail. */
5646 if (GET_CODE (x) == CONST_INT)
5648 HOST_WIDE_INT cval = INTVAL (x) & mask;
5649 int width = GET_MODE_BITSIZE (mode);
5651 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5652 number, sign extend it. */
5653 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5654 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5655 cval |= (HOST_WIDE_INT) -1 << width;
5657 return GEN_INT (cval);
5660 /* If X is narrower than MODE, just get X in the proper mode. */
5661 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
5662 return gen_lowpart_for_combine (mode, x);
5664 /* If we aren't changing the mode and all zero bits in MASK are already
5665 known to be zero in X, we need not do anything. */
5666 if (GET_MODE (x) == mode && (~ mask & nonzero) == 0)
5672 /* If X is a (clobber (const_int)), return it since we know we are
5673 generating something that won't match. */
5676 #if ! BITS_BIG_ENDIAN
5678 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5679 spanned the boundary of the MEM. If we are now masking so it is
5680 within that boundary, we don't need the USE any more. */
5681 if ((mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5682 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
5689 x = expand_compound_operation (x);
5690 if (GET_CODE (x) != code)
5691 return force_to_mode (x, mode, mask, reg, next_select);
5695 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5696 || rtx_equal_p (reg, get_last_value (x))))
5701 if (subreg_lowpart_p (x)
5702 /* We can ignore the effect this SUBREG if it narrows the mode or,
5703 on machines where register operations are performed on the full
5704 word, if the constant masks to zero all the bits the mode
5706 && ((GET_MODE_SIZE (GET_MODE (x))
5707 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5708 #ifdef WORD_REGISTER_OPERATIONS
5710 & GET_MODE_MASK (GET_MODE (x))
5711 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))
5714 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
5718 /* If this is an AND with a constant, convert it into an AND
5719 whose constant is the AND of that constant with MASK. If it
5720 remains an AND of MASK, delete it since it is redundant. */
5722 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5723 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
5725 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
5726 mask & INTVAL (XEXP (x, 1)));
5728 /* If X is still an AND, see if it is an AND with a mask that
5729 is just some low-order bits. If so, and it is BITS wide (it
5730 can't be wider), we don't need it. */
5732 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5733 && INTVAL (XEXP (x, 1)) == mask)
5742 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5743 low-order bits (as in an alignment operation) and FOO is already
5744 aligned to that boundary, mask C1 to that boundary as well.
5745 This may eliminate that PLUS and, later, the AND. */
5746 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5747 && exact_log2 (- mask) >= 0
5748 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
5749 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
5750 return force_to_mode (plus_constant (XEXP (x, 0),
5751 INTVAL (XEXP (x, 1)) & mask),
5752 mode, mask, reg, next_select);
5754 /* ... fall through ... */
5758 /* For PLUS, MINUS and MULT, we need any bits less significant than the
5759 most significant bit in MASK since carries from those bits will
5760 affect the bits we are interested in. */
5766 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5767 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5768 operation which may be a bitfield extraction. Ensure that the
5769 constant we form is not wider than the mode of X. */
5771 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5772 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5773 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5774 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5775 && GET_CODE (XEXP (x, 1)) == CONST_INT
5776 && ((INTVAL (XEXP (XEXP (x, 0), 1))
5777 + floor_log2 (INTVAL (XEXP (x, 1))))
5778 < GET_MODE_BITSIZE (GET_MODE (x)))
5779 && (INTVAL (XEXP (x, 1))
5780 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x)) == 0))
5782 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
5783 << INTVAL (XEXP (XEXP (x, 0), 1)));
5784 temp = gen_binary (GET_CODE (x), GET_MODE (x),
5785 XEXP (XEXP (x, 0), 0), temp);
5786 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (x, 1));
5787 return force_to_mode (x, mode, mask, reg, next_select);
5791 /* For most binary operations, just propagate into the operation and
5792 change the mode if we have an operation of that mode. */
5794 op0 = gen_lowpart_for_combine (op_mode,
5795 force_to_mode (XEXP (x, 0), mode, mask,
5797 op1 = gen_lowpart_for_combine (op_mode,
5798 force_to_mode (XEXP (x, 1), mode, mask,
5801 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
5802 MASK since OP1 might have been sign-extended but we never want
5803 to turn on extra bits, since combine might have previously relied
5804 on them being off. */
5805 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
5806 && (INTVAL (op1) & mask) != 0)
5807 op1 = GEN_INT (INTVAL (op1) & mask);
5809 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
5810 x = gen_binary (code, op_mode, op0, op1);
5814 /* For left shifts, do the same, but just for the first operand.
5815 However, we cannot do anything with shifts where we cannot
5816 guarantee that the counts are smaller than the size of the mode
5817 because such a count will have a different meaning in a
5820 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
5821 && INTVAL (XEXP (x, 1)) >= 0
5822 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
5823 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
5824 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
5825 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
5828 /* If the shift count is a constant and we can do arithmetic in
5829 the mode of the shift, refine which bits we need. Otherwise, use the
5830 conservative form of the mask. */
5831 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5832 && INTVAL (XEXP (x, 1)) >= 0
5833 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
5834 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
5835 mask >>= INTVAL (XEXP (x, 1));
5839 op0 = gen_lowpart_for_combine (op_mode,
5840 force_to_mode (XEXP (x, 0), op_mode,
5841 mask, reg, next_select));
5843 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
5844 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
5848 /* Here we can only do something if the shift count is a constant,
5849 this shift constant is valid for the host, and we can do arithmetic
5852 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5853 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5854 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
5856 rtx inner = XEXP (x, 0);
5858 /* Select the mask of the bits we need for the shift operand. */
5859 mask <<= INTVAL (XEXP (x, 1));
5861 /* We can only change the mode of the shift if we can do arithmetic
5862 in the mode of the shift and MASK is no wider than the width of
5864 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
5865 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
5866 op_mode = GET_MODE (x);
5868 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
5870 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
5871 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
5874 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
5875 shift and AND produces only copies of the sign bit (C2 is one less
5876 than a power of two), we can do this with just a shift. */
5878 if (GET_CODE (x) == LSHIFTRT
5879 && GET_CODE (XEXP (x, 1)) == CONST_INT
5880 && ((INTVAL (XEXP (x, 1))
5881 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
5882 >= GET_MODE_BITSIZE (GET_MODE (x)))
5883 && exact_log2 (mask + 1) >= 0
5884 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5885 >= exact_log2 (mask + 1)))
5886 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
5887 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
5888 - exact_log2 (mask + 1)));
5892 /* If we are just looking for the sign bit, we don't need this shift at
5893 all, even if it has a variable count. */
5894 if (mask == ((HOST_WIDE_INT) 1
5895 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))
5896 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
5898 /* If this is a shift by a constant, get a mask that contains those bits
5899 that are not copies of the sign bit. We then have two cases: If
5900 MASK only includes those bits, this can be a logical shift, which may
5901 allow simplifications. If MASK is a single-bit field not within
5902 those bits, we are requesting a copy of the sign bit and hence can
5903 shift the sign bit to the appropriate location. */
5905 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
5906 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
5910 nonzero = GET_MODE_MASK (GET_MODE (x));
5911 nonzero >>= INTVAL (XEXP (x, 1));
5913 if ((mask & ~ nonzero) == 0
5914 || (i = exact_log2 (mask)) >= 0)
5916 x = simplify_shift_const
5917 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
5918 i < 0 ? INTVAL (XEXP (x, 1))
5919 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
5921 if (GET_CODE (x) != ASHIFTRT)
5922 return force_to_mode (x, mode, mask, reg, next_select);
5926 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
5927 even if the shift count isn't a constant. */
5929 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
5931 /* If this is a sign-extension operation that just affects bits
5932 we don't care about, remove it. Be sure the call above returned
5933 something that is still a shift. */
5935 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
5936 && GET_CODE (XEXP (x, 1)) == CONST_INT
5937 && INTVAL (XEXP (x, 1)) >= 0
5938 && (INTVAL (XEXP (x, 1))
5939 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
5940 && GET_CODE (XEXP (x, 0)) == ASHIFT
5941 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5942 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5943 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
5950 /* If the shift count is constant and we can do computations
5951 in the mode of X, compute where the bits we care about are.
5952 Otherwise, we can't do anything. Don't change the mode of
5953 the shift or propagate MODE into the shift, though. */
5954 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5955 && INTVAL (XEXP (x, 1)) >= 0)
5957 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
5958 GET_MODE (x), GEN_INT (mask),
5960 if (temp && GET_CODE(temp) == CONST_INT)
5962 force_to_mode (XEXP (x, 0), GET_MODE (x),
5963 INTVAL (temp), reg, next_select));
5968 /* We need any bits less significant than the most significant bit in
5969 MASK since carries from those bits will affect the bits we are
5975 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
5976 same as the XOR case above. Ensure that the constant we form is not
5977 wider than the mode of X. */
5979 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5980 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5981 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5982 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
5983 < GET_MODE_BITSIZE (GET_MODE (x)))
5984 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
5986 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
5987 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
5988 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
5990 return force_to_mode (x, mode, mask, reg, next_select);
5994 op0 = gen_lowpart_for_combine (op_mode,
5995 force_to_mode (XEXP (x, 0), mode, mask,
5997 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
5998 x = gen_unary (code, op_mode, op0);
6002 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6003 in STORE_FLAG_VALUE and FOO has no bits that might be nonzero not
6005 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 0) == const0_rtx
6006 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0)
6007 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6012 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6013 written in a narrower mode. We play it safe and do not do so. */
6016 gen_lowpart_for_combine (GET_MODE (x),
6017 force_to_mode (XEXP (x, 1), mode,
6018 mask, reg, next_select)));
6020 gen_lowpart_for_combine (GET_MODE (x),
6021 force_to_mode (XEXP (x, 2), mode,
6022 mask, reg,next_select)));
6026 /* Ensure we return a value of the proper mode. */
6027 return gen_lowpart_for_combine (mode, x);
6030 /* Return nonzero if X is an expression that has one of two values depending on
6031 whether some other value is zero or nonzero. In that case, we return the
6032 value that is being tested, *PTRUE is set to the value if the rtx being
6033 returned has a nonzero value, and *PFALSE is set to the other alternative.
6035 If we return zero, we set *PTRUE and *PFALSE to X. */
6038 if_then_else_cond (x, ptrue, pfalse)
6040 rtx *ptrue, *pfalse;
6042 enum machine_mode mode = GET_MODE (x);
6043 enum rtx_code code = GET_CODE (x);
6044 int size = GET_MODE_BITSIZE (mode);
6045 rtx cond0, cond1, true0, true1, false0, false1;
6046 unsigned HOST_WIDE_INT nz;
6048 /* If this is a unary operation whose operand has one of two values, apply
6049 our opcode to compute those values. */
6050 if (GET_RTX_CLASS (code) == '1'
6051 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6053 *ptrue = gen_unary (code, mode, true0);
6054 *pfalse = gen_unary (code, mode, false0);
6058 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6059 make can't possibly match and would supress other optimizations. */
6060 else if (code == COMPARE)
6063 /* If this is a binary operation, see if either side has only one of two
6064 values. If either one does or if both do and they are conditional on
6065 the same value, compute the new true and false values. */
6066 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6067 || GET_RTX_CLASS (code) == '<')
6069 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6070 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6072 if ((cond0 != 0 || cond1 != 0)
6073 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6075 *ptrue = gen_binary (code, mode, true0, true1);
6076 *pfalse = gen_binary (code, mode, false0, false1);
6077 return cond0 ? cond0 : cond1;
6080 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6082 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6083 operands is zero when the other is non-zero, and vice-versa. */
6085 if ((code == PLUS || code == IOR || code == XOR || code == MINUS
6087 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6089 rtx op0 = XEXP (XEXP (x, 0), 1);
6090 rtx op1 = XEXP (XEXP (x, 1), 1);
6092 cond0 = XEXP (XEXP (x, 0), 0);
6093 cond1 = XEXP (XEXP (x, 1), 0);
6095 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6096 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6097 && reversible_comparison_p (cond1)
6098 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6099 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6100 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6101 || ((swap_condition (GET_CODE (cond0))
6102 == reverse_condition (GET_CODE (cond1)))
6103 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6104 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6105 && ! side_effects_p (x))
6107 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6108 *pfalse = gen_binary (MULT, mode,
6110 ? gen_unary (NEG, mode, op1) : op1),
6116 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6118 if ((code == MULT || code == AND || code == UMIN)
6119 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6121 cond0 = XEXP (XEXP (x, 0), 0);
6122 cond1 = XEXP (XEXP (x, 1), 0);
6124 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6125 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6126 && reversible_comparison_p (cond1)
6127 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6128 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6129 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6130 || ((swap_condition (GET_CODE (cond0))
6131 == reverse_condition (GET_CODE (cond1)))
6132 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6133 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6134 && ! side_effects_p (x))
6136 *ptrue = *pfalse = const0_rtx;
6143 else if (code == IF_THEN_ELSE)
6145 /* If we have IF_THEN_ELSE already, extract the condition and
6146 canonicalize it if it is NE or EQ. */
6147 cond0 = XEXP (x, 0);
6148 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6149 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6150 return XEXP (cond0, 0);
6151 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6153 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6154 return XEXP (cond0, 0);
6160 /* If X is a normal SUBREG with both inner and outer modes integral,
6161 we can narrow both the true and false values of the inner expression,
6162 if there is a condition. */
6163 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6164 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6165 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6166 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6169 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6171 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6176 /* If X is a constant, this isn't special and will cause confusions
6177 if we treat it as such. Likewise if it is equivalent to a constant. */
6178 else if (CONSTANT_P (x)
6179 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6182 /* If X is known to be either 0 or -1, those are the true and
6183 false values when testing X. */
6184 else if (num_sign_bit_copies (x, mode) == size)
6186 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6190 /* Likewise for 0 or a single bit. */
6191 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6193 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6197 /* Otherwise fail; show no condition with true and false values the same. */
6198 *ptrue = *pfalse = x;
6202 /* Return the value of expression X given the fact that condition COND
6203 is known to be true when applied to REG as its first operand and VAL
6204 as its second. X is known to not be shared and so can be modified in
6207 We only handle the simplest cases, and specifically those cases that
6208 arise with IF_THEN_ELSE expressions. */
6211 known_cond (x, cond, reg, val)
6216 enum rtx_code code = GET_CODE (x);
6221 if (side_effects_p (x))
6224 if (cond == EQ && rtx_equal_p (x, reg))
6227 /* If X is (abs REG) and we know something about REG's relationship
6228 with zero, we may be able to simplify this. */
6230 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6233 case GE: case GT: case EQ:
6236 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
6239 /* The only other cases we handle are MIN, MAX, and comparisons if the
6240 operands are the same as REG and VAL. */
6242 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6244 if (rtx_equal_p (XEXP (x, 0), val))
6245 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6247 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6249 if (GET_RTX_CLASS (code) == '<')
6250 return (comparison_dominates_p (cond, code) ? const_true_rtx
6251 : (comparison_dominates_p (cond,
6252 reverse_condition (code))
6255 else if (code == SMAX || code == SMIN
6256 || code == UMIN || code == UMAX)
6258 int unsignedp = (code == UMIN || code == UMAX);
6260 if (code == SMAX || code == UMAX)
6261 cond = reverse_condition (cond);
6266 return unsignedp ? x : XEXP (x, 1);
6268 return unsignedp ? x : XEXP (x, 0);
6270 return unsignedp ? XEXP (x, 1) : x;
6272 return unsignedp ? XEXP (x, 0) : x;
6278 fmt = GET_RTX_FORMAT (code);
6279 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6282 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6283 else if (fmt[i] == 'E')
6284 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6285 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6292 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6293 Return that assignment if so.
6295 We only handle the most common cases. */
6298 make_field_assignment (x)
6301 rtx dest = SET_DEST (x);
6302 rtx src = SET_SRC (x);
6307 enum machine_mode mode;
6309 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6310 a clear of a one-bit field. We will have changed it to
6311 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6314 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6315 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6316 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6317 && (rtx_equal_p (dest, XEXP (src, 1))
6318 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6319 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
6321 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6323 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6326 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6327 && subreg_lowpart_p (XEXP (src, 0))
6328 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6329 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6330 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6331 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6332 && (rtx_equal_p (dest, XEXP (src, 1))
6333 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6334 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
6336 assign = make_extraction (VOIDmode, dest, 0,
6337 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6339 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6342 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
6344 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6345 && XEXP (XEXP (src, 0), 0) == const1_rtx
6346 && (rtx_equal_p (dest, XEXP (src, 1))
6347 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
6348 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
6350 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6352 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6355 /* The other case we handle is assignments into a constant-position
6356 field. They look like (ior (and DEST C1) OTHER). If C1 represents
6357 a mask that has all one bits except for a group of zero bits and
6358 OTHER is known to have zeros where C1 has ones, this is such an
6359 assignment. Compute the position and length from C1. Shift OTHER
6360 to the appropriate position, force it to the required mode, and
6361 make the extraction. Check for the AND in both operands. */
6363 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
6364 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
6365 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
6366 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
6367 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
6368 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
6369 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
6370 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
6371 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
6372 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
6373 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
6375 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
6379 pos = get_pos_from_mask (c1 ^ GET_MODE_MASK (GET_MODE (dest)), &len);
6380 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6381 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6382 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6385 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6387 /* The mode to use for the source is the mode of the assignment, or of
6388 what is inside a possible STRICT_LOW_PART. */
6389 mode = (GET_CODE (assign) == STRICT_LOW_PART
6390 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6392 /* Shift OTHER right POS places and make it the source, restricting it
6393 to the proper length and mode. */
6395 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6396 GET_MODE (src), other, pos),
6398 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6399 ? GET_MODE_MASK (mode)
6400 : ((HOST_WIDE_INT) 1 << len) - 1,
6403 return gen_rtx_combine (SET, VOIDmode, assign, src);
6406 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6410 apply_distributive_law (x)
6413 enum rtx_code code = GET_CODE (x);
6414 rtx lhs, rhs, other;
6416 enum rtx_code inner_code;
6418 /* Distributivity is not true for floating point.
6419 It can change the value. So don't do it.
6420 -- rms and moshier@world.std.com. */
6421 if (FLOAT_MODE_P (GET_MODE (x)))
6424 /* The outer operation can only be one of the following: */
6425 if (code != IOR && code != AND && code != XOR
6426 && code != PLUS && code != MINUS)
6429 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6431 /* If either operand is a primitive we can't do anything, so get out fast. */
6432 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6433 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6436 lhs = expand_compound_operation (lhs);
6437 rhs = expand_compound_operation (rhs);
6438 inner_code = GET_CODE (lhs);
6439 if (inner_code != GET_CODE (rhs))
6442 /* See if the inner and outer operations distribute. */
6449 /* These all distribute except over PLUS. */
6450 if (code == PLUS || code == MINUS)
6455 if (code != PLUS && code != MINUS)
6460 /* This is also a multiply, so it distributes over everything. */
6464 /* Non-paradoxical SUBREGs distributes over all operations, provided
6465 the inner modes and word numbers are the same, this is an extraction
6466 of a low-order part, we don't convert an fp operation to int or
6467 vice versa, and we would not be converting a single-word
6468 operation into a multi-word operation. The latter test is not
6469 required, but it prevents generating unneeded multi-word operations.
6470 Some of the previous tests are redundant given the latter test, but
6471 are retained because they are required for correctness.
6473 We produce the result slightly differently in this case. */
6475 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6476 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6477 || ! subreg_lowpart_p (lhs)
6478 || (GET_MODE_CLASS (GET_MODE (lhs))
6479 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6480 || (GET_MODE_SIZE (GET_MODE (lhs))
6481 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6482 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6485 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6486 SUBREG_REG (lhs), SUBREG_REG (rhs));
6487 return gen_lowpart_for_combine (GET_MODE (x), tem);
6493 /* Set LHS and RHS to the inner operands (A and B in the example
6494 above) and set OTHER to the common operand (C in the example).
6495 These is only one way to do this unless the inner operation is
6497 if (GET_RTX_CLASS (inner_code) == 'c'
6498 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6499 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6500 else if (GET_RTX_CLASS (inner_code) == 'c'
6501 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6502 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6503 else if (GET_RTX_CLASS (inner_code) == 'c'
6504 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6505 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6506 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6507 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
6511 /* Form the new inner operation, seeing if it simplifies first. */
6512 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
6514 /* There is one exception to the general way of distributing:
6515 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6516 if (code == XOR && inner_code == IOR)
6519 other = gen_unary (NOT, GET_MODE (x), other);
6522 /* We may be able to continuing distributing the result, so call
6523 ourselves recursively on the inner operation before forming the
6524 outer operation, which we return. */
6525 return gen_binary (inner_code, GET_MODE (x),
6526 apply_distributive_law (tem), other);
6529 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6532 Return an equivalent form, if different from X. Otherwise, return X. If
6533 X is zero, we are to always construct the equivalent form. */
6536 simplify_and_const_int (x, mode, varop, constop)
6538 enum machine_mode mode;
6540 unsigned HOST_WIDE_INT constop;
6542 unsigned HOST_WIDE_INT nonzero;
6545 /* Simplify VAROP knowing that we will be only looking at some of the
6547 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
6549 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6550 CONST_INT, we are done. */
6551 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
6554 /* See what bits may be nonzero in VAROP. Unlike the general case of
6555 a call to nonzero_bits, here we don't care about bits outside
6558 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6560 /* Turn off all bits in the constant that are known to already be zero.
6561 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6562 which is tested below. */
6566 /* If we don't have any bits left, return zero. */
6570 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
6571 a power of two, we can replace this with a ASHIFT. */
6572 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
6573 && (i = exact_log2 (constop)) >= 0)
6574 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
6576 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
6577 or XOR, then try to apply the distributive law. This may eliminate
6578 operations if either branch can be simplified because of the AND.
6579 It may also make some cases more complex, but those cases probably
6580 won't match a pattern either with or without this. */
6582 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
6584 gen_lowpart_for_combine
6586 apply_distributive_law
6587 (gen_binary (GET_CODE (varop), GET_MODE (varop),
6588 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6589 XEXP (varop, 0), constop),
6590 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6591 XEXP (varop, 1), constop))));
6593 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6594 if we already had one (just check for the simplest cases). */
6595 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6596 && GET_MODE (XEXP (x, 0)) == mode
6597 && SUBREG_REG (XEXP (x, 0)) == varop)
6598 varop = XEXP (x, 0);
6600 varop = gen_lowpart_for_combine (mode, varop);
6602 /* If we can't make the SUBREG, try to return what we were given. */
6603 if (GET_CODE (varop) == CLOBBER)
6604 return x ? x : varop;
6606 /* If we are only masking insignificant bits, return VAROP. */
6607 if (constop == nonzero)
6610 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6611 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6612 x = gen_binary (AND, mode, varop, GEN_INT (constop));
6616 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6617 || INTVAL (XEXP (x, 1)) != constop)
6618 SUBST (XEXP (x, 1), GEN_INT (constop));
6620 SUBST (XEXP (x, 0), varop);
6626 /* Given an expression, X, compute which bits in X can be non-zero.
6627 We don't care about bits outside of those defined in MODE.
6629 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6630 a shift, AND, or zero_extract, we can do better. */
6632 static unsigned HOST_WIDE_INT
6633 nonzero_bits (x, mode)
6635 enum machine_mode mode;
6637 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6638 unsigned HOST_WIDE_INT inner_nz;
6640 int mode_width = GET_MODE_BITSIZE (mode);
6643 /* If X is wider than MODE, use its mode instead. */
6644 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6646 mode = GET_MODE (x);
6647 nonzero = GET_MODE_MASK (mode);
6648 mode_width = GET_MODE_BITSIZE (mode);
6651 if (mode_width > HOST_BITS_PER_WIDE_INT)
6652 /* Our only callers in this case look for single bit values. So
6653 just return the mode mask. Those tests will then be false. */
6656 #ifndef WORD_REGISTER_OPERATIONS
6657 /* If MODE is wider than X, but both are a single word for both the host
6658 and target machines, we can compute this from which bits of the
6659 object might be nonzero in its own mode, taking into account the fact
6660 that on many CISC machines, accessing an object in a wider mode
6661 causes the high-order bits to become undefined. So they are
6662 not known to be zero. */
6664 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
6665 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
6666 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6667 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
6669 nonzero &= nonzero_bits (x, GET_MODE (x));
6670 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
6675 code = GET_CODE (x);
6679 #ifdef STACK_BOUNDARY
6680 /* If this is the stack pointer, we may know something about its
6681 alignment. If PUSH_ROUNDING is defined, it is possible for the
6682 stack to be momentarily aligned only to that amount, so we pick
6683 the least alignment. */
6685 if (x == stack_pointer_rtx)
6687 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6689 #ifdef PUSH_ROUNDING
6690 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6693 return nonzero & ~ (sp_alignment - 1);
6697 /* If X is a register whose nonzero bits value is current, use it.
6698 Otherwise, if X is a register whose value we can find, use that
6699 value. Otherwise, use the previously-computed global nonzero bits
6700 for this register. */
6702 if (reg_last_set_value[REGNO (x)] != 0
6703 && reg_last_set_mode[REGNO (x)] == mode
6704 && (reg_n_sets[REGNO (x)] == 1
6705 || reg_last_set_label[REGNO (x)] == label_tick)
6706 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6707 return reg_last_set_nonzero_bits[REGNO (x)];
6709 tem = get_last_value (x);
6713 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6714 /* If X is narrower than MODE and TEM is a non-negative
6715 constant that would appear negative in the mode of X,
6716 sign-extend it for use in reg_nonzero_bits because some
6717 machines (maybe most) will actually do the sign-extension
6718 and this is the conservative approach.
6720 ??? For 2.5, try to tighten up the MD files in this regard
6721 instead of this kludge. */
6723 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
6724 && GET_CODE (tem) == CONST_INT
6726 && 0 != (INTVAL (tem)
6727 & ((HOST_WIDE_INT) 1
6728 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6729 tem = GEN_INT (INTVAL (tem)
6730 | ((HOST_WIDE_INT) (-1)
6731 << GET_MODE_BITSIZE (GET_MODE (x))));
6733 return nonzero_bits (tem, mode);
6735 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
6736 return reg_nonzero_bits[REGNO (x)] & nonzero;
6741 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6742 /* If X is negative in MODE, sign-extend the value. */
6743 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
6744 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
6745 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
6751 #ifdef LOAD_EXTEND_OP
6752 /* In many, if not most, RISC machines, reading a byte from memory
6753 zeros the rest of the register. Noticing that fact saves a lot
6754 of extra zero-extends. */
6755 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
6756 nonzero &= GET_MODE_MASK (GET_MODE (x));
6766 /* If this produces an integer result, we know which bits are set.
6767 Code here used to clear bits outside the mode of X, but that is
6770 if (GET_MODE_CLASS (mode) == MODE_INT
6771 && mode_width <= HOST_BITS_PER_WIDE_INT)
6772 nonzero = STORE_FLAG_VALUE;
6776 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6777 == GET_MODE_BITSIZE (GET_MODE (x)))
6780 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6781 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6785 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6786 == GET_MODE_BITSIZE (GET_MODE (x)))
6791 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6795 nonzero &= nonzero_bits (XEXP (x, 0), mode);
6796 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6797 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6801 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6802 Otherwise, show all the bits in the outer mode but not the inner
6804 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6805 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6807 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6810 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6811 inner_nz |= (GET_MODE_MASK (mode)
6812 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6815 nonzero &= inner_nz;
6819 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6820 & nonzero_bits (XEXP (x, 1), mode));
6824 case UMIN: case UMAX: case SMIN: case SMAX:
6825 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6826 | nonzero_bits (XEXP (x, 1), mode));
6829 case PLUS: case MINUS:
6831 case DIV: case UDIV:
6832 case MOD: case UMOD:
6833 /* We can apply the rules of arithmetic to compute the number of
6834 high- and low-order zero bits of these operations. We start by
6835 computing the width (position of the highest-order non-zero bit)
6836 and the number of low-order zero bits for each value. */
6838 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
6839 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
6840 int width0 = floor_log2 (nz0) + 1;
6841 int width1 = floor_log2 (nz1) + 1;
6842 int low0 = floor_log2 (nz0 & -nz0);
6843 int low1 = floor_log2 (nz1 & -nz1);
6844 int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6845 int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6846 int result_width = mode_width;
6852 result_width = MAX (width0, width1) + 1;
6853 result_low = MIN (low0, low1);
6856 result_low = MIN (low0, low1);
6859 result_width = width0 + width1;
6860 result_low = low0 + low1;
6863 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6864 result_width = width0;
6867 result_width = width0;
6870 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6871 result_width = MIN (width0, width1);
6872 result_low = MIN (low0, low1);
6875 result_width = MIN (width0, width1);
6876 result_low = MIN (low0, low1);
6880 if (result_width < mode_width)
6881 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6884 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6889 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6890 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6891 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6895 /* If this is a SUBREG formed for a promoted variable that has
6896 been zero-extended, we know that at least the high-order bits
6897 are zero, though others might be too. */
6899 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6900 nonzero = (GET_MODE_MASK (GET_MODE (x))
6901 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
6903 /* If the inner mode is a single word for both the host and target
6904 machines, we can compute this from which bits of the inner
6905 object might be nonzero. */
6906 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6907 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6908 <= HOST_BITS_PER_WIDE_INT))
6910 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
6912 #ifndef WORD_REGISTER_OPERATIONS
6913 /* On many CISC machines, accessing an object in a wider mode
6914 causes the high-order bits to become undefined. So they are
6915 not known to be zero. */
6916 if (GET_MODE_SIZE (GET_MODE (x))
6917 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6918 nonzero |= (GET_MODE_MASK (GET_MODE (x))
6919 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6928 /* The nonzero bits are in two classes: any bits within MODE
6929 that aren't in GET_MODE (x) are always significant. The rest of the
6930 nonzero bits are those that are significant in the operand of
6931 the shift when shifted the appropriate number of bits. This
6932 shows that high-order bits are cleared by the right shift and
6933 low-order bits by left shifts. */
6934 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6935 && INTVAL (XEXP (x, 1)) >= 0
6936 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6938 enum machine_mode inner_mode = GET_MODE (x);
6939 int width = GET_MODE_BITSIZE (inner_mode);
6940 int count = INTVAL (XEXP (x, 1));
6941 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6942 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
6943 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
6944 unsigned HOST_WIDE_INT outer = 0;
6946 if (mode_width > width)
6947 outer = (op_nonzero & nonzero & ~ mode_mask);
6949 if (code == LSHIFTRT)
6951 else if (code == ASHIFTRT)
6955 /* If the sign bit may have been nonzero before the shift, we
6956 need to mark all the places it could have been copied to
6957 by the shift as possibly nonzero. */
6958 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6959 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6961 else if (code == ASHIFT)
6964 inner = ((inner << (count % width)
6965 | (inner >> (width - (count % width)))) & mode_mask);
6967 nonzero &= (outer | inner);
6972 /* This is at most the number of bits in the mode. */
6973 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6977 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
6978 | nonzero_bits (XEXP (x, 2), mode));
6985 /* Return the number of bits at the high-order end of X that are known to
6986 be equal to the sign bit. X will be used in mode MODE; if MODE is
6987 VOIDmode, X will be used in its own mode. The returned value will always
6988 be between 1 and the number of bits in MODE. */
6991 num_sign_bit_copies (x, mode)
6993 enum machine_mode mode;
6995 enum rtx_code code = GET_CODE (x);
6997 int num0, num1, result;
6998 unsigned HOST_WIDE_INT nonzero;
7001 /* If we weren't given a mode, use the mode of X. If the mode is still
7002 VOIDmode, we don't know anything. */
7004 if (mode == VOIDmode)
7005 mode = GET_MODE (x);
7007 if (mode == VOIDmode)
7010 bitwidth = GET_MODE_BITSIZE (mode);
7012 /* For a smaller object, just ignore the high bits. */
7013 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7014 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7015 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7017 #ifndef WORD_REGISTER_OPERATIONS
7018 /* If this machine does not do all register operations on the entire
7019 register and MODE is wider than the mode of X, we can say nothing
7020 at all about the high-order bits. */
7021 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7029 if (reg_last_set_value[REGNO (x)] != 0
7030 && reg_last_set_mode[REGNO (x)] == mode
7031 && (reg_n_sets[REGNO (x)] == 1
7032 || reg_last_set_label[REGNO (x)] == label_tick)
7033 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7034 return reg_last_set_sign_bit_copies[REGNO (x)];
7036 tem = get_last_value (x);
7038 return num_sign_bit_copies (tem, mode);
7040 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7041 return reg_sign_bit_copies[REGNO (x)];
7045 #ifdef LOAD_EXTEND_OP
7046 /* Some RISC machines sign-extend all loads of smaller than a word. */
7047 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7048 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7053 /* If the constant is negative, take its 1's complement and remask.
7054 Then see how many zero bits we have. */
7055 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7056 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7057 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7058 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7060 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7063 /* If this is a SUBREG for a promoted object that is sign-extended
7064 and we are looking at it in a wider mode, we know that at least the
7065 high-order bits are known to be sign bit copies. */
7067 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7068 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7069 num_sign_bit_copies (SUBREG_REG (x), mode));
7071 /* For a smaller object, just ignore the high bits. */
7072 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7074 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7075 return MAX (1, (num0
7076 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7080 #ifdef WORD_REGISTER_OPERATIONS
7081 /* For paradoxical SUBREGs on machines where all register operations
7082 affect the entire register, just look inside. Note that we are
7083 passing MODE to the recursive call, so the number of sign bit copies
7084 will remain relative to that mode, not the inner mode. */
7086 if (GET_MODE_SIZE (GET_MODE (x))
7087 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7088 return num_sign_bit_copies (SUBREG_REG (x), mode);
7093 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7094 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7098 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7099 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7102 /* For a smaller object, just ignore the high bits. */
7103 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7104 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7108 return num_sign_bit_copies (XEXP (x, 0), mode);
7110 case ROTATE: case ROTATERT:
7111 /* If we are rotating left by a number of bits less than the number
7112 of sign bit copies, we can just subtract that amount from the
7114 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7115 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7117 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7118 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7119 : bitwidth - INTVAL (XEXP (x, 1))));
7124 /* In general, this subtracts one sign bit copy. But if the value
7125 is known to be positive, the number of sign bit copies is the
7126 same as that of the input. Finally, if the input has just one bit
7127 that might be nonzero, all the bits are copies of the sign bit. */
7128 nonzero = nonzero_bits (XEXP (x, 0), mode);
7132 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7134 && bitwidth <= HOST_BITS_PER_WIDE_INT
7135 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7140 case IOR: case AND: case XOR:
7141 case SMIN: case SMAX: case UMIN: case UMAX:
7142 /* Logical operations will preserve the number of sign-bit copies.
7143 MIN and MAX operations always return one of the operands. */
7144 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7145 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7146 return MIN (num0, num1);
7148 case PLUS: case MINUS:
7149 /* For addition and subtraction, we can have a 1-bit carry. However,
7150 if we are subtracting 1 from a positive number, there will not
7151 be such a carry. Furthermore, if the positive number is known to
7152 be 0 or 1, we know the result is either -1 or 0. */
7154 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7155 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7157 nonzero = nonzero_bits (XEXP (x, 0), mode);
7158 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7159 return (nonzero == 1 || nonzero == 0 ? bitwidth
7160 : bitwidth - floor_log2 (nonzero) - 1);
7163 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7164 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7165 return MAX (1, MIN (num0, num1) - 1);
7168 /* The number of bits of the product is the sum of the number of
7169 bits of both terms. However, unless one of the terms if known
7170 to be positive, we must allow for an additional bit since negating
7171 a negative number can remove one sign bit copy. */
7173 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7174 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7176 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7178 && bitwidth <= HOST_BITS_PER_WIDE_INT
7179 && ((nonzero_bits (XEXP (x, 0), mode)
7180 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7181 && (nonzero_bits (XEXP (x, 1), mode)
7182 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
7185 return MAX (1, result);
7188 /* The result must be <= the first operand. */
7189 return num_sign_bit_copies (XEXP (x, 0), mode);
7192 /* The result must be <= the scond operand. */
7193 return num_sign_bit_copies (XEXP (x, 1), mode);
7196 /* Similar to unsigned division, except that we have to worry about
7197 the case where the divisor is negative, in which case we have
7199 result = num_sign_bit_copies (XEXP (x, 0), mode);
7201 && bitwidth <= HOST_BITS_PER_WIDE_INT
7202 && (nonzero_bits (XEXP (x, 1), mode)
7203 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7209 result = num_sign_bit_copies (XEXP (x, 1), mode);
7211 && bitwidth <= HOST_BITS_PER_WIDE_INT
7212 && (nonzero_bits (XEXP (x, 1), mode)
7213 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7219 /* Shifts by a constant add to the number of bits equal to the
7221 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7222 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7223 && INTVAL (XEXP (x, 1)) > 0)
7224 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7229 /* Left shifts destroy copies. */
7230 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7231 || INTVAL (XEXP (x, 1)) < 0
7232 || INTVAL (XEXP (x, 1)) >= bitwidth)
7235 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7236 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7239 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7240 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7241 return MIN (num0, num1);
7243 #if STORE_FLAG_VALUE == -1
7244 case EQ: case NE: case GE: case GT: case LE: case LT:
7245 case GEU: case GTU: case LEU: case LTU:
7250 /* If we haven't been able to figure it out by one of the above rules,
7251 see if some of the high-order bits are known to be zero. If so,
7252 count those bits and return one less than that amount. If we can't
7253 safely compute the mask for this mode, always return BITWIDTH. */
7255 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7258 nonzero = nonzero_bits (x, mode);
7259 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7260 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7263 /* Return the number of "extended" bits there are in X, when interpreted
7264 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7265 unsigned quantities, this is the number of high-order zero bits.
7266 For signed quantities, this is the number of copies of the sign bit
7267 minus 1. In both case, this function returns the number of "spare"
7268 bits. For example, if two quantities for which this function returns
7269 at least 1 are added, the addition is known not to overflow.
7271 This function will always return 0 unless called during combine, which
7272 implies that it must be called from a define_split. */
7275 extended_count (x, mode, unsignedp)
7277 enum machine_mode mode;
7280 if (nonzero_sign_valid == 0)
7284 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7285 && (GET_MODE_BITSIZE (mode) - 1
7286 - floor_log2 (nonzero_bits (x, mode))))
7287 : num_sign_bit_copies (x, mode) - 1);
7290 /* This function is called from `simplify_shift_const' to merge two
7291 outer operations. Specifically, we have already found that we need
7292 to perform operation *POP0 with constant *PCONST0 at the outermost
7293 position. We would now like to also perform OP1 with constant CONST1
7294 (with *POP0 being done last).
7296 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7297 the resulting operation. *PCOMP_P is set to 1 if we would need to
7298 complement the innermost operand, otherwise it is unchanged.
7300 MODE is the mode in which the operation will be done. No bits outside
7301 the width of this mode matter. It is assumed that the width of this mode
7302 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7304 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7305 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7306 result is simply *PCONST0.
7308 If the resulting operation cannot be expressed as one operation, we
7309 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7312 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7313 enum rtx_code *pop0;
7314 HOST_WIDE_INT *pconst0;
7316 HOST_WIDE_INT const1;
7317 enum machine_mode mode;
7320 enum rtx_code op0 = *pop0;
7321 HOST_WIDE_INT const0 = *pconst0;
7323 const0 &= GET_MODE_MASK (mode);
7324 const1 &= GET_MODE_MASK (mode);
7326 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7330 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7333 if (op1 == NIL || op0 == SET)
7336 else if (op0 == NIL)
7337 op0 = op1, const0 = const1;
7339 else if (op0 == op1)
7361 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7362 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7365 /* If the two constants aren't the same, we can't do anything. The
7366 remaining six cases can all be done. */
7367 else if (const0 != const1)
7375 /* (a & b) | b == b */
7377 else /* op1 == XOR */
7378 /* (a ^ b) | b == a | b */
7384 /* (a & b) ^ b == (~a) & b */
7385 op0 = AND, *pcomp_p = 1;
7386 else /* op1 == IOR */
7387 /* (a | b) ^ b == a & ~b */
7388 op0 = AND, *pconst0 = ~ const0;
7393 /* (a | b) & b == b */
7395 else /* op1 == XOR */
7396 /* (a ^ b) & b) == (~a) & b */
7401 /* Check for NO-OP cases. */
7402 const0 &= GET_MODE_MASK (mode);
7404 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7406 else if (const0 == 0 && op0 == AND)
7408 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7417 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7418 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7419 that we started with.
7421 The shift is normally computed in the widest mode we find in VAROP, as
7422 long as it isn't a different number of words than RESULT_MODE. Exceptions
7423 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7426 simplify_shift_const (x, code, result_mode, varop, count)
7429 enum machine_mode result_mode;
7433 enum rtx_code orig_code = code;
7434 int orig_count = count;
7435 enum machine_mode mode = result_mode;
7436 enum machine_mode shift_mode, tmode;
7438 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7439 /* We form (outer_op (code varop count) (outer_const)). */
7440 enum rtx_code outer_op = NIL;
7441 HOST_WIDE_INT outer_const = 0;
7443 int complement_p = 0;
7446 /* If we were given an invalid count, don't do anything except exactly
7447 what was requested. */
7449 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7454 return gen_rtx (code, mode, varop, GEN_INT (count));
7457 /* Unless one of the branches of the `if' in this loop does a `continue',
7458 we will `break' the loop after the `if'. */
7462 /* If we have an operand of (clobber (const_int 0)), just return that
7464 if (GET_CODE (varop) == CLOBBER)
7467 /* If we discovered we had to complement VAROP, leave. Making a NOT
7468 here would cause an infinite loop. */
7472 /* Convert ROTATETRT to ROTATE. */
7473 if (code == ROTATERT)
7474 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7476 /* We need to determine what mode we will do the shift in. If the
7477 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
7478 was originally done in. Otherwise, we can do it in MODE, the widest
7479 mode encountered. */
7480 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7482 /* Handle cases where the count is greater than the size of the mode
7483 minus 1. For ASHIFT, use the size minus one as the count (this can
7484 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7485 take the count modulo the size. For other shifts, the result is
7488 Since these shifts are being produced by the compiler by combining
7489 multiple operations, each of which are defined, we know what the
7490 result is supposed to be. */
7492 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
7494 if (code == ASHIFTRT)
7495 count = GET_MODE_BITSIZE (shift_mode) - 1;
7496 else if (code == ROTATE || code == ROTATERT)
7497 count %= GET_MODE_BITSIZE (shift_mode);
7500 /* We can't simply return zero because there may be an
7508 /* Negative counts are invalid and should not have been made (a
7509 programmer-specified negative count should have been handled
7514 /* An arithmetic right shift of a quantity known to be -1 or 0
7516 if (code == ASHIFTRT
7517 && (num_sign_bit_copies (varop, shift_mode)
7518 == GET_MODE_BITSIZE (shift_mode)))
7524 /* If we are doing an arithmetic right shift and discarding all but
7525 the sign bit copies, this is equivalent to doing a shift by the
7526 bitsize minus one. Convert it into that shift because it will often
7527 allow other simplifications. */
7529 if (code == ASHIFTRT
7530 && (count + num_sign_bit_copies (varop, shift_mode)
7531 >= GET_MODE_BITSIZE (shift_mode)))
7532 count = GET_MODE_BITSIZE (shift_mode) - 1;
7534 /* We simplify the tests below and elsewhere by converting
7535 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7536 `make_compound_operation' will convert it to a ASHIFTRT for
7537 those machines (such as Vax) that don't have a LSHIFTRT. */
7538 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
7540 && ((nonzero_bits (varop, shift_mode)
7541 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
7545 switch (GET_CODE (varop))
7551 new = expand_compound_operation (varop);
7560 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7561 minus the width of a smaller mode, we can do this with a
7562 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7563 if ((code == ASHIFTRT || code == LSHIFTRT)
7564 && ! mode_dependent_address_p (XEXP (varop, 0))
7565 && ! MEM_VOLATILE_P (varop)
7566 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7567 MODE_INT, 1)) != BLKmode)
7569 #if BYTES_BIG_ENDIAN
7570 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
7572 new = gen_rtx (MEM, tmode,
7573 plus_constant (XEXP (varop, 0),
7574 count / BITS_PER_UNIT));
7575 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7576 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7577 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7579 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7580 : ZERO_EXTEND, mode, new);
7587 /* Similar to the case above, except that we can only do this if
7588 the resulting mode is the same as that of the underlying
7589 MEM and adjust the address depending on the *bits* endianness
7590 because of the way that bit-field extract insns are defined. */
7591 if ((code == ASHIFTRT || code == LSHIFTRT)
7592 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7593 MODE_INT, 1)) != BLKmode
7594 && tmode == GET_MODE (XEXP (varop, 0)))
7597 new = XEXP (varop, 0);
7599 new = copy_rtx (XEXP (varop, 0));
7600 SUBST (XEXP (new, 0),
7601 plus_constant (XEXP (new, 0),
7602 count / BITS_PER_UNIT));
7605 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7606 : ZERO_EXTEND, mode, new);
7613 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7614 the same number of words as what we've seen so far. Then store
7615 the widest mode in MODE. */
7616 if (subreg_lowpart_p (varop)
7617 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7618 > GET_MODE_SIZE (GET_MODE (varop)))
7619 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7620 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7623 varop = SUBREG_REG (varop);
7624 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
7625 mode = GET_MODE (varop);
7631 /* Some machines use MULT instead of ASHIFT because MULT
7632 is cheaper. But it is still better on those machines to
7633 merge two shifts into one. */
7634 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7635 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7637 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
7638 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
7644 /* Similar, for when divides are cheaper. */
7645 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7646 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7648 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
7649 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
7655 /* If we are extracting just the sign bit of an arithmetic right
7656 shift, that shift is not needed. */
7657 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
7659 varop = XEXP (varop, 0);
7663 /* ... fall through ... */
7668 /* Here we have two nested shifts. The result is usually the
7669 AND of a new shift with a mask. We compute the result below. */
7670 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7671 && INTVAL (XEXP (varop, 1)) >= 0
7672 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
7673 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7674 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
7676 enum rtx_code first_code = GET_CODE (varop);
7677 int first_count = INTVAL (XEXP (varop, 1));
7678 unsigned HOST_WIDE_INT mask;
7681 /* We have one common special case. We can't do any merging if
7682 the inner code is an ASHIFTRT of a smaller mode. However, if
7683 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
7684 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
7685 we can convert it to
7686 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
7687 This simplifies certain SIGN_EXTEND operations. */
7688 if (code == ASHIFT && first_code == ASHIFTRT
7689 && (GET_MODE_BITSIZE (result_mode)
7690 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
7692 /* C3 has the low-order C1 bits zero. */
7694 mask = (GET_MODE_MASK (mode)
7695 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
7697 varop = simplify_and_const_int (NULL_RTX, result_mode,
7698 XEXP (varop, 0), mask);
7699 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
7701 count = first_count;
7706 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
7707 than C1 high-order bits equal to the sign bit, we can convert
7708 this to either an ASHIFT or a ASHIFTRT depending on the
7711 We cannot do this if VAROP's mode is not SHIFT_MODE. */
7713 if (code == ASHIFTRT && first_code == ASHIFT
7714 && GET_MODE (varop) == shift_mode
7715 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
7718 count -= first_count;
7720 count = - count, code = ASHIFT;
7721 varop = XEXP (varop, 0);
7725 /* There are some cases we can't do. If CODE is ASHIFTRT,
7726 we can only do this if FIRST_CODE is also ASHIFTRT.
7728 We can't do the case when CODE is ROTATE and FIRST_CODE is
7731 If the mode of this shift is not the mode of the outer shift,
7732 we can't do this if either shift is ASHIFTRT or ROTATE.
7734 Finally, we can't do any of these if the mode is too wide
7735 unless the codes are the same.
7737 Handle the case where the shift codes are the same
7740 if (code == first_code)
7742 if (GET_MODE (varop) != result_mode
7743 && (code == ASHIFTRT || code == ROTATE))
7746 count += first_count;
7747 varop = XEXP (varop, 0);
7751 if (code == ASHIFTRT
7752 || (code == ROTATE && first_code == ASHIFTRT)
7753 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
7754 || (GET_MODE (varop) != result_mode
7755 && (first_code == ASHIFTRT || first_code == ROTATE
7756 || code == ROTATE)))
7759 /* To compute the mask to apply after the shift, shift the
7760 nonzero bits of the inner shift the same way the
7761 outer shift will. */
7763 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
7766 = simplify_binary_operation (code, result_mode, mask_rtx,
7769 /* Give up if we can't compute an outer operation to use. */
7771 || GET_CODE (mask_rtx) != CONST_INT
7772 || ! merge_outer_ops (&outer_op, &outer_const, AND,
7774 result_mode, &complement_p))
7777 /* If the shifts are in the same direction, we add the
7778 counts. Otherwise, we subtract them. */
7779 if ((code == ASHIFTRT || code == LSHIFTRT)
7780 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
7781 count += first_count;
7783 count -= first_count;
7785 /* If COUNT is positive, the new shift is usually CODE,
7786 except for the two exceptions below, in which case it is
7787 FIRST_CODE. If the count is negative, FIRST_CODE should
7790 && ((first_code == ROTATE && code == ASHIFT)
7791 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7794 code = first_code, count = - count;
7796 varop = XEXP (varop, 0);
7800 /* If we have (A << B << C) for any shift, we can convert this to
7801 (A << C << B). This wins if A is a constant. Only try this if
7802 B is not a constant. */
7804 else if (GET_CODE (varop) == code
7805 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7807 = simplify_binary_operation (code, mode,
7811 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7818 /* Make this fit the case below. */
7819 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7820 GEN_INT (GET_MODE_MASK (mode)));
7826 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7827 with C the size of VAROP - 1 and the shift is logical if
7828 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7829 we have an (le X 0) operation. If we have an arithmetic shift
7830 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7831 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7833 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7834 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7835 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7836 && (code == LSHIFTRT || code == ASHIFTRT)
7837 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7838 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7841 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7844 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7845 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7850 /* If we have (shift (logical)), move the logical to the outside
7851 to allow it to possibly combine with another logical and the
7852 shift to combine with another shift. This also canonicalizes to
7853 what a ZERO_EXTRACT looks like. Also, some machines have
7854 (and (shift)) insns. */
7856 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7857 && (new = simplify_binary_operation (code, result_mode,
7859 GEN_INT (count))) != 0
7860 && GET_CODE(new) == CONST_INT
7861 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7862 INTVAL (new), result_mode, &complement_p))
7864 varop = XEXP (varop, 0);
7868 /* If we can't do that, try to simplify the shift in each arm of the
7869 logical expression, make a new logical expression, and apply
7870 the inverse distributive law. */
7872 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
7873 XEXP (varop, 0), count);
7874 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
7875 XEXP (varop, 1), count);
7877 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
7878 varop = apply_distributive_law (varop);
7885 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7886 says that the sign bit can be tested, FOO has mode MODE, C is
7887 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
7888 that may be nonzero. */
7889 if (code == LSHIFTRT
7890 && XEXP (varop, 1) == const0_rtx
7891 && GET_MODE (XEXP (varop, 0)) == result_mode
7892 && count == GET_MODE_BITSIZE (result_mode) - 1
7893 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7894 && ((STORE_FLAG_VALUE
7895 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7896 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7897 && merge_outer_ops (&outer_op, &outer_const, XOR,
7898 (HOST_WIDE_INT) 1, result_mode,
7901 varop = XEXP (varop, 0);
7908 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7909 than the number of bits in the mode is equivalent to A. */
7910 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7911 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
7913 varop = XEXP (varop, 0);
7918 /* NEG commutes with ASHIFT since it is multiplication. Move the
7919 NEG outside to allow shifts to combine. */
7921 && merge_outer_ops (&outer_op, &outer_const, NEG,
7922 (HOST_WIDE_INT) 0, result_mode,
7925 varop = XEXP (varop, 0);
7931 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7932 is one less than the number of bits in the mode is
7933 equivalent to (xor A 1). */
7934 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7935 && XEXP (varop, 1) == constm1_rtx
7936 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7937 && merge_outer_ops (&outer_op, &outer_const, XOR,
7938 (HOST_WIDE_INT) 1, result_mode,
7942 varop = XEXP (varop, 0);
7946 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7947 that might be nonzero in BAR are those being shifted out and those
7948 bits are known zero in FOO, we can replace the PLUS with FOO.
7949 Similarly in the other operand order. This code occurs when
7950 we are computing the size of a variable-size array. */
7952 if ((code == ASHIFTRT || code == LSHIFTRT)
7953 && count < HOST_BITS_PER_WIDE_INT
7954 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
7955 && (nonzero_bits (XEXP (varop, 1), result_mode)
7956 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
7958 varop = XEXP (varop, 0);
7961 else if ((code == ASHIFTRT || code == LSHIFTRT)
7962 && count < HOST_BITS_PER_WIDE_INT
7963 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7964 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7966 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7967 & nonzero_bits (XEXP (varop, 1),
7970 varop = XEXP (varop, 1);
7974 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7976 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7977 && (new = simplify_binary_operation (ASHIFT, result_mode,
7979 GEN_INT (count))) != 0
7980 && GET_CODE(new) == CONST_INT
7981 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7982 INTVAL (new), result_mode, &complement_p))
7984 varop = XEXP (varop, 0);
7990 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7991 with C the size of VAROP - 1 and the shift is logical if
7992 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7993 we have a (gt X 0) operation. If the shift is arithmetic with
7994 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7995 we have a (neg (gt X 0)) operation. */
7997 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7998 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7999 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8000 && (code == LSHIFTRT || code == ASHIFTRT)
8001 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8002 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8003 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8006 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8009 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8010 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8020 /* We need to determine what mode to do the shift in. If the shift is
8021 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
8022 done in. Otherwise, we can do it in MODE, the widest mode encountered.
8023 The code we care about is that of the shift that will actually be done,
8024 not the shift that was originally requested. */
8025 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
8027 /* We have now finished analyzing the shift. The result should be
8028 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8029 OUTER_OP is non-NIL, it is an operation that needs to be applied
8030 to the result of the shift. OUTER_CONST is the relevant constant,
8031 but we must turn off all bits turned off in the shift.
8033 If we were passed a value for X, see if we can use any pieces of
8034 it. If not, make new rtx. */
8036 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8037 && GET_CODE (XEXP (x, 1)) == CONST_INT
8038 && INTVAL (XEXP (x, 1)) == count)
8039 const_rtx = XEXP (x, 1);
8041 const_rtx = GEN_INT (count);
8043 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8044 && GET_MODE (XEXP (x, 0)) == shift_mode
8045 && SUBREG_REG (XEXP (x, 0)) == varop)
8046 varop = XEXP (x, 0);
8047 else if (GET_MODE (varop) != shift_mode)
8048 varop = gen_lowpart_for_combine (shift_mode, varop);
8050 /* If we can't make the SUBREG, try to return what we were given. */
8051 if (GET_CODE (varop) == CLOBBER)
8052 return x ? x : varop;
8054 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8059 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8060 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8062 SUBST (XEXP (x, 0), varop);
8063 SUBST (XEXP (x, 1), const_rtx);
8066 /* If we have an outer operation and we just made a shift, it is
8067 possible that we could have simplified the shift were it not
8068 for the outer operation. So try to do the simplification
8071 if (outer_op != NIL && GET_CODE (x) == code
8072 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8073 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8074 INTVAL (XEXP (x, 1)));
8076 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8077 turn off all the bits that the shift would have turned off. */
8078 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8079 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8080 GET_MODE_MASK (result_mode) >> orig_count);
8082 /* Do the remainder of the processing in RESULT_MODE. */
8083 x = gen_lowpart_for_combine (result_mode, x);
8085 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8088 x = gen_unary (NOT, result_mode, x);
8090 if (outer_op != NIL)
8092 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8093 outer_const &= GET_MODE_MASK (result_mode);
8095 if (outer_op == AND)
8096 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8097 else if (outer_op == SET)
8098 /* This means that we have determined that the result is
8099 equivalent to a constant. This should be rare. */
8100 x = GEN_INT (outer_const);
8101 else if (GET_RTX_CLASS (outer_op) == '1')
8102 x = gen_unary (outer_op, result_mode, x);
8104 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8110 /* Like recog, but we receive the address of a pointer to a new pattern.
8111 We try to match the rtx that the pointer points to.
8112 If that fails, we may try to modify or replace the pattern,
8113 storing the replacement into the same pointer object.
8115 Modifications include deletion or addition of CLOBBERs.
8117 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8118 the CLOBBERs are placed.
8120 The value is the final insn code from the pattern ultimately matched,
8124 recog_for_combine (pnewpat, insn, pnotes)
8129 register rtx pat = *pnewpat;
8130 int insn_code_number;
8131 int num_clobbers_to_add = 0;
8135 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8136 we use to indicate that something didn't match. If we find such a
8137 thing, force rejection. */
8138 if (GET_CODE (pat) == PARALLEL)
8139 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8140 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8141 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8144 /* Is the result of combination a valid instruction? */
8145 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8147 /* If it isn't, there is the possibility that we previously had an insn
8148 that clobbered some register as a side effect, but the combined
8149 insn doesn't need to do that. So try once more without the clobbers
8150 unless this represents an ASM insn. */
8152 if (insn_code_number < 0 && ! check_asm_operands (pat)
8153 && GET_CODE (pat) == PARALLEL)
8157 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8158 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8161 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8165 SUBST_INT (XVECLEN (pat, 0), pos);
8168 pat = XVECEXP (pat, 0, 0);
8170 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8173 /* If we had any clobbers to add, make a new pattern than contains
8174 them. Then check to make sure that all of them are dead. */
8175 if (num_clobbers_to_add)
8177 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8178 gen_rtvec (GET_CODE (pat) == PARALLEL
8179 ? XVECLEN (pat, 0) + num_clobbers_to_add
8180 : num_clobbers_to_add + 1));
8182 if (GET_CODE (pat) == PARALLEL)
8183 for (i = 0; i < XVECLEN (pat, 0); i++)
8184 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8186 XVECEXP (newpat, 0, 0) = pat;
8188 add_clobbers (newpat, insn_code_number);
8190 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8191 i < XVECLEN (newpat, 0); i++)
8193 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8194 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8196 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8197 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8205 return insn_code_number;
8208 /* Like gen_lowpart but for use by combine. In combine it is not possible
8209 to create any new pseudoregs. However, it is safe to create
8210 invalid memory addresses, because combine will try to recognize
8211 them and all they will do is make the combine attempt fail.
8213 If for some reason this cannot do its job, an rtx
8214 (clobber (const_int 0)) is returned.
8215 An insn containing that will not be recognized. */
8220 gen_lowpart_for_combine (mode, x)
8221 enum machine_mode mode;
8226 if (GET_MODE (x) == mode)
8229 /* We can only support MODE being wider than a word if X is a
8230 constant integer or has a mode the same size. */
8232 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8233 && ! ((GET_MODE (x) == VOIDmode
8234 && (GET_CODE (x) == CONST_INT
8235 || GET_CODE (x) == CONST_DOUBLE))
8236 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8237 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8239 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8240 won't know what to do. So we will strip off the SUBREG here and
8241 process normally. */
8242 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8245 if (GET_MODE (x) == mode)
8249 result = gen_lowpart_common (mode, x);
8253 if (GET_CODE (x) == MEM)
8255 register int offset = 0;
8258 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8260 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8261 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8263 /* If we want to refer to something bigger than the original memref,
8264 generate a perverse subreg instead. That will force a reload
8265 of the original memref X. */
8266 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8267 return gen_rtx (SUBREG, mode, x, 0);
8269 #if WORDS_BIG_ENDIAN
8270 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8271 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8273 #if BYTES_BIG_ENDIAN
8274 /* Adjust the address so that the address-after-the-data
8276 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8277 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8279 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8280 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8281 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8282 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8286 /* If X is a comparison operator, rewrite it in a new mode. This
8287 probably won't match, but may allow further simplifications. */
8288 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8289 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8291 /* If we couldn't simplify X any other way, just enclose it in a
8292 SUBREG. Normally, this SUBREG won't match, but some patterns may
8293 include an explicit SUBREG or we may simplify it further in combine. */
8298 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8299 word = ((GET_MODE_SIZE (GET_MODE (x))
8300 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8302 return gen_rtx (SUBREG, mode, x, word);
8306 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8307 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8309 If the identical expression was previously in the insn (in the undobuf),
8310 it will be returned. Only if it is not found will a new expression
8315 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8319 enum machine_mode mode;
8331 code = va_arg (p, enum rtx_code);
8332 mode = va_arg (p, enum machine_mode);
8335 n_args = GET_RTX_LENGTH (code);
8336 fmt = GET_RTX_FORMAT (code);
8338 if (n_args == 0 || n_args > 3)
8341 /* Get each arg and verify that it is supposed to be an expression. */
8342 for (j = 0; j < n_args; j++)
8347 args[j] = va_arg (p, rtx);
8350 /* See if this is in undobuf. Be sure we don't use objects that came
8351 from another insn; this could produce circular rtl structures. */
8353 for (i = previous_num_undos; i < undobuf.num_undo; i++)
8354 if (!undobuf.undo[i].is_int
8355 && GET_CODE (undobuf.undo[i].old_contents.r) == code
8356 && GET_MODE (undobuf.undo[i].old_contents.r) == mode)
8358 for (j = 0; j < n_args; j++)
8359 if (XEXP (undobuf.undo[i].old_contents.r, j) != args[j])
8363 return undobuf.undo[i].old_contents.r;
8366 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8367 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8368 rt = rtx_alloc (code);
8369 PUT_MODE (rt, mode);
8370 XEXP (rt, 0) = args[0];
8373 XEXP (rt, 1) = args[1];
8375 XEXP (rt, 2) = args[2];
8380 /* These routines make binary and unary operations by first seeing if they
8381 fold; if not, a new expression is allocated. */
8384 gen_binary (code, mode, op0, op1)
8386 enum machine_mode mode;
8392 if (GET_RTX_CLASS (code) == 'c'
8393 && (GET_CODE (op0) == CONST_INT
8394 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8395 tem = op0, op0 = op1, op1 = tem;
8397 if (GET_RTX_CLASS (code) == '<')
8399 enum machine_mode op_mode = GET_MODE (op0);
8401 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8402 just (REL_OP X Y). */
8403 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
8405 op1 = XEXP (op0, 1);
8406 op0 = XEXP (op0, 0);
8407 op_mode = GET_MODE (op0);
8410 if (op_mode == VOIDmode)
8411 op_mode = GET_MODE (op1);
8412 result = simplify_relational_operation (code, op_mode, op0, op1);
8415 result = simplify_binary_operation (code, mode, op0, op1);
8420 /* Put complex operands first and constants second. */
8421 if (GET_RTX_CLASS (code) == 'c'
8422 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8423 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8424 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8425 || (GET_CODE (op0) == SUBREG
8426 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8427 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8428 return gen_rtx_combine (code, mode, op1, op0);
8430 return gen_rtx_combine (code, mode, op0, op1);
8434 gen_unary (code, mode, op0)
8436 enum machine_mode mode;
8439 rtx result = simplify_unary_operation (code, mode, op0, mode);
8444 return gen_rtx_combine (code, mode, op0);
8447 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8448 comparison code that will be tested.
8450 The result is a possibly different comparison code to use. *POP0 and
8451 *POP1 may be updated.
8453 It is possible that we might detect that a comparison is either always
8454 true or always false. However, we do not perform general constant
8455 folding in combine, so this knowledge isn't useful. Such tautologies
8456 should have been detected earlier. Hence we ignore all such cases. */
8458 static enum rtx_code
8459 simplify_comparison (code, pop0, pop1)
8468 enum machine_mode mode, tmode;
8470 /* Try a few ways of applying the same transformation to both operands. */
8473 #ifndef WORD_REGISTER_OPERATIONS
8474 /* The test below this one won't handle SIGN_EXTENDs on these machines,
8475 so check specially. */
8476 if (code != GTU && code != GEU && code != LTU && code != LEU
8477 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
8478 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8479 && GET_CODE (XEXP (op1, 0)) == ASHIFT
8480 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
8481 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
8482 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
8483 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
8484 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8485 && GET_CODE (XEXP (op1, 1)) == CONST_INT
8486 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8487 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
8488 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
8489 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
8490 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
8491 && (INTVAL (XEXP (op0, 1))
8492 == (GET_MODE_BITSIZE (GET_MODE (op0))
8494 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
8496 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
8497 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
8501 /* If both operands are the same constant shift, see if we can ignore the
8502 shift. We can if the shift is a rotate or if the bits shifted out of
8503 this shift are known to be zero for both inputs and if the type of
8504 comparison is compatible with the shift. */
8505 if (GET_CODE (op0) == GET_CODE (op1)
8506 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8507 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
8508 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
8509 && (code != GT && code != LT && code != GE && code != LE))
8510 || (GET_CODE (op0) == ASHIFTRT
8511 && (code != GTU && code != LTU
8512 && code != GEU && code != GEU)))
8513 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8514 && INTVAL (XEXP (op0, 1)) >= 0
8515 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8516 && XEXP (op0, 1) == XEXP (op1, 1))
8518 enum machine_mode mode = GET_MODE (op0);
8519 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8520 int shift_count = INTVAL (XEXP (op0, 1));
8522 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
8523 mask &= (mask >> shift_count) << shift_count;
8524 else if (GET_CODE (op0) == ASHIFT)
8525 mask = (mask & (mask << shift_count)) >> shift_count;
8527 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
8528 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
8529 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
8534 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8535 SUBREGs are of the same mode, and, in both cases, the AND would
8536 be redundant if the comparison was done in the narrower mode,
8537 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8538 and the operand's possibly nonzero bits are 0xffffff01; in that case
8539 if we only care about QImode, we don't need the AND). This case
8540 occurs if the output mode of an scc insn is not SImode and
8541 STORE_FLAG_VALUE == 1 (e.g., the 386). */
8543 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
8544 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8545 && GET_CODE (XEXP (op1, 1)) == CONST_INT
8546 && GET_CODE (XEXP (op0, 0)) == SUBREG
8547 && GET_CODE (XEXP (op1, 0)) == SUBREG
8548 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
8549 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
8550 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
8551 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8552 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8553 <= HOST_BITS_PER_WIDE_INT)
8554 && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)),
8555 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8556 & ~ INTVAL (XEXP (op0, 1))) == 0
8557 && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)),
8558 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8559 & ~ INTVAL (XEXP (op1, 1))) == 0)
8561 op0 = SUBREG_REG (XEXP (op0, 0));
8562 op1 = SUBREG_REG (XEXP (op1, 0));
8564 /* the resulting comparison is always unsigned since we masked off
8565 the original sign bit. */
8566 code = unsigned_condition (code);
8569 /* If both operands are NOT, we can strip off the outer operation
8570 and adjust the comparison code for swapped operands; similarly for
8571 NEG, except that this must be an equality comparison. */
8572 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
8573 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
8574 && (code == EQ || code == NE)))
8575 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
8581 /* If the first operand is a constant, swap the operands and adjust the
8582 comparison code appropriately. */
8583 if (CONSTANT_P (op0))
8585 tem = op0, op0 = op1, op1 = tem;
8586 code = swap_condition (code);
8589 /* We now enter a loop during which we will try to simplify the comparison.
8590 For the most part, we only are concerned with comparisons with zero,
8591 but some things may really be comparisons with zero but not start
8592 out looking that way. */
8594 while (GET_CODE (op1) == CONST_INT)
8596 enum machine_mode mode = GET_MODE (op0);
8597 int mode_width = GET_MODE_BITSIZE (mode);
8598 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8599 int equality_comparison_p;
8600 int sign_bit_comparison_p;
8601 int unsigned_comparison_p;
8602 HOST_WIDE_INT const_op;
8604 /* We only want to handle integral modes. This catches VOIDmode,
8605 CCmode, and the floating-point modes. An exception is that we
8606 can handle VOIDmode if OP0 is a COMPARE or a comparison
8609 if (GET_MODE_CLASS (mode) != MODE_INT
8610 && ! (mode == VOIDmode
8611 && (GET_CODE (op0) == COMPARE
8612 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
8615 /* Get the constant we are comparing against and turn off all bits
8616 not on in our mode. */
8617 const_op = INTVAL (op1);
8618 if (mode_width <= HOST_BITS_PER_WIDE_INT)
8621 /* If we are comparing against a constant power of two and the value
8622 being compared can only have that single bit nonzero (e.g., it was
8623 `and'ed with that bit), we can replace this with a comparison
8626 && (code == EQ || code == NE || code == GE || code == GEU
8627 || code == LT || code == LTU)
8628 && mode_width <= HOST_BITS_PER_WIDE_INT
8629 && exact_log2 (const_op) >= 0
8630 && nonzero_bits (op0, mode) == const_op)
8632 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
8633 op1 = const0_rtx, const_op = 0;
8636 /* Similarly, if we are comparing a value known to be either -1 or
8637 0 with -1, change it to the opposite comparison against zero. */
8640 && (code == EQ || code == NE || code == GT || code == LE
8641 || code == GEU || code == LTU)
8642 && num_sign_bit_copies (op0, mode) == mode_width)
8644 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
8645 op1 = const0_rtx, const_op = 0;
8648 /* Do some canonicalizations based on the comparison code. We prefer
8649 comparisons against zero and then prefer equality comparisons.
8650 If we can reduce the size of a constant, we will do that too. */
8655 /* < C is equivalent to <= (C - 1) */
8659 op1 = GEN_INT (const_op);
8661 /* ... fall through to LE case below. */
8667 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
8671 op1 = GEN_INT (const_op);
8675 /* If we are doing a <= 0 comparison on a value known to have
8676 a zero sign bit, we can replace this with == 0. */
8677 else if (const_op == 0
8678 && mode_width <= HOST_BITS_PER_WIDE_INT
8679 && (nonzero_bits (op0, mode)
8680 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8685 /* >= C is equivalent to > (C - 1). */
8689 op1 = GEN_INT (const_op);
8691 /* ... fall through to GT below. */
8697 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
8701 op1 = GEN_INT (const_op);
8705 /* If we are doing a > 0 comparison on a value known to have
8706 a zero sign bit, we can replace this with != 0. */
8707 else if (const_op == 0
8708 && mode_width <= HOST_BITS_PER_WIDE_INT
8709 && (nonzero_bits (op0, mode)
8710 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8715 /* < C is equivalent to <= (C - 1). */
8719 op1 = GEN_INT (const_op);
8721 /* ... fall through ... */
8724 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
8725 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8727 const_op = 0, op1 = const0_rtx;
8735 /* unsigned <= 0 is equivalent to == 0 */
8739 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
8740 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8742 const_op = 0, op1 = const0_rtx;
8748 /* >= C is equivalent to < (C - 1). */
8752 op1 = GEN_INT (const_op);
8754 /* ... fall through ... */
8757 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
8758 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8760 const_op = 0, op1 = const0_rtx;
8767 /* unsigned > 0 is equivalent to != 0 */
8771 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
8772 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8774 const_op = 0, op1 = const0_rtx;
8780 /* Compute some predicates to simplify code below. */
8782 equality_comparison_p = (code == EQ || code == NE);
8783 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
8784 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
8787 /* If this is a sign bit comparison and we can do arithmetic in
8788 MODE, say that we will only be needing the sign bit of OP0. */
8789 if (sign_bit_comparison_p
8790 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8791 op0 = force_to_mode (op0, mode,
8793 << (GET_MODE_BITSIZE (mode) - 1)),
8796 /* Now try cases based on the opcode of OP0. If none of the cases
8797 does a "continue", we exit this loop immediately after the
8800 switch (GET_CODE (op0))
8803 /* If we are extracting a single bit from a variable position in
8804 a constant that has only a single bit set and are comparing it
8805 with zero, we can convert this into an equality comparison
8806 between the position and the location of the single bit. We can't
8807 do this if bit endian and we don't have an extzv since we then
8808 can't know what mode to use for the endianness adjustment. */
8810 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
8811 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
8812 && XEXP (op0, 1) == const1_rtx
8813 && equality_comparison_p && const_op == 0
8814 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
8817 i = (GET_MODE_BITSIZE
8818 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
8821 op0 = XEXP (op0, 2);
8825 /* Result is nonzero iff shift count is equal to I. */
8826 code = reverse_condition (code);
8831 /* ... fall through ... */
8834 tem = expand_compound_operation (op0);
8843 /* If testing for equality, we can take the NOT of the constant. */
8844 if (equality_comparison_p
8845 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
8847 op0 = XEXP (op0, 0);
8852 /* If just looking at the sign bit, reverse the sense of the
8854 if (sign_bit_comparison_p)
8856 op0 = XEXP (op0, 0);
8857 code = (code == GE ? LT : GE);
8863 /* If testing for equality, we can take the NEG of the constant. */
8864 if (equality_comparison_p
8865 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
8867 op0 = XEXP (op0, 0);
8872 /* The remaining cases only apply to comparisons with zero. */
8876 /* When X is ABS or is known positive,
8877 (neg X) is < 0 if and only if X != 0. */
8879 if (sign_bit_comparison_p
8880 && (GET_CODE (XEXP (op0, 0)) == ABS
8881 || (mode_width <= HOST_BITS_PER_WIDE_INT
8882 && (nonzero_bits (XEXP (op0, 0), mode)
8883 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8885 op0 = XEXP (op0, 0);
8886 code = (code == LT ? NE : EQ);
8890 /* If we have NEG of something whose two high-order bits are the
8891 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8892 if (num_sign_bit_copies (op0, mode) >= 2)
8894 op0 = XEXP (op0, 0);
8895 code = swap_condition (code);
8901 /* If we are testing equality and our count is a constant, we
8902 can perform the inverse operation on our RHS. */
8903 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8904 && (tem = simplify_binary_operation (ROTATERT, mode,
8905 op1, XEXP (op0, 1))) != 0)
8907 op0 = XEXP (op0, 0);
8912 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8913 a particular bit. Convert it to an AND of a constant of that
8914 bit. This will be converted into a ZERO_EXTRACT. */
8915 if (const_op == 0 && sign_bit_comparison_p
8916 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8917 && mode_width <= HOST_BITS_PER_WIDE_INT)
8919 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8922 - INTVAL (XEXP (op0, 1)))));
8923 code = (code == LT ? NE : EQ);
8927 /* ... fall through ... */
8930 /* ABS is ignorable inside an equality comparison with zero. */
8931 if (const_op == 0 && equality_comparison_p)
8933 op0 = XEXP (op0, 0);
8940 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8941 to (compare FOO CONST) if CONST fits in FOO's mode and we
8942 are either testing inequality or have an unsigned comparison
8943 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8944 if (! unsigned_comparison_p
8945 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8946 <= HOST_BITS_PER_WIDE_INT)
8947 && ((unsigned HOST_WIDE_INT) const_op
8948 < (((HOST_WIDE_INT) 1
8949 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8951 op0 = XEXP (op0, 0);
8957 /* Check for the case where we are comparing A - C1 with C2,
8958 both constants are smaller than 1/2 the maxium positive
8959 value in MODE, and the comparison is equality or unsigned.
8960 In that case, if A is either zero-extended to MODE or has
8961 sufficient sign bits so that the high-order bit in MODE
8962 is a copy of the sign in the inner mode, we can prove that it is
8963 safe to do the operation in the wider mode. This simplifies
8964 many range checks. */
8966 if (mode_width <= HOST_BITS_PER_WIDE_INT
8967 && subreg_lowpart_p (op0)
8968 && GET_CODE (SUBREG_REG (op0)) == PLUS
8969 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8970 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8971 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8972 < GET_MODE_MASK (mode) / 2)
8973 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
8974 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
8975 GET_MODE (SUBREG_REG (op0)))
8976 & ~ GET_MODE_MASK (mode))
8977 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8978 GET_MODE (SUBREG_REG (op0)))
8979 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8980 - GET_MODE_BITSIZE (mode)))))
8982 op0 = SUBREG_REG (op0);
8986 /* If the inner mode is narrower and we are extracting the low part,
8987 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8988 if (subreg_lowpart_p (op0)
8989 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8990 /* Fall through */ ;
8994 /* ... fall through ... */
8997 if ((unsigned_comparison_p || equality_comparison_p)
8998 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8999 <= HOST_BITS_PER_WIDE_INT)
9000 && ((unsigned HOST_WIDE_INT) const_op
9001 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9003 op0 = XEXP (op0, 0);
9009 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9010 this for equality comparisons due to pathological cases involving
9012 if (equality_comparison_p
9013 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9014 op1, XEXP (op0, 1))))
9016 op0 = XEXP (op0, 0);
9021 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9022 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9023 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9025 op0 = XEXP (XEXP (op0, 0), 0);
9026 code = (code == LT ? EQ : NE);
9032 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9033 (eq B (minus A C)), whichever simplifies. We can only do
9034 this for equality comparisons due to pathological cases involving
9036 if (equality_comparison_p
9037 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9038 XEXP (op0, 1), op1)))
9040 op0 = XEXP (op0, 0);
9045 if (equality_comparison_p
9046 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9047 XEXP (op0, 0), op1)))
9049 op0 = XEXP (op0, 1);
9054 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9055 of bits in X minus 1, is one iff X > 0. */
9056 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9057 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9058 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9059 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9061 op0 = XEXP (op0, 1);
9062 code = (code == GE ? LE : GT);
9068 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9069 if C is zero or B is a constant. */
9070 if (equality_comparison_p
9071 && 0 != (tem = simplify_binary_operation (XOR, mode,
9072 XEXP (op0, 1), op1)))
9074 op0 = XEXP (op0, 0);
9081 case LT: case LTU: case LE: case LEU:
9082 case GT: case GTU: case GE: case GEU:
9083 /* We can't do anything if OP0 is a condition code value, rather
9084 than an actual data value. */
9087 || XEXP (op0, 0) == cc0_rtx
9089 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9092 /* Get the two operands being compared. */
9093 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9094 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9096 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9098 /* Check for the cases where we simply want the result of the
9099 earlier test or the opposite of that result. */
9101 || (code == EQ && reversible_comparison_p (op0))
9102 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9103 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9104 && (STORE_FLAG_VALUE
9105 & (((HOST_WIDE_INT) 1
9106 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9108 || (code == GE && reversible_comparison_p (op0)))))
9110 code = (code == LT || code == NE
9111 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9112 op0 = tem, op1 = tem1;
9118 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9120 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9121 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9122 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9124 op0 = XEXP (op0, 1);
9125 code = (code == GE ? GT : LE);
9131 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9132 will be converted to a ZERO_EXTRACT later. */
9133 if (const_op == 0 && equality_comparison_p
9134 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9135 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9137 op0 = simplify_and_const_int
9138 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9140 XEXP (XEXP (op0, 0), 1)),
9145 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9146 zero and X is a comparison and C1 and C2 describe only bits set
9147 in STORE_FLAG_VALUE, we can compare with X. */
9148 if (const_op == 0 && equality_comparison_p
9149 && mode_width <= HOST_BITS_PER_WIDE_INT
9150 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9151 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9152 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9153 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9154 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9156 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9157 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9158 if ((~ STORE_FLAG_VALUE & mask) == 0
9159 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9160 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9161 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9163 op0 = XEXP (XEXP (op0, 0), 0);
9168 /* If we are doing an equality comparison of an AND of a bit equal
9169 to the sign bit, replace this with a LT or GE comparison of
9170 the underlying value. */
9171 if (equality_comparison_p
9173 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9174 && mode_width <= HOST_BITS_PER_WIDE_INT
9175 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9176 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9178 op0 = XEXP (op0, 0);
9179 code = (code == EQ ? GE : LT);
9183 /* If this AND operation is really a ZERO_EXTEND from a narrower
9184 mode, the constant fits within that mode, and this is either an
9185 equality or unsigned comparison, try to do this comparison in
9186 the narrower mode. */
9187 if ((equality_comparison_p || unsigned_comparison_p)
9188 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9189 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9190 & GET_MODE_MASK (mode))
9192 && const_op >> i == 0
9193 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9195 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9201 /* If we have (compare (ashift FOO N) (const_int C)) and
9202 the high order N bits of FOO (N+1 if an inequality comparison)
9203 are known to be zero, we can do this by comparing FOO with C
9204 shifted right N bits so long as the low-order N bits of C are
9206 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9207 && INTVAL (XEXP (op0, 1)) >= 0
9208 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9209 < HOST_BITS_PER_WIDE_INT)
9211 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9212 && mode_width <= HOST_BITS_PER_WIDE_INT
9213 && (nonzero_bits (XEXP (op0, 0), mode)
9214 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9215 + ! equality_comparison_p))) == 0)
9217 const_op >>= INTVAL (XEXP (op0, 1));
9218 op1 = GEN_INT (const_op);
9219 op0 = XEXP (op0, 0);
9223 /* If we are doing a sign bit comparison, it means we are testing
9224 a particular bit. Convert it to the appropriate AND. */
9225 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9226 && mode_width <= HOST_BITS_PER_WIDE_INT)
9228 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9231 - INTVAL (XEXP (op0, 1)))));
9232 code = (code == LT ? NE : EQ);
9236 /* If this an equality comparison with zero and we are shifting
9237 the low bit to the sign bit, we can convert this to an AND of the
9239 if (const_op == 0 && equality_comparison_p
9240 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9241 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9243 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9250 /* If this is an equality comparison with zero, we can do this
9251 as a logical shift, which might be much simpler. */
9252 if (equality_comparison_p && const_op == 0
9253 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9255 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9257 INTVAL (XEXP (op0, 1)));
9261 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9262 do the comparison in a narrower mode. */
9263 if (! unsigned_comparison_p
9264 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9265 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9266 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9267 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9268 MODE_INT, 1)) != BLKmode
9269 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9270 || ((unsigned HOST_WIDE_INT) - const_op
9271 <= GET_MODE_MASK (tmode))))
9273 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9277 /* ... fall through ... */
9279 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9280 the low order N bits of FOO are known to be zero, we can do this
9281 by comparing FOO with C shifted left N bits so long as no
9283 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9284 && INTVAL (XEXP (op0, 1)) >= 0
9285 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9286 && mode_width <= HOST_BITS_PER_WIDE_INT
9287 && (nonzero_bits (XEXP (op0, 0), mode)
9288 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9290 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9293 const_op <<= INTVAL (XEXP (op0, 1));
9294 op1 = GEN_INT (const_op);
9295 op0 = XEXP (op0, 0);
9299 /* If we are using this shift to extract just the sign bit, we
9300 can replace this with an LT or GE comparison. */
9302 && (equality_comparison_p || sign_bit_comparison_p)
9303 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9304 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9306 op0 = XEXP (op0, 0);
9307 code = (code == NE || code == GT ? LT : GE);
9316 /* Now make any compound operations involved in this comparison. Then,
9317 check for an outmost SUBREG on OP0 that isn't doing anything or is
9318 paradoxical. The latter case can only occur when it is known that the
9319 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9320 We can never remove a SUBREG for a non-equality comparison because the
9321 sign bit is in a different place in the underlying object. */
9323 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9324 op1 = make_compound_operation (op1, SET);
9326 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9327 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9328 && (code == NE || code == EQ)
9329 && ((GET_MODE_SIZE (GET_MODE (op0))
9330 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9332 op0 = SUBREG_REG (op0);
9333 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9336 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9337 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9338 && (code == NE || code == EQ)
9339 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9340 <= HOST_BITS_PER_WIDE_INT)
9341 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9342 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9343 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9345 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9346 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9347 op0 = SUBREG_REG (op0), op1 = tem;
9349 /* We now do the opposite procedure: Some machines don't have compare
9350 insns in all modes. If OP0's mode is an integer mode smaller than a
9351 word and we can't do a compare in that mode, see if there is a larger
9352 mode for which we can do the compare. There are a number of cases in
9353 which we can use the wider mode. */
9355 mode = GET_MODE (op0);
9356 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9357 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
9358 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
9359 for (tmode = GET_MODE_WIDER_MODE (mode);
9361 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
9362 tmode = GET_MODE_WIDER_MODE (tmode))
9363 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
9365 /* If the only nonzero bits in OP0 and OP1 are those in the
9366 narrower mode and this is an equality or unsigned comparison,
9367 we can use the wider mode. Similarly for sign-extended
9368 values and equality or signed comparisons. */
9369 if (((code == EQ || code == NE
9370 || code == GEU || code == GTU || code == LEU || code == LTU)
9371 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
9372 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
9373 || ((code == EQ || code == NE
9374 || code == GE || code == GT || code == LE || code == LT)
9375 && (num_sign_bit_copies (op0, tmode)
9376 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
9377 && (num_sign_bit_copies (op1, tmode)
9378 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
9380 op0 = gen_lowpart_for_combine (tmode, op0);
9381 op1 = gen_lowpart_for_combine (tmode, op1);
9385 /* If this is a test for negative, we can make an explicit
9386 test of the sign bit. */
9388 if (op1 == const0_rtx && (code == LT || code == GE)
9389 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9391 op0 = gen_binary (AND, tmode,
9392 gen_lowpart_for_combine (tmode, op0),
9393 GEN_INT ((HOST_WIDE_INT) 1
9394 << (GET_MODE_BITSIZE (mode) - 1)));
9395 code = (code == LT) ? NE : EQ;
9406 /* Return 1 if we know that X, a comparison operation, is not operating
9407 on a floating-point value or is EQ or NE, meaning that we can safely
9411 reversible_comparison_p (x)
9414 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
9416 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
9419 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
9422 case MODE_PARTIAL_INT:
9423 case MODE_COMPLEX_INT:
9427 /* If the mode of the condition codes tells us that this is safe,
9428 we need look no further. */
9429 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
9432 /* Otherwise try and find where the condition codes were last set and
9434 x = get_last_value (XEXP (x, 0));
9435 return (x && GET_CODE (x) == COMPARE
9436 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
9442 /* Utility function for following routine. Called when X is part of a value
9443 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9444 for each register mentioned. Similar to mention_regs in cse.c */
9447 update_table_tick (x)
9450 register enum rtx_code code = GET_CODE (x);
9451 register char *fmt = GET_RTX_FORMAT (code);
9456 int regno = REGNO (x);
9457 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9458 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9460 for (i = regno; i < endregno; i++)
9461 reg_last_set_table_tick[i] = label_tick;
9466 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9467 /* Note that we can't have an "E" in values stored; see
9468 get_last_value_validate. */
9470 update_table_tick (XEXP (x, i));
9473 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
9474 are saying that the register is clobbered and we no longer know its
9475 value. If INSN is zero, don't update reg_last_set; this is only permitted
9476 with VALUE also zero and is used to invalidate the register. */
9479 record_value_for_reg (reg, insn, value)
9484 int regno = REGNO (reg);
9485 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9486 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
9489 /* If VALUE contains REG and we have a previous value for REG, substitute
9490 the previous value. */
9491 if (value && insn && reg_overlap_mentioned_p (reg, value))
9495 /* Set things up so get_last_value is allowed to see anything set up to
9497 subst_low_cuid = INSN_CUID (insn);
9498 tem = get_last_value (reg);
9501 value = replace_rtx (copy_rtx (value), reg, tem);
9504 /* For each register modified, show we don't know its value, that
9505 we don't know about its bitwise content, that its value has been
9506 updated, and that we don't know the location of the death of the
9508 for (i = regno; i < endregno; i ++)
9511 reg_last_set[i] = insn;
9512 reg_last_set_value[i] = 0;
9513 reg_last_set_mode[i] = 0;
9514 reg_last_set_nonzero_bits[i] = 0;
9515 reg_last_set_sign_bit_copies[i] = 0;
9516 reg_last_death[i] = 0;
9519 /* Mark registers that are being referenced in this value. */
9521 update_table_tick (value);
9523 /* Now update the status of each register being set.
9524 If someone is using this register in this block, set this register
9525 to invalid since we will get confused between the two lives in this
9526 basic block. This makes using this register always invalid. In cse, we
9527 scan the table to invalidate all entries using this register, but this
9528 is too much work for us. */
9530 for (i = regno; i < endregno; i++)
9532 reg_last_set_label[i] = label_tick;
9533 if (value && reg_last_set_table_tick[i] == label_tick)
9534 reg_last_set_invalid[i] = 1;
9536 reg_last_set_invalid[i] = 0;
9539 /* The value being assigned might refer to X (like in "x++;"). In that
9540 case, we must replace it with (clobber (const_int 0)) to prevent
9542 if (value && ! get_last_value_validate (&value,
9543 reg_last_set_label[regno], 0))
9545 value = copy_rtx (value);
9546 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
9550 /* For the main register being modified, update the value, the mode, the
9551 nonzero bits, and the number of sign bit copies. */
9553 reg_last_set_value[regno] = value;
9557 subst_low_cuid = INSN_CUID (insn);
9558 reg_last_set_mode[regno] = GET_MODE (reg);
9559 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
9560 reg_last_set_sign_bit_copies[regno]
9561 = num_sign_bit_copies (value, GET_MODE (reg));
9565 /* Used for communication between the following two routines. */
9566 static rtx record_dead_insn;
9568 /* Called via note_stores from record_dead_and_set_regs to handle one
9569 SET or CLOBBER in an insn. */
9572 record_dead_and_set_regs_1 (dest, setter)
9575 if (GET_CODE (dest) == REG)
9577 /* If we are setting the whole register, we know its value. Otherwise
9578 show that we don't know the value. We can handle SUBREG in
9580 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
9581 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
9582 else if (GET_CODE (setter) == SET
9583 && GET_CODE (SET_DEST (setter)) == SUBREG
9584 && SUBREG_REG (SET_DEST (setter)) == dest
9585 && subreg_lowpart_p (SET_DEST (setter)))
9586 record_value_for_reg (dest, record_dead_insn,
9587 gen_lowpart_for_combine (GET_MODE (dest),
9590 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
9592 else if (GET_CODE (dest) == MEM
9593 /* Ignore pushes, they clobber nothing. */
9594 && ! push_operand (dest, GET_MODE (dest)))
9595 mem_last_set = INSN_CUID (record_dead_insn);
9598 /* Update the records of when each REG was most recently set or killed
9599 for the things done by INSN. This is the last thing done in processing
9600 INSN in the combiner loop.
9602 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
9603 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
9604 and also the similar information mem_last_set (which insn most recently
9605 modified memory) and last_call_cuid (which insn was the most recent
9606 subroutine call). */
9609 record_dead_and_set_regs (insn)
9615 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
9617 if (REG_NOTE_KIND (link) == REG_DEAD
9618 && GET_CODE (XEXP (link, 0)) == REG)
9620 int regno = REGNO (XEXP (link, 0));
9622 = regno + (regno < FIRST_PSEUDO_REGISTER
9623 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
9626 for (i = regno; i < endregno; i++)
9627 reg_last_death[i] = insn;
9629 else if (REG_NOTE_KIND (link) == REG_INC)
9630 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
9633 if (GET_CODE (insn) == CALL_INSN)
9635 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9636 if (call_used_regs[i])
9638 reg_last_set_value[i] = 0;
9639 reg_last_set_mode[i] = 0;
9640 reg_last_set_nonzero_bits[i] = 0;
9641 reg_last_set_sign_bit_copies[i] = 0;
9642 reg_last_death[i] = 0;
9645 last_call_cuid = mem_last_set = INSN_CUID (insn);
9648 record_dead_insn = insn;
9649 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
9652 /* Utility routine for the following function. Verify that all the registers
9653 mentioned in *LOC are valid when *LOC was part of a value set when
9654 label_tick == TICK. Return 0 if some are not.
9656 If REPLACE is non-zero, replace the invalid reference with
9657 (clobber (const_int 0)) and return 1. This replacement is useful because
9658 we often can get useful information about the form of a value (e.g., if
9659 it was produced by a shift that always produces -1 or 0) even though
9660 we don't know exactly what registers it was produced from. */
9663 get_last_value_validate (loc, tick, replace)
9669 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
9670 int len = GET_RTX_LENGTH (GET_CODE (x));
9673 if (GET_CODE (x) == REG)
9675 int regno = REGNO (x);
9676 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9677 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9680 for (j = regno; j < endregno; j++)
9681 if (reg_last_set_invalid[j]
9682 /* If this is a pseudo-register that was only set once, it is
9684 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
9685 && reg_last_set_label[j] > tick))
9688 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9695 for (i = 0; i < len; i++)
9697 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
9698 /* Don't bother with these. They shouldn't occur anyway. */
9702 /* If we haven't found a reason for it to be invalid, it is valid. */
9706 /* Get the last value assigned to X, if known. Some registers
9707 in the value may be replaced with (clobber (const_int 0)) if their value
9708 is known longer known reliably. */
9717 /* If this is a non-paradoxical SUBREG, get the value of its operand and
9718 then convert it to the desired mode. If this is a paradoxical SUBREG,
9719 we cannot predict what values the "extra" bits might have. */
9720 if (GET_CODE (x) == SUBREG
9721 && subreg_lowpart_p (x)
9722 && (GET_MODE_SIZE (GET_MODE (x))
9723 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
9724 && (value = get_last_value (SUBREG_REG (x))) != 0)
9725 return gen_lowpart_for_combine (GET_MODE (x), value);
9727 if (GET_CODE (x) != REG)
9731 value = reg_last_set_value[regno];
9733 /* If we don't have a value or if it isn't for this basic block, return 0. */
9736 || (reg_n_sets[regno] != 1
9737 && reg_last_set_label[regno] != label_tick))
9740 /* If the value was set in a later insn that the ones we are processing,
9741 we can't use it even if the register was only set once, but make a quick
9742 check to see if the previous insn set it to something. This is commonly
9743 the case when the same pseudo is used by repeated insns. */
9745 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
9749 /* If there is an insn that is supposed to be immediately
9750 in front of subst_insn, use it. */
9751 if (subst_prev_insn != 0)
9752 insn = subst_prev_insn;
9754 for (insn = prev_nonnote_insn (subst_insn);
9755 insn && INSN_CUID (insn) >= subst_low_cuid;
9756 insn = prev_nonnote_insn (insn))
9760 && (set = single_set (insn)) != 0
9761 && rtx_equal_p (SET_DEST (set), x))
9763 value = SET_SRC (set);
9765 /* Make sure that VALUE doesn't reference X. Replace any
9766 expliit references with a CLOBBER. If there are any remaining
9767 references (rare), don't use the value. */
9769 if (reg_mentioned_p (x, value))
9770 value = replace_rtx (copy_rtx (value), x,
9771 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
9773 if (reg_overlap_mentioned_p (x, value))
9780 /* If the value has all its registers valid, return it. */
9781 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
9784 /* Otherwise, make a copy and replace any invalid register with
9785 (clobber (const_int 0)). If that fails for some reason, return 0. */
9787 value = copy_rtx (value);
9788 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
9794 /* Return nonzero if expression X refers to a REG or to memory
9795 that is set in an instruction more recent than FROM_CUID. */
9798 use_crosses_set_p (x, from_cuid)
9804 register enum rtx_code code = GET_CODE (x);
9808 register int regno = REGNO (x);
9809 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
9810 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9812 #ifdef PUSH_ROUNDING
9813 /* Don't allow uses of the stack pointer to be moved,
9814 because we don't know whether the move crosses a push insn. */
9815 if (regno == STACK_POINTER_REGNUM)
9818 for (;regno < endreg; regno++)
9819 if (reg_last_set[regno]
9820 && INSN_CUID (reg_last_set[regno]) > from_cuid)
9825 if (code == MEM && mem_last_set > from_cuid)
9828 fmt = GET_RTX_FORMAT (code);
9830 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9835 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9836 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
9839 else if (fmt[i] == 'e'
9840 && use_crosses_set_p (XEXP (x, i), from_cuid))
9846 /* Define three variables used for communication between the following
9849 static int reg_dead_regno, reg_dead_endregno;
9850 static int reg_dead_flag;
9852 /* Function called via note_stores from reg_dead_at_p.
9854 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
9855 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
9858 reg_dead_at_p_1 (dest, x)
9862 int regno, endregno;
9864 if (GET_CODE (dest) != REG)
9867 regno = REGNO (dest);
9868 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9869 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
9871 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
9872 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
9875 /* Return non-zero if REG is known to be dead at INSN.
9877 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
9878 referencing REG, it is dead. If we hit a SET referencing REG, it is
9879 live. Otherwise, see if it is live or dead at the start of the basic
9880 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
9881 must be assumed to be always live. */
9884 reg_dead_at_p (reg, insn)
9890 /* Set variables for reg_dead_at_p_1. */
9891 reg_dead_regno = REGNO (reg);
9892 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
9893 ? HARD_REGNO_NREGS (reg_dead_regno,
9899 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
9900 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
9902 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
9903 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
9907 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
9908 beginning of function. */
9909 for (; insn && GET_CODE (insn) != CODE_LABEL;
9910 insn = prev_nonnote_insn (insn))
9912 note_stores (PATTERN (insn), reg_dead_at_p_1);
9914 return reg_dead_flag == 1 ? 1 : 0;
9916 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
9920 /* Get the basic block number that we were in. */
9925 for (block = 0; block < n_basic_blocks; block++)
9926 if (insn == basic_block_head[block])
9929 if (block == n_basic_blocks)
9933 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
9934 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
9935 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
9941 /* Note hard registers in X that are used. This code is similar to
9942 that in flow.c, but much simpler since we don't care about pseudos. */
9945 mark_used_regs_combine (x)
9948 register RTX_CODE code = GET_CODE (x);
9964 /* CC0 must die in the insn after it is set, so we don't need to take
9965 special note of it here. */
9971 /* If we are clobbering a MEM, mark any hard registers inside the
9973 if (GET_CODE (XEXP (x, 0)) == MEM)
9974 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
9979 /* A hard reg in a wide mode may really be multiple registers.
9980 If so, mark all of them just like the first. */
9981 if (regno < FIRST_PSEUDO_REGISTER)
9983 /* None of this applies to the stack, frame or arg pointers */
9984 if (regno == STACK_POINTER_REGNUM
9985 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
9986 || regno == HARD_FRAME_POINTER_REGNUM
9988 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
9989 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
9991 || regno == FRAME_POINTER_REGNUM)
9994 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
9996 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10002 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10004 register rtx testreg = SET_DEST (x);
10006 while (GET_CODE (testreg) == SUBREG
10007 || GET_CODE (testreg) == ZERO_EXTRACT
10008 || GET_CODE (testreg) == SIGN_EXTRACT
10009 || GET_CODE (testreg) == STRICT_LOW_PART)
10010 testreg = XEXP (testreg, 0);
10012 if (GET_CODE (testreg) == MEM)
10013 mark_used_regs_combine (XEXP (testreg, 0));
10015 mark_used_regs_combine (SET_SRC (x));
10020 /* Recursively scan the operands of this expression. */
10023 register char *fmt = GET_RTX_FORMAT (code);
10025 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10028 mark_used_regs_combine (XEXP (x, i));
10029 else if (fmt[i] == 'E')
10033 for (j = 0; j < XVECLEN (x, i); j++)
10034 mark_used_regs_combine (XVECEXP (x, i, j));
10041 /* Remove register number REGNO from the dead registers list of INSN.
10043 Return the note used to record the death, if there was one. */
10046 remove_death (regno, insn)
10050 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10054 reg_n_deaths[regno]--;
10055 remove_note (insn, note);
10061 /* For each register (hardware or pseudo) used within expression X, if its
10062 death is in an instruction with cuid between FROM_CUID (inclusive) and
10063 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10064 list headed by PNOTES.
10066 This is done when X is being merged by combination into TO_INSN. These
10067 notes will then be distributed as needed. */
10070 move_deaths (x, from_cuid, to_insn, pnotes)
10076 register char *fmt;
10077 register int len, i;
10078 register enum rtx_code code = GET_CODE (x);
10082 register int regno = REGNO (x);
10083 register rtx where_dead = reg_last_death[regno];
10085 if (where_dead && INSN_CUID (where_dead) >= from_cuid
10086 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
10088 rtx note = remove_death (regno, where_dead);
10090 /* It is possible for the call above to return 0. This can occur
10091 when reg_last_death points to I2 or I1 that we combined with.
10092 In that case make a new note.
10094 We must also check for the case where X is a hard register
10095 and NOTE is a death note for a range of hard registers
10096 including X. In that case, we must put REG_DEAD notes for
10097 the remaining registers in place of NOTE. */
10099 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10100 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10101 != GET_MODE_SIZE (GET_MODE (x))))
10103 int deadregno = REGNO (XEXP (note, 0));
10105 = (deadregno + HARD_REGNO_NREGS (deadregno,
10106 GET_MODE (XEXP (note, 0))));
10107 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10110 for (i = deadregno; i < deadend; i++)
10111 if (i < regno || i >= ourend)
10112 REG_NOTES (where_dead)
10113 = gen_rtx (EXPR_LIST, REG_DEAD,
10114 gen_rtx (REG, reg_raw_mode[i], i),
10115 REG_NOTES (where_dead));
10118 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10120 XEXP (note, 1) = *pnotes;
10124 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10126 reg_n_deaths[regno]++;
10132 else if (GET_CODE (x) == SET)
10134 rtx dest = SET_DEST (x);
10136 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
10138 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10139 that accesses one word of a multi-word item, some
10140 piece of everything register in the expression is used by
10141 this insn, so remove any old death. */
10143 if (GET_CODE (dest) == ZERO_EXTRACT
10144 || GET_CODE (dest) == STRICT_LOW_PART
10145 || (GET_CODE (dest) == SUBREG
10146 && (((GET_MODE_SIZE (GET_MODE (dest))
10147 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10148 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10149 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10151 move_deaths (dest, from_cuid, to_insn, pnotes);
10155 /* If this is some other SUBREG, we know it replaces the entire
10156 value, so use that as the destination. */
10157 if (GET_CODE (dest) == SUBREG)
10158 dest = SUBREG_REG (dest);
10160 /* If this is a MEM, adjust deaths of anything used in the address.
10161 For a REG (the only other possibility), the entire value is
10162 being replaced so the old value is not used in this insn. */
10164 if (GET_CODE (dest) == MEM)
10165 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
10169 else if (GET_CODE (x) == CLOBBER)
10172 len = GET_RTX_LENGTH (code);
10173 fmt = GET_RTX_FORMAT (code);
10175 for (i = 0; i < len; i++)
10180 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10181 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
10183 else if (fmt[i] == 'e')
10184 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
10188 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10189 pattern of an insn. X must be a REG. */
10192 reg_bitfield_target_p (x, body)
10198 if (GET_CODE (body) == SET)
10200 rtx dest = SET_DEST (body);
10202 int regno, tregno, endregno, endtregno;
10204 if (GET_CODE (dest) == ZERO_EXTRACT)
10205 target = XEXP (dest, 0);
10206 else if (GET_CODE (dest) == STRICT_LOW_PART)
10207 target = SUBREG_REG (XEXP (dest, 0));
10211 if (GET_CODE (target) == SUBREG)
10212 target = SUBREG_REG (target);
10214 if (GET_CODE (target) != REG)
10217 tregno = REGNO (target), regno = REGNO (x);
10218 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10219 return target == x;
10221 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10222 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10224 return endregno > tregno && regno < endtregno;
10227 else if (GET_CODE (body) == PARALLEL)
10228 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10229 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10235 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10236 as appropriate. I3 and I2 are the insns resulting from the combination
10237 insns including FROM (I2 may be zero).
10239 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10240 not need REG_DEAD notes because they are being substituted for. This
10241 saves searching in the most common cases.
10243 Each note in the list is either ignored or placed on some insns, depending
10244 on the type of note. */
10247 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10251 rtx elim_i2, elim_i1;
10253 rtx note, next_note;
10256 for (note = notes; note; note = next_note)
10258 rtx place = 0, place2 = 0;
10260 /* If this NOTE references a pseudo register, ensure it references
10261 the latest copy of that register. */
10262 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
10263 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
10264 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
10266 next_note = XEXP (note, 1);
10267 switch (REG_NOTE_KIND (note))
10270 /* If this note is from any insn other than i3, then we have no
10271 use for it, and must ignore it.
10273 Any clobbers for i3 may still exist, and so we must process
10274 REG_UNUSED notes from that insn.
10276 Any clobbers from i2 or i1 can only exist if they were added by
10277 recog_for_combine. In that case, recog_for_combine created the
10278 necessary REG_UNUSED notes. Trying to keep any original
10279 REG_UNUSED notes from these insns can cause incorrect output
10280 if it is for the same register as the original i3 dest.
10281 In that case, we will notice that the register is set in i3,
10282 and then add a REG_UNUSED note for the destination of i3, which
10284 if (from_insn != i3)
10287 /* If this register is set or clobbered in I3, put the note there
10288 unless there is one already. */
10289 else if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
10291 if (! (GET_CODE (XEXP (note, 0)) == REG
10292 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
10293 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
10296 /* Otherwise, if this register is used by I3, then this register
10297 now dies here, so we must put a REG_DEAD note here unless there
10299 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
10300 && ! (GET_CODE (XEXP (note, 0)) == REG
10301 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
10302 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
10304 PUT_REG_NOTE_KIND (note, REG_DEAD);
10312 /* These notes say something about results of an insn. We can
10313 only support them if they used to be on I3 in which case they
10314 remain on I3. Otherwise they are ignored.
10316 If the note refers to an expression that is not a constant, we
10317 must also ignore the note since we cannot tell whether the
10318 equivalence is still true. It might be possible to do
10319 slightly better than this (we only have a problem if I2DEST
10320 or I1DEST is present in the expression), but it doesn't
10321 seem worth the trouble. */
10323 if (from_insn == i3
10324 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
10329 case REG_NO_CONFLICT:
10331 /* These notes say something about how a register is used. They must
10332 be present on any use of the register in I2 or I3. */
10333 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
10336 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
10346 /* It is too much trouble to try to see if this note is still
10347 correct in all situations. It is better to simply delete it. */
10351 /* If the insn previously containing this note still exists,
10352 put it back where it was. Otherwise move it to the previous
10353 insn. Adjust the corresponding REG_LIBCALL note. */
10354 if (GET_CODE (from_insn) != NOTE)
10358 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
10359 place = prev_real_insn (from_insn);
10361 XEXP (tem, 0) = place;
10366 /* This is handled similarly to REG_RETVAL. */
10367 if (GET_CODE (from_insn) != NOTE)
10371 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
10372 place = next_real_insn (from_insn);
10374 XEXP (tem, 0) = place;
10379 /* If the register is used as an input in I3, it dies there.
10380 Similarly for I2, if it is non-zero and adjacent to I3.
10382 If the register is not used as an input in either I3 or I2
10383 and it is not one of the registers we were supposed to eliminate,
10384 there are two possibilities. We might have a non-adjacent I2
10385 or we might have somehow eliminated an additional register
10386 from a computation. For example, we might have had A & B where
10387 we discover that B will always be zero. In this case we will
10388 eliminate the reference to A.
10390 In both cases, we must search to see if we can find a previous
10391 use of A and put the death note there. */
10393 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
10395 else if (i2 != 0 && next_nonnote_insn (i2) == i3
10396 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10399 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
10402 /* If the register is used in both I2 and I3 and it dies in I3,
10403 we might have added another reference to it. If reg_n_refs
10404 was 2, bump it to 3. This has to be correct since the
10405 register must have been set somewhere. The reason this is
10406 done is because local-alloc.c treats 2 references as a
10409 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
10410 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
10411 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10412 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
10415 for (tem = prev_nonnote_insn (i3);
10416 tem && (GET_CODE (tem) == INSN
10417 || GET_CODE (tem) == CALL_INSN);
10418 tem = prev_nonnote_insn (tem))
10420 /* If the register is being set at TEM, see if that is all
10421 TEM is doing. If so, delete TEM. Otherwise, make this
10422 into a REG_UNUSED note instead. */
10423 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
10425 rtx set = single_set (tem);
10427 /* Verify that it was the set, and not a clobber that
10428 modified the register. */
10430 if (set != 0 && ! side_effects_p (SET_SRC (set))
10431 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
10433 /* Move the notes and links of TEM elsewhere.
10434 This might delete other dead insns recursively.
10435 First set the pattern to something that won't use
10438 PATTERN (tem) = pc_rtx;
10440 distribute_notes (REG_NOTES (tem), tem, tem,
10441 NULL_RTX, NULL_RTX, NULL_RTX);
10442 distribute_links (LOG_LINKS (tem));
10444 PUT_CODE (tem, NOTE);
10445 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
10446 NOTE_SOURCE_FILE (tem) = 0;
10450 PUT_REG_NOTE_KIND (note, REG_UNUSED);
10452 /* If there isn't already a REG_UNUSED note, put one
10454 if (! find_regno_note (tem, REG_UNUSED,
10455 REGNO (XEXP (note, 0))))
10460 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
10467 /* If the register is set or already dead at PLACE, we needn't do
10468 anything with this note if it is still a REG_DEAD note.
10470 Note that we cannot use just `dead_or_set_p' here since we can
10471 convert an assignment to a register into a bit-field assignment.
10472 Therefore, we must also omit the note if the register is the
10473 target of a bitfield assignment. */
10475 if (place && REG_NOTE_KIND (note) == REG_DEAD)
10477 int regno = REGNO (XEXP (note, 0));
10479 if (dead_or_set_p (place, XEXP (note, 0))
10480 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
10482 /* Unless the register previously died in PLACE, clear
10483 reg_last_death. [I no longer understand why this is
10485 if (reg_last_death[regno] != place)
10486 reg_last_death[regno] = 0;
10490 reg_last_death[regno] = place;
10492 /* If this is a death note for a hard reg that is occupying
10493 multiple registers, ensure that we are still using all
10494 parts of the object. If we find a piece of the object
10495 that is unused, we must add a USE for that piece before
10496 PLACE and put the appropriate REG_DEAD note on it.
10498 An alternative would be to put a REG_UNUSED for the pieces
10499 on the insn that set the register, but that can't be done if
10500 it is not in the same block. It is simpler, though less
10501 efficient, to add the USE insns. */
10503 if (place && regno < FIRST_PSEUDO_REGISTER
10504 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
10507 = regno + HARD_REGNO_NREGS (regno,
10508 GET_MODE (XEXP (note, 0)));
10512 for (i = regno; i < endregno; i++)
10513 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
10515 rtx piece = gen_rtx (REG, word_mode, i);
10518 /* See if we already placed a USE note for this
10519 register in front of PLACE. */
10521 GET_CODE (PREV_INSN (p)) == INSN
10522 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
10524 if (rtx_equal_p (piece,
10525 XEXP (PATTERN (PREV_INSN (p)), 0)))
10534 = emit_insn_before (gen_rtx (USE, VOIDmode,
10537 REG_NOTES (use_insn)
10538 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
10539 REG_NOTES (use_insn));
10545 /* Check for the case where the register dying partially
10546 overlaps the register set by this insn. */
10548 for (i = regno; i < endregno; i++)
10549 if (dead_or_set_regno_p (place, i))
10557 /* Put only REG_DEAD notes for pieces that are
10558 still used and that are not already dead or set. */
10560 for (i = regno; i < endregno; i++)
10562 rtx piece = gen_rtx (REG, word_mode, i);
10564 if (reg_referenced_p (piece, PATTERN (place))
10565 && ! dead_or_set_p (place, piece)
10566 && ! reg_bitfield_target_p (piece,
10568 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
10570 REG_NOTES (place));
10580 /* Any other notes should not be present at this point in the
10587 XEXP (note, 1) = REG_NOTES (place);
10588 REG_NOTES (place) = note;
10590 else if ((REG_NOTE_KIND (note) == REG_DEAD
10591 || REG_NOTE_KIND (note) == REG_UNUSED)
10592 && GET_CODE (XEXP (note, 0)) == REG)
10593 reg_n_deaths[REGNO (XEXP (note, 0))]--;
10597 if ((REG_NOTE_KIND (note) == REG_DEAD
10598 || REG_NOTE_KIND (note) == REG_UNUSED)
10599 && GET_CODE (XEXP (note, 0)) == REG)
10600 reg_n_deaths[REGNO (XEXP (note, 0))]++;
10602 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
10603 XEXP (note, 0), REG_NOTES (place2));
10608 /* Similarly to above, distribute the LOG_LINKS that used to be present on
10609 I3, I2, and I1 to new locations. This is also called in one case to
10610 add a link pointing at I3 when I3's destination is changed. */
10613 distribute_links (links)
10616 rtx link, next_link;
10618 for (link = links; link; link = next_link)
10624 next_link = XEXP (link, 1);
10626 /* If the insn that this link points to is a NOTE or isn't a single
10627 set, ignore it. In the latter case, it isn't clear what we
10628 can do other than ignore the link, since we can't tell which
10629 register it was for. Such links wouldn't be used by combine
10632 It is not possible for the destination of the target of the link to
10633 have been changed by combine. The only potential of this is if we
10634 replace I3, I2, and I1 by I3 and I2. But in that case the
10635 destination of I2 also remains unchanged. */
10637 if (GET_CODE (XEXP (link, 0)) == NOTE
10638 || (set = single_set (XEXP (link, 0))) == 0)
10641 reg = SET_DEST (set);
10642 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
10643 || GET_CODE (reg) == SIGN_EXTRACT
10644 || GET_CODE (reg) == STRICT_LOW_PART)
10645 reg = XEXP (reg, 0);
10647 /* A LOG_LINK is defined as being placed on the first insn that uses
10648 a register and points to the insn that sets the register. Start
10649 searching at the next insn after the target of the link and stop
10650 when we reach a set of the register or the end of the basic block.
10652 Note that this correctly handles the link that used to point from
10653 I3 to I2. Also note that not much searching is typically done here
10654 since most links don't point very far away. */
10656 for (insn = NEXT_INSN (XEXP (link, 0));
10657 (insn && (this_basic_block == n_basic_blocks - 1
10658 || basic_block_head[this_basic_block + 1] != insn));
10659 insn = NEXT_INSN (insn))
10660 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
10661 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
10663 if (reg_referenced_p (reg, PATTERN (insn)))
10668 /* If we found a place to put the link, place it there unless there
10669 is already a link to the same insn as LINK at that point. */
10675 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
10676 if (XEXP (link2, 0) == XEXP (link, 0))
10681 XEXP (link, 1) = LOG_LINKS (place);
10682 LOG_LINKS (place) = link;
10684 /* Set added_links_insn to the earliest insn we added a
10686 if (added_links_insn == 0
10687 || INSN_CUID (added_links_insn) > INSN_CUID (place))
10688 added_links_insn = place;
10695 dump_combine_stats (file)
10700 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
10701 combine_attempts, combine_merges, combine_extras, combine_successes);
10705 dump_combine_total_stats (file)
10710 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
10711 total_attempts, total_merges, total_extras, total_successes);