1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST (rtx *, rtx);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
346 static int cant_combine_insn_p (rtx);
347 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
348 static int sets_function_arg_p (rtx);
349 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
350 static int contains_muldiv (rtx);
351 static rtx try_combine (rtx, rtx, rtx, int *);
352 static void undo_all (void);
353 static void undo_commit (void);
354 static rtx *find_split_point (rtx *, rtx);
355 static rtx subst (rtx, rtx, rtx, int, int);
356 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
357 static rtx simplify_if_then_else (rtx);
358 static rtx simplify_set (rtx);
359 static rtx simplify_logical (rtx, int);
360 static rtx expand_compound_operation (rtx);
361 static rtx expand_field_assignment (rtx);
362 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
363 rtx, unsigned HOST_WIDE_INT, int, int, int);
364 static rtx extract_left_shift (rtx, int);
365 static rtx make_compound_operation (rtx, enum rtx_code);
366 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
367 unsigned HOST_WIDE_INT *);
368 static rtx force_to_mode (rtx, enum machine_mode,
369 unsigned HOST_WIDE_INT, rtx, int);
370 static rtx if_then_else_cond (rtx, rtx *, rtx *);
371 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
372 static int rtx_equal_for_field_assignment_p (rtx, rtx);
373 static rtx make_field_assignment (rtx);
374 static rtx apply_distributive_law (rtx);
375 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
376 unsigned HOST_WIDE_INT);
377 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
378 rtx, enum machine_mode,
379 unsigned HOST_WIDE_INT);
380 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
382 unsigned HOST_WIDE_INT);
383 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
386 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
387 enum machine_mode, unsigned int);
388 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
389 HOST_WIDE_INT, enum machine_mode, int *);
390 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
392 static int recog_for_combine (rtx *, rtx, rtx *);
393 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
394 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
395 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
396 static void update_table_tick (rtx);
397 static void record_value_for_reg (rtx, rtx, rtx);
398 static void check_promoted_subreg (rtx, rtx);
399 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
400 static void record_dead_and_set_regs (rtx);
401 static int get_last_value_validate (rtx *, rtx, int, int);
402 static rtx get_last_value (rtx);
403 static int use_crosses_set_p (rtx, int);
404 static void reg_dead_at_p_1 (rtx, rtx, void *);
405 static int reg_dead_at_p (rtx, rtx);
406 static void move_deaths (rtx, rtx, int, rtx, rtx *);
407 static int reg_bitfield_target_p (rtx, rtx);
408 static void distribute_notes (rtx, rtx, rtx, rtx);
409 static void distribute_links (rtx);
410 static void mark_used_regs_combine (rtx);
411 static int insn_cuid (rtx);
412 static void record_promoted_value (rtx, rtx);
413 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
414 static enum rtx_code combine_reversed_comparison_code (rtx);
416 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
417 insn. The substitution can be undone by undo_all. If INTO is already
418 set to NEWVAL, do not record this change. Because computing NEWVAL might
419 also call SUBST, we have to compute it before we put anything into
423 do_SUBST (rtx *into, rtx newval)
428 if (oldval == newval)
431 /* We'd like to catch as many invalid transformations here as
432 possible. Unfortunately, there are way too many mode changes
433 that are perfectly valid, so we'd waste too much effort for
434 little gain doing the checks here. Focus on catching invalid
435 transformations involving integer constants. */
436 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
437 && GET_CODE (newval) == CONST_INT)
439 /* Sanity check that we're replacing oldval with a CONST_INT
440 that is a valid sign-extension for the original mode. */
441 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
445 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
446 CONST_INT is not valid, because after the replacement, the
447 original mode would be gone. Unfortunately, we can't tell
448 when do_SUBST is called to replace the operand thereof, so we
449 perform this test on oldval instead, checking whether an
450 invalid replacement took place before we got here. */
451 if ((GET_CODE (oldval) == SUBREG
452 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
453 || (GET_CODE (oldval) == ZERO_EXTEND
454 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
459 buf = undobuf.frees, undobuf.frees = buf->next;
461 buf = xmalloc (sizeof (struct undo));
465 buf->old_contents.r = oldval;
468 buf->next = undobuf.undos, undobuf.undos = buf;
471 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
473 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
474 for the value of a HOST_WIDE_INT value (including CONST_INT) is
478 do_SUBST_INT (int *into, int newval)
483 if (oldval == newval)
487 buf = undobuf.frees, undobuf.frees = buf->next;
489 buf = xmalloc (sizeof (struct undo));
493 buf->old_contents.i = oldval;
496 buf->next = undobuf.undos, undobuf.undos = buf;
499 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
501 /* Main entry point for combiner. F is the first insn of the function.
502 NREGS is the first unused pseudo-reg number.
504 Return nonzero if the combiner has turned an indirect jump
505 instruction into a direct jump. */
507 combine_instructions (rtx f, unsigned int nregs)
514 rtx links, nextlinks;
516 int new_direct_jump_p = 0;
518 combine_attempts = 0;
521 combine_successes = 0;
523 combine_max_regno = nregs;
525 reg_nonzero_bits = xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT));
526 reg_sign_bit_copies = xcalloc (nregs, sizeof (unsigned char));
528 reg_last_death = xmalloc (nregs * sizeof (rtx));
529 reg_last_set = xmalloc (nregs * sizeof (rtx));
530 reg_last_set_value = xmalloc (nregs * sizeof (rtx));
531 reg_last_set_table_tick = xmalloc (nregs * sizeof (int));
532 reg_last_set_label = xmalloc (nregs * sizeof (int));
533 reg_last_set_invalid = xmalloc (nregs * sizeof (char));
534 reg_last_set_mode = xmalloc (nregs * sizeof (enum machine_mode));
535 reg_last_set_nonzero_bits = xmalloc (nregs * sizeof (HOST_WIDE_INT));
536 reg_last_set_sign_bit_copies = xmalloc (nregs * sizeof (char));
538 init_reg_last_arrays ();
540 init_recog_no_volatile ();
542 /* Compute maximum uid value so uid_cuid can be allocated. */
544 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
545 if (INSN_UID (insn) > i)
548 uid_cuid = xmalloc ((i + 1) * sizeof (int));
551 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
553 /* Don't use reg_nonzero_bits when computing it. This can cause problems
554 when, for example, we have j <<= 1 in a loop. */
556 nonzero_sign_valid = 0;
558 /* Compute the mapping from uids to cuids.
559 Cuids are numbers assigned to insns, like uids,
560 except that cuids increase monotonically through the code.
562 Scan all SETs and see if we can deduce anything about what
563 bits are known to be zero for some registers and how many copies
564 of the sign bit are known to exist for those registers.
566 Also set any known values so that we can use it while searching
567 for what bits are known to be set. */
571 setup_incoming_promotions ();
573 refresh_blocks = sbitmap_alloc (last_basic_block);
574 sbitmap_zero (refresh_blocks);
576 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
578 uid_cuid[INSN_UID (insn)] = ++i;
584 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
586 record_dead_and_set_regs (insn);
589 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
590 if (REG_NOTE_KIND (links) == REG_INC)
591 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
596 if (GET_CODE (insn) == CODE_LABEL)
600 nonzero_sign_valid = 1;
602 /* Now scan all the insns in forward order. */
607 init_reg_last_arrays ();
608 setup_incoming_promotions ();
610 FOR_EACH_BB (this_basic_block)
612 for (insn = this_basic_block->head;
613 insn != NEXT_INSN (this_basic_block->end);
614 insn = next ? next : NEXT_INSN (insn))
618 if (GET_CODE (insn) == CODE_LABEL)
621 else if (INSN_P (insn))
623 /* See if we know about function return values before this
624 insn based upon SUBREG flags. */
625 check_promoted_subreg (insn, PATTERN (insn));
627 /* Try this insn with each insn it links back to. */
629 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
630 if ((next = try_combine (insn, XEXP (links, 0),
631 NULL_RTX, &new_direct_jump_p)) != 0)
634 /* Try each sequence of three linked insns ending with this one. */
636 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
638 rtx link = XEXP (links, 0);
640 /* If the linked insn has been replaced by a note, then there
641 is no point in pursuing this chain any further. */
642 if (GET_CODE (link) == NOTE)
645 for (nextlinks = LOG_LINKS (link);
647 nextlinks = XEXP (nextlinks, 1))
648 if ((next = try_combine (insn, link,
650 &new_direct_jump_p)) != 0)
655 /* Try to combine a jump insn that uses CC0
656 with a preceding insn that sets CC0, and maybe with its
657 logical predecessor as well.
658 This is how we make decrement-and-branch insns.
659 We need this special code because data flow connections
660 via CC0 do not get entered in LOG_LINKS. */
662 if (GET_CODE (insn) == JUMP_INSN
663 && (prev = prev_nonnote_insn (insn)) != 0
664 && GET_CODE (prev) == INSN
665 && sets_cc0_p (PATTERN (prev)))
667 if ((next = try_combine (insn, prev,
668 NULL_RTX, &new_direct_jump_p)) != 0)
671 for (nextlinks = LOG_LINKS (prev); nextlinks;
672 nextlinks = XEXP (nextlinks, 1))
673 if ((next = try_combine (insn, prev,
675 &new_direct_jump_p)) != 0)
679 /* Do the same for an insn that explicitly references CC0. */
680 if (GET_CODE (insn) == INSN
681 && (prev = prev_nonnote_insn (insn)) != 0
682 && GET_CODE (prev) == INSN
683 && sets_cc0_p (PATTERN (prev))
684 && GET_CODE (PATTERN (insn)) == SET
685 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
687 if ((next = try_combine (insn, prev,
688 NULL_RTX, &new_direct_jump_p)) != 0)
691 for (nextlinks = LOG_LINKS (prev); nextlinks;
692 nextlinks = XEXP (nextlinks, 1))
693 if ((next = try_combine (insn, prev,
695 &new_direct_jump_p)) != 0)
699 /* Finally, see if any of the insns that this insn links to
700 explicitly references CC0. If so, try this insn, that insn,
701 and its predecessor if it sets CC0. */
702 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
703 if (GET_CODE (XEXP (links, 0)) == INSN
704 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
705 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
706 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
707 && GET_CODE (prev) == INSN
708 && sets_cc0_p (PATTERN (prev))
709 && (next = try_combine (insn, XEXP (links, 0),
710 prev, &new_direct_jump_p)) != 0)
714 /* Try combining an insn with two different insns whose results it
716 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
717 for (nextlinks = XEXP (links, 1); nextlinks;
718 nextlinks = XEXP (nextlinks, 1))
719 if ((next = try_combine (insn, XEXP (links, 0),
721 &new_direct_jump_p)) != 0)
724 if (GET_CODE (insn) != NOTE)
725 record_dead_and_set_regs (insn);
734 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
735 BASIC_BLOCK (i)->flags |= BB_DIRTY);
736 new_direct_jump_p |= purge_all_dead_edges (0);
737 delete_noop_moves (f);
739 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
740 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
741 | PROP_KILL_DEAD_CODE);
744 sbitmap_free (refresh_blocks);
745 free (reg_nonzero_bits);
746 free (reg_sign_bit_copies);
747 free (reg_last_death);
749 free (reg_last_set_value);
750 free (reg_last_set_table_tick);
751 free (reg_last_set_label);
752 free (reg_last_set_invalid);
753 free (reg_last_set_mode);
754 free (reg_last_set_nonzero_bits);
755 free (reg_last_set_sign_bit_copies);
759 struct undo *undo, *next;
760 for (undo = undobuf.frees; undo; undo = next)
768 total_attempts += combine_attempts;
769 total_merges += combine_merges;
770 total_extras += combine_extras;
771 total_successes += combine_successes;
773 nonzero_sign_valid = 0;
775 /* Make recognizer allow volatile MEMs again. */
778 return new_direct_jump_p;
781 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
784 init_reg_last_arrays (void)
786 unsigned int nregs = combine_max_regno;
788 memset (reg_last_death, 0, nregs * sizeof (rtx));
789 memset (reg_last_set, 0, nregs * sizeof (rtx));
790 memset (reg_last_set_value, 0, nregs * sizeof (rtx));
791 memset (reg_last_set_table_tick, 0, nregs * sizeof (int));
792 memset (reg_last_set_label, 0, nregs * sizeof (int));
793 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
794 memset (reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
795 memset (reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
796 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
799 /* Set up any promoted values for incoming argument registers. */
802 setup_incoming_promotions (void)
806 enum machine_mode mode;
808 rtx first = get_insns ();
810 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
812 #ifndef OUTGOING_REGNO
813 #define OUTGOING_REGNO(N) N
815 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
816 /* Check whether this register can hold an incoming pointer
817 argument. FUNCTION_ARG_REGNO_P tests outgoing register
818 numbers, so translate if necessary due to register windows. */
819 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
820 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
823 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
826 gen_rtx_CLOBBER (mode, const0_rtx)));
831 /* Called via note_stores. If X is a pseudo that is narrower than
832 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
834 If we are setting only a portion of X and we can't figure out what
835 portion, assume all bits will be used since we don't know what will
838 Similarly, set how many bits of X are known to be copies of the sign bit
839 at all locations in the function. This is the smallest number implied
843 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
844 void *data ATTRIBUTE_UNUSED)
848 if (GET_CODE (x) == REG
849 && REGNO (x) >= FIRST_PSEUDO_REGISTER
850 /* If this register is undefined at the start of the file, we can't
851 say what its contents were. */
852 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
853 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
855 if (set == 0 || GET_CODE (set) == CLOBBER)
857 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
858 reg_sign_bit_copies[REGNO (x)] = 1;
862 /* If this is a complex assignment, see if we can convert it into a
863 simple assignment. */
864 set = expand_field_assignment (set);
866 /* If this is a simple assignment, or we have a paradoxical SUBREG,
867 set what we know about X. */
869 if (SET_DEST (set) == x
870 || (GET_CODE (SET_DEST (set)) == SUBREG
871 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
872 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
873 && SUBREG_REG (SET_DEST (set)) == x))
875 rtx src = SET_SRC (set);
877 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
878 /* If X is narrower than a word and SRC is a non-negative
879 constant that would appear negative in the mode of X,
880 sign-extend it for use in reg_nonzero_bits because some
881 machines (maybe most) will actually do the sign-extension
882 and this is the conservative approach.
884 ??? For 2.5, try to tighten up the MD files in this regard
885 instead of this kludge. */
887 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
888 && GET_CODE (src) == CONST_INT
890 && 0 != (INTVAL (src)
892 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
893 src = GEN_INT (INTVAL (src)
894 | ((HOST_WIDE_INT) (-1)
895 << GET_MODE_BITSIZE (GET_MODE (x))));
898 /* Don't call nonzero_bits if it cannot change anything. */
899 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
900 reg_nonzero_bits[REGNO (x)]
901 |= nonzero_bits (src, nonzero_bits_mode);
902 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
903 if (reg_sign_bit_copies[REGNO (x)] == 0
904 || reg_sign_bit_copies[REGNO (x)] > num)
905 reg_sign_bit_copies[REGNO (x)] = num;
909 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
910 reg_sign_bit_copies[REGNO (x)] = 1;
915 /* See if INSN can be combined into I3. PRED and SUCC are optionally
916 insns that were previously combined into I3 or that will be combined
917 into the merger of INSN and I3.
919 Return 0 if the combination is not allowed for any reason.
921 If the combination is allowed, *PDEST will be set to the single
922 destination of INSN and *PSRC to the single source, and this function
926 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
927 rtx *pdest, rtx *psrc)
930 rtx set = 0, src, dest;
935 int all_adjacent = (succ ? (next_active_insn (insn) == succ
936 && next_active_insn (succ) == i3)
937 : next_active_insn (insn) == i3);
939 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
940 or a PARALLEL consisting of such a SET and CLOBBERs.
942 If INSN has CLOBBER parallel parts, ignore them for our processing.
943 By definition, these happen during the execution of the insn. When it
944 is merged with another insn, all bets are off. If they are, in fact,
945 needed and aren't also supplied in I3, they may be added by
946 recog_for_combine. Otherwise, it won't match.
948 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
951 Get the source and destination of INSN. If more than one, can't
954 if (GET_CODE (PATTERN (insn)) == SET)
955 set = PATTERN (insn);
956 else if (GET_CODE (PATTERN (insn)) == PARALLEL
957 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
959 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
961 rtx elt = XVECEXP (PATTERN (insn), 0, i);
963 switch (GET_CODE (elt))
965 /* This is important to combine floating point insns
968 /* Combining an isolated USE doesn't make sense.
969 We depend here on combinable_i3pat to reject them. */
970 /* The code below this loop only verifies that the inputs of
971 the SET in INSN do not change. We call reg_set_between_p
972 to verify that the REG in the USE does not change between
974 If the USE in INSN was for a pseudo register, the matching
975 insn pattern will likely match any register; combining this
976 with any other USE would only be safe if we knew that the
977 used registers have identical values, or if there was
978 something to tell them apart, e.g. different modes. For
979 now, we forgo such complicated tests and simply disallow
980 combining of USES of pseudo registers with any other USE. */
981 if (GET_CODE (XEXP (elt, 0)) == REG
982 && GET_CODE (PATTERN (i3)) == PARALLEL)
984 rtx i3pat = PATTERN (i3);
985 int i = XVECLEN (i3pat, 0) - 1;
986 unsigned int regno = REGNO (XEXP (elt, 0));
990 rtx i3elt = XVECEXP (i3pat, 0, i);
992 if (GET_CODE (i3elt) == USE
993 && GET_CODE (XEXP (i3elt, 0)) == REG
994 && (REGNO (XEXP (i3elt, 0)) == regno
995 ? reg_set_between_p (XEXP (elt, 0),
996 PREV_INSN (insn), i3)
997 : regno >= FIRST_PSEUDO_REGISTER))
1004 /* We can ignore CLOBBERs. */
1009 /* Ignore SETs whose result isn't used but not those that
1010 have side-effects. */
1011 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1012 && ! side_effects_p (elt))
1015 /* If we have already found a SET, this is a second one and
1016 so we cannot combine with this insn. */
1024 /* Anything else means we can't combine. */
1030 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1031 so don't do anything with it. */
1032 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1041 set = expand_field_assignment (set);
1042 src = SET_SRC (set), dest = SET_DEST (set);
1044 /* Don't eliminate a store in the stack pointer. */
1045 if (dest == stack_pointer_rtx
1046 /* Don't combine with an insn that sets a register to itself if it has
1047 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1048 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1049 /* Can't merge an ASM_OPERANDS. */
1050 || GET_CODE (src) == ASM_OPERANDS
1051 /* Can't merge a function call. */
1052 || GET_CODE (src) == CALL
1053 /* Don't eliminate a function call argument. */
1054 || (GET_CODE (i3) == CALL_INSN
1055 && (find_reg_fusage (i3, USE, dest)
1056 || (GET_CODE (dest) == REG
1057 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1058 && global_regs[REGNO (dest)])))
1059 /* Don't substitute into an incremented register. */
1060 || FIND_REG_INC_NOTE (i3, dest)
1061 || (succ && FIND_REG_INC_NOTE (succ, dest))
1063 /* Don't combine the end of a libcall into anything. */
1064 /* ??? This gives worse code, and appears to be unnecessary, since no
1065 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1066 use REG_RETVAL notes for noconflict blocks, but other code here
1067 makes sure that those insns don't disappear. */
1068 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1070 /* Make sure that DEST is not used after SUCC but before I3. */
1071 || (succ && ! all_adjacent
1072 && reg_used_between_p (dest, succ, i3))
1073 /* Make sure that the value that is to be substituted for the register
1074 does not use any registers whose values alter in between. However,
1075 If the insns are adjacent, a use can't cross a set even though we
1076 think it might (this can happen for a sequence of insns each setting
1077 the same destination; reg_last_set of that register might point to
1078 a NOTE). If INSN has a REG_EQUIV note, the register is always
1079 equivalent to the memory so the substitution is valid even if there
1080 are intervening stores. Also, don't move a volatile asm or
1081 UNSPEC_VOLATILE across any other insns. */
1083 && (((GET_CODE (src) != MEM
1084 || ! find_reg_note (insn, REG_EQUIV, src))
1085 && use_crosses_set_p (src, INSN_CUID (insn)))
1086 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1087 || GET_CODE (src) == UNSPEC_VOLATILE))
1088 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1089 better register allocation by not doing the combine. */
1090 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1091 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1092 /* Don't combine across a CALL_INSN, because that would possibly
1093 change whether the life span of some REGs crosses calls or not,
1094 and it is a pain to update that information.
1095 Exception: if source is a constant, moving it later can't hurt.
1096 Accept that special case, because it helps -fforce-addr a lot. */
1097 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1100 /* DEST must either be a REG or CC0. */
1101 if (GET_CODE (dest) == REG)
1103 /* If register alignment is being enforced for multi-word items in all
1104 cases except for parameters, it is possible to have a register copy
1105 insn referencing a hard register that is not allowed to contain the
1106 mode being copied and which would not be valid as an operand of most
1107 insns. Eliminate this problem by not combining with such an insn.
1109 Also, on some machines we don't want to extend the life of a hard
1112 if (GET_CODE (src) == REG
1113 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1114 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1115 /* Don't extend the life of a hard register unless it is
1116 user variable (if we have few registers) or it can't
1117 fit into the desired register (meaning something special
1119 Also avoid substituting a return register into I3, because
1120 reload can't handle a conflict with constraints of other
1122 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1123 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1126 else if (GET_CODE (dest) != CC0)
1129 /* Don't substitute for a register intended as a clobberable operand.
1130 Similarly, don't substitute an expression containing a register that
1131 will be clobbered in I3. */
1132 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1133 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1134 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1135 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1137 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1140 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1141 or not), reject, unless nothing volatile comes between it and I3 */
1143 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1145 /* Make sure succ doesn't contain a volatile reference. */
1146 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1149 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1150 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1154 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1155 to be an explicit register variable, and was chosen for a reason. */
1157 if (GET_CODE (src) == ASM_OPERANDS
1158 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1161 /* If there are any volatile insns between INSN and I3, reject, because
1162 they might affect machine state. */
1164 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1165 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1168 /* If INSN or I2 contains an autoincrement or autodecrement,
1169 make sure that register is not used between there and I3,
1170 and not already used in I3 either.
1171 Also insist that I3 not be a jump; if it were one
1172 and the incremented register were spilled, we would lose. */
1175 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1176 if (REG_NOTE_KIND (link) == REG_INC
1177 && (GET_CODE (i3) == JUMP_INSN
1178 || reg_used_between_p (XEXP (link, 0), insn, i3)
1179 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1184 /* Don't combine an insn that follows a CC0-setting insn.
1185 An insn that uses CC0 must not be separated from the one that sets it.
1186 We do, however, allow I2 to follow a CC0-setting insn if that insn
1187 is passed as I1; in that case it will be deleted also.
1188 We also allow combining in this case if all the insns are adjacent
1189 because that would leave the two CC0 insns adjacent as well.
1190 It would be more logical to test whether CC0 occurs inside I1 or I2,
1191 but that would be much slower, and this ought to be equivalent. */
1193 p = prev_nonnote_insn (insn);
1194 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1199 /* If we get here, we have passed all the tests and the combination is
1208 /* Check if PAT is an insn - or a part of it - used to set up an
1209 argument for a function in a hard register. */
1212 sets_function_arg_p (rtx pat)
1217 switch (GET_CODE (pat))
1220 return sets_function_arg_p (PATTERN (pat));
1223 for (i = XVECLEN (pat, 0); --i >= 0;)
1224 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1230 inner_dest = SET_DEST (pat);
1231 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1232 || GET_CODE (inner_dest) == SUBREG
1233 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1234 inner_dest = XEXP (inner_dest, 0);
1236 return (GET_CODE (inner_dest) == REG
1237 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1238 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1247 /* LOC is the location within I3 that contains its pattern or the component
1248 of a PARALLEL of the pattern. We validate that it is valid for combining.
1250 One problem is if I3 modifies its output, as opposed to replacing it
1251 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1252 so would produce an insn that is not equivalent to the original insns.
1256 (set (reg:DI 101) (reg:DI 100))
1257 (set (subreg:SI (reg:DI 101) 0) <foo>)
1259 This is NOT equivalent to:
1261 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1262 (set (reg:DI 101) (reg:DI 100))])
1264 Not only does this modify 100 (in which case it might still be valid
1265 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1267 We can also run into a problem if I2 sets a register that I1
1268 uses and I1 gets directly substituted into I3 (not via I2). In that
1269 case, we would be getting the wrong value of I2DEST into I3, so we
1270 must reject the combination. This case occurs when I2 and I1 both
1271 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1272 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1273 of a SET must prevent combination from occurring.
1275 Before doing the above check, we first try to expand a field assignment
1276 into a set of logical operations.
1278 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1279 we place a register that is both set and used within I3. If more than one
1280 such register is detected, we fail.
1282 Return 1 if the combination is valid, zero otherwise. */
1285 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1286 int i1_not_in_src, rtx *pi3dest_killed)
1290 if (GET_CODE (x) == SET)
1293 rtx dest = SET_DEST (set);
1294 rtx src = SET_SRC (set);
1295 rtx inner_dest = dest;
1297 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1298 || GET_CODE (inner_dest) == SUBREG
1299 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1300 inner_dest = XEXP (inner_dest, 0);
1302 /* Check for the case where I3 modifies its output, as discussed
1303 above. We don't want to prevent pseudos from being combined
1304 into the address of a MEM, so only prevent the combination if
1305 i1 or i2 set the same MEM. */
1306 if ((inner_dest != dest &&
1307 (GET_CODE (inner_dest) != MEM
1308 || rtx_equal_p (i2dest, inner_dest)
1309 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1310 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1311 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1313 /* This is the same test done in can_combine_p except we can't test
1314 all_adjacent; we don't have to, since this instruction will stay
1315 in place, thus we are not considering increasing the lifetime of
1318 Also, if this insn sets a function argument, combining it with
1319 something that might need a spill could clobber a previous
1320 function argument; the all_adjacent test in can_combine_p also
1321 checks this; here, we do a more specific test for this case. */
1323 || (GET_CODE (inner_dest) == REG
1324 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1325 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1326 GET_MODE (inner_dest))))
1327 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1330 /* If DEST is used in I3, it is being killed in this insn,
1331 so record that for later.
1332 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1333 STACK_POINTER_REGNUM, since these are always considered to be
1334 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1335 if (pi3dest_killed && GET_CODE (dest) == REG
1336 && reg_referenced_p (dest, PATTERN (i3))
1337 && REGNO (dest) != FRAME_POINTER_REGNUM
1338 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1339 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1341 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1342 && (REGNO (dest) != ARG_POINTER_REGNUM
1343 || ! fixed_regs [REGNO (dest)])
1345 && REGNO (dest) != STACK_POINTER_REGNUM)
1347 if (*pi3dest_killed)
1350 *pi3dest_killed = dest;
1354 else if (GET_CODE (x) == PARALLEL)
1358 for (i = 0; i < XVECLEN (x, 0); i++)
1359 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1360 i1_not_in_src, pi3dest_killed))
1367 /* Return 1 if X is an arithmetic expression that contains a multiplication
1368 and division. We don't count multiplications by powers of two here. */
1371 contains_muldiv (rtx x)
1373 switch (GET_CODE (x))
1375 case MOD: case DIV: case UMOD: case UDIV:
1379 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1380 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1382 switch (GET_RTX_CLASS (GET_CODE (x)))
1384 case 'c': case '<': case '2':
1385 return contains_muldiv (XEXP (x, 0))
1386 || contains_muldiv (XEXP (x, 1));
1389 return contains_muldiv (XEXP (x, 0));
1397 /* Determine whether INSN can be used in a combination. Return nonzero if
1398 not. This is used in try_combine to detect early some cases where we
1399 can't perform combinations. */
1402 cant_combine_insn_p (rtx insn)
1407 /* If this isn't really an insn, we can't do anything.
1408 This can occur when flow deletes an insn that it has merged into an
1409 auto-increment address. */
1410 if (! INSN_P (insn))
1413 /* Never combine loads and stores involving hard regs that are likely
1414 to be spilled. The register allocator can usually handle such
1415 reg-reg moves by tying. If we allow the combiner to make
1416 substitutions of likely-spilled regs, we may abort in reload.
1417 As an exception, we allow combinations involving fixed regs; these are
1418 not available to the register allocator so there's no risk involved. */
1420 set = single_set (insn);
1423 src = SET_SRC (set);
1424 dest = SET_DEST (set);
1425 if (GET_CODE (src) == SUBREG)
1426 src = SUBREG_REG (src);
1427 if (GET_CODE (dest) == SUBREG)
1428 dest = SUBREG_REG (dest);
1429 if (REG_P (src) && REG_P (dest)
1430 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1431 && ! fixed_regs[REGNO (src)]
1432 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1433 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1434 && ! fixed_regs[REGNO (dest)]
1435 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1441 /* Try to combine the insns I1 and I2 into I3.
1442 Here I1 and I2 appear earlier than I3.
1443 I1 can be zero; then we combine just I2 into I3.
1445 If we are combining three insns and the resulting insn is not recognized,
1446 try splitting it into two insns. If that happens, I2 and I3 are retained
1447 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1450 Return 0 if the combination does not work. Then nothing is changed.
1451 If we did the combination, return the insn at which combine should
1454 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1455 new direct jump instruction. */
1458 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1460 /* New patterns for I3 and I2, respectively. */
1461 rtx newpat, newi2pat = 0;
1462 int substed_i2 = 0, substed_i1 = 0;
1463 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1464 int added_sets_1, added_sets_2;
1465 /* Total number of SETs to put into I3. */
1467 /* Nonzero is I2's body now appears in I3. */
1469 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1470 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1471 /* Contains I3 if the destination of I3 is used in its source, which means
1472 that the old life of I3 is being killed. If that usage is placed into
1473 I2 and not in I3, a REG_DEAD note must be made. */
1474 rtx i3dest_killed = 0;
1475 /* SET_DEST and SET_SRC of I2 and I1. */
1476 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1477 /* PATTERN (I2), or a copy of it in certain cases. */
1479 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1480 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1481 int i1_feeds_i3 = 0;
1482 /* Notes that must be added to REG_NOTES in I3 and I2. */
1483 rtx new_i3_notes, new_i2_notes;
1484 /* Notes that we substituted I3 into I2 instead of the normal case. */
1485 int i3_subst_into_i2 = 0;
1486 /* Notes that I1, I2 or I3 is a MULT operation. */
1494 /* Exit early if one of the insns involved can't be used for
1496 if (cant_combine_insn_p (i3)
1497 || cant_combine_insn_p (i2)
1498 || (i1 && cant_combine_insn_p (i1))
1499 /* We also can't do anything if I3 has a
1500 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1503 /* ??? This gives worse code, and appears to be unnecessary, since no
1504 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1505 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1511 undobuf.other_insn = 0;
1513 /* Reset the hard register usage information. */
1514 CLEAR_HARD_REG_SET (newpat_used_regs);
1516 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1517 code below, set I1 to be the earlier of the two insns. */
1518 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1519 temp = i1, i1 = i2, i2 = temp;
1521 added_links_insn = 0;
1523 /* First check for one important special-case that the code below will
1524 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1525 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1526 we may be able to replace that destination with the destination of I3.
1527 This occurs in the common code where we compute both a quotient and
1528 remainder into a structure, in which case we want to do the computation
1529 directly into the structure to avoid register-register copies.
1531 Note that this case handles both multiple sets in I2 and also
1532 cases where I2 has a number of CLOBBER or PARALLELs.
1534 We make very conservative checks below and only try to handle the
1535 most common cases of this. For example, we only handle the case
1536 where I2 and I3 are adjacent to avoid making difficult register
1539 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1540 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1541 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1542 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1543 && GET_CODE (PATTERN (i2)) == PARALLEL
1544 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1545 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1546 below would need to check what is inside (and reg_overlap_mentioned_p
1547 doesn't support those codes anyway). Don't allow those destinations;
1548 the resulting insn isn't likely to be recognized anyway. */
1549 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1550 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1551 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1552 SET_DEST (PATTERN (i3)))
1553 && next_real_insn (i2) == i3)
1555 rtx p2 = PATTERN (i2);
1557 /* Make sure that the destination of I3,
1558 which we are going to substitute into one output of I2,
1559 is not used within another output of I2. We must avoid making this:
1560 (parallel [(set (mem (reg 69)) ...)
1561 (set (reg 69) ...)])
1562 which is not well-defined as to order of actions.
1563 (Besides, reload can't handle output reloads for this.)
1565 The problem can also happen if the dest of I3 is a memory ref,
1566 if another dest in I2 is an indirect memory ref. */
1567 for (i = 0; i < XVECLEN (p2, 0); i++)
1568 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1569 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1570 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1571 SET_DEST (XVECEXP (p2, 0, i))))
1574 if (i == XVECLEN (p2, 0))
1575 for (i = 0; i < XVECLEN (p2, 0); i++)
1576 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1577 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1578 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1583 subst_low_cuid = INSN_CUID (i2);
1585 added_sets_2 = added_sets_1 = 0;
1586 i2dest = SET_SRC (PATTERN (i3));
1588 /* Replace the dest in I2 with our dest and make the resulting
1589 insn the new pattern for I3. Then skip to where we
1590 validate the pattern. Everything was set up above. */
1591 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1592 SET_DEST (PATTERN (i3)));
1595 i3_subst_into_i2 = 1;
1596 goto validate_replacement;
1600 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1601 one of those words to another constant, merge them by making a new
1604 && (temp = single_set (i2)) != 0
1605 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1606 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1607 && GET_CODE (SET_DEST (temp)) == REG
1608 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1609 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1610 && GET_CODE (PATTERN (i3)) == SET
1611 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1612 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1613 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1614 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1615 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1617 HOST_WIDE_INT lo, hi;
1619 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1620 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1623 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1624 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1627 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1629 /* We don't handle the case of the target word being wider
1630 than a host wide int. */
1631 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1634 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1635 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1636 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1638 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1639 hi = INTVAL (SET_SRC (PATTERN (i3)));
1640 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1642 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1643 >> (HOST_BITS_PER_WIDE_INT - 1));
1645 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1646 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1647 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1648 (INTVAL (SET_SRC (PATTERN (i3)))));
1650 hi = lo < 0 ? -1 : 0;
1653 /* We don't handle the case of the higher word not fitting
1654 entirely in either hi or lo. */
1659 subst_low_cuid = INSN_CUID (i2);
1660 added_sets_2 = added_sets_1 = 0;
1661 i2dest = SET_DEST (temp);
1663 SUBST (SET_SRC (temp),
1664 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1666 newpat = PATTERN (i2);
1667 goto validate_replacement;
1671 /* If we have no I1 and I2 looks like:
1672 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1674 make up a dummy I1 that is
1677 (set (reg:CC X) (compare:CC Y (const_int 0)))
1679 (We can ignore any trailing CLOBBERs.)
1681 This undoes a previous combination and allows us to match a branch-and-
1684 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1685 && XVECLEN (PATTERN (i2), 0) >= 2
1686 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1687 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1689 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1690 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1691 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1692 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1693 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1694 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1696 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1697 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1702 /* We make I1 with the same INSN_UID as I2. This gives it
1703 the same INSN_CUID for value tracking. Our fake I1 will
1704 never appear in the insn stream so giving it the same INSN_UID
1705 as I2 will not cause a problem. */
1707 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1708 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1709 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1712 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1713 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1714 SET_DEST (PATTERN (i1)));
1719 /* Verify that I2 and I1 are valid for combining. */
1720 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1721 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1727 /* Record whether I2DEST is used in I2SRC and similarly for the other
1728 cases. Knowing this will help in register status updating below. */
1729 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1730 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1731 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1733 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1735 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1737 /* Ensure that I3's pattern can be the destination of combines. */
1738 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1739 i1 && i2dest_in_i1src && i1_feeds_i3,
1746 /* See if any of the insns is a MULT operation. Unless one is, we will
1747 reject a combination that is, since it must be slower. Be conservative
1749 if (GET_CODE (i2src) == MULT
1750 || (i1 != 0 && GET_CODE (i1src) == MULT)
1751 || (GET_CODE (PATTERN (i3)) == SET
1752 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1755 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1756 We used to do this EXCEPT in one case: I3 has a post-inc in an
1757 output operand. However, that exception can give rise to insns like
1759 which is a famous insn on the PDP-11 where the value of r3 used as the
1760 source was model-dependent. Avoid this sort of thing. */
1763 if (!(GET_CODE (PATTERN (i3)) == SET
1764 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1765 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1766 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1767 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1768 /* It's not the exception. */
1771 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1772 if (REG_NOTE_KIND (link) == REG_INC
1773 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1775 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1782 /* See if the SETs in I1 or I2 need to be kept around in the merged
1783 instruction: whenever the value set there is still needed past I3.
1784 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1786 For the SET in I1, we have two cases: If I1 and I2 independently
1787 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1788 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1789 in I1 needs to be kept around unless I1DEST dies or is set in either
1790 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1791 I1DEST. If so, we know I1 feeds into I2. */
1793 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1796 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1797 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1799 /* If the set in I2 needs to be kept around, we must make a copy of
1800 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1801 PATTERN (I2), we are only substituting for the original I1DEST, not into
1802 an already-substituted copy. This also prevents making self-referential
1803 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1806 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1807 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1811 i2pat = copy_rtx (i2pat);
1815 /* Substitute in the latest insn for the regs set by the earlier ones. */
1817 maxreg = max_reg_num ();
1821 /* It is possible that the source of I2 or I1 may be performing an
1822 unneeded operation, such as a ZERO_EXTEND of something that is known
1823 to have the high part zero. Handle that case by letting subst look at
1824 the innermost one of them.
1826 Another way to do this would be to have a function that tries to
1827 simplify a single insn instead of merging two or more insns. We don't
1828 do this because of the potential of infinite loops and because
1829 of the potential extra memory required. However, doing it the way
1830 we are is a bit of a kludge and doesn't catch all cases.
1832 But only do this if -fexpensive-optimizations since it slows things down
1833 and doesn't usually win. */
1835 if (flag_expensive_optimizations)
1837 /* Pass pc_rtx so no substitutions are done, just simplifications.
1838 The cases that we are interested in here do not involve the few
1839 cases were is_replaced is checked. */
1842 subst_low_cuid = INSN_CUID (i1);
1843 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1847 subst_low_cuid = INSN_CUID (i2);
1848 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1853 /* Many machines that don't use CC0 have insns that can both perform an
1854 arithmetic operation and set the condition code. These operations will
1855 be represented as a PARALLEL with the first element of the vector
1856 being a COMPARE of an arithmetic operation with the constant zero.
1857 The second element of the vector will set some pseudo to the result
1858 of the same arithmetic operation. If we simplify the COMPARE, we won't
1859 match such a pattern and so will generate an extra insn. Here we test
1860 for this case, where both the comparison and the operation result are
1861 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1862 I2SRC. Later we will make the PARALLEL that contains I2. */
1864 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1865 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1866 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1867 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1869 #ifdef EXTRA_CC_MODES
1871 enum machine_mode compare_mode;
1874 newpat = PATTERN (i3);
1875 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1879 #ifdef EXTRA_CC_MODES
1880 /* See if a COMPARE with the operand we substituted in should be done
1881 with the mode that is currently being used. If not, do the same
1882 processing we do in `subst' for a SET; namely, if the destination
1883 is used only once, try to replace it with a register of the proper
1884 mode and also replace the COMPARE. */
1885 if (undobuf.other_insn == 0
1886 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1887 &undobuf.other_insn))
1888 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1890 != GET_MODE (SET_DEST (newpat))))
1892 unsigned int regno = REGNO (SET_DEST (newpat));
1893 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1895 if (regno < FIRST_PSEUDO_REGISTER
1896 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1897 && ! REG_USERVAR_P (SET_DEST (newpat))))
1899 if (regno >= FIRST_PSEUDO_REGISTER)
1900 SUBST (regno_reg_rtx[regno], new_dest);
1902 SUBST (SET_DEST (newpat), new_dest);
1903 SUBST (XEXP (*cc_use, 0), new_dest);
1904 SUBST (SET_SRC (newpat),
1905 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1908 undobuf.other_insn = 0;
1915 n_occurrences = 0; /* `subst' counts here */
1917 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1918 need to make a unique copy of I2SRC each time we substitute it
1919 to avoid self-referential rtl. */
1921 subst_low_cuid = INSN_CUID (i2);
1922 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1923 ! i1_feeds_i3 && i1dest_in_i1src);
1926 /* Record whether i2's body now appears within i3's body. */
1927 i2_is_used = n_occurrences;
1930 /* If we already got a failure, don't try to do more. Otherwise,
1931 try to substitute in I1 if we have it. */
1933 if (i1 && GET_CODE (newpat) != CLOBBER)
1935 /* Before we can do this substitution, we must redo the test done
1936 above (see detailed comments there) that ensures that I1DEST
1937 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1939 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1947 subst_low_cuid = INSN_CUID (i1);
1948 newpat = subst (newpat, i1dest, i1src, 0, 0);
1952 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1953 to count all the ways that I2SRC and I1SRC can be used. */
1954 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1955 && i2_is_used + added_sets_2 > 1)
1956 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1957 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1959 /* Fail if we tried to make a new register (we used to abort, but there's
1960 really no reason to). */
1961 || max_reg_num () != maxreg
1962 /* Fail if we couldn't do something and have a CLOBBER. */
1963 || GET_CODE (newpat) == CLOBBER
1964 /* Fail if this new pattern is a MULT and we didn't have one before
1965 at the outer level. */
1966 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1973 /* If the actions of the earlier insns must be kept
1974 in addition to substituting them into the latest one,
1975 we must make a new PARALLEL for the latest insn
1976 to hold additional the SETs. */
1978 if (added_sets_1 || added_sets_2)
1982 if (GET_CODE (newpat) == PARALLEL)
1984 rtvec old = XVEC (newpat, 0);
1985 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1986 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1987 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
1988 sizeof (old->elem[0]) * old->num_elem);
1993 total_sets = 1 + added_sets_1 + added_sets_2;
1994 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1995 XVECEXP (newpat, 0, 0) = old;
1999 XVECEXP (newpat, 0, --total_sets)
2000 = (GET_CODE (PATTERN (i1)) == PARALLEL
2001 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2005 /* If there is no I1, use I2's body as is. We used to also not do
2006 the subst call below if I2 was substituted into I3,
2007 but that could lose a simplification. */
2009 XVECEXP (newpat, 0, --total_sets) = i2pat;
2011 /* See comment where i2pat is assigned. */
2012 XVECEXP (newpat, 0, --total_sets)
2013 = subst (i2pat, i1dest, i1src, 0, 0);
2017 /* We come here when we are replacing a destination in I2 with the
2018 destination of I3. */
2019 validate_replacement:
2021 /* Note which hard regs this insn has as inputs. */
2022 mark_used_regs_combine (newpat);
2024 /* Is the result of combination a valid instruction? */
2025 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2027 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2028 the second SET's destination is a register that is unused. In that case,
2029 we just need the first SET. This can occur when simplifying a divmod
2030 insn. We *must* test for this case here because the code below that
2031 splits two independent SETs doesn't handle this case correctly when it
2032 updates the register status. Also check the case where the first
2033 SET's destination is unused. That would not cause incorrect code, but
2034 does cause an unneeded insn to remain. */
2036 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2037 && XVECLEN (newpat, 0) == 2
2038 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2039 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2040 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2041 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2042 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2043 && asm_noperands (newpat) < 0)
2045 newpat = XVECEXP (newpat, 0, 0);
2046 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2049 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2050 && XVECLEN (newpat, 0) == 2
2051 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2052 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2053 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2054 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2055 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2056 && asm_noperands (newpat) < 0)
2058 newpat = XVECEXP (newpat, 0, 1);
2059 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2062 /* If we were combining three insns and the result is a simple SET
2063 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2064 insns. There are two ways to do this. It can be split using a
2065 machine-specific method (like when you have an addition of a large
2066 constant) or by combine in the function find_split_point. */
2068 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2069 && asm_noperands (newpat) < 0)
2071 rtx m_split, *split;
2072 rtx ni2dest = i2dest;
2074 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2075 use I2DEST as a scratch register will help. In the latter case,
2076 convert I2DEST to the mode of the source of NEWPAT if we can. */
2078 m_split = split_insns (newpat, i3);
2080 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2081 inputs of NEWPAT. */
2083 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2084 possible to try that as a scratch reg. This would require adding
2085 more code to make it work though. */
2087 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2089 /* If I2DEST is a hard register or the only use of a pseudo,
2090 we can change its mode. */
2091 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2092 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2093 && GET_CODE (i2dest) == REG
2094 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2095 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2096 && ! REG_USERVAR_P (i2dest))))
2097 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2100 m_split = split_insns (gen_rtx_PARALLEL
2102 gen_rtvec (2, newpat,
2103 gen_rtx_CLOBBER (VOIDmode,
2106 /* If the split with the mode-changed register didn't work, try
2107 the original register. */
2108 if (! m_split && ni2dest != i2dest)
2111 m_split = split_insns (gen_rtx_PARALLEL
2113 gen_rtvec (2, newpat,
2114 gen_rtx_CLOBBER (VOIDmode,
2120 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2122 m_split = PATTERN (m_split);
2123 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2124 if (insn_code_number >= 0)
2127 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2128 && (next_real_insn (i2) == i3
2129 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2132 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2133 newi2pat = PATTERN (m_split);
2135 i3set = single_set (NEXT_INSN (m_split));
2136 i2set = single_set (m_split);
2138 /* In case we changed the mode of I2DEST, replace it in the
2139 pseudo-register table here. We can't do it above in case this
2140 code doesn't get executed and we do a split the other way. */
2142 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2143 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2145 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2147 /* If I2 or I3 has multiple SETs, we won't know how to track
2148 register status, so don't use these insns. If I2's destination
2149 is used between I2 and I3, we also can't use these insns. */
2151 if (i2_code_number >= 0 && i2set && i3set
2152 && (next_real_insn (i2) == i3
2153 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2154 insn_code_number = recog_for_combine (&newi3pat, i3,
2156 if (insn_code_number >= 0)
2159 /* It is possible that both insns now set the destination of I3.
2160 If so, we must show an extra use of it. */
2162 if (insn_code_number >= 0)
2164 rtx new_i3_dest = SET_DEST (i3set);
2165 rtx new_i2_dest = SET_DEST (i2set);
2167 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2168 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2169 || GET_CODE (new_i3_dest) == SUBREG)
2170 new_i3_dest = XEXP (new_i3_dest, 0);
2172 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2173 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2174 || GET_CODE (new_i2_dest) == SUBREG)
2175 new_i2_dest = XEXP (new_i2_dest, 0);
2177 if (GET_CODE (new_i3_dest) == REG
2178 && GET_CODE (new_i2_dest) == REG
2179 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2180 REG_N_SETS (REGNO (new_i2_dest))++;
2184 /* If we can split it and use I2DEST, go ahead and see if that
2185 helps things be recognized. Verify that none of the registers
2186 are set between I2 and I3. */
2187 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2189 && GET_CODE (i2dest) == REG
2191 /* We need I2DEST in the proper mode. If it is a hard register
2192 or the only use of a pseudo, we can change its mode. */
2193 && (GET_MODE (*split) == GET_MODE (i2dest)
2194 || GET_MODE (*split) == VOIDmode
2195 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2196 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2197 && ! REG_USERVAR_P (i2dest)))
2198 && (next_real_insn (i2) == i3
2199 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2200 /* We can't overwrite I2DEST if its value is still used by
2202 && ! reg_referenced_p (i2dest, newpat))
2204 rtx newdest = i2dest;
2205 enum rtx_code split_code = GET_CODE (*split);
2206 enum machine_mode split_mode = GET_MODE (*split);
2208 /* Get NEWDEST as a register in the proper mode. We have already
2209 validated that we can do this. */
2210 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2212 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2214 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2215 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2218 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2219 an ASHIFT. This can occur if it was inside a PLUS and hence
2220 appeared to be a memory address. This is a kludge. */
2221 if (split_code == MULT
2222 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2223 && INTVAL (XEXP (*split, 1)) > 0
2224 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2226 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2227 XEXP (*split, 0), GEN_INT (i)));
2228 /* Update split_code because we may not have a multiply
2230 split_code = GET_CODE (*split);
2233 #ifdef INSN_SCHEDULING
2234 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2235 be written as a ZERO_EXTEND. */
2236 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2238 #ifdef LOAD_EXTEND_OP
2239 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2240 what it really is. */
2241 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2243 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2244 SUBREG_REG (*split)));
2247 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2248 SUBREG_REG (*split)));
2252 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2253 SUBST (*split, newdest);
2254 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2256 /* If the split point was a MULT and we didn't have one before,
2257 don't use one now. */
2258 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2259 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2263 /* Check for a case where we loaded from memory in a narrow mode and
2264 then sign extended it, but we need both registers. In that case,
2265 we have a PARALLEL with both loads from the same memory location.
2266 We can split this into a load from memory followed by a register-register
2267 copy. This saves at least one insn, more if register allocation can
2270 We cannot do this if the destination of the first assignment is a
2271 condition code register or cc0. We eliminate this case by making sure
2272 the SET_DEST and SET_SRC have the same mode.
2274 We cannot do this if the destination of the second assignment is
2275 a register that we have already assumed is zero-extended. Similarly
2276 for a SUBREG of such a register. */
2278 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2279 && GET_CODE (newpat) == PARALLEL
2280 && XVECLEN (newpat, 0) == 2
2281 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2282 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2283 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2284 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2285 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2286 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2287 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2288 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2290 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2291 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2292 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2293 (GET_CODE (temp) == REG
2294 && reg_nonzero_bits[REGNO (temp)] != 0
2295 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2296 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2297 && (reg_nonzero_bits[REGNO (temp)]
2298 != GET_MODE_MASK (word_mode))))
2299 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2300 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2301 (GET_CODE (temp) == REG
2302 && reg_nonzero_bits[REGNO (temp)] != 0
2303 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2304 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2305 && (reg_nonzero_bits[REGNO (temp)]
2306 != GET_MODE_MASK (word_mode)))))
2307 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2308 SET_SRC (XVECEXP (newpat, 0, 1)))
2309 && ! find_reg_note (i3, REG_UNUSED,
2310 SET_DEST (XVECEXP (newpat, 0, 0))))
2314 newi2pat = XVECEXP (newpat, 0, 0);
2315 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2316 newpat = XVECEXP (newpat, 0, 1);
2317 SUBST (SET_SRC (newpat),
2318 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2319 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2321 if (i2_code_number >= 0)
2322 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2324 if (insn_code_number >= 0)
2329 /* If we will be able to accept this, we have made a change to the
2330 destination of I3. This can invalidate a LOG_LINKS pointing
2331 to I3. No other part of combine.c makes such a transformation.
2333 The new I3 will have a destination that was previously the
2334 destination of I1 or I2 and which was used in i2 or I3. Call
2335 distribute_links to make a LOG_LINK from the next use of
2336 that destination. */
2338 PATTERN (i3) = newpat;
2339 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2341 /* I3 now uses what used to be its destination and which is
2342 now I2's destination. That means we need a LOG_LINK from
2343 I3 to I2. But we used to have one, so we still will.
2345 However, some later insn might be using I2's dest and have
2346 a LOG_LINK pointing at I3. We must remove this link.
2347 The simplest way to remove the link is to point it at I1,
2348 which we know will be a NOTE. */
2350 for (insn = NEXT_INSN (i3);
2351 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2352 || insn != this_basic_block->next_bb->head);
2353 insn = NEXT_INSN (insn))
2355 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2357 for (link = LOG_LINKS (insn); link;
2358 link = XEXP (link, 1))
2359 if (XEXP (link, 0) == i3)
2360 XEXP (link, 0) = i1;
2368 /* Similarly, check for a case where we have a PARALLEL of two independent
2369 SETs but we started with three insns. In this case, we can do the sets
2370 as two separate insns. This case occurs when some SET allows two
2371 other insns to combine, but the destination of that SET is still live. */
2373 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2374 && GET_CODE (newpat) == PARALLEL
2375 && XVECLEN (newpat, 0) == 2
2376 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2379 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2380 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2381 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2382 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2384 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2385 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2386 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2387 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2388 XVECEXP (newpat, 0, 0))
2389 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2390 XVECEXP (newpat, 0, 1))
2391 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2392 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2394 /* Normally, it doesn't matter which of the two is done first,
2395 but it does if one references cc0. In that case, it has to
2398 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2400 newi2pat = XVECEXP (newpat, 0, 0);
2401 newpat = XVECEXP (newpat, 0, 1);
2406 newi2pat = XVECEXP (newpat, 0, 1);
2407 newpat = XVECEXP (newpat, 0, 0);
2410 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2412 if (i2_code_number >= 0)
2413 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2416 /* If it still isn't recognized, fail and change things back the way they
2418 if ((insn_code_number < 0
2419 /* Is the result a reasonable ASM_OPERANDS? */
2420 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2426 /* If we had to change another insn, make sure it is valid also. */
2427 if (undobuf.other_insn)
2429 rtx other_pat = PATTERN (undobuf.other_insn);
2430 rtx new_other_notes;
2433 CLEAR_HARD_REG_SET (newpat_used_regs);
2435 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2438 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2444 PATTERN (undobuf.other_insn) = other_pat;
2446 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2447 are still valid. Then add any non-duplicate notes added by
2448 recog_for_combine. */
2449 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2451 next = XEXP (note, 1);
2453 if (REG_NOTE_KIND (note) == REG_UNUSED
2454 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2456 if (GET_CODE (XEXP (note, 0)) == REG)
2457 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2459 remove_note (undobuf.other_insn, note);
2463 for (note = new_other_notes; note; note = XEXP (note, 1))
2464 if (GET_CODE (XEXP (note, 0)) == REG)
2465 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2467 distribute_notes (new_other_notes, undobuf.other_insn,
2468 undobuf.other_insn, NULL_RTX);
2471 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2472 they are adjacent to each other or not. */
2474 rtx p = prev_nonnote_insn (i3);
2475 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2476 && sets_cc0_p (newi2pat))
2484 /* We now know that we can do this combination. Merge the insns and
2485 update the status of registers and LOG_LINKS. */
2488 rtx i3notes, i2notes, i1notes = 0;
2489 rtx i3links, i2links, i1links = 0;
2493 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2495 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2496 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2498 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2500 /* Ensure that we do not have something that should not be shared but
2501 occurs multiple times in the new insns. Check this by first
2502 resetting all the `used' flags and then copying anything is shared. */
2504 reset_used_flags (i3notes);
2505 reset_used_flags (i2notes);
2506 reset_used_flags (i1notes);
2507 reset_used_flags (newpat);
2508 reset_used_flags (newi2pat);
2509 if (undobuf.other_insn)
2510 reset_used_flags (PATTERN (undobuf.other_insn));
2512 i3notes = copy_rtx_if_shared (i3notes);
2513 i2notes = copy_rtx_if_shared (i2notes);
2514 i1notes = copy_rtx_if_shared (i1notes);
2515 newpat = copy_rtx_if_shared (newpat);
2516 newi2pat = copy_rtx_if_shared (newi2pat);
2517 if (undobuf.other_insn)
2518 reset_used_flags (PATTERN (undobuf.other_insn));
2520 INSN_CODE (i3) = insn_code_number;
2521 PATTERN (i3) = newpat;
2523 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2525 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2527 reset_used_flags (call_usage);
2528 call_usage = copy_rtx (call_usage);
2531 replace_rtx (call_usage, i2dest, i2src);
2534 replace_rtx (call_usage, i1dest, i1src);
2536 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2539 if (undobuf.other_insn)
2540 INSN_CODE (undobuf.other_insn) = other_code_number;
2542 /* We had one special case above where I2 had more than one set and
2543 we replaced a destination of one of those sets with the destination
2544 of I3. In that case, we have to update LOG_LINKS of insns later
2545 in this basic block. Note that this (expensive) case is rare.
2547 Also, in this case, we must pretend that all REG_NOTEs for I2
2548 actually came from I3, so that REG_UNUSED notes from I2 will be
2549 properly handled. */
2551 if (i3_subst_into_i2)
2553 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2554 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2555 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2556 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2557 && ! find_reg_note (i2, REG_UNUSED,
2558 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2559 for (temp = NEXT_INSN (i2);
2560 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2561 || this_basic_block->head != temp);
2562 temp = NEXT_INSN (temp))
2563 if (temp != i3 && INSN_P (temp))
2564 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2565 if (XEXP (link, 0) == i2)
2566 XEXP (link, 0) = i3;
2571 while (XEXP (link, 1))
2572 link = XEXP (link, 1);
2573 XEXP (link, 1) = i2notes;
2587 INSN_CODE (i2) = i2_code_number;
2588 PATTERN (i2) = newi2pat;
2592 PUT_CODE (i2, NOTE);
2593 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2594 NOTE_SOURCE_FILE (i2) = 0;
2601 PUT_CODE (i1, NOTE);
2602 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2603 NOTE_SOURCE_FILE (i1) = 0;
2606 /* Get death notes for everything that is now used in either I3 or
2607 I2 and used to die in a previous insn. If we built two new
2608 patterns, move from I1 to I2 then I2 to I3 so that we get the
2609 proper movement on registers that I2 modifies. */
2613 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2614 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2617 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2620 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2622 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2624 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2626 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2628 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2630 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2631 know these are REG_UNUSED and want them to go to the desired insn,
2632 so we always pass it as i3. We have not counted the notes in
2633 reg_n_deaths yet, so we need to do so now. */
2635 if (newi2pat && new_i2_notes)
2637 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2638 if (GET_CODE (XEXP (temp, 0)) == REG)
2639 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2641 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2646 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2647 if (GET_CODE (XEXP (temp, 0)) == REG)
2648 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2650 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2653 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2654 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2655 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2656 in that case, it might delete I2. Similarly for I2 and I1.
2657 Show an additional death due to the REG_DEAD note we make here. If
2658 we discard it in distribute_notes, we will decrement it again. */
2662 if (GET_CODE (i3dest_killed) == REG)
2663 REG_N_DEATHS (REGNO (i3dest_killed))++;
2665 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2668 NULL_RTX, i2, NULL_RTX);
2670 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2672 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2675 if (i2dest_in_i2src)
2677 if (GET_CODE (i2dest) == REG)
2678 REG_N_DEATHS (REGNO (i2dest))++;
2680 if (newi2pat && reg_set_p (i2dest, newi2pat))
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2682 NULL_RTX, i2, NULL_RTX);
2684 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2685 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2688 if (i1dest_in_i1src)
2690 if (GET_CODE (i1dest) == REG)
2691 REG_N_DEATHS (REGNO (i1dest))++;
2693 if (newi2pat && reg_set_p (i1dest, newi2pat))
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2695 NULL_RTX, i2, NULL_RTX);
2697 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2698 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2701 distribute_links (i3links);
2702 distribute_links (i2links);
2703 distribute_links (i1links);
2705 if (GET_CODE (i2dest) == REG)
2708 rtx i2_insn = 0, i2_val = 0, set;
2710 /* The insn that used to set this register doesn't exist, and
2711 this life of the register may not exist either. See if one of
2712 I3's links points to an insn that sets I2DEST. If it does,
2713 that is now the last known value for I2DEST. If we don't update
2714 this and I2 set the register to a value that depended on its old
2715 contents, we will get confused. If this insn is used, thing
2716 will be set correctly in combine_instructions. */
2718 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2719 if ((set = single_set (XEXP (link, 0))) != 0
2720 && rtx_equal_p (i2dest, SET_DEST (set)))
2721 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2723 record_value_for_reg (i2dest, i2_insn, i2_val);
2725 /* If the reg formerly set in I2 died only once and that was in I3,
2726 zero its use count so it won't make `reload' do any work. */
2728 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2729 && ! i2dest_in_i2src)
2731 regno = REGNO (i2dest);
2732 REG_N_SETS (regno)--;
2736 if (i1 && GET_CODE (i1dest) == REG)
2739 rtx i1_insn = 0, i1_val = 0, set;
2741 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2742 if ((set = single_set (XEXP (link, 0))) != 0
2743 && rtx_equal_p (i1dest, SET_DEST (set)))
2744 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2746 record_value_for_reg (i1dest, i1_insn, i1_val);
2748 regno = REGNO (i1dest);
2749 if (! added_sets_1 && ! i1dest_in_i1src)
2750 REG_N_SETS (regno)--;
2753 /* Update reg_nonzero_bits et al for any changes that may have been made
2754 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2755 important. Because newi2pat can affect nonzero_bits of newpat */
2757 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2758 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2760 /* Set new_direct_jump_p if a new return or simple jump instruction
2763 If I3 is now an unconditional jump, ensure that it has a
2764 BARRIER following it since it may have initially been a
2765 conditional jump. It may also be the last nonnote insn. */
2767 if (returnjump_p (i3) || any_uncondjump_p (i3))
2769 *new_direct_jump_p = 1;
2770 mark_jump_label (PATTERN (i3), i3, 0);
2772 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2773 || GET_CODE (temp) != BARRIER)
2774 emit_barrier_after (i3);
2777 if (undobuf.other_insn != NULL_RTX
2778 && (returnjump_p (undobuf.other_insn)
2779 || any_uncondjump_p (undobuf.other_insn)))
2781 *new_direct_jump_p = 1;
2783 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2784 || GET_CODE (temp) != BARRIER)
2785 emit_barrier_after (undobuf.other_insn);
2788 /* An NOOP jump does not need barrier, but it does need cleaning up
2790 if (GET_CODE (newpat) == SET
2791 && SET_SRC (newpat) == pc_rtx
2792 && SET_DEST (newpat) == pc_rtx)
2793 *new_direct_jump_p = 1;
2796 combine_successes++;
2799 if (added_links_insn
2800 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2801 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2802 return added_links_insn;
2804 return newi2pat ? i2 : i3;
2807 /* Undo all the modifications recorded in undobuf. */
2812 struct undo *undo, *next;
2814 for (undo = undobuf.undos; undo; undo = next)
2818 *undo->where.i = undo->old_contents.i;
2820 *undo->where.r = undo->old_contents.r;
2822 undo->next = undobuf.frees;
2823 undobuf.frees = undo;
2829 /* We've committed to accepting the changes we made. Move all
2830 of the undos to the free list. */
2835 struct undo *undo, *next;
2837 for (undo = undobuf.undos; undo; undo = next)
2840 undo->next = undobuf.frees;
2841 undobuf.frees = undo;
2847 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2848 where we have an arithmetic expression and return that point. LOC will
2851 try_combine will call this function to see if an insn can be split into
2855 find_split_point (rtx *loc, rtx insn)
2858 enum rtx_code code = GET_CODE (x);
2860 unsigned HOST_WIDE_INT len = 0;
2861 HOST_WIDE_INT pos = 0;
2863 rtx inner = NULL_RTX;
2865 /* First special-case some codes. */
2869 #ifdef INSN_SCHEDULING
2870 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2872 if (GET_CODE (SUBREG_REG (x)) == MEM)
2875 return find_split_point (&SUBREG_REG (x), insn);
2879 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2880 using LO_SUM and HIGH. */
2881 if (GET_CODE (XEXP (x, 0)) == CONST
2882 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2885 gen_rtx_LO_SUM (Pmode,
2886 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2888 return &XEXP (XEXP (x, 0), 0);
2892 /* If we have a PLUS whose second operand is a constant and the
2893 address is not valid, perhaps will can split it up using
2894 the machine-specific way to split large constants. We use
2895 the first pseudo-reg (one of the virtual regs) as a placeholder;
2896 it will not remain in the result. */
2897 if (GET_CODE (XEXP (x, 0)) == PLUS
2898 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2899 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2901 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2902 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2905 /* This should have produced two insns, each of which sets our
2906 placeholder. If the source of the second is a valid address,
2907 we can make put both sources together and make a split point
2911 && NEXT_INSN (seq) != NULL_RTX
2912 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2913 && GET_CODE (seq) == INSN
2914 && GET_CODE (PATTERN (seq)) == SET
2915 && SET_DEST (PATTERN (seq)) == reg
2916 && ! reg_mentioned_p (reg,
2917 SET_SRC (PATTERN (seq)))
2918 && GET_CODE (NEXT_INSN (seq)) == INSN
2919 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2920 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2921 && memory_address_p (GET_MODE (x),
2922 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2924 rtx src1 = SET_SRC (PATTERN (seq));
2925 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2927 /* Replace the placeholder in SRC2 with SRC1. If we can
2928 find where in SRC2 it was placed, that can become our
2929 split point and we can replace this address with SRC2.
2930 Just try two obvious places. */
2932 src2 = replace_rtx (src2, reg, src1);
2934 if (XEXP (src2, 0) == src1)
2935 split = &XEXP (src2, 0);
2936 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2937 && XEXP (XEXP (src2, 0), 0) == src1)
2938 split = &XEXP (XEXP (src2, 0), 0);
2942 SUBST (XEXP (x, 0), src2);
2947 /* If that didn't work, perhaps the first operand is complex and
2948 needs to be computed separately, so make a split point there.
2949 This will occur on machines that just support REG + CONST
2950 and have a constant moved through some previous computation. */
2952 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2953 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2954 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2956 return &XEXP (XEXP (x, 0), 0);
2962 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2963 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2964 we need to put the operand into a register. So split at that
2967 if (SET_DEST (x) == cc0_rtx
2968 && GET_CODE (SET_SRC (x)) != COMPARE
2969 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2970 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2971 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2972 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2973 return &SET_SRC (x);
2976 /* See if we can split SET_SRC as it stands. */
2977 split = find_split_point (&SET_SRC (x), insn);
2978 if (split && split != &SET_SRC (x))
2981 /* See if we can split SET_DEST as it stands. */
2982 split = find_split_point (&SET_DEST (x), insn);
2983 if (split && split != &SET_DEST (x))
2986 /* See if this is a bitfield assignment with everything constant. If
2987 so, this is an IOR of an AND, so split it into that. */
2988 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2989 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2990 <= HOST_BITS_PER_WIDE_INT)
2991 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2992 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2993 && GET_CODE (SET_SRC (x)) == CONST_INT
2994 && ((INTVAL (XEXP (SET_DEST (x), 1))
2995 + INTVAL (XEXP (SET_DEST (x), 2)))
2996 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2997 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2999 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3000 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3001 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3002 rtx dest = XEXP (SET_DEST (x), 0);
3003 enum machine_mode mode = GET_MODE (dest);
3004 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3006 if (BITS_BIG_ENDIAN)
3007 pos = GET_MODE_BITSIZE (mode) - len - pos;
3011 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3014 gen_binary (IOR, mode,
3015 gen_binary (AND, mode, dest,
3016 gen_int_mode (~(mask << pos),
3018 GEN_INT (src << pos)));
3020 SUBST (SET_DEST (x), dest);
3022 split = find_split_point (&SET_SRC (x), insn);
3023 if (split && split != &SET_SRC (x))
3027 /* Otherwise, see if this is an operation that we can split into two.
3028 If so, try to split that. */
3029 code = GET_CODE (SET_SRC (x));
3034 /* If we are AND'ing with a large constant that is only a single
3035 bit and the result is only being used in a context where we
3036 need to know if it is zero or nonzero, replace it with a bit
3037 extraction. This will avoid the large constant, which might
3038 have taken more than one insn to make. If the constant were
3039 not a valid argument to the AND but took only one insn to make,
3040 this is no worse, but if it took more than one insn, it will
3043 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3044 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3045 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3046 && GET_CODE (SET_DEST (x)) == REG
3047 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3048 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3049 && XEXP (*split, 0) == SET_DEST (x)
3050 && XEXP (*split, 1) == const0_rtx)
3052 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3053 XEXP (SET_SRC (x), 0),
3054 pos, NULL_RTX, 1, 1, 0, 0);
3055 if (extraction != 0)
3057 SUBST (SET_SRC (x), extraction);
3058 return find_split_point (loc, insn);
3064 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3065 is known to be on, this can be converted into a NEG of a shift. */
3066 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3067 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3068 && 1 <= (pos = exact_log2
3069 (nonzero_bits (XEXP (SET_SRC (x), 0),
3070 GET_MODE (XEXP (SET_SRC (x), 0))))))
3072 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3076 gen_rtx_LSHIFTRT (mode,
3077 XEXP (SET_SRC (x), 0),
3080 split = find_split_point (&SET_SRC (x), insn);
3081 if (split && split != &SET_SRC (x))
3087 inner = XEXP (SET_SRC (x), 0);
3089 /* We can't optimize if either mode is a partial integer
3090 mode as we don't know how many bits are significant
3092 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3093 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3097 len = GET_MODE_BITSIZE (GET_MODE (inner));
3103 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3104 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3106 inner = XEXP (SET_SRC (x), 0);
3107 len = INTVAL (XEXP (SET_SRC (x), 1));
3108 pos = INTVAL (XEXP (SET_SRC (x), 2));
3110 if (BITS_BIG_ENDIAN)
3111 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3112 unsignedp = (code == ZERO_EXTRACT);
3120 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3122 enum machine_mode mode = GET_MODE (SET_SRC (x));
3124 /* For unsigned, we have a choice of a shift followed by an
3125 AND or two shifts. Use two shifts for field sizes where the
3126 constant might be too large. We assume here that we can
3127 always at least get 8-bit constants in an AND insn, which is
3128 true for every current RISC. */
3130 if (unsignedp && len <= 8)
3135 (mode, gen_lowpart_for_combine (mode, inner),
3137 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3139 split = find_split_point (&SET_SRC (x), insn);
3140 if (split && split != &SET_SRC (x))
3147 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3148 gen_rtx_ASHIFT (mode,
3149 gen_lowpart_for_combine (mode, inner),
3150 GEN_INT (GET_MODE_BITSIZE (mode)
3152 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3154 split = find_split_point (&SET_SRC (x), insn);
3155 if (split && split != &SET_SRC (x))
3160 /* See if this is a simple operation with a constant as the second
3161 operand. It might be that this constant is out of range and hence
3162 could be used as a split point. */
3163 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3165 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3166 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3167 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3168 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3169 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3171 return &XEXP (SET_SRC (x), 1);
3173 /* Finally, see if this is a simple operation with its first operand
3174 not in a register. The operation might require this operand in a
3175 register, so return it as a split point. We can always do this
3176 because if the first operand were another operation, we would have
3177 already found it as a split point. */
3178 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3179 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3182 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3183 return &XEXP (SET_SRC (x), 0);
3189 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3190 it is better to write this as (not (ior A B)) so we can split it.
3191 Similarly for IOR. */
3192 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3195 gen_rtx_NOT (GET_MODE (x),
3196 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3198 XEXP (XEXP (x, 0), 0),
3199 XEXP (XEXP (x, 1), 0))));
3200 return find_split_point (loc, insn);
3203 /* Many RISC machines have a large set of logical insns. If the
3204 second operand is a NOT, put it first so we will try to split the
3205 other operand first. */
3206 if (GET_CODE (XEXP (x, 1)) == NOT)
3208 rtx tem = XEXP (x, 0);
3209 SUBST (XEXP (x, 0), XEXP (x, 1));
3210 SUBST (XEXP (x, 1), tem);
3218 /* Otherwise, select our actions depending on our rtx class. */
3219 switch (GET_RTX_CLASS (code))
3221 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3223 split = find_split_point (&XEXP (x, 2), insn);
3226 /* ... fall through ... */
3230 split = find_split_point (&XEXP (x, 1), insn);
3233 /* ... fall through ... */
3235 /* Some machines have (and (shift ...) ...) insns. If X is not
3236 an AND, but XEXP (X, 0) is, use it as our split point. */
3237 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3238 return &XEXP (x, 0);
3240 split = find_split_point (&XEXP (x, 0), insn);
3246 /* Otherwise, we don't have a split point. */
3250 /* Throughout X, replace FROM with TO, and return the result.
3251 The result is TO if X is FROM;
3252 otherwise the result is X, but its contents may have been modified.
3253 If they were modified, a record was made in undobuf so that
3254 undo_all will (among other things) return X to its original state.
3256 If the number of changes necessary is too much to record to undo,
3257 the excess changes are not made, so the result is invalid.
3258 The changes already made can still be undone.
3259 undobuf.num_undo is incremented for such changes, so by testing that
3260 the caller can tell whether the result is valid.
3262 `n_occurrences' is incremented each time FROM is replaced.
3264 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3266 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3267 by copying if `n_occurrences' is nonzero. */
3270 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3272 enum rtx_code code = GET_CODE (x);
3273 enum machine_mode op0_mode = VOIDmode;
3278 /* Two expressions are equal if they are identical copies of a shared
3279 RTX or if they are both registers with the same register number
3282 #define COMBINE_RTX_EQUAL_P(X,Y) \
3284 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3285 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3287 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3290 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3293 /* If X and FROM are the same register but different modes, they will
3294 not have been seen as equal above. However, flow.c will make a
3295 LOG_LINKS entry for that case. If we do nothing, we will try to
3296 rerecognize our original insn and, when it succeeds, we will
3297 delete the feeding insn, which is incorrect.
3299 So force this insn not to match in this (rare) case. */
3300 if (! in_dest && code == REG && GET_CODE (from) == REG
3301 && REGNO (x) == REGNO (from))
3302 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3304 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3305 of which may contain things that can be combined. */
3306 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3309 /* It is possible to have a subexpression appear twice in the insn.
3310 Suppose that FROM is a register that appears within TO.
3311 Then, after that subexpression has been scanned once by `subst',
3312 the second time it is scanned, TO may be found. If we were
3313 to scan TO here, we would find FROM within it and create a
3314 self-referent rtl structure which is completely wrong. */
3315 if (COMBINE_RTX_EQUAL_P (x, to))
3318 /* Parallel asm_operands need special attention because all of the
3319 inputs are shared across the arms. Furthermore, unsharing the
3320 rtl results in recognition failures. Failure to handle this case
3321 specially can result in circular rtl.
3323 Solve this by doing a normal pass across the first entry of the
3324 parallel, and only processing the SET_DESTs of the subsequent
3327 if (code == PARALLEL
3328 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3329 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3331 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3333 /* If this substitution failed, this whole thing fails. */
3334 if (GET_CODE (new) == CLOBBER
3335 && XEXP (new, 0) == const0_rtx)
3338 SUBST (XVECEXP (x, 0, 0), new);
3340 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3342 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3344 if (GET_CODE (dest) != REG
3345 && GET_CODE (dest) != CC0
3346 && GET_CODE (dest) != PC)
3348 new = subst (dest, from, to, 0, unique_copy);
3350 /* If this substitution failed, this whole thing fails. */
3351 if (GET_CODE (new) == CLOBBER
3352 && XEXP (new, 0) == const0_rtx)
3355 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3361 len = GET_RTX_LENGTH (code);
3362 fmt = GET_RTX_FORMAT (code);
3364 /* We don't need to process a SET_DEST that is a register, CC0,
3365 or PC, so set up to skip this common case. All other cases
3366 where we want to suppress replacing something inside a
3367 SET_SRC are handled via the IN_DEST operand. */
3369 && (GET_CODE (SET_DEST (x)) == REG
3370 || GET_CODE (SET_DEST (x)) == CC0
3371 || GET_CODE (SET_DEST (x)) == PC))
3374 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3377 op0_mode = GET_MODE (XEXP (x, 0));
3379 for (i = 0; i < len; i++)
3384 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3386 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3388 new = (unique_copy && n_occurrences
3389 ? copy_rtx (to) : to);
3394 new = subst (XVECEXP (x, i, j), from, to, 0,
3397 /* If this substitution failed, this whole thing
3399 if (GET_CODE (new) == CLOBBER
3400 && XEXP (new, 0) == const0_rtx)
3404 SUBST (XVECEXP (x, i, j), new);
3407 else if (fmt[i] == 'e')
3409 /* If this is a register being set, ignore it. */
3412 && (code == SUBREG || code == STRICT_LOW_PART
3413 || code == ZERO_EXTRACT)
3415 && GET_CODE (new) == REG)
3418 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3420 /* In general, don't install a subreg involving two
3421 modes not tieable. It can worsen register
3422 allocation, and can even make invalid reload
3423 insns, since the reg inside may need to be copied
3424 from in the outside mode, and that may be invalid
3425 if it is an fp reg copied in integer mode.
3427 We allow two exceptions to this: It is valid if
3428 it is inside another SUBREG and the mode of that
3429 SUBREG and the mode of the inside of TO is
3430 tieable and it is valid if X is a SET that copies
3433 if (GET_CODE (to) == SUBREG
3434 && ! MODES_TIEABLE_P (GET_MODE (to),
3435 GET_MODE (SUBREG_REG (to)))
3436 && ! (code == SUBREG
3437 && MODES_TIEABLE_P (GET_MODE (x),
3438 GET_MODE (SUBREG_REG (to))))
3440 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3443 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3445 #ifdef CANNOT_CHANGE_MODE_CLASS
3447 && GET_CODE (to) == REG
3448 && REGNO (to) < FIRST_PSEUDO_REGISTER
3449 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3452 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3455 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3459 /* If we are in a SET_DEST, suppress most cases unless we
3460 have gone inside a MEM, in which case we want to
3461 simplify the address. We assume here that things that
3462 are actually part of the destination have their inner
3463 parts in the first expression. This is true for SUBREG,
3464 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3465 things aside from REG and MEM that should appear in a
3467 new = subst (XEXP (x, i), from, to,
3469 && (code == SUBREG || code == STRICT_LOW_PART
3470 || code == ZERO_EXTRACT))
3472 && i == 0), unique_copy);
3474 /* If we found that we will have to reject this combination,
3475 indicate that by returning the CLOBBER ourselves, rather than
3476 an expression containing it. This will speed things up as
3477 well as prevent accidents where two CLOBBERs are considered
3478 to be equal, thus producing an incorrect simplification. */
3480 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3483 if (GET_CODE (x) == SUBREG
3484 && (GET_CODE (new) == CONST_INT
3485 || GET_CODE (new) == CONST_DOUBLE))
3487 enum machine_mode mode = GET_MODE (x);
3489 x = simplify_subreg (GET_MODE (x), new,
3490 GET_MODE (SUBREG_REG (x)),
3493 x = gen_rtx_CLOBBER (mode, const0_rtx);
3495 else if (GET_CODE (new) == CONST_INT
3496 && GET_CODE (x) == ZERO_EXTEND)
3498 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3499 new, GET_MODE (XEXP (x, 0)));
3504 SUBST (XEXP (x, i), new);
3509 /* Try to simplify X. If the simplification changed the code, it is likely
3510 that further simplification will help, so loop, but limit the number
3511 of repetitions that will be performed. */
3513 for (i = 0; i < 4; i++)
3515 /* If X is sufficiently simple, don't bother trying to do anything
3517 if (code != CONST_INT && code != REG && code != CLOBBER)
3518 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3520 if (GET_CODE (x) == code)
3523 code = GET_CODE (x);
3525 /* We no longer know the original mode of operand 0 since we
3526 have changed the form of X) */
3527 op0_mode = VOIDmode;
3533 /* Simplify X, a piece of RTL. We just operate on the expression at the
3534 outer level; call `subst' to simplify recursively. Return the new
3537 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3538 will be the iteration even if an expression with a code different from
3539 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3542 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int last,
3545 enum rtx_code code = GET_CODE (x);
3546 enum machine_mode mode = GET_MODE (x);
3551 /* If this is a commutative operation, put a constant last and a complex
3552 expression first. We don't need to do this for comparisons here. */
3553 if (GET_RTX_CLASS (code) == 'c'
3554 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3557 SUBST (XEXP (x, 0), XEXP (x, 1));
3558 SUBST (XEXP (x, 1), temp);
3561 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3562 sign extension of a PLUS with a constant, reverse the order of the sign
3563 extension and the addition. Note that this not the same as the original
3564 code, but overflow is undefined for signed values. Also note that the
3565 PLUS will have been partially moved "inside" the sign-extension, so that
3566 the first operand of X will really look like:
3567 (ashiftrt (plus (ashift A C4) C5) C4).
3569 (plus (ashiftrt (ashift A C4) C2) C4)
3570 and replace the first operand of X with that expression. Later parts
3571 of this function may simplify the expression further.
3573 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3574 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3575 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3577 We do this to simplify address expressions. */
3579 if ((code == PLUS || code == MINUS || code == MULT)
3580 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3581 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3582 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3583 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3584 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3585 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3586 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3587 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3588 XEXP (XEXP (XEXP (x, 0), 0), 1),
3589 XEXP (XEXP (x, 0), 1))) != 0)
3592 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3593 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3594 INTVAL (XEXP (XEXP (x, 0), 1)));
3596 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3597 INTVAL (XEXP (XEXP (x, 0), 1)));
3599 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3602 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3603 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3604 things. Check for cases where both arms are testing the same
3607 Don't do anything if all operands are very simple. */
3609 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3610 || GET_RTX_CLASS (code) == '<')
3611 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3612 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3613 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3615 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3616 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3617 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3619 || (GET_RTX_CLASS (code) == '1'
3620 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3621 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3622 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3625 rtx cond, true_rtx, false_rtx;
3627 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3629 /* If everything is a comparison, what we have is highly unlikely
3630 to be simpler, so don't use it. */
3631 && ! (GET_RTX_CLASS (code) == '<'
3632 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3633 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3635 rtx cop1 = const0_rtx;
3636 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3638 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3641 /* Simplify the alternative arms; this may collapse the true and
3642 false arms to store-flag values. Be careful to use copy_rtx
3643 here since true_rtx or false_rtx might share RTL with x as a
3644 result of the if_then_else_cond call above. */
3645 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3646 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3648 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3649 is unlikely to be simpler. */
3650 if (general_operand (true_rtx, VOIDmode)
3651 && general_operand (false_rtx, VOIDmode))
3653 enum rtx_code reversed;
3655 /* Restarting if we generate a store-flag expression will cause
3656 us to loop. Just drop through in this case. */
3658 /* If the result values are STORE_FLAG_VALUE and zero, we can
3659 just make the comparison operation. */
3660 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3661 x = gen_binary (cond_code, mode, cond, cop1);
3662 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3663 && ((reversed = reversed_comparison_code_parts
3664 (cond_code, cond, cop1, NULL))
3666 x = gen_binary (reversed, mode, cond, cop1);
3668 /* Likewise, we can make the negate of a comparison operation
3669 if the result values are - STORE_FLAG_VALUE and zero. */
3670 else if (GET_CODE (true_rtx) == CONST_INT
3671 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3672 && false_rtx == const0_rtx)
3673 x = simplify_gen_unary (NEG, mode,
3674 gen_binary (cond_code, mode, cond,
3677 else if (GET_CODE (false_rtx) == CONST_INT
3678 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3679 && true_rtx == const0_rtx
3680 && ((reversed = reversed_comparison_code_parts
3681 (cond_code, cond, cop1, NULL))
3683 x = simplify_gen_unary (NEG, mode,
3684 gen_binary (reversed, mode,
3688 return gen_rtx_IF_THEN_ELSE (mode,
3689 gen_binary (cond_code, VOIDmode,
3691 true_rtx, false_rtx);
3693 code = GET_CODE (x);
3694 op0_mode = VOIDmode;
3699 /* Try to fold this expression in case we have constants that weren't
3702 switch (GET_RTX_CLASS (code))
3705 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3709 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3710 if (cmp_mode == VOIDmode)
3712 cmp_mode = GET_MODE (XEXP (x, 1));
3713 if (cmp_mode == VOIDmode)
3714 cmp_mode = op0_mode;
3716 temp = simplify_relational_operation (code, cmp_mode,
3717 XEXP (x, 0), XEXP (x, 1));
3719 #ifdef FLOAT_STORE_FLAG_VALUE
3720 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3722 if (temp == const0_rtx)
3723 temp = CONST0_RTX (mode);
3725 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3732 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3736 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3737 XEXP (x, 1), XEXP (x, 2));
3744 code = GET_CODE (temp);
3745 op0_mode = VOIDmode;
3746 mode = GET_MODE (temp);
3749 /* First see if we can apply the inverse distributive law. */
3750 if (code == PLUS || code == MINUS
3751 || code == AND || code == IOR || code == XOR)
3753 x = apply_distributive_law (x);
3754 code = GET_CODE (x);
3755 op0_mode = VOIDmode;
3758 /* If CODE is an associative operation not otherwise handled, see if we
3759 can associate some operands. This can win if they are constants or
3760 if they are logically related (i.e. (a & b) & a). */
3761 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3762 || code == AND || code == IOR || code == XOR
3763 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3764 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3765 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3767 if (GET_CODE (XEXP (x, 0)) == code)
3769 rtx other = XEXP (XEXP (x, 0), 0);
3770 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3771 rtx inner_op1 = XEXP (x, 1);
3774 /* Make sure we pass the constant operand if any as the second
3775 one if this is a commutative operation. */
3776 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3778 rtx tem = inner_op0;
3779 inner_op0 = inner_op1;
3782 inner = simplify_binary_operation (code == MINUS ? PLUS
3783 : code == DIV ? MULT
3785 mode, inner_op0, inner_op1);
3787 /* For commutative operations, try the other pair if that one
3789 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3791 other = XEXP (XEXP (x, 0), 1);
3792 inner = simplify_binary_operation (code, mode,
3793 XEXP (XEXP (x, 0), 0),
3798 return gen_binary (code, mode, other, inner);
3802 /* A little bit of algebraic simplification here. */
3806 /* Ensure that our address has any ASHIFTs converted to MULT in case
3807 address-recognizing predicates are called later. */
3808 temp = make_compound_operation (XEXP (x, 0), MEM);
3809 SUBST (XEXP (x, 0), temp);
3813 if (op0_mode == VOIDmode)
3814 op0_mode = GET_MODE (SUBREG_REG (x));
3816 /* simplify_subreg can't use gen_lowpart_for_combine. */
3817 if (CONSTANT_P (SUBREG_REG (x))
3818 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3819 /* Don't call gen_lowpart_for_combine if the inner mode
3820 is VOIDmode and we cannot simplify it, as SUBREG without
3821 inner mode is invalid. */
3822 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3823 || gen_lowpart_common (mode, SUBREG_REG (x))))
3824 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3826 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3830 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3836 /* Don't change the mode of the MEM if that would change the meaning
3838 if (GET_CODE (SUBREG_REG (x)) == MEM
3839 && (MEM_VOLATILE_P (SUBREG_REG (x))
3840 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3841 return gen_rtx_CLOBBER (mode, const0_rtx);
3843 /* Note that we cannot do any narrowing for non-constants since
3844 we might have been counting on using the fact that some bits were
3845 zero. We now do this in the SET. */
3850 if (GET_CODE (XEXP (x, 0)) == SUBREG
3851 && subreg_lowpart_p (XEXP (x, 0))
3852 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3853 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3854 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3855 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3857 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3859 x = gen_rtx_ROTATE (inner_mode,
3860 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3862 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3863 return gen_lowpart_for_combine (mode, x);
3866 /* Apply De Morgan's laws to reduce number of patterns for machines
3867 with negating logical insns (and-not, nand, etc.). If result has
3868 only one NOT, put it first, since that is how the patterns are
3871 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3873 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3874 enum machine_mode op_mode;
3876 op_mode = GET_MODE (in1);
3877 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3879 op_mode = GET_MODE (in2);
3880 if (op_mode == VOIDmode)
3882 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3884 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3887 in2 = in1; in1 = tem;
3890 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3896 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3897 if (GET_CODE (XEXP (x, 0)) == XOR
3898 && XEXP (XEXP (x, 0), 1) == const1_rtx
3899 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3900 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3902 temp = expand_compound_operation (XEXP (x, 0));
3904 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3905 replaced by (lshiftrt X C). This will convert
3906 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3908 if (GET_CODE (temp) == ASHIFTRT
3909 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3910 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3911 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3912 INTVAL (XEXP (temp, 1)));
3914 /* If X has only a single bit that might be nonzero, say, bit I, convert
3915 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3916 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3917 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3918 or a SUBREG of one since we'd be making the expression more
3919 complex if it was just a register. */
3921 if (GET_CODE (temp) != REG
3922 && ! (GET_CODE (temp) == SUBREG
3923 && GET_CODE (SUBREG_REG (temp)) == REG)
3924 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3926 rtx temp1 = simplify_shift_const
3927 (NULL_RTX, ASHIFTRT, mode,
3928 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3929 GET_MODE_BITSIZE (mode) - 1 - i),
3930 GET_MODE_BITSIZE (mode) - 1 - i);
3932 /* If all we did was surround TEMP with the two shifts, we
3933 haven't improved anything, so don't use it. Otherwise,
3934 we are better off with TEMP1. */
3935 if (GET_CODE (temp1) != ASHIFTRT
3936 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3937 || XEXP (XEXP (temp1, 0), 0) != temp)
3943 /* We can't handle truncation to a partial integer mode here
3944 because we don't know the real bitsize of the partial
3946 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3949 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3950 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3951 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3953 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3954 GET_MODE_MASK (mode), NULL_RTX, 0));
3956 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3957 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3958 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3959 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3960 return XEXP (XEXP (x, 0), 0);
3962 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3963 (OP:SI foo:SI) if OP is NEG or ABS. */
3964 if ((GET_CODE (XEXP (x, 0)) == ABS
3965 || GET_CODE (XEXP (x, 0)) == NEG)
3966 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3967 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3968 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3969 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
3970 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
3972 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3974 if (GET_CODE (XEXP (x, 0)) == SUBREG
3975 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3976 && subreg_lowpart_p (XEXP (x, 0)))
3977 return SUBREG_REG (XEXP (x, 0));
3979 /* If we know that the value is already truncated, we can
3980 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3981 is nonzero for the corresponding modes. But don't do this
3982 for an (LSHIFTRT (MULT ...)) since this will cause problems
3983 with the umulXi3_highpart patterns. */
3984 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3985 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3986 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3987 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
3988 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
3989 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
3990 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3992 /* A truncate of a comparison can be replaced with a subreg if
3993 STORE_FLAG_VALUE permits. This is like the previous test,
3994 but it works even if the comparison is done in a mode larger
3995 than HOST_BITS_PER_WIDE_INT. */
3996 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3997 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3998 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
3999 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4001 /* Similarly, a truncate of a register whose value is a
4002 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4004 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4005 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4006 && (temp = get_last_value (XEXP (x, 0)))
4007 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4008 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4012 case FLOAT_TRUNCATE:
4013 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4014 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4015 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4016 return XEXP (XEXP (x, 0), 0);
4018 /* (float_truncate:SF (float_truncate:DF foo:XF))
4019 = (float_truncate:SF foo:XF).
4020 This may eliminate double rounding, so it is unsafe.
4022 (float_truncate:SF (float_extend:XF foo:DF))
4023 = (float_truncate:SF foo:DF).
4025 (float_truncate:DF (float_extend:XF foo:SF))
4026 = (float_extend:SF foo:DF). */
4027 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4028 && flag_unsafe_math_optimizations)
4029 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4030 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4032 > GET_MODE_SIZE (mode)
4033 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4035 XEXP (XEXP (x, 0), 0), mode);
4037 /* (float_truncate (float x)) is (float x) */
4038 if (GET_CODE (XEXP (x, 0)) == FLOAT
4039 && (flag_unsafe_math_optimizations
4040 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4041 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4042 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4043 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4044 return simplify_gen_unary (FLOAT, mode,
4045 XEXP (XEXP (x, 0), 0),
4046 GET_MODE (XEXP (XEXP (x, 0), 0)));
4048 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4049 (OP:SF foo:SF) if OP is NEG or ABS. */
4050 if ((GET_CODE (XEXP (x, 0)) == ABS
4051 || GET_CODE (XEXP (x, 0)) == NEG)
4052 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4053 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4054 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4055 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4057 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4058 is (float_truncate:SF x). */
4059 if (GET_CODE (XEXP (x, 0)) == SUBREG
4060 && subreg_lowpart_p (XEXP (x, 0))
4061 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4062 return SUBREG_REG (XEXP (x, 0));
4065 /* (float_extend (float_extend x)) is (float_extend x)
4067 (float_extend (float x)) is (float x) assuming that double
4068 rounding can't happen.
4070 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4071 || (GET_CODE (XEXP (x, 0)) == FLOAT
4072 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4073 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4074 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4075 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4076 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4077 XEXP (XEXP (x, 0), 0),
4078 GET_MODE (XEXP (XEXP (x, 0), 0)));
4083 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4084 using cc0, in which case we want to leave it as a COMPARE
4085 so we can distinguish it from a register-register-copy. */
4086 if (XEXP (x, 1) == const0_rtx)
4089 /* x - 0 is the same as x unless x's mode has signed zeros and
4090 allows rounding towards -infinity. Under those conditions,
4092 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4093 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4094 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4100 /* (const (const X)) can become (const X). Do it this way rather than
4101 returning the inner CONST since CONST can be shared with a
4103 if (GET_CODE (XEXP (x, 0)) == CONST)
4104 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4109 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4110 can add in an offset. find_split_point will split this address up
4111 again if it doesn't match. */
4112 if (GET_CODE (XEXP (x, 0)) == HIGH
4113 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4119 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4121 if (GET_CODE (XEXP (x, 0)) == MULT
4122 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4126 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4127 in2 = XEXP (XEXP (x, 0), 1);
4128 return gen_binary (MINUS, mode, XEXP (x, 1),
4129 gen_binary (MULT, mode, in1, in2));
4132 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4133 outermost. That's because that's the way indexed addresses are
4134 supposed to appear. This code used to check many more cases, but
4135 they are now checked elsewhere. */
4136 if (GET_CODE (XEXP (x, 0)) == PLUS
4137 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4138 return gen_binary (PLUS, mode,
4139 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4141 XEXP (XEXP (x, 0), 1));
4143 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4144 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4145 bit-field and can be replaced by either a sign_extend or a
4146 sign_extract. The `and' may be a zero_extend and the two
4147 <c>, -<c> constants may be reversed. */
4148 if (GET_CODE (XEXP (x, 0)) == XOR
4149 && GET_CODE (XEXP (x, 1)) == CONST_INT
4150 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4151 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4152 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4153 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4154 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4155 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4156 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4157 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4158 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4159 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4160 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4161 == (unsigned int) i + 1))))
4162 return simplify_shift_const
4163 (NULL_RTX, ASHIFTRT, mode,
4164 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4165 XEXP (XEXP (XEXP (x, 0), 0), 0),
4166 GET_MODE_BITSIZE (mode) - (i + 1)),
4167 GET_MODE_BITSIZE (mode) - (i + 1));
4169 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4170 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4171 is 1. This produces better code than the alternative immediately
4173 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4174 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4175 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4176 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4177 XEXP (XEXP (x, 0), 0),
4178 XEXP (XEXP (x, 0), 1))))
4180 simplify_gen_unary (NEG, mode, reversed, mode);
4182 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4183 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4184 the bitsize of the mode - 1. This allows simplification of
4185 "a = (b & 8) == 0;" */
4186 if (XEXP (x, 1) == constm1_rtx
4187 && GET_CODE (XEXP (x, 0)) != REG
4188 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4189 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4190 && nonzero_bits (XEXP (x, 0), mode) == 1)
4191 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4192 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4193 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4194 GET_MODE_BITSIZE (mode) - 1),
4195 GET_MODE_BITSIZE (mode) - 1);
4197 /* If we are adding two things that have no bits in common, convert
4198 the addition into an IOR. This will often be further simplified,
4199 for example in cases like ((a & 1) + (a & 2)), which can
4202 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4203 && (nonzero_bits (XEXP (x, 0), mode)
4204 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4206 /* Try to simplify the expression further. */
4207 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4208 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4210 /* If we could, great. If not, do not go ahead with the IOR
4211 replacement, since PLUS appears in many special purpose
4212 address arithmetic instructions. */
4213 if (GET_CODE (temp) != CLOBBER && temp != tor)
4219 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4220 by reversing the comparison code if valid. */
4221 if (STORE_FLAG_VALUE == 1
4222 && XEXP (x, 0) == const1_rtx
4223 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4224 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4225 XEXP (XEXP (x, 1), 0),
4226 XEXP (XEXP (x, 1), 1))))
4229 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4230 (and <foo> (const_int pow2-1)) */
4231 if (GET_CODE (XEXP (x, 1)) == AND
4232 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4233 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4234 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4235 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4236 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4238 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4240 if (GET_CODE (XEXP (x, 1)) == MULT
4241 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4245 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4246 in2 = XEXP (XEXP (x, 1), 1);
4247 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4251 /* Canonicalize (minus (neg A) (mult B C)) to
4252 (minus (mult (neg B) C) A). */
4253 if (GET_CODE (XEXP (x, 1)) == MULT
4254 && GET_CODE (XEXP (x, 0)) == NEG)
4258 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4259 in2 = XEXP (XEXP (x, 1), 1);
4260 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4261 XEXP (XEXP (x, 0), 0));
4264 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4266 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4267 return gen_binary (MINUS, mode,
4268 gen_binary (MINUS, mode, XEXP (x, 0),
4269 XEXP (XEXP (x, 1), 0)),
4270 XEXP (XEXP (x, 1), 1));
4274 /* If we have (mult (plus A B) C), apply the distributive law and then
4275 the inverse distributive law to see if things simplify. This
4276 occurs mostly in addresses, often when unrolling loops. */
4278 if (GET_CODE (XEXP (x, 0)) == PLUS)
4280 x = apply_distributive_law
4281 (gen_binary (PLUS, mode,
4282 gen_binary (MULT, mode,
4283 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4284 gen_binary (MULT, mode,
4285 XEXP (XEXP (x, 0), 1),
4286 copy_rtx (XEXP (x, 1)))));
4288 if (GET_CODE (x) != MULT)
4291 /* Try simplify a*(b/c) as (a*b)/c. */
4292 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4293 && GET_CODE (XEXP (x, 0)) == DIV)
4295 rtx tem = simplify_binary_operation (MULT, mode,
4296 XEXP (XEXP (x, 0), 0),
4299 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4304 /* If this is a divide by a power of two, treat it as a shift if
4305 its first operand is a shift. */
4306 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4307 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4308 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4309 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4310 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4311 || GET_CODE (XEXP (x, 0)) == ROTATE
4312 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4313 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4317 case GT: case GTU: case GE: case GEU:
4318 case LT: case LTU: case LE: case LEU:
4319 case UNEQ: case LTGT:
4320 case UNGT: case UNGE:
4321 case UNLT: case UNLE:
4322 case UNORDERED: case ORDERED:
4323 /* If the first operand is a condition code, we can't do anything
4325 if (GET_CODE (XEXP (x, 0)) == COMPARE
4326 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4327 && ! CC0_P (XEXP (x, 0))))
4329 rtx op0 = XEXP (x, 0);
4330 rtx op1 = XEXP (x, 1);
4331 enum rtx_code new_code;
4333 if (GET_CODE (op0) == COMPARE)
4334 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4336 /* Simplify our comparison, if possible. */
4337 new_code = simplify_comparison (code, &op0, &op1);
4339 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4340 if only the low-order bit is possibly nonzero in X (such as when
4341 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4342 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4343 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4346 Remove any ZERO_EXTRACT we made when thinking this was a
4347 comparison. It may now be simpler to use, e.g., an AND. If a
4348 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4349 the call to make_compound_operation in the SET case. */
4351 if (STORE_FLAG_VALUE == 1
4352 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4353 && op1 == const0_rtx
4354 && mode == GET_MODE (op0)
4355 && nonzero_bits (op0, mode) == 1)
4356 return gen_lowpart_for_combine (mode,
4357 expand_compound_operation (op0));
4359 else if (STORE_FLAG_VALUE == 1
4360 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4361 && op1 == const0_rtx
4362 && mode == GET_MODE (op0)
4363 && (num_sign_bit_copies (op0, mode)
4364 == GET_MODE_BITSIZE (mode)))
4366 op0 = expand_compound_operation (op0);
4367 return simplify_gen_unary (NEG, mode,
4368 gen_lowpart_for_combine (mode, op0),
4372 else if (STORE_FLAG_VALUE == 1
4373 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4374 && op1 == const0_rtx
4375 && mode == GET_MODE (op0)
4376 && nonzero_bits (op0, mode) == 1)
4378 op0 = expand_compound_operation (op0);
4379 return gen_binary (XOR, mode,
4380 gen_lowpart_for_combine (mode, op0),
4384 else if (STORE_FLAG_VALUE == 1
4385 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4386 && op1 == const0_rtx
4387 && mode == GET_MODE (op0)
4388 && (num_sign_bit_copies (op0, mode)
4389 == GET_MODE_BITSIZE (mode)))
4391 op0 = expand_compound_operation (op0);
4392 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4395 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4397 if (STORE_FLAG_VALUE == -1
4398 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4399 && op1 == const0_rtx
4400 && (num_sign_bit_copies (op0, mode)
4401 == GET_MODE_BITSIZE (mode)))
4402 return gen_lowpart_for_combine (mode,
4403 expand_compound_operation (op0));
4405 else if (STORE_FLAG_VALUE == -1
4406 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4407 && op1 == const0_rtx
4408 && mode == GET_MODE (op0)
4409 && nonzero_bits (op0, mode) == 1)
4411 op0 = expand_compound_operation (op0);
4412 return simplify_gen_unary (NEG, mode,
4413 gen_lowpart_for_combine (mode, op0),
4417 else if (STORE_FLAG_VALUE == -1
4418 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4419 && op1 == const0_rtx
4420 && mode == GET_MODE (op0)
4421 && (num_sign_bit_copies (op0, mode)
4422 == GET_MODE_BITSIZE (mode)))
4424 op0 = expand_compound_operation (op0);
4425 return simplify_gen_unary (NOT, mode,
4426 gen_lowpart_for_combine (mode, op0),
4430 /* If X is 0/1, (eq X 0) is X-1. */
4431 else if (STORE_FLAG_VALUE == -1
4432 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4433 && op1 == const0_rtx
4434 && mode == GET_MODE (op0)
4435 && nonzero_bits (op0, mode) == 1)
4437 op0 = expand_compound_operation (op0);
4438 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4441 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4442 one bit that might be nonzero, we can convert (ne x 0) to
4443 (ashift x c) where C puts the bit in the sign bit. Remove any
4444 AND with STORE_FLAG_VALUE when we are done, since we are only
4445 going to test the sign bit. */
4446 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4447 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4448 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4449 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4450 && op1 == const0_rtx
4451 && mode == GET_MODE (op0)
4452 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4454 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4455 expand_compound_operation (op0),
4456 GET_MODE_BITSIZE (mode) - 1 - i);
4457 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4463 /* If the code changed, return a whole new comparison. */
4464 if (new_code != code)
4465 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4467 /* Otherwise, keep this operation, but maybe change its operands.
4468 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4469 SUBST (XEXP (x, 0), op0);
4470 SUBST (XEXP (x, 1), op1);
4475 return simplify_if_then_else (x);
4481 /* If we are processing SET_DEST, we are done. */
4485 return expand_compound_operation (x);
4488 return simplify_set (x);
4493 return simplify_logical (x, last);
4496 /* (abs (neg <foo>)) -> (abs <foo>) */
4497 if (GET_CODE (XEXP (x, 0)) == NEG)
4498 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4500 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4502 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4505 /* If operand is something known to be positive, ignore the ABS. */
4506 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4507 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4508 <= HOST_BITS_PER_WIDE_INT)
4509 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4510 & ((HOST_WIDE_INT) 1
4511 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4515 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4516 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4517 return gen_rtx_NEG (mode, XEXP (x, 0));
4522 /* (ffs (*_extend <X>)) = (ffs <X>) */
4523 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4524 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4525 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4530 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4531 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4532 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4536 /* (float (sign_extend <X>)) = (float <X>). */
4537 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4538 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4546 /* If this is a shift by a constant amount, simplify it. */
4547 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4548 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4549 INTVAL (XEXP (x, 1)));
4551 #ifdef SHIFT_COUNT_TRUNCATED
4552 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4554 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4556 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4565 rtx op0 = XEXP (x, 0);
4566 rtx op1 = XEXP (x, 1);
4569 if (GET_CODE (op1) != PARALLEL)
4571 len = XVECLEN (op1, 0);
4573 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4574 && GET_CODE (op0) == VEC_CONCAT)
4576 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4578 /* Try to find the element in the VEC_CONCAT. */
4581 if (GET_MODE (op0) == GET_MODE (x))
4583 if (GET_CODE (op0) == VEC_CONCAT)
4585 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4586 if (op0_size < offset)
4587 op0 = XEXP (op0, 0);
4591 op0 = XEXP (op0, 1);
4609 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4612 simplify_if_then_else (rtx x)
4614 enum machine_mode mode = GET_MODE (x);
4615 rtx cond = XEXP (x, 0);
4616 rtx true_rtx = XEXP (x, 1);
4617 rtx false_rtx = XEXP (x, 2);
4618 enum rtx_code true_code = GET_CODE (cond);
4619 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4622 enum rtx_code false_code;
4625 /* Simplify storing of the truth value. */
4626 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4627 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4629 /* Also when the truth value has to be reversed. */
4631 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4632 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4636 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4637 in it is being compared against certain values. Get the true and false
4638 comparisons and see if that says anything about the value of each arm. */
4641 && ((false_code = combine_reversed_comparison_code (cond))
4643 && GET_CODE (XEXP (cond, 0)) == REG)
4646 rtx from = XEXP (cond, 0);
4647 rtx true_val = XEXP (cond, 1);
4648 rtx false_val = true_val;
4651 /* If FALSE_CODE is EQ, swap the codes and arms. */
4653 if (false_code == EQ)
4655 swapped = 1, true_code = EQ, false_code = NE;
4656 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4659 /* If we are comparing against zero and the expression being tested has
4660 only a single bit that might be nonzero, that is its value when it is
4661 not equal to zero. Similarly if it is known to be -1 or 0. */
4663 if (true_code == EQ && true_val == const0_rtx
4664 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4665 false_code = EQ, false_val = GEN_INT (nzb);
4666 else if (true_code == EQ && true_val == const0_rtx
4667 && (num_sign_bit_copies (from, GET_MODE (from))
4668 == GET_MODE_BITSIZE (GET_MODE (from))))
4669 false_code = EQ, false_val = constm1_rtx;
4671 /* Now simplify an arm if we know the value of the register in the
4672 branch and it is used in the arm. Be careful due to the potential
4673 of locally-shared RTL. */
4675 if (reg_mentioned_p (from, true_rtx))
4676 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4678 pc_rtx, pc_rtx, 0, 0);
4679 if (reg_mentioned_p (from, false_rtx))
4680 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4682 pc_rtx, pc_rtx, 0, 0);
4684 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4685 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4687 true_rtx = XEXP (x, 1);
4688 false_rtx = XEXP (x, 2);
4689 true_code = GET_CODE (cond);
4692 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4693 reversed, do so to avoid needing two sets of patterns for
4694 subtract-and-branch insns. Similarly if we have a constant in the true
4695 arm, the false arm is the same as the first operand of the comparison, or
4696 the false arm is more complicated than the true arm. */
4699 && combine_reversed_comparison_code (cond) != UNKNOWN
4700 && (true_rtx == pc_rtx
4701 || (CONSTANT_P (true_rtx)
4702 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4703 || true_rtx == const0_rtx
4704 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4705 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4706 || (GET_CODE (true_rtx) == SUBREG
4707 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4708 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4709 || reg_mentioned_p (true_rtx, false_rtx)
4710 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4712 true_code = reversed_comparison_code (cond, NULL);
4714 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4717 SUBST (XEXP (x, 1), false_rtx);
4718 SUBST (XEXP (x, 2), true_rtx);
4720 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4723 /* It is possible that the conditional has been simplified out. */
4724 true_code = GET_CODE (cond);
4725 comparison_p = GET_RTX_CLASS (true_code) == '<';
4728 /* If the two arms are identical, we don't need the comparison. */
4730 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4733 /* Convert a == b ? b : a to "a". */
4734 if (true_code == EQ && ! side_effects_p (cond)
4735 && !HONOR_NANS (mode)
4736 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4737 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4739 else if (true_code == NE && ! side_effects_p (cond)
4740 && !HONOR_NANS (mode)
4741 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4742 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4745 /* Look for cases where we have (abs x) or (neg (abs X)). */
4747 if (GET_MODE_CLASS (mode) == MODE_INT
4748 && GET_CODE (false_rtx) == NEG
4749 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4751 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4752 && ! side_effects_p (true_rtx))
4757 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4761 simplify_gen_unary (NEG, mode,
4762 simplify_gen_unary (ABS, mode, true_rtx, mode),
4768 /* Look for MIN or MAX. */
4770 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4772 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4773 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4774 && ! side_effects_p (cond))
4779 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4782 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4785 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4788 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4793 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4794 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4795 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4796 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4797 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4798 neither 1 or -1, but it isn't worth checking for. */
4800 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4802 && GET_MODE_CLASS (mode) == MODE_INT
4803 && ! side_effects_p (x))
4805 rtx t = make_compound_operation (true_rtx, SET);
4806 rtx f = make_compound_operation (false_rtx, SET);
4807 rtx cond_op0 = XEXP (cond, 0);
4808 rtx cond_op1 = XEXP (cond, 1);
4809 enum rtx_code op = NIL, extend_op = NIL;
4810 enum machine_mode m = mode;
4811 rtx z = 0, c1 = NULL_RTX;
4813 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4814 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4815 || GET_CODE (t) == ASHIFT
4816 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4817 && rtx_equal_p (XEXP (t, 0), f))
4818 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4820 /* If an identity-zero op is commutative, check whether there
4821 would be a match if we swapped the operands. */
4822 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4823 || GET_CODE (t) == XOR)
4824 && rtx_equal_p (XEXP (t, 1), f))
4825 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4826 else if (GET_CODE (t) == SIGN_EXTEND
4827 && (GET_CODE (XEXP (t, 0)) == PLUS
4828 || GET_CODE (XEXP (t, 0)) == MINUS
4829 || GET_CODE (XEXP (t, 0)) == IOR
4830 || GET_CODE (XEXP (t, 0)) == XOR
4831 || GET_CODE (XEXP (t, 0)) == ASHIFT
4832 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4833 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4834 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4835 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4836 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4837 && (num_sign_bit_copies (f, GET_MODE (f))
4839 (GET_MODE_BITSIZE (mode)
4840 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4842 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4843 extend_op = SIGN_EXTEND;
4844 m = GET_MODE (XEXP (t, 0));
4846 else if (GET_CODE (t) == SIGN_EXTEND
4847 && (GET_CODE (XEXP (t, 0)) == PLUS
4848 || GET_CODE (XEXP (t, 0)) == IOR
4849 || GET_CODE (XEXP (t, 0)) == XOR)
4850 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4851 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4852 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4853 && (num_sign_bit_copies (f, GET_MODE (f))
4855 (GET_MODE_BITSIZE (mode)
4856 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4858 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4859 extend_op = SIGN_EXTEND;
4860 m = GET_MODE (XEXP (t, 0));
4862 else if (GET_CODE (t) == ZERO_EXTEND
4863 && (GET_CODE (XEXP (t, 0)) == PLUS
4864 || GET_CODE (XEXP (t, 0)) == MINUS
4865 || GET_CODE (XEXP (t, 0)) == IOR
4866 || GET_CODE (XEXP (t, 0)) == XOR
4867 || GET_CODE (XEXP (t, 0)) == ASHIFT
4868 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4869 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4870 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4871 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4872 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4873 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4874 && ((nonzero_bits (f, GET_MODE (f))
4875 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4878 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4879 extend_op = ZERO_EXTEND;
4880 m = GET_MODE (XEXP (t, 0));
4882 else if (GET_CODE (t) == ZERO_EXTEND
4883 && (GET_CODE (XEXP (t, 0)) == PLUS
4884 || GET_CODE (XEXP (t, 0)) == IOR
4885 || GET_CODE (XEXP (t, 0)) == XOR)
4886 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4887 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4888 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4889 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4890 && ((nonzero_bits (f, GET_MODE (f))
4891 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4894 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4895 extend_op = ZERO_EXTEND;
4896 m = GET_MODE (XEXP (t, 0));
4901 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4902 pc_rtx, pc_rtx, 0, 0);
4903 temp = gen_binary (MULT, m, temp,
4904 gen_binary (MULT, m, c1, const_true_rtx));
4905 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4906 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4908 if (extend_op != NIL)
4909 temp = simplify_gen_unary (extend_op, mode, temp, m);
4915 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4916 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4917 negation of a single bit, we can convert this operation to a shift. We
4918 can actually do this more generally, but it doesn't seem worth it. */
4920 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4921 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4922 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4923 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4924 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4925 == GET_MODE_BITSIZE (mode))
4926 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4928 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4929 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4931 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4932 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4933 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4934 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
4935 == nonzero_bits (XEXP (cond, 0), mode)
4936 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
4937 return XEXP (cond, 0);
4942 /* Simplify X, a SET expression. Return the new expression. */
4945 simplify_set (rtx x)
4947 rtx src = SET_SRC (x);
4948 rtx dest = SET_DEST (x);
4949 enum machine_mode mode
4950 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4954 /* (set (pc) (return)) gets written as (return). */
4955 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4958 /* Now that we know for sure which bits of SRC we are using, see if we can
4959 simplify the expression for the object knowing that we only need the
4962 if (GET_MODE_CLASS (mode) == MODE_INT
4963 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4965 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4966 SUBST (SET_SRC (x), src);
4969 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4970 the comparison result and try to simplify it unless we already have used
4971 undobuf.other_insn. */
4972 if ((GET_MODE_CLASS (mode) == MODE_CC
4973 || GET_CODE (src) == COMPARE
4975 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4976 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4977 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4978 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4980 enum rtx_code old_code = GET_CODE (*cc_use);
4981 enum rtx_code new_code;
4983 int other_changed = 0;
4984 enum machine_mode compare_mode = GET_MODE (dest);
4985 enum machine_mode tmp_mode;
4987 if (GET_CODE (src) == COMPARE)
4988 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4990 op0 = src, op1 = const0_rtx;
4992 /* Check whether the comparison is known at compile time. */
4993 if (GET_MODE (op0) != VOIDmode)
4994 tmp_mode = GET_MODE (op0);
4995 else if (GET_MODE (op1) != VOIDmode)
4996 tmp_mode = GET_MODE (op1);
4998 tmp_mode = compare_mode;
4999 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5000 if (tmp != NULL_RTX)
5002 rtx pat = PATTERN (other_insn);
5003 undobuf.other_insn = other_insn;
5004 SUBST (*cc_use, tmp);
5006 /* Attempt to simplify CC user. */
5007 if (GET_CODE (pat) == SET)
5009 rtx new = simplify_rtx (SET_SRC (pat));
5010 if (new != NULL_RTX)
5011 SUBST (SET_SRC (pat), new);
5014 /* Convert X into a no-op move. */
5015 SUBST (SET_DEST (x), pc_rtx);
5016 SUBST (SET_SRC (x), pc_rtx);
5020 /* Simplify our comparison, if possible. */
5021 new_code = simplify_comparison (old_code, &op0, &op1);
5023 #ifdef EXTRA_CC_MODES
5024 /* If this machine has CC modes other than CCmode, check to see if we
5025 need to use a different CC mode here. */
5026 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5027 #endif /* EXTRA_CC_MODES */
5029 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5030 /* If the mode changed, we have to change SET_DEST, the mode in the
5031 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5032 a hard register, just build new versions with the proper mode. If it
5033 is a pseudo, we lose unless it is only time we set the pseudo, in
5034 which case we can safely change its mode. */
5035 if (compare_mode != GET_MODE (dest))
5037 unsigned int regno = REGNO (dest);
5038 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5040 if (regno < FIRST_PSEUDO_REGISTER
5041 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5043 if (regno >= FIRST_PSEUDO_REGISTER)
5044 SUBST (regno_reg_rtx[regno], new_dest);
5046 SUBST (SET_DEST (x), new_dest);
5047 SUBST (XEXP (*cc_use, 0), new_dest);
5055 /* If the code changed, we have to build a new comparison in
5056 undobuf.other_insn. */
5057 if (new_code != old_code)
5059 unsigned HOST_WIDE_INT mask;
5061 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5064 /* If the only change we made was to change an EQ into an NE or
5065 vice versa, OP0 has only one bit that might be nonzero, and OP1
5066 is zero, check if changing the user of the condition code will
5067 produce a valid insn. If it won't, we can keep the original code
5068 in that insn by surrounding our operation with an XOR. */
5070 if (((old_code == NE && new_code == EQ)
5071 || (old_code == EQ && new_code == NE))
5072 && ! other_changed && op1 == const0_rtx
5073 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5074 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5076 rtx pat = PATTERN (other_insn), note = 0;
5078 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5079 && ! check_asm_operands (pat)))
5081 PUT_CODE (*cc_use, old_code);
5084 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5092 undobuf.other_insn = other_insn;
5095 /* If we are now comparing against zero, change our source if
5096 needed. If we do not use cc0, we always have a COMPARE. */
5097 if (op1 == const0_rtx && dest == cc0_rtx)
5099 SUBST (SET_SRC (x), op0);
5105 /* Otherwise, if we didn't previously have a COMPARE in the
5106 correct mode, we need one. */
5107 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5109 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5114 /* Otherwise, update the COMPARE if needed. */
5115 SUBST (XEXP (src, 0), op0);
5116 SUBST (XEXP (src, 1), op1);
5121 /* Get SET_SRC in a form where we have placed back any
5122 compound expressions. Then do the checks below. */
5123 src = make_compound_operation (src, SET);
5124 SUBST (SET_SRC (x), src);
5127 #ifdef WORD_REGISTER_OPERATIONS
5128 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5129 and X being a REG or (subreg (reg)), we may be able to convert this to
5130 (set (subreg:m2 x) (op)).
5132 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5133 transformation is safe as long as M1 and M2 have the same number
5136 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5137 we cannot apply this transformation because it would create a
5138 paradoxical subreg in SET_DEST. */
5140 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5141 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5142 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5144 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5145 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5146 #ifdef CANNOT_CHANGE_MODE_CLASS
5147 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5148 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5149 GET_MODE (SUBREG_REG (src)),
5152 && (GET_CODE (dest) == REG
5153 || (GET_CODE (dest) == SUBREG
5154 && GET_CODE (SUBREG_REG (dest)) == REG)))
5156 SUBST (SET_DEST (x),
5157 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5159 SUBST (SET_SRC (x), SUBREG_REG (src));
5161 src = SET_SRC (x), dest = SET_DEST (x);
5166 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5169 && GET_CODE (src) == SUBREG
5170 && subreg_lowpart_p (src)
5171 && (GET_MODE_BITSIZE (GET_MODE (src))
5172 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5174 rtx inner = SUBREG_REG (src);
5175 enum machine_mode inner_mode = GET_MODE (inner);
5177 /* Here we make sure that we don't have a sign bit on. */
5178 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5179 && (nonzero_bits (inner, inner_mode)
5180 < ((unsigned HOST_WIDE_INT) 1
5181 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5183 SUBST (SET_SRC (x), inner);
5189 #ifdef LOAD_EXTEND_OP
5190 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5191 would require a paradoxical subreg. Replace the subreg with a
5192 zero_extend to avoid the reload that would otherwise be required. */
5194 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5195 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5196 && SUBREG_BYTE (src) == 0
5197 && (GET_MODE_SIZE (GET_MODE (src))
5198 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5199 && GET_CODE (SUBREG_REG (src)) == MEM)
5202 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5203 GET_MODE (src), SUBREG_REG (src)));
5209 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5210 are comparing an item known to be 0 or -1 against 0, use a logical
5211 operation instead. Check for one of the arms being an IOR of the other
5212 arm with some value. We compute three terms to be IOR'ed together. In
5213 practice, at most two will be nonzero. Then we do the IOR's. */
5215 if (GET_CODE (dest) != PC
5216 && GET_CODE (src) == IF_THEN_ELSE
5217 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5218 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5219 && XEXP (XEXP (src, 0), 1) == const0_rtx
5220 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5221 #ifdef HAVE_conditional_move
5222 && ! can_conditionally_move_p (GET_MODE (src))
5224 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5225 GET_MODE (XEXP (XEXP (src, 0), 0)))
5226 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5227 && ! side_effects_p (src))
5229 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5230 ? XEXP (src, 1) : XEXP (src, 2));
5231 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5232 ? XEXP (src, 2) : XEXP (src, 1));
5233 rtx term1 = const0_rtx, term2, term3;
5235 if (GET_CODE (true_rtx) == IOR
5236 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5237 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5238 else if (GET_CODE (true_rtx) == IOR
5239 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5240 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5241 else if (GET_CODE (false_rtx) == IOR
5242 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5243 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5244 else if (GET_CODE (false_rtx) == IOR
5245 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5246 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5248 term2 = gen_binary (AND, GET_MODE (src),
5249 XEXP (XEXP (src, 0), 0), true_rtx);
5250 term3 = gen_binary (AND, GET_MODE (src),
5251 simplify_gen_unary (NOT, GET_MODE (src),
5252 XEXP (XEXP (src, 0), 0),
5257 gen_binary (IOR, GET_MODE (src),
5258 gen_binary (IOR, GET_MODE (src), term1, term2),
5264 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5265 whole thing fail. */
5266 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5268 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5271 /* Convert this into a field assignment operation, if possible. */
5272 return make_field_assignment (x);
5275 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5276 result. LAST is nonzero if this is the last retry. */
5279 simplify_logical (rtx x, int last)
5281 enum machine_mode mode = GET_MODE (x);
5282 rtx op0 = XEXP (x, 0);
5283 rtx op1 = XEXP (x, 1);
5286 switch (GET_CODE (x))
5289 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5290 insn (and may simplify more). */
5291 if (GET_CODE (op0) == XOR
5292 && rtx_equal_p (XEXP (op0, 0), op1)
5293 && ! side_effects_p (op1))
5294 x = gen_binary (AND, mode,
5295 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5298 if (GET_CODE (op0) == XOR
5299 && rtx_equal_p (XEXP (op0, 1), op1)
5300 && ! side_effects_p (op1))
5301 x = gen_binary (AND, mode,
5302 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5305 /* Similarly for (~(A ^ B)) & A. */
5306 if (GET_CODE (op0) == NOT
5307 && GET_CODE (XEXP (op0, 0)) == XOR
5308 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5309 && ! side_effects_p (op1))
5310 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5312 if (GET_CODE (op0) == NOT
5313 && GET_CODE (XEXP (op0, 0)) == XOR
5314 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5315 && ! side_effects_p (op1))
5316 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5318 /* We can call simplify_and_const_int only if we don't lose
5319 any (sign) bits when converting INTVAL (op1) to
5320 "unsigned HOST_WIDE_INT". */
5321 if (GET_CODE (op1) == CONST_INT
5322 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5323 || INTVAL (op1) > 0))
5325 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5327 /* If we have (ior (and (X C1) C2)) and the next restart would be
5328 the last, simplify this by making C1 as small as possible
5331 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5332 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5333 && GET_CODE (op1) == CONST_INT)
5334 return gen_binary (IOR, mode,
5335 gen_binary (AND, mode, XEXP (op0, 0),
5336 GEN_INT (INTVAL (XEXP (op0, 1))
5337 & ~INTVAL (op1))), op1);
5339 if (GET_CODE (x) != AND)
5342 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5343 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5344 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5347 /* Convert (A | B) & A to A. */
5348 if (GET_CODE (op0) == IOR
5349 && (rtx_equal_p (XEXP (op0, 0), op1)
5350 || rtx_equal_p (XEXP (op0, 1), op1))
5351 && ! side_effects_p (XEXP (op0, 0))
5352 && ! side_effects_p (XEXP (op0, 1)))
5355 /* In the following group of tests (and those in case IOR below),
5356 we start with some combination of logical operations and apply
5357 the distributive law followed by the inverse distributive law.
5358 Most of the time, this results in no change. However, if some of
5359 the operands are the same or inverses of each other, simplifications
5362 For example, (and (ior A B) (not B)) can occur as the result of
5363 expanding a bit field assignment. When we apply the distributive
5364 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5365 which then simplifies to (and (A (not B))).
5367 If we have (and (ior A B) C), apply the distributive law and then
5368 the inverse distributive law to see if things simplify. */
5370 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5372 x = apply_distributive_law
5373 (gen_binary (GET_CODE (op0), mode,
5374 gen_binary (AND, mode, XEXP (op0, 0), op1),
5375 gen_binary (AND, mode, XEXP (op0, 1),
5377 if (GET_CODE (x) != AND)
5381 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5382 return apply_distributive_law
5383 (gen_binary (GET_CODE (op1), mode,
5384 gen_binary (AND, mode, XEXP (op1, 0), op0),
5385 gen_binary (AND, mode, XEXP (op1, 1),
5388 /* Similarly, taking advantage of the fact that
5389 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5391 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5392 return apply_distributive_law
5393 (gen_binary (XOR, mode,
5394 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5395 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5398 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5399 return apply_distributive_law
5400 (gen_binary (XOR, mode,
5401 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5402 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5406 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5407 if (GET_CODE (op1) == CONST_INT
5408 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5409 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5412 /* Convert (A & B) | A to A. */
5413 if (GET_CODE (op0) == AND
5414 && (rtx_equal_p (XEXP (op0, 0), op1)
5415 || rtx_equal_p (XEXP (op0, 1), op1))
5416 && ! side_effects_p (XEXP (op0, 0))
5417 && ! side_effects_p (XEXP (op0, 1)))
5420 /* If we have (ior (and A B) C), apply the distributive law and then
5421 the inverse distributive law to see if things simplify. */
5423 if (GET_CODE (op0) == AND)
5425 x = apply_distributive_law
5426 (gen_binary (AND, mode,
5427 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5428 gen_binary (IOR, mode, XEXP (op0, 1),
5431 if (GET_CODE (x) != IOR)
5435 if (GET_CODE (op1) == AND)
5437 x = apply_distributive_law
5438 (gen_binary (AND, mode,
5439 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5440 gen_binary (IOR, mode, XEXP (op1, 1),
5443 if (GET_CODE (x) != IOR)
5447 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5448 mode size to (rotate A CX). */
5450 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5451 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5452 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5453 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5454 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5455 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5456 == GET_MODE_BITSIZE (mode)))
5457 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5458 (GET_CODE (op0) == ASHIFT
5459 ? XEXP (op0, 1) : XEXP (op1, 1)));
5461 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5462 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5463 does not affect any of the bits in OP1, it can really be done
5464 as a PLUS and we can associate. We do this by seeing if OP1
5465 can be safely shifted left C bits. */
5466 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5467 && GET_CODE (XEXP (op0, 0)) == PLUS
5468 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5469 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5470 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5472 int count = INTVAL (XEXP (op0, 1));
5473 HOST_WIDE_INT mask = INTVAL (op1) << count;
5475 if (mask >> count == INTVAL (op1)
5476 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5478 SUBST (XEXP (XEXP (op0, 0), 1),
5479 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5486 /* If we are XORing two things that have no bits in common,
5487 convert them into an IOR. This helps to detect rotation encoded
5488 using those methods and possibly other simplifications. */
5490 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5491 && (nonzero_bits (op0, mode)
5492 & nonzero_bits (op1, mode)) == 0)
5493 return (gen_binary (IOR, mode, op0, op1));
5495 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5496 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5499 int num_negated = 0;
5501 if (GET_CODE (op0) == NOT)
5502 num_negated++, op0 = XEXP (op0, 0);
5503 if (GET_CODE (op1) == NOT)
5504 num_negated++, op1 = XEXP (op1, 0);
5506 if (num_negated == 2)
5508 SUBST (XEXP (x, 0), op0);
5509 SUBST (XEXP (x, 1), op1);
5511 else if (num_negated == 1)
5513 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5517 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5518 correspond to a machine insn or result in further simplifications
5519 if B is a constant. */
5521 if (GET_CODE (op0) == AND
5522 && rtx_equal_p (XEXP (op0, 1), op1)
5523 && ! side_effects_p (op1))
5524 return gen_binary (AND, mode,
5525 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5528 else if (GET_CODE (op0) == AND
5529 && rtx_equal_p (XEXP (op0, 0), op1)
5530 && ! side_effects_p (op1))
5531 return gen_binary (AND, mode,
5532 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5535 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5536 comparison if STORE_FLAG_VALUE is 1. */
5537 if (STORE_FLAG_VALUE == 1
5538 && op1 == const1_rtx
5539 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5540 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5544 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5545 is (lt foo (const_int 0)), so we can perform the above
5546 simplification if STORE_FLAG_VALUE is 1. */
5548 if (STORE_FLAG_VALUE == 1
5549 && op1 == const1_rtx
5550 && GET_CODE (op0) == LSHIFTRT
5551 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5552 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5553 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5555 /* (xor (comparison foo bar) (const_int sign-bit))
5556 when STORE_FLAG_VALUE is the sign bit. */
5557 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5558 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5559 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5560 && op1 == const_true_rtx
5561 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5562 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5575 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5576 operations" because they can be replaced with two more basic operations.
5577 ZERO_EXTEND is also considered "compound" because it can be replaced with
5578 an AND operation, which is simpler, though only one operation.
5580 The function expand_compound_operation is called with an rtx expression
5581 and will convert it to the appropriate shifts and AND operations,
5582 simplifying at each stage.
5584 The function make_compound_operation is called to convert an expression
5585 consisting of shifts and ANDs into the equivalent compound expression.
5586 It is the inverse of this function, loosely speaking. */
5589 expand_compound_operation (rtx x)
5591 unsigned HOST_WIDE_INT pos = 0, len;
5593 unsigned int modewidth;
5596 switch (GET_CODE (x))
5601 /* We can't necessarily use a const_int for a multiword mode;
5602 it depends on implicitly extending the value.
5603 Since we don't know the right way to extend it,
5604 we can't tell whether the implicit way is right.
5606 Even for a mode that is no wider than a const_int,
5607 we can't win, because we need to sign extend one of its bits through
5608 the rest of it, and we don't know which bit. */
5609 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5612 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5613 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5614 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5615 reloaded. If not for that, MEM's would very rarely be safe.
5617 Reject MODEs bigger than a word, because we might not be able
5618 to reference a two-register group starting with an arbitrary register
5619 (and currently gen_lowpart might crash for a SUBREG). */
5621 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5624 /* Reject MODEs that aren't scalar integers because turning vector
5625 or complex modes into shifts causes problems. */
5627 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5630 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5631 /* If the inner object has VOIDmode (the only way this can happen
5632 is if it is an ASM_OPERANDS), we can't do anything since we don't
5633 know how much masking to do. */
5642 /* If the operand is a CLOBBER, just return it. */
5643 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5646 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5647 || GET_CODE (XEXP (x, 2)) != CONST_INT
5648 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5651 /* Reject MODEs that aren't scalar integers because turning vector
5652 or complex modes into shifts causes problems. */
5654 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5657 len = INTVAL (XEXP (x, 1));
5658 pos = INTVAL (XEXP (x, 2));
5660 /* If this goes outside the object being extracted, replace the object
5661 with a (use (mem ...)) construct that only combine understands
5662 and is used only for this purpose. */
5663 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5664 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5666 if (BITS_BIG_ENDIAN)
5667 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5674 /* Convert sign extension to zero extension, if we know that the high
5675 bit is not set, as this is easier to optimize. It will be converted
5676 back to cheaper alternative in make_extraction. */
5677 if (GET_CODE (x) == SIGN_EXTEND
5678 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5679 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5680 & ~(((unsigned HOST_WIDE_INT)
5681 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5685 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5686 rtx temp2 = expand_compound_operation (temp);
5688 /* Make sure this is a profitable operation. */
5689 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5691 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5697 /* We can optimize some special cases of ZERO_EXTEND. */
5698 if (GET_CODE (x) == ZERO_EXTEND)
5700 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5701 know that the last value didn't have any inappropriate bits
5703 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5704 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5705 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5706 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5707 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5708 return XEXP (XEXP (x, 0), 0);
5710 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5711 if (GET_CODE (XEXP (x, 0)) == SUBREG
5712 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5713 && subreg_lowpart_p (XEXP (x, 0))
5714 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5715 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5716 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5717 return SUBREG_REG (XEXP (x, 0));
5719 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5720 is a comparison and STORE_FLAG_VALUE permits. This is like
5721 the first case, but it works even when GET_MODE (x) is larger
5722 than HOST_WIDE_INT. */
5723 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5724 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5725 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5726 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5727 <= HOST_BITS_PER_WIDE_INT)
5728 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5729 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5730 return XEXP (XEXP (x, 0), 0);
5732 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5733 if (GET_CODE (XEXP (x, 0)) == SUBREG
5734 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5735 && subreg_lowpart_p (XEXP (x, 0))
5736 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5737 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5738 <= HOST_BITS_PER_WIDE_INT)
5739 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5740 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5741 return SUBREG_REG (XEXP (x, 0));
5745 /* If we reach here, we want to return a pair of shifts. The inner
5746 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5747 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5748 logical depending on the value of UNSIGNEDP.
5750 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5751 converted into an AND of a shift.
5753 We must check for the case where the left shift would have a negative
5754 count. This can happen in a case like (x >> 31) & 255 on machines
5755 that can't shift by a constant. On those machines, we would first
5756 combine the shift with the AND to produce a variable-position
5757 extraction. Then the constant of 31 would be substituted in to produce
5758 a such a position. */
5760 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5761 if (modewidth + len >= pos)
5762 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5764 simplify_shift_const (NULL_RTX, ASHIFT,
5767 modewidth - pos - len),
5770 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5771 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5772 simplify_shift_const (NULL_RTX, LSHIFTRT,
5775 ((HOST_WIDE_INT) 1 << len) - 1);
5777 /* Any other cases we can't handle. */
5780 /* If we couldn't do this for some reason, return the original
5782 if (GET_CODE (tem) == CLOBBER)
5788 /* X is a SET which contains an assignment of one object into
5789 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5790 or certain SUBREGS). If possible, convert it into a series of
5793 We half-heartedly support variable positions, but do not at all
5794 support variable lengths. */
5797 expand_field_assignment (rtx x)
5800 rtx pos; /* Always counts from low bit. */
5803 enum machine_mode compute_mode;
5805 /* Loop until we find something we can't simplify. */
5808 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5809 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5811 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5812 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5813 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5815 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5816 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5818 inner = XEXP (SET_DEST (x), 0);
5819 len = INTVAL (XEXP (SET_DEST (x), 1));
5820 pos = XEXP (SET_DEST (x), 2);
5822 /* If the position is constant and spans the width of INNER,
5823 surround INNER with a USE to indicate this. */
5824 if (GET_CODE (pos) == CONST_INT
5825 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5826 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5828 if (BITS_BIG_ENDIAN)
5830 if (GET_CODE (pos) == CONST_INT)
5831 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5833 else if (GET_CODE (pos) == MINUS
5834 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5835 && (INTVAL (XEXP (pos, 1))
5836 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5837 /* If position is ADJUST - X, new position is X. */
5838 pos = XEXP (pos, 0);
5840 pos = gen_binary (MINUS, GET_MODE (pos),
5841 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5847 /* A SUBREG between two modes that occupy the same numbers of words
5848 can be done by moving the SUBREG to the source. */
5849 else if (GET_CODE (SET_DEST (x)) == SUBREG
5850 /* We need SUBREGs to compute nonzero_bits properly. */
5851 && nonzero_sign_valid
5852 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5853 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5854 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5855 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5857 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5858 gen_lowpart_for_combine
5859 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5866 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5867 inner = SUBREG_REG (inner);
5869 compute_mode = GET_MODE (inner);
5871 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5872 if (! SCALAR_INT_MODE_P (compute_mode))
5874 enum machine_mode imode;
5876 /* Don't do anything for vector or complex integral types. */
5877 if (! FLOAT_MODE_P (compute_mode))
5880 /* Try to find an integral mode to pun with. */
5881 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5882 if (imode == BLKmode)
5885 compute_mode = imode;
5886 inner = gen_lowpart_for_combine (imode, inner);
5889 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5890 if (len < HOST_BITS_PER_WIDE_INT)
5891 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5895 /* Now compute the equivalent expression. Make a copy of INNER
5896 for the SET_DEST in case it is a MEM into which we will substitute;
5897 we don't want shared RTL in that case. */
5899 (VOIDmode, copy_rtx (inner),
5900 gen_binary (IOR, compute_mode,
5901 gen_binary (AND, compute_mode,
5902 simplify_gen_unary (NOT, compute_mode,
5908 gen_binary (ASHIFT, compute_mode,
5909 gen_binary (AND, compute_mode,
5910 gen_lowpart_for_combine
5911 (compute_mode, SET_SRC (x)),
5919 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5920 it is an RTX that represents a variable starting position; otherwise,
5921 POS is the (constant) starting bit position (counted from the LSB).
5923 INNER may be a USE. This will occur when we started with a bitfield
5924 that went outside the boundary of the object in memory, which is
5925 allowed on most machines. To isolate this case, we produce a USE
5926 whose mode is wide enough and surround the MEM with it. The only
5927 code that understands the USE is this routine. If it is not removed,
5928 it will cause the resulting insn not to match.
5930 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5933 IN_DEST is nonzero if this is a reference in the destination of a
5934 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5935 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5938 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5939 ZERO_EXTRACT should be built even for bits starting at bit 0.
5941 MODE is the desired mode of the result (if IN_DEST == 0).
5943 The result is an RTX for the extraction or NULL_RTX if the target
5947 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5948 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5949 int in_dest, int in_compare)
5951 /* This mode describes the size of the storage area
5952 to fetch the overall value from. Within that, we
5953 ignore the POS lowest bits, etc. */
5954 enum machine_mode is_mode = GET_MODE (inner);
5955 enum machine_mode inner_mode;
5956 enum machine_mode wanted_inner_mode = byte_mode;
5957 enum machine_mode wanted_inner_reg_mode = word_mode;
5958 enum machine_mode pos_mode = word_mode;
5959 enum machine_mode extraction_mode = word_mode;
5960 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5963 rtx orig_pos_rtx = pos_rtx;
5964 HOST_WIDE_INT orig_pos;
5966 /* Get some information about INNER and get the innermost object. */
5967 if (GET_CODE (inner) == USE)
5968 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5969 /* We don't need to adjust the position because we set up the USE
5970 to pretend that it was a full-word object. */
5971 spans_byte = 1, inner = XEXP (inner, 0);
5972 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5974 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5975 consider just the QI as the memory to extract from.
5976 The subreg adds or removes high bits; its mode is
5977 irrelevant to the meaning of this extraction,
5978 since POS and LEN count from the lsb. */
5979 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5980 is_mode = GET_MODE (SUBREG_REG (inner));
5981 inner = SUBREG_REG (inner);
5983 else if (GET_CODE (inner) == ASHIFT
5984 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5985 && pos_rtx == 0 && pos == 0
5986 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5988 /* We're extracting the least significant bits of an rtx
5989 (ashift X (const_int C)), where LEN > C. Extract the
5990 least significant (LEN - C) bits of X, giving an rtx
5991 whose mode is MODE, then shift it left C times. */
5992 new = make_extraction (mode, XEXP (inner, 0),
5993 0, 0, len - INTVAL (XEXP (inner, 1)),
5994 unsignedp, in_dest, in_compare);
5996 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5999 inner_mode = GET_MODE (inner);
6001 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6002 pos = INTVAL (pos_rtx), pos_rtx = 0;
6004 /* See if this can be done without an extraction. We never can if the
6005 width of the field is not the same as that of some integer mode. For
6006 registers, we can only avoid the extraction if the position is at the
6007 low-order bit and this is either not in the destination or we have the
6008 appropriate STRICT_LOW_PART operation available.
6010 For MEM, we can avoid an extract if the field starts on an appropriate
6011 boundary and we can change the mode of the memory reference. However,
6012 we cannot directly access the MEM if we have a USE and the underlying
6013 MEM is not TMODE. This combination means that MEM was being used in a
6014 context where bits outside its mode were being referenced; that is only
6015 valid in bit-field insns. */
6017 if (tmode != BLKmode
6018 && ! (spans_byte && inner_mode != tmode)
6019 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6020 && GET_CODE (inner) != MEM
6022 || (GET_CODE (inner) == REG
6023 && have_insn_for (STRICT_LOW_PART, tmode))))
6024 || (GET_CODE (inner) == MEM && pos_rtx == 0
6026 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6027 : BITS_PER_UNIT)) == 0
6028 /* We can't do this if we are widening INNER_MODE (it
6029 may not be aligned, for one thing). */
6030 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6031 && (inner_mode == tmode
6032 || (! mode_dependent_address_p (XEXP (inner, 0))
6033 && ! MEM_VOLATILE_P (inner))))))
6035 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6036 field. If the original and current mode are the same, we need not
6037 adjust the offset. Otherwise, we do if bytes big endian.
6039 If INNER is not a MEM, get a piece consisting of just the field
6040 of interest (in this case POS % BITS_PER_WORD must be 0). */
6042 if (GET_CODE (inner) == MEM)
6044 HOST_WIDE_INT offset;
6046 /* POS counts from lsb, but make OFFSET count in memory order. */
6047 if (BYTES_BIG_ENDIAN)
6048 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6050 offset = pos / BITS_PER_UNIT;
6052 new = adjust_address_nv (inner, tmode, offset);
6054 else if (GET_CODE (inner) == REG)
6056 if (tmode != inner_mode)
6060 /* We can't call gen_lowpart_for_combine here since we always want
6061 a SUBREG and it would sometimes return a new hard register. */
6062 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6064 if (WORDS_BIG_ENDIAN
6065 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6066 final_word = ((GET_MODE_SIZE (inner_mode)
6067 - GET_MODE_SIZE (tmode))
6068 / UNITS_PER_WORD) - final_word;
6070 final_word *= UNITS_PER_WORD;
6071 if (BYTES_BIG_ENDIAN &&
6072 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6073 final_word += (GET_MODE_SIZE (inner_mode)
6074 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6076 /* Avoid creating invalid subregs, for example when
6077 simplifying (x>>32)&255. */
6078 if (final_word >= GET_MODE_SIZE (inner_mode))
6081 new = gen_rtx_SUBREG (tmode, inner, final_word);
6084 new = gen_lowpart_for_combine (tmode, inner);
6090 new = force_to_mode (inner, tmode,
6091 len >= HOST_BITS_PER_WIDE_INT
6092 ? ~(unsigned HOST_WIDE_INT) 0
6093 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6096 /* If this extraction is going into the destination of a SET,
6097 make a STRICT_LOW_PART unless we made a MEM. */
6100 return (GET_CODE (new) == MEM ? new
6101 : (GET_CODE (new) != SUBREG
6102 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6103 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6108 if (GET_CODE (new) == CONST_INT)
6109 return gen_int_mode (INTVAL (new), mode);
6111 /* If we know that no extraneous bits are set, and that the high
6112 bit is not set, convert the extraction to the cheaper of
6113 sign and zero extension, that are equivalent in these cases. */
6114 if (flag_expensive_optimizations
6115 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6116 && ((nonzero_bits (new, tmode)
6117 & ~(((unsigned HOST_WIDE_INT)
6118 GET_MODE_MASK (tmode))
6122 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6123 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6125 /* Prefer ZERO_EXTENSION, since it gives more information to
6127 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6132 /* Otherwise, sign- or zero-extend unless we already are in the
6135 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6139 /* Unless this is a COMPARE or we have a funny memory reference,
6140 don't do anything with zero-extending field extracts starting at
6141 the low-order bit since they are simple AND operations. */
6142 if (pos_rtx == 0 && pos == 0 && ! in_dest
6143 && ! in_compare && ! spans_byte && unsignedp)
6146 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6147 we would be spanning bytes or if the position is not a constant and the
6148 length is not 1. In all other cases, we would only be going outside
6149 our object in cases when an original shift would have been
6151 if (! spans_byte && GET_CODE (inner) == MEM
6152 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6153 || (pos_rtx != 0 && len != 1)))
6156 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6157 and the mode for the result. */
6158 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6160 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6161 pos_mode = mode_for_extraction (EP_insv, 2);
6162 extraction_mode = mode_for_extraction (EP_insv, 3);
6165 if (! in_dest && unsignedp
6166 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6168 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6169 pos_mode = mode_for_extraction (EP_extzv, 3);
6170 extraction_mode = mode_for_extraction (EP_extzv, 0);
6173 if (! in_dest && ! unsignedp
6174 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6176 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6177 pos_mode = mode_for_extraction (EP_extv, 3);
6178 extraction_mode = mode_for_extraction (EP_extv, 0);
6181 /* Never narrow an object, since that might not be safe. */
6183 if (mode != VOIDmode
6184 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6185 extraction_mode = mode;
6187 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6188 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6189 pos_mode = GET_MODE (pos_rtx);
6191 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6192 if we have to change the mode of memory and cannot, the desired mode is
6194 if (GET_CODE (inner) != MEM)
6195 wanted_inner_mode = wanted_inner_reg_mode;
6196 else if (inner_mode != wanted_inner_mode
6197 && (mode_dependent_address_p (XEXP (inner, 0))
6198 || MEM_VOLATILE_P (inner)))
6199 wanted_inner_mode = extraction_mode;
6203 if (BITS_BIG_ENDIAN)
6205 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6206 BITS_BIG_ENDIAN style. If position is constant, compute new
6207 position. Otherwise, build subtraction.
6208 Note that POS is relative to the mode of the original argument.
6209 If it's a MEM we need to recompute POS relative to that.
6210 However, if we're extracting from (or inserting into) a register,
6211 we want to recompute POS relative to wanted_inner_mode. */
6212 int width = (GET_CODE (inner) == MEM
6213 ? GET_MODE_BITSIZE (is_mode)
6214 : GET_MODE_BITSIZE (wanted_inner_mode));
6217 pos = width - len - pos;
6220 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6221 /* POS may be less than 0 now, but we check for that below.
6222 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6225 /* If INNER has a wider mode, make it smaller. If this is a constant
6226 extract, try to adjust the byte to point to the byte containing
6228 if (wanted_inner_mode != VOIDmode
6229 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6230 && ((GET_CODE (inner) == MEM
6231 && (inner_mode == wanted_inner_mode
6232 || (! mode_dependent_address_p (XEXP (inner, 0))
6233 && ! MEM_VOLATILE_P (inner))))))
6237 /* The computations below will be correct if the machine is big
6238 endian in both bits and bytes or little endian in bits and bytes.
6239 If it is mixed, we must adjust. */
6241 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6242 adjust OFFSET to compensate. */
6243 if (BYTES_BIG_ENDIAN
6245 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6246 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6248 /* If this is a constant position, we can move to the desired byte. */
6251 offset += pos / BITS_PER_UNIT;
6252 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6255 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6257 && is_mode != wanted_inner_mode)
6258 offset = (GET_MODE_SIZE (is_mode)
6259 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6261 if (offset != 0 || inner_mode != wanted_inner_mode)
6262 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6265 /* If INNER is not memory, we can always get it into the proper mode. If we
6266 are changing its mode, POS must be a constant and smaller than the size
6268 else if (GET_CODE (inner) != MEM)
6270 if (GET_MODE (inner) != wanted_inner_mode
6272 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6275 inner = force_to_mode (inner, wanted_inner_mode,
6277 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6278 ? ~(unsigned HOST_WIDE_INT) 0
6279 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6284 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6285 have to zero extend. Otherwise, we can just use a SUBREG. */
6287 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6289 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6291 /* If we know that no extraneous bits are set, and that the high
6292 bit is not set, convert extraction to cheaper one - either
6293 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6295 if (flag_expensive_optimizations
6296 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6297 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6298 & ~(((unsigned HOST_WIDE_INT)
6299 GET_MODE_MASK (GET_MODE (pos_rtx)))
6303 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6305 /* Prefer ZERO_EXTENSION, since it gives more information to
6307 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6312 else if (pos_rtx != 0
6313 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6314 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6316 /* Make POS_RTX unless we already have it and it is correct. If we don't
6317 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6319 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6320 pos_rtx = orig_pos_rtx;
6322 else if (pos_rtx == 0)
6323 pos_rtx = GEN_INT (pos);
6325 /* Make the required operation. See if we can use existing rtx. */
6326 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6327 extraction_mode, inner, GEN_INT (len), pos_rtx);
6329 new = gen_lowpart_for_combine (mode, new);
6334 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6335 with any other operations in X. Return X without that shift if so. */
6338 extract_left_shift (rtx x, int count)
6340 enum rtx_code code = GET_CODE (x);
6341 enum machine_mode mode = GET_MODE (x);
6347 /* This is the shift itself. If it is wide enough, we will return
6348 either the value being shifted if the shift count is equal to
6349 COUNT or a shift for the difference. */
6350 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6351 && INTVAL (XEXP (x, 1)) >= count)
6352 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6353 INTVAL (XEXP (x, 1)) - count);
6357 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6358 return simplify_gen_unary (code, mode, tem, mode);
6362 case PLUS: case IOR: case XOR: case AND:
6363 /* If we can safely shift this constant and we find the inner shift,
6364 make a new operation. */
6365 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6366 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6367 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6368 return gen_binary (code, mode, tem,
6369 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6380 /* Look at the expression rooted at X. Look for expressions
6381 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6382 Form these expressions.
6384 Return the new rtx, usually just X.
6386 Also, for machines like the VAX that don't have logical shift insns,
6387 try to convert logical to arithmetic shift operations in cases where
6388 they are equivalent. This undoes the canonicalizations to logical
6389 shifts done elsewhere.
6391 We try, as much as possible, to re-use rtl expressions to save memory.
6393 IN_CODE says what kind of expression we are processing. Normally, it is
6394 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6395 being kludges), it is MEM. When processing the arguments of a comparison
6396 or a COMPARE against zero, it is COMPARE. */
6399 make_compound_operation (rtx x, enum rtx_code in_code)
6401 enum rtx_code code = GET_CODE (x);
6402 enum machine_mode mode = GET_MODE (x);
6403 int mode_width = GET_MODE_BITSIZE (mode);
6405 enum rtx_code next_code;
6411 /* Select the code to be used in recursive calls. Once we are inside an
6412 address, we stay there. If we have a comparison, set to COMPARE,
6413 but once inside, go back to our default of SET. */
6415 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6416 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6417 && XEXP (x, 1) == const0_rtx) ? COMPARE
6418 : in_code == COMPARE ? SET : in_code);
6420 /* Process depending on the code of this operation. If NEW is set
6421 nonzero, it will be returned. */
6426 /* Convert shifts by constants into multiplications if inside
6428 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6429 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6430 && INTVAL (XEXP (x, 1)) >= 0)
6432 new = make_compound_operation (XEXP (x, 0), next_code);
6433 new = gen_rtx_MULT (mode, new,
6434 GEN_INT ((HOST_WIDE_INT) 1
6435 << INTVAL (XEXP (x, 1))));
6440 /* If the second operand is not a constant, we can't do anything
6442 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6445 /* If the constant is a power of two minus one and the first operand
6446 is a logical right shift, make an extraction. */
6447 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6448 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6450 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6451 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6452 0, in_code == COMPARE);
6455 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6456 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6457 && subreg_lowpart_p (XEXP (x, 0))
6458 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6459 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6461 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6463 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6464 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6465 0, in_code == COMPARE);
6467 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6468 else if ((GET_CODE (XEXP (x, 0)) == XOR
6469 || GET_CODE (XEXP (x, 0)) == IOR)
6470 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6471 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6472 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6474 /* Apply the distributive law, and then try to make extractions. */
6475 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6476 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6478 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6480 new = make_compound_operation (new, in_code);
6483 /* If we are have (and (rotate X C) M) and C is larger than the number
6484 of bits in M, this is an extraction. */
6486 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6487 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6488 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6489 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6491 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6492 new = make_extraction (mode, new,
6493 (GET_MODE_BITSIZE (mode)
6494 - INTVAL (XEXP (XEXP (x, 0), 1))),
6495 NULL_RTX, i, 1, 0, in_code == COMPARE);
6498 /* On machines without logical shifts, if the operand of the AND is
6499 a logical shift and our mask turns off all the propagated sign
6500 bits, we can replace the logical shift with an arithmetic shift. */
6501 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6502 && !have_insn_for (LSHIFTRT, mode)
6503 && have_insn_for (ASHIFTRT, mode)
6504 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6505 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6506 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6507 && mode_width <= HOST_BITS_PER_WIDE_INT)
6509 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6511 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6512 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6514 gen_rtx_ASHIFTRT (mode,
6515 make_compound_operation
6516 (XEXP (XEXP (x, 0), 0), next_code),
6517 XEXP (XEXP (x, 0), 1)));
6520 /* If the constant is one less than a power of two, this might be
6521 representable by an extraction even if no shift is present.
6522 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6523 we are in a COMPARE. */
6524 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6525 new = make_extraction (mode,
6526 make_compound_operation (XEXP (x, 0),
6528 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6530 /* If we are in a comparison and this is an AND with a power of two,
6531 convert this into the appropriate bit extract. */
6532 else if (in_code == COMPARE
6533 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6534 new = make_extraction (mode,
6535 make_compound_operation (XEXP (x, 0),
6537 i, NULL_RTX, 1, 1, 0, 1);
6542 /* If the sign bit is known to be zero, replace this with an
6543 arithmetic shift. */
6544 if (have_insn_for (ASHIFTRT, mode)
6545 && ! have_insn_for (LSHIFTRT, mode)
6546 && mode_width <= HOST_BITS_PER_WIDE_INT
6547 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6549 new = gen_rtx_ASHIFTRT (mode,
6550 make_compound_operation (XEXP (x, 0),
6556 /* ... fall through ... */
6562 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6563 this is a SIGN_EXTRACT. */
6564 if (GET_CODE (rhs) == CONST_INT
6565 && GET_CODE (lhs) == ASHIFT
6566 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6567 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6569 new = make_compound_operation (XEXP (lhs, 0), next_code);
6570 new = make_extraction (mode, new,
6571 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6572 NULL_RTX, mode_width - INTVAL (rhs),
6573 code == LSHIFTRT, 0, in_code == COMPARE);
6577 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6578 If so, try to merge the shifts into a SIGN_EXTEND. We could
6579 also do this for some cases of SIGN_EXTRACT, but it doesn't
6580 seem worth the effort; the case checked for occurs on Alpha. */
6582 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6583 && ! (GET_CODE (lhs) == SUBREG
6584 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6585 && GET_CODE (rhs) == CONST_INT
6586 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6587 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6588 new = make_extraction (mode, make_compound_operation (new, next_code),
6589 0, NULL_RTX, mode_width - INTVAL (rhs),
6590 code == LSHIFTRT, 0, in_code == COMPARE);
6595 /* Call ourselves recursively on the inner expression. If we are
6596 narrowing the object and it has a different RTL code from
6597 what it originally did, do this SUBREG as a force_to_mode. */
6599 tem = make_compound_operation (SUBREG_REG (x), in_code);
6600 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6601 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6602 && subreg_lowpart_p (x))
6604 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6607 /* If we have something other than a SUBREG, we might have
6608 done an expansion, so rerun ourselves. */
6609 if (GET_CODE (newer) != SUBREG)
6610 newer = make_compound_operation (newer, in_code);
6615 /* If this is a paradoxical subreg, and the new code is a sign or
6616 zero extension, omit the subreg and widen the extension. If it
6617 is a regular subreg, we can still get rid of the subreg by not
6618 widening so much, or in fact removing the extension entirely. */
6619 if ((GET_CODE (tem) == SIGN_EXTEND
6620 || GET_CODE (tem) == ZERO_EXTEND)
6621 && subreg_lowpart_p (x))
6623 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6624 || (GET_MODE_SIZE (mode) >
6625 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6627 if (! SCALAR_INT_MODE_P (mode))
6629 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6632 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6643 x = gen_lowpart_for_combine (mode, new);
6644 code = GET_CODE (x);
6647 /* Now recursively process each operand of this operation. */
6648 fmt = GET_RTX_FORMAT (code);
6649 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6652 new = make_compound_operation (XEXP (x, i), next_code);
6653 SUBST (XEXP (x, i), new);
6659 /* Given M see if it is a value that would select a field of bits
6660 within an item, but not the entire word. Return -1 if not.
6661 Otherwise, return the starting position of the field, where 0 is the
6664 *PLEN is set to the length of the field. */
6667 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6669 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6670 int pos = exact_log2 (m & -m);
6676 /* Now shift off the low-order zero bits and see if we have a power of
6678 len = exact_log2 ((m >> pos) + 1);
6687 /* See if X can be simplified knowing that we will only refer to it in
6688 MODE and will only refer to those bits that are nonzero in MASK.
6689 If other bits are being computed or if masking operations are done
6690 that select a superset of the bits in MASK, they can sometimes be
6693 Return a possibly simplified expression, but always convert X to
6694 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6696 Also, if REG is nonzero and X is a register equal in value to REG,
6699 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6700 are all off in X. This is used when X will be complemented, by either
6701 NOT, NEG, or XOR. */
6704 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6705 rtx reg, int just_select)
6707 enum rtx_code code = GET_CODE (x);
6708 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6709 enum machine_mode op_mode;
6710 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6713 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6714 code below will do the wrong thing since the mode of such an
6715 expression is VOIDmode.
6717 Also do nothing if X is a CLOBBER; this can happen if X was
6718 the return value from a call to gen_lowpart_for_combine. */
6719 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6722 /* We want to perform the operation is its present mode unless we know
6723 that the operation is valid in MODE, in which case we do the operation
6725 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6726 && have_insn_for (code, mode))
6727 ? mode : GET_MODE (x));
6729 /* It is not valid to do a right-shift in a narrower mode
6730 than the one it came in with. */
6731 if ((code == LSHIFTRT || code == ASHIFTRT)
6732 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6733 op_mode = GET_MODE (x);
6735 /* Truncate MASK to fit OP_MODE. */
6737 mask &= GET_MODE_MASK (op_mode);
6739 /* When we have an arithmetic operation, or a shift whose count we
6740 do not know, we need to assume that all bits up to the highest-order
6741 bit in MASK will be needed. This is how we form such a mask. */
6742 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6743 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6745 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6748 /* Determine what bits of X are guaranteed to be (non)zero. */
6749 nonzero = nonzero_bits (x, mode);
6751 /* If none of the bits in X are needed, return a zero. */
6752 if (! just_select && (nonzero & mask) == 0)
6755 /* If X is a CONST_INT, return a new one. Do this here since the
6756 test below will fail. */
6757 if (GET_CODE (x) == CONST_INT)
6759 if (SCALAR_INT_MODE_P (mode))
6760 return gen_int_mode (INTVAL (x) & mask, mode);
6763 x = GEN_INT (INTVAL (x) & mask);
6764 return gen_lowpart_common (mode, x);
6768 /* If X is narrower than MODE and we want all the bits in X's mode, just
6769 get X in the proper mode. */
6770 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6771 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6772 return gen_lowpart_for_combine (mode, x);
6774 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6775 MASK are already known to be zero in X, we need not do anything. */
6776 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6782 /* If X is a (clobber (const_int)), return it since we know we are
6783 generating something that won't match. */
6787 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6788 spanned the boundary of the MEM. If we are now masking so it is
6789 within that boundary, we don't need the USE any more. */
6790 if (! BITS_BIG_ENDIAN
6791 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6792 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6799 x = expand_compound_operation (x);
6800 if (GET_CODE (x) != code)
6801 return force_to_mode (x, mode, mask, reg, next_select);
6805 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6806 || rtx_equal_p (reg, get_last_value (x))))
6811 if (subreg_lowpart_p (x)
6812 /* We can ignore the effect of this SUBREG if it narrows the mode or
6813 if the constant masks to zero all the bits the mode doesn't
6815 && ((GET_MODE_SIZE (GET_MODE (x))
6816 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6818 & GET_MODE_MASK (GET_MODE (x))
6819 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6820 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6824 /* If this is an AND with a constant, convert it into an AND
6825 whose constant is the AND of that constant with MASK. If it
6826 remains an AND of MASK, delete it since it is redundant. */
6828 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6830 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6831 mask & INTVAL (XEXP (x, 1)));
6833 /* If X is still an AND, see if it is an AND with a mask that
6834 is just some low-order bits. If so, and it is MASK, we don't
6837 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6838 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6842 /* If it remains an AND, try making another AND with the bits
6843 in the mode mask that aren't in MASK turned on. If the
6844 constant in the AND is wide enough, this might make a
6845 cheaper constant. */
6847 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6848 && GET_MODE_MASK (GET_MODE (x)) != mask
6849 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6851 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6852 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6853 int width = GET_MODE_BITSIZE (GET_MODE (x));
6856 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6857 number, sign extend it. */
6858 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6859 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6860 cval |= (HOST_WIDE_INT) -1 << width;
6862 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6863 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6873 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6874 low-order bits (as in an alignment operation) and FOO is already
6875 aligned to that boundary, mask C1 to that boundary as well.
6876 This may eliminate that PLUS and, later, the AND. */
6879 unsigned int width = GET_MODE_BITSIZE (mode);
6880 unsigned HOST_WIDE_INT smask = mask;
6882 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6883 number, sign extend it. */
6885 if (width < HOST_BITS_PER_WIDE_INT
6886 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6887 smask |= (HOST_WIDE_INT) -1 << width;
6889 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6890 && exact_log2 (- smask) >= 0
6891 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6892 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6893 return force_to_mode (plus_constant (XEXP (x, 0),
6894 (INTVAL (XEXP (x, 1)) & smask)),
6895 mode, smask, reg, next_select);
6898 /* ... fall through ... */
6901 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6902 most significant bit in MASK since carries from those bits will
6903 affect the bits we are interested in. */
6908 /* If X is (minus C Y) where C's least set bit is larger than any bit
6909 in the mask, then we may replace with (neg Y). */
6910 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6911 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6912 & -INTVAL (XEXP (x, 0))))
6915 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6917 return force_to_mode (x, mode, mask, reg, next_select);
6920 /* Similarly, if C contains every bit in the fuller_mask, then we may
6921 replace with (not Y). */
6922 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6923 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6924 == INTVAL (XEXP (x, 0))))
6926 x = simplify_gen_unary (NOT, GET_MODE (x),
6927 XEXP (x, 1), GET_MODE (x));
6928 return force_to_mode (x, mode, mask, reg, next_select);
6936 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6937 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6938 operation which may be a bitfield extraction. Ensure that the
6939 constant we form is not wider than the mode of X. */
6941 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6942 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6943 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6944 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6945 && GET_CODE (XEXP (x, 1)) == CONST_INT
6946 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6947 + floor_log2 (INTVAL (XEXP (x, 1))))
6948 < GET_MODE_BITSIZE (GET_MODE (x)))
6949 && (INTVAL (XEXP (x, 1))
6950 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6952 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6953 << INTVAL (XEXP (XEXP (x, 0), 1)));
6954 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6955 XEXP (XEXP (x, 0), 0), temp);
6956 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6957 XEXP (XEXP (x, 0), 1));
6958 return force_to_mode (x, mode, mask, reg, next_select);
6962 /* For most binary operations, just propagate into the operation and
6963 change the mode if we have an operation of that mode. */
6965 op0 = gen_lowpart_for_combine (op_mode,
6966 force_to_mode (XEXP (x, 0), mode, mask,
6968 op1 = gen_lowpart_for_combine (op_mode,
6969 force_to_mode (XEXP (x, 1), mode, mask,
6972 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6973 x = gen_binary (code, op_mode, op0, op1);
6977 /* For left shifts, do the same, but just for the first operand.
6978 However, we cannot do anything with shifts where we cannot
6979 guarantee that the counts are smaller than the size of the mode
6980 because such a count will have a different meaning in a
6983 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6984 && INTVAL (XEXP (x, 1)) >= 0
6985 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6986 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6987 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6988 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6991 /* If the shift count is a constant and we can do arithmetic in
6992 the mode of the shift, refine which bits we need. Otherwise, use the
6993 conservative form of the mask. */
6994 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6995 && INTVAL (XEXP (x, 1)) >= 0
6996 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6997 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6998 mask >>= INTVAL (XEXP (x, 1));
7002 op0 = gen_lowpart_for_combine (op_mode,
7003 force_to_mode (XEXP (x, 0), op_mode,
7004 mask, reg, next_select));
7006 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7007 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7011 /* Here we can only do something if the shift count is a constant,
7012 this shift constant is valid for the host, and we can do arithmetic
7015 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7016 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7017 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7019 rtx inner = XEXP (x, 0);
7020 unsigned HOST_WIDE_INT inner_mask;
7022 /* Select the mask of the bits we need for the shift operand. */
7023 inner_mask = mask << INTVAL (XEXP (x, 1));
7025 /* We can only change the mode of the shift if we can do arithmetic
7026 in the mode of the shift and INNER_MASK is no wider than the
7027 width of OP_MODE. */
7028 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7029 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7030 op_mode = GET_MODE (x);
7032 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7034 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7035 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7038 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7039 shift and AND produces only copies of the sign bit (C2 is one less
7040 than a power of two), we can do this with just a shift. */
7042 if (GET_CODE (x) == LSHIFTRT
7043 && GET_CODE (XEXP (x, 1)) == CONST_INT
7044 /* The shift puts one of the sign bit copies in the least significant
7046 && ((INTVAL (XEXP (x, 1))
7047 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7048 >= GET_MODE_BITSIZE (GET_MODE (x)))
7049 && exact_log2 (mask + 1) >= 0
7050 /* Number of bits left after the shift must be more than the mask
7052 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7053 <= GET_MODE_BITSIZE (GET_MODE (x)))
7054 /* Must be more sign bit copies than the mask needs. */
7055 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7056 >= exact_log2 (mask + 1)))
7057 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7058 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7059 - exact_log2 (mask + 1)));
7064 /* If we are just looking for the sign bit, we don't need this shift at
7065 all, even if it has a variable count. */
7066 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7067 && (mask == ((unsigned HOST_WIDE_INT) 1
7068 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7069 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7071 /* If this is a shift by a constant, get a mask that contains those bits
7072 that are not copies of the sign bit. We then have two cases: If
7073 MASK only includes those bits, this can be a logical shift, which may
7074 allow simplifications. If MASK is a single-bit field not within
7075 those bits, we are requesting a copy of the sign bit and hence can
7076 shift the sign bit to the appropriate location. */
7078 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7079 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7083 /* If the considered data is wider than HOST_WIDE_INT, we can't
7084 represent a mask for all its bits in a single scalar.
7085 But we only care about the lower bits, so calculate these. */
7087 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7089 nonzero = ~(HOST_WIDE_INT) 0;
7091 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7092 is the number of bits a full-width mask would have set.
7093 We need only shift if these are fewer than nonzero can
7094 hold. If not, we must keep all bits set in nonzero. */
7096 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7097 < HOST_BITS_PER_WIDE_INT)
7098 nonzero >>= INTVAL (XEXP (x, 1))
7099 + HOST_BITS_PER_WIDE_INT
7100 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7104 nonzero = GET_MODE_MASK (GET_MODE (x));
7105 nonzero >>= INTVAL (XEXP (x, 1));
7108 if ((mask & ~nonzero) == 0
7109 || (i = exact_log2 (mask)) >= 0)
7111 x = simplify_shift_const
7112 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7113 i < 0 ? INTVAL (XEXP (x, 1))
7114 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7116 if (GET_CODE (x) != ASHIFTRT)
7117 return force_to_mode (x, mode, mask, reg, next_select);
7121 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7122 even if the shift count isn't a constant. */
7124 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7128 /* If this is a zero- or sign-extension operation that just affects bits
7129 we don't care about, remove it. Be sure the call above returned
7130 something that is still a shift. */
7132 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7133 && GET_CODE (XEXP (x, 1)) == CONST_INT
7134 && INTVAL (XEXP (x, 1)) >= 0
7135 && (INTVAL (XEXP (x, 1))
7136 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7137 && GET_CODE (XEXP (x, 0)) == ASHIFT
7138 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7139 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7146 /* If the shift count is constant and we can do computations
7147 in the mode of X, compute where the bits we care about are.
7148 Otherwise, we can't do anything. Don't change the mode of
7149 the shift or propagate MODE into the shift, though. */
7150 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7151 && INTVAL (XEXP (x, 1)) >= 0)
7153 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7154 GET_MODE (x), GEN_INT (mask),
7156 if (temp && GET_CODE (temp) == CONST_INT)
7158 force_to_mode (XEXP (x, 0), GET_MODE (x),
7159 INTVAL (temp), reg, next_select));
7164 /* If we just want the low-order bit, the NEG isn't needed since it
7165 won't change the low-order bit. */
7167 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7169 /* We need any bits less significant than the most significant bit in
7170 MASK since carries from those bits will affect the bits we are
7176 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7177 same as the XOR case above. Ensure that the constant we form is not
7178 wider than the mode of X. */
7180 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7181 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7182 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7183 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7184 < GET_MODE_BITSIZE (GET_MODE (x)))
7185 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7187 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7189 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7190 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7192 return force_to_mode (x, mode, mask, reg, next_select);
7195 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7196 use the full mask inside the NOT. */
7200 op0 = gen_lowpart_for_combine (op_mode,
7201 force_to_mode (XEXP (x, 0), mode, mask,
7203 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7204 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7208 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7209 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7210 which is equal to STORE_FLAG_VALUE. */
7211 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7212 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7213 && (nonzero_bits (XEXP (x, 0), mode)
7214 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7215 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7220 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7221 written in a narrower mode. We play it safe and do not do so. */
7224 gen_lowpart_for_combine (GET_MODE (x),
7225 force_to_mode (XEXP (x, 1), mode,
7226 mask, reg, next_select)));
7228 gen_lowpart_for_combine (GET_MODE (x),
7229 force_to_mode (XEXP (x, 2), mode,
7230 mask, reg, next_select)));
7237 /* Ensure we return a value of the proper mode. */
7238 return gen_lowpart_for_combine (mode, x);
7241 /* Return nonzero if X is an expression that has one of two values depending on
7242 whether some other value is zero or nonzero. In that case, we return the
7243 value that is being tested, *PTRUE is set to the value if the rtx being
7244 returned has a nonzero value, and *PFALSE is set to the other alternative.
7246 If we return zero, we set *PTRUE and *PFALSE to X. */
7249 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7251 enum machine_mode mode = GET_MODE (x);
7252 enum rtx_code code = GET_CODE (x);
7253 rtx cond0, cond1, true0, true1, false0, false1;
7254 unsigned HOST_WIDE_INT nz;
7256 /* If we are comparing a value against zero, we are done. */
7257 if ((code == NE || code == EQ)
7258 && XEXP (x, 1) == const0_rtx)
7260 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7261 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7265 /* If this is a unary operation whose operand has one of two values, apply
7266 our opcode to compute those values. */
7267 else if (GET_RTX_CLASS (code) == '1'
7268 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7270 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7271 *pfalse = simplify_gen_unary (code, mode, false0,
7272 GET_MODE (XEXP (x, 0)));
7276 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7277 make can't possibly match and would suppress other optimizations. */
7278 else if (code == COMPARE)
7281 /* If this is a binary operation, see if either side has only one of two
7282 values. If either one does or if both do and they are conditional on
7283 the same value, compute the new true and false values. */
7284 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7285 || GET_RTX_CLASS (code) == '<')
7287 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7288 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7290 if ((cond0 != 0 || cond1 != 0)
7291 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7293 /* If if_then_else_cond returned zero, then true/false are the
7294 same rtl. We must copy one of them to prevent invalid rtl
7297 true0 = copy_rtx (true0);
7298 else if (cond1 == 0)
7299 true1 = copy_rtx (true1);
7301 *ptrue = gen_binary (code, mode, true0, true1);
7302 *pfalse = gen_binary (code, mode, false0, false1);
7303 return cond0 ? cond0 : cond1;
7306 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7307 operands is zero when the other is nonzero, and vice-versa,
7308 and STORE_FLAG_VALUE is 1 or -1. */
7310 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7311 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7313 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7315 rtx op0 = XEXP (XEXP (x, 0), 1);
7316 rtx op1 = XEXP (XEXP (x, 1), 1);
7318 cond0 = XEXP (XEXP (x, 0), 0);
7319 cond1 = XEXP (XEXP (x, 1), 0);
7321 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7322 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7323 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7324 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7325 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7326 || ((swap_condition (GET_CODE (cond0))
7327 == combine_reversed_comparison_code (cond1))
7328 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7329 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7330 && ! side_effects_p (x))
7332 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7333 *pfalse = gen_binary (MULT, mode,
7335 ? simplify_gen_unary (NEG, mode, op1,
7343 /* Similarly for MULT, AND and UMIN, except that for these the result
7345 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7346 && (code == MULT || code == AND || code == UMIN)
7347 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7349 cond0 = XEXP (XEXP (x, 0), 0);
7350 cond1 = XEXP (XEXP (x, 1), 0);
7352 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7353 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7354 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7355 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7356 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7357 || ((swap_condition (GET_CODE (cond0))
7358 == combine_reversed_comparison_code (cond1))
7359 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7360 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7361 && ! side_effects_p (x))
7363 *ptrue = *pfalse = const0_rtx;
7369 else if (code == IF_THEN_ELSE)
7371 /* If we have IF_THEN_ELSE already, extract the condition and
7372 canonicalize it if it is NE or EQ. */
7373 cond0 = XEXP (x, 0);
7374 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7375 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7376 return XEXP (cond0, 0);
7377 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7379 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7380 return XEXP (cond0, 0);
7386 /* If X is a SUBREG, we can narrow both the true and false values
7387 if the inner expression, if there is a condition. */
7388 else if (code == SUBREG
7389 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7392 *ptrue = simplify_gen_subreg (mode, true0,
7393 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7394 *pfalse = simplify_gen_subreg (mode, false0,
7395 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7400 /* If X is a constant, this isn't special and will cause confusions
7401 if we treat it as such. Likewise if it is equivalent to a constant. */
7402 else if (CONSTANT_P (x)
7403 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7406 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7407 will be least confusing to the rest of the compiler. */
7408 else if (mode == BImode)
7410 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7414 /* If X is known to be either 0 or -1, those are the true and
7415 false values when testing X. */
7416 else if (x == constm1_rtx || x == const0_rtx
7417 || (mode != VOIDmode
7418 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7420 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7424 /* Likewise for 0 or a single bit. */
7425 else if (mode != VOIDmode
7426 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7427 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7429 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7433 /* Otherwise fail; show no condition with true and false values the same. */
7434 *ptrue = *pfalse = x;
7438 /* Return the value of expression X given the fact that condition COND
7439 is known to be true when applied to REG as its first operand and VAL
7440 as its second. X is known to not be shared and so can be modified in
7443 We only handle the simplest cases, and specifically those cases that
7444 arise with IF_THEN_ELSE expressions. */
7447 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7449 enum rtx_code code = GET_CODE (x);
7454 if (side_effects_p (x))
7457 /* If either operand of the condition is a floating point value,
7458 then we have to avoid collapsing an EQ comparison. */
7460 && rtx_equal_p (x, reg)
7461 && ! FLOAT_MODE_P (GET_MODE (x))
7462 && ! FLOAT_MODE_P (GET_MODE (val)))
7465 if (cond == UNEQ && rtx_equal_p (x, reg))
7468 /* If X is (abs REG) and we know something about REG's relationship
7469 with zero, we may be able to simplify this. */
7471 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7474 case GE: case GT: case EQ:
7477 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7479 GET_MODE (XEXP (x, 0)));
7484 /* The only other cases we handle are MIN, MAX, and comparisons if the
7485 operands are the same as REG and VAL. */
7487 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7489 if (rtx_equal_p (XEXP (x, 0), val))
7490 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7492 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7494 if (GET_RTX_CLASS (code) == '<')
7496 if (comparison_dominates_p (cond, code))
7497 return const_true_rtx;
7499 code = combine_reversed_comparison_code (x);
7501 && comparison_dominates_p (cond, code))
7506 else if (code == SMAX || code == SMIN
7507 || code == UMIN || code == UMAX)
7509 int unsignedp = (code == UMIN || code == UMAX);
7511 /* Do not reverse the condition when it is NE or EQ.
7512 This is because we cannot conclude anything about
7513 the value of 'SMAX (x, y)' when x is not equal to y,
7514 but we can when x equals y. */
7515 if ((code == SMAX || code == UMAX)
7516 && ! (cond == EQ || cond == NE))
7517 cond = reverse_condition (cond);
7522 return unsignedp ? x : XEXP (x, 1);
7524 return unsignedp ? x : XEXP (x, 0);
7526 return unsignedp ? XEXP (x, 1) : x;
7528 return unsignedp ? XEXP (x, 0) : x;
7535 else if (code == SUBREG)
7537 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7538 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7540 if (SUBREG_REG (x) != r)
7542 /* We must simplify subreg here, before we lose track of the
7543 original inner_mode. */
7544 new = simplify_subreg (GET_MODE (x), r,
7545 inner_mode, SUBREG_BYTE (x));
7549 SUBST (SUBREG_REG (x), r);
7554 /* We don't have to handle SIGN_EXTEND here, because even in the
7555 case of replacing something with a modeless CONST_INT, a
7556 CONST_INT is already (supposed to be) a valid sign extension for
7557 its narrower mode, which implies it's already properly
7558 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7559 story is different. */
7560 else if (code == ZERO_EXTEND)
7562 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7563 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7565 if (XEXP (x, 0) != r)
7567 /* We must simplify the zero_extend here, before we lose
7568 track of the original inner_mode. */
7569 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7574 SUBST (XEXP (x, 0), r);
7580 fmt = GET_RTX_FORMAT (code);
7581 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7584 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7585 else if (fmt[i] == 'E')
7586 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7587 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7594 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7595 assignment as a field assignment. */
7598 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7600 if (x == y || rtx_equal_p (x, y))
7603 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7606 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7607 Note that all SUBREGs of MEM are paradoxical; otherwise they
7608 would have been rewritten. */
7609 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7610 && GET_CODE (SUBREG_REG (y)) == MEM
7611 && rtx_equal_p (SUBREG_REG (y),
7612 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7615 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7616 && GET_CODE (SUBREG_REG (x)) == MEM
7617 && rtx_equal_p (SUBREG_REG (x),
7618 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7621 /* We used to see if get_last_value of X and Y were the same but that's
7622 not correct. In one direction, we'll cause the assignment to have
7623 the wrong destination and in the case, we'll import a register into this
7624 insn that might have already have been dead. So fail if none of the
7625 above cases are true. */
7629 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7630 Return that assignment if so.
7632 We only handle the most common cases. */
7635 make_field_assignment (rtx x)
7637 rtx dest = SET_DEST (x);
7638 rtx src = SET_SRC (x);
7643 unsigned HOST_WIDE_INT len;
7645 enum machine_mode mode;
7647 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7648 a clear of a one-bit field. We will have changed it to
7649 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7652 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7653 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7654 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7655 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7657 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7660 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7664 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7665 && subreg_lowpart_p (XEXP (src, 0))
7666 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7667 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7668 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7669 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7670 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7672 assign = make_extraction (VOIDmode, dest, 0,
7673 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7676 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7680 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7682 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7683 && XEXP (XEXP (src, 0), 0) == const1_rtx
7684 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7686 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7689 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7693 /* The other case we handle is assignments into a constant-position
7694 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7695 a mask that has all one bits except for a group of zero bits and
7696 OTHER is known to have zeros where C1 has ones, this is such an
7697 assignment. Compute the position and length from C1. Shift OTHER
7698 to the appropriate position, force it to the required mode, and
7699 make the extraction. Check for the AND in both operands. */
7701 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7704 rhs = expand_compound_operation (XEXP (src, 0));
7705 lhs = expand_compound_operation (XEXP (src, 1));
7707 if (GET_CODE (rhs) == AND
7708 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7709 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7710 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7711 else if (GET_CODE (lhs) == AND
7712 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7713 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7714 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7718 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7719 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7720 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7721 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7724 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7728 /* The mode to use for the source is the mode of the assignment, or of
7729 what is inside a possible STRICT_LOW_PART. */
7730 mode = (GET_CODE (assign) == STRICT_LOW_PART
7731 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7733 /* Shift OTHER right POS places and make it the source, restricting it
7734 to the proper length and mode. */
7736 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7737 GET_MODE (src), other, pos),
7739 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7740 ? ~(unsigned HOST_WIDE_INT) 0
7741 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7744 /* If SRC is masked by an AND that does not make a difference in
7745 the value being stored, strip it. */
7746 if (GET_CODE (assign) == ZERO_EXTRACT
7747 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7748 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7749 && GET_CODE (src) == AND
7750 && GET_CODE (XEXP (src, 1)) == CONST_INT
7751 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7752 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7753 src = XEXP (src, 0);
7755 return gen_rtx_SET (VOIDmode, assign, src);
7758 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7762 apply_distributive_law (rtx x)
7764 enum rtx_code code = GET_CODE (x);
7765 rtx lhs, rhs, other;
7767 enum rtx_code inner_code;
7769 /* Distributivity is not true for floating point.
7770 It can change the value. So don't do it.
7771 -- rms and moshier@world.std.com. */
7772 if (FLOAT_MODE_P (GET_MODE (x)))
7775 /* The outer operation can only be one of the following: */
7776 if (code != IOR && code != AND && code != XOR
7777 && code != PLUS && code != MINUS)
7780 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7782 /* If either operand is a primitive we can't do anything, so get out
7784 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7785 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7788 lhs = expand_compound_operation (lhs);
7789 rhs = expand_compound_operation (rhs);
7790 inner_code = GET_CODE (lhs);
7791 if (inner_code != GET_CODE (rhs))
7794 /* See if the inner and outer operations distribute. */
7801 /* These all distribute except over PLUS. */
7802 if (code == PLUS || code == MINUS)
7807 if (code != PLUS && code != MINUS)
7812 /* This is also a multiply, so it distributes over everything. */
7816 /* Non-paradoxical SUBREGs distributes over all operations, provided
7817 the inner modes and byte offsets are the same, this is an extraction
7818 of a low-order part, we don't convert an fp operation to int or
7819 vice versa, and we would not be converting a single-word
7820 operation into a multi-word operation. The latter test is not
7821 required, but it prevents generating unneeded multi-word operations.
7822 Some of the previous tests are redundant given the latter test, but
7823 are retained because they are required for correctness.
7825 We produce the result slightly differently in this case. */
7827 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7828 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7829 || ! subreg_lowpart_p (lhs)
7830 || (GET_MODE_CLASS (GET_MODE (lhs))
7831 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7832 || (GET_MODE_SIZE (GET_MODE (lhs))
7833 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7834 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7837 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7838 SUBREG_REG (lhs), SUBREG_REG (rhs));
7839 return gen_lowpart_for_combine (GET_MODE (x), tem);
7845 /* Set LHS and RHS to the inner operands (A and B in the example
7846 above) and set OTHER to the common operand (C in the example).
7847 These is only one way to do this unless the inner operation is
7849 if (GET_RTX_CLASS (inner_code) == 'c'
7850 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7851 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7852 else if (GET_RTX_CLASS (inner_code) == 'c'
7853 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7854 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7855 else if (GET_RTX_CLASS (inner_code) == 'c'
7856 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7857 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7858 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7859 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7863 /* Form the new inner operation, seeing if it simplifies first. */
7864 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7866 /* There is one exception to the general way of distributing:
7867 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7868 if (code == XOR && inner_code == IOR)
7871 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7874 /* We may be able to continuing distributing the result, so call
7875 ourselves recursively on the inner operation before forming the
7876 outer operation, which we return. */
7877 return gen_binary (inner_code, GET_MODE (x),
7878 apply_distributive_law (tem), other);
7881 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7884 Return an equivalent form, if different from X. Otherwise, return X. If
7885 X is zero, we are to always construct the equivalent form. */
7888 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7889 unsigned HOST_WIDE_INT constop)
7891 unsigned HOST_WIDE_INT nonzero;
7894 /* Simplify VAROP knowing that we will be only looking at some of the
7897 Note by passing in CONSTOP, we guarantee that the bits not set in
7898 CONSTOP are not significant and will never be examined. We must
7899 ensure that is the case by explicitly masking out those bits
7900 before returning. */
7901 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7903 /* If VAROP is a CLOBBER, we will fail so return it. */
7904 if (GET_CODE (varop) == CLOBBER)
7907 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7908 to VAROP and return the new constant. */
7909 if (GET_CODE (varop) == CONST_INT)
7910 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7912 /* See what bits may be nonzero in VAROP. Unlike the general case of
7913 a call to nonzero_bits, here we don't care about bits outside
7916 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7918 /* Turn off all bits in the constant that are known to already be zero.
7919 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7920 which is tested below. */
7924 /* If we don't have any bits left, return zero. */
7928 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7929 a power of two, we can replace this with an ASHIFT. */
7930 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7931 && (i = exact_log2 (constop)) >= 0)
7932 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7934 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7935 or XOR, then try to apply the distributive law. This may eliminate
7936 operations if either branch can be simplified because of the AND.
7937 It may also make some cases more complex, but those cases probably
7938 won't match a pattern either with or without this. */
7940 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7942 gen_lowpart_for_combine
7944 apply_distributive_law
7945 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7946 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7947 XEXP (varop, 0), constop),
7948 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7949 XEXP (varop, 1), constop))));
7951 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7952 the AND and see if one of the operands simplifies to zero. If so, we
7953 may eliminate it. */
7955 if (GET_CODE (varop) == PLUS
7956 && exact_log2 (constop + 1) >= 0)
7960 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7961 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7962 if (o0 == const0_rtx)
7964 if (o1 == const0_rtx)
7968 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7969 if we already had one (just check for the simplest cases). */
7970 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7971 && GET_MODE (XEXP (x, 0)) == mode
7972 && SUBREG_REG (XEXP (x, 0)) == varop)
7973 varop = XEXP (x, 0);
7975 varop = gen_lowpart_for_combine (mode, varop);
7977 /* If we can't make the SUBREG, try to return what we were given. */
7978 if (GET_CODE (varop) == CLOBBER)
7979 return x ? x : varop;
7981 /* If we are only masking insignificant bits, return VAROP. */
7982 if (constop == nonzero)
7986 /* Otherwise, return an AND. */
7987 constop = trunc_int_for_mode (constop, mode);
7988 /* See how much, if any, of X we can use. */
7989 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7990 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7994 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7995 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7996 SUBST (XEXP (x, 1), GEN_INT (constop));
7998 SUBST (XEXP (x, 0), varop);
8005 #define nonzero_bits_with_known(X, MODE) \
8006 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8008 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8009 It avoids exponential behavior in nonzero_bits1 when X has
8010 identical subexpressions on the first or the second level. */
8012 static unsigned HOST_WIDE_INT
8013 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
8014 enum machine_mode known_mode,
8015 unsigned HOST_WIDE_INT known_ret)
8017 if (x == known_x && mode == known_mode)
8020 /* Try to find identical subexpressions. If found call
8021 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8022 precomputed value for the subexpression as KNOWN_RET. */
8024 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8025 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8027 rtx x0 = XEXP (x, 0);
8028 rtx x1 = XEXP (x, 1);
8030 /* Check the first level. */
8032 return nonzero_bits1 (x, mode, x0, mode,
8033 nonzero_bits_with_known (x0, mode));
8035 /* Check the second level. */
8036 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8037 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8038 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8039 return nonzero_bits1 (x, mode, x1, mode,
8040 nonzero_bits_with_known (x1, mode));
8042 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8043 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8044 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8045 return nonzero_bits1 (x, mode, x0, mode,
8046 nonzero_bits_with_known (x0, mode));
8049 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8052 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8053 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8054 is less useful. We can't allow both, because that results in exponential
8055 run time recursion. There is a nullstone testcase that triggered
8056 this. This macro avoids accidental uses of num_sign_bit_copies. */
8057 #define cached_num_sign_bit_copies()
8059 /* Given an expression, X, compute which bits in X can be nonzero.
8060 We don't care about bits outside of those defined in MODE.
8062 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8063 a shift, AND, or zero_extract, we can do better. */
8065 static unsigned HOST_WIDE_INT
8066 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
8067 enum machine_mode known_mode,
8068 unsigned HOST_WIDE_INT known_ret)
8070 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8071 unsigned HOST_WIDE_INT inner_nz;
8073 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8076 /* For floating-point values, assume all bits are needed. */
8077 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8080 /* If X is wider than MODE, use its mode instead. */
8081 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8083 mode = GET_MODE (x);
8084 nonzero = GET_MODE_MASK (mode);
8085 mode_width = GET_MODE_BITSIZE (mode);
8088 if (mode_width > HOST_BITS_PER_WIDE_INT)
8089 /* Our only callers in this case look for single bit values. So
8090 just return the mode mask. Those tests will then be false. */
8093 #ifndef WORD_REGISTER_OPERATIONS
8094 /* If MODE is wider than X, but both are a single word for both the host
8095 and target machines, we can compute this from which bits of the
8096 object might be nonzero in its own mode, taking into account the fact
8097 that on many CISC machines, accessing an object in a wider mode
8098 causes the high-order bits to become undefined. So they are
8099 not known to be zero. */
8101 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8102 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8103 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8104 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8106 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8107 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8112 code = GET_CODE (x);
8116 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8117 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8118 all the bits above ptr_mode are known to be zero. */
8119 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8121 nonzero &= GET_MODE_MASK (ptr_mode);
8124 /* Include declared information about alignment of pointers. */
8125 /* ??? We don't properly preserve REG_POINTER changes across
8126 pointer-to-integer casts, so we can't trust it except for
8127 things that we know must be pointers. See execute/960116-1.c. */
8128 if ((x == stack_pointer_rtx
8129 || x == frame_pointer_rtx
8130 || x == arg_pointer_rtx)
8131 && REGNO_POINTER_ALIGN (REGNO (x)))
8133 unsigned HOST_WIDE_INT alignment
8134 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8136 #ifdef PUSH_ROUNDING
8137 /* If PUSH_ROUNDING is defined, it is possible for the
8138 stack to be momentarily aligned only to that amount,
8139 so we pick the least alignment. */
8140 if (x == stack_pointer_rtx && PUSH_ARGS)
8141 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
8145 nonzero &= ~(alignment - 1);
8148 /* If X is a register whose nonzero bits value is current, use it.
8149 Otherwise, if X is a register whose value we can find, use that
8150 value. Otherwise, use the previously-computed global nonzero bits
8151 for this register. */
8153 if (reg_last_set_value[REGNO (x)] != 0
8154 && (reg_last_set_mode[REGNO (x)] == mode
8155 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8156 && GET_MODE_CLASS (mode) == MODE_INT))
8157 && (reg_last_set_label[REGNO (x)] == label_tick
8158 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8159 && REG_N_SETS (REGNO (x)) == 1
8160 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8162 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8163 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8165 tem = get_last_value (x);
8169 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8170 /* If X is narrower than MODE and TEM is a non-negative
8171 constant that would appear negative in the mode of X,
8172 sign-extend it for use in reg_nonzero_bits because some
8173 machines (maybe most) will actually do the sign-extension
8174 and this is the conservative approach.
8176 ??? For 2.5, try to tighten up the MD files in this regard
8177 instead of this kludge. */
8179 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8180 && GET_CODE (tem) == CONST_INT
8182 && 0 != (INTVAL (tem)
8183 & ((HOST_WIDE_INT) 1
8184 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8185 tem = GEN_INT (INTVAL (tem)
8186 | ((HOST_WIDE_INT) (-1)
8187 << GET_MODE_BITSIZE (GET_MODE (x))));
8189 return nonzero_bits_with_known (tem, mode) & nonzero;
8191 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8193 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8195 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8196 /* We don't know anything about the upper bits. */
8197 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8198 return nonzero & mask;
8204 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8205 /* If X is negative in MODE, sign-extend the value. */
8206 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8207 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8208 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8214 #ifdef LOAD_EXTEND_OP
8215 /* In many, if not most, RISC machines, reading a byte from memory
8216 zeros the rest of the register. Noticing that fact saves a lot
8217 of extra zero-extends. */
8218 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8219 nonzero &= GET_MODE_MASK (GET_MODE (x));
8224 case UNEQ: case LTGT:
8225 case GT: case GTU: case UNGT:
8226 case LT: case LTU: case UNLT:
8227 case GE: case GEU: case UNGE:
8228 case LE: case LEU: case UNLE:
8229 case UNORDERED: case ORDERED:
8231 /* If this produces an integer result, we know which bits are set.
8232 Code here used to clear bits outside the mode of X, but that is
8235 if (GET_MODE_CLASS (mode) == MODE_INT
8236 && mode_width <= HOST_BITS_PER_WIDE_INT)
8237 nonzero = STORE_FLAG_VALUE;
8242 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8243 and num_sign_bit_copies. */
8244 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8245 == GET_MODE_BITSIZE (GET_MODE (x)))
8249 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8250 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8255 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8256 and num_sign_bit_copies. */
8257 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8258 == GET_MODE_BITSIZE (GET_MODE (x)))
8264 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8265 & GET_MODE_MASK (mode));
8269 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8270 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8271 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8275 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8276 Otherwise, show all the bits in the outer mode but not the inner
8278 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8279 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8281 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8283 & (((HOST_WIDE_INT) 1
8284 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8285 inner_nz |= (GET_MODE_MASK (mode)
8286 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8289 nonzero &= inner_nz;
8293 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8294 & nonzero_bits_with_known (XEXP (x, 1), mode));
8298 case UMIN: case UMAX: case SMIN: case SMAX:
8300 unsigned HOST_WIDE_INT nonzero0 =
8301 nonzero_bits_with_known (XEXP (x, 0), mode);
8303 /* Don't call nonzero_bits for the second time if it cannot change
8305 if ((nonzero & nonzero0) != nonzero)
8306 nonzero &= (nonzero0
8307 | nonzero_bits_with_known (XEXP (x, 1), mode));
8311 case PLUS: case MINUS:
8313 case DIV: case UDIV:
8314 case MOD: case UMOD:
8315 /* We can apply the rules of arithmetic to compute the number of
8316 high- and low-order zero bits of these operations. We start by
8317 computing the width (position of the highest-order nonzero bit)
8318 and the number of low-order zero bits for each value. */
8320 unsigned HOST_WIDE_INT nz0 =
8321 nonzero_bits_with_known (XEXP (x, 0), mode);
8322 unsigned HOST_WIDE_INT nz1 =
8323 nonzero_bits_with_known (XEXP (x, 1), mode);
8324 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8325 int width0 = floor_log2 (nz0) + 1;
8326 int width1 = floor_log2 (nz1) + 1;
8327 int low0 = floor_log2 (nz0 & -nz0);
8328 int low1 = floor_log2 (nz1 & -nz1);
8329 HOST_WIDE_INT op0_maybe_minusp
8330 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8331 HOST_WIDE_INT op1_maybe_minusp
8332 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8333 unsigned int result_width = mode_width;
8339 result_width = MAX (width0, width1) + 1;
8340 result_low = MIN (low0, low1);
8343 result_low = MIN (low0, low1);
8346 result_width = width0 + width1;
8347 result_low = low0 + low1;
8352 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8353 result_width = width0;
8358 result_width = width0;
8363 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8364 result_width = MIN (width0, width1);
8365 result_low = MIN (low0, low1);
8370 result_width = MIN (width0, width1);
8371 result_low = MIN (low0, low1);
8377 if (result_width < mode_width)
8378 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8381 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8383 #ifdef POINTERS_EXTEND_UNSIGNED
8384 /* If pointers extend unsigned and this is an addition or subtraction
8385 to a pointer in Pmode, all the bits above ptr_mode are known to be
8387 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8388 && (code == PLUS || code == MINUS)
8389 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8390 nonzero &= GET_MODE_MASK (ptr_mode);
8396 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8397 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8398 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8402 /* If this is a SUBREG formed for a promoted variable that has
8403 been zero-extended, we know that at least the high-order bits
8404 are zero, though others might be too. */
8406 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8407 nonzero = (GET_MODE_MASK (GET_MODE (x))
8408 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8410 /* If the inner mode is a single word for both the host and target
8411 machines, we can compute this from which bits of the inner
8412 object might be nonzero. */
8413 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8414 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8415 <= HOST_BITS_PER_WIDE_INT))
8417 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8419 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8420 /* If this is a typical RISC machine, we only have to worry
8421 about the way loads are extended. */
8422 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8424 & (((unsigned HOST_WIDE_INT) 1
8425 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8427 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8428 || GET_CODE (SUBREG_REG (x)) != MEM)
8431 /* On many CISC machines, accessing an object in a wider mode
8432 causes the high-order bits to become undefined. So they are
8433 not known to be zero. */
8434 if (GET_MODE_SIZE (GET_MODE (x))
8435 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8436 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8437 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8446 /* The nonzero bits are in two classes: any bits within MODE
8447 that aren't in GET_MODE (x) are always significant. The rest of the
8448 nonzero bits are those that are significant in the operand of
8449 the shift when shifted the appropriate number of bits. This
8450 shows that high-order bits are cleared by the right shift and
8451 low-order bits by left shifts. */
8452 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8453 && INTVAL (XEXP (x, 1)) >= 0
8454 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8456 enum machine_mode inner_mode = GET_MODE (x);
8457 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8458 int count = INTVAL (XEXP (x, 1));
8459 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8460 unsigned HOST_WIDE_INT op_nonzero =
8461 nonzero_bits_with_known (XEXP (x, 0), mode);
8462 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8463 unsigned HOST_WIDE_INT outer = 0;
8465 if (mode_width > width)
8466 outer = (op_nonzero & nonzero & ~mode_mask);
8468 if (code == LSHIFTRT)
8470 else if (code == ASHIFTRT)
8474 /* If the sign bit may have been nonzero before the shift, we
8475 need to mark all the places it could have been copied to
8476 by the shift as possibly nonzero. */
8477 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8478 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8480 else if (code == ASHIFT)
8483 inner = ((inner << (count % width)
8484 | (inner >> (width - (count % width)))) & mode_mask);
8486 nonzero &= (outer | inner);
8492 /* This is at most the number of bits in the mode. */
8493 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8497 /* If CLZ has a known value at zero, then the nonzero bits are
8498 that value, plus the number of bits in the mode minus one. */
8499 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8500 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8506 /* If CTZ has a known value at zero, then the nonzero bits are
8507 that value, plus the number of bits in the mode minus one. */
8508 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8509 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8519 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8520 | nonzero_bits_with_known (XEXP (x, 2), mode));
8530 /* See the macro definition above. */
8531 #undef cached_num_sign_bit_copies
8533 #define num_sign_bit_copies_with_known(X, M) \
8534 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8536 /* The function cached_num_sign_bit_copies is a wrapper around
8537 num_sign_bit_copies1. It avoids exponential behavior in
8538 num_sign_bit_copies1 when X has identical subexpressions on the
8539 first or the second level. */
8542 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
8543 enum machine_mode known_mode,
8544 unsigned int known_ret)
8546 if (x == known_x && mode == known_mode)
8549 /* Try to find identical subexpressions. If found call
8550 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8551 the precomputed value for the subexpression as KNOWN_RET. */
8553 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8554 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8556 rtx x0 = XEXP (x, 0);
8557 rtx x1 = XEXP (x, 1);
8559 /* Check the first level. */
8562 num_sign_bit_copies1 (x, mode, x0, mode,
8563 num_sign_bit_copies_with_known (x0, mode));
8565 /* Check the second level. */
8566 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8567 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8568 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8570 num_sign_bit_copies1 (x, mode, x1, mode,
8571 num_sign_bit_copies_with_known (x1, mode));
8573 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8574 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8575 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8577 num_sign_bit_copies1 (x, mode, x0, mode,
8578 num_sign_bit_copies_with_known (x0, mode));
8581 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8584 /* Return the number of bits at the high-order end of X that are known to
8585 be equal to the sign bit. X will be used in mode MODE; if MODE is
8586 VOIDmode, X will be used in its own mode. The returned value will always
8587 be between 1 and the number of bits in MODE. */
8590 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
8591 enum machine_mode known_mode,
8592 unsigned int known_ret)
8594 enum rtx_code code = GET_CODE (x);
8595 unsigned int bitwidth;
8596 int num0, num1, result;
8597 unsigned HOST_WIDE_INT nonzero;
8600 /* If we weren't given a mode, use the mode of X. If the mode is still
8601 VOIDmode, we don't know anything. Likewise if one of the modes is
8604 if (mode == VOIDmode)
8605 mode = GET_MODE (x);
8607 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8610 bitwidth = GET_MODE_BITSIZE (mode);
8612 /* For a smaller object, just ignore the high bits. */
8613 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8615 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8617 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8620 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8622 #ifndef WORD_REGISTER_OPERATIONS
8623 /* If this machine does not do all register operations on the entire
8624 register and MODE is wider than the mode of X, we can say nothing
8625 at all about the high-order bits. */
8628 /* Likewise on machines that do, if the mode of the object is smaller
8629 than a word and loads of that size don't sign extend, we can say
8630 nothing about the high order bits. */
8631 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8632 #ifdef LOAD_EXTEND_OP
8633 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8644 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8645 /* If pointers extend signed and this is a pointer in Pmode, say that
8646 all the bits above ptr_mode are known to be sign bit copies. */
8647 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8649 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8652 if (reg_last_set_value[REGNO (x)] != 0
8653 && reg_last_set_mode[REGNO (x)] == mode
8654 && (reg_last_set_label[REGNO (x)] == label_tick
8655 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8656 && REG_N_SETS (REGNO (x)) == 1
8657 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8659 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8660 return reg_last_set_sign_bit_copies[REGNO (x)];
8662 tem = get_last_value (x);
8664 return num_sign_bit_copies_with_known (tem, mode);
8666 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8667 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8668 return reg_sign_bit_copies[REGNO (x)];
8672 #ifdef LOAD_EXTEND_OP
8673 /* Some RISC machines sign-extend all loads of smaller than a word. */
8674 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8675 return MAX (1, ((int) bitwidth
8676 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8681 /* If the constant is negative, take its 1's complement and remask.
8682 Then see how many zero bits we have. */
8683 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8684 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8685 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8686 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8688 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8691 /* If this is a SUBREG for a promoted object that is sign-extended
8692 and we are looking at it in a wider mode, we know that at least the
8693 high-order bits are known to be sign bit copies. */
8695 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8697 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8698 return MAX ((int) bitwidth
8699 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8703 /* For a smaller object, just ignore the high bits. */
8704 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8706 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8707 return MAX (1, (num0
8708 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8712 #ifdef WORD_REGISTER_OPERATIONS
8713 #ifdef LOAD_EXTEND_OP
8714 /* For paradoxical SUBREGs on machines where all register operations
8715 affect the entire register, just look inside. Note that we are
8716 passing MODE to the recursive call, so the number of sign bit copies
8717 will remain relative to that mode, not the inner mode. */
8719 /* This works only if loads sign extend. Otherwise, if we get a
8720 reload for the inner part, it may be loaded from the stack, and
8721 then we lose all sign bit copies that existed before the store
8724 if ((GET_MODE_SIZE (GET_MODE (x))
8725 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8726 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8727 && GET_CODE (SUBREG_REG (x)) == MEM)
8728 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8734 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8735 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8739 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8740 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8743 /* For a smaller object, just ignore the high bits. */
8744 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8745 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8749 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8751 case ROTATE: case ROTATERT:
8752 /* If we are rotating left by a number of bits less than the number
8753 of sign bit copies, we can just subtract that amount from the
8755 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8756 && INTVAL (XEXP (x, 1)) >= 0
8757 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8759 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8760 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8761 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8766 /* In general, this subtracts one sign bit copy. But if the value
8767 is known to be positive, the number of sign bit copies is the
8768 same as that of the input. Finally, if the input has just one bit
8769 that might be nonzero, all the bits are copies of the sign bit. */
8770 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8771 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8772 return num0 > 1 ? num0 - 1 : 1;
8774 nonzero = nonzero_bits (XEXP (x, 0), mode);
8779 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8784 case IOR: case AND: case XOR:
8785 case SMIN: case SMAX: case UMIN: case UMAX:
8786 /* Logical operations will preserve the number of sign-bit copies.
8787 MIN and MAX operations always return one of the operands. */
8788 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8789 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8790 return MIN (num0, num1);
8792 case PLUS: case MINUS:
8793 /* For addition and subtraction, we can have a 1-bit carry. However,
8794 if we are subtracting 1 from a positive number, there will not
8795 be such a carry. Furthermore, if the positive number is known to
8796 be 0 or 1, we know the result is either -1 or 0. */
8798 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8799 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8801 nonzero = nonzero_bits (XEXP (x, 0), mode);
8802 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8803 return (nonzero == 1 || nonzero == 0 ? bitwidth
8804 : bitwidth - floor_log2 (nonzero) - 1);
8807 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8808 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8809 result = MAX (1, MIN (num0, num1) - 1);
8811 #ifdef POINTERS_EXTEND_UNSIGNED
8812 /* If pointers extend signed and this is an addition or subtraction
8813 to a pointer in Pmode, all the bits above ptr_mode are known to be
8815 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8816 && (code == PLUS || code == MINUS)
8817 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8818 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8819 - GET_MODE_BITSIZE (ptr_mode) + 1),
8825 /* The number of bits of the product is the sum of the number of
8826 bits of both terms. However, unless one of the terms if known
8827 to be positive, we must allow for an additional bit since negating
8828 a negative number can remove one sign bit copy. */
8830 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8831 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8833 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8835 && (bitwidth > HOST_BITS_PER_WIDE_INT
8836 || (((nonzero_bits (XEXP (x, 0), mode)
8837 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8838 && ((nonzero_bits (XEXP (x, 1), mode)
8839 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8842 return MAX (1, result);
8845 /* The result must be <= the first operand. If the first operand
8846 has the high bit set, we know nothing about the number of sign
8848 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8850 else if ((nonzero_bits (XEXP (x, 0), mode)
8851 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8854 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8857 /* The result must be <= the second operand. */
8858 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8861 /* Similar to unsigned division, except that we have to worry about
8862 the case where the divisor is negative, in which case we have
8864 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8866 && (bitwidth > HOST_BITS_PER_WIDE_INT
8867 || (nonzero_bits (XEXP (x, 1), mode)
8868 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8874 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8876 && (bitwidth > HOST_BITS_PER_WIDE_INT
8877 || (nonzero_bits (XEXP (x, 1), mode)
8878 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8884 /* Shifts by a constant add to the number of bits equal to the
8886 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8887 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8888 && INTVAL (XEXP (x, 1)) > 0)
8889 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8894 /* Left shifts destroy copies. */
8895 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8896 || INTVAL (XEXP (x, 1)) < 0
8897 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8900 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8901 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8904 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8905 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
8906 return MIN (num0, num1);
8908 case EQ: case NE: case GE: case GT: case LE: case LT:
8909 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8910 case GEU: case GTU: case LEU: case LTU:
8911 case UNORDERED: case ORDERED:
8912 /* If the constant is negative, take its 1's complement and remask.
8913 Then see how many zero bits we have. */
8914 nonzero = STORE_FLAG_VALUE;
8915 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8916 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8917 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8919 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8926 /* If we haven't been able to figure it out by one of the above rules,
8927 see if some of the high-order bits are known to be zero. If so,
8928 count those bits and return one less than that amount. If we can't
8929 safely compute the mask for this mode, always return BITWIDTH. */
8931 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8934 nonzero = nonzero_bits (x, mode);
8935 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8936 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8939 /* Return the number of "extended" bits there are in X, when interpreted
8940 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8941 unsigned quantities, this is the number of high-order zero bits.
8942 For signed quantities, this is the number of copies of the sign bit
8943 minus 1. In both case, this function returns the number of "spare"
8944 bits. For example, if two quantities for which this function returns
8945 at least 1 are added, the addition is known not to overflow.
8947 This function will always return 0 unless called during combine, which
8948 implies that it must be called from a define_split. */
8951 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8953 if (nonzero_sign_valid == 0)
8957 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8958 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8959 - floor_log2 (nonzero_bits (x, mode)))
8961 : num_sign_bit_copies (x, mode) - 1);
8964 /* This function is called from `simplify_shift_const' to merge two
8965 outer operations. Specifically, we have already found that we need
8966 to perform operation *POP0 with constant *PCONST0 at the outermost
8967 position. We would now like to also perform OP1 with constant CONST1
8968 (with *POP0 being done last).
8970 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8971 the resulting operation. *PCOMP_P is set to 1 if we would need to
8972 complement the innermost operand, otherwise it is unchanged.
8974 MODE is the mode in which the operation will be done. No bits outside
8975 the width of this mode matter. It is assumed that the width of this mode
8976 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8978 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8979 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8980 result is simply *PCONST0.
8982 If the resulting operation cannot be expressed as one operation, we
8983 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8986 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8988 enum rtx_code op0 = *pop0;
8989 HOST_WIDE_INT const0 = *pconst0;
8991 const0 &= GET_MODE_MASK (mode);
8992 const1 &= GET_MODE_MASK (mode);
8994 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8998 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9001 if (op1 == NIL || op0 == SET)
9004 else if (op0 == NIL)
9005 op0 = op1, const0 = const1;
9007 else if (op0 == op1)
9031 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9032 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9035 /* If the two constants aren't the same, we can't do anything. The
9036 remaining six cases can all be done. */
9037 else if (const0 != const1)
9045 /* (a & b) | b == b */
9047 else /* op1 == XOR */
9048 /* (a ^ b) | b == a | b */
9054 /* (a & b) ^ b == (~a) & b */
9055 op0 = AND, *pcomp_p = 1;
9056 else /* op1 == IOR */
9057 /* (a | b) ^ b == a & ~b */
9058 op0 = AND, const0 = ~const0;
9063 /* (a | b) & b == b */
9065 else /* op1 == XOR */
9066 /* (a ^ b) & b) == (~a) & b */
9073 /* Check for NO-OP cases. */
9074 const0 &= GET_MODE_MASK (mode);
9076 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9078 else if (const0 == 0 && op0 == AND)
9080 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9084 /* ??? Slightly redundant with the above mask, but not entirely.
9085 Moving this above means we'd have to sign-extend the mode mask
9086 for the final test. */
9087 const0 = trunc_int_for_mode (const0, mode);
9095 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9096 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9097 that we started with.
9099 The shift is normally computed in the widest mode we find in VAROP, as
9100 long as it isn't a different number of words than RESULT_MODE. Exceptions
9101 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9104 simplify_shift_const (rtx x, enum rtx_code code,
9105 enum machine_mode result_mode, rtx varop,
9108 enum rtx_code orig_code = code;
9111 enum machine_mode mode = result_mode;
9112 enum machine_mode shift_mode, tmode;
9113 unsigned int mode_words
9114 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9115 /* We form (outer_op (code varop count) (outer_const)). */
9116 enum rtx_code outer_op = NIL;
9117 HOST_WIDE_INT outer_const = 0;
9119 int complement_p = 0;
9122 /* Make sure and truncate the "natural" shift on the way in. We don't
9123 want to do this inside the loop as it makes it more difficult to
9125 #ifdef SHIFT_COUNT_TRUNCATED
9126 if (SHIFT_COUNT_TRUNCATED)
9127 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9130 /* If we were given an invalid count, don't do anything except exactly
9131 what was requested. */
9133 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9138 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9143 /* Unless one of the branches of the `if' in this loop does a `continue',
9144 we will `break' the loop after the `if'. */
9148 /* If we have an operand of (clobber (const_int 0)), just return that
9150 if (GET_CODE (varop) == CLOBBER)
9153 /* If we discovered we had to complement VAROP, leave. Making a NOT
9154 here would cause an infinite loop. */
9158 /* Convert ROTATERT to ROTATE. */
9159 if (code == ROTATERT)
9161 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9163 if (VECTOR_MODE_P (result_mode))
9164 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9166 count = bitsize - count;
9169 /* We need to determine what mode we will do the shift in. If the
9170 shift is a right shift or a ROTATE, we must always do it in the mode
9171 it was originally done in. Otherwise, we can do it in MODE, the
9172 widest mode encountered. */
9174 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9175 ? result_mode : mode);
9177 /* Handle cases where the count is greater than the size of the mode
9178 minus 1. For ASHIFT, use the size minus one as the count (this can
9179 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9180 take the count modulo the size. For other shifts, the result is
9183 Since these shifts are being produced by the compiler by combining
9184 multiple operations, each of which are defined, we know what the
9185 result is supposed to be. */
9187 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9189 if (code == ASHIFTRT)
9190 count = GET_MODE_BITSIZE (shift_mode) - 1;
9191 else if (code == ROTATE || code == ROTATERT)
9192 count %= GET_MODE_BITSIZE (shift_mode);
9195 /* We can't simply return zero because there may be an
9203 /* An arithmetic right shift of a quantity known to be -1 or 0
9205 if (code == ASHIFTRT
9206 && (num_sign_bit_copies (varop, shift_mode)
9207 == GET_MODE_BITSIZE (shift_mode)))
9213 /* If we are doing an arithmetic right shift and discarding all but
9214 the sign bit copies, this is equivalent to doing a shift by the
9215 bitsize minus one. Convert it into that shift because it will often
9216 allow other simplifications. */
9218 if (code == ASHIFTRT
9219 && (count + num_sign_bit_copies (varop, shift_mode)
9220 >= GET_MODE_BITSIZE (shift_mode)))
9221 count = GET_MODE_BITSIZE (shift_mode) - 1;
9223 /* We simplify the tests below and elsewhere by converting
9224 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9225 `make_compound_operation' will convert it to an ASHIFTRT for
9226 those machines (such as VAX) that don't have an LSHIFTRT. */
9227 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9229 && ((nonzero_bits (varop, shift_mode)
9230 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9234 if (code == LSHIFTRT
9235 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9236 && !(nonzero_bits (varop, shift_mode) >> count))
9239 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9240 && !((nonzero_bits (varop, shift_mode) << count)
9241 & GET_MODE_MASK (shift_mode)))
9244 switch (GET_CODE (varop))
9250 new = expand_compound_operation (varop);
9259 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9260 minus the width of a smaller mode, we can do this with a
9261 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9262 if ((code == ASHIFTRT || code == LSHIFTRT)
9263 && ! mode_dependent_address_p (XEXP (varop, 0))
9264 && ! MEM_VOLATILE_P (varop)
9265 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9266 MODE_INT, 1)) != BLKmode)
9268 new = adjust_address_nv (varop, tmode,
9269 BYTES_BIG_ENDIAN ? 0
9270 : count / BITS_PER_UNIT);
9272 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9273 : ZERO_EXTEND, mode, new);
9280 /* Similar to the case above, except that we can only do this if
9281 the resulting mode is the same as that of the underlying
9282 MEM and adjust the address depending on the *bits* endianness
9283 because of the way that bit-field extract insns are defined. */
9284 if ((code == ASHIFTRT || code == LSHIFTRT)
9285 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9286 MODE_INT, 1)) != BLKmode
9287 && tmode == GET_MODE (XEXP (varop, 0)))
9289 if (BITS_BIG_ENDIAN)
9290 new = XEXP (varop, 0);
9293 new = copy_rtx (XEXP (varop, 0));
9294 SUBST (XEXP (new, 0),
9295 plus_constant (XEXP (new, 0),
9296 count / BITS_PER_UNIT));
9299 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9300 : ZERO_EXTEND, mode, new);
9307 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9308 the same number of words as what we've seen so far. Then store
9309 the widest mode in MODE. */
9310 if (subreg_lowpart_p (varop)
9311 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9312 > GET_MODE_SIZE (GET_MODE (varop)))
9313 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9314 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9317 varop = SUBREG_REG (varop);
9318 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9319 mode = GET_MODE (varop);
9325 /* Some machines use MULT instead of ASHIFT because MULT
9326 is cheaper. But it is still better on those machines to
9327 merge two shifts into one. */
9328 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9329 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9332 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9333 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9339 /* Similar, for when divides are cheaper. */
9340 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9341 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9344 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9345 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9351 /* If we are extracting just the sign bit of an arithmetic
9352 right shift, that shift is not needed. However, the sign
9353 bit of a wider mode may be different from what would be
9354 interpreted as the sign bit in a narrower mode, so, if
9355 the result is narrower, don't discard the shift. */
9356 if (code == LSHIFTRT
9357 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9358 && (GET_MODE_BITSIZE (result_mode)
9359 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9361 varop = XEXP (varop, 0);
9365 /* ... fall through ... */
9370 /* Here we have two nested shifts. The result is usually the
9371 AND of a new shift with a mask. We compute the result below. */
9372 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9373 && INTVAL (XEXP (varop, 1)) >= 0
9374 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9375 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9376 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9378 enum rtx_code first_code = GET_CODE (varop);
9379 unsigned int first_count = INTVAL (XEXP (varop, 1));
9380 unsigned HOST_WIDE_INT mask;
9383 /* We have one common special case. We can't do any merging if
9384 the inner code is an ASHIFTRT of a smaller mode. However, if
9385 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9386 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9387 we can convert it to
9388 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9389 This simplifies certain SIGN_EXTEND operations. */
9390 if (code == ASHIFT && first_code == ASHIFTRT
9391 && count == (unsigned int)
9392 (GET_MODE_BITSIZE (result_mode)
9393 - GET_MODE_BITSIZE (GET_MODE (varop))))
9395 /* C3 has the low-order C1 bits zero. */
9397 mask = (GET_MODE_MASK (mode)
9398 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9400 varop = simplify_and_const_int (NULL_RTX, result_mode,
9401 XEXP (varop, 0), mask);
9402 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9404 count = first_count;
9409 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9410 than C1 high-order bits equal to the sign bit, we can convert
9411 this to either an ASHIFT or an ASHIFTRT depending on the
9414 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9416 if (code == ASHIFTRT && first_code == ASHIFT
9417 && GET_MODE (varop) == shift_mode
9418 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9421 varop = XEXP (varop, 0);
9423 signed_count = count - first_count;
9424 if (signed_count < 0)
9425 count = -signed_count, code = ASHIFT;
9427 count = signed_count;
9432 /* There are some cases we can't do. If CODE is ASHIFTRT,
9433 we can only do this if FIRST_CODE is also ASHIFTRT.
9435 We can't do the case when CODE is ROTATE and FIRST_CODE is
9438 If the mode of this shift is not the mode of the outer shift,
9439 we can't do this if either shift is a right shift or ROTATE.
9441 Finally, we can't do any of these if the mode is too wide
9442 unless the codes are the same.
9444 Handle the case where the shift codes are the same
9447 if (code == first_code)
9449 if (GET_MODE (varop) != result_mode
9450 && (code == ASHIFTRT || code == LSHIFTRT
9454 count += first_count;
9455 varop = XEXP (varop, 0);
9459 if (code == ASHIFTRT
9460 || (code == ROTATE && first_code == ASHIFTRT)
9461 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9462 || (GET_MODE (varop) != result_mode
9463 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9464 || first_code == ROTATE
9465 || code == ROTATE)))
9468 /* To compute the mask to apply after the shift, shift the
9469 nonzero bits of the inner shift the same way the
9470 outer shift will. */
9472 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9475 = simplify_binary_operation (code, result_mode, mask_rtx,
9478 /* Give up if we can't compute an outer operation to use. */
9480 || GET_CODE (mask_rtx) != CONST_INT
9481 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9483 result_mode, &complement_p))
9486 /* If the shifts are in the same direction, we add the
9487 counts. Otherwise, we subtract them. */
9488 signed_count = count;
9489 if ((code == ASHIFTRT || code == LSHIFTRT)
9490 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9491 signed_count += first_count;
9493 signed_count -= first_count;
9495 /* If COUNT is positive, the new shift is usually CODE,
9496 except for the two exceptions below, in which case it is
9497 FIRST_CODE. If the count is negative, FIRST_CODE should
9499 if (signed_count > 0
9500 && ((first_code == ROTATE && code == ASHIFT)
9501 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9502 code = first_code, count = signed_count;
9503 else if (signed_count < 0)
9504 code = first_code, count = -signed_count;
9506 count = signed_count;
9508 varop = XEXP (varop, 0);
9512 /* If we have (A << B << C) for any shift, we can convert this to
9513 (A << C << B). This wins if A is a constant. Only try this if
9514 B is not a constant. */
9516 else if (GET_CODE (varop) == code
9517 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9519 = simplify_binary_operation (code, mode,
9523 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9530 /* Make this fit the case below. */
9531 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9532 GEN_INT (GET_MODE_MASK (mode)));
9538 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9539 with C the size of VAROP - 1 and the shift is logical if
9540 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9541 we have an (le X 0) operation. If we have an arithmetic shift
9542 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9543 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9545 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9546 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9547 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9548 && (code == LSHIFTRT || code == ASHIFTRT)
9549 && count == (unsigned int)
9550 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9551 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9554 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9557 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9558 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9563 /* If we have (shift (logical)), move the logical to the outside
9564 to allow it to possibly combine with another logical and the
9565 shift to combine with another shift. This also canonicalizes to
9566 what a ZERO_EXTRACT looks like. Also, some machines have
9567 (and (shift)) insns. */
9569 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9570 && (new = simplify_binary_operation (code, result_mode,
9572 GEN_INT (count))) != 0
9573 && GET_CODE (new) == CONST_INT
9574 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9575 INTVAL (new), result_mode, &complement_p))
9577 varop = XEXP (varop, 0);
9581 /* If we can't do that, try to simplify the shift in each arm of the
9582 logical expression, make a new logical expression, and apply
9583 the inverse distributive law. */
9585 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9586 XEXP (varop, 0), count);
9587 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9588 XEXP (varop, 1), count);
9590 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9591 varop = apply_distributive_law (varop);
9598 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9599 says that the sign bit can be tested, FOO has mode MODE, C is
9600 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9601 that may be nonzero. */
9602 if (code == LSHIFTRT
9603 && XEXP (varop, 1) == const0_rtx
9604 && GET_MODE (XEXP (varop, 0)) == result_mode
9605 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9606 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9607 && ((STORE_FLAG_VALUE
9608 & ((HOST_WIDE_INT) 1
9609 < (GET_MODE_BITSIZE (result_mode) - 1))))
9610 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9611 && merge_outer_ops (&outer_op, &outer_const, XOR,
9612 (HOST_WIDE_INT) 1, result_mode,
9615 varop = XEXP (varop, 0);
9622 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9623 than the number of bits in the mode is equivalent to A. */
9624 if (code == LSHIFTRT
9625 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9626 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9628 varop = XEXP (varop, 0);
9633 /* NEG commutes with ASHIFT since it is multiplication. Move the
9634 NEG outside to allow shifts to combine. */
9636 && merge_outer_ops (&outer_op, &outer_const, NEG,
9637 (HOST_WIDE_INT) 0, result_mode,
9640 varop = XEXP (varop, 0);
9646 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9647 is one less than the number of bits in the mode is
9648 equivalent to (xor A 1). */
9649 if (code == LSHIFTRT
9650 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9651 && XEXP (varop, 1) == constm1_rtx
9652 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9653 && merge_outer_ops (&outer_op, &outer_const, XOR,
9654 (HOST_WIDE_INT) 1, result_mode,
9658 varop = XEXP (varop, 0);
9662 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9663 that might be nonzero in BAR are those being shifted out and those
9664 bits are known zero in FOO, we can replace the PLUS with FOO.
9665 Similarly in the other operand order. This code occurs when
9666 we are computing the size of a variable-size array. */
9668 if ((code == ASHIFTRT || code == LSHIFTRT)
9669 && count < HOST_BITS_PER_WIDE_INT
9670 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9671 && (nonzero_bits (XEXP (varop, 1), result_mode)
9672 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9674 varop = XEXP (varop, 0);
9677 else if ((code == ASHIFTRT || code == LSHIFTRT)
9678 && count < HOST_BITS_PER_WIDE_INT
9679 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9680 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9682 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9683 & nonzero_bits (XEXP (varop, 1),
9686 varop = XEXP (varop, 1);
9690 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9692 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9693 && (new = simplify_binary_operation (ASHIFT, result_mode,
9695 GEN_INT (count))) != 0
9696 && GET_CODE (new) == CONST_INT
9697 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9698 INTVAL (new), result_mode, &complement_p))
9700 varop = XEXP (varop, 0);
9706 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9707 with C the size of VAROP - 1 and the shift is logical if
9708 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9709 we have a (gt X 0) operation. If the shift is arithmetic with
9710 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9711 we have a (neg (gt X 0)) operation. */
9713 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9714 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9715 && count == (unsigned int)
9716 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9717 && (code == LSHIFTRT || code == ASHIFTRT)
9718 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9719 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9721 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9724 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9727 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9728 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9735 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9736 if the truncate does not affect the value. */
9737 if (code == LSHIFTRT
9738 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9739 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9740 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9741 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9742 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9744 rtx varop_inner = XEXP (varop, 0);
9747 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9748 XEXP (varop_inner, 0),
9750 (count + INTVAL (XEXP (varop_inner, 1))));
9751 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9764 /* We need to determine what mode to do the shift in. If the shift is
9765 a right shift or ROTATE, we must always do it in the mode it was
9766 originally done in. Otherwise, we can do it in MODE, the widest mode
9767 encountered. The code we care about is that of the shift that will
9768 actually be done, not the shift that was originally requested. */
9770 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9771 ? result_mode : mode);
9773 /* We have now finished analyzing the shift. The result should be
9774 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9775 OUTER_OP is non-NIL, it is an operation that needs to be applied
9776 to the result of the shift. OUTER_CONST is the relevant constant,
9777 but we must turn off all bits turned off in the shift.
9779 If we were passed a value for X, see if we can use any pieces of
9780 it. If not, make new rtx. */
9782 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9783 && GET_CODE (XEXP (x, 1)) == CONST_INT
9784 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9785 const_rtx = XEXP (x, 1);
9787 const_rtx = GEN_INT (count);
9789 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9790 && GET_MODE (XEXP (x, 0)) == shift_mode
9791 && SUBREG_REG (XEXP (x, 0)) == varop)
9792 varop = XEXP (x, 0);
9793 else if (GET_MODE (varop) != shift_mode)
9794 varop = gen_lowpart_for_combine (shift_mode, varop);
9796 /* If we can't make the SUBREG, try to return what we were given. */
9797 if (GET_CODE (varop) == CLOBBER)
9798 return x ? x : varop;
9800 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9804 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9806 /* If we have an outer operation and we just made a shift, it is
9807 possible that we could have simplified the shift were it not
9808 for the outer operation. So try to do the simplification
9811 if (outer_op != NIL && GET_CODE (x) == code
9812 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9813 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9814 INTVAL (XEXP (x, 1)));
9816 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9817 turn off all the bits that the shift would have turned off. */
9818 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9819 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9820 GET_MODE_MASK (result_mode) >> orig_count);
9822 /* Do the remainder of the processing in RESULT_MODE. */
9823 x = gen_lowpart_for_combine (result_mode, x);
9825 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9828 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9830 if (outer_op != NIL)
9832 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9833 outer_const = trunc_int_for_mode (outer_const, result_mode);
9835 if (outer_op == AND)
9836 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9837 else if (outer_op == SET)
9838 /* This means that we have determined that the result is
9839 equivalent to a constant. This should be rare. */
9840 x = GEN_INT (outer_const);
9841 else if (GET_RTX_CLASS (outer_op) == '1')
9842 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9844 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9850 /* Like recog, but we receive the address of a pointer to a new pattern.
9851 We try to match the rtx that the pointer points to.
9852 If that fails, we may try to modify or replace the pattern,
9853 storing the replacement into the same pointer object.
9855 Modifications include deletion or addition of CLOBBERs.
9857 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9858 the CLOBBERs are placed.
9860 The value is the final insn code from the pattern ultimately matched,
9864 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9867 int insn_code_number;
9868 int num_clobbers_to_add = 0;
9873 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9874 we use to indicate that something didn't match. If we find such a
9875 thing, force rejection. */
9876 if (GET_CODE (pat) == PARALLEL)
9877 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9878 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9879 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9882 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9883 instruction for pattern recognition. */
9884 dummy_insn = shallow_copy_rtx (insn);
9885 PATTERN (dummy_insn) = pat;
9886 REG_NOTES (dummy_insn) = 0;
9888 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9890 /* If it isn't, there is the possibility that we previously had an insn
9891 that clobbered some register as a side effect, but the combined
9892 insn doesn't need to do that. So try once more without the clobbers
9893 unless this represents an ASM insn. */
9895 if (insn_code_number < 0 && ! check_asm_operands (pat)
9896 && GET_CODE (pat) == PARALLEL)
9900 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9901 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9904 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9908 SUBST_INT (XVECLEN (pat, 0), pos);
9911 pat = XVECEXP (pat, 0, 0);
9913 PATTERN (dummy_insn) = pat;
9914 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9917 /* Recognize all noop sets, these will be killed by followup pass. */
9918 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9919 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9921 /* If we had any clobbers to add, make a new pattern than contains
9922 them. Then check to make sure that all of them are dead. */
9923 if (num_clobbers_to_add)
9925 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9926 rtvec_alloc (GET_CODE (pat) == PARALLEL
9928 + num_clobbers_to_add)
9929 : num_clobbers_to_add + 1));
9931 if (GET_CODE (pat) == PARALLEL)
9932 for (i = 0; i < XVECLEN (pat, 0); i++)
9933 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9935 XVECEXP (newpat, 0, 0) = pat;
9937 add_clobbers (newpat, insn_code_number);
9939 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9940 i < XVECLEN (newpat, 0); i++)
9942 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9943 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9945 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9946 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9954 return insn_code_number;
9957 /* Like gen_lowpart but for use by combine. In combine it is not possible
9958 to create any new pseudoregs. However, it is safe to create
9959 invalid memory addresses, because combine will try to recognize
9960 them and all they will do is make the combine attempt fail.
9962 If for some reason this cannot do its job, an rtx
9963 (clobber (const_int 0)) is returned.
9964 An insn containing that will not be recognized. */
9969 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9973 if (GET_MODE (x) == mode)
9976 /* Return identity if this is a CONST or symbolic
9979 && (GET_CODE (x) == CONST
9980 || GET_CODE (x) == SYMBOL_REF
9981 || GET_CODE (x) == LABEL_REF))
9984 /* We can only support MODE being wider than a word if X is a
9985 constant integer or has a mode the same size. */
9987 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9988 && ! ((GET_MODE (x) == VOIDmode
9989 && (GET_CODE (x) == CONST_INT
9990 || GET_CODE (x) == CONST_DOUBLE))
9991 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9992 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9994 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9995 won't know what to do. So we will strip off the SUBREG here and
9996 process normally. */
9997 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10000 if (GET_MODE (x) == mode)
10004 result = gen_lowpart_common (mode, x);
10005 #ifdef CANNOT_CHANGE_MODE_CLASS
10007 && GET_CODE (result) == SUBREG
10008 && GET_CODE (SUBREG_REG (result)) == REG
10009 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10010 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10012 + GET_MODE (result));
10018 if (GET_CODE (x) == MEM)
10022 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10024 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10025 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10027 /* If we want to refer to something bigger than the original memref,
10028 generate a perverse subreg instead. That will force a reload
10029 of the original memref X. */
10030 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10031 return gen_rtx_SUBREG (mode, x, 0);
10033 if (WORDS_BIG_ENDIAN)
10034 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10035 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10037 if (BYTES_BIG_ENDIAN)
10039 /* Adjust the address so that the address-after-the-data is
10041 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10042 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10045 return adjust_address_nv (x, mode, offset);
10048 /* If X is a comparison operator, rewrite it in a new mode. This
10049 probably won't match, but may allow further simplifications. */
10050 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10051 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10053 /* If we couldn't simplify X any other way, just enclose it in a
10054 SUBREG. Normally, this SUBREG won't match, but some patterns may
10055 include an explicit SUBREG or we may simplify it further in combine. */
10060 enum machine_mode sub_mode = GET_MODE (x);
10062 offset = subreg_lowpart_offset (mode, sub_mode);
10063 if (sub_mode == VOIDmode)
10065 sub_mode = int_mode_for_mode (mode);
10066 x = gen_lowpart_common (sub_mode, x);
10068 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
10070 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10073 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10077 /* These routines make binary and unary operations by first seeing if they
10078 fold; if not, a new expression is allocated. */
10081 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
10086 if (GET_CODE (op0) == CLOBBER)
10088 else if (GET_CODE (op1) == CLOBBER)
10091 if (GET_RTX_CLASS (code) == 'c'
10092 && swap_commutative_operands_p (op0, op1))
10093 tem = op0, op0 = op1, op1 = tem;
10095 if (GET_RTX_CLASS (code) == '<')
10097 enum machine_mode op_mode = GET_MODE (op0);
10099 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10100 just (REL_OP X Y). */
10101 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10103 op1 = XEXP (op0, 1);
10104 op0 = XEXP (op0, 0);
10105 op_mode = GET_MODE (op0);
10108 if (op_mode == VOIDmode)
10109 op_mode = GET_MODE (op1);
10110 result = simplify_relational_operation (code, op_mode, op0, op1);
10113 result = simplify_binary_operation (code, mode, op0, op1);
10118 /* Put complex operands first and constants second. */
10119 if (GET_RTX_CLASS (code) == 'c'
10120 && swap_commutative_operands_p (op0, op1))
10121 return gen_rtx_fmt_ee (code, mode, op1, op0);
10123 /* If we are turning off bits already known off in OP0, we need not do
10125 else if (code == AND && GET_CODE (op1) == CONST_INT
10126 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10127 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10130 return gen_rtx_fmt_ee (code, mode, op0, op1);
10133 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10134 comparison code that will be tested.
10136 The result is a possibly different comparison code to use. *POP0 and
10137 *POP1 may be updated.
10139 It is possible that we might detect that a comparison is either always
10140 true or always false. However, we do not perform general constant
10141 folding in combine, so this knowledge isn't useful. Such tautologies
10142 should have been detected earlier. Hence we ignore all such cases. */
10144 static enum rtx_code
10145 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10151 enum machine_mode mode, tmode;
10153 /* Try a few ways of applying the same transformation to both operands. */
10156 #ifndef WORD_REGISTER_OPERATIONS
10157 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10158 so check specially. */
10159 if (code != GTU && code != GEU && code != LTU && code != LEU
10160 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10161 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10162 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10163 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10164 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10165 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10166 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10167 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10168 && XEXP (op0, 1) == XEXP (op1, 1)
10169 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10170 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10171 && (INTVAL (XEXP (op0, 1))
10172 == (GET_MODE_BITSIZE (GET_MODE (op0))
10173 - (GET_MODE_BITSIZE
10174 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10176 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10177 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10181 /* If both operands are the same constant shift, see if we can ignore the
10182 shift. We can if the shift is a rotate or if the bits shifted out of
10183 this shift are known to be zero for both inputs and if the type of
10184 comparison is compatible with the shift. */
10185 if (GET_CODE (op0) == GET_CODE (op1)
10186 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10187 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10188 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10189 && (code != GT && code != LT && code != GE && code != LE))
10190 || (GET_CODE (op0) == ASHIFTRT
10191 && (code != GTU && code != LTU
10192 && code != GEU && code != LEU)))
10193 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10194 && INTVAL (XEXP (op0, 1)) >= 0
10195 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10196 && XEXP (op0, 1) == XEXP (op1, 1))
10198 enum machine_mode mode = GET_MODE (op0);
10199 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10200 int shift_count = INTVAL (XEXP (op0, 1));
10202 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10203 mask &= (mask >> shift_count) << shift_count;
10204 else if (GET_CODE (op0) == ASHIFT)
10205 mask = (mask & (mask << shift_count)) >> shift_count;
10207 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10208 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10209 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10214 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10215 SUBREGs are of the same mode, and, in both cases, the AND would
10216 be redundant if the comparison was done in the narrower mode,
10217 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10218 and the operand's possibly nonzero bits are 0xffffff01; in that case
10219 if we only care about QImode, we don't need the AND). This case
10220 occurs if the output mode of an scc insn is not SImode and
10221 STORE_FLAG_VALUE == 1 (e.g., the 386).
10223 Similarly, check for a case where the AND's are ZERO_EXTEND
10224 operations from some narrower mode even though a SUBREG is not
10227 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10228 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10229 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10231 rtx inner_op0 = XEXP (op0, 0);
10232 rtx inner_op1 = XEXP (op1, 0);
10233 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10234 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10237 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10238 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10239 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10240 && (GET_MODE (SUBREG_REG (inner_op0))
10241 == GET_MODE (SUBREG_REG (inner_op1)))
10242 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10243 <= HOST_BITS_PER_WIDE_INT)
10244 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10245 GET_MODE (SUBREG_REG (inner_op0)))))
10246 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10247 GET_MODE (SUBREG_REG (inner_op1))))))
10249 op0 = SUBREG_REG (inner_op0);
10250 op1 = SUBREG_REG (inner_op1);
10252 /* The resulting comparison is always unsigned since we masked
10253 off the original sign bit. */
10254 code = unsigned_condition (code);
10260 for (tmode = GET_CLASS_NARROWEST_MODE
10261 (GET_MODE_CLASS (GET_MODE (op0)));
10262 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10263 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10265 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10266 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10267 code = unsigned_condition (code);
10276 /* If both operands are NOT, we can strip off the outer operation
10277 and adjust the comparison code for swapped operands; similarly for
10278 NEG, except that this must be an equality comparison. */
10279 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10280 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10281 && (code == EQ || code == NE)))
10282 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10288 /* If the first operand is a constant, swap the operands and adjust the
10289 comparison code appropriately, but don't do this if the second operand
10290 is already a constant integer. */
10291 if (swap_commutative_operands_p (op0, op1))
10293 tem = op0, op0 = op1, op1 = tem;
10294 code = swap_condition (code);
10297 /* We now enter a loop during which we will try to simplify the comparison.
10298 For the most part, we only are concerned with comparisons with zero,
10299 but some things may really be comparisons with zero but not start
10300 out looking that way. */
10302 while (GET_CODE (op1) == CONST_INT)
10304 enum machine_mode mode = GET_MODE (op0);
10305 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10306 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10307 int equality_comparison_p;
10308 int sign_bit_comparison_p;
10309 int unsigned_comparison_p;
10310 HOST_WIDE_INT const_op;
10312 /* We only want to handle integral modes. This catches VOIDmode,
10313 CCmode, and the floating-point modes. An exception is that we
10314 can handle VOIDmode if OP0 is a COMPARE or a comparison
10317 if (GET_MODE_CLASS (mode) != MODE_INT
10318 && ! (mode == VOIDmode
10319 && (GET_CODE (op0) == COMPARE
10320 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10323 /* Get the constant we are comparing against and turn off all bits
10324 not on in our mode. */
10325 const_op = INTVAL (op1);
10326 if (mode != VOIDmode)
10327 const_op = trunc_int_for_mode (const_op, mode);
10328 op1 = GEN_INT (const_op);
10330 /* If we are comparing against a constant power of two and the value
10331 being compared can only have that single bit nonzero (e.g., it was
10332 `and'ed with that bit), we can replace this with a comparison
10335 && (code == EQ || code == NE || code == GE || code == GEU
10336 || code == LT || code == LTU)
10337 && mode_width <= HOST_BITS_PER_WIDE_INT
10338 && exact_log2 (const_op) >= 0
10339 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10341 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10342 op1 = const0_rtx, const_op = 0;
10345 /* Similarly, if we are comparing a value known to be either -1 or
10346 0 with -1, change it to the opposite comparison against zero. */
10349 && (code == EQ || code == NE || code == GT || code == LE
10350 || code == GEU || code == LTU)
10351 && num_sign_bit_copies (op0, mode) == mode_width)
10353 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10354 op1 = const0_rtx, const_op = 0;
10357 /* Do some canonicalizations based on the comparison code. We prefer
10358 comparisons against zero and then prefer equality comparisons.
10359 If we can reduce the size of a constant, we will do that too. */
10364 /* < C is equivalent to <= (C - 1) */
10368 op1 = GEN_INT (const_op);
10370 /* ... fall through to LE case below. */
10376 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10380 op1 = GEN_INT (const_op);
10384 /* If we are doing a <= 0 comparison on a value known to have
10385 a zero sign bit, we can replace this with == 0. */
10386 else if (const_op == 0
10387 && mode_width <= HOST_BITS_PER_WIDE_INT
10388 && (nonzero_bits (op0, mode)
10389 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10394 /* >= C is equivalent to > (C - 1). */
10398 op1 = GEN_INT (const_op);
10400 /* ... fall through to GT below. */
10406 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10410 op1 = GEN_INT (const_op);
10414 /* If we are doing a > 0 comparison on a value known to have
10415 a zero sign bit, we can replace this with != 0. */
10416 else if (const_op == 0
10417 && mode_width <= HOST_BITS_PER_WIDE_INT
10418 && (nonzero_bits (op0, mode)
10419 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10424 /* < C is equivalent to <= (C - 1). */
10428 op1 = GEN_INT (const_op);
10430 /* ... fall through ... */
10433 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10434 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10435 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10437 const_op = 0, op1 = const0_rtx;
10445 /* unsigned <= 0 is equivalent to == 0 */
10449 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10450 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10451 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10453 const_op = 0, op1 = const0_rtx;
10459 /* >= C is equivalent to < (C - 1). */
10463 op1 = GEN_INT (const_op);
10465 /* ... fall through ... */
10468 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10469 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10470 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10472 const_op = 0, op1 = const0_rtx;
10480 /* unsigned > 0 is equivalent to != 0 */
10484 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10485 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10486 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10488 const_op = 0, op1 = const0_rtx;
10497 /* Compute some predicates to simplify code below. */
10499 equality_comparison_p = (code == EQ || code == NE);
10500 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10501 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10504 /* If this is a sign bit comparison and we can do arithmetic in
10505 MODE, say that we will only be needing the sign bit of OP0. */
10506 if (sign_bit_comparison_p
10507 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10508 op0 = force_to_mode (op0, mode,
10510 << (GET_MODE_BITSIZE (mode) - 1)),
10513 /* Now try cases based on the opcode of OP0. If none of the cases
10514 does a "continue", we exit this loop immediately after the
10517 switch (GET_CODE (op0))
10520 /* If we are extracting a single bit from a variable position in
10521 a constant that has only a single bit set and are comparing it
10522 with zero, we can convert this into an equality comparison
10523 between the position and the location of the single bit. */
10525 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10526 && XEXP (op0, 1) == const1_rtx
10527 && equality_comparison_p && const_op == 0
10528 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10530 if (BITS_BIG_ENDIAN)
10532 enum machine_mode new_mode
10533 = mode_for_extraction (EP_extzv, 1);
10534 if (new_mode == MAX_MACHINE_MODE)
10535 i = BITS_PER_WORD - 1 - i;
10539 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10543 op0 = XEXP (op0, 2);
10547 /* Result is nonzero iff shift count is equal to I. */
10548 code = reverse_condition (code);
10552 /* ... fall through ... */
10555 tem = expand_compound_operation (op0);
10564 /* If testing for equality, we can take the NOT of the constant. */
10565 if (equality_comparison_p
10566 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10568 op0 = XEXP (op0, 0);
10573 /* If just looking at the sign bit, reverse the sense of the
10575 if (sign_bit_comparison_p)
10577 op0 = XEXP (op0, 0);
10578 code = (code == GE ? LT : GE);
10584 /* If testing for equality, we can take the NEG of the constant. */
10585 if (equality_comparison_p
10586 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10588 op0 = XEXP (op0, 0);
10593 /* The remaining cases only apply to comparisons with zero. */
10597 /* When X is ABS or is known positive,
10598 (neg X) is < 0 if and only if X != 0. */
10600 if (sign_bit_comparison_p
10601 && (GET_CODE (XEXP (op0, 0)) == ABS
10602 || (mode_width <= HOST_BITS_PER_WIDE_INT
10603 && (nonzero_bits (XEXP (op0, 0), mode)
10604 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10606 op0 = XEXP (op0, 0);
10607 code = (code == LT ? NE : EQ);
10611 /* If we have NEG of something whose two high-order bits are the
10612 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10613 if (num_sign_bit_copies (op0, mode) >= 2)
10615 op0 = XEXP (op0, 0);
10616 code = swap_condition (code);
10622 /* If we are testing equality and our count is a constant, we
10623 can perform the inverse operation on our RHS. */
10624 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10625 && (tem = simplify_binary_operation (ROTATERT, mode,
10626 op1, XEXP (op0, 1))) != 0)
10628 op0 = XEXP (op0, 0);
10633 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10634 a particular bit. Convert it to an AND of a constant of that
10635 bit. This will be converted into a ZERO_EXTRACT. */
10636 if (const_op == 0 && sign_bit_comparison_p
10637 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10638 && mode_width <= HOST_BITS_PER_WIDE_INT)
10640 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10643 - INTVAL (XEXP (op0, 1)))));
10644 code = (code == LT ? NE : EQ);
10648 /* Fall through. */
10651 /* ABS is ignorable inside an equality comparison with zero. */
10652 if (const_op == 0 && equality_comparison_p)
10654 op0 = XEXP (op0, 0);
10660 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10661 to (compare FOO CONST) if CONST fits in FOO's mode and we
10662 are either testing inequality or have an unsigned comparison
10663 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10664 if (! unsigned_comparison_p
10665 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10666 <= HOST_BITS_PER_WIDE_INT)
10667 && ((unsigned HOST_WIDE_INT) const_op
10668 < (((unsigned HOST_WIDE_INT) 1
10669 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10671 op0 = XEXP (op0, 0);
10677 /* Check for the case where we are comparing A - C1 with C2,
10678 both constants are smaller than 1/2 the maximum positive
10679 value in MODE, and the comparison is equality or unsigned.
10680 In that case, if A is either zero-extended to MODE or has
10681 sufficient sign bits so that the high-order bit in MODE
10682 is a copy of the sign in the inner mode, we can prove that it is
10683 safe to do the operation in the wider mode. This simplifies
10684 many range checks. */
10686 if (mode_width <= HOST_BITS_PER_WIDE_INT
10687 && subreg_lowpart_p (op0)
10688 && GET_CODE (SUBREG_REG (op0)) == PLUS
10689 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10690 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10691 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10692 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10693 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10694 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10695 GET_MODE (SUBREG_REG (op0)))
10696 & ~GET_MODE_MASK (mode))
10697 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10698 GET_MODE (SUBREG_REG (op0)))
10700 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10701 - GET_MODE_BITSIZE (mode)))))
10703 op0 = SUBREG_REG (op0);
10707 /* If the inner mode is narrower and we are extracting the low part,
10708 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10709 if (subreg_lowpart_p (op0)
10710 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10711 /* Fall through */ ;
10715 /* ... fall through ... */
10718 if ((unsigned_comparison_p || equality_comparison_p)
10719 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10720 <= HOST_BITS_PER_WIDE_INT)
10721 && ((unsigned HOST_WIDE_INT) const_op
10722 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10724 op0 = XEXP (op0, 0);
10730 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10731 this for equality comparisons due to pathological cases involving
10733 if (equality_comparison_p
10734 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10735 op1, XEXP (op0, 1))))
10737 op0 = XEXP (op0, 0);
10742 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10743 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10744 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10746 op0 = XEXP (XEXP (op0, 0), 0);
10747 code = (code == LT ? EQ : NE);
10753 /* We used to optimize signed comparisons against zero, but that
10754 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10755 arrive here as equality comparisons, or (GEU, LTU) are
10756 optimized away. No need to special-case them. */
10758 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10759 (eq B (minus A C)), whichever simplifies. We can only do
10760 this for equality comparisons due to pathological cases involving
10762 if (equality_comparison_p
10763 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10764 XEXP (op0, 1), op1)))
10766 op0 = XEXP (op0, 0);
10771 if (equality_comparison_p
10772 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10773 XEXP (op0, 0), op1)))
10775 op0 = XEXP (op0, 1);
10780 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10781 of bits in X minus 1, is one iff X > 0. */
10782 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10783 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10784 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10786 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10788 op0 = XEXP (op0, 1);
10789 code = (code == GE ? LE : GT);
10795 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10796 if C is zero or B is a constant. */
10797 if (equality_comparison_p
10798 && 0 != (tem = simplify_binary_operation (XOR, mode,
10799 XEXP (op0, 1), op1)))
10801 op0 = XEXP (op0, 0);
10808 case UNEQ: case LTGT:
10809 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10810 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10811 case UNORDERED: case ORDERED:
10812 /* We can't do anything if OP0 is a condition code value, rather
10813 than an actual data value. */
10815 || CC0_P (XEXP (op0, 0))
10816 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10819 /* Get the two operands being compared. */
10820 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10821 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10823 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10825 /* Check for the cases where we simply want the result of the
10826 earlier test or the opposite of that result. */
10827 if (code == NE || code == EQ
10828 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10829 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10830 && (STORE_FLAG_VALUE
10831 & (((HOST_WIDE_INT) 1
10832 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10833 && (code == LT || code == GE)))
10835 enum rtx_code new_code;
10836 if (code == LT || code == NE)
10837 new_code = GET_CODE (op0);
10839 new_code = combine_reversed_comparison_code (op0);
10841 if (new_code != UNKNOWN)
10852 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10854 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10855 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10856 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10858 op0 = XEXP (op0, 1);
10859 code = (code == GE ? GT : LE);
10865 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10866 will be converted to a ZERO_EXTRACT later. */
10867 if (const_op == 0 && equality_comparison_p
10868 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10869 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10871 op0 = simplify_and_const_int
10872 (op0, mode, gen_rtx_LSHIFTRT (mode,
10874 XEXP (XEXP (op0, 0), 1)),
10875 (HOST_WIDE_INT) 1);
10879 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10880 zero and X is a comparison and C1 and C2 describe only bits set
10881 in STORE_FLAG_VALUE, we can compare with X. */
10882 if (const_op == 0 && equality_comparison_p
10883 && mode_width <= HOST_BITS_PER_WIDE_INT
10884 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10885 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10886 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10887 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10888 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10890 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10891 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10892 if ((~STORE_FLAG_VALUE & mask) == 0
10893 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10894 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10895 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10897 op0 = XEXP (XEXP (op0, 0), 0);
10902 /* If we are doing an equality comparison of an AND of a bit equal
10903 to the sign bit, replace this with a LT or GE comparison of
10904 the underlying value. */
10905 if (equality_comparison_p
10907 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10908 && mode_width <= HOST_BITS_PER_WIDE_INT
10909 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10910 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10912 op0 = XEXP (op0, 0);
10913 code = (code == EQ ? GE : LT);
10917 /* If this AND operation is really a ZERO_EXTEND from a narrower
10918 mode, the constant fits within that mode, and this is either an
10919 equality or unsigned comparison, try to do this comparison in
10920 the narrower mode. */
10921 if ((equality_comparison_p || unsigned_comparison_p)
10922 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10923 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10924 & GET_MODE_MASK (mode))
10926 && const_op >> i == 0
10927 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10929 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10933 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10934 fits in both M1 and M2 and the SUBREG is either paradoxical
10935 or represents the low part, permute the SUBREG and the AND
10937 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10939 unsigned HOST_WIDE_INT c1;
10940 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10941 /* Require an integral mode, to avoid creating something like
10943 if (SCALAR_INT_MODE_P (tmode)
10944 /* It is unsafe to commute the AND into the SUBREG if the
10945 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10946 not defined. As originally written the upper bits
10947 have a defined value due to the AND operation.
10948 However, if we commute the AND inside the SUBREG then
10949 they no longer have defined values and the meaning of
10950 the code has been changed. */
10952 #ifdef WORD_REGISTER_OPERATIONS
10953 || (mode_width > GET_MODE_BITSIZE (tmode)
10954 && mode_width <= BITS_PER_WORD)
10956 || (mode_width <= GET_MODE_BITSIZE (tmode)
10957 && subreg_lowpart_p (XEXP (op0, 0))))
10958 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10959 && mode_width <= HOST_BITS_PER_WIDE_INT
10960 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10961 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10962 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10964 && c1 != GET_MODE_MASK (tmode))
10966 op0 = gen_binary (AND, tmode,
10967 SUBREG_REG (XEXP (op0, 0)),
10968 gen_int_mode (c1, tmode));
10969 op0 = gen_lowpart_for_combine (mode, op0);
10974 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10975 if (const_op == 0 && equality_comparison_p
10976 && XEXP (op0, 1) == const1_rtx
10977 && GET_CODE (XEXP (op0, 0)) == NOT)
10979 op0 = simplify_and_const_int
10980 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10981 code = (code == NE ? EQ : NE);
10985 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10986 (eq (and (lshiftrt X) 1) 0). */
10987 if (const_op == 0 && equality_comparison_p
10988 && XEXP (op0, 1) == const1_rtx
10989 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10990 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10992 op0 = simplify_and_const_int
10994 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10995 XEXP (XEXP (op0, 0), 1)),
10996 (HOST_WIDE_INT) 1);
10997 code = (code == NE ? EQ : NE);
11003 /* If we have (compare (ashift FOO N) (const_int C)) and
11004 the high order N bits of FOO (N+1 if an inequality comparison)
11005 are known to be zero, we can do this by comparing FOO with C
11006 shifted right N bits so long as the low-order N bits of C are
11008 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11009 && INTVAL (XEXP (op0, 1)) >= 0
11010 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11011 < HOST_BITS_PER_WIDE_INT)
11013 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11014 && mode_width <= HOST_BITS_PER_WIDE_INT
11015 && (nonzero_bits (XEXP (op0, 0), mode)
11016 & ~(mask >> (INTVAL (XEXP (op0, 1))
11017 + ! equality_comparison_p))) == 0)
11019 /* We must perform a logical shift, not an arithmetic one,
11020 as we want the top N bits of C to be zero. */
11021 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11023 temp >>= INTVAL (XEXP (op0, 1));
11024 op1 = gen_int_mode (temp, mode);
11025 op0 = XEXP (op0, 0);
11029 /* If we are doing a sign bit comparison, it means we are testing
11030 a particular bit. Convert it to the appropriate AND. */
11031 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11032 && mode_width <= HOST_BITS_PER_WIDE_INT)
11034 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11037 - INTVAL (XEXP (op0, 1)))));
11038 code = (code == LT ? NE : EQ);
11042 /* If this an equality comparison with zero and we are shifting
11043 the low bit to the sign bit, we can convert this to an AND of the
11045 if (const_op == 0 && equality_comparison_p
11046 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11047 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11050 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11051 (HOST_WIDE_INT) 1);
11057 /* If this is an equality comparison with zero, we can do this
11058 as a logical shift, which might be much simpler. */
11059 if (equality_comparison_p && const_op == 0
11060 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11062 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11064 INTVAL (XEXP (op0, 1)));
11068 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11069 do the comparison in a narrower mode. */
11070 if (! unsigned_comparison_p
11071 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11072 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11073 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11074 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11075 MODE_INT, 1)) != BLKmode
11076 && (((unsigned HOST_WIDE_INT) const_op
11077 + (GET_MODE_MASK (tmode) >> 1) + 1)
11078 <= GET_MODE_MASK (tmode)))
11080 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11084 /* Likewise if OP0 is a PLUS of a sign extension with a
11085 constant, which is usually represented with the PLUS
11086 between the shifts. */
11087 if (! unsigned_comparison_p
11088 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11089 && GET_CODE (XEXP (op0, 0)) == PLUS
11090 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11091 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11092 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11093 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11094 MODE_INT, 1)) != BLKmode
11095 && (((unsigned HOST_WIDE_INT) const_op
11096 + (GET_MODE_MASK (tmode) >> 1) + 1)
11097 <= GET_MODE_MASK (tmode)))
11099 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11100 rtx add_const = XEXP (XEXP (op0, 0), 1);
11101 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11104 op0 = gen_binary (PLUS, tmode,
11105 gen_lowpart_for_combine (tmode, inner),
11110 /* ... fall through ... */
11112 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11113 the low order N bits of FOO are known to be zero, we can do this
11114 by comparing FOO with C shifted left N bits so long as no
11115 overflow occurs. */
11116 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11117 && INTVAL (XEXP (op0, 1)) >= 0
11118 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11119 && mode_width <= HOST_BITS_PER_WIDE_INT
11120 && (nonzero_bits (XEXP (op0, 0), mode)
11121 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11122 && (((unsigned HOST_WIDE_INT) const_op
11123 + (GET_CODE (op0) != LSHIFTRT
11124 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11127 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11129 /* If the shift was logical, then we must make the condition
11131 if (GET_CODE (op0) == LSHIFTRT)
11132 code = unsigned_condition (code);
11134 const_op <<= INTVAL (XEXP (op0, 1));
11135 op1 = GEN_INT (const_op);
11136 op0 = XEXP (op0, 0);
11140 /* If we are using this shift to extract just the sign bit, we
11141 can replace this with an LT or GE comparison. */
11143 && (equality_comparison_p || sign_bit_comparison_p)
11144 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11145 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11148 op0 = XEXP (op0, 0);
11149 code = (code == NE || code == GT ? LT : GE);
11161 /* Now make any compound operations involved in this comparison. Then,
11162 check for an outmost SUBREG on OP0 that is not doing anything or is
11163 paradoxical. The latter transformation must only be performed when
11164 it is known that the "extra" bits will be the same in op0 and op1 or
11165 that they don't matter. There are three cases to consider:
11167 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11168 care bits and we can assume they have any convenient value. So
11169 making the transformation is safe.
11171 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11172 In this case the upper bits of op0 are undefined. We should not make
11173 the simplification in that case as we do not know the contents of
11176 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11177 NIL. In that case we know those bits are zeros or ones. We must
11178 also be sure that they are the same as the upper bits of op1.
11180 We can never remove a SUBREG for a non-equality comparison because
11181 the sign bit is in a different place in the underlying object. */
11183 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11184 op1 = make_compound_operation (op1, SET);
11186 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11187 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11188 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11189 && (code == NE || code == EQ))
11191 if (GET_MODE_SIZE (GET_MODE (op0))
11192 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11194 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11196 if (GET_CODE (SUBREG_REG (op0)) == REG)
11198 op0 = SUBREG_REG (op0);
11199 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11202 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11203 <= HOST_BITS_PER_WIDE_INT)
11204 && (nonzero_bits (SUBREG_REG (op0),
11205 GET_MODE (SUBREG_REG (op0)))
11206 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11208 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11210 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11211 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11212 op0 = SUBREG_REG (op0), op1 = tem;
11216 /* We now do the opposite procedure: Some machines don't have compare
11217 insns in all modes. If OP0's mode is an integer mode smaller than a
11218 word and we can't do a compare in that mode, see if there is a larger
11219 mode for which we can do the compare. There are a number of cases in
11220 which we can use the wider mode. */
11222 mode = GET_MODE (op0);
11223 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11224 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11225 && ! have_insn_for (COMPARE, mode))
11226 for (tmode = GET_MODE_WIDER_MODE (mode);
11228 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11229 tmode = GET_MODE_WIDER_MODE (tmode))
11230 if (have_insn_for (COMPARE, tmode))
11234 /* If the only nonzero bits in OP0 and OP1 are those in the
11235 narrower mode and this is an equality or unsigned comparison,
11236 we can use the wider mode. Similarly for sign-extended
11237 values, in which case it is true for all comparisons. */
11238 zero_extended = ((code == EQ || code == NE
11239 || code == GEU || code == GTU
11240 || code == LEU || code == LTU)
11241 && (nonzero_bits (op0, tmode)
11242 & ~GET_MODE_MASK (mode)) == 0
11243 && ((GET_CODE (op1) == CONST_INT
11244 || (nonzero_bits (op1, tmode)
11245 & ~GET_MODE_MASK (mode)) == 0)));
11248 || ((num_sign_bit_copies (op0, tmode)
11249 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11250 - GET_MODE_BITSIZE (mode)))
11251 && (num_sign_bit_copies (op1, tmode)
11252 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11253 - GET_MODE_BITSIZE (mode)))))
11255 /* If OP0 is an AND and we don't have an AND in MODE either,
11256 make a new AND in the proper mode. */
11257 if (GET_CODE (op0) == AND
11258 && !have_insn_for (AND, mode))
11259 op0 = gen_binary (AND, tmode,
11260 gen_lowpart_for_combine (tmode,
11262 gen_lowpart_for_combine (tmode,
11265 op0 = gen_lowpart_for_combine (tmode, op0);
11266 if (zero_extended && GET_CODE (op1) == CONST_INT)
11267 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11268 op1 = gen_lowpart_for_combine (tmode, op1);
11272 /* If this is a test for negative, we can make an explicit
11273 test of the sign bit. */
11275 if (op1 == const0_rtx && (code == LT || code == GE)
11276 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11278 op0 = gen_binary (AND, tmode,
11279 gen_lowpart_for_combine (tmode, op0),
11280 GEN_INT ((HOST_WIDE_INT) 1
11281 << (GET_MODE_BITSIZE (mode) - 1)));
11282 code = (code == LT) ? NE : EQ;
11287 #ifdef CANONICALIZE_COMPARISON
11288 /* If this machine only supports a subset of valid comparisons, see if we
11289 can convert an unsupported one into a supported one. */
11290 CANONICALIZE_COMPARISON (code, op0, op1);
11299 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11300 searching backward. */
11301 static enum rtx_code
11302 combine_reversed_comparison_code (rtx exp)
11304 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11307 if (code1 != UNKNOWN
11308 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11310 /* Otherwise try and find where the condition codes were last set and
11312 x = get_last_value (XEXP (exp, 0));
11313 if (!x || GET_CODE (x) != COMPARE)
11315 return reversed_comparison_code_parts (GET_CODE (exp),
11316 XEXP (x, 0), XEXP (x, 1), NULL);
11319 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11320 Return NULL_RTX in case we fail to do the reversal. */
11322 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
11324 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11325 if (reversed_code == UNKNOWN)
11328 return gen_binary (reversed_code, mode, op0, op1);
11331 /* Utility function for following routine. Called when X is part of a value
11332 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11333 for each register mentioned. Similar to mention_regs in cse.c */
11336 update_table_tick (rtx x)
11338 enum rtx_code code = GET_CODE (x);
11339 const char *fmt = GET_RTX_FORMAT (code);
11344 unsigned int regno = REGNO (x);
11345 unsigned int endregno
11346 = regno + (regno < FIRST_PSEUDO_REGISTER
11347 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11350 for (r = regno; r < endregno; r++)
11351 reg_last_set_table_tick[r] = label_tick;
11356 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11357 /* Note that we can't have an "E" in values stored; see
11358 get_last_value_validate. */
11361 /* Check for identical subexpressions. If x contains
11362 identical subexpression we only have to traverse one of
11365 && (GET_RTX_CLASS (code) == '2'
11366 || GET_RTX_CLASS (code) == 'c'))
11368 /* Note that at this point x1 has already been
11370 rtx x0 = XEXP (x, 0);
11371 rtx x1 = XEXP (x, 1);
11373 /* If x0 and x1 are identical then there is no need to
11378 /* If x0 is identical to a subexpression of x1 then while
11379 processing x1, x0 has already been processed. Thus we
11380 are done with x. */
11381 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11382 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11383 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11386 /* If x1 is identical to a subexpression of x0 then we
11387 still have to process the rest of x0. */
11388 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11389 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11390 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11392 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11397 update_table_tick (XEXP (x, i));
11401 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11402 are saying that the register is clobbered and we no longer know its
11403 value. If INSN is zero, don't update reg_last_set; this is only permitted
11404 with VALUE also zero and is used to invalidate the register. */
11407 record_value_for_reg (rtx reg, rtx insn, rtx value)
11409 unsigned int regno = REGNO (reg);
11410 unsigned int endregno
11411 = regno + (regno < FIRST_PSEUDO_REGISTER
11412 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11415 /* If VALUE contains REG and we have a previous value for REG, substitute
11416 the previous value. */
11417 if (value && insn && reg_overlap_mentioned_p (reg, value))
11421 /* Set things up so get_last_value is allowed to see anything set up to
11423 subst_low_cuid = INSN_CUID (insn);
11424 tem = get_last_value (reg);
11426 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11427 it isn't going to be useful and will take a lot of time to process,
11428 so just use the CLOBBER. */
11432 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11433 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11434 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11435 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11436 tem = XEXP (tem, 0);
11438 value = replace_rtx (copy_rtx (value), reg, tem);
11442 /* For each register modified, show we don't know its value, that
11443 we don't know about its bitwise content, that its value has been
11444 updated, and that we don't know the location of the death of the
11446 for (i = regno; i < endregno; i++)
11449 reg_last_set[i] = insn;
11451 reg_last_set_value[i] = 0;
11452 reg_last_set_mode[i] = 0;
11453 reg_last_set_nonzero_bits[i] = 0;
11454 reg_last_set_sign_bit_copies[i] = 0;
11455 reg_last_death[i] = 0;
11458 /* Mark registers that are being referenced in this value. */
11460 update_table_tick (value);
11462 /* Now update the status of each register being set.
11463 If someone is using this register in this block, set this register
11464 to invalid since we will get confused between the two lives in this
11465 basic block. This makes using this register always invalid. In cse, we
11466 scan the table to invalidate all entries using this register, but this
11467 is too much work for us. */
11469 for (i = regno; i < endregno; i++)
11471 reg_last_set_label[i] = label_tick;
11472 if (value && reg_last_set_table_tick[i] == label_tick)
11473 reg_last_set_invalid[i] = 1;
11475 reg_last_set_invalid[i] = 0;
11478 /* The value being assigned might refer to X (like in "x++;"). In that
11479 case, we must replace it with (clobber (const_int 0)) to prevent
11481 if (value && ! get_last_value_validate (&value, insn,
11482 reg_last_set_label[regno], 0))
11484 value = copy_rtx (value);
11485 if (! get_last_value_validate (&value, insn,
11486 reg_last_set_label[regno], 1))
11490 /* For the main register being modified, update the value, the mode, the
11491 nonzero bits, and the number of sign bit copies. */
11493 reg_last_set_value[regno] = value;
11497 enum machine_mode mode = GET_MODE (reg);
11498 subst_low_cuid = INSN_CUID (insn);
11499 reg_last_set_mode[regno] = mode;
11500 if (GET_MODE_CLASS (mode) == MODE_INT
11501 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11502 mode = nonzero_bits_mode;
11503 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11504 reg_last_set_sign_bit_copies[regno]
11505 = num_sign_bit_copies (value, GET_MODE (reg));
11509 /* Called via note_stores from record_dead_and_set_regs to handle one
11510 SET or CLOBBER in an insn. DATA is the instruction in which the
11511 set is occurring. */
11514 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11516 rtx record_dead_insn = (rtx) data;
11518 if (GET_CODE (dest) == SUBREG)
11519 dest = SUBREG_REG (dest);
11521 if (GET_CODE (dest) == REG)
11523 /* If we are setting the whole register, we know its value. Otherwise
11524 show that we don't know the value. We can handle SUBREG in
11526 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11527 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11528 else if (GET_CODE (setter) == SET
11529 && GET_CODE (SET_DEST (setter)) == SUBREG
11530 && SUBREG_REG (SET_DEST (setter)) == dest
11531 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11532 && subreg_lowpart_p (SET_DEST (setter)))
11533 record_value_for_reg (dest, record_dead_insn,
11534 gen_lowpart_for_combine (GET_MODE (dest),
11535 SET_SRC (setter)));
11537 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11539 else if (GET_CODE (dest) == MEM
11540 /* Ignore pushes, they clobber nothing. */
11541 && ! push_operand (dest, GET_MODE (dest)))
11542 mem_last_set = INSN_CUID (record_dead_insn);
11545 /* Update the records of when each REG was most recently set or killed
11546 for the things done by INSN. This is the last thing done in processing
11547 INSN in the combiner loop.
11549 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11550 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11551 and also the similar information mem_last_set (which insn most recently
11552 modified memory) and last_call_cuid (which insn was the most recent
11553 subroutine call). */
11556 record_dead_and_set_regs (rtx insn)
11561 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11563 if (REG_NOTE_KIND (link) == REG_DEAD
11564 && GET_CODE (XEXP (link, 0)) == REG)
11566 unsigned int regno = REGNO (XEXP (link, 0));
11567 unsigned int endregno
11568 = regno + (regno < FIRST_PSEUDO_REGISTER
11569 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11572 for (i = regno; i < endregno; i++)
11573 reg_last_death[i] = insn;
11575 else if (REG_NOTE_KIND (link) == REG_INC)
11576 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11579 if (GET_CODE (insn) == CALL_INSN)
11581 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11582 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11584 reg_last_set_value[i] = 0;
11585 reg_last_set_mode[i] = 0;
11586 reg_last_set_nonzero_bits[i] = 0;
11587 reg_last_set_sign_bit_copies[i] = 0;
11588 reg_last_death[i] = 0;
11591 last_call_cuid = mem_last_set = INSN_CUID (insn);
11593 /* Don't bother recording what this insn does. It might set the
11594 return value register, but we can't combine into a call
11595 pattern anyway, so there's no point trying (and it may cause
11596 a crash, if e.g. we wind up asking for last_set_value of a
11597 SUBREG of the return value register). */
11601 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11604 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11605 register present in the SUBREG, so for each such SUBREG go back and
11606 adjust nonzero and sign bit information of the registers that are
11607 known to have some zero/sign bits set.
11609 This is needed because when combine blows the SUBREGs away, the
11610 information on zero/sign bits is lost and further combines can be
11611 missed because of that. */
11614 record_promoted_value (rtx insn, rtx subreg)
11617 unsigned int regno = REGNO (SUBREG_REG (subreg));
11618 enum machine_mode mode = GET_MODE (subreg);
11620 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11623 for (links = LOG_LINKS (insn); links;)
11625 insn = XEXP (links, 0);
11626 set = single_set (insn);
11628 if (! set || GET_CODE (SET_DEST (set)) != REG
11629 || REGNO (SET_DEST (set)) != regno
11630 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11632 links = XEXP (links, 1);
11636 if (reg_last_set[regno] == insn)
11638 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11639 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11642 if (GET_CODE (SET_SRC (set)) == REG)
11644 regno = REGNO (SET_SRC (set));
11645 links = LOG_LINKS (insn);
11652 /* Scan X for promoted SUBREGs. For each one found,
11653 note what it implies to the registers used in it. */
11656 check_promoted_subreg (rtx insn, rtx x)
11658 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11659 && GET_CODE (SUBREG_REG (x)) == REG)
11660 record_promoted_value (insn, x);
11663 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11666 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11670 check_promoted_subreg (insn, XEXP (x, i));
11674 if (XVEC (x, i) != 0)
11675 for (j = 0; j < XVECLEN (x, i); j++)
11676 check_promoted_subreg (insn, XVECEXP (x, i, j));
11682 /* Utility routine for the following function. Verify that all the registers
11683 mentioned in *LOC are valid when *LOC was part of a value set when
11684 label_tick == TICK. Return 0 if some are not.
11686 If REPLACE is nonzero, replace the invalid reference with
11687 (clobber (const_int 0)) and return 1. This replacement is useful because
11688 we often can get useful information about the form of a value (e.g., if
11689 it was produced by a shift that always produces -1 or 0) even though
11690 we don't know exactly what registers it was produced from. */
11693 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11696 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11697 int len = GET_RTX_LENGTH (GET_CODE (x));
11700 if (GET_CODE (x) == REG)
11702 unsigned int regno = REGNO (x);
11703 unsigned int endregno
11704 = regno + (regno < FIRST_PSEUDO_REGISTER
11705 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11708 for (j = regno; j < endregno; j++)
11709 if (reg_last_set_invalid[j]
11710 /* If this is a pseudo-register that was only set once and not
11711 live at the beginning of the function, it is always valid. */
11712 || (! (regno >= FIRST_PSEUDO_REGISTER
11713 && REG_N_SETS (regno) == 1
11714 && (! REGNO_REG_SET_P
11715 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11716 && reg_last_set_label[j] > tick))
11719 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11725 /* If this is a memory reference, make sure that there were
11726 no stores after it that might have clobbered the value. We don't
11727 have alias info, so we assume any store invalidates it. */
11728 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11729 && INSN_CUID (insn) <= mem_last_set)
11732 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11736 for (i = 0; i < len; i++)
11740 /* Check for identical subexpressions. If x contains
11741 identical subexpression we only have to traverse one of
11744 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11745 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11747 /* Note that at this point x0 has already been checked
11748 and found valid. */
11749 rtx x0 = XEXP (x, 0);
11750 rtx x1 = XEXP (x, 1);
11752 /* If x0 and x1 are identical then x is also valid. */
11756 /* If x1 is identical to a subexpression of x0 then
11757 while checking x0, x1 has already been checked. Thus
11758 it is valid and so as x. */
11759 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11760 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11761 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11764 /* If x0 is identical to a subexpression of x1 then x is
11765 valid iff the rest of x1 is valid. */
11766 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11767 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11768 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11770 get_last_value_validate (&XEXP (x1,
11771 x0 == XEXP (x1, 0) ? 1 : 0),
11772 insn, tick, replace);
11775 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11779 /* Don't bother with these. They shouldn't occur anyway. */
11780 else if (fmt[i] == 'E')
11784 /* If we haven't found a reason for it to be invalid, it is valid. */
11788 /* Get the last value assigned to X, if known. Some registers
11789 in the value may be replaced with (clobber (const_int 0)) if their value
11790 is known longer known reliably. */
11793 get_last_value (rtx x)
11795 unsigned int regno;
11798 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11799 then convert it to the desired mode. If this is a paradoxical SUBREG,
11800 we cannot predict what values the "extra" bits might have. */
11801 if (GET_CODE (x) == SUBREG
11802 && subreg_lowpart_p (x)
11803 && (GET_MODE_SIZE (GET_MODE (x))
11804 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11805 && (value = get_last_value (SUBREG_REG (x))) != 0)
11806 return gen_lowpart_for_combine (GET_MODE (x), value);
11808 if (GET_CODE (x) != REG)
11812 value = reg_last_set_value[regno];
11814 /* If we don't have a value, or if it isn't for this basic block and
11815 it's either a hard register, set more than once, or it's a live
11816 at the beginning of the function, return 0.
11818 Because if it's not live at the beginning of the function then the reg
11819 is always set before being used (is never used without being set).
11820 And, if it's set only once, and it's always set before use, then all
11821 uses must have the same last value, even if it's not from this basic
11825 || (reg_last_set_label[regno] != label_tick
11826 && (regno < FIRST_PSEUDO_REGISTER
11827 || REG_N_SETS (regno) != 1
11828 || (REGNO_REG_SET_P
11829 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11832 /* If the value was set in a later insn than the ones we are processing,
11833 we can't use it even if the register was only set once. */
11834 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11837 /* If the value has all its registers valid, return it. */
11838 if (get_last_value_validate (&value, reg_last_set[regno],
11839 reg_last_set_label[regno], 0))
11842 /* Otherwise, make a copy and replace any invalid register with
11843 (clobber (const_int 0)). If that fails for some reason, return 0. */
11845 value = copy_rtx (value);
11846 if (get_last_value_validate (&value, reg_last_set[regno],
11847 reg_last_set_label[regno], 1))
11853 /* Return nonzero if expression X refers to a REG or to memory
11854 that is set in an instruction more recent than FROM_CUID. */
11857 use_crosses_set_p (rtx x, int from_cuid)
11861 enum rtx_code code = GET_CODE (x);
11865 unsigned int regno = REGNO (x);
11866 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11867 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11869 #ifdef PUSH_ROUNDING
11870 /* Don't allow uses of the stack pointer to be moved,
11871 because we don't know whether the move crosses a push insn. */
11872 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11875 for (; regno < endreg; regno++)
11876 if (reg_last_set[regno]
11877 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11882 if (code == MEM && mem_last_set > from_cuid)
11885 fmt = GET_RTX_FORMAT (code);
11887 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11892 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11893 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11896 else if (fmt[i] == 'e'
11897 && use_crosses_set_p (XEXP (x, i), from_cuid))
11903 /* Define three variables used for communication between the following
11906 static unsigned int reg_dead_regno, reg_dead_endregno;
11907 static int reg_dead_flag;
11909 /* Function called via note_stores from reg_dead_at_p.
11911 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11912 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11915 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11917 unsigned int regno, endregno;
11919 if (GET_CODE (dest) != REG)
11922 regno = REGNO (dest);
11923 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11924 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11926 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11927 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11930 /* Return nonzero if REG is known to be dead at INSN.
11932 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11933 referencing REG, it is dead. If we hit a SET referencing REG, it is
11934 live. Otherwise, see if it is live or dead at the start of the basic
11935 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11936 must be assumed to be always live. */
11939 reg_dead_at_p (rtx reg, rtx insn)
11944 /* Set variables for reg_dead_at_p_1. */
11945 reg_dead_regno = REGNO (reg);
11946 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11947 ? HARD_REGNO_NREGS (reg_dead_regno,
11953 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11954 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11956 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11957 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11961 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11962 beginning of function. */
11963 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11964 insn = prev_nonnote_insn (insn))
11966 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11968 return reg_dead_flag == 1 ? 1 : 0;
11970 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11974 /* Get the basic block that we were in. */
11976 block = ENTRY_BLOCK_PTR->next_bb;
11979 FOR_EACH_BB (block)
11980 if (insn == block->head)
11983 if (block == EXIT_BLOCK_PTR)
11987 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11988 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11994 /* Note hard registers in X that are used. This code is similar to
11995 that in flow.c, but much simpler since we don't care about pseudos. */
11998 mark_used_regs_combine (rtx x)
12000 RTX_CODE code = GET_CODE (x);
12001 unsigned int regno;
12014 case ADDR_DIFF_VEC:
12017 /* CC0 must die in the insn after it is set, so we don't need to take
12018 special note of it here. */
12024 /* If we are clobbering a MEM, mark any hard registers inside the
12025 address as used. */
12026 if (GET_CODE (XEXP (x, 0)) == MEM)
12027 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12032 /* A hard reg in a wide mode may really be multiple registers.
12033 If so, mark all of them just like the first. */
12034 if (regno < FIRST_PSEUDO_REGISTER)
12036 unsigned int endregno, r;
12038 /* None of this applies to the stack, frame or arg pointers. */
12039 if (regno == STACK_POINTER_REGNUM
12040 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12041 || regno == HARD_FRAME_POINTER_REGNUM
12043 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12044 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12046 || regno == FRAME_POINTER_REGNUM)
12049 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12050 for (r = regno; r < endregno; r++)
12051 SET_HARD_REG_BIT (newpat_used_regs, r);
12057 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12059 rtx testreg = SET_DEST (x);
12061 while (GET_CODE (testreg) == SUBREG
12062 || GET_CODE (testreg) == ZERO_EXTRACT
12063 || GET_CODE (testreg) == SIGN_EXTRACT
12064 || GET_CODE (testreg) == STRICT_LOW_PART)
12065 testreg = XEXP (testreg, 0);
12067 if (GET_CODE (testreg) == MEM)
12068 mark_used_regs_combine (XEXP (testreg, 0));
12070 mark_used_regs_combine (SET_SRC (x));
12078 /* Recursively scan the operands of this expression. */
12081 const char *fmt = GET_RTX_FORMAT (code);
12083 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12086 mark_used_regs_combine (XEXP (x, i));
12087 else if (fmt[i] == 'E')
12091 for (j = 0; j < XVECLEN (x, i); j++)
12092 mark_used_regs_combine (XVECEXP (x, i, j));
12098 /* Remove register number REGNO from the dead registers list of INSN.
12100 Return the note used to record the death, if there was one. */
12103 remove_death (unsigned int regno, rtx insn)
12105 rtx note = find_regno_note (insn, REG_DEAD, regno);
12109 REG_N_DEATHS (regno)--;
12110 remove_note (insn, note);
12116 /* For each register (hardware or pseudo) used within expression X, if its
12117 death is in an instruction with cuid between FROM_CUID (inclusive) and
12118 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12119 list headed by PNOTES.
12121 That said, don't move registers killed by maybe_kill_insn.
12123 This is done when X is being merged by combination into TO_INSN. These
12124 notes will then be distributed as needed. */
12127 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
12132 enum rtx_code code = GET_CODE (x);
12136 unsigned int regno = REGNO (x);
12137 rtx where_dead = reg_last_death[regno];
12138 rtx before_dead, after_dead;
12140 /* Don't move the register if it gets killed in between from and to. */
12141 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12142 && ! reg_referenced_p (x, maybe_kill_insn))
12145 /* WHERE_DEAD could be a USE insn made by combine, so first we
12146 make sure that we have insns with valid INSN_CUID values. */
12147 before_dead = where_dead;
12148 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12149 before_dead = PREV_INSN (before_dead);
12151 after_dead = where_dead;
12152 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12153 after_dead = NEXT_INSN (after_dead);
12155 if (before_dead && after_dead
12156 && INSN_CUID (before_dead) >= from_cuid
12157 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12158 || (where_dead != after_dead
12159 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12161 rtx note = remove_death (regno, where_dead);
12163 /* It is possible for the call above to return 0. This can occur
12164 when reg_last_death points to I2 or I1 that we combined with.
12165 In that case make a new note.
12167 We must also check for the case where X is a hard register
12168 and NOTE is a death note for a range of hard registers
12169 including X. In that case, we must put REG_DEAD notes for
12170 the remaining registers in place of NOTE. */
12172 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12173 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12174 > GET_MODE_SIZE (GET_MODE (x))))
12176 unsigned int deadregno = REGNO (XEXP (note, 0));
12177 unsigned int deadend
12178 = (deadregno + HARD_REGNO_NREGS (deadregno,
12179 GET_MODE (XEXP (note, 0))));
12180 unsigned int ourend
12181 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12184 for (i = deadregno; i < deadend; i++)
12185 if (i < regno || i >= ourend)
12186 REG_NOTES (where_dead)
12187 = gen_rtx_EXPR_LIST (REG_DEAD,
12189 REG_NOTES (where_dead));
12192 /* If we didn't find any note, or if we found a REG_DEAD note that
12193 covers only part of the given reg, and we have a multi-reg hard
12194 register, then to be safe we must check for REG_DEAD notes
12195 for each register other than the first. They could have
12196 their own REG_DEAD notes lying around. */
12197 else if ((note == 0
12199 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12200 < GET_MODE_SIZE (GET_MODE (x)))))
12201 && regno < FIRST_PSEUDO_REGISTER
12202 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12204 unsigned int ourend
12205 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12206 unsigned int i, offset;
12210 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12214 for (i = regno + offset; i < ourend; i++)
12215 move_deaths (regno_reg_rtx[i],
12216 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12219 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12221 XEXP (note, 1) = *pnotes;
12225 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12227 REG_N_DEATHS (regno)++;
12233 else if (GET_CODE (x) == SET)
12235 rtx dest = SET_DEST (x);
12237 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12239 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12240 that accesses one word of a multi-word item, some
12241 piece of everything register in the expression is used by
12242 this insn, so remove any old death. */
12243 /* ??? So why do we test for equality of the sizes? */
12245 if (GET_CODE (dest) == ZERO_EXTRACT
12246 || GET_CODE (dest) == STRICT_LOW_PART
12247 || (GET_CODE (dest) == SUBREG
12248 && (((GET_MODE_SIZE (GET_MODE (dest))
12249 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12250 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12251 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12253 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12257 /* If this is some other SUBREG, we know it replaces the entire
12258 value, so use that as the destination. */
12259 if (GET_CODE (dest) == SUBREG)
12260 dest = SUBREG_REG (dest);
12262 /* If this is a MEM, adjust deaths of anything used in the address.
12263 For a REG (the only other possibility), the entire value is
12264 being replaced so the old value is not used in this insn. */
12266 if (GET_CODE (dest) == MEM)
12267 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12272 else if (GET_CODE (x) == CLOBBER)
12275 len = GET_RTX_LENGTH (code);
12276 fmt = GET_RTX_FORMAT (code);
12278 for (i = 0; i < len; i++)
12283 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12284 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12287 else if (fmt[i] == 'e')
12288 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12292 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12293 pattern of an insn. X must be a REG. */
12296 reg_bitfield_target_p (rtx x, rtx body)
12300 if (GET_CODE (body) == SET)
12302 rtx dest = SET_DEST (body);
12304 unsigned int regno, tregno, endregno, endtregno;
12306 if (GET_CODE (dest) == ZERO_EXTRACT)
12307 target = XEXP (dest, 0);
12308 else if (GET_CODE (dest) == STRICT_LOW_PART)
12309 target = SUBREG_REG (XEXP (dest, 0));
12313 if (GET_CODE (target) == SUBREG)
12314 target = SUBREG_REG (target);
12316 if (GET_CODE (target) != REG)
12319 tregno = REGNO (target), regno = REGNO (x);
12320 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12321 return target == x;
12323 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12324 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12326 return endregno > tregno && regno < endtregno;
12329 else if (GET_CODE (body) == PARALLEL)
12330 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12331 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12337 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12338 as appropriate. I3 and I2 are the insns resulting from the combination
12339 insns including FROM (I2 may be zero).
12341 Each note in the list is either ignored or placed on some insns, depending
12342 on the type of note. */
12345 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
12347 rtx note, next_note;
12350 for (note = notes; note; note = next_note)
12352 rtx place = 0, place2 = 0;
12354 /* If this NOTE references a pseudo register, ensure it references
12355 the latest copy of that register. */
12356 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12357 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12358 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12360 next_note = XEXP (note, 1);
12361 switch (REG_NOTE_KIND (note))
12365 /* Doesn't matter much where we put this, as long as it's somewhere.
12366 It is preferable to keep these notes on branches, which is most
12367 likely to be i3. */
12371 case REG_VALUE_PROFILE:
12372 /* Just get rid of this note, as it is unused later anyway. */
12375 case REG_VTABLE_REF:
12376 /* ??? Should remain with *a particular* memory load. Given the
12377 nature of vtable data, the last insn seems relatively safe. */
12381 case REG_NON_LOCAL_GOTO:
12382 if (GET_CODE (i3) == JUMP_INSN)
12384 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12390 case REG_EH_REGION:
12391 /* These notes must remain with the call or trapping instruction. */
12392 if (GET_CODE (i3) == CALL_INSN)
12394 else if (i2 && GET_CODE (i2) == CALL_INSN)
12396 else if (flag_non_call_exceptions)
12398 if (may_trap_p (i3))
12400 else if (i2 && may_trap_p (i2))
12402 /* ??? Otherwise assume we've combined things such that we
12403 can now prove that the instructions can't trap. Drop the
12404 note in this case. */
12410 case REG_ALWAYS_RETURN:
12413 /* These notes must remain with the call. It should not be
12414 possible for both I2 and I3 to be a call. */
12415 if (GET_CODE (i3) == CALL_INSN)
12417 else if (i2 && GET_CODE (i2) == CALL_INSN)
12424 /* Any clobbers for i3 may still exist, and so we must process
12425 REG_UNUSED notes from that insn.
12427 Any clobbers from i2 or i1 can only exist if they were added by
12428 recog_for_combine. In that case, recog_for_combine created the
12429 necessary REG_UNUSED notes. Trying to keep any original
12430 REG_UNUSED notes from these insns can cause incorrect output
12431 if it is for the same register as the original i3 dest.
12432 In that case, we will notice that the register is set in i3,
12433 and then add a REG_UNUSED note for the destination of i3, which
12434 is wrong. However, it is possible to have REG_UNUSED notes from
12435 i2 or i1 for register which were both used and clobbered, so
12436 we keep notes from i2 or i1 if they will turn into REG_DEAD
12439 /* If this register is set or clobbered in I3, put the note there
12440 unless there is one already. */
12441 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12443 if (from_insn != i3)
12446 if (! (GET_CODE (XEXP (note, 0)) == REG
12447 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12448 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12451 /* Otherwise, if this register is used by I3, then this register
12452 now dies here, so we must put a REG_DEAD note here unless there
12454 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12455 && ! (GET_CODE (XEXP (note, 0)) == REG
12456 ? find_regno_note (i3, REG_DEAD,
12457 REGNO (XEXP (note, 0)))
12458 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12460 PUT_REG_NOTE_KIND (note, REG_DEAD);
12468 /* These notes say something about results of an insn. We can
12469 only support them if they used to be on I3 in which case they
12470 remain on I3. Otherwise they are ignored.
12472 If the note refers to an expression that is not a constant, we
12473 must also ignore the note since we cannot tell whether the
12474 equivalence is still true. It might be possible to do
12475 slightly better than this (we only have a problem if I2DEST
12476 or I1DEST is present in the expression), but it doesn't
12477 seem worth the trouble. */
12479 if (from_insn == i3
12480 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12485 case REG_NO_CONFLICT:
12486 /* These notes say something about how a register is used. They must
12487 be present on any use of the register in I2 or I3. */
12488 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12491 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12501 /* This can show up in several ways -- either directly in the
12502 pattern, or hidden off in the constant pool with (or without?)
12503 a REG_EQUAL note. */
12504 /* ??? Ignore the without-reg_equal-note problem for now. */
12505 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12506 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12507 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12508 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12512 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12513 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12514 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12515 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12523 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12524 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12525 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12527 if (JUMP_LABEL (place) != XEXP (note, 0))
12529 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12530 LABEL_NUSES (JUMP_LABEL (place))--;
12533 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12535 if (JUMP_LABEL (place2) != XEXP (note, 0))
12537 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12538 LABEL_NUSES (JUMP_LABEL (place2))--;
12544 /* This note says something about the value of a register prior
12545 to the execution of an insn. It is too much trouble to see
12546 if the note is still correct in all situations. It is better
12547 to simply delete it. */
12551 /* If the insn previously containing this note still exists,
12552 put it back where it was. Otherwise move it to the previous
12553 insn. Adjust the corresponding REG_LIBCALL note. */
12554 if (GET_CODE (from_insn) != NOTE)
12558 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12559 place = prev_real_insn (from_insn);
12561 XEXP (tem, 0) = place;
12562 /* If we're deleting the last remaining instruction of a
12563 libcall sequence, don't add the notes. */
12564 else if (XEXP (note, 0) == from_insn)
12570 /* This is handled similarly to REG_RETVAL. */
12571 if (GET_CODE (from_insn) != NOTE)
12575 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12576 place = next_real_insn (from_insn);
12578 XEXP (tem, 0) = place;
12579 /* If we're deleting the last remaining instruction of a
12580 libcall sequence, don't add the notes. */
12581 else if (XEXP (note, 0) == from_insn)
12587 /* If the register is used as an input in I3, it dies there.
12588 Similarly for I2, if it is nonzero and adjacent to I3.
12590 If the register is not used as an input in either I3 or I2
12591 and it is not one of the registers we were supposed to eliminate,
12592 there are two possibilities. We might have a non-adjacent I2
12593 or we might have somehow eliminated an additional register
12594 from a computation. For example, we might have had A & B where
12595 we discover that B will always be zero. In this case we will
12596 eliminate the reference to A.
12598 In both cases, we must search to see if we can find a previous
12599 use of A and put the death note there. */
12602 && GET_CODE (from_insn) == CALL_INSN
12603 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12605 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12607 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12608 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12613 basic_block bb = this_basic_block;
12615 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12617 if (! INSN_P (tem))
12619 if (tem == bb->head)
12624 /* If the register is being set at TEM, see if that is all
12625 TEM is doing. If so, delete TEM. Otherwise, make this
12626 into a REG_UNUSED note instead. */
12627 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12629 rtx set = single_set (tem);
12630 rtx inner_dest = 0;
12632 rtx cc0_setter = NULL_RTX;
12636 for (inner_dest = SET_DEST (set);
12637 (GET_CODE (inner_dest) == STRICT_LOW_PART
12638 || GET_CODE (inner_dest) == SUBREG
12639 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12640 inner_dest = XEXP (inner_dest, 0))
12643 /* Verify that it was the set, and not a clobber that
12644 modified the register.
12646 CC0 targets must be careful to maintain setter/user
12647 pairs. If we cannot delete the setter due to side
12648 effects, mark the user with an UNUSED note instead
12651 if (set != 0 && ! side_effects_p (SET_SRC (set))
12652 && rtx_equal_p (XEXP (note, 0), inner_dest)
12654 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12655 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12656 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12660 /* Move the notes and links of TEM elsewhere.
12661 This might delete other dead insns recursively.
12662 First set the pattern to something that won't use
12665 PATTERN (tem) = pc_rtx;
12667 distribute_notes (REG_NOTES (tem), tem, tem,
12669 distribute_links (LOG_LINKS (tem));
12671 PUT_CODE (tem, NOTE);
12672 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12673 NOTE_SOURCE_FILE (tem) = 0;
12676 /* Delete the setter too. */
12679 PATTERN (cc0_setter) = pc_rtx;
12681 distribute_notes (REG_NOTES (cc0_setter),
12682 cc0_setter, cc0_setter,
12684 distribute_links (LOG_LINKS (cc0_setter));
12686 PUT_CODE (cc0_setter, NOTE);
12687 NOTE_LINE_NUMBER (cc0_setter)
12688 = NOTE_INSN_DELETED;
12689 NOTE_SOURCE_FILE (cc0_setter) = 0;
12693 /* If the register is both set and used here, put the
12694 REG_DEAD note here, but place a REG_UNUSED note
12695 here too unless there already is one. */
12696 else if (reg_referenced_p (XEXP (note, 0),
12701 if (! find_regno_note (tem, REG_UNUSED,
12702 REGNO (XEXP (note, 0))))
12704 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12709 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12711 /* If there isn't already a REG_UNUSED note, put one
12713 if (! find_regno_note (tem, REG_UNUSED,
12714 REGNO (XEXP (note, 0))))
12719 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12720 || (GET_CODE (tem) == CALL_INSN
12721 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12725 /* If we are doing a 3->2 combination, and we have a
12726 register which formerly died in i3 and was not used
12727 by i2, which now no longer dies in i3 and is used in
12728 i2 but does not die in i2, and place is between i2
12729 and i3, then we may need to move a link from place to
12731 if (i2 && INSN_UID (place) <= max_uid_cuid
12732 && INSN_CUID (place) > INSN_CUID (i2)
12734 && INSN_CUID (from_insn) > INSN_CUID (i2)
12735 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12737 rtx links = LOG_LINKS (place);
12738 LOG_LINKS (place) = 0;
12739 distribute_links (links);
12744 if (tem == bb->head)
12748 /* We haven't found an insn for the death note and it
12749 is still a REG_DEAD note, but we have hit the beginning
12750 of the block. If the existing life info says the reg
12751 was dead, there's nothing left to do. Otherwise, we'll
12752 need to do a global life update after combine. */
12753 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12754 && REGNO_REG_SET_P (bb->global_live_at_start,
12755 REGNO (XEXP (note, 0))))
12756 SET_BIT (refresh_blocks, this_basic_block->index);
12759 /* If the register is set or already dead at PLACE, we needn't do
12760 anything with this note if it is still a REG_DEAD note.
12761 We can here if it is set at all, not if is it totally replace,
12762 which is what `dead_or_set_p' checks, so also check for it being
12765 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12767 unsigned int regno = REGNO (XEXP (note, 0));
12769 /* Similarly, if the instruction on which we want to place
12770 the note is a noop, we'll need do a global live update
12771 after we remove them in delete_noop_moves. */
12772 if (noop_move_p (place))
12773 SET_BIT (refresh_blocks, this_basic_block->index);
12775 if (dead_or_set_p (place, XEXP (note, 0))
12776 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12778 /* Unless the register previously died in PLACE, clear
12779 reg_last_death. [I no longer understand why this is
12781 if (reg_last_death[regno] != place)
12782 reg_last_death[regno] = 0;
12786 reg_last_death[regno] = place;
12788 /* If this is a death note for a hard reg that is occupying
12789 multiple registers, ensure that we are still using all
12790 parts of the object. If we find a piece of the object
12791 that is unused, we must arrange for an appropriate REG_DEAD
12792 note to be added for it. However, we can't just emit a USE
12793 and tag the note to it, since the register might actually
12794 be dead; so we recourse, and the recursive call then finds
12795 the previous insn that used this register. */
12797 if (place && regno < FIRST_PSEUDO_REGISTER
12798 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12800 unsigned int endregno
12801 = regno + HARD_REGNO_NREGS (regno,
12802 GET_MODE (XEXP (note, 0)));
12806 for (i = regno; i < endregno; i++)
12807 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12808 && ! find_regno_fusage (place, USE, i))
12809 || dead_or_set_regno_p (place, i))
12814 /* Put only REG_DEAD notes for pieces that are
12815 not already dead or set. */
12817 for (i = regno; i < endregno;
12818 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12820 rtx piece = regno_reg_rtx[i];
12821 basic_block bb = this_basic_block;
12823 if (! dead_or_set_p (place, piece)
12824 && ! reg_bitfield_target_p (piece,
12828 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12830 distribute_notes (new_note, place, place,
12833 else if (! refers_to_regno_p (i, i + 1,
12834 PATTERN (place), 0)
12835 && ! find_regno_fusage (place, USE, i))
12836 for (tem = PREV_INSN (place); ;
12837 tem = PREV_INSN (tem))
12839 if (! INSN_P (tem))
12841 if (tem == bb->head)
12843 SET_BIT (refresh_blocks,
12844 this_basic_block->index);
12849 if (dead_or_set_p (tem, piece)
12850 || reg_bitfield_target_p (piece,
12854 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12869 /* Any other notes should not be present at this point in the
12876 XEXP (note, 1) = REG_NOTES (place);
12877 REG_NOTES (place) = note;
12879 else if ((REG_NOTE_KIND (note) == REG_DEAD
12880 || REG_NOTE_KIND (note) == REG_UNUSED)
12881 && GET_CODE (XEXP (note, 0)) == REG)
12882 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12886 if ((REG_NOTE_KIND (note) == REG_DEAD
12887 || REG_NOTE_KIND (note) == REG_UNUSED)
12888 && GET_CODE (XEXP (note, 0)) == REG)
12889 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12891 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12892 REG_NOTE_KIND (note),
12894 REG_NOTES (place2));
12899 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12900 I3, I2, and I1 to new locations. This is also called in one case to
12901 add a link pointing at I3 when I3's destination is changed. */
12904 distribute_links (rtx links)
12906 rtx link, next_link;
12908 for (link = links; link; link = next_link)
12914 next_link = XEXP (link, 1);
12916 /* If the insn that this link points to is a NOTE or isn't a single
12917 set, ignore it. In the latter case, it isn't clear what we
12918 can do other than ignore the link, since we can't tell which
12919 register it was for. Such links wouldn't be used by combine
12922 It is not possible for the destination of the target of the link to
12923 have been changed by combine. The only potential of this is if we
12924 replace I3, I2, and I1 by I3 and I2. But in that case the
12925 destination of I2 also remains unchanged. */
12927 if (GET_CODE (XEXP (link, 0)) == NOTE
12928 || (set = single_set (XEXP (link, 0))) == 0)
12931 reg = SET_DEST (set);
12932 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12933 || GET_CODE (reg) == SIGN_EXTRACT
12934 || GET_CODE (reg) == STRICT_LOW_PART)
12935 reg = XEXP (reg, 0);
12937 /* A LOG_LINK is defined as being placed on the first insn that uses
12938 a register and points to the insn that sets the register. Start
12939 searching at the next insn after the target of the link and stop
12940 when we reach a set of the register or the end of the basic block.
12942 Note that this correctly handles the link that used to point from
12943 I3 to I2. Also note that not much searching is typically done here
12944 since most links don't point very far away. */
12946 for (insn = NEXT_INSN (XEXP (link, 0));
12947 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12948 || this_basic_block->next_bb->head != insn));
12949 insn = NEXT_INSN (insn))
12950 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12952 if (reg_referenced_p (reg, PATTERN (insn)))
12956 else if (GET_CODE (insn) == CALL_INSN
12957 && find_reg_fusage (insn, USE, reg))
12963 /* If we found a place to put the link, place it there unless there
12964 is already a link to the same insn as LINK at that point. */
12970 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12971 if (XEXP (link2, 0) == XEXP (link, 0))
12976 XEXP (link, 1) = LOG_LINKS (place);
12977 LOG_LINKS (place) = link;
12979 /* Set added_links_insn to the earliest insn we added a
12981 if (added_links_insn == 0
12982 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12983 added_links_insn = place;
12989 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12992 insn_cuid (rtx insn)
12994 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12995 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12996 insn = NEXT_INSN (insn);
12998 if (INSN_UID (insn) > max_uid_cuid)
13001 return INSN_CUID (insn);
13005 dump_combine_stats (FILE *file)
13009 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13010 combine_attempts, combine_merges, combine_extras, combine_successes);
13014 dump_combine_total_stats (FILE *file)
13018 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13019 total_attempts, total_merges, total_extras, total_successes);