1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
85 #include "hard-reg-set.h"
86 #include "basic-block.h"
87 #include "insn-config.h"
89 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid;
129 static int max_uid_cuid;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx *reg_last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx *reg_last_set;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn;
172 /* This is the lowest CUID that `subst' is currently dealing with.
173 get_last_value will not return a value if the register was set at or
174 after this CUID. If not for this mechanism, we could get confused if
175 I2 or I1 in try_combine were an insn that used the old value of a register
176 to obtain a new value. In that case, we might erroneously get the
177 new value of the register when we wanted the old one. */
179 static int subst_low_cuid;
181 /* This contains any hard registers that are used in newpat; reg_dead_at_p
182 must consider all these registers to be always live. */
184 static HARD_REG_SET newpat_used_regs;
186 /* This is an insn to which a LOG_LINKS entry has been added. If this
187 insn is the earlier than I2 or I3, combine should rescan starting at
190 static rtx added_links_insn;
192 /* Basic block in which we are performing combines. */
193 static basic_block this_basic_block;
195 /* A bitmap indicating which blocks had registers go dead at entry.
196 After combine, we'll need to re-do global life analysis with
197 those blocks as starting points. */
198 static sbitmap refresh_blocks;
200 /* The next group of arrays allows the recording of the last value assigned
201 to (hard or pseudo) register n. We use this information to see if a
202 operation being processed is redundant given a prior operation performed
203 on the register. For example, an `and' with a constant is redundant if
204 all the zero bits are already known to be turned off.
206 We use an approach similar to that used by cse, but change it in the
209 (1) We do not want to reinitialize at each label.
210 (2) It is useful, but not critical, to know the actual value assigned
211 to a register. Often just its form is helpful.
213 Therefore, we maintain the following arrays:
215 reg_last_set_value the last value assigned
216 reg_last_set_label records the value of label_tick when the
217 register was assigned
218 reg_last_set_table_tick records the value of label_tick when a
219 value using the register is assigned
220 reg_last_set_invalid set to nonzero when it is not valid
221 to use the value of this register in some
224 To understand the usage of these tables, it is important to understand
225 the distinction between the value in reg_last_set_value being valid
226 and the register being validly contained in some other expression in the
229 Entry I in reg_last_set_value is valid if it is nonzero, and either
230 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
232 Register I may validly appear in any expression returned for the value
233 of another register if reg_n_sets[i] is 1. It may also appear in the
234 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
235 reg_last_set_invalid[j] is zero.
237 If an expression is found in the table containing a register which may
238 not validly appear in an expression, the register is replaced by
239 something that won't match, (clobber (const_int 0)).
241 reg_last_set_invalid[i] is set nonzero when register I is being assigned
242 to and reg_last_set_table_tick[i] == label_tick. */
244 /* Record last value assigned to (hard or pseudo) register n. */
246 static rtx *reg_last_set_value;
248 /* Record the value of label_tick when the value for register n is placed in
249 reg_last_set_value[n]. */
251 static int *reg_last_set_label;
253 /* Record the value of label_tick when an expression involving register n
254 is placed in reg_last_set_value. */
256 static int *reg_last_set_table_tick;
258 /* Set nonzero if references to register n in expressions should not be
261 static char *reg_last_set_invalid;
263 /* Incremented for each label. */
265 static int label_tick;
267 /* Some registers that are set more than once and used in more than one
268 basic block are nevertheless always set in similar ways. For example,
269 a QImode register may be loaded from memory in two places on a machine
270 where byte loads zero extend.
272 We record in the following array what we know about the nonzero
273 bits of a register, specifically which bits are known to be zero.
275 If an entry is zero, it means that we don't know anything special. */
277 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
279 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
280 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
282 static enum machine_mode nonzero_bits_mode;
284 /* Nonzero if we know that a register has some leading bits that are always
285 equal to the sign bit. */
287 static unsigned char *reg_sign_bit_copies;
289 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
290 It is zero while computing them and after combine has completed. This
291 former test prevents propagating values based on previously set values,
292 which can be incorrect if a variable is modified in a loop. */
294 static int nonzero_sign_valid;
296 /* These arrays are maintained in parallel with reg_last_set_value
297 and are used to store the mode in which the register was last set,
298 the bits that were known to be zero when it was last set, and the
299 number of sign bits copies it was known to have when it was last set. */
301 static enum machine_mode *reg_last_set_mode;
302 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
303 static char *reg_last_set_sign_bit_copies;
305 /* Record one modification to rtl structure
306 to be undone by storing old_contents into *where.
307 is_int is 1 if the contents are an int. */
313 union {rtx r; int i;} old_contents;
314 union {rtx *r; int *i;} where;
317 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
318 num_undo says how many are currently recorded.
320 other_insn is nonzero if we have modified some other insn in the process
321 of working on subst_insn. It must be verified too. */
330 static struct undobuf undobuf;
332 /* Number of times the pseudo being substituted for
333 was found and replaced. */
335 static int n_occurrences;
337 static void do_SUBST PARAMS ((rtx *, rtx));
338 static void do_SUBST_INT PARAMS ((int *, int));
339 static void init_reg_last_arrays PARAMS ((void));
340 static void setup_incoming_promotions PARAMS ((void));
341 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
342 static int cant_combine_insn_p PARAMS ((rtx));
343 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
344 static int sets_function_arg_p PARAMS ((rtx));
345 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
346 static int contains_muldiv PARAMS ((rtx));
347 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
348 static void undo_all PARAMS ((void));
349 static void undo_commit PARAMS ((void));
350 static rtx *find_split_point PARAMS ((rtx *, rtx));
351 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
352 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
353 static rtx simplify_if_then_else PARAMS ((rtx));
354 static rtx simplify_set PARAMS ((rtx));
355 static rtx simplify_logical PARAMS ((rtx, int));
356 static rtx expand_compound_operation PARAMS ((rtx));
357 static rtx expand_field_assignment PARAMS ((rtx));
358 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
359 rtx, unsigned HOST_WIDE_INT, int,
361 static rtx extract_left_shift PARAMS ((rtx, int));
362 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
363 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
364 unsigned HOST_WIDE_INT *));
365 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
366 unsigned HOST_WIDE_INT, rtx, int));
367 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
368 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
369 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
370 static rtx make_field_assignment PARAMS ((rtx));
371 static rtx apply_distributive_law PARAMS ((rtx));
372 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
373 unsigned HOST_WIDE_INT));
374 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
375 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
376 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
377 enum rtx_code, HOST_WIDE_INT,
378 enum machine_mode, int *));
379 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
381 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
382 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
383 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
385 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
386 static void update_table_tick PARAMS ((rtx));
387 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
388 static void check_promoted_subreg PARAMS ((rtx, rtx));
389 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
390 static void record_dead_and_set_regs PARAMS ((rtx));
391 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
392 static rtx get_last_value PARAMS ((rtx));
393 static int use_crosses_set_p PARAMS ((rtx, int));
394 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
395 static int reg_dead_at_p PARAMS ((rtx, rtx));
396 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
397 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
398 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
399 static void distribute_links PARAMS ((rtx));
400 static void mark_used_regs_combine PARAMS ((rtx));
401 static int insn_cuid PARAMS ((rtx));
402 static void record_promoted_value PARAMS ((rtx, rtx));
403 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
404 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
406 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
407 insn. The substitution can be undone by undo_all. If INTO is already
408 set to NEWVAL, do not record this change. Because computing NEWVAL might
409 also call SUBST, we have to compute it before we put anything into
413 do_SUBST (into, newval)
419 if (oldval == newval)
422 /* We'd like to catch as many invalid transformations here as
423 possible. Unfortunately, there are way too many mode changes
424 that are perfectly valid, so we'd waste too much effort for
425 little gain doing the checks here. Focus on catching invalid
426 transformations involving integer constants. */
427 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
428 && GET_CODE (newval) == CONST_INT)
430 /* Sanity check that we're replacing oldval with a CONST_INT
431 that is a valid sign-extension for the original mode. */
432 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
436 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
437 CONST_INT is not valid, because after the replacement, the
438 original mode would be gone. Unfortunately, we can't tell
439 when do_SUBST is called to replace the operand thereof, so we
440 perform this test on oldval instead, checking whether an
441 invalid replacement took place before we got here. */
442 if ((GET_CODE (oldval) == SUBREG
443 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
444 || (GET_CODE (oldval) == ZERO_EXTEND
445 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
450 buf = undobuf.frees, undobuf.frees = buf->next;
452 buf = (struct undo *) xmalloc (sizeof (struct undo));
456 buf->old_contents.r = oldval;
459 buf->next = undobuf.undos, undobuf.undos = buf;
462 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
464 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
465 for the value of a HOST_WIDE_INT value (including CONST_INT) is
469 do_SUBST_INT (into, newval)
475 if (oldval == newval)
479 buf = undobuf.frees, undobuf.frees = buf->next;
481 buf = (struct undo *) xmalloc (sizeof (struct undo));
485 buf->old_contents.i = oldval;
488 buf->next = undobuf.undos, undobuf.undos = buf;
491 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
493 /* Main entry point for combiner. F is the first insn of the function.
494 NREGS is the first unused pseudo-reg number.
496 Return nonzero if the combiner has turned an indirect jump
497 instruction into a direct jump. */
499 combine_instructions (f, nregs)
508 rtx links, nextlinks;
510 int new_direct_jump_p = 0;
512 combine_attempts = 0;
515 combine_successes = 0;
517 combine_max_regno = nregs;
519 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
520 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
522 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
524 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
525 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
526 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
527 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
528 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
529 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
531 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
532 reg_last_set_nonzero_bits
533 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
534 reg_last_set_sign_bit_copies
535 = (char *) xmalloc (nregs * sizeof (char));
537 init_reg_last_arrays ();
539 init_recog_no_volatile ();
541 /* Compute maximum uid value so uid_cuid can be allocated. */
543 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
544 if (INSN_UID (insn) > i)
547 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
550 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
552 /* Don't use reg_nonzero_bits when computing it. This can cause problems
553 when, for example, we have j <<= 1 in a loop. */
555 nonzero_sign_valid = 0;
557 /* Compute the mapping from uids to cuids.
558 Cuids are numbers assigned to insns, like uids,
559 except that cuids increase monotonically through the code.
561 Scan all SETs and see if we can deduce anything about what
562 bits are known to be zero for some registers and how many copies
563 of the sign bit are known to exist for those registers.
565 Also set any known values so that we can use it while searching
566 for what bits are known to be set. */
570 setup_incoming_promotions ();
572 refresh_blocks = sbitmap_alloc (last_basic_block);
573 sbitmap_zero (refresh_blocks);
575 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
577 uid_cuid[INSN_UID (insn)] = ++i;
583 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
585 record_dead_and_set_regs (insn);
588 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
589 if (REG_NOTE_KIND (links) == REG_INC)
590 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
595 if (GET_CODE (insn) == CODE_LABEL)
599 nonzero_sign_valid = 1;
601 /* Now scan all the insns in forward order. */
606 init_reg_last_arrays ();
607 setup_incoming_promotions ();
609 FOR_EACH_BB (this_basic_block)
611 for (insn = this_basic_block->head;
612 insn != NEXT_INSN (this_basic_block->end);
613 insn = next ? next : NEXT_INSN (insn))
617 if (GET_CODE (insn) == CODE_LABEL)
620 else if (INSN_P (insn))
622 /* See if we know about function return values before this
623 insn based upon SUBREG flags. */
624 check_promoted_subreg (insn, PATTERN (insn));
626 /* Try this insn with each insn it links back to. */
628 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
629 if ((next = try_combine (insn, XEXP (links, 0),
630 NULL_RTX, &new_direct_jump_p)) != 0)
633 /* Try each sequence of three linked insns ending with this one. */
635 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
637 rtx link = XEXP (links, 0);
639 /* If the linked insn has been replaced by a note, then there
640 is no point in pursuing this chain any further. */
641 if (GET_CODE (link) == NOTE)
644 for (nextlinks = LOG_LINKS (link);
646 nextlinks = XEXP (nextlinks, 1))
647 if ((next = try_combine (insn, link,
649 &new_direct_jump_p)) != 0)
654 /* Try to combine a jump insn that uses CC0
655 with a preceding insn that sets CC0, and maybe with its
656 logical predecessor as well.
657 This is how we make decrement-and-branch insns.
658 We need this special code because data flow connections
659 via CC0 do not get entered in LOG_LINKS. */
661 if (GET_CODE (insn) == JUMP_INSN
662 && (prev = prev_nonnote_insn (insn)) != 0
663 && GET_CODE (prev) == INSN
664 && sets_cc0_p (PATTERN (prev)))
666 if ((next = try_combine (insn, prev,
667 NULL_RTX, &new_direct_jump_p)) != 0)
670 for (nextlinks = LOG_LINKS (prev); nextlinks;
671 nextlinks = XEXP (nextlinks, 1))
672 if ((next = try_combine (insn, prev,
674 &new_direct_jump_p)) != 0)
678 /* Do the same for an insn that explicitly references CC0. */
679 if (GET_CODE (insn) == INSN
680 && (prev = prev_nonnote_insn (insn)) != 0
681 && GET_CODE (prev) == INSN
682 && sets_cc0_p (PATTERN (prev))
683 && GET_CODE (PATTERN (insn)) == SET
684 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
686 if ((next = try_combine (insn, prev,
687 NULL_RTX, &new_direct_jump_p)) != 0)
690 for (nextlinks = LOG_LINKS (prev); nextlinks;
691 nextlinks = XEXP (nextlinks, 1))
692 if ((next = try_combine (insn, prev,
694 &new_direct_jump_p)) != 0)
698 /* Finally, see if any of the insns that this insn links to
699 explicitly references CC0. If so, try this insn, that insn,
700 and its predecessor if it sets CC0. */
701 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
702 if (GET_CODE (XEXP (links, 0)) == INSN
703 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
704 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
705 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
706 && GET_CODE (prev) == INSN
707 && sets_cc0_p (PATTERN (prev))
708 && (next = try_combine (insn, XEXP (links, 0),
709 prev, &new_direct_jump_p)) != 0)
713 /* Try combining an insn with two different insns whose results it
715 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
716 for (nextlinks = XEXP (links, 1); nextlinks;
717 nextlinks = XEXP (nextlinks, 1))
718 if ((next = try_combine (insn, XEXP (links, 0),
720 &new_direct_jump_p)) != 0)
723 if (GET_CODE (insn) != NOTE)
724 record_dead_and_set_regs (insn);
733 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
734 BASIC_BLOCK (i)->flags |= BB_DIRTY);
735 new_direct_jump_p |= purge_all_dead_edges (0);
736 delete_noop_moves (f);
738 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
739 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
740 | PROP_KILL_DEAD_CODE);
743 sbitmap_free (refresh_blocks);
744 free (reg_nonzero_bits);
745 free (reg_sign_bit_copies);
746 free (reg_last_death);
748 free (reg_last_set_value);
749 free (reg_last_set_table_tick);
750 free (reg_last_set_label);
751 free (reg_last_set_invalid);
752 free (reg_last_set_mode);
753 free (reg_last_set_nonzero_bits);
754 free (reg_last_set_sign_bit_copies);
758 struct undo *undo, *next;
759 for (undo = undobuf.frees; undo; undo = next)
767 total_attempts += combine_attempts;
768 total_merges += combine_merges;
769 total_extras += combine_extras;
770 total_successes += combine_successes;
772 nonzero_sign_valid = 0;
774 /* Make recognizer allow volatile MEMs again. */
777 return new_direct_jump_p;
780 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
783 init_reg_last_arrays ()
785 unsigned int nregs = combine_max_regno;
787 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
788 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
789 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
790 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
791 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
792 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
793 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
794 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
795 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
798 /* Set up any promoted values for incoming argument registers. */
801 setup_incoming_promotions ()
803 #ifdef PROMOTE_FUNCTION_ARGS
806 enum machine_mode mode;
808 rtx first = get_insns ();
810 #ifndef OUTGOING_REGNO
811 #define OUTGOING_REGNO(N) N
813 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
814 /* Check whether this register can hold an incoming pointer
815 argument. FUNCTION_ARG_REGNO_P tests outgoing register
816 numbers, so translate if necessary due to register windows. */
817 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
818 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
821 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
824 gen_rtx_CLOBBER (mode, const0_rtx)));
829 /* Called via note_stores. If X is a pseudo that is narrower than
830 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
832 If we are setting only a portion of X and we can't figure out what
833 portion, assume all bits will be used since we don't know what will
836 Similarly, set how many bits of X are known to be copies of the sign bit
837 at all locations in the function. This is the smallest number implied
841 set_nonzero_bits_and_sign_copies (x, set, data)
844 void *data ATTRIBUTE_UNUSED;
848 if (GET_CODE (x) == REG
849 && REGNO (x) >= FIRST_PSEUDO_REGISTER
850 /* If this register is undefined at the start of the file, we can't
851 say what its contents were. */
852 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
853 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
855 if (set == 0 || GET_CODE (set) == CLOBBER)
857 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
858 reg_sign_bit_copies[REGNO (x)] = 1;
862 /* If this is a complex assignment, see if we can convert it into a
863 simple assignment. */
864 set = expand_field_assignment (set);
866 /* If this is a simple assignment, or we have a paradoxical SUBREG,
867 set what we know about X. */
869 if (SET_DEST (set) == x
870 || (GET_CODE (SET_DEST (set)) == SUBREG
871 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
872 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
873 && SUBREG_REG (SET_DEST (set)) == x))
875 rtx src = SET_SRC (set);
877 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
878 /* If X is narrower than a word and SRC is a non-negative
879 constant that would appear negative in the mode of X,
880 sign-extend it for use in reg_nonzero_bits because some
881 machines (maybe most) will actually do the sign-extension
882 and this is the conservative approach.
884 ??? For 2.5, try to tighten up the MD files in this regard
885 instead of this kludge. */
887 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
888 && GET_CODE (src) == CONST_INT
890 && 0 != (INTVAL (src)
892 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
893 src = GEN_INT (INTVAL (src)
894 | ((HOST_WIDE_INT) (-1)
895 << GET_MODE_BITSIZE (GET_MODE (x))));
898 /* Don't call nonzero_bits if it cannot change anything. */
899 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
900 reg_nonzero_bits[REGNO (x)]
901 |= nonzero_bits (src, nonzero_bits_mode);
902 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
903 if (reg_sign_bit_copies[REGNO (x)] == 0
904 || reg_sign_bit_copies[REGNO (x)] > num)
905 reg_sign_bit_copies[REGNO (x)] = num;
909 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
910 reg_sign_bit_copies[REGNO (x)] = 1;
915 /* See if INSN can be combined into I3. PRED and SUCC are optionally
916 insns that were previously combined into I3 or that will be combined
917 into the merger of INSN and I3.
919 Return 0 if the combination is not allowed for any reason.
921 If the combination is allowed, *PDEST will be set to the single
922 destination of INSN and *PSRC to the single source, and this function
926 can_combine_p (insn, i3, pred, succ, pdest, psrc)
929 rtx pred ATTRIBUTE_UNUSED;
934 rtx set = 0, src, dest;
939 int all_adjacent = (succ ? (next_active_insn (insn) == succ
940 && next_active_insn (succ) == i3)
941 : next_active_insn (insn) == i3);
943 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
944 or a PARALLEL consisting of such a SET and CLOBBERs.
946 If INSN has CLOBBER parallel parts, ignore them for our processing.
947 By definition, these happen during the execution of the insn. When it
948 is merged with another insn, all bets are off. If they are, in fact,
949 needed and aren't also supplied in I3, they may be added by
950 recog_for_combine. Otherwise, it won't match.
952 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
955 Get the source and destination of INSN. If more than one, can't
958 if (GET_CODE (PATTERN (insn)) == SET)
959 set = PATTERN (insn);
960 else if (GET_CODE (PATTERN (insn)) == PARALLEL
961 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
963 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
965 rtx elt = XVECEXP (PATTERN (insn), 0, i);
967 switch (GET_CODE (elt))
969 /* This is important to combine floating point insns
972 /* Combining an isolated USE doesn't make sense.
973 We depend here on combinable_i3pat to reject them. */
974 /* The code below this loop only verifies that the inputs of
975 the SET in INSN do not change. We call reg_set_between_p
976 to verify that the REG in the USE does not change between
978 If the USE in INSN was for a pseudo register, the matching
979 insn pattern will likely match any register; combining this
980 with any other USE would only be safe if we knew that the
981 used registers have identical values, or if there was
982 something to tell them apart, e.g. different modes. For
983 now, we forgo such complicated tests and simply disallow
984 combining of USES of pseudo registers with any other USE. */
985 if (GET_CODE (XEXP (elt, 0)) == REG
986 && GET_CODE (PATTERN (i3)) == PARALLEL)
988 rtx i3pat = PATTERN (i3);
989 int i = XVECLEN (i3pat, 0) - 1;
990 unsigned int regno = REGNO (XEXP (elt, 0));
994 rtx i3elt = XVECEXP (i3pat, 0, i);
996 if (GET_CODE (i3elt) == USE
997 && GET_CODE (XEXP (i3elt, 0)) == REG
998 && (REGNO (XEXP (i3elt, 0)) == regno
999 ? reg_set_between_p (XEXP (elt, 0),
1000 PREV_INSN (insn), i3)
1001 : regno >= FIRST_PSEUDO_REGISTER))
1008 /* We can ignore CLOBBERs. */
1013 /* Ignore SETs whose result isn't used but not those that
1014 have side-effects. */
1015 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1016 && ! side_effects_p (elt))
1019 /* If we have already found a SET, this is a second one and
1020 so we cannot combine with this insn. */
1028 /* Anything else means we can't combine. */
1034 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1035 so don't do anything with it. */
1036 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1045 set = expand_field_assignment (set);
1046 src = SET_SRC (set), dest = SET_DEST (set);
1048 /* Don't eliminate a store in the stack pointer. */
1049 if (dest == stack_pointer_rtx
1050 /* If we couldn't eliminate a field assignment, we can't combine. */
1051 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1052 /* Don't combine with an insn that sets a register to itself if it has
1053 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1054 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1055 /* Can't merge an ASM_OPERANDS. */
1056 || GET_CODE (src) == ASM_OPERANDS
1057 /* Can't merge a function call. */
1058 || GET_CODE (src) == CALL
1059 /* Don't eliminate a function call argument. */
1060 || (GET_CODE (i3) == CALL_INSN
1061 && (find_reg_fusage (i3, USE, dest)
1062 || (GET_CODE (dest) == REG
1063 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1064 && global_regs[REGNO (dest)])))
1065 /* Don't substitute into an incremented register. */
1066 || FIND_REG_INC_NOTE (i3, dest)
1067 || (succ && FIND_REG_INC_NOTE (succ, dest))
1069 /* Don't combine the end of a libcall into anything. */
1070 /* ??? This gives worse code, and appears to be unnecessary, since no
1071 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1072 use REG_RETVAL notes for noconflict blocks, but other code here
1073 makes sure that those insns don't disappear. */
1074 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1076 /* Make sure that DEST is not used after SUCC but before I3. */
1077 || (succ && ! all_adjacent
1078 && reg_used_between_p (dest, succ, i3))
1079 /* Make sure that the value that is to be substituted for the register
1080 does not use any registers whose values alter in between. However,
1081 If the insns are adjacent, a use can't cross a set even though we
1082 think it might (this can happen for a sequence of insns each setting
1083 the same destination; reg_last_set of that register might point to
1084 a NOTE). If INSN has a REG_EQUIV note, the register is always
1085 equivalent to the memory so the substitution is valid even if there
1086 are intervening stores. Also, don't move a volatile asm or
1087 UNSPEC_VOLATILE across any other insns. */
1089 && (((GET_CODE (src) != MEM
1090 || ! find_reg_note (insn, REG_EQUIV, src))
1091 && use_crosses_set_p (src, INSN_CUID (insn)))
1092 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1093 || GET_CODE (src) == UNSPEC_VOLATILE))
1094 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1095 better register allocation by not doing the combine. */
1096 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1097 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1098 /* Don't combine across a CALL_INSN, because that would possibly
1099 change whether the life span of some REGs crosses calls or not,
1100 and it is a pain to update that information.
1101 Exception: if source is a constant, moving it later can't hurt.
1102 Accept that special case, because it helps -fforce-addr a lot. */
1103 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1106 /* DEST must either be a REG or CC0. */
1107 if (GET_CODE (dest) == REG)
1109 /* If register alignment is being enforced for multi-word items in all
1110 cases except for parameters, it is possible to have a register copy
1111 insn referencing a hard register that is not allowed to contain the
1112 mode being copied and which would not be valid as an operand of most
1113 insns. Eliminate this problem by not combining with such an insn.
1115 Also, on some machines we don't want to extend the life of a hard
1118 if (GET_CODE (src) == REG
1119 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1120 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1121 /* Don't extend the life of a hard register unless it is
1122 user variable (if we have few registers) or it can't
1123 fit into the desired register (meaning something special
1125 Also avoid substituting a return register into I3, because
1126 reload can't handle a conflict with constraints of other
1128 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1132 else if (GET_CODE (dest) != CC0)
1135 /* Don't substitute for a register intended as a clobberable operand.
1136 Similarly, don't substitute an expression containing a register that
1137 will be clobbered in I3. */
1138 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1139 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1140 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1141 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1143 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1146 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1147 or not), reject, unless nothing volatile comes between it and I3 */
1149 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1151 /* Make sure succ doesn't contain a volatile reference. */
1152 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1155 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1156 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1160 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1161 to be an explicit register variable, and was chosen for a reason. */
1163 if (GET_CODE (src) == ASM_OPERANDS
1164 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1167 /* If there are any volatile insns between INSN and I3, reject, because
1168 they might affect machine state. */
1170 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1171 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1174 /* If INSN or I2 contains an autoincrement or autodecrement,
1175 make sure that register is not used between there and I3,
1176 and not already used in I3 either.
1177 Also insist that I3 not be a jump; if it were one
1178 and the incremented register were spilled, we would lose. */
1181 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1182 if (REG_NOTE_KIND (link) == REG_INC
1183 && (GET_CODE (i3) == JUMP_INSN
1184 || reg_used_between_p (XEXP (link, 0), insn, i3)
1185 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1190 /* Don't combine an insn that follows a CC0-setting insn.
1191 An insn that uses CC0 must not be separated from the one that sets it.
1192 We do, however, allow I2 to follow a CC0-setting insn if that insn
1193 is passed as I1; in that case it will be deleted also.
1194 We also allow combining in this case if all the insns are adjacent
1195 because that would leave the two CC0 insns adjacent as well.
1196 It would be more logical to test whether CC0 occurs inside I1 or I2,
1197 but that would be much slower, and this ought to be equivalent. */
1199 p = prev_nonnote_insn (insn);
1200 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1205 /* If we get here, we have passed all the tests and the combination is
1214 /* Check if PAT is an insn - or a part of it - used to set up an
1215 argument for a function in a hard register. */
1218 sets_function_arg_p (pat)
1224 switch (GET_CODE (pat))
1227 return sets_function_arg_p (PATTERN (pat));
1230 for (i = XVECLEN (pat, 0); --i >= 0;)
1231 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1237 inner_dest = SET_DEST (pat);
1238 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1239 || GET_CODE (inner_dest) == SUBREG
1240 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1241 inner_dest = XEXP (inner_dest, 0);
1243 return (GET_CODE (inner_dest) == REG
1244 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1245 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1254 /* LOC is the location within I3 that contains its pattern or the component
1255 of a PARALLEL of the pattern. We validate that it is valid for combining.
1257 One problem is if I3 modifies its output, as opposed to replacing it
1258 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1259 so would produce an insn that is not equivalent to the original insns.
1263 (set (reg:DI 101) (reg:DI 100))
1264 (set (subreg:SI (reg:DI 101) 0) <foo>)
1266 This is NOT equivalent to:
1268 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1269 (set (reg:DI 101) (reg:DI 100))])
1271 Not only does this modify 100 (in which case it might still be valid
1272 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1274 We can also run into a problem if I2 sets a register that I1
1275 uses and I1 gets directly substituted into I3 (not via I2). In that
1276 case, we would be getting the wrong value of I2DEST into I3, so we
1277 must reject the combination. This case occurs when I2 and I1 both
1278 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1279 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1280 of a SET must prevent combination from occurring.
1282 Before doing the above check, we first try to expand a field assignment
1283 into a set of logical operations.
1285 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1286 we place a register that is both set and used within I3. If more than one
1287 such register is detected, we fail.
1289 Return 1 if the combination is valid, zero otherwise. */
1292 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1298 rtx *pi3dest_killed;
1302 if (GET_CODE (x) == SET)
1304 rtx set = expand_field_assignment (x);
1305 rtx dest = SET_DEST (set);
1306 rtx src = SET_SRC (set);
1307 rtx inner_dest = dest;
1310 rtx inner_src = src;
1315 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1316 || GET_CODE (inner_dest) == SUBREG
1317 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1318 inner_dest = XEXP (inner_dest, 0);
1320 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1323 while (GET_CODE (inner_src) == STRICT_LOW_PART
1324 || GET_CODE (inner_src) == SUBREG
1325 || GET_CODE (inner_src) == ZERO_EXTRACT)
1326 inner_src = XEXP (inner_src, 0);
1328 /* If it is better that two different modes keep two different pseudos,
1329 avoid combining them. This avoids producing the following pattern
1331 (set (subreg:SI (reg/v:QI 21) 0)
1332 (lshiftrt:SI (reg/v:SI 20)
1334 If that were made, reload could not handle the pair of
1335 reg 20/21, since it would try to get any GENERAL_REGS
1336 but some of them don't handle QImode. */
1338 if (rtx_equal_p (inner_src, i2dest)
1339 && GET_CODE (inner_dest) == REG
1340 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1344 /* Check for the case where I3 modifies its output, as
1346 if ((inner_dest != dest
1347 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1348 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1350 /* This is the same test done in can_combine_p except we can't test
1351 all_adjacent; we don't have to, since this instruction will stay
1352 in place, thus we are not considering increasing the lifetime of
1355 Also, if this insn sets a function argument, combining it with
1356 something that might need a spill could clobber a previous
1357 function argument; the all_adjacent test in can_combine_p also
1358 checks this; here, we do a more specific test for this case. */
1360 || (GET_CODE (inner_dest) == REG
1361 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1362 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1363 GET_MODE (inner_dest))))
1364 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1367 /* If DEST is used in I3, it is being killed in this insn,
1368 so record that for later.
1369 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1370 STACK_POINTER_REGNUM, since these are always considered to be
1371 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1372 if (pi3dest_killed && GET_CODE (dest) == REG
1373 && reg_referenced_p (dest, PATTERN (i3))
1374 && REGNO (dest) != FRAME_POINTER_REGNUM
1375 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1376 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1378 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1379 && (REGNO (dest) != ARG_POINTER_REGNUM
1380 || ! fixed_regs [REGNO (dest)])
1382 && REGNO (dest) != STACK_POINTER_REGNUM)
1384 if (*pi3dest_killed)
1387 *pi3dest_killed = dest;
1391 else if (GET_CODE (x) == PARALLEL)
1395 for (i = 0; i < XVECLEN (x, 0); i++)
1396 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1397 i1_not_in_src, pi3dest_killed))
1404 /* Return 1 if X is an arithmetic expression that contains a multiplication
1405 and division. We don't count multiplications by powers of two here. */
1411 switch (GET_CODE (x))
1413 case MOD: case DIV: case UMOD: case UDIV:
1417 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1418 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1420 switch (GET_RTX_CLASS (GET_CODE (x)))
1422 case 'c': case '<': case '2':
1423 return contains_muldiv (XEXP (x, 0))
1424 || contains_muldiv (XEXP (x, 1));
1427 return contains_muldiv (XEXP (x, 0));
1435 /* Determine whether INSN can be used in a combination. Return nonzero if
1436 not. This is used in try_combine to detect early some cases where we
1437 can't perform combinations. */
1440 cant_combine_insn_p (insn)
1446 /* If this isn't really an insn, we can't do anything.
1447 This can occur when flow deletes an insn that it has merged into an
1448 auto-increment address. */
1449 if (! INSN_P (insn))
1452 /* Never combine loads and stores involving hard regs. The register
1453 allocator can usually handle such reg-reg moves by tying. If we allow
1454 the combiner to make substitutions of hard regs, we risk aborting in
1455 reload on machines that have SMALL_REGISTER_CLASSES.
1456 As an exception, we allow combinations involving fixed regs; these are
1457 not available to the register allocator so there's no risk involved. */
1459 set = single_set (insn);
1462 src = SET_SRC (set);
1463 dest = SET_DEST (set);
1464 if (GET_CODE (src) == SUBREG)
1465 src = SUBREG_REG (src);
1466 if (GET_CODE (dest) == SUBREG)
1467 dest = SUBREG_REG (dest);
1468 if (REG_P (src) && REG_P (dest)
1469 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1470 && ! fixed_regs[REGNO (src)])
1471 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1472 && ! fixed_regs[REGNO (dest)])))
1478 /* Try to combine the insns I1 and I2 into I3.
1479 Here I1 and I2 appear earlier than I3.
1480 I1 can be zero; then we combine just I2 into I3.
1482 If we are combining three insns and the resulting insn is not recognized,
1483 try splitting it into two insns. If that happens, I2 and I3 are retained
1484 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1487 Return 0 if the combination does not work. Then nothing is changed.
1488 If we did the combination, return the insn at which combine should
1491 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1492 new direct jump instruction. */
1495 try_combine (i3, i2, i1, new_direct_jump_p)
1497 int *new_direct_jump_p;
1499 /* New patterns for I3 and I2, respectively. */
1500 rtx newpat, newi2pat = 0;
1501 int substed_i2 = 0, substed_i1 = 0;
1502 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1503 int added_sets_1, added_sets_2;
1504 /* Total number of SETs to put into I3. */
1506 /* Nonzero is I2's body now appears in I3. */
1508 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1509 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1510 /* Contains I3 if the destination of I3 is used in its source, which means
1511 that the old life of I3 is being killed. If that usage is placed into
1512 I2 and not in I3, a REG_DEAD note must be made. */
1513 rtx i3dest_killed = 0;
1514 /* SET_DEST and SET_SRC of I2 and I1. */
1515 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1516 /* PATTERN (I2), or a copy of it in certain cases. */
1518 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1519 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1520 int i1_feeds_i3 = 0;
1521 /* Notes that must be added to REG_NOTES in I3 and I2. */
1522 rtx new_i3_notes, new_i2_notes;
1523 /* Notes that we substituted I3 into I2 instead of the normal case. */
1524 int i3_subst_into_i2 = 0;
1525 /* Notes that I1, I2 or I3 is a MULT operation. */
1533 /* Exit early if one of the insns involved can't be used for
1535 if (cant_combine_insn_p (i3)
1536 || cant_combine_insn_p (i2)
1537 || (i1 && cant_combine_insn_p (i1))
1538 /* We also can't do anything if I3 has a
1539 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1542 /* ??? This gives worse code, and appears to be unnecessary, since no
1543 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1544 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1550 undobuf.other_insn = 0;
1552 /* Reset the hard register usage information. */
1553 CLEAR_HARD_REG_SET (newpat_used_regs);
1555 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1556 code below, set I1 to be the earlier of the two insns. */
1557 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1558 temp = i1, i1 = i2, i2 = temp;
1560 added_links_insn = 0;
1562 /* First check for one important special-case that the code below will
1563 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1564 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1565 we may be able to replace that destination with the destination of I3.
1566 This occurs in the common code where we compute both a quotient and
1567 remainder into a structure, in which case we want to do the computation
1568 directly into the structure to avoid register-register copies.
1570 Note that this case handles both multiple sets in I2 and also
1571 cases where I2 has a number of CLOBBER or PARALLELs.
1573 We make very conservative checks below and only try to handle the
1574 most common cases of this. For example, we only handle the case
1575 where I2 and I3 are adjacent to avoid making difficult register
1578 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1579 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1580 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1581 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1582 && GET_CODE (PATTERN (i2)) == PARALLEL
1583 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1584 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1585 below would need to check what is inside (and reg_overlap_mentioned_p
1586 doesn't support those codes anyway). Don't allow those destinations;
1587 the resulting insn isn't likely to be recognized anyway. */
1588 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1589 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1590 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1591 SET_DEST (PATTERN (i3)))
1592 && next_real_insn (i2) == i3)
1594 rtx p2 = PATTERN (i2);
1596 /* Make sure that the destination of I3,
1597 which we are going to substitute into one output of I2,
1598 is not used within another output of I2. We must avoid making this:
1599 (parallel [(set (mem (reg 69)) ...)
1600 (set (reg 69) ...)])
1601 which is not well-defined as to order of actions.
1602 (Besides, reload can't handle output reloads for this.)
1604 The problem can also happen if the dest of I3 is a memory ref,
1605 if another dest in I2 is an indirect memory ref. */
1606 for (i = 0; i < XVECLEN (p2, 0); i++)
1607 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1608 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1609 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1610 SET_DEST (XVECEXP (p2, 0, i))))
1613 if (i == XVECLEN (p2, 0))
1614 for (i = 0; i < XVECLEN (p2, 0); i++)
1615 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1616 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1617 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1622 subst_low_cuid = INSN_CUID (i2);
1624 added_sets_2 = added_sets_1 = 0;
1625 i2dest = SET_SRC (PATTERN (i3));
1627 /* Replace the dest in I2 with our dest and make the resulting
1628 insn the new pattern for I3. Then skip to where we
1629 validate the pattern. Everything was set up above. */
1630 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1631 SET_DEST (PATTERN (i3)));
1634 i3_subst_into_i2 = 1;
1635 goto validate_replacement;
1639 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1640 one of those words to another constant, merge them by making a new
1643 && (temp = single_set (i2)) != 0
1644 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1645 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1646 && GET_CODE (SET_DEST (temp)) == REG
1647 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1648 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1649 && GET_CODE (PATTERN (i3)) == SET
1650 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1651 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1652 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1653 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1654 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1656 HOST_WIDE_INT lo, hi;
1658 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1659 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1662 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1663 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1666 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1668 /* We don't handle the case of the target word being wider
1669 than a host wide int. */
1670 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1673 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1674 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1675 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1677 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1678 hi = INTVAL (SET_SRC (PATTERN (i3)));
1679 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1681 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1682 >> (HOST_BITS_PER_WIDE_INT - 1));
1684 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1685 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1687 (INTVAL (SET_SRC (PATTERN (i3)))));
1689 hi = lo < 0 ? -1 : 0;
1692 /* We don't handle the case of the higher word not fitting
1693 entirely in either hi or lo. */
1698 subst_low_cuid = INSN_CUID (i2);
1699 added_sets_2 = added_sets_1 = 0;
1700 i2dest = SET_DEST (temp);
1702 SUBST (SET_SRC (temp),
1703 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1705 newpat = PATTERN (i2);
1706 goto validate_replacement;
1710 /* If we have no I1 and I2 looks like:
1711 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1713 make up a dummy I1 that is
1716 (set (reg:CC X) (compare:CC Y (const_int 0)))
1718 (We can ignore any trailing CLOBBERs.)
1720 This undoes a previous combination and allows us to match a branch-and-
1723 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1724 && XVECLEN (PATTERN (i2), 0) >= 2
1725 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1726 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1728 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1729 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1730 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1731 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1732 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1733 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1735 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1736 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1741 /* We make I1 with the same INSN_UID as I2. This gives it
1742 the same INSN_CUID for value tracking. Our fake I1 will
1743 never appear in the insn stream so giving it the same INSN_UID
1744 as I2 will not cause a problem. */
1746 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1747 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1748 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1751 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1752 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1753 SET_DEST (PATTERN (i1)));
1758 /* Verify that I2 and I1 are valid for combining. */
1759 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1760 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1766 /* Record whether I2DEST is used in I2SRC and similarly for the other
1767 cases. Knowing this will help in register status updating below. */
1768 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1769 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1770 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1772 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1774 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1776 /* Ensure that I3's pattern can be the destination of combines. */
1777 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1778 i1 && i2dest_in_i1src && i1_feeds_i3,
1785 /* See if any of the insns is a MULT operation. Unless one is, we will
1786 reject a combination that is, since it must be slower. Be conservative
1788 if (GET_CODE (i2src) == MULT
1789 || (i1 != 0 && GET_CODE (i1src) == MULT)
1790 || (GET_CODE (PATTERN (i3)) == SET
1791 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1794 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1795 We used to do this EXCEPT in one case: I3 has a post-inc in an
1796 output operand. However, that exception can give rise to insns like
1798 which is a famous insn on the PDP-11 where the value of r3 used as the
1799 source was model-dependent. Avoid this sort of thing. */
1802 if (!(GET_CODE (PATTERN (i3)) == SET
1803 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1804 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1805 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1806 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1807 /* It's not the exception. */
1810 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1811 if (REG_NOTE_KIND (link) == REG_INC
1812 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1814 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1821 /* See if the SETs in I1 or I2 need to be kept around in the merged
1822 instruction: whenever the value set there is still needed past I3.
1823 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1825 For the SET in I1, we have two cases: If I1 and I2 independently
1826 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1827 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1828 in I1 needs to be kept around unless I1DEST dies or is set in either
1829 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1830 I1DEST. If so, we know I1 feeds into I2. */
1832 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1835 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1836 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1838 /* If the set in I2 needs to be kept around, we must make a copy of
1839 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1840 PATTERN (I2), we are only substituting for the original I1DEST, not into
1841 an already-substituted copy. This also prevents making self-referential
1842 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1845 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1846 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1850 i2pat = copy_rtx (i2pat);
1854 /* Substitute in the latest insn for the regs set by the earlier ones. */
1856 maxreg = max_reg_num ();
1860 /* It is possible that the source of I2 or I1 may be performing an
1861 unneeded operation, such as a ZERO_EXTEND of something that is known
1862 to have the high part zero. Handle that case by letting subst look at
1863 the innermost one of them.
1865 Another way to do this would be to have a function that tries to
1866 simplify a single insn instead of merging two or more insns. We don't
1867 do this because of the potential of infinite loops and because
1868 of the potential extra memory required. However, doing it the way
1869 we are is a bit of a kludge and doesn't catch all cases.
1871 But only do this if -fexpensive-optimizations since it slows things down
1872 and doesn't usually win. */
1874 if (flag_expensive_optimizations)
1876 /* Pass pc_rtx so no substitutions are done, just simplifications.
1877 The cases that we are interested in here do not involve the few
1878 cases were is_replaced is checked. */
1881 subst_low_cuid = INSN_CUID (i1);
1882 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1886 subst_low_cuid = INSN_CUID (i2);
1887 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1892 /* Many machines that don't use CC0 have insns that can both perform an
1893 arithmetic operation and set the condition code. These operations will
1894 be represented as a PARALLEL with the first element of the vector
1895 being a COMPARE of an arithmetic operation with the constant zero.
1896 The second element of the vector will set some pseudo to the result
1897 of the same arithmetic operation. If we simplify the COMPARE, we won't
1898 match such a pattern and so will generate an extra insn. Here we test
1899 for this case, where both the comparison and the operation result are
1900 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1901 I2SRC. Later we will make the PARALLEL that contains I2. */
1903 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1904 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1905 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1906 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1908 #ifdef EXTRA_CC_MODES
1910 enum machine_mode compare_mode;
1913 newpat = PATTERN (i3);
1914 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1918 #ifdef EXTRA_CC_MODES
1919 /* See if a COMPARE with the operand we substituted in should be done
1920 with the mode that is currently being used. If not, do the same
1921 processing we do in `subst' for a SET; namely, if the destination
1922 is used only once, try to replace it with a register of the proper
1923 mode and also replace the COMPARE. */
1924 if (undobuf.other_insn == 0
1925 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1926 &undobuf.other_insn))
1927 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1929 != GET_MODE (SET_DEST (newpat))))
1931 unsigned int regno = REGNO (SET_DEST (newpat));
1932 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1934 if (regno < FIRST_PSEUDO_REGISTER
1935 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1936 && ! REG_USERVAR_P (SET_DEST (newpat))))
1938 if (regno >= FIRST_PSEUDO_REGISTER)
1939 SUBST (regno_reg_rtx[regno], new_dest);
1941 SUBST (SET_DEST (newpat), new_dest);
1942 SUBST (XEXP (*cc_use, 0), new_dest);
1943 SUBST (SET_SRC (newpat),
1944 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1947 undobuf.other_insn = 0;
1954 n_occurrences = 0; /* `subst' counts here */
1956 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1957 need to make a unique copy of I2SRC each time we substitute it
1958 to avoid self-referential rtl. */
1960 subst_low_cuid = INSN_CUID (i2);
1961 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1962 ! i1_feeds_i3 && i1dest_in_i1src);
1965 /* Record whether i2's body now appears within i3's body. */
1966 i2_is_used = n_occurrences;
1969 /* If we already got a failure, don't try to do more. Otherwise,
1970 try to substitute in I1 if we have it. */
1972 if (i1 && GET_CODE (newpat) != CLOBBER)
1974 /* Before we can do this substitution, we must redo the test done
1975 above (see detailed comments there) that ensures that I1DEST
1976 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1978 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1986 subst_low_cuid = INSN_CUID (i1);
1987 newpat = subst (newpat, i1dest, i1src, 0, 0);
1991 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1992 to count all the ways that I2SRC and I1SRC can be used. */
1993 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1994 && i2_is_used + added_sets_2 > 1)
1995 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1996 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1998 /* Fail if we tried to make a new register (we used to abort, but there's
1999 really no reason to). */
2000 || max_reg_num () != maxreg
2001 /* Fail if we couldn't do something and have a CLOBBER. */
2002 || GET_CODE (newpat) == CLOBBER
2003 /* Fail if this new pattern is a MULT and we didn't have one before
2004 at the outer level. */
2005 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2012 /* If the actions of the earlier insns must be kept
2013 in addition to substituting them into the latest one,
2014 we must make a new PARALLEL for the latest insn
2015 to hold additional the SETs. */
2017 if (added_sets_1 || added_sets_2)
2021 if (GET_CODE (newpat) == PARALLEL)
2023 rtvec old = XVEC (newpat, 0);
2024 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2025 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2026 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2027 sizeof (old->elem[0]) * old->num_elem);
2032 total_sets = 1 + added_sets_1 + added_sets_2;
2033 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2034 XVECEXP (newpat, 0, 0) = old;
2038 XVECEXP (newpat, 0, --total_sets)
2039 = (GET_CODE (PATTERN (i1)) == PARALLEL
2040 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2044 /* If there is no I1, use I2's body as is. We used to also not do
2045 the subst call below if I2 was substituted into I3,
2046 but that could lose a simplification. */
2048 XVECEXP (newpat, 0, --total_sets) = i2pat;
2050 /* See comment where i2pat is assigned. */
2051 XVECEXP (newpat, 0, --total_sets)
2052 = subst (i2pat, i1dest, i1src, 0, 0);
2056 /* We come here when we are replacing a destination in I2 with the
2057 destination of I3. */
2058 validate_replacement:
2060 /* Note which hard regs this insn has as inputs. */
2061 mark_used_regs_combine (newpat);
2063 /* Is the result of combination a valid instruction? */
2064 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2066 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2067 the second SET's destination is a register that is unused. In that case,
2068 we just need the first SET. This can occur when simplifying a divmod
2069 insn. We *must* test for this case here because the code below that
2070 splits two independent SETs doesn't handle this case correctly when it
2071 updates the register status. Also check the case where the first
2072 SET's destination is unused. That would not cause incorrect code, but
2073 does cause an unneeded insn to remain. */
2075 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2076 && XVECLEN (newpat, 0) == 2
2077 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2078 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2079 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2080 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2081 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2082 && asm_noperands (newpat) < 0)
2084 newpat = XVECEXP (newpat, 0, 0);
2085 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2088 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2089 && XVECLEN (newpat, 0) == 2
2090 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2091 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2092 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2093 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2094 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2095 && asm_noperands (newpat) < 0)
2097 newpat = XVECEXP (newpat, 0, 1);
2098 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2101 /* If we were combining three insns and the result is a simple SET
2102 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2103 insns. There are two ways to do this. It can be split using a
2104 machine-specific method (like when you have an addition of a large
2105 constant) or by combine in the function find_split_point. */
2107 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2108 && asm_noperands (newpat) < 0)
2110 rtx m_split, *split;
2111 rtx ni2dest = i2dest;
2113 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2114 use I2DEST as a scratch register will help. In the latter case,
2115 convert I2DEST to the mode of the source of NEWPAT if we can. */
2117 m_split = split_insns (newpat, i3);
2119 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2120 inputs of NEWPAT. */
2122 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2123 possible to try that as a scratch reg. This would require adding
2124 more code to make it work though. */
2126 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2128 /* If I2DEST is a hard register or the only use of a pseudo,
2129 we can change its mode. */
2130 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2131 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2132 && GET_CODE (i2dest) == REG
2133 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2134 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2135 && ! REG_USERVAR_P (i2dest))))
2136 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2139 m_split = split_insns (gen_rtx_PARALLEL
2141 gen_rtvec (2, newpat,
2142 gen_rtx_CLOBBER (VOIDmode,
2145 /* If the split with the mode-changed register didn't work, try
2146 the original register. */
2147 if (! m_split && ni2dest != i2dest)
2150 m_split = split_insns (gen_rtx_PARALLEL
2152 gen_rtvec (2, newpat,
2153 gen_rtx_CLOBBER (VOIDmode,
2159 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2161 m_split = PATTERN (m_split);
2162 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2163 if (insn_code_number >= 0)
2166 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2167 && (next_real_insn (i2) == i3
2168 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2171 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2172 newi2pat = PATTERN (m_split);
2174 i3set = single_set (NEXT_INSN (m_split));
2175 i2set = single_set (m_split);
2177 /* In case we changed the mode of I2DEST, replace it in the
2178 pseudo-register table here. We can't do it above in case this
2179 code doesn't get executed and we do a split the other way. */
2181 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2182 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2184 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2186 /* If I2 or I3 has multiple SETs, we won't know how to track
2187 register status, so don't use these insns. If I2's destination
2188 is used between I2 and I3, we also can't use these insns. */
2190 if (i2_code_number >= 0 && i2set && i3set
2191 && (next_real_insn (i2) == i3
2192 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2193 insn_code_number = recog_for_combine (&newi3pat, i3,
2195 if (insn_code_number >= 0)
2198 /* It is possible that both insns now set the destination of I3.
2199 If so, we must show an extra use of it. */
2201 if (insn_code_number >= 0)
2203 rtx new_i3_dest = SET_DEST (i3set);
2204 rtx new_i2_dest = SET_DEST (i2set);
2206 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2207 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2208 || GET_CODE (new_i3_dest) == SUBREG)
2209 new_i3_dest = XEXP (new_i3_dest, 0);
2211 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2212 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2213 || GET_CODE (new_i2_dest) == SUBREG)
2214 new_i2_dest = XEXP (new_i2_dest, 0);
2216 if (GET_CODE (new_i3_dest) == REG
2217 && GET_CODE (new_i2_dest) == REG
2218 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2219 REG_N_SETS (REGNO (new_i2_dest))++;
2223 /* If we can split it and use I2DEST, go ahead and see if that
2224 helps things be recognized. Verify that none of the registers
2225 are set between I2 and I3. */
2226 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2228 && GET_CODE (i2dest) == REG
2230 /* We need I2DEST in the proper mode. If it is a hard register
2231 or the only use of a pseudo, we can change its mode. */
2232 && (GET_MODE (*split) == GET_MODE (i2dest)
2233 || GET_MODE (*split) == VOIDmode
2234 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2235 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2236 && ! REG_USERVAR_P (i2dest)))
2237 && (next_real_insn (i2) == i3
2238 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2239 /* We can't overwrite I2DEST if its value is still used by
2241 && ! reg_referenced_p (i2dest, newpat))
2243 rtx newdest = i2dest;
2244 enum rtx_code split_code = GET_CODE (*split);
2245 enum machine_mode split_mode = GET_MODE (*split);
2247 /* Get NEWDEST as a register in the proper mode. We have already
2248 validated that we can do this. */
2249 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2251 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2253 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2254 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2257 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2258 an ASHIFT. This can occur if it was inside a PLUS and hence
2259 appeared to be a memory address. This is a kludge. */
2260 if (split_code == MULT
2261 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2262 && INTVAL (XEXP (*split, 1)) > 0
2263 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2265 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2266 XEXP (*split, 0), GEN_INT (i)));
2267 /* Update split_code because we may not have a multiply
2269 split_code = GET_CODE (*split);
2272 #ifdef INSN_SCHEDULING
2273 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2274 be written as a ZERO_EXTEND. */
2275 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2277 #ifdef LOAD_EXTEND_OP
2278 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2279 what it really is. */
2280 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2282 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2283 SUBREG_REG (*split)));
2286 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2287 SUBREG_REG (*split)));
2291 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2292 SUBST (*split, newdest);
2293 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2295 /* If the split point was a MULT and we didn't have one before,
2296 don't use one now. */
2297 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2298 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2302 /* Check for a case where we loaded from memory in a narrow mode and
2303 then sign extended it, but we need both registers. In that case,
2304 we have a PARALLEL with both loads from the same memory location.
2305 We can split this into a load from memory followed by a register-register
2306 copy. This saves at least one insn, more if register allocation can
2309 We cannot do this if the destination of the first assignment is a
2310 condition code register or cc0. We eliminate this case by making sure
2311 the SET_DEST and SET_SRC have the same mode.
2313 We cannot do this if the destination of the second assignment is
2314 a register that we have already assumed is zero-extended. Similarly
2315 for a SUBREG of such a register. */
2317 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2318 && GET_CODE (newpat) == PARALLEL
2319 && XVECLEN (newpat, 0) == 2
2320 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2321 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2322 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2323 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2324 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2325 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2326 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2327 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2329 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2330 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2331 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2332 (GET_CODE (temp) == REG
2333 && reg_nonzero_bits[REGNO (temp)] != 0
2334 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2335 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2336 && (reg_nonzero_bits[REGNO (temp)]
2337 != GET_MODE_MASK (word_mode))))
2338 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2339 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2340 (GET_CODE (temp) == REG
2341 && reg_nonzero_bits[REGNO (temp)] != 0
2342 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2343 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2344 && (reg_nonzero_bits[REGNO (temp)]
2345 != GET_MODE_MASK (word_mode)))))
2346 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2347 SET_SRC (XVECEXP (newpat, 0, 1)))
2348 && ! find_reg_note (i3, REG_UNUSED,
2349 SET_DEST (XVECEXP (newpat, 0, 0))))
2353 newi2pat = XVECEXP (newpat, 0, 0);
2354 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2355 newpat = XVECEXP (newpat, 0, 1);
2356 SUBST (SET_SRC (newpat),
2357 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2358 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2360 if (i2_code_number >= 0)
2361 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2363 if (insn_code_number >= 0)
2368 /* If we will be able to accept this, we have made a change to the
2369 destination of I3. This can invalidate a LOG_LINKS pointing
2370 to I3. No other part of combine.c makes such a transformation.
2372 The new I3 will have a destination that was previously the
2373 destination of I1 or I2 and which was used in i2 or I3. Call
2374 distribute_links to make a LOG_LINK from the next use of
2375 that destination. */
2377 PATTERN (i3) = newpat;
2378 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2380 /* I3 now uses what used to be its destination and which is
2381 now I2's destination. That means we need a LOG_LINK from
2382 I3 to I2. But we used to have one, so we still will.
2384 However, some later insn might be using I2's dest and have
2385 a LOG_LINK pointing at I3. We must remove this link.
2386 The simplest way to remove the link is to point it at I1,
2387 which we know will be a NOTE. */
2389 for (insn = NEXT_INSN (i3);
2390 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2391 || insn != this_basic_block->next_bb->head);
2392 insn = NEXT_INSN (insn))
2394 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2396 for (link = LOG_LINKS (insn); link;
2397 link = XEXP (link, 1))
2398 if (XEXP (link, 0) == i3)
2399 XEXP (link, 0) = i1;
2407 /* Similarly, check for a case where we have a PARALLEL of two independent
2408 SETs but we started with three insns. In this case, we can do the sets
2409 as two separate insns. This case occurs when some SET allows two
2410 other insns to combine, but the destination of that SET is still live. */
2412 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2413 && GET_CODE (newpat) == PARALLEL
2414 && XVECLEN (newpat, 0) == 2
2415 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2416 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2417 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2418 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2419 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2420 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2421 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2423 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2424 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2425 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2426 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2427 XVECEXP (newpat, 0, 0))
2428 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2429 XVECEXP (newpat, 0, 1))
2430 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2431 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2433 /* Normally, it doesn't matter which of the two is done first,
2434 but it does if one references cc0. In that case, it has to
2437 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2439 newi2pat = XVECEXP (newpat, 0, 0);
2440 newpat = XVECEXP (newpat, 0, 1);
2445 newi2pat = XVECEXP (newpat, 0, 1);
2446 newpat = XVECEXP (newpat, 0, 0);
2449 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2451 if (i2_code_number >= 0)
2452 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2455 /* If it still isn't recognized, fail and change things back the way they
2457 if ((insn_code_number < 0
2458 /* Is the result a reasonable ASM_OPERANDS? */
2459 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2465 /* If we had to change another insn, make sure it is valid also. */
2466 if (undobuf.other_insn)
2468 rtx other_pat = PATTERN (undobuf.other_insn);
2469 rtx new_other_notes;
2472 CLEAR_HARD_REG_SET (newpat_used_regs);
2474 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2477 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2483 PATTERN (undobuf.other_insn) = other_pat;
2485 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2486 are still valid. Then add any non-duplicate notes added by
2487 recog_for_combine. */
2488 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2490 next = XEXP (note, 1);
2492 if (REG_NOTE_KIND (note) == REG_UNUSED
2493 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2495 if (GET_CODE (XEXP (note, 0)) == REG)
2496 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2498 remove_note (undobuf.other_insn, note);
2502 for (note = new_other_notes; note; note = XEXP (note, 1))
2503 if (GET_CODE (XEXP (note, 0)) == REG)
2504 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2506 distribute_notes (new_other_notes, undobuf.other_insn,
2507 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2510 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2511 they are adjacent to each other or not. */
2513 rtx p = prev_nonnote_insn (i3);
2514 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2515 && sets_cc0_p (newi2pat))
2523 /* We now know that we can do this combination. Merge the insns and
2524 update the status of registers and LOG_LINKS. */
2527 rtx i3notes, i2notes, i1notes = 0;
2528 rtx i3links, i2links, i1links = 0;
2531 /* Compute which registers we expect to eliminate. newi2pat may be setting
2532 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2533 same as i3dest, in which case newi2pat may be setting i1dest. */
2534 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2535 || i2dest_in_i2src || i2dest_in_i1src
2537 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2538 || (newi2pat && reg_set_p (i1dest, newi2pat))
2541 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2543 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2544 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2546 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2548 /* Ensure that we do not have something that should not be shared but
2549 occurs multiple times in the new insns. Check this by first
2550 resetting all the `used' flags and then copying anything is shared. */
2552 reset_used_flags (i3notes);
2553 reset_used_flags (i2notes);
2554 reset_used_flags (i1notes);
2555 reset_used_flags (newpat);
2556 reset_used_flags (newi2pat);
2557 if (undobuf.other_insn)
2558 reset_used_flags (PATTERN (undobuf.other_insn));
2560 i3notes = copy_rtx_if_shared (i3notes);
2561 i2notes = copy_rtx_if_shared (i2notes);
2562 i1notes = copy_rtx_if_shared (i1notes);
2563 newpat = copy_rtx_if_shared (newpat);
2564 newi2pat = copy_rtx_if_shared (newi2pat);
2565 if (undobuf.other_insn)
2566 reset_used_flags (PATTERN (undobuf.other_insn));
2568 INSN_CODE (i3) = insn_code_number;
2569 PATTERN (i3) = newpat;
2571 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2573 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2575 reset_used_flags (call_usage);
2576 call_usage = copy_rtx (call_usage);
2579 replace_rtx (call_usage, i2dest, i2src);
2582 replace_rtx (call_usage, i1dest, i1src);
2584 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2587 if (undobuf.other_insn)
2588 INSN_CODE (undobuf.other_insn) = other_code_number;
2590 /* We had one special case above where I2 had more than one set and
2591 we replaced a destination of one of those sets with the destination
2592 of I3. In that case, we have to update LOG_LINKS of insns later
2593 in this basic block. Note that this (expensive) case is rare.
2595 Also, in this case, we must pretend that all REG_NOTEs for I2
2596 actually came from I3, so that REG_UNUSED notes from I2 will be
2597 properly handled. */
2599 if (i3_subst_into_i2)
2601 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2602 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2603 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2604 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2605 && ! find_reg_note (i2, REG_UNUSED,
2606 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2607 for (temp = NEXT_INSN (i2);
2608 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2609 || this_basic_block->head != temp);
2610 temp = NEXT_INSN (temp))
2611 if (temp != i3 && INSN_P (temp))
2612 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2613 if (XEXP (link, 0) == i2)
2614 XEXP (link, 0) = i3;
2619 while (XEXP (link, 1))
2620 link = XEXP (link, 1);
2621 XEXP (link, 1) = i2notes;
2635 INSN_CODE (i2) = i2_code_number;
2636 PATTERN (i2) = newi2pat;
2640 PUT_CODE (i2, NOTE);
2641 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2642 NOTE_SOURCE_FILE (i2) = 0;
2649 PUT_CODE (i1, NOTE);
2650 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2651 NOTE_SOURCE_FILE (i1) = 0;
2654 /* Get death notes for everything that is now used in either I3 or
2655 I2 and used to die in a previous insn. If we built two new
2656 patterns, move from I1 to I2 then I2 to I3 so that we get the
2657 proper movement on registers that I2 modifies. */
2661 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2662 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2665 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2668 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2670 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2673 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2676 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2679 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2682 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2683 know these are REG_UNUSED and want them to go to the desired insn,
2684 so we always pass it as i3. We have not counted the notes in
2685 reg_n_deaths yet, so we need to do so now. */
2687 if (newi2pat && new_i2_notes)
2689 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2690 if (GET_CODE (XEXP (temp, 0)) == REG)
2691 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2693 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2698 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2699 if (GET_CODE (XEXP (temp, 0)) == REG)
2700 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2702 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2705 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2706 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2707 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2708 in that case, it might delete I2. Similarly for I2 and I1.
2709 Show an additional death due to the REG_DEAD note we make here. If
2710 we discard it in distribute_notes, we will decrement it again. */
2714 if (GET_CODE (i3dest_killed) == REG)
2715 REG_N_DEATHS (REGNO (i3dest_killed))++;
2717 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2718 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2720 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2722 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2724 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2728 if (i2dest_in_i2src)
2730 if (GET_CODE (i2dest) == REG)
2731 REG_N_DEATHS (REGNO (i2dest))++;
2733 if (newi2pat && reg_set_p (i2dest, newi2pat))
2734 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2735 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2737 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2738 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2739 NULL_RTX, NULL_RTX);
2742 if (i1dest_in_i1src)
2744 if (GET_CODE (i1dest) == REG)
2745 REG_N_DEATHS (REGNO (i1dest))++;
2747 if (newi2pat && reg_set_p (i1dest, newi2pat))
2748 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2749 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2751 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2752 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2753 NULL_RTX, NULL_RTX);
2756 distribute_links (i3links);
2757 distribute_links (i2links);
2758 distribute_links (i1links);
2760 if (GET_CODE (i2dest) == REG)
2763 rtx i2_insn = 0, i2_val = 0, set;
2765 /* The insn that used to set this register doesn't exist, and
2766 this life of the register may not exist either. See if one of
2767 I3's links points to an insn that sets I2DEST. If it does,
2768 that is now the last known value for I2DEST. If we don't update
2769 this and I2 set the register to a value that depended on its old
2770 contents, we will get confused. If this insn is used, thing
2771 will be set correctly in combine_instructions. */
2773 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2774 if ((set = single_set (XEXP (link, 0))) != 0
2775 && rtx_equal_p (i2dest, SET_DEST (set)))
2776 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2778 record_value_for_reg (i2dest, i2_insn, i2_val);
2780 /* If the reg formerly set in I2 died only once and that was in I3,
2781 zero its use count so it won't make `reload' do any work. */
2783 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2784 && ! i2dest_in_i2src)
2786 regno = REGNO (i2dest);
2787 REG_N_SETS (regno)--;
2791 if (i1 && GET_CODE (i1dest) == REG)
2794 rtx i1_insn = 0, i1_val = 0, set;
2796 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2797 if ((set = single_set (XEXP (link, 0))) != 0
2798 && rtx_equal_p (i1dest, SET_DEST (set)))
2799 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2801 record_value_for_reg (i1dest, i1_insn, i1_val);
2803 regno = REGNO (i1dest);
2804 if (! added_sets_1 && ! i1dest_in_i1src)
2805 REG_N_SETS (regno)--;
2808 /* Update reg_nonzero_bits et al for any changes that may have been made
2809 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2810 important. Because newi2pat can affect nonzero_bits of newpat */
2812 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2813 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2815 /* Set new_direct_jump_p if a new return or simple jump instruction
2818 If I3 is now an unconditional jump, ensure that it has a
2819 BARRIER following it since it may have initially been a
2820 conditional jump. It may also be the last nonnote insn. */
2822 if (returnjump_p (i3) || any_uncondjump_p (i3))
2824 *new_direct_jump_p = 1;
2826 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2827 || GET_CODE (temp) != BARRIER)
2828 emit_barrier_after (i3);
2831 if (undobuf.other_insn != NULL_RTX
2832 && (returnjump_p (undobuf.other_insn)
2833 || any_uncondjump_p (undobuf.other_insn)))
2835 *new_direct_jump_p = 1;
2837 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2838 || GET_CODE (temp) != BARRIER)
2839 emit_barrier_after (undobuf.other_insn);
2842 /* An NOOP jump does not need barrier, but it does need cleaning up
2844 if (GET_CODE (newpat) == SET
2845 && SET_SRC (newpat) == pc_rtx
2846 && SET_DEST (newpat) == pc_rtx)
2847 *new_direct_jump_p = 1;
2850 combine_successes++;
2853 if (added_links_insn
2854 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2855 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2856 return added_links_insn;
2858 return newi2pat ? i2 : i3;
2861 /* Undo all the modifications recorded in undobuf. */
2866 struct undo *undo, *next;
2868 for (undo = undobuf.undos; undo; undo = next)
2872 *undo->where.i = undo->old_contents.i;
2874 *undo->where.r = undo->old_contents.r;
2876 undo->next = undobuf.frees;
2877 undobuf.frees = undo;
2883 /* We've committed to accepting the changes we made. Move all
2884 of the undos to the free list. */
2889 struct undo *undo, *next;
2891 for (undo = undobuf.undos; undo; undo = next)
2894 undo->next = undobuf.frees;
2895 undobuf.frees = undo;
2901 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2902 where we have an arithmetic expression and return that point. LOC will
2905 try_combine will call this function to see if an insn can be split into
2909 find_split_point (loc, insn)
2914 enum rtx_code code = GET_CODE (x);
2916 unsigned HOST_WIDE_INT len = 0;
2917 HOST_WIDE_INT pos = 0;
2919 rtx inner = NULL_RTX;
2921 /* First special-case some codes. */
2925 #ifdef INSN_SCHEDULING
2926 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2928 if (GET_CODE (SUBREG_REG (x)) == MEM)
2931 return find_split_point (&SUBREG_REG (x), insn);
2935 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2936 using LO_SUM and HIGH. */
2937 if (GET_CODE (XEXP (x, 0)) == CONST
2938 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2941 gen_rtx_LO_SUM (Pmode,
2942 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2944 return &XEXP (XEXP (x, 0), 0);
2948 /* If we have a PLUS whose second operand is a constant and the
2949 address is not valid, perhaps will can split it up using
2950 the machine-specific way to split large constants. We use
2951 the first pseudo-reg (one of the virtual regs) as a placeholder;
2952 it will not remain in the result. */
2953 if (GET_CODE (XEXP (x, 0)) == PLUS
2954 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2955 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2957 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2958 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2961 /* This should have produced two insns, each of which sets our
2962 placeholder. If the source of the second is a valid address,
2963 we can make put both sources together and make a split point
2967 && NEXT_INSN (seq) != NULL_RTX
2968 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2969 && GET_CODE (seq) == INSN
2970 && GET_CODE (PATTERN (seq)) == SET
2971 && SET_DEST (PATTERN (seq)) == reg
2972 && ! reg_mentioned_p (reg,
2973 SET_SRC (PATTERN (seq)))
2974 && GET_CODE (NEXT_INSN (seq)) == INSN
2975 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2976 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2977 && memory_address_p (GET_MODE (x),
2978 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2980 rtx src1 = SET_SRC (PATTERN (seq));
2981 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2983 /* Replace the placeholder in SRC2 with SRC1. If we can
2984 find where in SRC2 it was placed, that can become our
2985 split point and we can replace this address with SRC2.
2986 Just try two obvious places. */
2988 src2 = replace_rtx (src2, reg, src1);
2990 if (XEXP (src2, 0) == src1)
2991 split = &XEXP (src2, 0);
2992 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2993 && XEXP (XEXP (src2, 0), 0) == src1)
2994 split = &XEXP (XEXP (src2, 0), 0);
2998 SUBST (XEXP (x, 0), src2);
3003 /* If that didn't work, perhaps the first operand is complex and
3004 needs to be computed separately, so make a split point there.
3005 This will occur on machines that just support REG + CONST
3006 and have a constant moved through some previous computation. */
3008 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3009 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3010 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3012 return &XEXP (XEXP (x, 0), 0);
3018 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3019 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3020 we need to put the operand into a register. So split at that
3023 if (SET_DEST (x) == cc0_rtx
3024 && GET_CODE (SET_SRC (x)) != COMPARE
3025 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3026 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3027 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3028 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3029 return &SET_SRC (x);
3032 /* See if we can split SET_SRC as it stands. */
3033 split = find_split_point (&SET_SRC (x), insn);
3034 if (split && split != &SET_SRC (x))
3037 /* See if we can split SET_DEST as it stands. */
3038 split = find_split_point (&SET_DEST (x), insn);
3039 if (split && split != &SET_DEST (x))
3042 /* See if this is a bitfield assignment with everything constant. If
3043 so, this is an IOR of an AND, so split it into that. */
3044 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3045 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3046 <= HOST_BITS_PER_WIDE_INT)
3047 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3048 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3049 && GET_CODE (SET_SRC (x)) == CONST_INT
3050 && ((INTVAL (XEXP (SET_DEST (x), 1))
3051 + INTVAL (XEXP (SET_DEST (x), 2)))
3052 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3053 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3055 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3056 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3057 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3058 rtx dest = XEXP (SET_DEST (x), 0);
3059 enum machine_mode mode = GET_MODE (dest);
3060 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3062 if (BITS_BIG_ENDIAN)
3063 pos = GET_MODE_BITSIZE (mode) - len - pos;
3067 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3070 gen_binary (IOR, mode,
3071 gen_binary (AND, mode, dest,
3072 gen_int_mode (~(mask << pos),
3074 GEN_INT (src << pos)));
3076 SUBST (SET_DEST (x), dest);
3078 split = find_split_point (&SET_SRC (x), insn);
3079 if (split && split != &SET_SRC (x))
3083 /* Otherwise, see if this is an operation that we can split into two.
3084 If so, try to split that. */
3085 code = GET_CODE (SET_SRC (x));
3090 /* If we are AND'ing with a large constant that is only a single
3091 bit and the result is only being used in a context where we
3092 need to know if it is zero or nonzero, replace it with a bit
3093 extraction. This will avoid the large constant, which might
3094 have taken more than one insn to make. If the constant were
3095 not a valid argument to the AND but took only one insn to make,
3096 this is no worse, but if it took more than one insn, it will
3099 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3100 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3101 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3102 && GET_CODE (SET_DEST (x)) == REG
3103 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3104 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3105 && XEXP (*split, 0) == SET_DEST (x)
3106 && XEXP (*split, 1) == const0_rtx)
3108 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3109 XEXP (SET_SRC (x), 0),
3110 pos, NULL_RTX, 1, 1, 0, 0);
3111 if (extraction != 0)
3113 SUBST (SET_SRC (x), extraction);
3114 return find_split_point (loc, insn);
3120 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3121 is known to be on, this can be converted into a NEG of a shift. */
3122 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3123 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3124 && 1 <= (pos = exact_log2
3125 (nonzero_bits (XEXP (SET_SRC (x), 0),
3126 GET_MODE (XEXP (SET_SRC (x), 0))))))
3128 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3132 gen_rtx_LSHIFTRT (mode,
3133 XEXP (SET_SRC (x), 0),
3136 split = find_split_point (&SET_SRC (x), insn);
3137 if (split && split != &SET_SRC (x))
3143 inner = XEXP (SET_SRC (x), 0);
3145 /* We can't optimize if either mode is a partial integer
3146 mode as we don't know how many bits are significant
3148 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3149 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3153 len = GET_MODE_BITSIZE (GET_MODE (inner));
3159 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3160 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3162 inner = XEXP (SET_SRC (x), 0);
3163 len = INTVAL (XEXP (SET_SRC (x), 1));
3164 pos = INTVAL (XEXP (SET_SRC (x), 2));
3166 if (BITS_BIG_ENDIAN)
3167 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3168 unsignedp = (code == ZERO_EXTRACT);
3176 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3178 enum machine_mode mode = GET_MODE (SET_SRC (x));
3180 /* For unsigned, we have a choice of a shift followed by an
3181 AND or two shifts. Use two shifts for field sizes where the
3182 constant might be too large. We assume here that we can
3183 always at least get 8-bit constants in an AND insn, which is
3184 true for every current RISC. */
3186 if (unsignedp && len <= 8)
3191 (mode, gen_lowpart_for_combine (mode, inner),
3193 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3195 split = find_split_point (&SET_SRC (x), insn);
3196 if (split && split != &SET_SRC (x))
3203 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3204 gen_rtx_ASHIFT (mode,
3205 gen_lowpart_for_combine (mode, inner),
3206 GEN_INT (GET_MODE_BITSIZE (mode)
3208 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3210 split = find_split_point (&SET_SRC (x), insn);
3211 if (split && split != &SET_SRC (x))
3216 /* See if this is a simple operation with a constant as the second
3217 operand. It might be that this constant is out of range and hence
3218 could be used as a split point. */
3219 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3220 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3221 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3222 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3223 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3224 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3225 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3227 return &XEXP (SET_SRC (x), 1);
3229 /* Finally, see if this is a simple operation with its first operand
3230 not in a register. The operation might require this operand in a
3231 register, so return it as a split point. We can always do this
3232 because if the first operand were another operation, we would have
3233 already found it as a split point. */
3234 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3235 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3236 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3237 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3238 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3239 return &XEXP (SET_SRC (x), 0);
3245 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3246 it is better to write this as (not (ior A B)) so we can split it.
3247 Similarly for IOR. */
3248 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3251 gen_rtx_NOT (GET_MODE (x),
3252 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3254 XEXP (XEXP (x, 0), 0),
3255 XEXP (XEXP (x, 1), 0))));
3256 return find_split_point (loc, insn);
3259 /* Many RISC machines have a large set of logical insns. If the
3260 second operand is a NOT, put it first so we will try to split the
3261 other operand first. */
3262 if (GET_CODE (XEXP (x, 1)) == NOT)
3264 rtx tem = XEXP (x, 0);
3265 SUBST (XEXP (x, 0), XEXP (x, 1));
3266 SUBST (XEXP (x, 1), tem);
3274 /* Otherwise, select our actions depending on our rtx class. */
3275 switch (GET_RTX_CLASS (code))
3277 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3279 split = find_split_point (&XEXP (x, 2), insn);
3282 /* ... fall through ... */
3286 split = find_split_point (&XEXP (x, 1), insn);
3289 /* ... fall through ... */
3291 /* Some machines have (and (shift ...) ...) insns. If X is not
3292 an AND, but XEXP (X, 0) is, use it as our split point. */
3293 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3294 return &XEXP (x, 0);
3296 split = find_split_point (&XEXP (x, 0), insn);
3302 /* Otherwise, we don't have a split point. */
3306 /* Throughout X, replace FROM with TO, and return the result.
3307 The result is TO if X is FROM;
3308 otherwise the result is X, but its contents may have been modified.
3309 If they were modified, a record was made in undobuf so that
3310 undo_all will (among other things) return X to its original state.
3312 If the number of changes necessary is too much to record to undo,
3313 the excess changes are not made, so the result is invalid.
3314 The changes already made can still be undone.
3315 undobuf.num_undo is incremented for such changes, so by testing that
3316 the caller can tell whether the result is valid.
3318 `n_occurrences' is incremented each time FROM is replaced.
3320 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3322 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3323 by copying if `n_occurrences' is nonzero. */
3326 subst (x, from, to, in_dest, unique_copy)
3331 enum rtx_code code = GET_CODE (x);
3332 enum machine_mode op0_mode = VOIDmode;
3337 /* Two expressions are equal if they are identical copies of a shared
3338 RTX or if they are both registers with the same register number
3341 #define COMBINE_RTX_EQUAL_P(X,Y) \
3343 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3344 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3346 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3349 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3352 /* If X and FROM are the same register but different modes, they will
3353 not have been seen as equal above. However, flow.c will make a
3354 LOG_LINKS entry for that case. If we do nothing, we will try to
3355 rerecognize our original insn and, when it succeeds, we will
3356 delete the feeding insn, which is incorrect.
3358 So force this insn not to match in this (rare) case. */
3359 if (! in_dest && code == REG && GET_CODE (from) == REG
3360 && REGNO (x) == REGNO (from))
3361 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3363 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3364 of which may contain things that can be combined. */
3365 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3368 /* It is possible to have a subexpression appear twice in the insn.
3369 Suppose that FROM is a register that appears within TO.
3370 Then, after that subexpression has been scanned once by `subst',
3371 the second time it is scanned, TO may be found. If we were
3372 to scan TO here, we would find FROM within it and create a
3373 self-referent rtl structure which is completely wrong. */
3374 if (COMBINE_RTX_EQUAL_P (x, to))
3377 /* Parallel asm_operands need special attention because all of the
3378 inputs are shared across the arms. Furthermore, unsharing the
3379 rtl results in recognition failures. Failure to handle this case
3380 specially can result in circular rtl.
3382 Solve this by doing a normal pass across the first entry of the
3383 parallel, and only processing the SET_DESTs of the subsequent
3386 if (code == PARALLEL
3387 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3388 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3390 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3392 /* If this substitution failed, this whole thing fails. */
3393 if (GET_CODE (new) == CLOBBER
3394 && XEXP (new, 0) == const0_rtx)
3397 SUBST (XVECEXP (x, 0, 0), new);
3399 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3401 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3403 if (GET_CODE (dest) != REG
3404 && GET_CODE (dest) != CC0
3405 && GET_CODE (dest) != PC)
3407 new = subst (dest, from, to, 0, unique_copy);
3409 /* If this substitution failed, this whole thing fails. */
3410 if (GET_CODE (new) == CLOBBER
3411 && XEXP (new, 0) == const0_rtx)
3414 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3420 len = GET_RTX_LENGTH (code);
3421 fmt = GET_RTX_FORMAT (code);
3423 /* We don't need to process a SET_DEST that is a register, CC0,
3424 or PC, so set up to skip this common case. All other cases
3425 where we want to suppress replacing something inside a
3426 SET_SRC are handled via the IN_DEST operand. */
3428 && (GET_CODE (SET_DEST (x)) == REG
3429 || GET_CODE (SET_DEST (x)) == CC0
3430 || GET_CODE (SET_DEST (x)) == PC))
3433 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3436 op0_mode = GET_MODE (XEXP (x, 0));
3438 for (i = 0; i < len; i++)
3443 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3445 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3447 new = (unique_copy && n_occurrences
3448 ? copy_rtx (to) : to);
3453 new = subst (XVECEXP (x, i, j), from, to, 0,
3456 /* If this substitution failed, this whole thing
3458 if (GET_CODE (new) == CLOBBER
3459 && XEXP (new, 0) == const0_rtx)
3463 SUBST (XVECEXP (x, i, j), new);
3466 else if (fmt[i] == 'e')
3468 /* If this is a register being set, ignore it. */
3471 && (code == SUBREG || code == STRICT_LOW_PART
3472 || code == ZERO_EXTRACT)
3474 && GET_CODE (new) == REG)
3477 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3479 /* In general, don't install a subreg involving two
3480 modes not tieable. It can worsen register
3481 allocation, and can even make invalid reload
3482 insns, since the reg inside may need to be copied
3483 from in the outside mode, and that may be invalid
3484 if it is an fp reg copied in integer mode.
3486 We allow two exceptions to this: It is valid if
3487 it is inside another SUBREG and the mode of that
3488 SUBREG and the mode of the inside of TO is
3489 tieable and it is valid if X is a SET that copies
3492 if (GET_CODE (to) == SUBREG
3493 && ! MODES_TIEABLE_P (GET_MODE (to),
3494 GET_MODE (SUBREG_REG (to)))
3495 && ! (code == SUBREG
3496 && MODES_TIEABLE_P (GET_MODE (x),
3497 GET_MODE (SUBREG_REG (to))))
3499 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3502 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3504 #ifdef CANNOT_CHANGE_MODE_CLASS
3506 && GET_CODE (to) == REG
3507 && REGNO (to) < FIRST_PSEUDO_REGISTER
3508 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3511 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3514 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3518 /* If we are in a SET_DEST, suppress most cases unless we
3519 have gone inside a MEM, in which case we want to
3520 simplify the address. We assume here that things that
3521 are actually part of the destination have their inner
3522 parts in the first expression. This is true for SUBREG,
3523 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3524 things aside from REG and MEM that should appear in a
3526 new = subst (XEXP (x, i), from, to,
3528 && (code == SUBREG || code == STRICT_LOW_PART
3529 || code == ZERO_EXTRACT))
3531 && i == 0), unique_copy);
3533 /* If we found that we will have to reject this combination,
3534 indicate that by returning the CLOBBER ourselves, rather than
3535 an expression containing it. This will speed things up as
3536 well as prevent accidents where two CLOBBERs are considered
3537 to be equal, thus producing an incorrect simplification. */
3539 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3542 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3544 enum machine_mode mode = GET_MODE (x);
3546 x = simplify_subreg (GET_MODE (x), new,
3547 GET_MODE (SUBREG_REG (x)),
3550 x = gen_rtx_CLOBBER (mode, const0_rtx);
3552 else if (GET_CODE (new) == CONST_INT
3553 && GET_CODE (x) == ZERO_EXTEND)
3555 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3556 new, GET_MODE (XEXP (x, 0)));
3561 SUBST (XEXP (x, i), new);
3566 /* Try to simplify X. If the simplification changed the code, it is likely
3567 that further simplification will help, so loop, but limit the number
3568 of repetitions that will be performed. */
3570 for (i = 0; i < 4; i++)
3572 /* If X is sufficiently simple, don't bother trying to do anything
3574 if (code != CONST_INT && code != REG && code != CLOBBER)
3575 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3577 if (GET_CODE (x) == code)
3580 code = GET_CODE (x);
3582 /* We no longer know the original mode of operand 0 since we
3583 have changed the form of X) */
3584 op0_mode = VOIDmode;
3590 /* Simplify X, a piece of RTL. We just operate on the expression at the
3591 outer level; call `subst' to simplify recursively. Return the new
3594 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3595 will be the iteration even if an expression with a code different from
3596 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3599 combine_simplify_rtx (x, op0_mode, last, in_dest)
3601 enum machine_mode op0_mode;
3605 enum rtx_code code = GET_CODE (x);
3606 enum machine_mode mode = GET_MODE (x);
3611 /* If this is a commutative operation, put a constant last and a complex
3612 expression first. We don't need to do this for comparisons here. */
3613 if (GET_RTX_CLASS (code) == 'c'
3614 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3617 SUBST (XEXP (x, 0), XEXP (x, 1));
3618 SUBST (XEXP (x, 1), temp);
3621 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3622 sign extension of a PLUS with a constant, reverse the order of the sign
3623 extension and the addition. Note that this not the same as the original
3624 code, but overflow is undefined for signed values. Also note that the
3625 PLUS will have been partially moved "inside" the sign-extension, so that
3626 the first operand of X will really look like:
3627 (ashiftrt (plus (ashift A C4) C5) C4).
3629 (plus (ashiftrt (ashift A C4) C2) C4)
3630 and replace the first operand of X with that expression. Later parts
3631 of this function may simplify the expression further.
3633 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3634 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3635 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3637 We do this to simplify address expressions. */
3639 if ((code == PLUS || code == MINUS || code == MULT)
3640 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3641 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3642 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3643 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3644 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3645 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3646 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3647 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3648 XEXP (XEXP (XEXP (x, 0), 0), 1),
3649 XEXP (XEXP (x, 0), 1))) != 0)
3652 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3653 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3654 INTVAL (XEXP (XEXP (x, 0), 1)));
3656 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3657 INTVAL (XEXP (XEXP (x, 0), 1)));
3659 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3662 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3663 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3664 things. Check for cases where both arms are testing the same
3667 Don't do anything if all operands are very simple. */
3669 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3670 || GET_RTX_CLASS (code) == '<')
3671 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3672 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3673 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3675 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3676 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3677 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3679 || (GET_RTX_CLASS (code) == '1'
3680 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3681 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3682 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3685 rtx cond, true_rtx, false_rtx;
3687 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3689 /* If everything is a comparison, what we have is highly unlikely
3690 to be simpler, so don't use it. */
3691 && ! (GET_RTX_CLASS (code) == '<'
3692 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3693 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3695 rtx cop1 = const0_rtx;
3696 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3698 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3701 /* Simplify the alternative arms; this may collapse the true and
3702 false arms to store-flag values. */
3703 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3704 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3706 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3707 is unlikely to be simpler. */
3708 if (general_operand (true_rtx, VOIDmode)
3709 && general_operand (false_rtx, VOIDmode))
3711 enum rtx_code reversed;
3713 /* Restarting if we generate a store-flag expression will cause
3714 us to loop. Just drop through in this case. */
3716 /* If the result values are STORE_FLAG_VALUE and zero, we can
3717 just make the comparison operation. */
3718 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3719 x = gen_binary (cond_code, mode, cond, cop1);
3720 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3721 && ((reversed = reversed_comparison_code_parts
3722 (cond_code, cond, cop1, NULL))
3724 x = gen_binary (reversed, mode, cond, cop1);
3726 /* Likewise, we can make the negate of a comparison operation
3727 if the result values are - STORE_FLAG_VALUE and zero. */
3728 else if (GET_CODE (true_rtx) == CONST_INT
3729 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3730 && false_rtx == const0_rtx)
3731 x = simplify_gen_unary (NEG, mode,
3732 gen_binary (cond_code, mode, cond,
3735 else if (GET_CODE (false_rtx) == CONST_INT
3736 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3737 && true_rtx == const0_rtx
3738 && ((reversed = reversed_comparison_code_parts
3739 (cond_code, cond, cop1, NULL))
3741 x = simplify_gen_unary (NEG, mode,
3742 gen_binary (reversed, mode,
3746 return gen_rtx_IF_THEN_ELSE (mode,
3747 gen_binary (cond_code, VOIDmode,
3749 true_rtx, false_rtx);
3751 code = GET_CODE (x);
3752 op0_mode = VOIDmode;
3757 /* Try to fold this expression in case we have constants that weren't
3760 switch (GET_RTX_CLASS (code))
3763 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3767 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3768 if (cmp_mode == VOIDmode)
3770 cmp_mode = GET_MODE (XEXP (x, 1));
3771 if (cmp_mode == VOIDmode)
3772 cmp_mode = op0_mode;
3774 temp = simplify_relational_operation (code, cmp_mode,
3775 XEXP (x, 0), XEXP (x, 1));
3777 #ifdef FLOAT_STORE_FLAG_VALUE
3778 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3780 if (temp == const0_rtx)
3781 temp = CONST0_RTX (mode);
3783 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3790 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3794 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3795 XEXP (x, 1), XEXP (x, 2));
3802 code = GET_CODE (temp);
3803 op0_mode = VOIDmode;
3804 mode = GET_MODE (temp);
3807 /* First see if we can apply the inverse distributive law. */
3808 if (code == PLUS || code == MINUS
3809 || code == AND || code == IOR || code == XOR)
3811 x = apply_distributive_law (x);
3812 code = GET_CODE (x);
3813 op0_mode = VOIDmode;
3816 /* If CODE is an associative operation not otherwise handled, see if we
3817 can associate some operands. This can win if they are constants or
3818 if they are logically related (i.e. (a & b) & a). */
3819 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3820 || code == AND || code == IOR || code == XOR
3821 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3822 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3823 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3825 if (GET_CODE (XEXP (x, 0)) == code)
3827 rtx other = XEXP (XEXP (x, 0), 0);
3828 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3829 rtx inner_op1 = XEXP (x, 1);
3832 /* Make sure we pass the constant operand if any as the second
3833 one if this is a commutative operation. */
3834 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3836 rtx tem = inner_op0;
3837 inner_op0 = inner_op1;
3840 inner = simplify_binary_operation (code == MINUS ? PLUS
3841 : code == DIV ? MULT
3843 mode, inner_op0, inner_op1);
3845 /* For commutative operations, try the other pair if that one
3847 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3849 other = XEXP (XEXP (x, 0), 1);
3850 inner = simplify_binary_operation (code, mode,
3851 XEXP (XEXP (x, 0), 0),
3856 return gen_binary (code, mode, other, inner);
3860 /* A little bit of algebraic simplification here. */
3864 /* Ensure that our address has any ASHIFTs converted to MULT in case
3865 address-recognizing predicates are called later. */
3866 temp = make_compound_operation (XEXP (x, 0), MEM);
3867 SUBST (XEXP (x, 0), temp);
3871 if (op0_mode == VOIDmode)
3872 op0_mode = GET_MODE (SUBREG_REG (x));
3874 /* simplify_subreg can't use gen_lowpart_for_combine. */
3875 if (CONSTANT_P (SUBREG_REG (x))
3876 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3877 /* Don't call gen_lowpart_for_combine if the inner mode
3878 is VOIDmode and we cannot simplify it, as SUBREG without
3879 inner mode is invalid. */
3880 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3881 || gen_lowpart_common (mode, SUBREG_REG (x))))
3882 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3884 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3888 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3894 /* Don't change the mode of the MEM if that would change the meaning
3896 if (GET_CODE (SUBREG_REG (x)) == MEM
3897 && (MEM_VOLATILE_P (SUBREG_REG (x))
3898 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3899 return gen_rtx_CLOBBER (mode, const0_rtx);
3901 /* Note that we cannot do any narrowing for non-constants since
3902 we might have been counting on using the fact that some bits were
3903 zero. We now do this in the SET. */
3908 /* (not (plus X -1)) can become (neg X). */
3909 if (GET_CODE (XEXP (x, 0)) == PLUS
3910 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3911 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3913 /* Similarly, (not (neg X)) is (plus X -1). */
3914 if (GET_CODE (XEXP (x, 0)) == NEG)
3915 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3917 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3918 if (GET_CODE (XEXP (x, 0)) == XOR
3919 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3920 && (temp = simplify_unary_operation (NOT, mode,
3921 XEXP (XEXP (x, 0), 1),
3923 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3925 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3926 other than 1, but that is not valid. We could do a similar
3927 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3928 but this doesn't seem common enough to bother with. */
3929 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3930 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3931 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3933 XEXP (XEXP (x, 0), 1));
3935 if (GET_CODE (XEXP (x, 0)) == SUBREG
3936 && subreg_lowpart_p (XEXP (x, 0))
3937 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3938 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3939 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3940 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3942 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3944 x = gen_rtx_ROTATE (inner_mode,
3945 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3947 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3948 return gen_lowpart_for_combine (mode, x);
3951 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3952 reversing the comparison code if valid. */
3953 if (STORE_FLAG_VALUE == -1
3954 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3955 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3956 XEXP (XEXP (x, 0), 1))))
3959 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3960 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3961 perform the above simplification. */
3963 if (STORE_FLAG_VALUE == -1
3964 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3965 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3966 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3967 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3969 /* Apply De Morgan's laws to reduce number of patterns for machines
3970 with negating logical insns (and-not, nand, etc.). If result has
3971 only one NOT, put it first, since that is how the patterns are
3974 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3976 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3977 enum machine_mode op_mode;
3979 op_mode = GET_MODE (in1);
3980 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3982 op_mode = GET_MODE (in2);
3983 if (op_mode == VOIDmode)
3985 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3987 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3990 in2 = in1; in1 = tem;
3993 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3999 /* (neg (plus X 1)) can become (not X). */
4000 if (GET_CODE (XEXP (x, 0)) == PLUS
4001 && XEXP (XEXP (x, 0), 1) == const1_rtx)
4002 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
4004 /* Similarly, (neg (not X)) is (plus X 1). */
4005 if (GET_CODE (XEXP (x, 0)) == NOT)
4006 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
4008 /* (neg (minus X Y)) can become (minus Y X). This transformation
4009 isn't safe for modes with signed zeros, since if X and Y are
4010 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4011 mode is towards +infinity (or -infinity) then the two expressions
4012 will be rounded differently. */
4013 if (GET_CODE (XEXP (x, 0)) == MINUS
4014 && !HONOR_SIGNED_ZEROS (mode)
4015 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4016 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4017 XEXP (XEXP (x, 0), 0));
4019 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
4020 if (GET_CODE (XEXP (x, 0)) == PLUS
4021 && !HONOR_SIGNED_ZEROS (mode)
4022 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4024 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4025 temp = combine_simplify_rtx (temp, mode, last, in_dest);
4026 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
4029 /* (neg (mult A B)) becomes (mult (neg A) B).
4030 This works even for floating-point values. */
4031 if (GET_CODE (XEXP (x, 0)) == MULT)
4033 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4034 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
4037 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4038 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4039 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4040 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4042 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4043 if we can then eliminate the NEG (e.g.,
4044 if the operand is a constant). */
4046 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4048 temp = simplify_unary_operation (NEG, mode,
4049 XEXP (XEXP (x, 0), 0), mode);
4051 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4054 temp = expand_compound_operation (XEXP (x, 0));
4056 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4057 replaced by (lshiftrt X C). This will convert
4058 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4060 if (GET_CODE (temp) == ASHIFTRT
4061 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4062 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4063 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4064 INTVAL (XEXP (temp, 1)));
4066 /* If X has only a single bit that might be nonzero, say, bit I, convert
4067 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4068 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4069 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4070 or a SUBREG of one since we'd be making the expression more
4071 complex if it was just a register. */
4073 if (GET_CODE (temp) != REG
4074 && ! (GET_CODE (temp) == SUBREG
4075 && GET_CODE (SUBREG_REG (temp)) == REG)
4076 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4078 rtx temp1 = simplify_shift_const
4079 (NULL_RTX, ASHIFTRT, mode,
4080 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4081 GET_MODE_BITSIZE (mode) - 1 - i),
4082 GET_MODE_BITSIZE (mode) - 1 - i);
4084 /* If all we did was surround TEMP with the two shifts, we
4085 haven't improved anything, so don't use it. Otherwise,
4086 we are better off with TEMP1. */
4087 if (GET_CODE (temp1) != ASHIFTRT
4088 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4089 || XEXP (XEXP (temp1, 0), 0) != temp)
4095 /* We can't handle truncation to a partial integer mode here
4096 because we don't know the real bitsize of the partial
4098 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4101 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4102 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4103 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4105 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4106 GET_MODE_MASK (mode), NULL_RTX, 0));
4108 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4109 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4110 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4111 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4112 return XEXP (XEXP (x, 0), 0);
4114 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4115 (OP:SI foo:SI) if OP is NEG or ABS. */
4116 if ((GET_CODE (XEXP (x, 0)) == ABS
4117 || GET_CODE (XEXP (x, 0)) == NEG)
4118 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4119 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4120 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4121 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4122 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4124 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4126 if (GET_CODE (XEXP (x, 0)) == SUBREG
4127 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4128 && subreg_lowpart_p (XEXP (x, 0)))
4129 return SUBREG_REG (XEXP (x, 0));
4131 /* If we know that the value is already truncated, we can
4132 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4133 is nonzero for the corresponding modes. But don't do this
4134 for an (LSHIFTRT (MULT ...)) since this will cause problems
4135 with the umulXi3_highpart patterns. */
4136 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4137 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4138 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4139 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4140 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4141 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4142 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4144 /* A truncate of a comparison can be replaced with a subreg if
4145 STORE_FLAG_VALUE permits. This is like the previous test,
4146 but it works even if the comparison is done in a mode larger
4147 than HOST_BITS_PER_WIDE_INT. */
4148 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4149 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4150 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4151 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4153 /* Similarly, a truncate of a register whose value is a
4154 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4156 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4157 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4158 && (temp = get_last_value (XEXP (x, 0)))
4159 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4160 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4164 case FLOAT_TRUNCATE:
4165 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4166 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4167 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4168 return XEXP (XEXP (x, 0), 0);
4170 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4171 (OP:SF foo:SF) if OP is NEG or ABS. */
4172 if ((GET_CODE (XEXP (x, 0)) == ABS
4173 || GET_CODE (XEXP (x, 0)) == NEG)
4174 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4175 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4176 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4177 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4179 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4180 is (float_truncate:SF x). */
4181 if (GET_CODE (XEXP (x, 0)) == SUBREG
4182 && subreg_lowpart_p (XEXP (x, 0))
4183 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4184 return SUBREG_REG (XEXP (x, 0));
4189 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4190 using cc0, in which case we want to leave it as a COMPARE
4191 so we can distinguish it from a register-register-copy. */
4192 if (XEXP (x, 1) == const0_rtx)
4195 /* x - 0 is the same as x unless x's mode has signed zeros and
4196 allows rounding towards -infinity. Under those conditions,
4198 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4199 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4200 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4206 /* (const (const X)) can become (const X). Do it this way rather than
4207 returning the inner CONST since CONST can be shared with a
4209 if (GET_CODE (XEXP (x, 0)) == CONST)
4210 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4215 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4216 can add in an offset. find_split_point will split this address up
4217 again if it doesn't match. */
4218 if (GET_CODE (XEXP (x, 0)) == HIGH
4219 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4225 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4227 if (GET_CODE (XEXP (x, 0)) == MULT
4228 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4232 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4233 in2 = XEXP (XEXP (x, 0), 1);
4234 return gen_binary (MINUS, mode, XEXP (x, 1),
4235 gen_binary (MULT, mode, in1, in2));
4238 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4239 outermost. That's because that's the way indexed addresses are
4240 supposed to appear. This code used to check many more cases, but
4241 they are now checked elsewhere. */
4242 if (GET_CODE (XEXP (x, 0)) == PLUS
4243 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4244 return gen_binary (PLUS, mode,
4245 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4247 XEXP (XEXP (x, 0), 1));
4249 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4250 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4251 bit-field and can be replaced by either a sign_extend or a
4252 sign_extract. The `and' may be a zero_extend and the two
4253 <c>, -<c> constants may be reversed. */
4254 if (GET_CODE (XEXP (x, 0)) == XOR
4255 && GET_CODE (XEXP (x, 1)) == CONST_INT
4256 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4257 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4258 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4259 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4260 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4261 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4262 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4263 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4264 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4265 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4266 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4267 == (unsigned int) i + 1))))
4268 return simplify_shift_const
4269 (NULL_RTX, ASHIFTRT, mode,
4270 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4271 XEXP (XEXP (XEXP (x, 0), 0), 0),
4272 GET_MODE_BITSIZE (mode) - (i + 1)),
4273 GET_MODE_BITSIZE (mode) - (i + 1));
4275 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4276 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4277 is 1. This produces better code than the alternative immediately
4279 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4280 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4281 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4282 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4283 XEXP (XEXP (x, 0), 0),
4284 XEXP (XEXP (x, 0), 1))))
4286 simplify_gen_unary (NEG, mode, reversed, mode);
4288 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4289 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4290 the bitsize of the mode - 1. This allows simplification of
4291 "a = (b & 8) == 0;" */
4292 if (XEXP (x, 1) == constm1_rtx
4293 && GET_CODE (XEXP (x, 0)) != REG
4294 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4295 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4296 && nonzero_bits (XEXP (x, 0), mode) == 1)
4297 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4298 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4299 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4300 GET_MODE_BITSIZE (mode) - 1),
4301 GET_MODE_BITSIZE (mode) - 1);
4303 /* If we are adding two things that have no bits in common, convert
4304 the addition into an IOR. This will often be further simplified,
4305 for example in cases like ((a & 1) + (a & 2)), which can
4308 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4309 && (nonzero_bits (XEXP (x, 0), mode)
4310 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4312 /* Try to simplify the expression further. */
4313 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4314 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4316 /* If we could, great. If not, do not go ahead with the IOR
4317 replacement, since PLUS appears in many special purpose
4318 address arithmetic instructions. */
4319 if (GET_CODE (temp) != CLOBBER && temp != tor)
4325 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4326 by reversing the comparison code if valid. */
4327 if (STORE_FLAG_VALUE == 1
4328 && XEXP (x, 0) == const1_rtx
4329 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4330 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4331 XEXP (XEXP (x, 1), 0),
4332 XEXP (XEXP (x, 1), 1))))
4335 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4336 (and <foo> (const_int pow2-1)) */
4337 if (GET_CODE (XEXP (x, 1)) == AND
4338 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4339 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4340 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4341 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4342 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4344 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4346 if (GET_CODE (XEXP (x, 1)) == MULT
4347 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4351 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4352 in2 = XEXP (XEXP (x, 1), 1);
4353 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4357 /* Canonicalize (minus (neg A) (mult B C)) to
4358 (minus (mult (neg B) C) A). */
4359 if (GET_CODE (XEXP (x, 1)) == MULT
4360 && GET_CODE (XEXP (x, 0)) == NEG)
4364 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4365 in2 = XEXP (XEXP (x, 1), 1);
4366 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4367 XEXP (XEXP (x, 0), 0));
4370 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4372 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4373 return gen_binary (MINUS, mode,
4374 gen_binary (MINUS, mode, XEXP (x, 0),
4375 XEXP (XEXP (x, 1), 0)),
4376 XEXP (XEXP (x, 1), 1));
4380 /* If we have (mult (plus A B) C), apply the distributive law and then
4381 the inverse distributive law to see if things simplify. This
4382 occurs mostly in addresses, often when unrolling loops. */
4384 if (GET_CODE (XEXP (x, 0)) == PLUS)
4386 x = apply_distributive_law
4387 (gen_binary (PLUS, mode,
4388 gen_binary (MULT, mode,
4389 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4390 gen_binary (MULT, mode,
4391 XEXP (XEXP (x, 0), 1),
4392 copy_rtx (XEXP (x, 1)))));
4394 if (GET_CODE (x) != MULT)
4397 /* Try simplify a*(b/c) as (a*b)/c. */
4398 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4399 && GET_CODE (XEXP (x, 0)) == DIV)
4401 rtx tem = simplify_binary_operation (MULT, mode,
4402 XEXP (XEXP (x, 0), 0),
4405 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4410 /* If this is a divide by a power of two, treat it as a shift if
4411 its first operand is a shift. */
4412 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4413 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4414 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4415 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4416 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4417 || GET_CODE (XEXP (x, 0)) == ROTATE
4418 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4419 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4423 case GT: case GTU: case GE: case GEU:
4424 case LT: case LTU: case LE: case LEU:
4425 case UNEQ: case LTGT:
4426 case UNGT: case UNGE:
4427 case UNLT: case UNLE:
4428 case UNORDERED: case ORDERED:
4429 /* If the first operand is a condition code, we can't do anything
4431 if (GET_CODE (XEXP (x, 0)) == COMPARE
4432 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4434 && XEXP (x, 0) != cc0_rtx
4438 rtx op0 = XEXP (x, 0);
4439 rtx op1 = XEXP (x, 1);
4440 enum rtx_code new_code;
4442 if (GET_CODE (op0) == COMPARE)
4443 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4445 /* Simplify our comparison, if possible. */
4446 new_code = simplify_comparison (code, &op0, &op1);
4448 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4449 if only the low-order bit is possibly nonzero in X (such as when
4450 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4451 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4452 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4455 Remove any ZERO_EXTRACT we made when thinking this was a
4456 comparison. It may now be simpler to use, e.g., an AND. If a
4457 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4458 the call to make_compound_operation in the SET case. */
4460 if (STORE_FLAG_VALUE == 1
4461 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4462 && op1 == const0_rtx
4463 && mode == GET_MODE (op0)
4464 && nonzero_bits (op0, mode) == 1)
4465 return gen_lowpart_for_combine (mode,
4466 expand_compound_operation (op0));
4468 else if (STORE_FLAG_VALUE == 1
4469 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4470 && op1 == const0_rtx
4471 && mode == GET_MODE (op0)
4472 && (num_sign_bit_copies (op0, mode)
4473 == GET_MODE_BITSIZE (mode)))
4475 op0 = expand_compound_operation (op0);
4476 return simplify_gen_unary (NEG, mode,
4477 gen_lowpart_for_combine (mode, op0),
4481 else if (STORE_FLAG_VALUE == 1
4482 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4483 && op1 == const0_rtx
4484 && mode == GET_MODE (op0)
4485 && nonzero_bits (op0, mode) == 1)
4487 op0 = expand_compound_operation (op0);
4488 return gen_binary (XOR, mode,
4489 gen_lowpart_for_combine (mode, op0),
4493 else if (STORE_FLAG_VALUE == 1
4494 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4495 && op1 == const0_rtx
4496 && mode == GET_MODE (op0)
4497 && (num_sign_bit_copies (op0, mode)
4498 == GET_MODE_BITSIZE (mode)))
4500 op0 = expand_compound_operation (op0);
4501 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4504 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4506 if (STORE_FLAG_VALUE == -1
4507 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4508 && op1 == const0_rtx
4509 && (num_sign_bit_copies (op0, mode)
4510 == GET_MODE_BITSIZE (mode)))
4511 return gen_lowpart_for_combine (mode,
4512 expand_compound_operation (op0));
4514 else if (STORE_FLAG_VALUE == -1
4515 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4516 && op1 == const0_rtx
4517 && mode == GET_MODE (op0)
4518 && nonzero_bits (op0, mode) == 1)
4520 op0 = expand_compound_operation (op0);
4521 return simplify_gen_unary (NEG, mode,
4522 gen_lowpart_for_combine (mode, op0),
4526 else if (STORE_FLAG_VALUE == -1
4527 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4528 && op1 == const0_rtx
4529 && mode == GET_MODE (op0)
4530 && (num_sign_bit_copies (op0, mode)
4531 == GET_MODE_BITSIZE (mode)))
4533 op0 = expand_compound_operation (op0);
4534 return simplify_gen_unary (NOT, mode,
4535 gen_lowpart_for_combine (mode, op0),
4539 /* If X is 0/1, (eq X 0) is X-1. */
4540 else if (STORE_FLAG_VALUE == -1
4541 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4542 && op1 == const0_rtx
4543 && mode == GET_MODE (op0)
4544 && nonzero_bits (op0, mode) == 1)
4546 op0 = expand_compound_operation (op0);
4547 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4550 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4551 one bit that might be nonzero, we can convert (ne x 0) to
4552 (ashift x c) where C puts the bit in the sign bit. Remove any
4553 AND with STORE_FLAG_VALUE when we are done, since we are only
4554 going to test the sign bit. */
4555 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4556 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4557 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4558 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4559 && op1 == const0_rtx
4560 && mode == GET_MODE (op0)
4561 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4563 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4564 expand_compound_operation (op0),
4565 GET_MODE_BITSIZE (mode) - 1 - i);
4566 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4572 /* If the code changed, return a whole new comparison. */
4573 if (new_code != code)
4574 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4576 /* Otherwise, keep this operation, but maybe change its operands.
4577 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4578 SUBST (XEXP (x, 0), op0);
4579 SUBST (XEXP (x, 1), op1);
4584 return simplify_if_then_else (x);
4590 /* If we are processing SET_DEST, we are done. */
4594 return expand_compound_operation (x);
4597 return simplify_set (x);
4602 return simplify_logical (x, last);
4605 /* (abs (neg <foo>)) -> (abs <foo>) */
4606 if (GET_CODE (XEXP (x, 0)) == NEG)
4607 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4609 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4611 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4614 /* If operand is something known to be positive, ignore the ABS. */
4615 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4616 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4617 <= HOST_BITS_PER_WIDE_INT)
4618 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4619 & ((HOST_WIDE_INT) 1
4620 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4624 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4625 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4626 return gen_rtx_NEG (mode, XEXP (x, 0));
4631 /* (ffs (*_extend <X>)) = (ffs <X>) */
4632 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4633 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4634 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4639 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4640 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4641 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4645 /* (float (sign_extend <X>)) = (float <X>). */
4646 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4647 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4655 /* If this is a shift by a constant amount, simplify it. */
4656 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4657 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4658 INTVAL (XEXP (x, 1)));
4660 #ifdef SHIFT_COUNT_TRUNCATED
4661 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4663 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4665 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4674 rtx op0 = XEXP (x, 0);
4675 rtx op1 = XEXP (x, 1);
4678 if (GET_CODE (op1) != PARALLEL)
4680 len = XVECLEN (op1, 0);
4682 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4683 && GET_CODE (op0) == VEC_CONCAT)
4685 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4687 /* Try to find the element in the VEC_CONCAT. */
4690 if (GET_MODE (op0) == GET_MODE (x))
4692 if (GET_CODE (op0) == VEC_CONCAT)
4694 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4695 if (op0_size < offset)
4696 op0 = XEXP (op0, 0);
4700 op0 = XEXP (op0, 1);
4718 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4721 simplify_if_then_else (x)
4724 enum machine_mode mode = GET_MODE (x);
4725 rtx cond = XEXP (x, 0);
4726 rtx true_rtx = XEXP (x, 1);
4727 rtx false_rtx = XEXP (x, 2);
4728 enum rtx_code true_code = GET_CODE (cond);
4729 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4732 enum rtx_code false_code;
4735 /* Simplify storing of the truth value. */
4736 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4737 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4739 /* Also when the truth value has to be reversed. */
4741 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4742 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4746 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4747 in it is being compared against certain values. Get the true and false
4748 comparisons and see if that says anything about the value of each arm. */
4751 && ((false_code = combine_reversed_comparison_code (cond))
4753 && GET_CODE (XEXP (cond, 0)) == REG)
4756 rtx from = XEXP (cond, 0);
4757 rtx true_val = XEXP (cond, 1);
4758 rtx false_val = true_val;
4761 /* If FALSE_CODE is EQ, swap the codes and arms. */
4763 if (false_code == EQ)
4765 swapped = 1, true_code = EQ, false_code = NE;
4766 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4769 /* If we are comparing against zero and the expression being tested has
4770 only a single bit that might be nonzero, that is its value when it is
4771 not equal to zero. Similarly if it is known to be -1 or 0. */
4773 if (true_code == EQ && true_val == const0_rtx
4774 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4775 false_code = EQ, false_val = GEN_INT (nzb);
4776 else if (true_code == EQ && true_val == const0_rtx
4777 && (num_sign_bit_copies (from, GET_MODE (from))
4778 == GET_MODE_BITSIZE (GET_MODE (from))))
4779 false_code = EQ, false_val = constm1_rtx;
4781 /* Now simplify an arm if we know the value of the register in the
4782 branch and it is used in the arm. Be careful due to the potential
4783 of locally-shared RTL. */
4785 if (reg_mentioned_p (from, true_rtx))
4786 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4788 pc_rtx, pc_rtx, 0, 0);
4789 if (reg_mentioned_p (from, false_rtx))
4790 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4792 pc_rtx, pc_rtx, 0, 0);
4794 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4795 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4797 true_rtx = XEXP (x, 1);
4798 false_rtx = XEXP (x, 2);
4799 true_code = GET_CODE (cond);
4802 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4803 reversed, do so to avoid needing two sets of patterns for
4804 subtract-and-branch insns. Similarly if we have a constant in the true
4805 arm, the false arm is the same as the first operand of the comparison, or
4806 the false arm is more complicated than the true arm. */
4809 && combine_reversed_comparison_code (cond) != UNKNOWN
4810 && (true_rtx == pc_rtx
4811 || (CONSTANT_P (true_rtx)
4812 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4813 || true_rtx == const0_rtx
4814 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4815 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4816 || (GET_CODE (true_rtx) == SUBREG
4817 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4818 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4819 || reg_mentioned_p (true_rtx, false_rtx)
4820 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4822 true_code = reversed_comparison_code (cond, NULL);
4824 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4827 SUBST (XEXP (x, 1), false_rtx);
4828 SUBST (XEXP (x, 2), true_rtx);
4830 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4833 /* It is possible that the conditional has been simplified out. */
4834 true_code = GET_CODE (cond);
4835 comparison_p = GET_RTX_CLASS (true_code) == '<';
4838 /* If the two arms are identical, we don't need the comparison. */
4840 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4843 /* Convert a == b ? b : a to "a". */
4844 if (true_code == EQ && ! side_effects_p (cond)
4845 && !HONOR_NANS (mode)
4846 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4847 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4849 else if (true_code == NE && ! side_effects_p (cond)
4850 && !HONOR_NANS (mode)
4851 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4852 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4855 /* Look for cases where we have (abs x) or (neg (abs X)). */
4857 if (GET_MODE_CLASS (mode) == MODE_INT
4858 && GET_CODE (false_rtx) == NEG
4859 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4861 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4862 && ! side_effects_p (true_rtx))
4867 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4871 simplify_gen_unary (NEG, mode,
4872 simplify_gen_unary (ABS, mode, true_rtx, mode),
4878 /* Look for MIN or MAX. */
4880 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4882 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4883 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4884 && ! side_effects_p (cond))
4889 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4892 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4895 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4898 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4903 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4904 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4905 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4906 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4907 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4908 neither 1 or -1, but it isn't worth checking for. */
4910 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4911 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4913 rtx t = make_compound_operation (true_rtx, SET);
4914 rtx f = make_compound_operation (false_rtx, SET);
4915 rtx cond_op0 = XEXP (cond, 0);
4916 rtx cond_op1 = XEXP (cond, 1);
4917 enum rtx_code op = NIL, extend_op = NIL;
4918 enum machine_mode m = mode;
4919 rtx z = 0, c1 = NULL_RTX;
4921 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4922 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4923 || GET_CODE (t) == ASHIFT
4924 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4925 && rtx_equal_p (XEXP (t, 0), f))
4926 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4928 /* If an identity-zero op is commutative, check whether there
4929 would be a match if we swapped the operands. */
4930 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4931 || GET_CODE (t) == XOR)
4932 && rtx_equal_p (XEXP (t, 1), f))
4933 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4934 else if (GET_CODE (t) == SIGN_EXTEND
4935 && (GET_CODE (XEXP (t, 0)) == PLUS
4936 || GET_CODE (XEXP (t, 0)) == MINUS
4937 || GET_CODE (XEXP (t, 0)) == IOR
4938 || GET_CODE (XEXP (t, 0)) == XOR
4939 || GET_CODE (XEXP (t, 0)) == ASHIFT
4940 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4941 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4942 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4943 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4944 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4945 && (num_sign_bit_copies (f, GET_MODE (f))
4947 (GET_MODE_BITSIZE (mode)
4948 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4950 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4951 extend_op = SIGN_EXTEND;
4952 m = GET_MODE (XEXP (t, 0));
4954 else if (GET_CODE (t) == SIGN_EXTEND
4955 && (GET_CODE (XEXP (t, 0)) == PLUS
4956 || GET_CODE (XEXP (t, 0)) == IOR
4957 || GET_CODE (XEXP (t, 0)) == XOR)
4958 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4959 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4960 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4961 && (num_sign_bit_copies (f, GET_MODE (f))
4963 (GET_MODE_BITSIZE (mode)
4964 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4966 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4967 extend_op = SIGN_EXTEND;
4968 m = GET_MODE (XEXP (t, 0));
4970 else if (GET_CODE (t) == ZERO_EXTEND
4971 && (GET_CODE (XEXP (t, 0)) == PLUS
4972 || GET_CODE (XEXP (t, 0)) == MINUS
4973 || GET_CODE (XEXP (t, 0)) == IOR
4974 || GET_CODE (XEXP (t, 0)) == XOR
4975 || GET_CODE (XEXP (t, 0)) == ASHIFT
4976 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4977 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4978 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4979 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4980 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4981 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4982 && ((nonzero_bits (f, GET_MODE (f))
4983 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4986 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4987 extend_op = ZERO_EXTEND;
4988 m = GET_MODE (XEXP (t, 0));
4990 else if (GET_CODE (t) == ZERO_EXTEND
4991 && (GET_CODE (XEXP (t, 0)) == PLUS
4992 || GET_CODE (XEXP (t, 0)) == IOR
4993 || GET_CODE (XEXP (t, 0)) == XOR)
4994 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4995 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4996 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4997 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4998 && ((nonzero_bits (f, GET_MODE (f))
4999 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5002 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5003 extend_op = ZERO_EXTEND;
5004 m = GET_MODE (XEXP (t, 0));
5009 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5010 pc_rtx, pc_rtx, 0, 0);
5011 temp = gen_binary (MULT, m, temp,
5012 gen_binary (MULT, m, c1, const_true_rtx));
5013 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5014 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
5016 if (extend_op != NIL)
5017 temp = simplify_gen_unary (extend_op, mode, temp, m);
5023 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5024 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5025 negation of a single bit, we can convert this operation to a shift. We
5026 can actually do this more generally, but it doesn't seem worth it. */
5028 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5029 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5030 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5031 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5032 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5033 == GET_MODE_BITSIZE (mode))
5034 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5036 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5037 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5042 /* Simplify X, a SET expression. Return the new expression. */
5048 rtx src = SET_SRC (x);
5049 rtx dest = SET_DEST (x);
5050 enum machine_mode mode
5051 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5055 /* (set (pc) (return)) gets written as (return). */
5056 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5059 /* Now that we know for sure which bits of SRC we are using, see if we can
5060 simplify the expression for the object knowing that we only need the
5063 if (GET_MODE_CLASS (mode) == MODE_INT
5064 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5066 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5067 SUBST (SET_SRC (x), src);
5070 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5071 the comparison result and try to simplify it unless we already have used
5072 undobuf.other_insn. */
5073 if ((GET_MODE_CLASS (mode) == MODE_CC
5074 || GET_CODE (src) == COMPARE
5076 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5077 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5078 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5079 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5081 enum rtx_code old_code = GET_CODE (*cc_use);
5082 enum rtx_code new_code;
5084 int other_changed = 0;
5085 enum machine_mode compare_mode = GET_MODE (dest);
5086 enum machine_mode tmp_mode;
5088 if (GET_CODE (src) == COMPARE)
5089 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5091 op0 = src, op1 = const0_rtx;
5093 /* Check whether the comparison is known at compile time. */
5094 if (GET_MODE (op0) != VOIDmode)
5095 tmp_mode = GET_MODE (op0);
5096 else if (GET_MODE (op1) != VOIDmode)
5097 tmp_mode = GET_MODE (op1);
5099 tmp_mode = compare_mode;
5100 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5101 if (tmp != NULL_RTX)
5103 rtx pat = PATTERN (other_insn);
5104 undobuf.other_insn = other_insn;
5105 SUBST (*cc_use, tmp);
5107 /* Attempt to simplify CC user. */
5108 if (GET_CODE (pat) == SET)
5110 rtx new = simplify_rtx (SET_SRC (pat));
5111 if (new != NULL_RTX)
5112 SUBST (SET_SRC (pat), new);
5115 /* Convert X into a no-op move. */
5116 SUBST (SET_DEST (x), pc_rtx);
5117 SUBST (SET_SRC (x), pc_rtx);
5121 /* Simplify our comparison, if possible. */
5122 new_code = simplify_comparison (old_code, &op0, &op1);
5124 #ifdef EXTRA_CC_MODES
5125 /* If this machine has CC modes other than CCmode, check to see if we
5126 need to use a different CC mode here. */
5127 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5128 #endif /* EXTRA_CC_MODES */
5130 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5131 /* If the mode changed, we have to change SET_DEST, the mode in the
5132 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5133 a hard register, just build new versions with the proper mode. If it
5134 is a pseudo, we lose unless it is only time we set the pseudo, in
5135 which case we can safely change its mode. */
5136 if (compare_mode != GET_MODE (dest))
5138 unsigned int regno = REGNO (dest);
5139 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5141 if (regno < FIRST_PSEUDO_REGISTER
5142 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5144 if (regno >= FIRST_PSEUDO_REGISTER)
5145 SUBST (regno_reg_rtx[regno], new_dest);
5147 SUBST (SET_DEST (x), new_dest);
5148 SUBST (XEXP (*cc_use, 0), new_dest);
5156 /* If the code changed, we have to build a new comparison in
5157 undobuf.other_insn. */
5158 if (new_code != old_code)
5160 unsigned HOST_WIDE_INT mask;
5162 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5165 /* If the only change we made was to change an EQ into an NE or
5166 vice versa, OP0 has only one bit that might be nonzero, and OP1
5167 is zero, check if changing the user of the condition code will
5168 produce a valid insn. If it won't, we can keep the original code
5169 in that insn by surrounding our operation with an XOR. */
5171 if (((old_code == NE && new_code == EQ)
5172 || (old_code == EQ && new_code == NE))
5173 && ! other_changed && op1 == const0_rtx
5174 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5175 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5177 rtx pat = PATTERN (other_insn), note = 0;
5179 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5180 && ! check_asm_operands (pat)))
5182 PUT_CODE (*cc_use, old_code);
5185 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5193 undobuf.other_insn = other_insn;
5196 /* If we are now comparing against zero, change our source if
5197 needed. If we do not use cc0, we always have a COMPARE. */
5198 if (op1 == const0_rtx && dest == cc0_rtx)
5200 SUBST (SET_SRC (x), op0);
5206 /* Otherwise, if we didn't previously have a COMPARE in the
5207 correct mode, we need one. */
5208 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5210 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5215 /* Otherwise, update the COMPARE if needed. */
5216 SUBST (XEXP (src, 0), op0);
5217 SUBST (XEXP (src, 1), op1);
5222 /* Get SET_SRC in a form where we have placed back any
5223 compound expressions. Then do the checks below. */
5224 src = make_compound_operation (src, SET);
5225 SUBST (SET_SRC (x), src);
5228 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5229 and X being a REG or (subreg (reg)), we may be able to convert this to
5230 (set (subreg:m2 x) (op)).
5232 We can always do this if M1 is narrower than M2 because that means that
5233 we only care about the low bits of the result.
5235 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5236 perform a narrower operation than requested since the high-order bits will
5237 be undefined. On machine where it is defined, this transformation is safe
5238 as long as M1 and M2 have the same number of words. */
5240 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5241 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5242 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5244 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5245 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5246 #ifndef WORD_REGISTER_OPERATIONS
5247 && (GET_MODE_SIZE (GET_MODE (src))
5248 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5250 #ifdef CANNOT_CHANGE_MODE_CLASS
5251 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5252 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5253 GET_MODE (SUBREG_REG (src)),
5256 && (GET_CODE (dest) == REG
5257 || (GET_CODE (dest) == SUBREG
5258 && GET_CODE (SUBREG_REG (dest)) == REG)))
5260 SUBST (SET_DEST (x),
5261 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5263 SUBST (SET_SRC (x), SUBREG_REG (src));
5265 src = SET_SRC (x), dest = SET_DEST (x);
5269 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5272 && GET_CODE (src) == SUBREG
5273 && subreg_lowpart_p (src)
5274 && (GET_MODE_BITSIZE (GET_MODE (src))
5275 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5277 rtx inner = SUBREG_REG (src);
5278 enum machine_mode inner_mode = GET_MODE (inner);
5280 /* Here we make sure that we don't have a sign bit on. */
5281 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5282 && (nonzero_bits (inner, inner_mode)
5283 < ((unsigned HOST_WIDE_INT) 1
5284 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5286 SUBST (SET_SRC (x), inner);
5292 #ifdef LOAD_EXTEND_OP
5293 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5294 would require a paradoxical subreg. Replace the subreg with a
5295 zero_extend to avoid the reload that would otherwise be required. */
5297 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5298 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5299 && SUBREG_BYTE (src) == 0
5300 && (GET_MODE_SIZE (GET_MODE (src))
5301 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5302 && GET_CODE (SUBREG_REG (src)) == MEM)
5305 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5306 GET_MODE (src), SUBREG_REG (src)));
5312 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5313 are comparing an item known to be 0 or -1 against 0, use a logical
5314 operation instead. Check for one of the arms being an IOR of the other
5315 arm with some value. We compute three terms to be IOR'ed together. In
5316 practice, at most two will be nonzero. Then we do the IOR's. */
5318 if (GET_CODE (dest) != PC
5319 && GET_CODE (src) == IF_THEN_ELSE
5320 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5321 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5322 && XEXP (XEXP (src, 0), 1) == const0_rtx
5323 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5324 #ifdef HAVE_conditional_move
5325 && ! can_conditionally_move_p (GET_MODE (src))
5327 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5328 GET_MODE (XEXP (XEXP (src, 0), 0)))
5329 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5330 && ! side_effects_p (src))
5332 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5333 ? XEXP (src, 1) : XEXP (src, 2));
5334 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5335 ? XEXP (src, 2) : XEXP (src, 1));
5336 rtx term1 = const0_rtx, term2, term3;
5338 if (GET_CODE (true_rtx) == IOR
5339 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5340 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5341 else if (GET_CODE (true_rtx) == IOR
5342 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5343 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5344 else if (GET_CODE (false_rtx) == IOR
5345 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5346 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5347 else if (GET_CODE (false_rtx) == IOR
5348 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5349 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5351 term2 = gen_binary (AND, GET_MODE (src),
5352 XEXP (XEXP (src, 0), 0), true_rtx);
5353 term3 = gen_binary (AND, GET_MODE (src),
5354 simplify_gen_unary (NOT, GET_MODE (src),
5355 XEXP (XEXP (src, 0), 0),
5360 gen_binary (IOR, GET_MODE (src),
5361 gen_binary (IOR, GET_MODE (src), term1, term2),
5367 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5368 whole thing fail. */
5369 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5371 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5374 /* Convert this into a field assignment operation, if possible. */
5375 return make_field_assignment (x);
5378 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5379 result. LAST is nonzero if this is the last retry. */
5382 simplify_logical (x, last)
5386 enum machine_mode mode = GET_MODE (x);
5387 rtx op0 = XEXP (x, 0);
5388 rtx op1 = XEXP (x, 1);
5391 switch (GET_CODE (x))
5394 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5395 insn (and may simplify more). */
5396 if (GET_CODE (op0) == XOR
5397 && rtx_equal_p (XEXP (op0, 0), op1)
5398 && ! side_effects_p (op1))
5399 x = gen_binary (AND, mode,
5400 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5403 if (GET_CODE (op0) == XOR
5404 && rtx_equal_p (XEXP (op0, 1), op1)
5405 && ! side_effects_p (op1))
5406 x = gen_binary (AND, mode,
5407 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5410 /* Similarly for (~(A ^ B)) & A. */
5411 if (GET_CODE (op0) == NOT
5412 && GET_CODE (XEXP (op0, 0)) == XOR
5413 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5414 && ! side_effects_p (op1))
5415 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5417 if (GET_CODE (op0) == NOT
5418 && GET_CODE (XEXP (op0, 0)) == XOR
5419 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5420 && ! side_effects_p (op1))
5421 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5423 /* We can call simplify_and_const_int only if we don't lose
5424 any (sign) bits when converting INTVAL (op1) to
5425 "unsigned HOST_WIDE_INT". */
5426 if (GET_CODE (op1) == CONST_INT
5427 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5428 || INTVAL (op1) > 0))
5430 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5432 /* If we have (ior (and (X C1) C2)) and the next restart would be
5433 the last, simplify this by making C1 as small as possible
5436 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5437 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5438 && GET_CODE (op1) == CONST_INT)
5439 return gen_binary (IOR, mode,
5440 gen_binary (AND, mode, XEXP (op0, 0),
5441 GEN_INT (INTVAL (XEXP (op0, 1))
5442 & ~INTVAL (op1))), op1);
5444 if (GET_CODE (x) != AND)
5447 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5448 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5449 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5452 /* Convert (A | B) & A to A. */
5453 if (GET_CODE (op0) == IOR
5454 && (rtx_equal_p (XEXP (op0, 0), op1)
5455 || rtx_equal_p (XEXP (op0, 1), op1))
5456 && ! side_effects_p (XEXP (op0, 0))
5457 && ! side_effects_p (XEXP (op0, 1)))
5460 /* In the following group of tests (and those in case IOR below),
5461 we start with some combination of logical operations and apply
5462 the distributive law followed by the inverse distributive law.
5463 Most of the time, this results in no change. However, if some of
5464 the operands are the same or inverses of each other, simplifications
5467 For example, (and (ior A B) (not B)) can occur as the result of
5468 expanding a bit field assignment. When we apply the distributive
5469 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5470 which then simplifies to (and (A (not B))).
5472 If we have (and (ior A B) C), apply the distributive law and then
5473 the inverse distributive law to see if things simplify. */
5475 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5477 x = apply_distributive_law
5478 (gen_binary (GET_CODE (op0), mode,
5479 gen_binary (AND, mode, XEXP (op0, 0), op1),
5480 gen_binary (AND, mode, XEXP (op0, 1),
5482 if (GET_CODE (x) != AND)
5486 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5487 return apply_distributive_law
5488 (gen_binary (GET_CODE (op1), mode,
5489 gen_binary (AND, mode, XEXP (op1, 0), op0),
5490 gen_binary (AND, mode, XEXP (op1, 1),
5493 /* Similarly, taking advantage of the fact that
5494 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5496 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5497 return apply_distributive_law
5498 (gen_binary (XOR, mode,
5499 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5500 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5503 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5504 return apply_distributive_law
5505 (gen_binary (XOR, mode,
5506 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5507 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5511 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5512 if (GET_CODE (op1) == CONST_INT
5513 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5514 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5517 /* Convert (A & B) | A to A. */
5518 if (GET_CODE (op0) == AND
5519 && (rtx_equal_p (XEXP (op0, 0), op1)
5520 || rtx_equal_p (XEXP (op0, 1), op1))
5521 && ! side_effects_p (XEXP (op0, 0))
5522 && ! side_effects_p (XEXP (op0, 1)))
5525 /* If we have (ior (and A B) C), apply the distributive law and then
5526 the inverse distributive law to see if things simplify. */
5528 if (GET_CODE (op0) == AND)
5530 x = apply_distributive_law
5531 (gen_binary (AND, mode,
5532 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5533 gen_binary (IOR, mode, XEXP (op0, 1),
5536 if (GET_CODE (x) != IOR)
5540 if (GET_CODE (op1) == AND)
5542 x = apply_distributive_law
5543 (gen_binary (AND, mode,
5544 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5545 gen_binary (IOR, mode, XEXP (op1, 1),
5548 if (GET_CODE (x) != IOR)
5552 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5553 mode size to (rotate A CX). */
5555 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5556 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5557 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5558 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5559 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5560 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5561 == GET_MODE_BITSIZE (mode)))
5562 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5563 (GET_CODE (op0) == ASHIFT
5564 ? XEXP (op0, 1) : XEXP (op1, 1)));
5566 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5567 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5568 does not affect any of the bits in OP1, it can really be done
5569 as a PLUS and we can associate. We do this by seeing if OP1
5570 can be safely shifted left C bits. */
5571 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5572 && GET_CODE (XEXP (op0, 0)) == PLUS
5573 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5574 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5575 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5577 int count = INTVAL (XEXP (op0, 1));
5578 HOST_WIDE_INT mask = INTVAL (op1) << count;
5580 if (mask >> count == INTVAL (op1)
5581 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5583 SUBST (XEXP (XEXP (op0, 0), 1),
5584 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5591 /* If we are XORing two things that have no bits in common,
5592 convert them into an IOR. This helps to detect rotation encoded
5593 using those methods and possibly other simplifications. */
5595 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5596 && (nonzero_bits (op0, mode)
5597 & nonzero_bits (op1, mode)) == 0)
5598 return (gen_binary (IOR, mode, op0, op1));
5600 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5601 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5604 int num_negated = 0;
5606 if (GET_CODE (op0) == NOT)
5607 num_negated++, op0 = XEXP (op0, 0);
5608 if (GET_CODE (op1) == NOT)
5609 num_negated++, op1 = XEXP (op1, 0);
5611 if (num_negated == 2)
5613 SUBST (XEXP (x, 0), op0);
5614 SUBST (XEXP (x, 1), op1);
5616 else if (num_negated == 1)
5618 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5622 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5623 correspond to a machine insn or result in further simplifications
5624 if B is a constant. */
5626 if (GET_CODE (op0) == AND
5627 && rtx_equal_p (XEXP (op0, 1), op1)
5628 && ! side_effects_p (op1))
5629 return gen_binary (AND, mode,
5630 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5633 else if (GET_CODE (op0) == AND
5634 && rtx_equal_p (XEXP (op0, 0), op1)
5635 && ! side_effects_p (op1))
5636 return gen_binary (AND, mode,
5637 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5640 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5641 comparison if STORE_FLAG_VALUE is 1. */
5642 if (STORE_FLAG_VALUE == 1
5643 && op1 == const1_rtx
5644 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5645 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5649 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5650 is (lt foo (const_int 0)), so we can perform the above
5651 simplification if STORE_FLAG_VALUE is 1. */
5653 if (STORE_FLAG_VALUE == 1
5654 && op1 == const1_rtx
5655 && GET_CODE (op0) == LSHIFTRT
5656 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5657 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5658 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5660 /* (xor (comparison foo bar) (const_int sign-bit))
5661 when STORE_FLAG_VALUE is the sign bit. */
5662 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5663 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5664 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5665 && op1 == const_true_rtx
5666 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5667 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5680 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5681 operations" because they can be replaced with two more basic operations.
5682 ZERO_EXTEND is also considered "compound" because it can be replaced with
5683 an AND operation, which is simpler, though only one operation.
5685 The function expand_compound_operation is called with an rtx expression
5686 and will convert it to the appropriate shifts and AND operations,
5687 simplifying at each stage.
5689 The function make_compound_operation is called to convert an expression
5690 consisting of shifts and ANDs into the equivalent compound expression.
5691 It is the inverse of this function, loosely speaking. */
5694 expand_compound_operation (x)
5697 unsigned HOST_WIDE_INT pos = 0, len;
5699 unsigned int modewidth;
5702 switch (GET_CODE (x))
5707 /* We can't necessarily use a const_int for a multiword mode;
5708 it depends on implicitly extending the value.
5709 Since we don't know the right way to extend it,
5710 we can't tell whether the implicit way is right.
5712 Even for a mode that is no wider than a const_int,
5713 we can't win, because we need to sign extend one of its bits through
5714 the rest of it, and we don't know which bit. */
5715 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5718 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5719 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5720 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5721 reloaded. If not for that, MEM's would very rarely be safe.
5723 Reject MODEs bigger than a word, because we might not be able
5724 to reference a two-register group starting with an arbitrary register
5725 (and currently gen_lowpart might crash for a SUBREG). */
5727 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5730 /* Reject MODEs that aren't scalar integers because turning vector
5731 or complex modes into shifts causes problems. */
5733 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5736 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5737 /* If the inner object has VOIDmode (the only way this can happen
5738 is if it is an ASM_OPERANDS), we can't do anything since we don't
5739 know how much masking to do. */
5748 /* If the operand is a CLOBBER, just return it. */
5749 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5752 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5753 || GET_CODE (XEXP (x, 2)) != CONST_INT
5754 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5757 /* Reject MODEs that aren't scalar integers because turning vector
5758 or complex modes into shifts causes problems. */
5760 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5763 len = INTVAL (XEXP (x, 1));
5764 pos = INTVAL (XEXP (x, 2));
5766 /* If this goes outside the object being extracted, replace the object
5767 with a (use (mem ...)) construct that only combine understands
5768 and is used only for this purpose. */
5769 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5770 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5772 if (BITS_BIG_ENDIAN)
5773 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5780 /* Convert sign extension to zero extension, if we know that the high
5781 bit is not set, as this is easier to optimize. It will be converted
5782 back to cheaper alternative in make_extraction. */
5783 if (GET_CODE (x) == SIGN_EXTEND
5784 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5785 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5786 & ~(((unsigned HOST_WIDE_INT)
5787 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5791 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5792 return expand_compound_operation (temp);
5795 /* We can optimize some special cases of ZERO_EXTEND. */
5796 if (GET_CODE (x) == ZERO_EXTEND)
5798 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5799 know that the last value didn't have any inappropriate bits
5801 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5802 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5803 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5804 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5805 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5806 return XEXP (XEXP (x, 0), 0);
5808 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5809 if (GET_CODE (XEXP (x, 0)) == SUBREG
5810 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5811 && subreg_lowpart_p (XEXP (x, 0))
5812 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5813 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5814 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5815 return SUBREG_REG (XEXP (x, 0));
5817 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5818 is a comparison and STORE_FLAG_VALUE permits. This is like
5819 the first case, but it works even when GET_MODE (x) is larger
5820 than HOST_WIDE_INT. */
5821 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5822 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5823 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5824 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5825 <= HOST_BITS_PER_WIDE_INT)
5826 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5827 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5828 return XEXP (XEXP (x, 0), 0);
5830 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5831 if (GET_CODE (XEXP (x, 0)) == SUBREG
5832 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5833 && subreg_lowpart_p (XEXP (x, 0))
5834 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5835 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5836 <= HOST_BITS_PER_WIDE_INT)
5837 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5838 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5839 return SUBREG_REG (XEXP (x, 0));
5843 /* If we reach here, we want to return a pair of shifts. The inner
5844 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5845 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5846 logical depending on the value of UNSIGNEDP.
5848 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5849 converted into an AND of a shift.
5851 We must check for the case where the left shift would have a negative
5852 count. This can happen in a case like (x >> 31) & 255 on machines
5853 that can't shift by a constant. On those machines, we would first
5854 combine the shift with the AND to produce a variable-position
5855 extraction. Then the constant of 31 would be substituted in to produce
5856 a such a position. */
5858 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5859 if (modewidth + len >= pos)
5860 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5862 simplify_shift_const (NULL_RTX, ASHIFT,
5865 modewidth - pos - len),
5868 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5869 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5870 simplify_shift_const (NULL_RTX, LSHIFTRT,
5873 ((HOST_WIDE_INT) 1 << len) - 1);
5875 /* Any other cases we can't handle. */
5878 /* If we couldn't do this for some reason, return the original
5880 if (GET_CODE (tem) == CLOBBER)
5886 /* X is a SET which contains an assignment of one object into
5887 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5888 or certain SUBREGS). If possible, convert it into a series of
5891 We half-heartedly support variable positions, but do not at all
5892 support variable lengths. */
5895 expand_field_assignment (x)
5899 rtx pos; /* Always counts from low bit. */
5902 enum machine_mode compute_mode;
5904 /* Loop until we find something we can't simplify. */
5907 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5908 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5910 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5911 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5912 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5914 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5915 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5917 inner = XEXP (SET_DEST (x), 0);
5918 len = INTVAL (XEXP (SET_DEST (x), 1));
5919 pos = XEXP (SET_DEST (x), 2);
5921 /* If the position is constant and spans the width of INNER,
5922 surround INNER with a USE to indicate this. */
5923 if (GET_CODE (pos) == CONST_INT
5924 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5925 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5927 if (BITS_BIG_ENDIAN)
5929 if (GET_CODE (pos) == CONST_INT)
5930 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5932 else if (GET_CODE (pos) == MINUS
5933 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5934 && (INTVAL (XEXP (pos, 1))
5935 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5936 /* If position is ADJUST - X, new position is X. */
5937 pos = XEXP (pos, 0);
5939 pos = gen_binary (MINUS, GET_MODE (pos),
5940 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5946 /* A SUBREG between two modes that occupy the same numbers of words
5947 can be done by moving the SUBREG to the source. */
5948 else if (GET_CODE (SET_DEST (x)) == SUBREG
5949 /* We need SUBREGs to compute nonzero_bits properly. */
5950 && nonzero_sign_valid
5951 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5952 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5953 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5954 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5956 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5957 gen_lowpart_for_combine
5958 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5965 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5966 inner = SUBREG_REG (inner);
5968 compute_mode = GET_MODE (inner);
5970 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5971 if (! SCALAR_INT_MODE_P (compute_mode))
5973 enum machine_mode imode;
5975 /* Don't do anything for vector or complex integral types. */
5976 if (! FLOAT_MODE_P (compute_mode))
5979 /* Try to find an integral mode to pun with. */
5980 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5981 if (imode == BLKmode)
5984 compute_mode = imode;
5985 inner = gen_lowpart_for_combine (imode, inner);
5988 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5989 if (len < HOST_BITS_PER_WIDE_INT)
5990 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5994 /* Now compute the equivalent expression. Make a copy of INNER
5995 for the SET_DEST in case it is a MEM into which we will substitute;
5996 we don't want shared RTL in that case. */
5998 (VOIDmode, copy_rtx (inner),
5999 gen_binary (IOR, compute_mode,
6000 gen_binary (AND, compute_mode,
6001 simplify_gen_unary (NOT, compute_mode,
6007 gen_binary (ASHIFT, compute_mode,
6008 gen_binary (AND, compute_mode,
6009 gen_lowpart_for_combine
6010 (compute_mode, SET_SRC (x)),
6018 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6019 it is an RTX that represents a variable starting position; otherwise,
6020 POS is the (constant) starting bit position (counted from the LSB).
6022 INNER may be a USE. This will occur when we started with a bitfield
6023 that went outside the boundary of the object in memory, which is
6024 allowed on most machines. To isolate this case, we produce a USE
6025 whose mode is wide enough and surround the MEM with it. The only
6026 code that understands the USE is this routine. If it is not removed,
6027 it will cause the resulting insn not to match.
6029 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6032 IN_DEST is nonzero if this is a reference in the destination of a
6033 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6034 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6037 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6038 ZERO_EXTRACT should be built even for bits starting at bit 0.
6040 MODE is the desired mode of the result (if IN_DEST == 0).
6042 The result is an RTX for the extraction or NULL_RTX if the target
6046 make_extraction (mode, inner, pos, pos_rtx, len,
6047 unsignedp, in_dest, in_compare)
6048 enum machine_mode mode;
6052 unsigned HOST_WIDE_INT len;
6054 int in_dest, in_compare;
6056 /* This mode describes the size of the storage area
6057 to fetch the overall value from. Within that, we
6058 ignore the POS lowest bits, etc. */
6059 enum machine_mode is_mode = GET_MODE (inner);
6060 enum machine_mode inner_mode;
6061 enum machine_mode wanted_inner_mode = byte_mode;
6062 enum machine_mode wanted_inner_reg_mode = word_mode;
6063 enum machine_mode pos_mode = word_mode;
6064 enum machine_mode extraction_mode = word_mode;
6065 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6068 rtx orig_pos_rtx = pos_rtx;
6069 HOST_WIDE_INT orig_pos;
6071 /* Get some information about INNER and get the innermost object. */
6072 if (GET_CODE (inner) == USE)
6073 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6074 /* We don't need to adjust the position because we set up the USE
6075 to pretend that it was a full-word object. */
6076 spans_byte = 1, inner = XEXP (inner, 0);
6077 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6079 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6080 consider just the QI as the memory to extract from.
6081 The subreg adds or removes high bits; its mode is
6082 irrelevant to the meaning of this extraction,
6083 since POS and LEN count from the lsb. */
6084 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6085 is_mode = GET_MODE (SUBREG_REG (inner));
6086 inner = SUBREG_REG (inner);
6088 else if (GET_CODE (inner) == ASHIFT
6089 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6090 && pos_rtx == 0 && pos == 0
6091 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6093 /* We're extracting the least significant bits of an rtx
6094 (ashift X (const_int C)), where LEN > C. Extract the
6095 least significant (LEN - C) bits of X, giving an rtx
6096 whose mode is MODE, then shift it left C times. */
6097 new = make_extraction (mode, XEXP (inner, 0),
6098 0, 0, len - INTVAL (XEXP (inner, 1)),
6099 unsignedp, in_dest, in_compare);
6101 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6104 inner_mode = GET_MODE (inner);
6106 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6107 pos = INTVAL (pos_rtx), pos_rtx = 0;
6109 /* See if this can be done without an extraction. We never can if the
6110 width of the field is not the same as that of some integer mode. For
6111 registers, we can only avoid the extraction if the position is at the
6112 low-order bit and this is either not in the destination or we have the
6113 appropriate STRICT_LOW_PART operation available.
6115 For MEM, we can avoid an extract if the field starts on an appropriate
6116 boundary and we can change the mode of the memory reference. However,
6117 we cannot directly access the MEM if we have a USE and the underlying
6118 MEM is not TMODE. This combination means that MEM was being used in a
6119 context where bits outside its mode were being referenced; that is only
6120 valid in bit-field insns. */
6122 if (tmode != BLKmode
6123 && ! (spans_byte && inner_mode != tmode)
6124 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6125 && GET_CODE (inner) != MEM
6127 || (GET_CODE (inner) == REG
6128 && have_insn_for (STRICT_LOW_PART, tmode))))
6129 || (GET_CODE (inner) == MEM && pos_rtx == 0
6131 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6132 : BITS_PER_UNIT)) == 0
6133 /* We can't do this if we are widening INNER_MODE (it
6134 may not be aligned, for one thing). */
6135 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6136 && (inner_mode == tmode
6137 || (! mode_dependent_address_p (XEXP (inner, 0))
6138 && ! MEM_VOLATILE_P (inner))))))
6140 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6141 field. If the original and current mode are the same, we need not
6142 adjust the offset. Otherwise, we do if bytes big endian.
6144 If INNER is not a MEM, get a piece consisting of just the field
6145 of interest (in this case POS % BITS_PER_WORD must be 0). */
6147 if (GET_CODE (inner) == MEM)
6149 HOST_WIDE_INT offset;
6151 /* POS counts from lsb, but make OFFSET count in memory order. */
6152 if (BYTES_BIG_ENDIAN)
6153 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6155 offset = pos / BITS_PER_UNIT;
6157 new = adjust_address_nv (inner, tmode, offset);
6159 else if (GET_CODE (inner) == REG)
6161 /* We can't call gen_lowpart_for_combine here since we always want
6162 a SUBREG and it would sometimes return a new hard register. */
6163 if (tmode != inner_mode)
6165 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6167 if (WORDS_BIG_ENDIAN
6168 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6169 final_word = ((GET_MODE_SIZE (inner_mode)
6170 - GET_MODE_SIZE (tmode))
6171 / UNITS_PER_WORD) - final_word;
6173 final_word *= UNITS_PER_WORD;
6174 if (BYTES_BIG_ENDIAN &&
6175 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6176 final_word += (GET_MODE_SIZE (inner_mode)
6177 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6179 /* Avoid creating invalid subregs, for example when
6180 simplifying (x>>32)&255. */
6181 if (final_word >= GET_MODE_SIZE (inner_mode))
6184 new = gen_rtx_SUBREG (tmode, inner, final_word);
6190 new = force_to_mode (inner, tmode,
6191 len >= HOST_BITS_PER_WIDE_INT
6192 ? ~(unsigned HOST_WIDE_INT) 0
6193 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6196 /* If this extraction is going into the destination of a SET,
6197 make a STRICT_LOW_PART unless we made a MEM. */
6200 return (GET_CODE (new) == MEM ? new
6201 : (GET_CODE (new) != SUBREG
6202 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6203 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6208 if (GET_CODE (new) == CONST_INT)
6209 return gen_int_mode (INTVAL (new), mode);
6211 /* If we know that no extraneous bits are set, and that the high
6212 bit is not set, convert the extraction to the cheaper of
6213 sign and zero extension, that are equivalent in these cases. */
6214 if (flag_expensive_optimizations
6215 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6216 && ((nonzero_bits (new, tmode)
6217 & ~(((unsigned HOST_WIDE_INT)
6218 GET_MODE_MASK (tmode))
6222 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6223 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6225 /* Prefer ZERO_EXTENSION, since it gives more information to
6227 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6232 /* Otherwise, sign- or zero-extend unless we already are in the
6235 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6239 /* Unless this is a COMPARE or we have a funny memory reference,
6240 don't do anything with zero-extending field extracts starting at
6241 the low-order bit since they are simple AND operations. */
6242 if (pos_rtx == 0 && pos == 0 && ! in_dest
6243 && ! in_compare && ! spans_byte && unsignedp)
6246 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6247 we would be spanning bytes or if the position is not a constant and the
6248 length is not 1. In all other cases, we would only be going outside
6249 our object in cases when an original shift would have been
6251 if (! spans_byte && GET_CODE (inner) == MEM
6252 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6253 || (pos_rtx != 0 && len != 1)))
6256 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6257 and the mode for the result. */
6258 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6260 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6261 pos_mode = mode_for_extraction (EP_insv, 2);
6262 extraction_mode = mode_for_extraction (EP_insv, 3);
6265 if (! in_dest && unsignedp
6266 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6268 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6269 pos_mode = mode_for_extraction (EP_extzv, 3);
6270 extraction_mode = mode_for_extraction (EP_extzv, 0);
6273 if (! in_dest && ! unsignedp
6274 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6276 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6277 pos_mode = mode_for_extraction (EP_extv, 3);
6278 extraction_mode = mode_for_extraction (EP_extv, 0);
6281 /* Never narrow an object, since that might not be safe. */
6283 if (mode != VOIDmode
6284 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6285 extraction_mode = mode;
6287 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6288 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6289 pos_mode = GET_MODE (pos_rtx);
6291 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6292 if we have to change the mode of memory and cannot, the desired mode is
6294 if (GET_CODE (inner) != MEM)
6295 wanted_inner_mode = wanted_inner_reg_mode;
6296 else if (inner_mode != wanted_inner_mode
6297 && (mode_dependent_address_p (XEXP (inner, 0))
6298 || MEM_VOLATILE_P (inner)))
6299 wanted_inner_mode = extraction_mode;
6303 if (BITS_BIG_ENDIAN)
6305 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6306 BITS_BIG_ENDIAN style. If position is constant, compute new
6307 position. Otherwise, build subtraction.
6308 Note that POS is relative to the mode of the original argument.
6309 If it's a MEM we need to recompute POS relative to that.
6310 However, if we're extracting from (or inserting into) a register,
6311 we want to recompute POS relative to wanted_inner_mode. */
6312 int width = (GET_CODE (inner) == MEM
6313 ? GET_MODE_BITSIZE (is_mode)
6314 : GET_MODE_BITSIZE (wanted_inner_mode));
6317 pos = width - len - pos;
6320 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6321 /* POS may be less than 0 now, but we check for that below.
6322 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6325 /* If INNER has a wider mode, make it smaller. If this is a constant
6326 extract, try to adjust the byte to point to the byte containing
6328 if (wanted_inner_mode != VOIDmode
6329 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6330 && ((GET_CODE (inner) == MEM
6331 && (inner_mode == wanted_inner_mode
6332 || (! mode_dependent_address_p (XEXP (inner, 0))
6333 && ! MEM_VOLATILE_P (inner))))))
6337 /* The computations below will be correct if the machine is big
6338 endian in both bits and bytes or little endian in bits and bytes.
6339 If it is mixed, we must adjust. */
6341 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6342 adjust OFFSET to compensate. */
6343 if (BYTES_BIG_ENDIAN
6345 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6346 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6348 /* If this is a constant position, we can move to the desired byte. */
6351 offset += pos / BITS_PER_UNIT;
6352 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6355 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6357 && is_mode != wanted_inner_mode)
6358 offset = (GET_MODE_SIZE (is_mode)
6359 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6361 if (offset != 0 || inner_mode != wanted_inner_mode)
6362 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6365 /* If INNER is not memory, we can always get it into the proper mode. If we
6366 are changing its mode, POS must be a constant and smaller than the size
6368 else if (GET_CODE (inner) != MEM)
6370 if (GET_MODE (inner) != wanted_inner_mode
6372 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6375 inner = force_to_mode (inner, wanted_inner_mode,
6377 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6378 ? ~(unsigned HOST_WIDE_INT) 0
6379 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6384 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6385 have to zero extend. Otherwise, we can just use a SUBREG. */
6387 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6389 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6391 /* If we know that no extraneous bits are set, and that the high
6392 bit is not set, convert extraction to cheaper one - either
6393 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6395 if (flag_expensive_optimizations
6396 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6397 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6398 & ~(((unsigned HOST_WIDE_INT)
6399 GET_MODE_MASK (GET_MODE (pos_rtx)))
6403 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6405 /* Prefer ZERO_EXTENSION, since it gives more information to
6407 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6412 else if (pos_rtx != 0
6413 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6414 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6416 /* Make POS_RTX unless we already have it and it is correct. If we don't
6417 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6419 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6420 pos_rtx = orig_pos_rtx;
6422 else if (pos_rtx == 0)
6423 pos_rtx = GEN_INT (pos);
6425 /* Make the required operation. See if we can use existing rtx. */
6426 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6427 extraction_mode, inner, GEN_INT (len), pos_rtx);
6429 new = gen_lowpart_for_combine (mode, new);
6434 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6435 with any other operations in X. Return X without that shift if so. */
6438 extract_left_shift (x, count)
6442 enum rtx_code code = GET_CODE (x);
6443 enum machine_mode mode = GET_MODE (x);
6449 /* This is the shift itself. If it is wide enough, we will return
6450 either the value being shifted if the shift count is equal to
6451 COUNT or a shift for the difference. */
6452 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6453 && INTVAL (XEXP (x, 1)) >= count)
6454 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6455 INTVAL (XEXP (x, 1)) - count);
6459 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6460 return simplify_gen_unary (code, mode, tem, mode);
6464 case PLUS: case IOR: case XOR: case AND:
6465 /* If we can safely shift this constant and we find the inner shift,
6466 make a new operation. */
6467 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6468 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6469 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6470 return gen_binary (code, mode, tem,
6471 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6482 /* Look at the expression rooted at X. Look for expressions
6483 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6484 Form these expressions.
6486 Return the new rtx, usually just X.
6488 Also, for machines like the VAX that don't have logical shift insns,
6489 try to convert logical to arithmetic shift operations in cases where
6490 they are equivalent. This undoes the canonicalizations to logical
6491 shifts done elsewhere.
6493 We try, as much as possible, to re-use rtl expressions to save memory.
6495 IN_CODE says what kind of expression we are processing. Normally, it is
6496 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6497 being kludges), it is MEM. When processing the arguments of a comparison
6498 or a COMPARE against zero, it is COMPARE. */
6501 make_compound_operation (x, in_code)
6503 enum rtx_code in_code;
6505 enum rtx_code code = GET_CODE (x);
6506 enum machine_mode mode = GET_MODE (x);
6507 int mode_width = GET_MODE_BITSIZE (mode);
6509 enum rtx_code next_code;
6515 /* Select the code to be used in recursive calls. Once we are inside an
6516 address, we stay there. If we have a comparison, set to COMPARE,
6517 but once inside, go back to our default of SET. */
6519 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6520 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6521 && XEXP (x, 1) == const0_rtx) ? COMPARE
6522 : in_code == COMPARE ? SET : in_code);
6524 /* Process depending on the code of this operation. If NEW is set
6525 nonzero, it will be returned. */
6530 /* Convert shifts by constants into multiplications if inside
6532 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6533 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6534 && INTVAL (XEXP (x, 1)) >= 0)
6536 new = make_compound_operation (XEXP (x, 0), next_code);
6537 new = gen_rtx_MULT (mode, new,
6538 GEN_INT ((HOST_WIDE_INT) 1
6539 << INTVAL (XEXP (x, 1))));
6544 /* If the second operand is not a constant, we can't do anything
6546 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6549 /* If the constant is a power of two minus one and the first operand
6550 is a logical right shift, make an extraction. */
6551 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6552 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6554 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6555 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6556 0, in_code == COMPARE);
6559 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6560 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6561 && subreg_lowpart_p (XEXP (x, 0))
6562 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6563 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6565 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6567 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6568 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6569 0, in_code == COMPARE);
6571 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6572 else if ((GET_CODE (XEXP (x, 0)) == XOR
6573 || GET_CODE (XEXP (x, 0)) == IOR)
6574 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6575 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6576 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6578 /* Apply the distributive law, and then try to make extractions. */
6579 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6580 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6582 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6584 new = make_compound_operation (new, in_code);
6587 /* If we are have (and (rotate X C) M) and C is larger than the number
6588 of bits in M, this is an extraction. */
6590 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6591 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6592 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6593 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6595 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6596 new = make_extraction (mode, new,
6597 (GET_MODE_BITSIZE (mode)
6598 - INTVAL (XEXP (XEXP (x, 0), 1))),
6599 NULL_RTX, i, 1, 0, in_code == COMPARE);
6602 /* On machines without logical shifts, if the operand of the AND is
6603 a logical shift and our mask turns off all the propagated sign
6604 bits, we can replace the logical shift with an arithmetic shift. */
6605 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6606 && !have_insn_for (LSHIFTRT, mode)
6607 && have_insn_for (ASHIFTRT, mode)
6608 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6609 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6610 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6611 && mode_width <= HOST_BITS_PER_WIDE_INT)
6613 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6615 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6616 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6618 gen_rtx_ASHIFTRT (mode,
6619 make_compound_operation
6620 (XEXP (XEXP (x, 0), 0), next_code),
6621 XEXP (XEXP (x, 0), 1)));
6624 /* If the constant is one less than a power of two, this might be
6625 representable by an extraction even if no shift is present.
6626 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6627 we are in a COMPARE. */
6628 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6629 new = make_extraction (mode,
6630 make_compound_operation (XEXP (x, 0),
6632 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6634 /* If we are in a comparison and this is an AND with a power of two,
6635 convert this into the appropriate bit extract. */
6636 else if (in_code == COMPARE
6637 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6638 new = make_extraction (mode,
6639 make_compound_operation (XEXP (x, 0),
6641 i, NULL_RTX, 1, 1, 0, 1);
6646 /* If the sign bit is known to be zero, replace this with an
6647 arithmetic shift. */
6648 if (have_insn_for (ASHIFTRT, mode)
6649 && ! have_insn_for (LSHIFTRT, mode)
6650 && mode_width <= HOST_BITS_PER_WIDE_INT
6651 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6653 new = gen_rtx_ASHIFTRT (mode,
6654 make_compound_operation (XEXP (x, 0),
6660 /* ... fall through ... */
6666 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6667 this is a SIGN_EXTRACT. */
6668 if (GET_CODE (rhs) == CONST_INT
6669 && GET_CODE (lhs) == ASHIFT
6670 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6671 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6673 new = make_compound_operation (XEXP (lhs, 0), next_code);
6674 new = make_extraction (mode, new,
6675 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6676 NULL_RTX, mode_width - INTVAL (rhs),
6677 code == LSHIFTRT, 0, in_code == COMPARE);
6681 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6682 If so, try to merge the shifts into a SIGN_EXTEND. We could
6683 also do this for some cases of SIGN_EXTRACT, but it doesn't
6684 seem worth the effort; the case checked for occurs on Alpha. */
6686 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6687 && ! (GET_CODE (lhs) == SUBREG
6688 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6689 && GET_CODE (rhs) == CONST_INT
6690 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6691 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6692 new = make_extraction (mode, make_compound_operation (new, next_code),
6693 0, NULL_RTX, mode_width - INTVAL (rhs),
6694 code == LSHIFTRT, 0, in_code == COMPARE);
6699 /* Call ourselves recursively on the inner expression. If we are
6700 narrowing the object and it has a different RTL code from
6701 what it originally did, do this SUBREG as a force_to_mode. */
6703 tem = make_compound_operation (SUBREG_REG (x), in_code);
6704 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6705 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6706 && subreg_lowpart_p (x))
6708 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6711 /* If we have something other than a SUBREG, we might have
6712 done an expansion, so rerun ourselves. */
6713 if (GET_CODE (newer) != SUBREG)
6714 newer = make_compound_operation (newer, in_code);
6719 /* If this is a paradoxical subreg, and the new code is a sign or
6720 zero extension, omit the subreg and widen the extension. If it
6721 is a regular subreg, we can still get rid of the subreg by not
6722 widening so much, or in fact removing the extension entirely. */
6723 if ((GET_CODE (tem) == SIGN_EXTEND
6724 || GET_CODE (tem) == ZERO_EXTEND)
6725 && subreg_lowpart_p (x))
6727 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6728 || (GET_MODE_SIZE (mode) >
6729 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6731 if (! SCALAR_INT_MODE_P (mode))
6733 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6736 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6747 x = gen_lowpart_for_combine (mode, new);
6748 code = GET_CODE (x);
6751 /* Now recursively process each operand of this operation. */
6752 fmt = GET_RTX_FORMAT (code);
6753 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6756 new = make_compound_operation (XEXP (x, i), next_code);
6757 SUBST (XEXP (x, i), new);
6763 /* Given M see if it is a value that would select a field of bits
6764 within an item, but not the entire word. Return -1 if not.
6765 Otherwise, return the starting position of the field, where 0 is the
6768 *PLEN is set to the length of the field. */
6771 get_pos_from_mask (m, plen)
6772 unsigned HOST_WIDE_INT m;
6773 unsigned HOST_WIDE_INT *plen;
6775 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6776 int pos = exact_log2 (m & -m);
6782 /* Now shift off the low-order zero bits and see if we have a power of
6784 len = exact_log2 ((m >> pos) + 1);
6793 /* See if X can be simplified knowing that we will only refer to it in
6794 MODE and will only refer to those bits that are nonzero in MASK.
6795 If other bits are being computed or if masking operations are done
6796 that select a superset of the bits in MASK, they can sometimes be
6799 Return a possibly simplified expression, but always convert X to
6800 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6802 Also, if REG is nonzero and X is a register equal in value to REG,
6805 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6806 are all off in X. This is used when X will be complemented, by either
6807 NOT, NEG, or XOR. */
6810 force_to_mode (x, mode, mask, reg, just_select)
6812 enum machine_mode mode;
6813 unsigned HOST_WIDE_INT mask;
6817 enum rtx_code code = GET_CODE (x);
6818 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6819 enum machine_mode op_mode;
6820 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6823 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6824 code below will do the wrong thing since the mode of such an
6825 expression is VOIDmode.
6827 Also do nothing if X is a CLOBBER; this can happen if X was
6828 the return value from a call to gen_lowpart_for_combine. */
6829 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6832 /* We want to perform the operation is its present mode unless we know
6833 that the operation is valid in MODE, in which case we do the operation
6835 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6836 && have_insn_for (code, mode))
6837 ? mode : GET_MODE (x));
6839 /* It is not valid to do a right-shift in a narrower mode
6840 than the one it came in with. */
6841 if ((code == LSHIFTRT || code == ASHIFTRT)
6842 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6843 op_mode = GET_MODE (x);
6845 /* Truncate MASK to fit OP_MODE. */
6847 mask &= GET_MODE_MASK (op_mode);
6849 /* When we have an arithmetic operation, or a shift whose count we
6850 do not know, we need to assume that all bit the up to the highest-order
6851 bit in MASK will be needed. This is how we form such a mask. */
6853 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6854 ? GET_MODE_MASK (op_mode)
6855 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6858 fuller_mask = ~(HOST_WIDE_INT) 0;
6860 /* Determine what bits of X are guaranteed to be (non)zero. */
6861 nonzero = nonzero_bits (x, mode);
6863 /* If none of the bits in X are needed, return a zero. */
6864 if (! just_select && (nonzero & mask) == 0)
6867 /* If X is a CONST_INT, return a new one. Do this here since the
6868 test below will fail. */
6869 if (GET_CODE (x) == CONST_INT)
6871 if (SCALAR_INT_MODE_P (mode))
6872 return gen_int_mode (INTVAL (x) & mask, mode);
6875 x = GEN_INT (INTVAL (x) & mask);
6876 return gen_lowpart_common (mode, x);
6880 /* If X is narrower than MODE and we want all the bits in X's mode, just
6881 get X in the proper mode. */
6882 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6883 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6884 return gen_lowpart_for_combine (mode, x);
6886 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6887 MASK are already known to be zero in X, we need not do anything. */
6888 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6894 /* If X is a (clobber (const_int)), return it since we know we are
6895 generating something that won't match. */
6899 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6900 spanned the boundary of the MEM. If we are now masking so it is
6901 within that boundary, we don't need the USE any more. */
6902 if (! BITS_BIG_ENDIAN
6903 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6904 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6911 x = expand_compound_operation (x);
6912 if (GET_CODE (x) != code)
6913 return force_to_mode (x, mode, mask, reg, next_select);
6917 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6918 || rtx_equal_p (reg, get_last_value (x))))
6923 if (subreg_lowpart_p (x)
6924 /* We can ignore the effect of this SUBREG if it narrows the mode or
6925 if the constant masks to zero all the bits the mode doesn't
6927 && ((GET_MODE_SIZE (GET_MODE (x))
6928 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6930 & GET_MODE_MASK (GET_MODE (x))
6931 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6932 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6936 /* If this is an AND with a constant, convert it into an AND
6937 whose constant is the AND of that constant with MASK. If it
6938 remains an AND of MASK, delete it since it is redundant. */
6940 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6942 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6943 mask & INTVAL (XEXP (x, 1)));
6945 /* If X is still an AND, see if it is an AND with a mask that
6946 is just some low-order bits. If so, and it is MASK, we don't
6949 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6950 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6954 /* If it remains an AND, try making another AND with the bits
6955 in the mode mask that aren't in MASK turned on. If the
6956 constant in the AND is wide enough, this might make a
6957 cheaper constant. */
6959 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6960 && GET_MODE_MASK (GET_MODE (x)) != mask
6961 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6963 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6964 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6965 int width = GET_MODE_BITSIZE (GET_MODE (x));
6968 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6969 number, sign extend it. */
6970 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6971 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6972 cval |= (HOST_WIDE_INT) -1 << width;
6974 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6975 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6985 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6986 low-order bits (as in an alignment operation) and FOO is already
6987 aligned to that boundary, mask C1 to that boundary as well.
6988 This may eliminate that PLUS and, later, the AND. */
6991 unsigned int width = GET_MODE_BITSIZE (mode);
6992 unsigned HOST_WIDE_INT smask = mask;
6994 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6995 number, sign extend it. */
6997 if (width < HOST_BITS_PER_WIDE_INT
6998 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6999 smask |= (HOST_WIDE_INT) -1 << width;
7001 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7002 && exact_log2 (- smask) >= 0
7003 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7004 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7005 return force_to_mode (plus_constant (XEXP (x, 0),
7006 (INTVAL (XEXP (x, 1)) & smask)),
7007 mode, smask, reg, next_select);
7010 /* ... fall through ... */
7013 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7014 most significant bit in MASK since carries from those bits will
7015 affect the bits we are interested in. */
7020 /* If X is (minus C Y) where C's least set bit is larger than any bit
7021 in the mask, then we may replace with (neg Y). */
7022 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7023 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7024 & -INTVAL (XEXP (x, 0))))
7027 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7029 return force_to_mode (x, mode, mask, reg, next_select);
7032 /* Similarly, if C contains every bit in the fuller_mask, then we may
7033 replace with (not Y). */
7034 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7035 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7036 == INTVAL (XEXP (x, 0))))
7038 x = simplify_gen_unary (NOT, GET_MODE (x),
7039 XEXP (x, 1), GET_MODE (x));
7040 return force_to_mode (x, mode, mask, reg, next_select);
7048 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7049 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7050 operation which may be a bitfield extraction. Ensure that the
7051 constant we form is not wider than the mode of X. */
7053 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7054 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7055 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7056 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7057 && GET_CODE (XEXP (x, 1)) == CONST_INT
7058 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7059 + floor_log2 (INTVAL (XEXP (x, 1))))
7060 < GET_MODE_BITSIZE (GET_MODE (x)))
7061 && (INTVAL (XEXP (x, 1))
7062 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7064 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7065 << INTVAL (XEXP (XEXP (x, 0), 1)));
7066 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7067 XEXP (XEXP (x, 0), 0), temp);
7068 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7069 XEXP (XEXP (x, 0), 1));
7070 return force_to_mode (x, mode, mask, reg, next_select);
7074 /* For most binary operations, just propagate into the operation and
7075 change the mode if we have an operation of that mode. */
7077 op0 = gen_lowpart_for_combine (op_mode,
7078 force_to_mode (XEXP (x, 0), mode, mask,
7080 op1 = gen_lowpart_for_combine (op_mode,
7081 force_to_mode (XEXP (x, 1), mode, mask,
7084 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7085 x = gen_binary (code, op_mode, op0, op1);
7089 /* For left shifts, do the same, but just for the first operand.
7090 However, we cannot do anything with shifts where we cannot
7091 guarantee that the counts are smaller than the size of the mode
7092 because such a count will have a different meaning in a
7095 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7096 && INTVAL (XEXP (x, 1)) >= 0
7097 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7098 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7099 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7100 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7103 /* If the shift count is a constant and we can do arithmetic in
7104 the mode of the shift, refine which bits we need. Otherwise, use the
7105 conservative form of the mask. */
7106 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7107 && INTVAL (XEXP (x, 1)) >= 0
7108 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7109 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7110 mask >>= INTVAL (XEXP (x, 1));
7114 op0 = gen_lowpart_for_combine (op_mode,
7115 force_to_mode (XEXP (x, 0), op_mode,
7116 mask, reg, next_select));
7118 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7119 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7123 /* Here we can only do something if the shift count is a constant,
7124 this shift constant is valid for the host, and we can do arithmetic
7127 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7128 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7129 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7131 rtx inner = XEXP (x, 0);
7132 unsigned HOST_WIDE_INT inner_mask;
7134 /* Select the mask of the bits we need for the shift operand. */
7135 inner_mask = mask << INTVAL (XEXP (x, 1));
7137 /* We can only change the mode of the shift if we can do arithmetic
7138 in the mode of the shift and INNER_MASK is no wider than the
7139 width of OP_MODE. */
7140 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7141 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7142 op_mode = GET_MODE (x);
7144 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7146 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7147 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7150 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7151 shift and AND produces only copies of the sign bit (C2 is one less
7152 than a power of two), we can do this with just a shift. */
7154 if (GET_CODE (x) == LSHIFTRT
7155 && GET_CODE (XEXP (x, 1)) == CONST_INT
7156 /* The shift puts one of the sign bit copies in the least significant
7158 && ((INTVAL (XEXP (x, 1))
7159 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7160 >= GET_MODE_BITSIZE (GET_MODE (x)))
7161 && exact_log2 (mask + 1) >= 0
7162 /* Number of bits left after the shift must be more than the mask
7164 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7165 <= GET_MODE_BITSIZE (GET_MODE (x)))
7166 /* Must be more sign bit copies than the mask needs. */
7167 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7168 >= exact_log2 (mask + 1)))
7169 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7170 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7171 - exact_log2 (mask + 1)));
7176 /* If we are just looking for the sign bit, we don't need this shift at
7177 all, even if it has a variable count. */
7178 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7179 && (mask == ((unsigned HOST_WIDE_INT) 1
7180 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7181 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7183 /* If this is a shift by a constant, get a mask that contains those bits
7184 that are not copies of the sign bit. We then have two cases: If
7185 MASK only includes those bits, this can be a logical shift, which may
7186 allow simplifications. If MASK is a single-bit field not within
7187 those bits, we are requesting a copy of the sign bit and hence can
7188 shift the sign bit to the appropriate location. */
7190 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7191 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7195 /* If the considered data is wider than HOST_WIDE_INT, we can't
7196 represent a mask for all its bits in a single scalar.
7197 But we only care about the lower bits, so calculate these. */
7199 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7201 nonzero = ~(HOST_WIDE_INT) 0;
7203 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7204 is the number of bits a full-width mask would have set.
7205 We need only shift if these are fewer than nonzero can
7206 hold. If not, we must keep all bits set in nonzero. */
7208 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7209 < HOST_BITS_PER_WIDE_INT)
7210 nonzero >>= INTVAL (XEXP (x, 1))
7211 + HOST_BITS_PER_WIDE_INT
7212 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7216 nonzero = GET_MODE_MASK (GET_MODE (x));
7217 nonzero >>= INTVAL (XEXP (x, 1));
7220 if ((mask & ~nonzero) == 0
7221 || (i = exact_log2 (mask)) >= 0)
7223 x = simplify_shift_const
7224 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7225 i < 0 ? INTVAL (XEXP (x, 1))
7226 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7228 if (GET_CODE (x) != ASHIFTRT)
7229 return force_to_mode (x, mode, mask, reg, next_select);
7233 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7234 even if the shift count isn't a constant. */
7236 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7240 /* If this is a zero- or sign-extension operation that just affects bits
7241 we don't care about, remove it. Be sure the call above returned
7242 something that is still a shift. */
7244 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7245 && GET_CODE (XEXP (x, 1)) == CONST_INT
7246 && INTVAL (XEXP (x, 1)) >= 0
7247 && (INTVAL (XEXP (x, 1))
7248 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7249 && GET_CODE (XEXP (x, 0)) == ASHIFT
7250 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7251 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7252 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7259 /* If the shift count is constant and we can do computations
7260 in the mode of X, compute where the bits we care about are.
7261 Otherwise, we can't do anything. Don't change the mode of
7262 the shift or propagate MODE into the shift, though. */
7263 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7264 && INTVAL (XEXP (x, 1)) >= 0)
7266 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7267 GET_MODE (x), GEN_INT (mask),
7269 if (temp && GET_CODE (temp) == CONST_INT)
7271 force_to_mode (XEXP (x, 0), GET_MODE (x),
7272 INTVAL (temp), reg, next_select));
7277 /* If we just want the low-order bit, the NEG isn't needed since it
7278 won't change the low-order bit. */
7280 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7282 /* We need any bits less significant than the most significant bit in
7283 MASK since carries from those bits will affect the bits we are
7289 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7290 same as the XOR case above. Ensure that the constant we form is not
7291 wider than the mode of X. */
7293 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7294 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7295 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7296 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7297 < GET_MODE_BITSIZE (GET_MODE (x)))
7298 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7300 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7301 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7302 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7304 return force_to_mode (x, mode, mask, reg, next_select);
7307 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7308 use the full mask inside the NOT. */
7312 op0 = gen_lowpart_for_combine (op_mode,
7313 force_to_mode (XEXP (x, 0), mode, mask,
7315 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7316 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7320 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7321 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7322 which is equal to STORE_FLAG_VALUE. */
7323 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7324 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7325 && (nonzero_bits (XEXP (x, 0), mode)
7326 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7327 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7332 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7333 written in a narrower mode. We play it safe and do not do so. */
7336 gen_lowpart_for_combine (GET_MODE (x),
7337 force_to_mode (XEXP (x, 1), mode,
7338 mask, reg, next_select)));
7340 gen_lowpart_for_combine (GET_MODE (x),
7341 force_to_mode (XEXP (x, 2), mode,
7342 mask, reg, next_select)));
7349 /* Ensure we return a value of the proper mode. */
7350 return gen_lowpart_for_combine (mode, x);
7353 /* Return nonzero if X is an expression that has one of two values depending on
7354 whether some other value is zero or nonzero. In that case, we return the
7355 value that is being tested, *PTRUE is set to the value if the rtx being
7356 returned has a nonzero value, and *PFALSE is set to the other alternative.
7358 If we return zero, we set *PTRUE and *PFALSE to X. */
7361 if_then_else_cond (x, ptrue, pfalse)
7363 rtx *ptrue, *pfalse;
7365 enum machine_mode mode = GET_MODE (x);
7366 enum rtx_code code = GET_CODE (x);
7367 rtx cond0, cond1, true0, true1, false0, false1;
7368 unsigned HOST_WIDE_INT nz;
7370 /* If we are comparing a value against zero, we are done. */
7371 if ((code == NE || code == EQ)
7372 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7374 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7375 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7379 /* If this is a unary operation whose operand has one of two values, apply
7380 our opcode to compute those values. */
7381 else if (GET_RTX_CLASS (code) == '1'
7382 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7384 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7385 *pfalse = simplify_gen_unary (code, mode, false0,
7386 GET_MODE (XEXP (x, 0)));
7390 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7391 make can't possibly match and would suppress other optimizations. */
7392 else if (code == COMPARE)
7395 /* If this is a binary operation, see if either side has only one of two
7396 values. If either one does or if both do and they are conditional on
7397 the same value, compute the new true and false values. */
7398 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7399 || GET_RTX_CLASS (code) == '<')
7401 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7402 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7404 if ((cond0 != 0 || cond1 != 0)
7405 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7407 /* If if_then_else_cond returned zero, then true/false are the
7408 same rtl. We must copy one of them to prevent invalid rtl
7411 true0 = copy_rtx (true0);
7412 else if (cond1 == 0)
7413 true1 = copy_rtx (true1);
7415 *ptrue = gen_binary (code, mode, true0, true1);
7416 *pfalse = gen_binary (code, mode, false0, false1);
7417 return cond0 ? cond0 : cond1;
7420 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7421 operands is zero when the other is nonzero, and vice-versa,
7422 and STORE_FLAG_VALUE is 1 or -1. */
7424 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7425 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7427 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7429 rtx op0 = XEXP (XEXP (x, 0), 1);
7430 rtx op1 = XEXP (XEXP (x, 1), 1);
7432 cond0 = XEXP (XEXP (x, 0), 0);
7433 cond1 = XEXP (XEXP (x, 1), 0);
7435 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7436 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7437 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7438 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7439 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7440 || ((swap_condition (GET_CODE (cond0))
7441 == combine_reversed_comparison_code (cond1))
7442 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7443 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7444 && ! side_effects_p (x))
7446 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7447 *pfalse = gen_binary (MULT, mode,
7449 ? simplify_gen_unary (NEG, mode, op1,
7457 /* Similarly for MULT, AND and UMIN, except that for these the result
7459 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7460 && (code == MULT || code == AND || code == UMIN)
7461 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7463 cond0 = XEXP (XEXP (x, 0), 0);
7464 cond1 = XEXP (XEXP (x, 1), 0);
7466 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7467 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7468 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7469 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7470 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7471 || ((swap_condition (GET_CODE (cond0))
7472 == combine_reversed_comparison_code (cond1))
7473 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7474 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7475 && ! side_effects_p (x))
7477 *ptrue = *pfalse = const0_rtx;
7483 else if (code == IF_THEN_ELSE)
7485 /* If we have IF_THEN_ELSE already, extract the condition and
7486 canonicalize it if it is NE or EQ. */
7487 cond0 = XEXP (x, 0);
7488 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7489 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7490 return XEXP (cond0, 0);
7491 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7493 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7494 return XEXP (cond0, 0);
7500 /* If X is a SUBREG, we can narrow both the true and false values
7501 if the inner expression, if there is a condition. */
7502 else if (code == SUBREG
7503 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7506 *ptrue = simplify_gen_subreg (mode, true0,
7507 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7508 *pfalse = simplify_gen_subreg (mode, false0,
7509 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7514 /* If X is a constant, this isn't special and will cause confusions
7515 if we treat it as such. Likewise if it is equivalent to a constant. */
7516 else if (CONSTANT_P (x)
7517 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7520 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7521 will be least confusing to the rest of the compiler. */
7522 else if (mode == BImode)
7524 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7528 /* If X is known to be either 0 or -1, those are the true and
7529 false values when testing X. */
7530 else if (x == constm1_rtx || x == const0_rtx
7531 || (mode != VOIDmode
7532 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7534 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7538 /* Likewise for 0 or a single bit. */
7539 else if (mode != VOIDmode
7540 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7541 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7543 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7547 /* Otherwise fail; show no condition with true and false values the same. */
7548 *ptrue = *pfalse = x;
7552 /* Return the value of expression X given the fact that condition COND
7553 is known to be true when applied to REG as its first operand and VAL
7554 as its second. X is known to not be shared and so can be modified in
7557 We only handle the simplest cases, and specifically those cases that
7558 arise with IF_THEN_ELSE expressions. */
7561 known_cond (x, cond, reg, val)
7566 enum rtx_code code = GET_CODE (x);
7571 if (side_effects_p (x))
7574 /* If either operand of the condition is a floating point value,
7575 then we have to avoid collapsing an EQ comparison. */
7577 && rtx_equal_p (x, reg)
7578 && ! FLOAT_MODE_P (GET_MODE (x))
7579 && ! FLOAT_MODE_P (GET_MODE (val)))
7582 if (cond == UNEQ && rtx_equal_p (x, reg))
7585 /* If X is (abs REG) and we know something about REG's relationship
7586 with zero, we may be able to simplify this. */
7588 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7591 case GE: case GT: case EQ:
7594 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7596 GET_MODE (XEXP (x, 0)));
7601 /* The only other cases we handle are MIN, MAX, and comparisons if the
7602 operands are the same as REG and VAL. */
7604 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7606 if (rtx_equal_p (XEXP (x, 0), val))
7607 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7609 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7611 if (GET_RTX_CLASS (code) == '<')
7613 if (comparison_dominates_p (cond, code))
7614 return const_true_rtx;
7616 code = combine_reversed_comparison_code (x);
7618 && comparison_dominates_p (cond, code))
7623 else if (code == SMAX || code == SMIN
7624 || code == UMIN || code == UMAX)
7626 int unsignedp = (code == UMIN || code == UMAX);
7628 /* Do not reverse the condition when it is NE or EQ.
7629 This is because we cannot conclude anything about
7630 the value of 'SMAX (x, y)' when x is not equal to y,
7631 but we can when x equals y. */
7632 if ((code == SMAX || code == UMAX)
7633 && ! (cond == EQ || cond == NE))
7634 cond = reverse_condition (cond);
7639 return unsignedp ? x : XEXP (x, 1);
7641 return unsignedp ? x : XEXP (x, 0);
7643 return unsignedp ? XEXP (x, 1) : x;
7645 return unsignedp ? XEXP (x, 0) : x;
7652 else if (code == SUBREG)
7654 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7655 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7657 if (SUBREG_REG (x) != r)
7659 /* We must simplify subreg here, before we lose track of the
7660 original inner_mode. */
7661 new = simplify_subreg (GET_MODE (x), r,
7662 inner_mode, SUBREG_BYTE (x));
7666 SUBST (SUBREG_REG (x), r);
7671 /* We don't have to handle SIGN_EXTEND here, because even in the
7672 case of replacing something with a modeless CONST_INT, a
7673 CONST_INT is already (supposed to be) a valid sign extension for
7674 its narrower mode, which implies it's already properly
7675 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7676 story is different. */
7677 else if (code == ZERO_EXTEND)
7679 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7680 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7682 if (XEXP (x, 0) != r)
7684 /* We must simplify the zero_extend here, before we lose
7685 track of the original inner_mode. */
7686 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7691 SUBST (XEXP (x, 0), r);
7697 fmt = GET_RTX_FORMAT (code);
7698 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7701 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7702 else if (fmt[i] == 'E')
7703 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7704 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7711 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7712 assignment as a field assignment. */
7715 rtx_equal_for_field_assignment_p (x, y)
7719 if (x == y || rtx_equal_p (x, y))
7722 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7725 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7726 Note that all SUBREGs of MEM are paradoxical; otherwise they
7727 would have been rewritten. */
7728 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7729 && GET_CODE (SUBREG_REG (y)) == MEM
7730 && rtx_equal_p (SUBREG_REG (y),
7731 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7734 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7735 && GET_CODE (SUBREG_REG (x)) == MEM
7736 && rtx_equal_p (SUBREG_REG (x),
7737 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7740 /* We used to see if get_last_value of X and Y were the same but that's
7741 not correct. In one direction, we'll cause the assignment to have
7742 the wrong destination and in the case, we'll import a register into this
7743 insn that might have already have been dead. So fail if none of the
7744 above cases are true. */
7748 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7749 Return that assignment if so.
7751 We only handle the most common cases. */
7754 make_field_assignment (x)
7757 rtx dest = SET_DEST (x);
7758 rtx src = SET_SRC (x);
7763 unsigned HOST_WIDE_INT len;
7765 enum machine_mode mode;
7767 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7768 a clear of a one-bit field. We will have changed it to
7769 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7772 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7773 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7774 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7775 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7777 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7780 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7784 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7785 && subreg_lowpart_p (XEXP (src, 0))
7786 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7787 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7788 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7789 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7790 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7792 assign = make_extraction (VOIDmode, dest, 0,
7793 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7796 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7800 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7802 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7803 && XEXP (XEXP (src, 0), 0) == const1_rtx
7804 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7806 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7809 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7813 /* The other case we handle is assignments into a constant-position
7814 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7815 a mask that has all one bits except for a group of zero bits and
7816 OTHER is known to have zeros where C1 has ones, this is such an
7817 assignment. Compute the position and length from C1. Shift OTHER
7818 to the appropriate position, force it to the required mode, and
7819 make the extraction. Check for the AND in both operands. */
7821 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7824 rhs = expand_compound_operation (XEXP (src, 0));
7825 lhs = expand_compound_operation (XEXP (src, 1));
7827 if (GET_CODE (rhs) == AND
7828 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7829 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7830 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7831 else if (GET_CODE (lhs) == AND
7832 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7833 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7834 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7838 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7839 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7840 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7841 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7844 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7848 /* The mode to use for the source is the mode of the assignment, or of
7849 what is inside a possible STRICT_LOW_PART. */
7850 mode = (GET_CODE (assign) == STRICT_LOW_PART
7851 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7853 /* Shift OTHER right POS places and make it the source, restricting it
7854 to the proper length and mode. */
7856 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7857 GET_MODE (src), other, pos),
7859 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7860 ? ~(unsigned HOST_WIDE_INT) 0
7861 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7864 return gen_rtx_SET (VOIDmode, assign, src);
7867 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7871 apply_distributive_law (x)
7874 enum rtx_code code = GET_CODE (x);
7875 rtx lhs, rhs, other;
7877 enum rtx_code inner_code;
7879 /* Distributivity is not true for floating point.
7880 It can change the value. So don't do it.
7881 -- rms and moshier@world.std.com. */
7882 if (FLOAT_MODE_P (GET_MODE (x)))
7885 /* The outer operation can only be one of the following: */
7886 if (code != IOR && code != AND && code != XOR
7887 && code != PLUS && code != MINUS)
7890 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7892 /* If either operand is a primitive we can't do anything, so get out
7894 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7895 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7898 lhs = expand_compound_operation (lhs);
7899 rhs = expand_compound_operation (rhs);
7900 inner_code = GET_CODE (lhs);
7901 if (inner_code != GET_CODE (rhs))
7904 /* See if the inner and outer operations distribute. */
7911 /* These all distribute except over PLUS. */
7912 if (code == PLUS || code == MINUS)
7917 if (code != PLUS && code != MINUS)
7922 /* This is also a multiply, so it distributes over everything. */
7926 /* Non-paradoxical SUBREGs distributes over all operations, provided
7927 the inner modes and byte offsets are the same, this is an extraction
7928 of a low-order part, we don't convert an fp operation to int or
7929 vice versa, and we would not be converting a single-word
7930 operation into a multi-word operation. The latter test is not
7931 required, but it prevents generating unneeded multi-word operations.
7932 Some of the previous tests are redundant given the latter test, but
7933 are retained because they are required for correctness.
7935 We produce the result slightly differently in this case. */
7937 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7938 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7939 || ! subreg_lowpart_p (lhs)
7940 || (GET_MODE_CLASS (GET_MODE (lhs))
7941 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7942 || (GET_MODE_SIZE (GET_MODE (lhs))
7943 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7944 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7947 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7948 SUBREG_REG (lhs), SUBREG_REG (rhs));
7949 return gen_lowpart_for_combine (GET_MODE (x), tem);
7955 /* Set LHS and RHS to the inner operands (A and B in the example
7956 above) and set OTHER to the common operand (C in the example).
7957 These is only one way to do this unless the inner operation is
7959 if (GET_RTX_CLASS (inner_code) == 'c'
7960 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7961 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7962 else if (GET_RTX_CLASS (inner_code) == 'c'
7963 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7964 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7965 else if (GET_RTX_CLASS (inner_code) == 'c'
7966 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7967 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7968 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7969 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7973 /* Form the new inner operation, seeing if it simplifies first. */
7974 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7976 /* There is one exception to the general way of distributing:
7977 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7978 if (code == XOR && inner_code == IOR)
7981 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7984 /* We may be able to continuing distributing the result, so call
7985 ourselves recursively on the inner operation before forming the
7986 outer operation, which we return. */
7987 return gen_binary (inner_code, GET_MODE (x),
7988 apply_distributive_law (tem), other);
7991 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7994 Return an equivalent form, if different from X. Otherwise, return X. If
7995 X is zero, we are to always construct the equivalent form. */
7998 simplify_and_const_int (x, mode, varop, constop)
8000 enum machine_mode mode;
8002 unsigned HOST_WIDE_INT constop;
8004 unsigned HOST_WIDE_INT nonzero;
8007 /* Simplify VAROP knowing that we will be only looking at some of the
8010 Note by passing in CONSTOP, we guarantee that the bits not set in
8011 CONSTOP are not significant and will never be examined. We must
8012 ensure that is the case by explicitly masking out those bits
8013 before returning. */
8014 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8016 /* If VAROP is a CLOBBER, we will fail so return it. */
8017 if (GET_CODE (varop) == CLOBBER)
8020 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8021 to VAROP and return the new constant. */
8022 if (GET_CODE (varop) == CONST_INT)
8023 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8025 /* See what bits may be nonzero in VAROP. Unlike the general case of
8026 a call to nonzero_bits, here we don't care about bits outside
8029 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8031 /* Turn off all bits in the constant that are known to already be zero.
8032 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8033 which is tested below. */
8037 /* If we don't have any bits left, return zero. */
8041 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8042 a power of two, we can replace this with an ASHIFT. */
8043 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8044 && (i = exact_log2 (constop)) >= 0)
8045 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8047 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8048 or XOR, then try to apply the distributive law. This may eliminate
8049 operations if either branch can be simplified because of the AND.
8050 It may also make some cases more complex, but those cases probably
8051 won't match a pattern either with or without this. */
8053 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8055 gen_lowpart_for_combine
8057 apply_distributive_law
8058 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8059 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8060 XEXP (varop, 0), constop),
8061 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8062 XEXP (varop, 1), constop))));
8064 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8065 the AND and see if one of the operands simplifies to zero. If so, we
8066 may eliminate it. */
8068 if (GET_CODE (varop) == PLUS
8069 && exact_log2 (constop + 1) >= 0)
8073 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8074 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8075 if (o0 == const0_rtx)
8077 if (o1 == const0_rtx)
8081 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8082 if we already had one (just check for the simplest cases). */
8083 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8084 && GET_MODE (XEXP (x, 0)) == mode
8085 && SUBREG_REG (XEXP (x, 0)) == varop)
8086 varop = XEXP (x, 0);
8088 varop = gen_lowpart_for_combine (mode, varop);
8090 /* If we can't make the SUBREG, try to return what we were given. */
8091 if (GET_CODE (varop) == CLOBBER)
8092 return x ? x : varop;
8094 /* If we are only masking insignificant bits, return VAROP. */
8095 if (constop == nonzero)
8099 /* Otherwise, return an AND. */
8100 constop = trunc_int_for_mode (constop, mode);
8101 /* See how much, if any, of X we can use. */
8102 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8103 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8107 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8108 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8109 SUBST (XEXP (x, 1), GEN_INT (constop));
8111 SUBST (XEXP (x, 0), varop);
8118 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8119 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8120 is less useful. We can't allow both, because that results in exponential
8121 run time recursion. There is a nullstone testcase that triggered
8122 this. This macro avoids accidental uses of num_sign_bit_copies. */
8123 #define num_sign_bit_copies()
8125 /* Given an expression, X, compute which bits in X can be nonzero.
8126 We don't care about bits outside of those defined in MODE.
8128 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8129 a shift, AND, or zero_extract, we can do better. */
8131 static unsigned HOST_WIDE_INT
8132 nonzero_bits (x, mode)
8134 enum machine_mode mode;
8136 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8137 unsigned HOST_WIDE_INT inner_nz;
8139 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8142 /* For floating-point values, assume all bits are needed. */
8143 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8146 /* If X is wider than MODE, use its mode instead. */
8147 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8149 mode = GET_MODE (x);
8150 nonzero = GET_MODE_MASK (mode);
8151 mode_width = GET_MODE_BITSIZE (mode);
8154 if (mode_width > HOST_BITS_PER_WIDE_INT)
8155 /* Our only callers in this case look for single bit values. So
8156 just return the mode mask. Those tests will then be false. */
8159 #ifndef WORD_REGISTER_OPERATIONS
8160 /* If MODE is wider than X, but both are a single word for both the host
8161 and target machines, we can compute this from which bits of the
8162 object might be nonzero in its own mode, taking into account the fact
8163 that on many CISC machines, accessing an object in a wider mode
8164 causes the high-order bits to become undefined. So they are
8165 not known to be zero. */
8167 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8168 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8169 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8170 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8172 nonzero &= nonzero_bits (x, GET_MODE (x));
8173 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8178 code = GET_CODE (x);
8182 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8183 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8184 all the bits above ptr_mode are known to be zero. */
8185 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8187 nonzero &= GET_MODE_MASK (ptr_mode);
8190 /* Include declared information about alignment of pointers. */
8191 /* ??? We don't properly preserve REG_POINTER changes across
8192 pointer-to-integer casts, so we can't trust it except for
8193 things that we know must be pointers. See execute/960116-1.c. */
8194 if ((x == stack_pointer_rtx
8195 || x == frame_pointer_rtx
8196 || x == arg_pointer_rtx)
8197 && REGNO_POINTER_ALIGN (REGNO (x)))
8199 unsigned HOST_WIDE_INT alignment
8200 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8202 #ifdef PUSH_ROUNDING
8203 /* If PUSH_ROUNDING is defined, it is possible for the
8204 stack to be momentarily aligned only to that amount,
8205 so we pick the least alignment. */
8206 if (x == stack_pointer_rtx && PUSH_ARGS)
8207 alignment = MIN (PUSH_ROUNDING (1), alignment);
8210 nonzero &= ~(alignment - 1);
8213 /* If X is a register whose nonzero bits value is current, use it.
8214 Otherwise, if X is a register whose value we can find, use that
8215 value. Otherwise, use the previously-computed global nonzero bits
8216 for this register. */
8218 if (reg_last_set_value[REGNO (x)] != 0
8219 && (reg_last_set_mode[REGNO (x)] == mode
8220 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8221 && GET_MODE_CLASS (mode) == MODE_INT))
8222 && (reg_last_set_label[REGNO (x)] == label_tick
8223 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8224 && REG_N_SETS (REGNO (x)) == 1
8225 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8227 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8228 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8230 tem = get_last_value (x);
8234 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8235 /* If X is narrower than MODE and TEM is a non-negative
8236 constant that would appear negative in the mode of X,
8237 sign-extend it for use in reg_nonzero_bits because some
8238 machines (maybe most) will actually do the sign-extension
8239 and this is the conservative approach.
8241 ??? For 2.5, try to tighten up the MD files in this regard
8242 instead of this kludge. */
8244 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8245 && GET_CODE (tem) == CONST_INT
8247 && 0 != (INTVAL (tem)
8248 & ((HOST_WIDE_INT) 1
8249 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8250 tem = GEN_INT (INTVAL (tem)
8251 | ((HOST_WIDE_INT) (-1)
8252 << GET_MODE_BITSIZE (GET_MODE (x))));
8254 return nonzero_bits (tem, mode) & nonzero;
8256 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8258 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8260 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8261 /* We don't know anything about the upper bits. */
8262 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8263 return nonzero & mask;
8269 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8270 /* If X is negative in MODE, sign-extend the value. */
8271 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8272 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8273 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8279 #ifdef LOAD_EXTEND_OP
8280 /* In many, if not most, RISC machines, reading a byte from memory
8281 zeros the rest of the register. Noticing that fact saves a lot
8282 of extra zero-extends. */
8283 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8284 nonzero &= GET_MODE_MASK (GET_MODE (x));
8289 case UNEQ: case LTGT:
8290 case GT: case GTU: case UNGT:
8291 case LT: case LTU: case UNLT:
8292 case GE: case GEU: case UNGE:
8293 case LE: case LEU: case UNLE:
8294 case UNORDERED: case ORDERED:
8296 /* If this produces an integer result, we know which bits are set.
8297 Code here used to clear bits outside the mode of X, but that is
8300 if (GET_MODE_CLASS (mode) == MODE_INT
8301 && mode_width <= HOST_BITS_PER_WIDE_INT)
8302 nonzero = STORE_FLAG_VALUE;
8307 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8308 and num_sign_bit_copies. */
8309 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8310 == GET_MODE_BITSIZE (GET_MODE (x)))
8314 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8315 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8320 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8321 and num_sign_bit_copies. */
8322 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8323 == GET_MODE_BITSIZE (GET_MODE (x)))
8329 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8333 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8334 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8335 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8339 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8340 Otherwise, show all the bits in the outer mode but not the inner
8342 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8343 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8345 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8347 & (((HOST_WIDE_INT) 1
8348 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8349 inner_nz |= (GET_MODE_MASK (mode)
8350 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8353 nonzero &= inner_nz;
8357 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8358 & nonzero_bits (XEXP (x, 1), mode));
8362 case UMIN: case UMAX: case SMIN: case SMAX:
8364 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8366 /* Don't call nonzero_bits for the second time if it cannot change
8368 if ((nonzero & nonzero0) != nonzero)
8369 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8373 case PLUS: case MINUS:
8375 case DIV: case UDIV:
8376 case MOD: case UMOD:
8377 /* We can apply the rules of arithmetic to compute the number of
8378 high- and low-order zero bits of these operations. We start by
8379 computing the width (position of the highest-order nonzero bit)
8380 and the number of low-order zero bits for each value. */
8382 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8383 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8384 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8385 int width0 = floor_log2 (nz0) + 1;
8386 int width1 = floor_log2 (nz1) + 1;
8387 int low0 = floor_log2 (nz0 & -nz0);
8388 int low1 = floor_log2 (nz1 & -nz1);
8389 HOST_WIDE_INT op0_maybe_minusp
8390 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8391 HOST_WIDE_INT op1_maybe_minusp
8392 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8393 unsigned int result_width = mode_width;
8399 result_width = MAX (width0, width1) + 1;
8400 result_low = MIN (low0, low1);
8403 result_low = MIN (low0, low1);
8406 result_width = width0 + width1;
8407 result_low = low0 + low1;
8412 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8413 result_width = width0;
8418 result_width = width0;
8423 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8424 result_width = MIN (width0, width1);
8425 result_low = MIN (low0, low1);
8430 result_width = MIN (width0, width1);
8431 result_low = MIN (low0, low1);
8437 if (result_width < mode_width)
8438 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8441 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8443 #ifdef POINTERS_EXTEND_UNSIGNED
8444 /* If pointers extend unsigned and this is an addition or subtraction
8445 to a pointer in Pmode, all the bits above ptr_mode are known to be
8447 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8448 && (code == PLUS || code == MINUS)
8449 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8450 nonzero &= GET_MODE_MASK (ptr_mode);
8456 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8457 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8458 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8462 /* If this is a SUBREG formed for a promoted variable that has
8463 been zero-extended, we know that at least the high-order bits
8464 are zero, though others might be too. */
8466 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8467 nonzero = (GET_MODE_MASK (GET_MODE (x))
8468 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8470 /* If the inner mode is a single word for both the host and target
8471 machines, we can compute this from which bits of the inner
8472 object might be nonzero. */
8473 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8474 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8475 <= HOST_BITS_PER_WIDE_INT))
8477 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8479 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8480 /* If this is a typical RISC machine, we only have to worry
8481 about the way loads are extended. */
8482 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8484 & (((unsigned HOST_WIDE_INT) 1
8485 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8487 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8488 || GET_CODE (SUBREG_REG (x)) != MEM)
8491 /* On many CISC machines, accessing an object in a wider mode
8492 causes the high-order bits to become undefined. So they are
8493 not known to be zero. */
8494 if (GET_MODE_SIZE (GET_MODE (x))
8495 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8496 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8497 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8506 /* The nonzero bits are in two classes: any bits within MODE
8507 that aren't in GET_MODE (x) are always significant. The rest of the
8508 nonzero bits are those that are significant in the operand of
8509 the shift when shifted the appropriate number of bits. This
8510 shows that high-order bits are cleared by the right shift and
8511 low-order bits by left shifts. */
8512 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8513 && INTVAL (XEXP (x, 1)) >= 0
8514 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8516 enum machine_mode inner_mode = GET_MODE (x);
8517 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8518 int count = INTVAL (XEXP (x, 1));
8519 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8520 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8521 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8522 unsigned HOST_WIDE_INT outer = 0;
8524 if (mode_width > width)
8525 outer = (op_nonzero & nonzero & ~mode_mask);
8527 if (code == LSHIFTRT)
8529 else if (code == ASHIFTRT)
8533 /* If the sign bit may have been nonzero before the shift, we
8534 need to mark all the places it could have been copied to
8535 by the shift as possibly nonzero. */
8536 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8537 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8539 else if (code == ASHIFT)
8542 inner = ((inner << (count % width)
8543 | (inner >> (width - (count % width)))) & mode_mask);
8545 nonzero &= (outer | inner);
8551 /* This is at most the number of bits in the mode. */
8552 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8556 /* If CLZ has a known value at zero, then the nonzero bits are
8557 that value, plus the number of bits in the mode minus one. */
8558 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8559 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8565 /* If CTZ has a known value at zero, then the nonzero bits are
8566 that value, plus the number of bits in the mode minus one. */
8567 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8568 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8579 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8580 | nonzero_bits (XEXP (x, 2), mode));
8590 /* See the macro definition above. */
8591 #undef num_sign_bit_copies
8593 /* Return the number of bits at the high-order end of X that are known to
8594 be equal to the sign bit. X will be used in mode MODE; if MODE is
8595 VOIDmode, X will be used in its own mode. The returned value will always
8596 be between 1 and the number of bits in MODE. */
8599 num_sign_bit_copies (x, mode)
8601 enum machine_mode mode;
8603 enum rtx_code code = GET_CODE (x);
8604 unsigned int bitwidth;
8605 int num0, num1, result;
8606 unsigned HOST_WIDE_INT nonzero;
8609 /* If we weren't given a mode, use the mode of X. If the mode is still
8610 VOIDmode, we don't know anything. Likewise if one of the modes is
8613 if (mode == VOIDmode)
8614 mode = GET_MODE (x);
8616 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8619 bitwidth = GET_MODE_BITSIZE (mode);
8621 /* For a smaller object, just ignore the high bits. */
8622 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8624 num0 = num_sign_bit_copies (x, GET_MODE (x));
8626 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8629 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8631 #ifndef WORD_REGISTER_OPERATIONS
8632 /* If this machine does not do all register operations on the entire
8633 register and MODE is wider than the mode of X, we can say nothing
8634 at all about the high-order bits. */
8637 /* Likewise on machines that do, if the mode of the object is smaller
8638 than a word and loads of that size don't sign extend, we can say
8639 nothing about the high order bits. */
8640 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8641 #ifdef LOAD_EXTEND_OP
8642 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8653 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8654 /* If pointers extend signed and this is a pointer in Pmode, say that
8655 all the bits above ptr_mode are known to be sign bit copies. */
8656 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8658 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8661 if (reg_last_set_value[REGNO (x)] != 0
8662 && reg_last_set_mode[REGNO (x)] == mode
8663 && (reg_last_set_label[REGNO (x)] == label_tick
8664 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8665 && REG_N_SETS (REGNO (x)) == 1
8666 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8668 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8669 return reg_last_set_sign_bit_copies[REGNO (x)];
8671 tem = get_last_value (x);
8673 return num_sign_bit_copies (tem, mode);
8675 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8676 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8677 return reg_sign_bit_copies[REGNO (x)];
8681 #ifdef LOAD_EXTEND_OP
8682 /* Some RISC machines sign-extend all loads of smaller than a word. */
8683 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8684 return MAX (1, ((int) bitwidth
8685 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8690 /* If the constant is negative, take its 1's complement and remask.
8691 Then see how many zero bits we have. */
8692 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8693 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8694 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8695 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8697 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8700 /* If this is a SUBREG for a promoted object that is sign-extended
8701 and we are looking at it in a wider mode, we know that at least the
8702 high-order bits are known to be sign bit copies. */
8704 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8706 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8707 return MAX ((int) bitwidth
8708 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8712 /* For a smaller object, just ignore the high bits. */
8713 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8715 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8716 return MAX (1, (num0
8717 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8721 #ifdef WORD_REGISTER_OPERATIONS
8722 #ifdef LOAD_EXTEND_OP
8723 /* For paradoxical SUBREGs on machines where all register operations
8724 affect the entire register, just look inside. Note that we are
8725 passing MODE to the recursive call, so the number of sign bit copies
8726 will remain relative to that mode, not the inner mode. */
8728 /* This works only if loads sign extend. Otherwise, if we get a
8729 reload for the inner part, it may be loaded from the stack, and
8730 then we lose all sign bit copies that existed before the store
8733 if ((GET_MODE_SIZE (GET_MODE (x))
8734 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8735 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8736 && GET_CODE (SUBREG_REG (x)) == MEM)
8737 return num_sign_bit_copies (SUBREG_REG (x), mode);
8743 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8744 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8748 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8749 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8752 /* For a smaller object, just ignore the high bits. */
8753 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8754 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8758 return num_sign_bit_copies (XEXP (x, 0), mode);
8760 case ROTATE: case ROTATERT:
8761 /* If we are rotating left by a number of bits less than the number
8762 of sign bit copies, we can just subtract that amount from the
8764 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8765 && INTVAL (XEXP (x, 1)) >= 0
8766 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8768 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8769 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8770 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8775 /* In general, this subtracts one sign bit copy. But if the value
8776 is known to be positive, the number of sign bit copies is the
8777 same as that of the input. Finally, if the input has just one bit
8778 that might be nonzero, all the bits are copies of the sign bit. */
8779 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8780 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8781 return num0 > 1 ? num0 - 1 : 1;
8783 nonzero = nonzero_bits (XEXP (x, 0), mode);
8788 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8793 case IOR: case AND: case XOR:
8794 case SMIN: case SMAX: case UMIN: case UMAX:
8795 /* Logical operations will preserve the number of sign-bit copies.
8796 MIN and MAX operations always return one of the operands. */
8797 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8798 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8799 return MIN (num0, num1);
8801 case PLUS: case MINUS:
8802 /* For addition and subtraction, we can have a 1-bit carry. However,
8803 if we are subtracting 1 from a positive number, there will not
8804 be such a carry. Furthermore, if the positive number is known to
8805 be 0 or 1, we know the result is either -1 or 0. */
8807 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8808 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8810 nonzero = nonzero_bits (XEXP (x, 0), mode);
8811 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8812 return (nonzero == 1 || nonzero == 0 ? bitwidth
8813 : bitwidth - floor_log2 (nonzero) - 1);
8816 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8817 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8818 result = MAX (1, MIN (num0, num1) - 1);
8820 #ifdef POINTERS_EXTEND_UNSIGNED
8821 /* If pointers extend signed and this is an addition or subtraction
8822 to a pointer in Pmode, all the bits above ptr_mode are known to be
8824 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8825 && (code == PLUS || code == MINUS)
8826 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8827 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8828 - GET_MODE_BITSIZE (ptr_mode) + 1),
8834 /* The number of bits of the product is the sum of the number of
8835 bits of both terms. However, unless one of the terms if known
8836 to be positive, we must allow for an additional bit since negating
8837 a negative number can remove one sign bit copy. */
8839 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8840 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8842 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8844 && (bitwidth > HOST_BITS_PER_WIDE_INT
8845 || (((nonzero_bits (XEXP (x, 0), mode)
8846 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8847 && ((nonzero_bits (XEXP (x, 1), mode)
8848 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8851 return MAX (1, result);
8854 /* The result must be <= the first operand. If the first operand
8855 has the high bit set, we know nothing about the number of sign
8857 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8859 else if ((nonzero_bits (XEXP (x, 0), mode)
8860 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8863 return num_sign_bit_copies (XEXP (x, 0), mode);
8866 /* The result must be <= the second operand. */
8867 return num_sign_bit_copies (XEXP (x, 1), mode);
8870 /* Similar to unsigned division, except that we have to worry about
8871 the case where the divisor is negative, in which case we have
8873 result = num_sign_bit_copies (XEXP (x, 0), mode);
8875 && (bitwidth > HOST_BITS_PER_WIDE_INT
8876 || (nonzero_bits (XEXP (x, 1), mode)
8877 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8883 result = num_sign_bit_copies (XEXP (x, 1), mode);
8885 && (bitwidth > HOST_BITS_PER_WIDE_INT
8886 || (nonzero_bits (XEXP (x, 1), mode)
8887 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8893 /* Shifts by a constant add to the number of bits equal to the
8895 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8896 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8897 && INTVAL (XEXP (x, 1)) > 0)
8898 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8903 /* Left shifts destroy copies. */
8904 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8905 || INTVAL (XEXP (x, 1)) < 0
8906 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8909 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8910 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8913 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8914 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8915 return MIN (num0, num1);
8917 case EQ: case NE: case GE: case GT: case LE: case LT:
8918 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8919 case GEU: case GTU: case LEU: case LTU:
8920 case UNORDERED: case ORDERED:
8921 /* If the constant is negative, take its 1's complement and remask.
8922 Then see how many zero bits we have. */
8923 nonzero = STORE_FLAG_VALUE;
8924 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8925 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8926 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8928 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8935 /* If we haven't been able to figure it out by one of the above rules,
8936 see if some of the high-order bits are known to be zero. If so,
8937 count those bits and return one less than that amount. If we can't
8938 safely compute the mask for this mode, always return BITWIDTH. */
8940 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8943 nonzero = nonzero_bits (x, mode);
8944 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8945 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8948 /* Return the number of "extended" bits there are in X, when interpreted
8949 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8950 unsigned quantities, this is the number of high-order zero bits.
8951 For signed quantities, this is the number of copies of the sign bit
8952 minus 1. In both case, this function returns the number of "spare"
8953 bits. For example, if two quantities for which this function returns
8954 at least 1 are added, the addition is known not to overflow.
8956 This function will always return 0 unless called during combine, which
8957 implies that it must be called from a define_split. */
8960 extended_count (x, mode, unsignedp)
8962 enum machine_mode mode;
8965 if (nonzero_sign_valid == 0)
8969 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8970 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8971 - floor_log2 (nonzero_bits (x, mode)))
8973 : num_sign_bit_copies (x, mode) - 1);
8976 /* This function is called from `simplify_shift_const' to merge two
8977 outer operations. Specifically, we have already found that we need
8978 to perform operation *POP0 with constant *PCONST0 at the outermost
8979 position. We would now like to also perform OP1 with constant CONST1
8980 (with *POP0 being done last).
8982 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8983 the resulting operation. *PCOMP_P is set to 1 if we would need to
8984 complement the innermost operand, otherwise it is unchanged.
8986 MODE is the mode in which the operation will be done. No bits outside
8987 the width of this mode matter. It is assumed that the width of this mode
8988 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8990 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8991 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8992 result is simply *PCONST0.
8994 If the resulting operation cannot be expressed as one operation, we
8995 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8998 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8999 enum rtx_code *pop0;
9000 HOST_WIDE_INT *pconst0;
9002 HOST_WIDE_INT const1;
9003 enum machine_mode mode;
9006 enum rtx_code op0 = *pop0;
9007 HOST_WIDE_INT const0 = *pconst0;
9009 const0 &= GET_MODE_MASK (mode);
9010 const1 &= GET_MODE_MASK (mode);
9012 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9016 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9019 if (op1 == NIL || op0 == SET)
9022 else if (op0 == NIL)
9023 op0 = op1, const0 = const1;
9025 else if (op0 == op1)
9049 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9050 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9053 /* If the two constants aren't the same, we can't do anything. The
9054 remaining six cases can all be done. */
9055 else if (const0 != const1)
9063 /* (a & b) | b == b */
9065 else /* op1 == XOR */
9066 /* (a ^ b) | b == a | b */
9072 /* (a & b) ^ b == (~a) & b */
9073 op0 = AND, *pcomp_p = 1;
9074 else /* op1 == IOR */
9075 /* (a | b) ^ b == a & ~b */
9076 op0 = AND, *pconst0 = ~const0;
9081 /* (a | b) & b == b */
9083 else /* op1 == XOR */
9084 /* (a ^ b) & b) == (~a) & b */
9091 /* Check for NO-OP cases. */
9092 const0 &= GET_MODE_MASK (mode);
9094 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9096 else if (const0 == 0 && op0 == AND)
9098 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9102 /* ??? Slightly redundant with the above mask, but not entirely.
9103 Moving this above means we'd have to sign-extend the mode mask
9104 for the final test. */
9105 const0 = trunc_int_for_mode (const0, mode);
9113 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9114 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9115 that we started with.
9117 The shift is normally computed in the widest mode we find in VAROP, as
9118 long as it isn't a different number of words than RESULT_MODE. Exceptions
9119 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9122 simplify_shift_const (x, code, result_mode, varop, orig_count)
9125 enum machine_mode result_mode;
9129 enum rtx_code orig_code = code;
9132 enum machine_mode mode = result_mode;
9133 enum machine_mode shift_mode, tmode;
9134 unsigned int mode_words
9135 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9136 /* We form (outer_op (code varop count) (outer_const)). */
9137 enum rtx_code outer_op = NIL;
9138 HOST_WIDE_INT outer_const = 0;
9140 int complement_p = 0;
9143 /* Make sure and truncate the "natural" shift on the way in. We don't
9144 want to do this inside the loop as it makes it more difficult to
9146 #ifdef SHIFT_COUNT_TRUNCATED
9147 if (SHIFT_COUNT_TRUNCATED)
9148 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9151 /* If we were given an invalid count, don't do anything except exactly
9152 what was requested. */
9154 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9159 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9164 /* Unless one of the branches of the `if' in this loop does a `continue',
9165 we will `break' the loop after the `if'. */
9169 /* If we have an operand of (clobber (const_int 0)), just return that
9171 if (GET_CODE (varop) == CLOBBER)
9174 /* If we discovered we had to complement VAROP, leave. Making a NOT
9175 here would cause an infinite loop. */
9179 /* Convert ROTATERT to ROTATE. */
9180 if (code == ROTATERT)
9182 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9184 if (VECTOR_MODE_P (result_mode))
9185 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9187 count = bitsize - count;
9190 /* We need to determine what mode we will do the shift in. If the
9191 shift is a right shift or a ROTATE, we must always do it in the mode
9192 it was originally done in. Otherwise, we can do it in MODE, the
9193 widest mode encountered. */
9195 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9196 ? result_mode : mode);
9198 /* Handle cases where the count is greater than the size of the mode
9199 minus 1. For ASHIFT, use the size minus one as the count (this can
9200 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9201 take the count modulo the size. For other shifts, the result is
9204 Since these shifts are being produced by the compiler by combining
9205 multiple operations, each of which are defined, we know what the
9206 result is supposed to be. */
9208 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9210 if (code == ASHIFTRT)
9211 count = GET_MODE_BITSIZE (shift_mode) - 1;
9212 else if (code == ROTATE || code == ROTATERT)
9213 count %= GET_MODE_BITSIZE (shift_mode);
9216 /* We can't simply return zero because there may be an
9224 /* An arithmetic right shift of a quantity known to be -1 or 0
9226 if (code == ASHIFTRT
9227 && (num_sign_bit_copies (varop, shift_mode)
9228 == GET_MODE_BITSIZE (shift_mode)))
9234 /* If we are doing an arithmetic right shift and discarding all but
9235 the sign bit copies, this is equivalent to doing a shift by the
9236 bitsize minus one. Convert it into that shift because it will often
9237 allow other simplifications. */
9239 if (code == ASHIFTRT
9240 && (count + num_sign_bit_copies (varop, shift_mode)
9241 >= GET_MODE_BITSIZE (shift_mode)))
9242 count = GET_MODE_BITSIZE (shift_mode) - 1;
9244 /* We simplify the tests below and elsewhere by converting
9245 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9246 `make_compound_operation' will convert it to an ASHIFTRT for
9247 those machines (such as VAX) that don't have an LSHIFTRT. */
9248 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9250 && ((nonzero_bits (varop, shift_mode)
9251 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9255 switch (GET_CODE (varop))
9261 new = expand_compound_operation (varop);
9270 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9271 minus the width of a smaller mode, we can do this with a
9272 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9273 if ((code == ASHIFTRT || code == LSHIFTRT)
9274 && ! mode_dependent_address_p (XEXP (varop, 0))
9275 && ! MEM_VOLATILE_P (varop)
9276 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9277 MODE_INT, 1)) != BLKmode)
9279 new = adjust_address_nv (varop, tmode,
9280 BYTES_BIG_ENDIAN ? 0
9281 : count / BITS_PER_UNIT);
9283 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9284 : ZERO_EXTEND, mode, new);
9291 /* Similar to the case above, except that we can only do this if
9292 the resulting mode is the same as that of the underlying
9293 MEM and adjust the address depending on the *bits* endianness
9294 because of the way that bit-field extract insns are defined. */
9295 if ((code == ASHIFTRT || code == LSHIFTRT)
9296 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9297 MODE_INT, 1)) != BLKmode
9298 && tmode == GET_MODE (XEXP (varop, 0)))
9300 if (BITS_BIG_ENDIAN)
9301 new = XEXP (varop, 0);
9304 new = copy_rtx (XEXP (varop, 0));
9305 SUBST (XEXP (new, 0),
9306 plus_constant (XEXP (new, 0),
9307 count / BITS_PER_UNIT));
9310 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9311 : ZERO_EXTEND, mode, new);
9318 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9319 the same number of words as what we've seen so far. Then store
9320 the widest mode in MODE. */
9321 if (subreg_lowpart_p (varop)
9322 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9323 > GET_MODE_SIZE (GET_MODE (varop)))
9324 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9325 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9328 varop = SUBREG_REG (varop);
9329 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9330 mode = GET_MODE (varop);
9336 /* Some machines use MULT instead of ASHIFT because MULT
9337 is cheaper. But it is still better on those machines to
9338 merge two shifts into one. */
9339 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9340 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9343 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9344 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9350 /* Similar, for when divides are cheaper. */
9351 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9352 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9355 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9356 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9362 /* If we are extracting just the sign bit of an arithmetic
9363 right shift, that shift is not needed. However, the sign
9364 bit of a wider mode may be different from what would be
9365 interpreted as the sign bit in a narrower mode, so, if
9366 the result is narrower, don't discard the shift. */
9367 if (code == LSHIFTRT
9368 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9369 && (GET_MODE_BITSIZE (result_mode)
9370 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9372 varop = XEXP (varop, 0);
9376 /* ... fall through ... */
9381 /* Here we have two nested shifts. The result is usually the
9382 AND of a new shift with a mask. We compute the result below. */
9383 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9384 && INTVAL (XEXP (varop, 1)) >= 0
9385 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9386 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9387 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9389 enum rtx_code first_code = GET_CODE (varop);
9390 unsigned int first_count = INTVAL (XEXP (varop, 1));
9391 unsigned HOST_WIDE_INT mask;
9394 /* We have one common special case. We can't do any merging if
9395 the inner code is an ASHIFTRT of a smaller mode. However, if
9396 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9397 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9398 we can convert it to
9399 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9400 This simplifies certain SIGN_EXTEND operations. */
9401 if (code == ASHIFT && first_code == ASHIFTRT
9402 && count == (unsigned int)
9403 (GET_MODE_BITSIZE (result_mode)
9404 - GET_MODE_BITSIZE (GET_MODE (varop))))
9406 /* C3 has the low-order C1 bits zero. */
9408 mask = (GET_MODE_MASK (mode)
9409 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9411 varop = simplify_and_const_int (NULL_RTX, result_mode,
9412 XEXP (varop, 0), mask);
9413 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9415 count = first_count;
9420 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9421 than C1 high-order bits equal to the sign bit, we can convert
9422 this to either an ASHIFT or an ASHIFTRT depending on the
9425 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9427 if (code == ASHIFTRT && first_code == ASHIFT
9428 && GET_MODE (varop) == shift_mode
9429 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9432 varop = XEXP (varop, 0);
9434 signed_count = count - first_count;
9435 if (signed_count < 0)
9436 count = -signed_count, code = ASHIFT;
9438 count = signed_count;
9443 /* There are some cases we can't do. If CODE is ASHIFTRT,
9444 we can only do this if FIRST_CODE is also ASHIFTRT.
9446 We can't do the case when CODE is ROTATE and FIRST_CODE is
9449 If the mode of this shift is not the mode of the outer shift,
9450 we can't do this if either shift is a right shift or ROTATE.
9452 Finally, we can't do any of these if the mode is too wide
9453 unless the codes are the same.
9455 Handle the case where the shift codes are the same
9458 if (code == first_code)
9460 if (GET_MODE (varop) != result_mode
9461 && (code == ASHIFTRT || code == LSHIFTRT
9465 count += first_count;
9466 varop = XEXP (varop, 0);
9470 if (code == ASHIFTRT
9471 || (code == ROTATE && first_code == ASHIFTRT)
9472 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9473 || (GET_MODE (varop) != result_mode
9474 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9475 || first_code == ROTATE
9476 || code == ROTATE)))
9479 /* To compute the mask to apply after the shift, shift the
9480 nonzero bits of the inner shift the same way the
9481 outer shift will. */
9483 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9486 = simplify_binary_operation (code, result_mode, mask_rtx,
9489 /* Give up if we can't compute an outer operation to use. */
9491 || GET_CODE (mask_rtx) != CONST_INT
9492 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9494 result_mode, &complement_p))
9497 /* If the shifts are in the same direction, we add the
9498 counts. Otherwise, we subtract them. */
9499 signed_count = count;
9500 if ((code == ASHIFTRT || code == LSHIFTRT)
9501 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9502 signed_count += first_count;
9504 signed_count -= first_count;
9506 /* If COUNT is positive, the new shift is usually CODE,
9507 except for the two exceptions below, in which case it is
9508 FIRST_CODE. If the count is negative, FIRST_CODE should
9510 if (signed_count > 0
9511 && ((first_code == ROTATE && code == ASHIFT)
9512 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9513 code = first_code, count = signed_count;
9514 else if (signed_count < 0)
9515 code = first_code, count = -signed_count;
9517 count = signed_count;
9519 varop = XEXP (varop, 0);
9523 /* If we have (A << B << C) for any shift, we can convert this to
9524 (A << C << B). This wins if A is a constant. Only try this if
9525 B is not a constant. */
9527 else if (GET_CODE (varop) == code
9528 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9530 = simplify_binary_operation (code, mode,
9534 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9541 /* Make this fit the case below. */
9542 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9543 GEN_INT (GET_MODE_MASK (mode)));
9549 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9550 with C the size of VAROP - 1 and the shift is logical if
9551 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9552 we have an (le X 0) operation. If we have an arithmetic shift
9553 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9554 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9556 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9557 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9558 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9559 && (code == LSHIFTRT || code == ASHIFTRT)
9560 && count == (unsigned int)
9561 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9562 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9565 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9568 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9569 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9574 /* If we have (shift (logical)), move the logical to the outside
9575 to allow it to possibly combine with another logical and the
9576 shift to combine with another shift. This also canonicalizes to
9577 what a ZERO_EXTRACT looks like. Also, some machines have
9578 (and (shift)) insns. */
9580 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9581 && (new = simplify_binary_operation (code, result_mode,
9583 GEN_INT (count))) != 0
9584 && GET_CODE (new) == CONST_INT
9585 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9586 INTVAL (new), result_mode, &complement_p))
9588 varop = XEXP (varop, 0);
9592 /* If we can't do that, try to simplify the shift in each arm of the
9593 logical expression, make a new logical expression, and apply
9594 the inverse distributive law. */
9596 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9597 XEXP (varop, 0), count);
9598 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9599 XEXP (varop, 1), count);
9601 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9602 varop = apply_distributive_law (varop);
9609 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9610 says that the sign bit can be tested, FOO has mode MODE, C is
9611 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9612 that may be nonzero. */
9613 if (code == LSHIFTRT
9614 && XEXP (varop, 1) == const0_rtx
9615 && GET_MODE (XEXP (varop, 0)) == result_mode
9616 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9617 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9618 && ((STORE_FLAG_VALUE
9619 & ((HOST_WIDE_INT) 1
9620 < (GET_MODE_BITSIZE (result_mode) - 1))))
9621 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9622 && merge_outer_ops (&outer_op, &outer_const, XOR,
9623 (HOST_WIDE_INT) 1, result_mode,
9626 varop = XEXP (varop, 0);
9633 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9634 than the number of bits in the mode is equivalent to A. */
9635 if (code == LSHIFTRT
9636 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9637 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9639 varop = XEXP (varop, 0);
9644 /* NEG commutes with ASHIFT since it is multiplication. Move the
9645 NEG outside to allow shifts to combine. */
9647 && merge_outer_ops (&outer_op, &outer_const, NEG,
9648 (HOST_WIDE_INT) 0, result_mode,
9651 varop = XEXP (varop, 0);
9657 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9658 is one less than the number of bits in the mode is
9659 equivalent to (xor A 1). */
9660 if (code == LSHIFTRT
9661 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9662 && XEXP (varop, 1) == constm1_rtx
9663 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9664 && merge_outer_ops (&outer_op, &outer_const, XOR,
9665 (HOST_WIDE_INT) 1, result_mode,
9669 varop = XEXP (varop, 0);
9673 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9674 that might be nonzero in BAR are those being shifted out and those
9675 bits are known zero in FOO, we can replace the PLUS with FOO.
9676 Similarly in the other operand order. This code occurs when
9677 we are computing the size of a variable-size array. */
9679 if ((code == ASHIFTRT || code == LSHIFTRT)
9680 && count < HOST_BITS_PER_WIDE_INT
9681 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9682 && (nonzero_bits (XEXP (varop, 1), result_mode)
9683 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9685 varop = XEXP (varop, 0);
9688 else if ((code == ASHIFTRT || code == LSHIFTRT)
9689 && count < HOST_BITS_PER_WIDE_INT
9690 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9691 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9693 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9694 & nonzero_bits (XEXP (varop, 1),
9697 varop = XEXP (varop, 1);
9701 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9703 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9704 && (new = simplify_binary_operation (ASHIFT, result_mode,
9706 GEN_INT (count))) != 0
9707 && GET_CODE (new) == CONST_INT
9708 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9709 INTVAL (new), result_mode, &complement_p))
9711 varop = XEXP (varop, 0);
9717 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9718 with C the size of VAROP - 1 and the shift is logical if
9719 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9720 we have a (gt X 0) operation. If the shift is arithmetic with
9721 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9722 we have a (neg (gt X 0)) operation. */
9724 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9725 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9726 && count == (unsigned int)
9727 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9728 && (code == LSHIFTRT || code == ASHIFTRT)
9729 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9730 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9732 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9735 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9738 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9739 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9746 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9747 if the truncate does not affect the value. */
9748 if (code == LSHIFTRT
9749 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9750 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9751 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9752 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9753 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9755 rtx varop_inner = XEXP (varop, 0);
9758 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9759 XEXP (varop_inner, 0),
9761 (count + INTVAL (XEXP (varop_inner, 1))));
9762 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9775 /* We need to determine what mode to do the shift in. If the shift is
9776 a right shift or ROTATE, we must always do it in the mode it was
9777 originally done in. Otherwise, we can do it in MODE, the widest mode
9778 encountered. The code we care about is that of the shift that will
9779 actually be done, not the shift that was originally requested. */
9781 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9782 ? result_mode : mode);
9784 /* We have now finished analyzing the shift. The result should be
9785 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9786 OUTER_OP is non-NIL, it is an operation that needs to be applied
9787 to the result of the shift. OUTER_CONST is the relevant constant,
9788 but we must turn off all bits turned off in the shift.
9790 If we were passed a value for X, see if we can use any pieces of
9791 it. If not, make new rtx. */
9793 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9794 && GET_CODE (XEXP (x, 1)) == CONST_INT
9795 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9796 const_rtx = XEXP (x, 1);
9798 const_rtx = GEN_INT (count);
9800 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9801 && GET_MODE (XEXP (x, 0)) == shift_mode
9802 && SUBREG_REG (XEXP (x, 0)) == varop)
9803 varop = XEXP (x, 0);
9804 else if (GET_MODE (varop) != shift_mode)
9805 varop = gen_lowpart_for_combine (shift_mode, varop);
9807 /* If we can't make the SUBREG, try to return what we were given. */
9808 if (GET_CODE (varop) == CLOBBER)
9809 return x ? x : varop;
9811 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9815 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9817 /* If we have an outer operation and we just made a shift, it is
9818 possible that we could have simplified the shift were it not
9819 for the outer operation. So try to do the simplification
9822 if (outer_op != NIL && GET_CODE (x) == code
9823 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9824 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9825 INTVAL (XEXP (x, 1)));
9827 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9828 turn off all the bits that the shift would have turned off. */
9829 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9830 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9831 GET_MODE_MASK (result_mode) >> orig_count);
9833 /* Do the remainder of the processing in RESULT_MODE. */
9834 x = gen_lowpart_for_combine (result_mode, x);
9836 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9839 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9841 if (outer_op != NIL)
9843 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9844 outer_const = trunc_int_for_mode (outer_const, result_mode);
9846 if (outer_op == AND)
9847 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9848 else if (outer_op == SET)
9849 /* This means that we have determined that the result is
9850 equivalent to a constant. This should be rare. */
9851 x = GEN_INT (outer_const);
9852 else if (GET_RTX_CLASS (outer_op) == '1')
9853 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9855 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9861 /* Like recog, but we receive the address of a pointer to a new pattern.
9862 We try to match the rtx that the pointer points to.
9863 If that fails, we may try to modify or replace the pattern,
9864 storing the replacement into the same pointer object.
9866 Modifications include deletion or addition of CLOBBERs.
9868 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9869 the CLOBBERs are placed.
9871 The value is the final insn code from the pattern ultimately matched,
9875 recog_for_combine (pnewpat, insn, pnotes)
9881 int insn_code_number;
9882 int num_clobbers_to_add = 0;
9887 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9888 we use to indicate that something didn't match. If we find such a
9889 thing, force rejection. */
9890 if (GET_CODE (pat) == PARALLEL)
9891 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9892 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9893 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9896 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9897 instruction for pattern recognition. */
9898 dummy_insn = shallow_copy_rtx (insn);
9899 PATTERN (dummy_insn) = pat;
9900 REG_NOTES (dummy_insn) = 0;
9902 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9904 /* If it isn't, there is the possibility that we previously had an insn
9905 that clobbered some register as a side effect, but the combined
9906 insn doesn't need to do that. So try once more without the clobbers
9907 unless this represents an ASM insn. */
9909 if (insn_code_number < 0 && ! check_asm_operands (pat)
9910 && GET_CODE (pat) == PARALLEL)
9914 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9915 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9918 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9922 SUBST_INT (XVECLEN (pat, 0), pos);
9925 pat = XVECEXP (pat, 0, 0);
9927 PATTERN (dummy_insn) = pat;
9928 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9931 /* Recognize all noop sets, these will be killed by followup pass. */
9932 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9933 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9935 /* If we had any clobbers to add, make a new pattern than contains
9936 them. Then check to make sure that all of them are dead. */
9937 if (num_clobbers_to_add)
9939 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9940 rtvec_alloc (GET_CODE (pat) == PARALLEL
9942 + num_clobbers_to_add)
9943 : num_clobbers_to_add + 1));
9945 if (GET_CODE (pat) == PARALLEL)
9946 for (i = 0; i < XVECLEN (pat, 0); i++)
9947 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9949 XVECEXP (newpat, 0, 0) = pat;
9951 add_clobbers (newpat, insn_code_number);
9953 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9954 i < XVECLEN (newpat, 0); i++)
9956 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9957 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9959 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9960 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9968 return insn_code_number;
9971 /* Like gen_lowpart but for use by combine. In combine it is not possible
9972 to create any new pseudoregs. However, it is safe to create
9973 invalid memory addresses, because combine will try to recognize
9974 them and all they will do is make the combine attempt fail.
9976 If for some reason this cannot do its job, an rtx
9977 (clobber (const_int 0)) is returned.
9978 An insn containing that will not be recognized. */
9983 gen_lowpart_for_combine (mode, x)
9984 enum machine_mode mode;
9989 if (GET_MODE (x) == mode)
9992 /* We can only support MODE being wider than a word if X is a
9993 constant integer or has a mode the same size. */
9995 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9996 && ! ((GET_MODE (x) == VOIDmode
9997 && (GET_CODE (x) == CONST_INT
9998 || GET_CODE (x) == CONST_DOUBLE))
9999 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10000 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10002 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10003 won't know what to do. So we will strip off the SUBREG here and
10004 process normally. */
10005 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10007 x = SUBREG_REG (x);
10008 if (GET_MODE (x) == mode)
10012 result = gen_lowpart_common (mode, x);
10013 #ifdef CANNOT_CHANGE_MODE_CLASS
10015 && GET_CODE (result) == SUBREG
10016 && GET_CODE (SUBREG_REG (result)) == REG
10017 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10018 SET_REGNO_REG_SET (&subregs_of_mode[GET_MODE (result)],
10019 REGNO (SUBREG_REG (result)));
10025 if (GET_CODE (x) == MEM)
10029 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10031 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10032 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10034 /* If we want to refer to something bigger than the original memref,
10035 generate a perverse subreg instead. That will force a reload
10036 of the original memref X. */
10037 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10038 return gen_rtx_SUBREG (mode, x, 0);
10040 if (WORDS_BIG_ENDIAN)
10041 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10042 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10044 if (BYTES_BIG_ENDIAN)
10046 /* Adjust the address so that the address-after-the-data is
10048 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10049 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10052 return adjust_address_nv (x, mode, offset);
10055 /* If X is a comparison operator, rewrite it in a new mode. This
10056 probably won't match, but may allow further simplifications. */
10057 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10058 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10060 /* If we couldn't simplify X any other way, just enclose it in a
10061 SUBREG. Normally, this SUBREG won't match, but some patterns may
10062 include an explicit SUBREG or we may simplify it further in combine. */
10067 enum machine_mode sub_mode = GET_MODE (x);
10069 offset = subreg_lowpart_offset (mode, sub_mode);
10070 if (sub_mode == VOIDmode)
10072 sub_mode = int_mode_for_mode (mode);
10073 x = gen_lowpart_common (sub_mode, x);
10075 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10078 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10082 /* These routines make binary and unary operations by first seeing if they
10083 fold; if not, a new expression is allocated. */
10086 gen_binary (code, mode, op0, op1)
10087 enum rtx_code code;
10088 enum machine_mode mode;
10094 if (GET_RTX_CLASS (code) == 'c'
10095 && swap_commutative_operands_p (op0, op1))
10096 tem = op0, op0 = op1, op1 = tem;
10098 if (GET_RTX_CLASS (code) == '<')
10100 enum machine_mode op_mode = GET_MODE (op0);
10102 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10103 just (REL_OP X Y). */
10104 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10106 op1 = XEXP (op0, 1);
10107 op0 = XEXP (op0, 0);
10108 op_mode = GET_MODE (op0);
10111 if (op_mode == VOIDmode)
10112 op_mode = GET_MODE (op1);
10113 result = simplify_relational_operation (code, op_mode, op0, op1);
10116 result = simplify_binary_operation (code, mode, op0, op1);
10121 /* Put complex operands first and constants second. */
10122 if (GET_RTX_CLASS (code) == 'c'
10123 && swap_commutative_operands_p (op0, op1))
10124 return gen_rtx_fmt_ee (code, mode, op1, op0);
10126 /* If we are turning off bits already known off in OP0, we need not do
10128 else if (code == AND && GET_CODE (op1) == CONST_INT
10129 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10130 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10133 return gen_rtx_fmt_ee (code, mode, op0, op1);
10136 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10137 comparison code that will be tested.
10139 The result is a possibly different comparison code to use. *POP0 and
10140 *POP1 may be updated.
10142 It is possible that we might detect that a comparison is either always
10143 true or always false. However, we do not perform general constant
10144 folding in combine, so this knowledge isn't useful. Such tautologies
10145 should have been detected earlier. Hence we ignore all such cases. */
10147 static enum rtx_code
10148 simplify_comparison (code, pop0, pop1)
10149 enum rtx_code code;
10157 enum machine_mode mode, tmode;
10159 /* Try a few ways of applying the same transformation to both operands. */
10162 #ifndef WORD_REGISTER_OPERATIONS
10163 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10164 so check specially. */
10165 if (code != GTU && code != GEU && code != LTU && code != LEU
10166 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10167 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10168 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10169 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10170 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10171 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10172 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10173 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10174 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10175 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10176 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10177 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10178 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10179 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10180 && (INTVAL (XEXP (op0, 1))
10181 == (GET_MODE_BITSIZE (GET_MODE (op0))
10182 - (GET_MODE_BITSIZE
10183 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10185 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10186 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10190 /* If both operands are the same constant shift, see if we can ignore the
10191 shift. We can if the shift is a rotate or if the bits shifted out of
10192 this shift are known to be zero for both inputs and if the type of
10193 comparison is compatible with the shift. */
10194 if (GET_CODE (op0) == GET_CODE (op1)
10195 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10196 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10197 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10198 && (code != GT && code != LT && code != GE && code != LE))
10199 || (GET_CODE (op0) == ASHIFTRT
10200 && (code != GTU && code != LTU
10201 && code != GEU && code != LEU)))
10202 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10203 && INTVAL (XEXP (op0, 1)) >= 0
10204 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10205 && XEXP (op0, 1) == XEXP (op1, 1))
10207 enum machine_mode mode = GET_MODE (op0);
10208 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10209 int shift_count = INTVAL (XEXP (op0, 1));
10211 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10212 mask &= (mask >> shift_count) << shift_count;
10213 else if (GET_CODE (op0) == ASHIFT)
10214 mask = (mask & (mask << shift_count)) >> shift_count;
10216 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10217 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10218 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10223 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10224 SUBREGs are of the same mode, and, in both cases, the AND would
10225 be redundant if the comparison was done in the narrower mode,
10226 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10227 and the operand's possibly nonzero bits are 0xffffff01; in that case
10228 if we only care about QImode, we don't need the AND). This case
10229 occurs if the output mode of an scc insn is not SImode and
10230 STORE_FLAG_VALUE == 1 (e.g., the 386).
10232 Similarly, check for a case where the AND's are ZERO_EXTEND
10233 operations from some narrower mode even though a SUBREG is not
10236 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10237 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10238 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10240 rtx inner_op0 = XEXP (op0, 0);
10241 rtx inner_op1 = XEXP (op1, 0);
10242 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10243 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10246 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10247 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10248 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10249 && (GET_MODE (SUBREG_REG (inner_op0))
10250 == GET_MODE (SUBREG_REG (inner_op1)))
10251 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10252 <= HOST_BITS_PER_WIDE_INT)
10253 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10254 GET_MODE (SUBREG_REG (inner_op0)))))
10255 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10256 GET_MODE (SUBREG_REG (inner_op1))))))
10258 op0 = SUBREG_REG (inner_op0);
10259 op1 = SUBREG_REG (inner_op1);
10261 /* The resulting comparison is always unsigned since we masked
10262 off the original sign bit. */
10263 code = unsigned_condition (code);
10269 for (tmode = GET_CLASS_NARROWEST_MODE
10270 (GET_MODE_CLASS (GET_MODE (op0)));
10271 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10272 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10274 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10275 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10276 code = unsigned_condition (code);
10285 /* If both operands are NOT, we can strip off the outer operation
10286 and adjust the comparison code for swapped operands; similarly for
10287 NEG, except that this must be an equality comparison. */
10288 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10289 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10290 && (code == EQ || code == NE)))
10291 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10297 /* If the first operand is a constant, swap the operands and adjust the
10298 comparison code appropriately, but don't do this if the second operand
10299 is already a constant integer. */
10300 if (swap_commutative_operands_p (op0, op1))
10302 tem = op0, op0 = op1, op1 = tem;
10303 code = swap_condition (code);
10306 /* We now enter a loop during which we will try to simplify the comparison.
10307 For the most part, we only are concerned with comparisons with zero,
10308 but some things may really be comparisons with zero but not start
10309 out looking that way. */
10311 while (GET_CODE (op1) == CONST_INT)
10313 enum machine_mode mode = GET_MODE (op0);
10314 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10315 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10316 int equality_comparison_p;
10317 int sign_bit_comparison_p;
10318 int unsigned_comparison_p;
10319 HOST_WIDE_INT const_op;
10321 /* We only want to handle integral modes. This catches VOIDmode,
10322 CCmode, and the floating-point modes. An exception is that we
10323 can handle VOIDmode if OP0 is a COMPARE or a comparison
10326 if (GET_MODE_CLASS (mode) != MODE_INT
10327 && ! (mode == VOIDmode
10328 && (GET_CODE (op0) == COMPARE
10329 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10332 /* Get the constant we are comparing against and turn off all bits
10333 not on in our mode. */
10334 const_op = INTVAL (op1);
10335 if (mode != VOIDmode)
10336 const_op = trunc_int_for_mode (const_op, mode);
10337 op1 = GEN_INT (const_op);
10339 /* If we are comparing against a constant power of two and the value
10340 being compared can only have that single bit nonzero (e.g., it was
10341 `and'ed with that bit), we can replace this with a comparison
10344 && (code == EQ || code == NE || code == GE || code == GEU
10345 || code == LT || code == LTU)
10346 && mode_width <= HOST_BITS_PER_WIDE_INT
10347 && exact_log2 (const_op) >= 0
10348 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10350 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10351 op1 = const0_rtx, const_op = 0;
10354 /* Similarly, if we are comparing a value known to be either -1 or
10355 0 with -1, change it to the opposite comparison against zero. */
10358 && (code == EQ || code == NE || code == GT || code == LE
10359 || code == GEU || code == LTU)
10360 && num_sign_bit_copies (op0, mode) == mode_width)
10362 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10363 op1 = const0_rtx, const_op = 0;
10366 /* Do some canonicalizations based on the comparison code. We prefer
10367 comparisons against zero and then prefer equality comparisons.
10368 If we can reduce the size of a constant, we will do that too. */
10373 /* < C is equivalent to <= (C - 1) */
10377 op1 = GEN_INT (const_op);
10379 /* ... fall through to LE case below. */
10385 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10389 op1 = GEN_INT (const_op);
10393 /* If we are doing a <= 0 comparison on a value known to have
10394 a zero sign bit, we can replace this with == 0. */
10395 else if (const_op == 0
10396 && mode_width <= HOST_BITS_PER_WIDE_INT
10397 && (nonzero_bits (op0, mode)
10398 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10403 /* >= C is equivalent to > (C - 1). */
10407 op1 = GEN_INT (const_op);
10409 /* ... fall through to GT below. */
10415 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10419 op1 = GEN_INT (const_op);
10423 /* If we are doing a > 0 comparison on a value known to have
10424 a zero sign bit, we can replace this with != 0. */
10425 else if (const_op == 0
10426 && mode_width <= HOST_BITS_PER_WIDE_INT
10427 && (nonzero_bits (op0, mode)
10428 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10433 /* < C is equivalent to <= (C - 1). */
10437 op1 = GEN_INT (const_op);
10439 /* ... fall through ... */
10442 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10443 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10444 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10446 const_op = 0, op1 = const0_rtx;
10454 /* unsigned <= 0 is equivalent to == 0 */
10458 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10459 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10460 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10462 const_op = 0, op1 = const0_rtx;
10468 /* >= C is equivalent to < (C - 1). */
10472 op1 = GEN_INT (const_op);
10474 /* ... fall through ... */
10477 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10478 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10479 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10481 const_op = 0, op1 = const0_rtx;
10489 /* unsigned > 0 is equivalent to != 0 */
10493 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10494 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10495 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10497 const_op = 0, op1 = const0_rtx;
10506 /* Compute some predicates to simplify code below. */
10508 equality_comparison_p = (code == EQ || code == NE);
10509 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10510 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10513 /* If this is a sign bit comparison and we can do arithmetic in
10514 MODE, say that we will only be needing the sign bit of OP0. */
10515 if (sign_bit_comparison_p
10516 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10517 op0 = force_to_mode (op0, mode,
10519 << (GET_MODE_BITSIZE (mode) - 1)),
10522 /* Now try cases based on the opcode of OP0. If none of the cases
10523 does a "continue", we exit this loop immediately after the
10526 switch (GET_CODE (op0))
10529 /* If we are extracting a single bit from a variable position in
10530 a constant that has only a single bit set and are comparing it
10531 with zero, we can convert this into an equality comparison
10532 between the position and the location of the single bit. */
10534 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10535 && XEXP (op0, 1) == const1_rtx
10536 && equality_comparison_p && const_op == 0
10537 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10539 if (BITS_BIG_ENDIAN)
10541 enum machine_mode new_mode
10542 = mode_for_extraction (EP_extzv, 1);
10543 if (new_mode == MAX_MACHINE_MODE)
10544 i = BITS_PER_WORD - 1 - i;
10548 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10552 op0 = XEXP (op0, 2);
10556 /* Result is nonzero iff shift count is equal to I. */
10557 code = reverse_condition (code);
10561 /* ... fall through ... */
10564 tem = expand_compound_operation (op0);
10573 /* If testing for equality, we can take the NOT of the constant. */
10574 if (equality_comparison_p
10575 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10577 op0 = XEXP (op0, 0);
10582 /* If just looking at the sign bit, reverse the sense of the
10584 if (sign_bit_comparison_p)
10586 op0 = XEXP (op0, 0);
10587 code = (code == GE ? LT : GE);
10593 /* If testing for equality, we can take the NEG of the constant. */
10594 if (equality_comparison_p
10595 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10597 op0 = XEXP (op0, 0);
10602 /* The remaining cases only apply to comparisons with zero. */
10606 /* When X is ABS or is known positive,
10607 (neg X) is < 0 if and only if X != 0. */
10609 if (sign_bit_comparison_p
10610 && (GET_CODE (XEXP (op0, 0)) == ABS
10611 || (mode_width <= HOST_BITS_PER_WIDE_INT
10612 && (nonzero_bits (XEXP (op0, 0), mode)
10613 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10615 op0 = XEXP (op0, 0);
10616 code = (code == LT ? NE : EQ);
10620 /* If we have NEG of something whose two high-order bits are the
10621 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10622 if (num_sign_bit_copies (op0, mode) >= 2)
10624 op0 = XEXP (op0, 0);
10625 code = swap_condition (code);
10631 /* If we are testing equality and our count is a constant, we
10632 can perform the inverse operation on our RHS. */
10633 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10634 && (tem = simplify_binary_operation (ROTATERT, mode,
10635 op1, XEXP (op0, 1))) != 0)
10637 op0 = XEXP (op0, 0);
10642 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10643 a particular bit. Convert it to an AND of a constant of that
10644 bit. This will be converted into a ZERO_EXTRACT. */
10645 if (const_op == 0 && sign_bit_comparison_p
10646 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10647 && mode_width <= HOST_BITS_PER_WIDE_INT)
10649 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10652 - INTVAL (XEXP (op0, 1)))));
10653 code = (code == LT ? NE : EQ);
10657 /* Fall through. */
10660 /* ABS is ignorable inside an equality comparison with zero. */
10661 if (const_op == 0 && equality_comparison_p)
10663 op0 = XEXP (op0, 0);
10669 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10670 to (compare FOO CONST) if CONST fits in FOO's mode and we
10671 are either testing inequality or have an unsigned comparison
10672 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10673 if (! unsigned_comparison_p
10674 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10675 <= HOST_BITS_PER_WIDE_INT)
10676 && ((unsigned HOST_WIDE_INT) const_op
10677 < (((unsigned HOST_WIDE_INT) 1
10678 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10680 op0 = XEXP (op0, 0);
10686 /* Check for the case where we are comparing A - C1 with C2,
10687 both constants are smaller than 1/2 the maximum positive
10688 value in MODE, and the comparison is equality or unsigned.
10689 In that case, if A is either zero-extended to MODE or has
10690 sufficient sign bits so that the high-order bit in MODE
10691 is a copy of the sign in the inner mode, we can prove that it is
10692 safe to do the operation in the wider mode. This simplifies
10693 many range checks. */
10695 if (mode_width <= HOST_BITS_PER_WIDE_INT
10696 && subreg_lowpart_p (op0)
10697 && GET_CODE (SUBREG_REG (op0)) == PLUS
10698 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10699 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10700 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10701 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10702 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10703 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10704 GET_MODE (SUBREG_REG (op0)))
10705 & ~GET_MODE_MASK (mode))
10706 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10707 GET_MODE (SUBREG_REG (op0)))
10709 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10710 - GET_MODE_BITSIZE (mode)))))
10712 op0 = SUBREG_REG (op0);
10716 /* If the inner mode is narrower and we are extracting the low part,
10717 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10718 if (subreg_lowpart_p (op0)
10719 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10720 /* Fall through */ ;
10724 /* ... fall through ... */
10727 if ((unsigned_comparison_p || equality_comparison_p)
10728 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10729 <= HOST_BITS_PER_WIDE_INT)
10730 && ((unsigned HOST_WIDE_INT) const_op
10731 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10733 op0 = XEXP (op0, 0);
10739 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10740 this for equality comparisons due to pathological cases involving
10742 if (equality_comparison_p
10743 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10744 op1, XEXP (op0, 1))))
10746 op0 = XEXP (op0, 0);
10751 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10752 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10753 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10755 op0 = XEXP (XEXP (op0, 0), 0);
10756 code = (code == LT ? EQ : NE);
10762 /* We used to optimize signed comparisons against zero, but that
10763 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10764 arrive here as equality comparisons, or (GEU, LTU) are
10765 optimized away. No need to special-case them. */
10767 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10768 (eq B (minus A C)), whichever simplifies. We can only do
10769 this for equality comparisons due to pathological cases involving
10771 if (equality_comparison_p
10772 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10773 XEXP (op0, 1), op1)))
10775 op0 = XEXP (op0, 0);
10780 if (equality_comparison_p
10781 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10782 XEXP (op0, 0), op1)))
10784 op0 = XEXP (op0, 1);
10789 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10790 of bits in X minus 1, is one iff X > 0. */
10791 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10792 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10793 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10795 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10797 op0 = XEXP (op0, 1);
10798 code = (code == GE ? LE : GT);
10804 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10805 if C is zero or B is a constant. */
10806 if (equality_comparison_p
10807 && 0 != (tem = simplify_binary_operation (XOR, mode,
10808 XEXP (op0, 1), op1)))
10810 op0 = XEXP (op0, 0);
10817 case UNEQ: case LTGT:
10818 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10819 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10820 case UNORDERED: case ORDERED:
10821 /* We can't do anything if OP0 is a condition code value, rather
10822 than an actual data value. */
10825 || XEXP (op0, 0) == cc0_rtx
10827 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10830 /* Get the two operands being compared. */
10831 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10832 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10834 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10836 /* Check for the cases where we simply want the result of the
10837 earlier test or the opposite of that result. */
10838 if (code == NE || code == EQ
10839 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10840 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10841 && (STORE_FLAG_VALUE
10842 & (((HOST_WIDE_INT) 1
10843 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10844 && (code == LT || code == GE)))
10846 enum rtx_code new_code;
10847 if (code == LT || code == NE)
10848 new_code = GET_CODE (op0);
10850 new_code = combine_reversed_comparison_code (op0);
10852 if (new_code != UNKNOWN)
10863 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10865 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10866 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10867 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10869 op0 = XEXP (op0, 1);
10870 code = (code == GE ? GT : LE);
10876 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10877 will be converted to a ZERO_EXTRACT later. */
10878 if (const_op == 0 && equality_comparison_p
10879 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10880 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10882 op0 = simplify_and_const_int
10883 (op0, mode, gen_rtx_LSHIFTRT (mode,
10885 XEXP (XEXP (op0, 0), 1)),
10886 (HOST_WIDE_INT) 1);
10890 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10891 zero and X is a comparison and C1 and C2 describe only bits set
10892 in STORE_FLAG_VALUE, we can compare with X. */
10893 if (const_op == 0 && equality_comparison_p
10894 && mode_width <= HOST_BITS_PER_WIDE_INT
10895 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10896 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10897 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10898 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10899 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10901 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10902 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10903 if ((~STORE_FLAG_VALUE & mask) == 0
10904 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10905 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10906 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10908 op0 = XEXP (XEXP (op0, 0), 0);
10913 /* If we are doing an equality comparison of an AND of a bit equal
10914 to the sign bit, replace this with a LT or GE comparison of
10915 the underlying value. */
10916 if (equality_comparison_p
10918 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10919 && mode_width <= HOST_BITS_PER_WIDE_INT
10920 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10921 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10923 op0 = XEXP (op0, 0);
10924 code = (code == EQ ? GE : LT);
10928 /* If this AND operation is really a ZERO_EXTEND from a narrower
10929 mode, the constant fits within that mode, and this is either an
10930 equality or unsigned comparison, try to do this comparison in
10931 the narrower mode. */
10932 if ((equality_comparison_p || unsigned_comparison_p)
10933 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10934 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10935 & GET_MODE_MASK (mode))
10937 && const_op >> i == 0
10938 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10940 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10944 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10945 in both M1 and M2 and the SUBREG is either paradoxical or
10946 represents the low part, permute the SUBREG and the AND and
10948 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10949 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10950 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10951 As originally written the upper bits have a defined value
10952 due to the AND operation. However, if we commute the AND
10953 inside the SUBREG then they no longer have defined values
10954 and the meaning of the code has been changed. */
10956 #ifdef WORD_REGISTER_OPERATIONS
10958 > (GET_MODE_BITSIZE
10959 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10960 && mode_width <= BITS_PER_WORD)
10963 <= (GET_MODE_BITSIZE
10964 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10965 && subreg_lowpart_p (XEXP (op0, 0))))
10966 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10967 && mode_width <= HOST_BITS_PER_WIDE_INT
10968 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10969 <= HOST_BITS_PER_WIDE_INT)
10970 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10971 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10972 & INTVAL (XEXP (op0, 1)))
10973 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10974 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10975 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10979 = gen_lowpart_for_combine
10981 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10982 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10986 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10987 (eq (and (lshiftrt X) 1) 0). */
10988 if (const_op == 0 && equality_comparison_p
10989 && XEXP (op0, 1) == const1_rtx
10990 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10991 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10993 op0 = simplify_and_const_int
10995 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10996 XEXP (XEXP (op0, 0), 1)),
10997 (HOST_WIDE_INT) 1);
10998 code = (code == NE ? EQ : NE);
11004 /* If we have (compare (ashift FOO N) (const_int C)) and
11005 the high order N bits of FOO (N+1 if an inequality comparison)
11006 are known to be zero, we can do this by comparing FOO with C
11007 shifted right N bits so long as the low-order N bits of C are
11009 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11010 && INTVAL (XEXP (op0, 1)) >= 0
11011 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11012 < HOST_BITS_PER_WIDE_INT)
11014 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11015 && mode_width <= HOST_BITS_PER_WIDE_INT
11016 && (nonzero_bits (XEXP (op0, 0), mode)
11017 & ~(mask >> (INTVAL (XEXP (op0, 1))
11018 + ! equality_comparison_p))) == 0)
11020 /* We must perform a logical shift, not an arithmetic one,
11021 as we want the top N bits of C to be zero. */
11022 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11024 temp >>= INTVAL (XEXP (op0, 1));
11025 op1 = gen_int_mode (temp, mode);
11026 op0 = XEXP (op0, 0);
11030 /* If we are doing a sign bit comparison, it means we are testing
11031 a particular bit. Convert it to the appropriate AND. */
11032 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11033 && mode_width <= HOST_BITS_PER_WIDE_INT)
11035 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11038 - INTVAL (XEXP (op0, 1)))));
11039 code = (code == LT ? NE : EQ);
11043 /* If this an equality comparison with zero and we are shifting
11044 the low bit to the sign bit, we can convert this to an AND of the
11046 if (const_op == 0 && equality_comparison_p
11047 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11048 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11051 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11052 (HOST_WIDE_INT) 1);
11058 /* If this is an equality comparison with zero, we can do this
11059 as a logical shift, which might be much simpler. */
11060 if (equality_comparison_p && const_op == 0
11061 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11063 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11065 INTVAL (XEXP (op0, 1)));
11069 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11070 do the comparison in a narrower mode. */
11071 if (! unsigned_comparison_p
11072 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11073 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11074 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11075 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11076 MODE_INT, 1)) != BLKmode
11077 && (((unsigned HOST_WIDE_INT) const_op
11078 + (GET_MODE_MASK (tmode) >> 1) + 1)
11079 <= GET_MODE_MASK (tmode)))
11081 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11085 /* Likewise if OP0 is a PLUS of a sign extension with a
11086 constant, which is usually represented with the PLUS
11087 between the shifts. */
11088 if (! unsigned_comparison_p
11089 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11090 && GET_CODE (XEXP (op0, 0)) == PLUS
11091 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11092 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11093 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11094 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11095 MODE_INT, 1)) != BLKmode
11096 && (((unsigned HOST_WIDE_INT) const_op
11097 + (GET_MODE_MASK (tmode) >> 1) + 1)
11098 <= GET_MODE_MASK (tmode)))
11100 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11101 rtx add_const = XEXP (XEXP (op0, 0), 1);
11102 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11105 op0 = gen_binary (PLUS, tmode,
11106 gen_lowpart_for_combine (tmode, inner),
11111 /* ... fall through ... */
11113 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11114 the low order N bits of FOO are known to be zero, we can do this
11115 by comparing FOO with C shifted left N bits so long as no
11116 overflow occurs. */
11117 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11118 && INTVAL (XEXP (op0, 1)) >= 0
11119 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11120 && mode_width <= HOST_BITS_PER_WIDE_INT
11121 && (nonzero_bits (XEXP (op0, 0), mode)
11122 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11123 && (((unsigned HOST_WIDE_INT) const_op
11124 + (GET_CODE (op0) != LSHIFTRT
11125 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11128 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11130 /* If the shift was logical, then we must make the condition
11132 if (GET_CODE (op0) == LSHIFTRT)
11133 code = unsigned_condition (code);
11135 const_op <<= INTVAL (XEXP (op0, 1));
11136 op1 = GEN_INT (const_op);
11137 op0 = XEXP (op0, 0);
11141 /* If we are using this shift to extract just the sign bit, we
11142 can replace this with an LT or GE comparison. */
11144 && (equality_comparison_p || sign_bit_comparison_p)
11145 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11146 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11149 op0 = XEXP (op0, 0);
11150 code = (code == NE || code == GT ? LT : GE);
11162 /* Now make any compound operations involved in this comparison. Then,
11163 check for an outmost SUBREG on OP0 that is not doing anything or is
11164 paradoxical. The latter transformation must only be performed when
11165 it is known that the "extra" bits will be the same in op0 and op1 or
11166 that they don't matter. There are three cases to consider:
11168 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11169 care bits and we can assume they have any convenient value. So
11170 making the transformation is safe.
11172 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11173 In this case the upper bits of op0 are undefined. We should not make
11174 the simplification in that case as we do not know the contents of
11177 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11178 NIL. In that case we know those bits are zeros or ones. We must
11179 also be sure that they are the same as the upper bits of op1.
11181 We can never remove a SUBREG for a non-equality comparison because
11182 the sign bit is in a different place in the underlying object. */
11184 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11185 op1 = make_compound_operation (op1, SET);
11187 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11188 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11190 && GET_CODE (SUBREG_REG (op0)) == REG
11191 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11192 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11193 && (code == NE || code == EQ))
11195 if (GET_MODE_SIZE (GET_MODE (op0))
11196 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11198 op0 = SUBREG_REG (op0);
11199 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11201 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11202 <= HOST_BITS_PER_WIDE_INT)
11203 && (nonzero_bits (SUBREG_REG (op0),
11204 GET_MODE (SUBREG_REG (op0)))
11205 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11207 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11209 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11210 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11211 op0 = SUBREG_REG (op0), op1 = tem;
11215 /* We now do the opposite procedure: Some machines don't have compare
11216 insns in all modes. If OP0's mode is an integer mode smaller than a
11217 word and we can't do a compare in that mode, see if there is a larger
11218 mode for which we can do the compare. There are a number of cases in
11219 which we can use the wider mode. */
11221 mode = GET_MODE (op0);
11222 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11223 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11224 && ! have_insn_for (COMPARE, mode))
11225 for (tmode = GET_MODE_WIDER_MODE (mode);
11227 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11228 tmode = GET_MODE_WIDER_MODE (tmode))
11229 if (have_insn_for (COMPARE, tmode))
11233 /* If the only nonzero bits in OP0 and OP1 are those in the
11234 narrower mode and this is an equality or unsigned comparison,
11235 we can use the wider mode. Similarly for sign-extended
11236 values, in which case it is true for all comparisons. */
11237 zero_extended = ((code == EQ || code == NE
11238 || code == GEU || code == GTU
11239 || code == LEU || code == LTU)
11240 && (nonzero_bits (op0, tmode)
11241 & ~GET_MODE_MASK (mode)) == 0
11242 && ((GET_CODE (op1) == CONST_INT
11243 || (nonzero_bits (op1, tmode)
11244 & ~GET_MODE_MASK (mode)) == 0)));
11247 || ((num_sign_bit_copies (op0, tmode)
11248 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11249 - GET_MODE_BITSIZE (mode)))
11250 && (num_sign_bit_copies (op1, tmode)
11251 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11252 - GET_MODE_BITSIZE (mode)))))
11254 /* If OP0 is an AND and we don't have an AND in MODE either,
11255 make a new AND in the proper mode. */
11256 if (GET_CODE (op0) == AND
11257 && !have_insn_for (AND, mode))
11258 op0 = gen_binary (AND, tmode,
11259 gen_lowpart_for_combine (tmode,
11261 gen_lowpart_for_combine (tmode,
11264 op0 = gen_lowpart_for_combine (tmode, op0);
11265 if (zero_extended && GET_CODE (op1) == CONST_INT)
11266 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11267 op1 = gen_lowpart_for_combine (tmode, op1);
11271 /* If this is a test for negative, we can make an explicit
11272 test of the sign bit. */
11274 if (op1 == const0_rtx && (code == LT || code == GE)
11275 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11277 op0 = gen_binary (AND, tmode,
11278 gen_lowpart_for_combine (tmode, op0),
11279 GEN_INT ((HOST_WIDE_INT) 1
11280 << (GET_MODE_BITSIZE (mode) - 1)));
11281 code = (code == LT) ? NE : EQ;
11286 #ifdef CANONICALIZE_COMPARISON
11287 /* If this machine only supports a subset of valid comparisons, see if we
11288 can convert an unsupported one into a supported one. */
11289 CANONICALIZE_COMPARISON (code, op0, op1);
11298 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11299 searching backward. */
11300 static enum rtx_code
11301 combine_reversed_comparison_code (exp)
11304 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11307 if (code1 != UNKNOWN
11308 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11310 /* Otherwise try and find where the condition codes were last set and
11312 x = get_last_value (XEXP (exp, 0));
11313 if (!x || GET_CODE (x) != COMPARE)
11315 return reversed_comparison_code_parts (GET_CODE (exp),
11316 XEXP (x, 0), XEXP (x, 1), NULL);
11319 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11320 Return NULL_RTX in case we fail to do the reversal. */
11322 reversed_comparison (exp, mode, op0, op1)
11324 enum machine_mode mode;
11326 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11327 if (reversed_code == UNKNOWN)
11330 return gen_binary (reversed_code, mode, op0, op1);
11333 /* Utility function for following routine. Called when X is part of a value
11334 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11335 for each register mentioned. Similar to mention_regs in cse.c */
11338 update_table_tick (x)
11341 enum rtx_code code = GET_CODE (x);
11342 const char *fmt = GET_RTX_FORMAT (code);
11347 unsigned int regno = REGNO (x);
11348 unsigned int endregno
11349 = regno + (regno < FIRST_PSEUDO_REGISTER
11350 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11353 for (r = regno; r < endregno; r++)
11354 reg_last_set_table_tick[r] = label_tick;
11359 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11360 /* Note that we can't have an "E" in values stored; see
11361 get_last_value_validate. */
11363 update_table_tick (XEXP (x, i));
11366 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11367 are saying that the register is clobbered and we no longer know its
11368 value. If INSN is zero, don't update reg_last_set; this is only permitted
11369 with VALUE also zero and is used to invalidate the register. */
11372 record_value_for_reg (reg, insn, value)
11377 unsigned int regno = REGNO (reg);
11378 unsigned int endregno
11379 = regno + (regno < FIRST_PSEUDO_REGISTER
11380 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11383 /* If VALUE contains REG and we have a previous value for REG, substitute
11384 the previous value. */
11385 if (value && insn && reg_overlap_mentioned_p (reg, value))
11389 /* Set things up so get_last_value is allowed to see anything set up to
11391 subst_low_cuid = INSN_CUID (insn);
11392 tem = get_last_value (reg);
11394 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11395 it isn't going to be useful and will take a lot of time to process,
11396 so just use the CLOBBER. */
11400 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11401 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11402 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11403 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11404 tem = XEXP (tem, 0);
11406 value = replace_rtx (copy_rtx (value), reg, tem);
11410 /* For each register modified, show we don't know its value, that
11411 we don't know about its bitwise content, that its value has been
11412 updated, and that we don't know the location of the death of the
11414 for (i = regno; i < endregno; i++)
11417 reg_last_set[i] = insn;
11419 reg_last_set_value[i] = 0;
11420 reg_last_set_mode[i] = 0;
11421 reg_last_set_nonzero_bits[i] = 0;
11422 reg_last_set_sign_bit_copies[i] = 0;
11423 reg_last_death[i] = 0;
11426 /* Mark registers that are being referenced in this value. */
11428 update_table_tick (value);
11430 /* Now update the status of each register being set.
11431 If someone is using this register in this block, set this register
11432 to invalid since we will get confused between the two lives in this
11433 basic block. This makes using this register always invalid. In cse, we
11434 scan the table to invalidate all entries using this register, but this
11435 is too much work for us. */
11437 for (i = regno; i < endregno; i++)
11439 reg_last_set_label[i] = label_tick;
11440 if (value && reg_last_set_table_tick[i] == label_tick)
11441 reg_last_set_invalid[i] = 1;
11443 reg_last_set_invalid[i] = 0;
11446 /* The value being assigned might refer to X (like in "x++;"). In that
11447 case, we must replace it with (clobber (const_int 0)) to prevent
11449 if (value && ! get_last_value_validate (&value, insn,
11450 reg_last_set_label[regno], 0))
11452 value = copy_rtx (value);
11453 if (! get_last_value_validate (&value, insn,
11454 reg_last_set_label[regno], 1))
11458 /* For the main register being modified, update the value, the mode, the
11459 nonzero bits, and the number of sign bit copies. */
11461 reg_last_set_value[regno] = value;
11465 enum machine_mode mode = GET_MODE (reg);
11466 subst_low_cuid = INSN_CUID (insn);
11467 reg_last_set_mode[regno] = mode;
11468 if (GET_MODE_CLASS (mode) == MODE_INT
11469 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11470 mode = nonzero_bits_mode;
11471 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11472 reg_last_set_sign_bit_copies[regno]
11473 = num_sign_bit_copies (value, GET_MODE (reg));
11477 /* Called via note_stores from record_dead_and_set_regs to handle one
11478 SET or CLOBBER in an insn. DATA is the instruction in which the
11479 set is occurring. */
11482 record_dead_and_set_regs_1 (dest, setter, data)
11486 rtx record_dead_insn = (rtx) data;
11488 if (GET_CODE (dest) == SUBREG)
11489 dest = SUBREG_REG (dest);
11491 if (GET_CODE (dest) == REG)
11493 /* If we are setting the whole register, we know its value. Otherwise
11494 show that we don't know the value. We can handle SUBREG in
11496 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11497 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11498 else if (GET_CODE (setter) == SET
11499 && GET_CODE (SET_DEST (setter)) == SUBREG
11500 && SUBREG_REG (SET_DEST (setter)) == dest
11501 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11502 && subreg_lowpart_p (SET_DEST (setter)))
11503 record_value_for_reg (dest, record_dead_insn,
11504 gen_lowpart_for_combine (GET_MODE (dest),
11505 SET_SRC (setter)));
11507 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11509 else if (GET_CODE (dest) == MEM
11510 /* Ignore pushes, they clobber nothing. */
11511 && ! push_operand (dest, GET_MODE (dest)))
11512 mem_last_set = INSN_CUID (record_dead_insn);
11515 /* Update the records of when each REG was most recently set or killed
11516 for the things done by INSN. This is the last thing done in processing
11517 INSN in the combiner loop.
11519 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11520 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11521 and also the similar information mem_last_set (which insn most recently
11522 modified memory) and last_call_cuid (which insn was the most recent
11523 subroutine call). */
11526 record_dead_and_set_regs (insn)
11532 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11534 if (REG_NOTE_KIND (link) == REG_DEAD
11535 && GET_CODE (XEXP (link, 0)) == REG)
11537 unsigned int regno = REGNO (XEXP (link, 0));
11538 unsigned int endregno
11539 = regno + (regno < FIRST_PSEUDO_REGISTER
11540 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11543 for (i = regno; i < endregno; i++)
11544 reg_last_death[i] = insn;
11546 else if (REG_NOTE_KIND (link) == REG_INC)
11547 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11550 if (GET_CODE (insn) == CALL_INSN)
11552 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11553 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11555 reg_last_set_value[i] = 0;
11556 reg_last_set_mode[i] = 0;
11557 reg_last_set_nonzero_bits[i] = 0;
11558 reg_last_set_sign_bit_copies[i] = 0;
11559 reg_last_death[i] = 0;
11562 last_call_cuid = mem_last_set = INSN_CUID (insn);
11564 /* Don't bother recording what this insn does. It might set the
11565 return value register, but we can't combine into a call
11566 pattern anyway, so there's no point trying (and it may cause
11567 a crash, if e.g. we wind up asking for last_set_value of a
11568 SUBREG of the return value register). */
11572 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11575 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11576 register present in the SUBREG, so for each such SUBREG go back and
11577 adjust nonzero and sign bit information of the registers that are
11578 known to have some zero/sign bits set.
11580 This is needed because when combine blows the SUBREGs away, the
11581 information on zero/sign bits is lost and further combines can be
11582 missed because of that. */
11585 record_promoted_value (insn, subreg)
11590 unsigned int regno = REGNO (SUBREG_REG (subreg));
11591 enum machine_mode mode = GET_MODE (subreg);
11593 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11596 for (links = LOG_LINKS (insn); links;)
11598 insn = XEXP (links, 0);
11599 set = single_set (insn);
11601 if (! set || GET_CODE (SET_DEST (set)) != REG
11602 || REGNO (SET_DEST (set)) != regno
11603 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11605 links = XEXP (links, 1);
11609 if (reg_last_set[regno] == insn)
11611 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11612 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11615 if (GET_CODE (SET_SRC (set)) == REG)
11617 regno = REGNO (SET_SRC (set));
11618 links = LOG_LINKS (insn);
11625 /* Scan X for promoted SUBREGs. For each one found,
11626 note what it implies to the registers used in it. */
11629 check_promoted_subreg (insn, x)
11633 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11634 && GET_CODE (SUBREG_REG (x)) == REG)
11635 record_promoted_value (insn, x);
11638 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11641 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11645 check_promoted_subreg (insn, XEXP (x, i));
11649 if (XVEC (x, i) != 0)
11650 for (j = 0; j < XVECLEN (x, i); j++)
11651 check_promoted_subreg (insn, XVECEXP (x, i, j));
11657 /* Utility routine for the following function. Verify that all the registers
11658 mentioned in *LOC are valid when *LOC was part of a value set when
11659 label_tick == TICK. Return 0 if some are not.
11661 If REPLACE is nonzero, replace the invalid reference with
11662 (clobber (const_int 0)) and return 1. This replacement is useful because
11663 we often can get useful information about the form of a value (e.g., if
11664 it was produced by a shift that always produces -1 or 0) even though
11665 we don't know exactly what registers it was produced from. */
11668 get_last_value_validate (loc, insn, tick, replace)
11675 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11676 int len = GET_RTX_LENGTH (GET_CODE (x));
11679 if (GET_CODE (x) == REG)
11681 unsigned int regno = REGNO (x);
11682 unsigned int endregno
11683 = regno + (regno < FIRST_PSEUDO_REGISTER
11684 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11687 for (j = regno; j < endregno; j++)
11688 if (reg_last_set_invalid[j]
11689 /* If this is a pseudo-register that was only set once and not
11690 live at the beginning of the function, it is always valid. */
11691 || (! (regno >= FIRST_PSEUDO_REGISTER
11692 && REG_N_SETS (regno) == 1
11693 && (! REGNO_REG_SET_P
11694 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11695 && reg_last_set_label[j] > tick))
11698 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11704 /* If this is a memory reference, make sure that there were
11705 no stores after it that might have clobbered the value. We don't
11706 have alias info, so we assume any store invalidates it. */
11707 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11708 && INSN_CUID (insn) <= mem_last_set)
11711 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11715 for (i = 0; i < len; i++)
11717 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11718 /* Don't bother with these. They shouldn't occur anyway. */
11722 /* If we haven't found a reason for it to be invalid, it is valid. */
11726 /* Get the last value assigned to X, if known. Some registers
11727 in the value may be replaced with (clobber (const_int 0)) if their value
11728 is known longer known reliably. */
11734 unsigned int regno;
11737 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11738 then convert it to the desired mode. If this is a paradoxical SUBREG,
11739 we cannot predict what values the "extra" bits might have. */
11740 if (GET_CODE (x) == SUBREG
11741 && subreg_lowpart_p (x)
11742 && (GET_MODE_SIZE (GET_MODE (x))
11743 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11744 && (value = get_last_value (SUBREG_REG (x))) != 0)
11745 return gen_lowpart_for_combine (GET_MODE (x), value);
11747 if (GET_CODE (x) != REG)
11751 value = reg_last_set_value[regno];
11753 /* If we don't have a value, or if it isn't for this basic block and
11754 it's either a hard register, set more than once, or it's a live
11755 at the beginning of the function, return 0.
11757 Because if it's not live at the beginning of the function then the reg
11758 is always set before being used (is never used without being set).
11759 And, if it's set only once, and it's always set before use, then all
11760 uses must have the same last value, even if it's not from this basic
11764 || (reg_last_set_label[regno] != label_tick
11765 && (regno < FIRST_PSEUDO_REGISTER
11766 || REG_N_SETS (regno) != 1
11767 || (REGNO_REG_SET_P
11768 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11771 /* If the value was set in a later insn than the ones we are processing,
11772 we can't use it even if the register was only set once. */
11773 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11776 /* If the value has all its registers valid, return it. */
11777 if (get_last_value_validate (&value, reg_last_set[regno],
11778 reg_last_set_label[regno], 0))
11781 /* Otherwise, make a copy and replace any invalid register with
11782 (clobber (const_int 0)). If that fails for some reason, return 0. */
11784 value = copy_rtx (value);
11785 if (get_last_value_validate (&value, reg_last_set[regno],
11786 reg_last_set_label[regno], 1))
11792 /* Return nonzero if expression X refers to a REG or to memory
11793 that is set in an instruction more recent than FROM_CUID. */
11796 use_crosses_set_p (x, from_cuid)
11802 enum rtx_code code = GET_CODE (x);
11806 unsigned int regno = REGNO (x);
11807 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11808 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11810 #ifdef PUSH_ROUNDING
11811 /* Don't allow uses of the stack pointer to be moved,
11812 because we don't know whether the move crosses a push insn. */
11813 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11816 for (; regno < endreg; regno++)
11817 if (reg_last_set[regno]
11818 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11823 if (code == MEM && mem_last_set > from_cuid)
11826 fmt = GET_RTX_FORMAT (code);
11828 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11833 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11834 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11837 else if (fmt[i] == 'e'
11838 && use_crosses_set_p (XEXP (x, i), from_cuid))
11844 /* Define three variables used for communication between the following
11847 static unsigned int reg_dead_regno, reg_dead_endregno;
11848 static int reg_dead_flag;
11850 /* Function called via note_stores from reg_dead_at_p.
11852 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11853 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11856 reg_dead_at_p_1 (dest, x, data)
11859 void *data ATTRIBUTE_UNUSED;
11861 unsigned int regno, endregno;
11863 if (GET_CODE (dest) != REG)
11866 regno = REGNO (dest);
11867 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11868 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11870 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11871 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11874 /* Return nonzero if REG is known to be dead at INSN.
11876 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11877 referencing REG, it is dead. If we hit a SET referencing REG, it is
11878 live. Otherwise, see if it is live or dead at the start of the basic
11879 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11880 must be assumed to be always live. */
11883 reg_dead_at_p (reg, insn)
11890 /* Set variables for reg_dead_at_p_1. */
11891 reg_dead_regno = REGNO (reg);
11892 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11893 ? HARD_REGNO_NREGS (reg_dead_regno,
11899 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11900 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11902 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11903 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11907 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11908 beginning of function. */
11909 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11910 insn = prev_nonnote_insn (insn))
11912 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11914 return reg_dead_flag == 1 ? 1 : 0;
11916 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11920 /* Get the basic block that we were in. */
11922 block = ENTRY_BLOCK_PTR->next_bb;
11925 FOR_EACH_BB (block)
11926 if (insn == block->head)
11929 if (block == EXIT_BLOCK_PTR)
11933 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11934 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11940 /* Note hard registers in X that are used. This code is similar to
11941 that in flow.c, but much simpler since we don't care about pseudos. */
11944 mark_used_regs_combine (x)
11947 RTX_CODE code = GET_CODE (x);
11948 unsigned int regno;
11961 case ADDR_DIFF_VEC:
11964 /* CC0 must die in the insn after it is set, so we don't need to take
11965 special note of it here. */
11971 /* If we are clobbering a MEM, mark any hard registers inside the
11972 address as used. */
11973 if (GET_CODE (XEXP (x, 0)) == MEM)
11974 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11979 /* A hard reg in a wide mode may really be multiple registers.
11980 If so, mark all of them just like the first. */
11981 if (regno < FIRST_PSEUDO_REGISTER)
11983 unsigned int endregno, r;
11985 /* None of this applies to the stack, frame or arg pointers. */
11986 if (regno == STACK_POINTER_REGNUM
11987 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11988 || regno == HARD_FRAME_POINTER_REGNUM
11990 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11991 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11993 || regno == FRAME_POINTER_REGNUM)
11996 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11997 for (r = regno; r < endregno; r++)
11998 SET_HARD_REG_BIT (newpat_used_regs, r);
12004 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12006 rtx testreg = SET_DEST (x);
12008 while (GET_CODE (testreg) == SUBREG
12009 || GET_CODE (testreg) == ZERO_EXTRACT
12010 || GET_CODE (testreg) == SIGN_EXTRACT
12011 || GET_CODE (testreg) == STRICT_LOW_PART)
12012 testreg = XEXP (testreg, 0);
12014 if (GET_CODE (testreg) == MEM)
12015 mark_used_regs_combine (XEXP (testreg, 0));
12017 mark_used_regs_combine (SET_SRC (x));
12025 /* Recursively scan the operands of this expression. */
12028 const char *fmt = GET_RTX_FORMAT (code);
12030 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12033 mark_used_regs_combine (XEXP (x, i));
12034 else if (fmt[i] == 'E')
12038 for (j = 0; j < XVECLEN (x, i); j++)
12039 mark_used_regs_combine (XVECEXP (x, i, j));
12045 /* Remove register number REGNO from the dead registers list of INSN.
12047 Return the note used to record the death, if there was one. */
12050 remove_death (regno, insn)
12051 unsigned int regno;
12054 rtx note = find_regno_note (insn, REG_DEAD, regno);
12058 REG_N_DEATHS (regno)--;
12059 remove_note (insn, note);
12065 /* For each register (hardware or pseudo) used within expression X, if its
12066 death is in an instruction with cuid between FROM_CUID (inclusive) and
12067 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12068 list headed by PNOTES.
12070 That said, don't move registers killed by maybe_kill_insn.
12072 This is done when X is being merged by combination into TO_INSN. These
12073 notes will then be distributed as needed. */
12076 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
12078 rtx maybe_kill_insn;
12085 enum rtx_code code = GET_CODE (x);
12089 unsigned int regno = REGNO (x);
12090 rtx where_dead = reg_last_death[regno];
12091 rtx before_dead, after_dead;
12093 /* Don't move the register if it gets killed in between from and to. */
12094 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12095 && ! reg_referenced_p (x, maybe_kill_insn))
12098 /* WHERE_DEAD could be a USE insn made by combine, so first we
12099 make sure that we have insns with valid INSN_CUID values. */
12100 before_dead = where_dead;
12101 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12102 before_dead = PREV_INSN (before_dead);
12104 after_dead = where_dead;
12105 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12106 after_dead = NEXT_INSN (after_dead);
12108 if (before_dead && after_dead
12109 && INSN_CUID (before_dead) >= from_cuid
12110 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12111 || (where_dead != after_dead
12112 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12114 rtx note = remove_death (regno, where_dead);
12116 /* It is possible for the call above to return 0. This can occur
12117 when reg_last_death points to I2 or I1 that we combined with.
12118 In that case make a new note.
12120 We must also check for the case where X is a hard register
12121 and NOTE is a death note for a range of hard registers
12122 including X. In that case, we must put REG_DEAD notes for
12123 the remaining registers in place of NOTE. */
12125 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12126 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12127 > GET_MODE_SIZE (GET_MODE (x))))
12129 unsigned int deadregno = REGNO (XEXP (note, 0));
12130 unsigned int deadend
12131 = (deadregno + HARD_REGNO_NREGS (deadregno,
12132 GET_MODE (XEXP (note, 0))));
12133 unsigned int ourend
12134 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12137 for (i = deadregno; i < deadend; i++)
12138 if (i < regno || i >= ourend)
12139 REG_NOTES (where_dead)
12140 = gen_rtx_EXPR_LIST (REG_DEAD,
12142 REG_NOTES (where_dead));
12145 /* If we didn't find any note, or if we found a REG_DEAD note that
12146 covers only part of the given reg, and we have a multi-reg hard
12147 register, then to be safe we must check for REG_DEAD notes
12148 for each register other than the first. They could have
12149 their own REG_DEAD notes lying around. */
12150 else if ((note == 0
12152 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12153 < GET_MODE_SIZE (GET_MODE (x)))))
12154 && regno < FIRST_PSEUDO_REGISTER
12155 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12157 unsigned int ourend
12158 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12159 unsigned int i, offset;
12163 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12167 for (i = regno + offset; i < ourend; i++)
12168 move_deaths (regno_reg_rtx[i],
12169 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12172 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12174 XEXP (note, 1) = *pnotes;
12178 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12180 REG_N_DEATHS (regno)++;
12186 else if (GET_CODE (x) == SET)
12188 rtx dest = SET_DEST (x);
12190 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12192 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12193 that accesses one word of a multi-word item, some
12194 piece of everything register in the expression is used by
12195 this insn, so remove any old death. */
12196 /* ??? So why do we test for equality of the sizes? */
12198 if (GET_CODE (dest) == ZERO_EXTRACT
12199 || GET_CODE (dest) == STRICT_LOW_PART
12200 || (GET_CODE (dest) == SUBREG
12201 && (((GET_MODE_SIZE (GET_MODE (dest))
12202 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12203 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12204 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12206 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12210 /* If this is some other SUBREG, we know it replaces the entire
12211 value, so use that as the destination. */
12212 if (GET_CODE (dest) == SUBREG)
12213 dest = SUBREG_REG (dest);
12215 /* If this is a MEM, adjust deaths of anything used in the address.
12216 For a REG (the only other possibility), the entire value is
12217 being replaced so the old value is not used in this insn. */
12219 if (GET_CODE (dest) == MEM)
12220 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12225 else if (GET_CODE (x) == CLOBBER)
12228 len = GET_RTX_LENGTH (code);
12229 fmt = GET_RTX_FORMAT (code);
12231 for (i = 0; i < len; i++)
12236 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12237 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12240 else if (fmt[i] == 'e')
12241 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12245 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12246 pattern of an insn. X must be a REG. */
12249 reg_bitfield_target_p (x, body)
12255 if (GET_CODE (body) == SET)
12257 rtx dest = SET_DEST (body);
12259 unsigned int regno, tregno, endregno, endtregno;
12261 if (GET_CODE (dest) == ZERO_EXTRACT)
12262 target = XEXP (dest, 0);
12263 else if (GET_CODE (dest) == STRICT_LOW_PART)
12264 target = SUBREG_REG (XEXP (dest, 0));
12268 if (GET_CODE (target) == SUBREG)
12269 target = SUBREG_REG (target);
12271 if (GET_CODE (target) != REG)
12274 tregno = REGNO (target), regno = REGNO (x);
12275 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12276 return target == x;
12278 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12279 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12281 return endregno > tregno && regno < endtregno;
12284 else if (GET_CODE (body) == PARALLEL)
12285 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12286 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12292 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12293 as appropriate. I3 and I2 are the insns resulting from the combination
12294 insns including FROM (I2 may be zero).
12296 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12297 not need REG_DEAD notes because they are being substituted for. This
12298 saves searching in the most common cases.
12300 Each note in the list is either ignored or placed on some insns, depending
12301 on the type of note. */
12304 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12308 rtx elim_i2, elim_i1;
12310 rtx note, next_note;
12313 for (note = notes; note; note = next_note)
12315 rtx place = 0, place2 = 0;
12317 /* If this NOTE references a pseudo register, ensure it references
12318 the latest copy of that register. */
12319 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12320 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12321 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12323 next_note = XEXP (note, 1);
12324 switch (REG_NOTE_KIND (note))
12328 case REG_EXEC_COUNT:
12329 /* Doesn't matter much where we put this, as long as it's somewhere.
12330 It is preferable to keep these notes on branches, which is most
12331 likely to be i3. */
12335 case REG_VTABLE_REF:
12336 /* ??? Should remain with *a particular* memory load. Given the
12337 nature of vtable data, the last insn seems relatively safe. */
12341 case REG_NON_LOCAL_GOTO:
12342 if (GET_CODE (i3) == JUMP_INSN)
12344 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12350 case REG_EH_REGION:
12351 /* These notes must remain with the call or trapping instruction. */
12352 if (GET_CODE (i3) == CALL_INSN)
12354 else if (i2 && GET_CODE (i2) == CALL_INSN)
12356 else if (flag_non_call_exceptions)
12358 if (may_trap_p (i3))
12360 else if (i2 && may_trap_p (i2))
12362 /* ??? Otherwise assume we've combined things such that we
12363 can now prove that the instructions can't trap. Drop the
12364 note in this case. */
12372 /* These notes must remain with the call. It should not be
12373 possible for both I2 and I3 to be a call. */
12374 if (GET_CODE (i3) == CALL_INSN)
12376 else if (i2 && GET_CODE (i2) == CALL_INSN)
12383 /* Any clobbers for i3 may still exist, and so we must process
12384 REG_UNUSED notes from that insn.
12386 Any clobbers from i2 or i1 can only exist if they were added by
12387 recog_for_combine. In that case, recog_for_combine created the
12388 necessary REG_UNUSED notes. Trying to keep any original
12389 REG_UNUSED notes from these insns can cause incorrect output
12390 if it is for the same register as the original i3 dest.
12391 In that case, we will notice that the register is set in i3,
12392 and then add a REG_UNUSED note for the destination of i3, which
12393 is wrong. However, it is possible to have REG_UNUSED notes from
12394 i2 or i1 for register which were both used and clobbered, so
12395 we keep notes from i2 or i1 if they will turn into REG_DEAD
12398 /* If this register is set or clobbered in I3, put the note there
12399 unless there is one already. */
12400 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12402 if (from_insn != i3)
12405 if (! (GET_CODE (XEXP (note, 0)) == REG
12406 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12407 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12410 /* Otherwise, if this register is used by I3, then this register
12411 now dies here, so we must put a REG_DEAD note here unless there
12413 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12414 && ! (GET_CODE (XEXP (note, 0)) == REG
12415 ? find_regno_note (i3, REG_DEAD,
12416 REGNO (XEXP (note, 0)))
12417 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12419 PUT_REG_NOTE_KIND (note, REG_DEAD);
12427 /* These notes say something about results of an insn. We can
12428 only support them if they used to be on I3 in which case they
12429 remain on I3. Otherwise they are ignored.
12431 If the note refers to an expression that is not a constant, we
12432 must also ignore the note since we cannot tell whether the
12433 equivalence is still true. It might be possible to do
12434 slightly better than this (we only have a problem if I2DEST
12435 or I1DEST is present in the expression), but it doesn't
12436 seem worth the trouble. */
12438 if (from_insn == i3
12439 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12444 case REG_NO_CONFLICT:
12445 /* These notes say something about how a register is used. They must
12446 be present on any use of the register in I2 or I3. */
12447 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12450 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12460 /* This can show up in several ways -- either directly in the
12461 pattern, or hidden off in the constant pool with (or without?)
12462 a REG_EQUAL note. */
12463 /* ??? Ignore the without-reg_equal-note problem for now. */
12464 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12465 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12466 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12467 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12471 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12472 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12473 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12474 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12482 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12483 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12484 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12486 if (JUMP_LABEL (place) != XEXP (note, 0))
12488 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12489 LABEL_NUSES (JUMP_LABEL (place))--;
12492 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12494 if (JUMP_LABEL (place2) != XEXP (note, 0))
12496 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12497 LABEL_NUSES (JUMP_LABEL (place2))--;
12504 /* These notes say something about the value of a register prior
12505 to the execution of an insn. It is too much trouble to see
12506 if the note is still correct in all situations. It is better
12507 to simply delete it. */
12511 /* If the insn previously containing this note still exists,
12512 put it back where it was. Otherwise move it to the previous
12513 insn. Adjust the corresponding REG_LIBCALL note. */
12514 if (GET_CODE (from_insn) != NOTE)
12518 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12519 place = prev_real_insn (from_insn);
12521 XEXP (tem, 0) = place;
12522 /* If we're deleting the last remaining instruction of a
12523 libcall sequence, don't add the notes. */
12524 else if (XEXP (note, 0) == from_insn)
12530 /* This is handled similarly to REG_RETVAL. */
12531 if (GET_CODE (from_insn) != NOTE)
12535 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12536 place = next_real_insn (from_insn);
12538 XEXP (tem, 0) = place;
12539 /* If we're deleting the last remaining instruction of a
12540 libcall sequence, don't add the notes. */
12541 else if (XEXP (note, 0) == from_insn)
12547 /* If the register is used as an input in I3, it dies there.
12548 Similarly for I2, if it is nonzero and adjacent to I3.
12550 If the register is not used as an input in either I3 or I2
12551 and it is not one of the registers we were supposed to eliminate,
12552 there are two possibilities. We might have a non-adjacent I2
12553 or we might have somehow eliminated an additional register
12554 from a computation. For example, we might have had A & B where
12555 we discover that B will always be zero. In this case we will
12556 eliminate the reference to A.
12558 In both cases, we must search to see if we can find a previous
12559 use of A and put the death note there. */
12562 && GET_CODE (from_insn) == CALL_INSN
12563 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12565 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12567 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12568 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12571 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12572 || rtx_equal_p (XEXP (note, 0), elim_i1))
12577 basic_block bb = this_basic_block;
12579 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12581 if (! INSN_P (tem))
12583 if (tem == bb->head)
12588 /* If the register is being set at TEM, see if that is all
12589 TEM is doing. If so, delete TEM. Otherwise, make this
12590 into a REG_UNUSED note instead. */
12591 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12593 rtx set = single_set (tem);
12594 rtx inner_dest = 0;
12596 rtx cc0_setter = NULL_RTX;
12600 for (inner_dest = SET_DEST (set);
12601 (GET_CODE (inner_dest) == STRICT_LOW_PART
12602 || GET_CODE (inner_dest) == SUBREG
12603 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12604 inner_dest = XEXP (inner_dest, 0))
12607 /* Verify that it was the set, and not a clobber that
12608 modified the register.
12610 CC0 targets must be careful to maintain setter/user
12611 pairs. If we cannot delete the setter due to side
12612 effects, mark the user with an UNUSED note instead
12615 if (set != 0 && ! side_effects_p (SET_SRC (set))
12616 && rtx_equal_p (XEXP (note, 0), inner_dest)
12618 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12619 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12620 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12624 /* Move the notes and links of TEM elsewhere.
12625 This might delete other dead insns recursively.
12626 First set the pattern to something that won't use
12629 PATTERN (tem) = pc_rtx;
12631 distribute_notes (REG_NOTES (tem), tem, tem,
12632 NULL_RTX, NULL_RTX, NULL_RTX);
12633 distribute_links (LOG_LINKS (tem));
12635 PUT_CODE (tem, NOTE);
12636 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12637 NOTE_SOURCE_FILE (tem) = 0;
12640 /* Delete the setter too. */
12643 PATTERN (cc0_setter) = pc_rtx;
12645 distribute_notes (REG_NOTES (cc0_setter),
12646 cc0_setter, cc0_setter,
12647 NULL_RTX, NULL_RTX, NULL_RTX);
12648 distribute_links (LOG_LINKS (cc0_setter));
12650 PUT_CODE (cc0_setter, NOTE);
12651 NOTE_LINE_NUMBER (cc0_setter)
12652 = NOTE_INSN_DELETED;
12653 NOTE_SOURCE_FILE (cc0_setter) = 0;
12657 /* If the register is both set and used here, put the
12658 REG_DEAD note here, but place a REG_UNUSED note
12659 here too unless there already is one. */
12660 else if (reg_referenced_p (XEXP (note, 0),
12665 if (! find_regno_note (tem, REG_UNUSED,
12666 REGNO (XEXP (note, 0))))
12668 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12673 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12675 /* If there isn't already a REG_UNUSED note, put one
12677 if (! find_regno_note (tem, REG_UNUSED,
12678 REGNO (XEXP (note, 0))))
12683 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12684 || (GET_CODE (tem) == CALL_INSN
12685 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12689 /* If we are doing a 3->2 combination, and we have a
12690 register which formerly died in i3 and was not used
12691 by i2, which now no longer dies in i3 and is used in
12692 i2 but does not die in i2, and place is between i2
12693 and i3, then we may need to move a link from place to
12695 if (i2 && INSN_UID (place) <= max_uid_cuid
12696 && INSN_CUID (place) > INSN_CUID (i2)
12698 && INSN_CUID (from_insn) > INSN_CUID (i2)
12699 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12701 rtx links = LOG_LINKS (place);
12702 LOG_LINKS (place) = 0;
12703 distribute_links (links);
12708 if (tem == bb->head)
12712 /* We haven't found an insn for the death note and it
12713 is still a REG_DEAD note, but we have hit the beginning
12714 of the block. If the existing life info says the reg
12715 was dead, there's nothing left to do. Otherwise, we'll
12716 need to do a global life update after combine. */
12717 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12718 && REGNO_REG_SET_P (bb->global_live_at_start,
12719 REGNO (XEXP (note, 0))))
12720 SET_BIT (refresh_blocks, this_basic_block->index);
12723 /* If the register is set or already dead at PLACE, we needn't do
12724 anything with this note if it is still a REG_DEAD note.
12725 We can here if it is set at all, not if is it totally replace,
12726 which is what `dead_or_set_p' checks, so also check for it being
12729 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12731 unsigned int regno = REGNO (XEXP (note, 0));
12733 /* Similarly, if the instruction on which we want to place
12734 the note is a noop, we'll need do a global live update
12735 after we remove them in delete_noop_moves. */
12736 if (noop_move_p (place))
12737 SET_BIT (refresh_blocks, this_basic_block->index);
12739 if (dead_or_set_p (place, XEXP (note, 0))
12740 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12742 /* Unless the register previously died in PLACE, clear
12743 reg_last_death. [I no longer understand why this is
12745 if (reg_last_death[regno] != place)
12746 reg_last_death[regno] = 0;
12750 reg_last_death[regno] = place;
12752 /* If this is a death note for a hard reg that is occupying
12753 multiple registers, ensure that we are still using all
12754 parts of the object. If we find a piece of the object
12755 that is unused, we must arrange for an appropriate REG_DEAD
12756 note to be added for it. However, we can't just emit a USE
12757 and tag the note to it, since the register might actually
12758 be dead; so we recourse, and the recursive call then finds
12759 the previous insn that used this register. */
12761 if (place && regno < FIRST_PSEUDO_REGISTER
12762 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12764 unsigned int endregno
12765 = regno + HARD_REGNO_NREGS (regno,
12766 GET_MODE (XEXP (note, 0)));
12770 for (i = regno; i < endregno; i++)
12771 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12772 && ! find_regno_fusage (place, USE, i))
12773 || dead_or_set_regno_p (place, i))
12778 /* Put only REG_DEAD notes for pieces that are
12779 not already dead or set. */
12781 for (i = regno; i < endregno;
12782 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12784 rtx piece = regno_reg_rtx[i];
12785 basic_block bb = this_basic_block;
12787 if (! dead_or_set_p (place, piece)
12788 && ! reg_bitfield_target_p (piece,
12792 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12794 distribute_notes (new_note, place, place,
12795 NULL_RTX, NULL_RTX, NULL_RTX);
12797 else if (! refers_to_regno_p (i, i + 1,
12798 PATTERN (place), 0)
12799 && ! find_regno_fusage (place, USE, i))
12800 for (tem = PREV_INSN (place); ;
12801 tem = PREV_INSN (tem))
12803 if (! INSN_P (tem))
12805 if (tem == bb->head)
12807 SET_BIT (refresh_blocks,
12808 this_basic_block->index);
12813 if (dead_or_set_p (tem, piece)
12814 || reg_bitfield_target_p (piece,
12818 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12833 /* Any other notes should not be present at this point in the
12840 XEXP (note, 1) = REG_NOTES (place);
12841 REG_NOTES (place) = note;
12843 else if ((REG_NOTE_KIND (note) == REG_DEAD
12844 || REG_NOTE_KIND (note) == REG_UNUSED)
12845 && GET_CODE (XEXP (note, 0)) == REG)
12846 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12850 if ((REG_NOTE_KIND (note) == REG_DEAD
12851 || REG_NOTE_KIND (note) == REG_UNUSED)
12852 && GET_CODE (XEXP (note, 0)) == REG)
12853 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12855 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12856 REG_NOTE_KIND (note),
12858 REG_NOTES (place2));
12863 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12864 I3, I2, and I1 to new locations. This is also called in one case to
12865 add a link pointing at I3 when I3's destination is changed. */
12868 distribute_links (links)
12871 rtx link, next_link;
12873 for (link = links; link; link = next_link)
12879 next_link = XEXP (link, 1);
12881 /* If the insn that this link points to is a NOTE or isn't a single
12882 set, ignore it. In the latter case, it isn't clear what we
12883 can do other than ignore the link, since we can't tell which
12884 register it was for. Such links wouldn't be used by combine
12887 It is not possible for the destination of the target of the link to
12888 have been changed by combine. The only potential of this is if we
12889 replace I3, I2, and I1 by I3 and I2. But in that case the
12890 destination of I2 also remains unchanged. */
12892 if (GET_CODE (XEXP (link, 0)) == NOTE
12893 || (set = single_set (XEXP (link, 0))) == 0)
12896 reg = SET_DEST (set);
12897 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12898 || GET_CODE (reg) == SIGN_EXTRACT
12899 || GET_CODE (reg) == STRICT_LOW_PART)
12900 reg = XEXP (reg, 0);
12902 /* A LOG_LINK is defined as being placed on the first insn that uses
12903 a register and points to the insn that sets the register. Start
12904 searching at the next insn after the target of the link and stop
12905 when we reach a set of the register or the end of the basic block.
12907 Note that this correctly handles the link that used to point from
12908 I3 to I2. Also note that not much searching is typically done here
12909 since most links don't point very far away. */
12911 for (insn = NEXT_INSN (XEXP (link, 0));
12912 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12913 || this_basic_block->next_bb->head != insn));
12914 insn = NEXT_INSN (insn))
12915 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12917 if (reg_referenced_p (reg, PATTERN (insn)))
12921 else if (GET_CODE (insn) == CALL_INSN
12922 && find_reg_fusage (insn, USE, reg))
12928 /* If we found a place to put the link, place it there unless there
12929 is already a link to the same insn as LINK at that point. */
12935 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12936 if (XEXP (link2, 0) == XEXP (link, 0))
12941 XEXP (link, 1) = LOG_LINKS (place);
12942 LOG_LINKS (place) = link;
12944 /* Set added_links_insn to the earliest insn we added a
12946 if (added_links_insn == 0
12947 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12948 added_links_insn = place;
12954 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12960 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12961 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12962 insn = NEXT_INSN (insn);
12964 if (INSN_UID (insn) > max_uid_cuid)
12967 return INSN_CUID (insn);
12971 dump_combine_stats (file)
12976 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12977 combine_attempts, combine_merges, combine_extras, combine_successes);
12981 dump_combine_total_stats (file)
12986 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12987 total_attempts, total_merges, total_extras, total_successes);