1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
85 #include "hard-reg-set.h"
86 #include "basic-block.h"
87 #include "insn-config.h"
89 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid;
129 static int max_uid_cuid;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 #define nonzero_bits(X, M) \
143 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
145 #define num_sign_bit_copies(X, M) \
146 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno;
152 /* Record last point of death of (hard or pseudo) register n. */
154 static rtx *reg_last_death;
156 /* Record last point of modification of (hard or pseudo) register n. */
158 static rtx *reg_last_set;
160 /* Record the cuid of the last insn that invalidated memory
161 (anything that writes memory, and subroutine calls, but not pushes). */
163 static int mem_last_set;
165 /* Record the cuid of the last CALL_INSN
166 so we can tell whether a potential combination crosses any calls. */
168 static int last_call_cuid;
170 /* When `subst' is called, this is the insn that is being modified
171 (by combining in a previous insn). The PATTERN of this insn
172 is still the old pattern partially modified and it should not be
173 looked at, but this may be used to examine the successors of the insn
174 to judge whether a simplification is valid. */
176 static rtx subst_insn;
178 /* This is the lowest CUID that `subst' is currently dealing with.
179 get_last_value will not return a value if the register was set at or
180 after this CUID. If not for this mechanism, we could get confused if
181 I2 or I1 in try_combine were an insn that used the old value of a register
182 to obtain a new value. In that case, we might erroneously get the
183 new value of the register when we wanted the old one. */
185 static int subst_low_cuid;
187 /* This contains any hard registers that are used in newpat; reg_dead_at_p
188 must consider all these registers to be always live. */
190 static HARD_REG_SET newpat_used_regs;
192 /* This is an insn to which a LOG_LINKS entry has been added. If this
193 insn is the earlier than I2 or I3, combine should rescan starting at
196 static rtx added_links_insn;
198 /* Basic block in which we are performing combines. */
199 static basic_block this_basic_block;
201 /* A bitmap indicating which blocks had registers go dead at entry.
202 After combine, we'll need to re-do global life analysis with
203 those blocks as starting points. */
204 static sbitmap refresh_blocks;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if an
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to nonzero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is nonzero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set nonzero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx *reg_last_set_value;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick;
264 /* Set nonzero if references to register n in expressions should not be
267 static char *reg_last_set_invalid;
269 /* Incremented for each label. */
271 static int label_tick;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static unsigned char *reg_sign_bit_copies;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode *reg_last_set_mode;
308 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
309 static char *reg_last_set_sign_bit_copies;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 other_insn is nonzero if we have modified some other insn in the process
327 of working on subst_insn. It must be verified too. */
336 static struct undobuf undobuf;
338 /* Number of times the pseudo being substituted for
339 was found and replaced. */
341 static int n_occurrences;
343 static void do_SUBST PARAMS ((rtx *, rtx));
344 static void do_SUBST_INT PARAMS ((int *, int));
345 static void init_reg_last_arrays PARAMS ((void));
346 static void setup_incoming_promotions PARAMS ((void));
347 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
348 static int cant_combine_insn_p PARAMS ((rtx));
349 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
350 static int sets_function_arg_p PARAMS ((rtx));
351 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
352 static int contains_muldiv PARAMS ((rtx));
353 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
354 static void undo_all PARAMS ((void));
355 static void undo_commit PARAMS ((void));
356 static rtx *find_split_point PARAMS ((rtx *, rtx));
357 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
358 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
359 static rtx simplify_if_then_else PARAMS ((rtx));
360 static rtx simplify_set PARAMS ((rtx));
361 static rtx simplify_logical PARAMS ((rtx, int));
362 static rtx expand_compound_operation PARAMS ((rtx));
363 static rtx expand_field_assignment PARAMS ((rtx));
364 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
365 rtx, unsigned HOST_WIDE_INT, int,
367 static rtx extract_left_shift PARAMS ((rtx, int));
368 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
369 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
370 unsigned HOST_WIDE_INT *));
371 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
372 unsigned HOST_WIDE_INT, rtx, int));
373 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
374 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
375 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
376 static rtx make_field_assignment PARAMS ((rtx));
377 static rtx apply_distributive_law PARAMS ((rtx));
378 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
379 unsigned HOST_WIDE_INT));
380 static unsigned HOST_WIDE_INT cached_nonzero_bits
381 PARAMS ((rtx, enum machine_mode, rtx,
383 unsigned HOST_WIDE_INT));
384 static unsigned HOST_WIDE_INT nonzero_bits1
385 PARAMS ((rtx, enum machine_mode, rtx,
387 unsigned HOST_WIDE_INT));
388 static unsigned int cached_num_sign_bit_copies
389 PARAMS ((rtx, enum machine_mode, rtx,
390 enum machine_mode, unsigned int));
391 static unsigned int num_sign_bit_copies1
392 PARAMS ((rtx, enum machine_mode, rtx,
393 enum machine_mode, unsigned int));
394 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
395 enum rtx_code, HOST_WIDE_INT,
396 enum machine_mode, int *));
397 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
399 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
400 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
401 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
403 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
404 static void update_table_tick PARAMS ((rtx));
405 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
406 static void check_promoted_subreg PARAMS ((rtx, rtx));
407 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
408 static void record_dead_and_set_regs PARAMS ((rtx));
409 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
410 static rtx get_last_value PARAMS ((rtx));
411 static int use_crosses_set_p PARAMS ((rtx, int));
412 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
413 static int reg_dead_at_p PARAMS ((rtx, rtx));
414 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
415 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
416 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
417 static void distribute_links PARAMS ((rtx));
418 static void mark_used_regs_combine PARAMS ((rtx));
419 static int insn_cuid PARAMS ((rtx));
420 static void record_promoted_value PARAMS ((rtx, rtx));
421 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
422 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
424 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
425 insn. The substitution can be undone by undo_all. If INTO is already
426 set to NEWVAL, do not record this change. Because computing NEWVAL might
427 also call SUBST, we have to compute it before we put anything into
431 do_SUBST (into, newval)
437 if (oldval == newval)
440 /* We'd like to catch as many invalid transformations here as
441 possible. Unfortunately, there are way too many mode changes
442 that are perfectly valid, so we'd waste too much effort for
443 little gain doing the checks here. Focus on catching invalid
444 transformations involving integer constants. */
445 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
446 && GET_CODE (newval) == CONST_INT)
448 /* Sanity check that we're replacing oldval with a CONST_INT
449 that is a valid sign-extension for the original mode. */
450 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
454 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
455 CONST_INT is not valid, because after the replacement, the
456 original mode would be gone. Unfortunately, we can't tell
457 when do_SUBST is called to replace the operand thereof, so we
458 perform this test on oldval instead, checking whether an
459 invalid replacement took place before we got here. */
460 if ((GET_CODE (oldval) == SUBREG
461 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
462 || (GET_CODE (oldval) == ZERO_EXTEND
463 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
468 buf = undobuf.frees, undobuf.frees = buf->next;
470 buf = (struct undo *) xmalloc (sizeof (struct undo));
474 buf->old_contents.r = oldval;
477 buf->next = undobuf.undos, undobuf.undos = buf;
480 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
482 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
483 for the value of a HOST_WIDE_INT value (including CONST_INT) is
487 do_SUBST_INT (into, newval)
493 if (oldval == newval)
497 buf = undobuf.frees, undobuf.frees = buf->next;
499 buf = (struct undo *) xmalloc (sizeof (struct undo));
503 buf->old_contents.i = oldval;
506 buf->next = undobuf.undos, undobuf.undos = buf;
509 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
511 /* Main entry point for combiner. F is the first insn of the function.
512 NREGS is the first unused pseudo-reg number.
514 Return nonzero if the combiner has turned an indirect jump
515 instruction into a direct jump. */
517 combine_instructions (f, nregs)
526 rtx links, nextlinks;
528 int new_direct_jump_p = 0;
530 combine_attempts = 0;
533 combine_successes = 0;
535 combine_max_regno = nregs;
537 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
538 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
540 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
542 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
543 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
544 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
545 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
546 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
547 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
549 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
550 reg_last_set_nonzero_bits
551 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
552 reg_last_set_sign_bit_copies
553 = (char *) xmalloc (nregs * sizeof (char));
555 init_reg_last_arrays ();
557 init_recog_no_volatile ();
559 /* Compute maximum uid value so uid_cuid can be allocated. */
561 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
562 if (INSN_UID (insn) > i)
565 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
568 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
570 /* Don't use reg_nonzero_bits when computing it. This can cause problems
571 when, for example, we have j <<= 1 in a loop. */
573 nonzero_sign_valid = 0;
575 /* Compute the mapping from uids to cuids.
576 Cuids are numbers assigned to insns, like uids,
577 except that cuids increase monotonically through the code.
579 Scan all SETs and see if we can deduce anything about what
580 bits are known to be zero for some registers and how many copies
581 of the sign bit are known to exist for those registers.
583 Also set any known values so that we can use it while searching
584 for what bits are known to be set. */
588 setup_incoming_promotions ();
590 refresh_blocks = sbitmap_alloc (last_basic_block);
591 sbitmap_zero (refresh_blocks);
593 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
595 uid_cuid[INSN_UID (insn)] = ++i;
601 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
603 record_dead_and_set_regs (insn);
606 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
607 if (REG_NOTE_KIND (links) == REG_INC)
608 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
613 if (GET_CODE (insn) == CODE_LABEL)
617 nonzero_sign_valid = 1;
619 /* Now scan all the insns in forward order. */
624 init_reg_last_arrays ();
625 setup_incoming_promotions ();
627 FOR_EACH_BB (this_basic_block)
629 for (insn = this_basic_block->head;
630 insn != NEXT_INSN (this_basic_block->end);
631 insn = next ? next : NEXT_INSN (insn))
635 if (GET_CODE (insn) == CODE_LABEL)
638 else if (INSN_P (insn))
640 /* See if we know about function return values before this
641 insn based upon SUBREG flags. */
642 check_promoted_subreg (insn, PATTERN (insn));
644 /* Try this insn with each insn it links back to. */
646 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
647 if ((next = try_combine (insn, XEXP (links, 0),
648 NULL_RTX, &new_direct_jump_p)) != 0)
651 /* Try each sequence of three linked insns ending with this one. */
653 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
655 rtx link = XEXP (links, 0);
657 /* If the linked insn has been replaced by a note, then there
658 is no point in pursuing this chain any further. */
659 if (GET_CODE (link) == NOTE)
662 for (nextlinks = LOG_LINKS (link);
664 nextlinks = XEXP (nextlinks, 1))
665 if ((next = try_combine (insn, link,
667 &new_direct_jump_p)) != 0)
672 /* Try to combine a jump insn that uses CC0
673 with a preceding insn that sets CC0, and maybe with its
674 logical predecessor as well.
675 This is how we make decrement-and-branch insns.
676 We need this special code because data flow connections
677 via CC0 do not get entered in LOG_LINKS. */
679 if (GET_CODE (insn) == JUMP_INSN
680 && (prev = prev_nonnote_insn (insn)) != 0
681 && GET_CODE (prev) == INSN
682 && sets_cc0_p (PATTERN (prev)))
684 if ((next = try_combine (insn, prev,
685 NULL_RTX, &new_direct_jump_p)) != 0)
688 for (nextlinks = LOG_LINKS (prev); nextlinks;
689 nextlinks = XEXP (nextlinks, 1))
690 if ((next = try_combine (insn, prev,
692 &new_direct_jump_p)) != 0)
696 /* Do the same for an insn that explicitly references CC0. */
697 if (GET_CODE (insn) == INSN
698 && (prev = prev_nonnote_insn (insn)) != 0
699 && GET_CODE (prev) == INSN
700 && sets_cc0_p (PATTERN (prev))
701 && GET_CODE (PATTERN (insn)) == SET
702 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
704 if ((next = try_combine (insn, prev,
705 NULL_RTX, &new_direct_jump_p)) != 0)
708 for (nextlinks = LOG_LINKS (prev); nextlinks;
709 nextlinks = XEXP (nextlinks, 1))
710 if ((next = try_combine (insn, prev,
712 &new_direct_jump_p)) != 0)
716 /* Finally, see if any of the insns that this insn links to
717 explicitly references CC0. If so, try this insn, that insn,
718 and its predecessor if it sets CC0. */
719 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
720 if (GET_CODE (XEXP (links, 0)) == INSN
721 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
722 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
723 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
724 && GET_CODE (prev) == INSN
725 && sets_cc0_p (PATTERN (prev))
726 && (next = try_combine (insn, XEXP (links, 0),
727 prev, &new_direct_jump_p)) != 0)
731 /* Try combining an insn with two different insns whose results it
733 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
734 for (nextlinks = XEXP (links, 1); nextlinks;
735 nextlinks = XEXP (nextlinks, 1))
736 if ((next = try_combine (insn, XEXP (links, 0),
738 &new_direct_jump_p)) != 0)
741 if (GET_CODE (insn) != NOTE)
742 record_dead_and_set_regs (insn);
751 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
752 BASIC_BLOCK (i)->flags |= BB_DIRTY);
753 new_direct_jump_p |= purge_all_dead_edges (0);
754 delete_noop_moves (f);
756 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
757 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
758 | PROP_KILL_DEAD_CODE);
761 sbitmap_free (refresh_blocks);
762 free (reg_nonzero_bits);
763 free (reg_sign_bit_copies);
764 free (reg_last_death);
766 free (reg_last_set_value);
767 free (reg_last_set_table_tick);
768 free (reg_last_set_label);
769 free (reg_last_set_invalid);
770 free (reg_last_set_mode);
771 free (reg_last_set_nonzero_bits);
772 free (reg_last_set_sign_bit_copies);
776 struct undo *undo, *next;
777 for (undo = undobuf.frees; undo; undo = next)
785 total_attempts += combine_attempts;
786 total_merges += combine_merges;
787 total_extras += combine_extras;
788 total_successes += combine_successes;
790 nonzero_sign_valid = 0;
792 /* Make recognizer allow volatile MEMs again. */
795 return new_direct_jump_p;
798 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
801 init_reg_last_arrays ()
803 unsigned int nregs = combine_max_regno;
805 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
806 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
807 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
808 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
809 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
810 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
811 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
812 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
813 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
816 /* Set up any promoted values for incoming argument registers. */
819 setup_incoming_promotions ()
821 #ifdef PROMOTE_FUNCTION_ARGS
824 enum machine_mode mode;
826 rtx first = get_insns ();
828 #ifndef OUTGOING_REGNO
829 #define OUTGOING_REGNO(N) N
831 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
832 /* Check whether this register can hold an incoming pointer
833 argument. FUNCTION_ARG_REGNO_P tests outgoing register
834 numbers, so translate if necessary due to register windows. */
835 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
836 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
839 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
842 gen_rtx_CLOBBER (mode, const0_rtx)));
847 /* Called via note_stores. If X is a pseudo that is narrower than
848 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
850 If we are setting only a portion of X and we can't figure out what
851 portion, assume all bits will be used since we don't know what will
854 Similarly, set how many bits of X are known to be copies of the sign bit
855 at all locations in the function. This is the smallest number implied
859 set_nonzero_bits_and_sign_copies (x, set, data)
862 void *data ATTRIBUTE_UNUSED;
866 if (GET_CODE (x) == REG
867 && REGNO (x) >= FIRST_PSEUDO_REGISTER
868 /* If this register is undefined at the start of the file, we can't
869 say what its contents were. */
870 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
871 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
873 if (set == 0 || GET_CODE (set) == CLOBBER)
875 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
876 reg_sign_bit_copies[REGNO (x)] = 1;
880 /* If this is a complex assignment, see if we can convert it into a
881 simple assignment. */
882 set = expand_field_assignment (set);
884 /* If this is a simple assignment, or we have a paradoxical SUBREG,
885 set what we know about X. */
887 if (SET_DEST (set) == x
888 || (GET_CODE (SET_DEST (set)) == SUBREG
889 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
890 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
891 && SUBREG_REG (SET_DEST (set)) == x))
893 rtx src = SET_SRC (set);
895 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
896 /* If X is narrower than a word and SRC is a non-negative
897 constant that would appear negative in the mode of X,
898 sign-extend it for use in reg_nonzero_bits because some
899 machines (maybe most) will actually do the sign-extension
900 and this is the conservative approach.
902 ??? For 2.5, try to tighten up the MD files in this regard
903 instead of this kludge. */
905 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
906 && GET_CODE (src) == CONST_INT
908 && 0 != (INTVAL (src)
910 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
911 src = GEN_INT (INTVAL (src)
912 | ((HOST_WIDE_INT) (-1)
913 << GET_MODE_BITSIZE (GET_MODE (x))));
916 /* Don't call nonzero_bits if it cannot change anything. */
917 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
918 reg_nonzero_bits[REGNO (x)]
919 |= nonzero_bits (src, nonzero_bits_mode);
920 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
921 if (reg_sign_bit_copies[REGNO (x)] == 0
922 || reg_sign_bit_copies[REGNO (x)] > num)
923 reg_sign_bit_copies[REGNO (x)] = num;
927 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
928 reg_sign_bit_copies[REGNO (x)] = 1;
933 /* See if INSN can be combined into I3. PRED and SUCC are optionally
934 insns that were previously combined into I3 or that will be combined
935 into the merger of INSN and I3.
937 Return 0 if the combination is not allowed for any reason.
939 If the combination is allowed, *PDEST will be set to the single
940 destination of INSN and *PSRC to the single source, and this function
944 can_combine_p (insn, i3, pred, succ, pdest, psrc)
947 rtx pred ATTRIBUTE_UNUSED;
952 rtx set = 0, src, dest;
957 int all_adjacent = (succ ? (next_active_insn (insn) == succ
958 && next_active_insn (succ) == i3)
959 : next_active_insn (insn) == i3);
961 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
962 or a PARALLEL consisting of such a SET and CLOBBERs.
964 If INSN has CLOBBER parallel parts, ignore them for our processing.
965 By definition, these happen during the execution of the insn. When it
966 is merged with another insn, all bets are off. If they are, in fact,
967 needed and aren't also supplied in I3, they may be added by
968 recog_for_combine. Otherwise, it won't match.
970 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
973 Get the source and destination of INSN. If more than one, can't
976 if (GET_CODE (PATTERN (insn)) == SET)
977 set = PATTERN (insn);
978 else if (GET_CODE (PATTERN (insn)) == PARALLEL
979 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
981 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
983 rtx elt = XVECEXP (PATTERN (insn), 0, i);
985 switch (GET_CODE (elt))
987 /* This is important to combine floating point insns
990 /* Combining an isolated USE doesn't make sense.
991 We depend here on combinable_i3pat to reject them. */
992 /* The code below this loop only verifies that the inputs of
993 the SET in INSN do not change. We call reg_set_between_p
994 to verify that the REG in the USE does not change between
996 If the USE in INSN was for a pseudo register, the matching
997 insn pattern will likely match any register; combining this
998 with any other USE would only be safe if we knew that the
999 used registers have identical values, or if there was
1000 something to tell them apart, e.g. different modes. For
1001 now, we forgo such complicated tests and simply disallow
1002 combining of USES of pseudo registers with any other USE. */
1003 if (GET_CODE (XEXP (elt, 0)) == REG
1004 && GET_CODE (PATTERN (i3)) == PARALLEL)
1006 rtx i3pat = PATTERN (i3);
1007 int i = XVECLEN (i3pat, 0) - 1;
1008 unsigned int regno = REGNO (XEXP (elt, 0));
1012 rtx i3elt = XVECEXP (i3pat, 0, i);
1014 if (GET_CODE (i3elt) == USE
1015 && GET_CODE (XEXP (i3elt, 0)) == REG
1016 && (REGNO (XEXP (i3elt, 0)) == regno
1017 ? reg_set_between_p (XEXP (elt, 0),
1018 PREV_INSN (insn), i3)
1019 : regno >= FIRST_PSEUDO_REGISTER))
1026 /* We can ignore CLOBBERs. */
1031 /* Ignore SETs whose result isn't used but not those that
1032 have side-effects. */
1033 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1034 && ! side_effects_p (elt))
1037 /* If we have already found a SET, this is a second one and
1038 so we cannot combine with this insn. */
1046 /* Anything else means we can't combine. */
1052 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1053 so don't do anything with it. */
1054 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1063 set = expand_field_assignment (set);
1064 src = SET_SRC (set), dest = SET_DEST (set);
1066 /* Don't eliminate a store in the stack pointer. */
1067 if (dest == stack_pointer_rtx
1068 /* Don't combine with an insn that sets a register to itself if it has
1069 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1070 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1071 /* Can't merge an ASM_OPERANDS. */
1072 || GET_CODE (src) == ASM_OPERANDS
1073 /* Can't merge a function call. */
1074 || GET_CODE (src) == CALL
1075 /* Don't eliminate a function call argument. */
1076 || (GET_CODE (i3) == CALL_INSN
1077 && (find_reg_fusage (i3, USE, dest)
1078 || (GET_CODE (dest) == REG
1079 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1080 && global_regs[REGNO (dest)])))
1081 /* Don't substitute into an incremented register. */
1082 || FIND_REG_INC_NOTE (i3, dest)
1083 || (succ && FIND_REG_INC_NOTE (succ, dest))
1085 /* Don't combine the end of a libcall into anything. */
1086 /* ??? This gives worse code, and appears to be unnecessary, since no
1087 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1088 use REG_RETVAL notes for noconflict blocks, but other code here
1089 makes sure that those insns don't disappear. */
1090 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1092 /* Make sure that DEST is not used after SUCC but before I3. */
1093 || (succ && ! all_adjacent
1094 && reg_used_between_p (dest, succ, i3))
1095 /* Make sure that the value that is to be substituted for the register
1096 does not use any registers whose values alter in between. However,
1097 If the insns are adjacent, a use can't cross a set even though we
1098 think it might (this can happen for a sequence of insns each setting
1099 the same destination; reg_last_set of that register might point to
1100 a NOTE). If INSN has a REG_EQUIV note, the register is always
1101 equivalent to the memory so the substitution is valid even if there
1102 are intervening stores. Also, don't move a volatile asm or
1103 UNSPEC_VOLATILE across any other insns. */
1105 && (((GET_CODE (src) != MEM
1106 || ! find_reg_note (insn, REG_EQUIV, src))
1107 && use_crosses_set_p (src, INSN_CUID (insn)))
1108 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1109 || GET_CODE (src) == UNSPEC_VOLATILE))
1110 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1111 better register allocation by not doing the combine. */
1112 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1113 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1114 /* Don't combine across a CALL_INSN, because that would possibly
1115 change whether the life span of some REGs crosses calls or not,
1116 and it is a pain to update that information.
1117 Exception: if source is a constant, moving it later can't hurt.
1118 Accept that special case, because it helps -fforce-addr a lot. */
1119 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1122 /* DEST must either be a REG or CC0. */
1123 if (GET_CODE (dest) == REG)
1125 /* If register alignment is being enforced for multi-word items in all
1126 cases except for parameters, it is possible to have a register copy
1127 insn referencing a hard register that is not allowed to contain the
1128 mode being copied and which would not be valid as an operand of most
1129 insns. Eliminate this problem by not combining with such an insn.
1131 Also, on some machines we don't want to extend the life of a hard
1134 if (GET_CODE (src) == REG
1135 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1136 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1137 /* Don't extend the life of a hard register unless it is
1138 user variable (if we have few registers) or it can't
1139 fit into the desired register (meaning something special
1141 Also avoid substituting a return register into I3, because
1142 reload can't handle a conflict with constraints of other
1144 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1145 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1148 else if (GET_CODE (dest) != CC0)
1151 /* Don't substitute for a register intended as a clobberable operand.
1152 Similarly, don't substitute an expression containing a register that
1153 will be clobbered in I3. */
1154 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1155 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1156 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1157 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1159 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1162 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1163 or not), reject, unless nothing volatile comes between it and I3 */
1165 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1167 /* Make sure succ doesn't contain a volatile reference. */
1168 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1171 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1172 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1176 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1177 to be an explicit register variable, and was chosen for a reason. */
1179 if (GET_CODE (src) == ASM_OPERANDS
1180 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1183 /* If there are any volatile insns between INSN and I3, reject, because
1184 they might affect machine state. */
1186 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1187 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1190 /* If INSN or I2 contains an autoincrement or autodecrement,
1191 make sure that register is not used between there and I3,
1192 and not already used in I3 either.
1193 Also insist that I3 not be a jump; if it were one
1194 and the incremented register were spilled, we would lose. */
1197 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1198 if (REG_NOTE_KIND (link) == REG_INC
1199 && (GET_CODE (i3) == JUMP_INSN
1200 || reg_used_between_p (XEXP (link, 0), insn, i3)
1201 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1206 /* Don't combine an insn that follows a CC0-setting insn.
1207 An insn that uses CC0 must not be separated from the one that sets it.
1208 We do, however, allow I2 to follow a CC0-setting insn if that insn
1209 is passed as I1; in that case it will be deleted also.
1210 We also allow combining in this case if all the insns are adjacent
1211 because that would leave the two CC0 insns adjacent as well.
1212 It would be more logical to test whether CC0 occurs inside I1 or I2,
1213 but that would be much slower, and this ought to be equivalent. */
1215 p = prev_nonnote_insn (insn);
1216 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1221 /* If we get here, we have passed all the tests and the combination is
1230 /* Check if PAT is an insn - or a part of it - used to set up an
1231 argument for a function in a hard register. */
1234 sets_function_arg_p (pat)
1240 switch (GET_CODE (pat))
1243 return sets_function_arg_p (PATTERN (pat));
1246 for (i = XVECLEN (pat, 0); --i >= 0;)
1247 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1253 inner_dest = SET_DEST (pat);
1254 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1255 || GET_CODE (inner_dest) == SUBREG
1256 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1257 inner_dest = XEXP (inner_dest, 0);
1259 return (GET_CODE (inner_dest) == REG
1260 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1261 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1270 /* LOC is the location within I3 that contains its pattern or the component
1271 of a PARALLEL of the pattern. We validate that it is valid for combining.
1273 One problem is if I3 modifies its output, as opposed to replacing it
1274 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1275 so would produce an insn that is not equivalent to the original insns.
1279 (set (reg:DI 101) (reg:DI 100))
1280 (set (subreg:SI (reg:DI 101) 0) <foo>)
1282 This is NOT equivalent to:
1284 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1285 (set (reg:DI 101) (reg:DI 100))])
1287 Not only does this modify 100 (in which case it might still be valid
1288 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1290 We can also run into a problem if I2 sets a register that I1
1291 uses and I1 gets directly substituted into I3 (not via I2). In that
1292 case, we would be getting the wrong value of I2DEST into I3, so we
1293 must reject the combination. This case occurs when I2 and I1 both
1294 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1295 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1296 of a SET must prevent combination from occurring.
1298 Before doing the above check, we first try to expand a field assignment
1299 into a set of logical operations.
1301 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1302 we place a register that is both set and used within I3. If more than one
1303 such register is detected, we fail.
1305 Return 1 if the combination is valid, zero otherwise. */
1308 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1314 rtx *pi3dest_killed;
1318 if (GET_CODE (x) == SET)
1321 rtx dest = SET_DEST (set);
1322 rtx src = SET_SRC (set);
1323 rtx inner_dest = dest;
1325 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1326 || GET_CODE (inner_dest) == SUBREG
1327 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1328 inner_dest = XEXP (inner_dest, 0);
1330 /* Check for the case where I3 modifies its output, as
1332 if ((inner_dest != dest
1333 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1334 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1336 /* This is the same test done in can_combine_p except we can't test
1337 all_adjacent; we don't have to, since this instruction will stay
1338 in place, thus we are not considering increasing the lifetime of
1341 Also, if this insn sets a function argument, combining it with
1342 something that might need a spill could clobber a previous
1343 function argument; the all_adjacent test in can_combine_p also
1344 checks this; here, we do a more specific test for this case. */
1346 || (GET_CODE (inner_dest) == REG
1347 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1348 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1349 GET_MODE (inner_dest))))
1350 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1353 /* If DEST is used in I3, it is being killed in this insn,
1354 so record that for later.
1355 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1356 STACK_POINTER_REGNUM, since these are always considered to be
1357 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1358 if (pi3dest_killed && GET_CODE (dest) == REG
1359 && reg_referenced_p (dest, PATTERN (i3))
1360 && REGNO (dest) != FRAME_POINTER_REGNUM
1361 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1362 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1364 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1365 && (REGNO (dest) != ARG_POINTER_REGNUM
1366 || ! fixed_regs [REGNO (dest)])
1368 && REGNO (dest) != STACK_POINTER_REGNUM)
1370 if (*pi3dest_killed)
1373 *pi3dest_killed = dest;
1377 else if (GET_CODE (x) == PARALLEL)
1381 for (i = 0; i < XVECLEN (x, 0); i++)
1382 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1383 i1_not_in_src, pi3dest_killed))
1390 /* Return 1 if X is an arithmetic expression that contains a multiplication
1391 and division. We don't count multiplications by powers of two here. */
1397 switch (GET_CODE (x))
1399 case MOD: case DIV: case UMOD: case UDIV:
1403 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1404 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1406 switch (GET_RTX_CLASS (GET_CODE (x)))
1408 case 'c': case '<': case '2':
1409 return contains_muldiv (XEXP (x, 0))
1410 || contains_muldiv (XEXP (x, 1));
1413 return contains_muldiv (XEXP (x, 0));
1421 /* Determine whether INSN can be used in a combination. Return nonzero if
1422 not. This is used in try_combine to detect early some cases where we
1423 can't perform combinations. */
1426 cant_combine_insn_p (insn)
1432 /* If this isn't really an insn, we can't do anything.
1433 This can occur when flow deletes an insn that it has merged into an
1434 auto-increment address. */
1435 if (! INSN_P (insn))
1438 /* Never combine loads and stores involving hard regs. The register
1439 allocator can usually handle such reg-reg moves by tying. If we allow
1440 the combiner to make substitutions of hard regs, we risk aborting in
1441 reload on machines that have SMALL_REGISTER_CLASSES.
1442 As an exception, we allow combinations involving fixed regs; these are
1443 not available to the register allocator so there's no risk involved. */
1445 set = single_set (insn);
1448 src = SET_SRC (set);
1449 dest = SET_DEST (set);
1450 if (GET_CODE (src) == SUBREG)
1451 src = SUBREG_REG (src);
1452 if (GET_CODE (dest) == SUBREG)
1453 dest = SUBREG_REG (dest);
1454 if (REG_P (src) && REG_P (dest)
1455 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1456 && ! fixed_regs[REGNO (src)])
1457 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1458 && ! fixed_regs[REGNO (dest)])))
1464 /* Try to combine the insns I1 and I2 into I3.
1465 Here I1 and I2 appear earlier than I3.
1466 I1 can be zero; then we combine just I2 into I3.
1468 If we are combining three insns and the resulting insn is not recognized,
1469 try splitting it into two insns. If that happens, I2 and I3 are retained
1470 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1473 Return 0 if the combination does not work. Then nothing is changed.
1474 If we did the combination, return the insn at which combine should
1477 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1478 new direct jump instruction. */
1481 try_combine (i3, i2, i1, new_direct_jump_p)
1483 int *new_direct_jump_p;
1485 /* New patterns for I3 and I2, respectively. */
1486 rtx newpat, newi2pat = 0;
1487 int substed_i2 = 0, substed_i1 = 0;
1488 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1489 int added_sets_1, added_sets_2;
1490 /* Total number of SETs to put into I3. */
1492 /* Nonzero is I2's body now appears in I3. */
1494 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1495 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1496 /* Contains I3 if the destination of I3 is used in its source, which means
1497 that the old life of I3 is being killed. If that usage is placed into
1498 I2 and not in I3, a REG_DEAD note must be made. */
1499 rtx i3dest_killed = 0;
1500 /* SET_DEST and SET_SRC of I2 and I1. */
1501 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1502 /* PATTERN (I2), or a copy of it in certain cases. */
1504 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1505 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1506 int i1_feeds_i3 = 0;
1507 /* Notes that must be added to REG_NOTES in I3 and I2. */
1508 rtx new_i3_notes, new_i2_notes;
1509 /* Notes that we substituted I3 into I2 instead of the normal case. */
1510 int i3_subst_into_i2 = 0;
1511 /* Notes that I1, I2 or I3 is a MULT operation. */
1519 /* Exit early if one of the insns involved can't be used for
1521 if (cant_combine_insn_p (i3)
1522 || cant_combine_insn_p (i2)
1523 || (i1 && cant_combine_insn_p (i1))
1524 /* We also can't do anything if I3 has a
1525 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1528 /* ??? This gives worse code, and appears to be unnecessary, since no
1529 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1530 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1536 undobuf.other_insn = 0;
1538 /* Reset the hard register usage information. */
1539 CLEAR_HARD_REG_SET (newpat_used_regs);
1541 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1542 code below, set I1 to be the earlier of the two insns. */
1543 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1544 temp = i1, i1 = i2, i2 = temp;
1546 added_links_insn = 0;
1548 /* First check for one important special-case that the code below will
1549 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1550 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1551 we may be able to replace that destination with the destination of I3.
1552 This occurs in the common code where we compute both a quotient and
1553 remainder into a structure, in which case we want to do the computation
1554 directly into the structure to avoid register-register copies.
1556 Note that this case handles both multiple sets in I2 and also
1557 cases where I2 has a number of CLOBBER or PARALLELs.
1559 We make very conservative checks below and only try to handle the
1560 most common cases of this. For example, we only handle the case
1561 where I2 and I3 are adjacent to avoid making difficult register
1564 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1565 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1566 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1567 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1568 && GET_CODE (PATTERN (i2)) == PARALLEL
1569 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1570 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1571 below would need to check what is inside (and reg_overlap_mentioned_p
1572 doesn't support those codes anyway). Don't allow those destinations;
1573 the resulting insn isn't likely to be recognized anyway. */
1574 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1575 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1576 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1577 SET_DEST (PATTERN (i3)))
1578 && next_real_insn (i2) == i3)
1580 rtx p2 = PATTERN (i2);
1582 /* Make sure that the destination of I3,
1583 which we are going to substitute into one output of I2,
1584 is not used within another output of I2. We must avoid making this:
1585 (parallel [(set (mem (reg 69)) ...)
1586 (set (reg 69) ...)])
1587 which is not well-defined as to order of actions.
1588 (Besides, reload can't handle output reloads for this.)
1590 The problem can also happen if the dest of I3 is a memory ref,
1591 if another dest in I2 is an indirect memory ref. */
1592 for (i = 0; i < XVECLEN (p2, 0); i++)
1593 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1594 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1595 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1596 SET_DEST (XVECEXP (p2, 0, i))))
1599 if (i == XVECLEN (p2, 0))
1600 for (i = 0; i < XVECLEN (p2, 0); i++)
1601 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1602 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1603 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1608 subst_low_cuid = INSN_CUID (i2);
1610 added_sets_2 = added_sets_1 = 0;
1611 i2dest = SET_SRC (PATTERN (i3));
1613 /* Replace the dest in I2 with our dest and make the resulting
1614 insn the new pattern for I3. Then skip to where we
1615 validate the pattern. Everything was set up above. */
1616 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1617 SET_DEST (PATTERN (i3)));
1620 i3_subst_into_i2 = 1;
1621 goto validate_replacement;
1625 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1626 one of those words to another constant, merge them by making a new
1629 && (temp = single_set (i2)) != 0
1630 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1631 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1632 && GET_CODE (SET_DEST (temp)) == REG
1633 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1634 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1635 && GET_CODE (PATTERN (i3)) == SET
1636 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1637 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1638 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1639 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1640 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1642 HOST_WIDE_INT lo, hi;
1644 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1645 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1648 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1649 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1652 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1654 /* We don't handle the case of the target word being wider
1655 than a host wide int. */
1656 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1659 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1660 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1661 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1663 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1664 hi = INTVAL (SET_SRC (PATTERN (i3)));
1665 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1667 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1668 >> (HOST_BITS_PER_WIDE_INT - 1));
1670 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1671 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1672 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1673 (INTVAL (SET_SRC (PATTERN (i3)))));
1675 hi = lo < 0 ? -1 : 0;
1678 /* We don't handle the case of the higher word not fitting
1679 entirely in either hi or lo. */
1684 subst_low_cuid = INSN_CUID (i2);
1685 added_sets_2 = added_sets_1 = 0;
1686 i2dest = SET_DEST (temp);
1688 SUBST (SET_SRC (temp),
1689 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1691 newpat = PATTERN (i2);
1692 goto validate_replacement;
1696 /* If we have no I1 and I2 looks like:
1697 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1699 make up a dummy I1 that is
1702 (set (reg:CC X) (compare:CC Y (const_int 0)))
1704 (We can ignore any trailing CLOBBERs.)
1706 This undoes a previous combination and allows us to match a branch-and-
1709 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1710 && XVECLEN (PATTERN (i2), 0) >= 2
1711 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1712 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1714 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1715 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1716 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1717 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1718 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1719 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1721 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1722 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1727 /* We make I1 with the same INSN_UID as I2. This gives it
1728 the same INSN_CUID for value tracking. Our fake I1 will
1729 never appear in the insn stream so giving it the same INSN_UID
1730 as I2 will not cause a problem. */
1732 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1733 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1734 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1737 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1738 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1739 SET_DEST (PATTERN (i1)));
1744 /* Verify that I2 and I1 are valid for combining. */
1745 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1746 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1752 /* Record whether I2DEST is used in I2SRC and similarly for the other
1753 cases. Knowing this will help in register status updating below. */
1754 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1755 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1756 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1758 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1760 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1762 /* Ensure that I3's pattern can be the destination of combines. */
1763 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1764 i1 && i2dest_in_i1src && i1_feeds_i3,
1771 /* See if any of the insns is a MULT operation. Unless one is, we will
1772 reject a combination that is, since it must be slower. Be conservative
1774 if (GET_CODE (i2src) == MULT
1775 || (i1 != 0 && GET_CODE (i1src) == MULT)
1776 || (GET_CODE (PATTERN (i3)) == SET
1777 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1780 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1781 We used to do this EXCEPT in one case: I3 has a post-inc in an
1782 output operand. However, that exception can give rise to insns like
1784 which is a famous insn on the PDP-11 where the value of r3 used as the
1785 source was model-dependent. Avoid this sort of thing. */
1788 if (!(GET_CODE (PATTERN (i3)) == SET
1789 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1790 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1791 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1792 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1793 /* It's not the exception. */
1796 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1797 if (REG_NOTE_KIND (link) == REG_INC
1798 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1800 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1807 /* See if the SETs in I1 or I2 need to be kept around in the merged
1808 instruction: whenever the value set there is still needed past I3.
1809 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1811 For the SET in I1, we have two cases: If I1 and I2 independently
1812 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1813 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1814 in I1 needs to be kept around unless I1DEST dies or is set in either
1815 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1816 I1DEST. If so, we know I1 feeds into I2. */
1818 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1821 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1822 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1824 /* If the set in I2 needs to be kept around, we must make a copy of
1825 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1826 PATTERN (I2), we are only substituting for the original I1DEST, not into
1827 an already-substituted copy. This also prevents making self-referential
1828 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1831 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1832 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1836 i2pat = copy_rtx (i2pat);
1840 /* Substitute in the latest insn for the regs set by the earlier ones. */
1842 maxreg = max_reg_num ();
1846 /* It is possible that the source of I2 or I1 may be performing an
1847 unneeded operation, such as a ZERO_EXTEND of something that is known
1848 to have the high part zero. Handle that case by letting subst look at
1849 the innermost one of them.
1851 Another way to do this would be to have a function that tries to
1852 simplify a single insn instead of merging two or more insns. We don't
1853 do this because of the potential of infinite loops and because
1854 of the potential extra memory required. However, doing it the way
1855 we are is a bit of a kludge and doesn't catch all cases.
1857 But only do this if -fexpensive-optimizations since it slows things down
1858 and doesn't usually win. */
1860 if (flag_expensive_optimizations)
1862 /* Pass pc_rtx so no substitutions are done, just simplifications.
1863 The cases that we are interested in here do not involve the few
1864 cases were is_replaced is checked. */
1867 subst_low_cuid = INSN_CUID (i1);
1868 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1872 subst_low_cuid = INSN_CUID (i2);
1873 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1878 /* Many machines that don't use CC0 have insns that can both perform an
1879 arithmetic operation and set the condition code. These operations will
1880 be represented as a PARALLEL with the first element of the vector
1881 being a COMPARE of an arithmetic operation with the constant zero.
1882 The second element of the vector will set some pseudo to the result
1883 of the same arithmetic operation. If we simplify the COMPARE, we won't
1884 match such a pattern and so will generate an extra insn. Here we test
1885 for this case, where both the comparison and the operation result are
1886 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1887 I2SRC. Later we will make the PARALLEL that contains I2. */
1889 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1890 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1891 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1892 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1894 #ifdef EXTRA_CC_MODES
1896 enum machine_mode compare_mode;
1899 newpat = PATTERN (i3);
1900 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1904 #ifdef EXTRA_CC_MODES
1905 /* See if a COMPARE with the operand we substituted in should be done
1906 with the mode that is currently being used. If not, do the same
1907 processing we do in `subst' for a SET; namely, if the destination
1908 is used only once, try to replace it with a register of the proper
1909 mode and also replace the COMPARE. */
1910 if (undobuf.other_insn == 0
1911 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1912 &undobuf.other_insn))
1913 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1915 != GET_MODE (SET_DEST (newpat))))
1917 unsigned int regno = REGNO (SET_DEST (newpat));
1918 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1920 if (regno < FIRST_PSEUDO_REGISTER
1921 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1922 && ! REG_USERVAR_P (SET_DEST (newpat))))
1924 if (regno >= FIRST_PSEUDO_REGISTER)
1925 SUBST (regno_reg_rtx[regno], new_dest);
1927 SUBST (SET_DEST (newpat), new_dest);
1928 SUBST (XEXP (*cc_use, 0), new_dest);
1929 SUBST (SET_SRC (newpat),
1930 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1933 undobuf.other_insn = 0;
1940 n_occurrences = 0; /* `subst' counts here */
1942 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1943 need to make a unique copy of I2SRC each time we substitute it
1944 to avoid self-referential rtl. */
1946 subst_low_cuid = INSN_CUID (i2);
1947 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1948 ! i1_feeds_i3 && i1dest_in_i1src);
1951 /* Record whether i2's body now appears within i3's body. */
1952 i2_is_used = n_occurrences;
1955 /* If we already got a failure, don't try to do more. Otherwise,
1956 try to substitute in I1 if we have it. */
1958 if (i1 && GET_CODE (newpat) != CLOBBER)
1960 /* Before we can do this substitution, we must redo the test done
1961 above (see detailed comments there) that ensures that I1DEST
1962 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1964 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1972 subst_low_cuid = INSN_CUID (i1);
1973 newpat = subst (newpat, i1dest, i1src, 0, 0);
1977 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1978 to count all the ways that I2SRC and I1SRC can be used. */
1979 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1980 && i2_is_used + added_sets_2 > 1)
1981 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1982 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1984 /* Fail if we tried to make a new register (we used to abort, but there's
1985 really no reason to). */
1986 || max_reg_num () != maxreg
1987 /* Fail if we couldn't do something and have a CLOBBER. */
1988 || GET_CODE (newpat) == CLOBBER
1989 /* Fail if this new pattern is a MULT and we didn't have one before
1990 at the outer level. */
1991 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1998 /* If the actions of the earlier insns must be kept
1999 in addition to substituting them into the latest one,
2000 we must make a new PARALLEL for the latest insn
2001 to hold additional the SETs. */
2003 if (added_sets_1 || added_sets_2)
2007 if (GET_CODE (newpat) == PARALLEL)
2009 rtvec old = XVEC (newpat, 0);
2010 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2011 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2012 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2013 sizeof (old->elem[0]) * old->num_elem);
2018 total_sets = 1 + added_sets_1 + added_sets_2;
2019 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2020 XVECEXP (newpat, 0, 0) = old;
2024 XVECEXP (newpat, 0, --total_sets)
2025 = (GET_CODE (PATTERN (i1)) == PARALLEL
2026 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2030 /* If there is no I1, use I2's body as is. We used to also not do
2031 the subst call below if I2 was substituted into I3,
2032 but that could lose a simplification. */
2034 XVECEXP (newpat, 0, --total_sets) = i2pat;
2036 /* See comment where i2pat is assigned. */
2037 XVECEXP (newpat, 0, --total_sets)
2038 = subst (i2pat, i1dest, i1src, 0, 0);
2042 /* We come here when we are replacing a destination in I2 with the
2043 destination of I3. */
2044 validate_replacement:
2046 /* Note which hard regs this insn has as inputs. */
2047 mark_used_regs_combine (newpat);
2049 /* Is the result of combination a valid instruction? */
2050 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2052 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2053 the second SET's destination is a register that is unused. In that case,
2054 we just need the first SET. This can occur when simplifying a divmod
2055 insn. We *must* test for this case here because the code below that
2056 splits two independent SETs doesn't handle this case correctly when it
2057 updates the register status. Also check the case where the first
2058 SET's destination is unused. That would not cause incorrect code, but
2059 does cause an unneeded insn to remain. */
2061 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2062 && XVECLEN (newpat, 0) == 2
2063 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2064 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2065 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2066 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2067 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2068 && asm_noperands (newpat) < 0)
2070 newpat = XVECEXP (newpat, 0, 0);
2071 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2074 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2075 && XVECLEN (newpat, 0) == 2
2076 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2077 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2078 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2079 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2080 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2081 && asm_noperands (newpat) < 0)
2083 newpat = XVECEXP (newpat, 0, 1);
2084 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2087 /* If we were combining three insns and the result is a simple SET
2088 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2089 insns. There are two ways to do this. It can be split using a
2090 machine-specific method (like when you have an addition of a large
2091 constant) or by combine in the function find_split_point. */
2093 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2094 && asm_noperands (newpat) < 0)
2096 rtx m_split, *split;
2097 rtx ni2dest = i2dest;
2099 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2100 use I2DEST as a scratch register will help. In the latter case,
2101 convert I2DEST to the mode of the source of NEWPAT if we can. */
2103 m_split = split_insns (newpat, i3);
2105 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2106 inputs of NEWPAT. */
2108 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2109 possible to try that as a scratch reg. This would require adding
2110 more code to make it work though. */
2112 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2114 /* If I2DEST is a hard register or the only use of a pseudo,
2115 we can change its mode. */
2116 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2117 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2118 && GET_CODE (i2dest) == REG
2119 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2120 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2121 && ! REG_USERVAR_P (i2dest))))
2122 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2125 m_split = split_insns (gen_rtx_PARALLEL
2127 gen_rtvec (2, newpat,
2128 gen_rtx_CLOBBER (VOIDmode,
2131 /* If the split with the mode-changed register didn't work, try
2132 the original register. */
2133 if (! m_split && ni2dest != i2dest)
2136 m_split = split_insns (gen_rtx_PARALLEL
2138 gen_rtvec (2, newpat,
2139 gen_rtx_CLOBBER (VOIDmode,
2145 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2147 m_split = PATTERN (m_split);
2148 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2149 if (insn_code_number >= 0)
2152 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2153 && (next_real_insn (i2) == i3
2154 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2157 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2158 newi2pat = PATTERN (m_split);
2160 i3set = single_set (NEXT_INSN (m_split));
2161 i2set = single_set (m_split);
2163 /* In case we changed the mode of I2DEST, replace it in the
2164 pseudo-register table here. We can't do it above in case this
2165 code doesn't get executed and we do a split the other way. */
2167 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2168 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2170 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2172 /* If I2 or I3 has multiple SETs, we won't know how to track
2173 register status, so don't use these insns. If I2's destination
2174 is used between I2 and I3, we also can't use these insns. */
2176 if (i2_code_number >= 0 && i2set && i3set
2177 && (next_real_insn (i2) == i3
2178 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2179 insn_code_number = recog_for_combine (&newi3pat, i3,
2181 if (insn_code_number >= 0)
2184 /* It is possible that both insns now set the destination of I3.
2185 If so, we must show an extra use of it. */
2187 if (insn_code_number >= 0)
2189 rtx new_i3_dest = SET_DEST (i3set);
2190 rtx new_i2_dest = SET_DEST (i2set);
2192 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2193 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2194 || GET_CODE (new_i3_dest) == SUBREG)
2195 new_i3_dest = XEXP (new_i3_dest, 0);
2197 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2198 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2199 || GET_CODE (new_i2_dest) == SUBREG)
2200 new_i2_dest = XEXP (new_i2_dest, 0);
2202 if (GET_CODE (new_i3_dest) == REG
2203 && GET_CODE (new_i2_dest) == REG
2204 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2205 REG_N_SETS (REGNO (new_i2_dest))++;
2209 /* If we can split it and use I2DEST, go ahead and see if that
2210 helps things be recognized. Verify that none of the registers
2211 are set between I2 and I3. */
2212 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2214 && GET_CODE (i2dest) == REG
2216 /* We need I2DEST in the proper mode. If it is a hard register
2217 or the only use of a pseudo, we can change its mode. */
2218 && (GET_MODE (*split) == GET_MODE (i2dest)
2219 || GET_MODE (*split) == VOIDmode
2220 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2221 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2222 && ! REG_USERVAR_P (i2dest)))
2223 && (next_real_insn (i2) == i3
2224 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2225 /* We can't overwrite I2DEST if its value is still used by
2227 && ! reg_referenced_p (i2dest, newpat))
2229 rtx newdest = i2dest;
2230 enum rtx_code split_code = GET_CODE (*split);
2231 enum machine_mode split_mode = GET_MODE (*split);
2233 /* Get NEWDEST as a register in the proper mode. We have already
2234 validated that we can do this. */
2235 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2237 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2239 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2240 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2243 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2244 an ASHIFT. This can occur if it was inside a PLUS and hence
2245 appeared to be a memory address. This is a kludge. */
2246 if (split_code == MULT
2247 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2248 && INTVAL (XEXP (*split, 1)) > 0
2249 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2251 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2252 XEXP (*split, 0), GEN_INT (i)));
2253 /* Update split_code because we may not have a multiply
2255 split_code = GET_CODE (*split);
2258 #ifdef INSN_SCHEDULING
2259 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2260 be written as a ZERO_EXTEND. */
2261 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2263 #ifdef LOAD_EXTEND_OP
2264 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2265 what it really is. */
2266 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2268 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2269 SUBREG_REG (*split)));
2272 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2273 SUBREG_REG (*split)));
2277 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2278 SUBST (*split, newdest);
2279 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2281 /* If the split point was a MULT and we didn't have one before,
2282 don't use one now. */
2283 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2284 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2288 /* Check for a case where we loaded from memory in a narrow mode and
2289 then sign extended it, but we need both registers. In that case,
2290 we have a PARALLEL with both loads from the same memory location.
2291 We can split this into a load from memory followed by a register-register
2292 copy. This saves at least one insn, more if register allocation can
2295 We cannot do this if the destination of the first assignment is a
2296 condition code register or cc0. We eliminate this case by making sure
2297 the SET_DEST and SET_SRC have the same mode.
2299 We cannot do this if the destination of the second assignment is
2300 a register that we have already assumed is zero-extended. Similarly
2301 for a SUBREG of such a register. */
2303 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2304 && GET_CODE (newpat) == PARALLEL
2305 && XVECLEN (newpat, 0) == 2
2306 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2307 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2308 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2309 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2310 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2311 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2312 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2313 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2315 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2316 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2317 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2318 (GET_CODE (temp) == REG
2319 && reg_nonzero_bits[REGNO (temp)] != 0
2320 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2321 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2322 && (reg_nonzero_bits[REGNO (temp)]
2323 != GET_MODE_MASK (word_mode))))
2324 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2325 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2326 (GET_CODE (temp) == REG
2327 && reg_nonzero_bits[REGNO (temp)] != 0
2328 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2329 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2330 && (reg_nonzero_bits[REGNO (temp)]
2331 != GET_MODE_MASK (word_mode)))))
2332 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2333 SET_SRC (XVECEXP (newpat, 0, 1)))
2334 && ! find_reg_note (i3, REG_UNUSED,
2335 SET_DEST (XVECEXP (newpat, 0, 0))))
2339 newi2pat = XVECEXP (newpat, 0, 0);
2340 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2341 newpat = XVECEXP (newpat, 0, 1);
2342 SUBST (SET_SRC (newpat),
2343 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2344 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2346 if (i2_code_number >= 0)
2347 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2349 if (insn_code_number >= 0)
2354 /* If we will be able to accept this, we have made a change to the
2355 destination of I3. This can invalidate a LOG_LINKS pointing
2356 to I3. No other part of combine.c makes such a transformation.
2358 The new I3 will have a destination that was previously the
2359 destination of I1 or I2 and which was used in i2 or I3. Call
2360 distribute_links to make a LOG_LINK from the next use of
2361 that destination. */
2363 PATTERN (i3) = newpat;
2364 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2366 /* I3 now uses what used to be its destination and which is
2367 now I2's destination. That means we need a LOG_LINK from
2368 I3 to I2. But we used to have one, so we still will.
2370 However, some later insn might be using I2's dest and have
2371 a LOG_LINK pointing at I3. We must remove this link.
2372 The simplest way to remove the link is to point it at I1,
2373 which we know will be a NOTE. */
2375 for (insn = NEXT_INSN (i3);
2376 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2377 || insn != this_basic_block->next_bb->head);
2378 insn = NEXT_INSN (insn))
2380 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2382 for (link = LOG_LINKS (insn); link;
2383 link = XEXP (link, 1))
2384 if (XEXP (link, 0) == i3)
2385 XEXP (link, 0) = i1;
2393 /* Similarly, check for a case where we have a PARALLEL of two independent
2394 SETs but we started with three insns. In this case, we can do the sets
2395 as two separate insns. This case occurs when some SET allows two
2396 other insns to combine, but the destination of that SET is still live. */
2398 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2399 && GET_CODE (newpat) == PARALLEL
2400 && XVECLEN (newpat, 0) == 2
2401 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2402 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2403 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2404 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2405 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2406 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2407 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2409 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2410 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2411 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2412 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2413 XVECEXP (newpat, 0, 0))
2414 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2415 XVECEXP (newpat, 0, 1))
2416 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2417 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2419 /* Normally, it doesn't matter which of the two is done first,
2420 but it does if one references cc0. In that case, it has to
2423 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2425 newi2pat = XVECEXP (newpat, 0, 0);
2426 newpat = XVECEXP (newpat, 0, 1);
2431 newi2pat = XVECEXP (newpat, 0, 1);
2432 newpat = XVECEXP (newpat, 0, 0);
2435 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2437 if (i2_code_number >= 0)
2438 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2441 /* If it still isn't recognized, fail and change things back the way they
2443 if ((insn_code_number < 0
2444 /* Is the result a reasonable ASM_OPERANDS? */
2445 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2451 /* If we had to change another insn, make sure it is valid also. */
2452 if (undobuf.other_insn)
2454 rtx other_pat = PATTERN (undobuf.other_insn);
2455 rtx new_other_notes;
2458 CLEAR_HARD_REG_SET (newpat_used_regs);
2460 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2463 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2469 PATTERN (undobuf.other_insn) = other_pat;
2471 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2472 are still valid. Then add any non-duplicate notes added by
2473 recog_for_combine. */
2474 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2476 next = XEXP (note, 1);
2478 if (REG_NOTE_KIND (note) == REG_UNUSED
2479 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2481 if (GET_CODE (XEXP (note, 0)) == REG)
2482 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2484 remove_note (undobuf.other_insn, note);
2488 for (note = new_other_notes; note; note = XEXP (note, 1))
2489 if (GET_CODE (XEXP (note, 0)) == REG)
2490 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2492 distribute_notes (new_other_notes, undobuf.other_insn,
2493 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2496 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2497 they are adjacent to each other or not. */
2499 rtx p = prev_nonnote_insn (i3);
2500 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2501 && sets_cc0_p (newi2pat))
2509 /* We now know that we can do this combination. Merge the insns and
2510 update the status of registers and LOG_LINKS. */
2513 rtx i3notes, i2notes, i1notes = 0;
2514 rtx i3links, i2links, i1links = 0;
2517 /* Compute which registers we expect to eliminate. newi2pat may be setting
2518 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2519 same as i3dest, in which case newi2pat may be setting i1dest. */
2520 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2521 || i2dest_in_i2src || i2dest_in_i1src
2523 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2524 || (newi2pat && reg_set_p (i1dest, newi2pat))
2527 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2529 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2530 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2532 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2534 /* Ensure that we do not have something that should not be shared but
2535 occurs multiple times in the new insns. Check this by first
2536 resetting all the `used' flags and then copying anything is shared. */
2538 reset_used_flags (i3notes);
2539 reset_used_flags (i2notes);
2540 reset_used_flags (i1notes);
2541 reset_used_flags (newpat);
2542 reset_used_flags (newi2pat);
2543 if (undobuf.other_insn)
2544 reset_used_flags (PATTERN (undobuf.other_insn));
2546 i3notes = copy_rtx_if_shared (i3notes);
2547 i2notes = copy_rtx_if_shared (i2notes);
2548 i1notes = copy_rtx_if_shared (i1notes);
2549 newpat = copy_rtx_if_shared (newpat);
2550 newi2pat = copy_rtx_if_shared (newi2pat);
2551 if (undobuf.other_insn)
2552 reset_used_flags (PATTERN (undobuf.other_insn));
2554 INSN_CODE (i3) = insn_code_number;
2555 PATTERN (i3) = newpat;
2557 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2559 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2561 reset_used_flags (call_usage);
2562 call_usage = copy_rtx (call_usage);
2565 replace_rtx (call_usage, i2dest, i2src);
2568 replace_rtx (call_usage, i1dest, i1src);
2570 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2573 if (undobuf.other_insn)
2574 INSN_CODE (undobuf.other_insn) = other_code_number;
2576 /* We had one special case above where I2 had more than one set and
2577 we replaced a destination of one of those sets with the destination
2578 of I3. In that case, we have to update LOG_LINKS of insns later
2579 in this basic block. Note that this (expensive) case is rare.
2581 Also, in this case, we must pretend that all REG_NOTEs for I2
2582 actually came from I3, so that REG_UNUSED notes from I2 will be
2583 properly handled. */
2585 if (i3_subst_into_i2)
2587 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2588 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2589 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2590 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2591 && ! find_reg_note (i2, REG_UNUSED,
2592 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2593 for (temp = NEXT_INSN (i2);
2594 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2595 || this_basic_block->head != temp);
2596 temp = NEXT_INSN (temp))
2597 if (temp != i3 && INSN_P (temp))
2598 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2599 if (XEXP (link, 0) == i2)
2600 XEXP (link, 0) = i3;
2605 while (XEXP (link, 1))
2606 link = XEXP (link, 1);
2607 XEXP (link, 1) = i2notes;
2621 INSN_CODE (i2) = i2_code_number;
2622 PATTERN (i2) = newi2pat;
2626 PUT_CODE (i2, NOTE);
2627 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2628 NOTE_SOURCE_FILE (i2) = 0;
2635 PUT_CODE (i1, NOTE);
2636 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2637 NOTE_SOURCE_FILE (i1) = 0;
2640 /* Get death notes for everything that is now used in either I3 or
2641 I2 and used to die in a previous insn. If we built two new
2642 patterns, move from I1 to I2 then I2 to I3 so that we get the
2643 proper movement on registers that I2 modifies. */
2647 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2648 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2651 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2654 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2656 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2659 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2662 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2665 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2668 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2669 know these are REG_UNUSED and want them to go to the desired insn,
2670 so we always pass it as i3. We have not counted the notes in
2671 reg_n_deaths yet, so we need to do so now. */
2673 if (newi2pat && new_i2_notes)
2675 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2676 if (GET_CODE (XEXP (temp, 0)) == REG)
2677 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2679 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2684 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2685 if (GET_CODE (XEXP (temp, 0)) == REG)
2686 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2688 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2691 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2692 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2693 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2694 in that case, it might delete I2. Similarly for I2 and I1.
2695 Show an additional death due to the REG_DEAD note we make here. If
2696 we discard it in distribute_notes, we will decrement it again. */
2700 if (GET_CODE (i3dest_killed) == REG)
2701 REG_N_DEATHS (REGNO (i3dest_killed))++;
2703 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2704 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2706 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2708 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2710 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2714 if (i2dest_in_i2src)
2716 if (GET_CODE (i2dest) == REG)
2717 REG_N_DEATHS (REGNO (i2dest))++;
2719 if (newi2pat && reg_set_p (i2dest, newi2pat))
2720 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2721 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2723 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2724 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2725 NULL_RTX, NULL_RTX);
2728 if (i1dest_in_i1src)
2730 if (GET_CODE (i1dest) == REG)
2731 REG_N_DEATHS (REGNO (i1dest))++;
2733 if (newi2pat && reg_set_p (i1dest, newi2pat))
2734 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2735 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2737 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2738 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2739 NULL_RTX, NULL_RTX);
2742 distribute_links (i3links);
2743 distribute_links (i2links);
2744 distribute_links (i1links);
2746 if (GET_CODE (i2dest) == REG)
2749 rtx i2_insn = 0, i2_val = 0, set;
2751 /* The insn that used to set this register doesn't exist, and
2752 this life of the register may not exist either. See if one of
2753 I3's links points to an insn that sets I2DEST. If it does,
2754 that is now the last known value for I2DEST. If we don't update
2755 this and I2 set the register to a value that depended on its old
2756 contents, we will get confused. If this insn is used, thing
2757 will be set correctly in combine_instructions. */
2759 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2760 if ((set = single_set (XEXP (link, 0))) != 0
2761 && rtx_equal_p (i2dest, SET_DEST (set)))
2762 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2764 record_value_for_reg (i2dest, i2_insn, i2_val);
2766 /* If the reg formerly set in I2 died only once and that was in I3,
2767 zero its use count so it won't make `reload' do any work. */
2769 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2770 && ! i2dest_in_i2src)
2772 regno = REGNO (i2dest);
2773 REG_N_SETS (regno)--;
2777 if (i1 && GET_CODE (i1dest) == REG)
2780 rtx i1_insn = 0, i1_val = 0, set;
2782 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2783 if ((set = single_set (XEXP (link, 0))) != 0
2784 && rtx_equal_p (i1dest, SET_DEST (set)))
2785 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2787 record_value_for_reg (i1dest, i1_insn, i1_val);
2789 regno = REGNO (i1dest);
2790 if (! added_sets_1 && ! i1dest_in_i1src)
2791 REG_N_SETS (regno)--;
2794 /* Update reg_nonzero_bits et al for any changes that may have been made
2795 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2796 important. Because newi2pat can affect nonzero_bits of newpat */
2798 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2799 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2801 /* Set new_direct_jump_p if a new return or simple jump instruction
2804 If I3 is now an unconditional jump, ensure that it has a
2805 BARRIER following it since it may have initially been a
2806 conditional jump. It may also be the last nonnote insn. */
2808 if (returnjump_p (i3) || any_uncondjump_p (i3))
2810 *new_direct_jump_p = 1;
2812 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2813 || GET_CODE (temp) != BARRIER)
2814 emit_barrier_after (i3);
2817 if (undobuf.other_insn != NULL_RTX
2818 && (returnjump_p (undobuf.other_insn)
2819 || any_uncondjump_p (undobuf.other_insn)))
2821 *new_direct_jump_p = 1;
2823 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2824 || GET_CODE (temp) != BARRIER)
2825 emit_barrier_after (undobuf.other_insn);
2828 /* An NOOP jump does not need barrier, but it does need cleaning up
2830 if (GET_CODE (newpat) == SET
2831 && SET_SRC (newpat) == pc_rtx
2832 && SET_DEST (newpat) == pc_rtx)
2833 *new_direct_jump_p = 1;
2836 combine_successes++;
2839 if (added_links_insn
2840 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2841 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2842 return added_links_insn;
2844 return newi2pat ? i2 : i3;
2847 /* Undo all the modifications recorded in undobuf. */
2852 struct undo *undo, *next;
2854 for (undo = undobuf.undos; undo; undo = next)
2858 *undo->where.i = undo->old_contents.i;
2860 *undo->where.r = undo->old_contents.r;
2862 undo->next = undobuf.frees;
2863 undobuf.frees = undo;
2869 /* We've committed to accepting the changes we made. Move all
2870 of the undos to the free list. */
2875 struct undo *undo, *next;
2877 for (undo = undobuf.undos; undo; undo = next)
2880 undo->next = undobuf.frees;
2881 undobuf.frees = undo;
2887 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2888 where we have an arithmetic expression and return that point. LOC will
2891 try_combine will call this function to see if an insn can be split into
2895 find_split_point (loc, insn)
2900 enum rtx_code code = GET_CODE (x);
2902 unsigned HOST_WIDE_INT len = 0;
2903 HOST_WIDE_INT pos = 0;
2905 rtx inner = NULL_RTX;
2907 /* First special-case some codes. */
2911 #ifdef INSN_SCHEDULING
2912 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2914 if (GET_CODE (SUBREG_REG (x)) == MEM)
2917 return find_split_point (&SUBREG_REG (x), insn);
2921 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2922 using LO_SUM and HIGH. */
2923 if (GET_CODE (XEXP (x, 0)) == CONST
2924 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2927 gen_rtx_LO_SUM (Pmode,
2928 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2930 return &XEXP (XEXP (x, 0), 0);
2934 /* If we have a PLUS whose second operand is a constant and the
2935 address is not valid, perhaps will can split it up using
2936 the machine-specific way to split large constants. We use
2937 the first pseudo-reg (one of the virtual regs) as a placeholder;
2938 it will not remain in the result. */
2939 if (GET_CODE (XEXP (x, 0)) == PLUS
2940 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2941 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2943 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2944 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2947 /* This should have produced two insns, each of which sets our
2948 placeholder. If the source of the second is a valid address,
2949 we can make put both sources together and make a split point
2953 && NEXT_INSN (seq) != NULL_RTX
2954 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2955 && GET_CODE (seq) == INSN
2956 && GET_CODE (PATTERN (seq)) == SET
2957 && SET_DEST (PATTERN (seq)) == reg
2958 && ! reg_mentioned_p (reg,
2959 SET_SRC (PATTERN (seq)))
2960 && GET_CODE (NEXT_INSN (seq)) == INSN
2961 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2962 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2963 && memory_address_p (GET_MODE (x),
2964 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2966 rtx src1 = SET_SRC (PATTERN (seq));
2967 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2969 /* Replace the placeholder in SRC2 with SRC1. If we can
2970 find where in SRC2 it was placed, that can become our
2971 split point and we can replace this address with SRC2.
2972 Just try two obvious places. */
2974 src2 = replace_rtx (src2, reg, src1);
2976 if (XEXP (src2, 0) == src1)
2977 split = &XEXP (src2, 0);
2978 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2979 && XEXP (XEXP (src2, 0), 0) == src1)
2980 split = &XEXP (XEXP (src2, 0), 0);
2984 SUBST (XEXP (x, 0), src2);
2989 /* If that didn't work, perhaps the first operand is complex and
2990 needs to be computed separately, so make a split point there.
2991 This will occur on machines that just support REG + CONST
2992 and have a constant moved through some previous computation. */
2994 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2995 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2996 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2998 return &XEXP (XEXP (x, 0), 0);
3004 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3005 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3006 we need to put the operand into a register. So split at that
3009 if (SET_DEST (x) == cc0_rtx
3010 && GET_CODE (SET_SRC (x)) != COMPARE
3011 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3012 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3013 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3014 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3015 return &SET_SRC (x);
3018 /* See if we can split SET_SRC as it stands. */
3019 split = find_split_point (&SET_SRC (x), insn);
3020 if (split && split != &SET_SRC (x))
3023 /* See if we can split SET_DEST as it stands. */
3024 split = find_split_point (&SET_DEST (x), insn);
3025 if (split && split != &SET_DEST (x))
3028 /* See if this is a bitfield assignment with everything constant. If
3029 so, this is an IOR of an AND, so split it into that. */
3030 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3031 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3032 <= HOST_BITS_PER_WIDE_INT)
3033 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3034 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3035 && GET_CODE (SET_SRC (x)) == CONST_INT
3036 && ((INTVAL (XEXP (SET_DEST (x), 1))
3037 + INTVAL (XEXP (SET_DEST (x), 2)))
3038 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3039 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3041 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3042 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3043 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3044 rtx dest = XEXP (SET_DEST (x), 0);
3045 enum machine_mode mode = GET_MODE (dest);
3046 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3048 if (BITS_BIG_ENDIAN)
3049 pos = GET_MODE_BITSIZE (mode) - len - pos;
3053 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3056 gen_binary (IOR, mode,
3057 gen_binary (AND, mode, dest,
3058 gen_int_mode (~(mask << pos),
3060 GEN_INT (src << pos)));
3062 SUBST (SET_DEST (x), dest);
3064 split = find_split_point (&SET_SRC (x), insn);
3065 if (split && split != &SET_SRC (x))
3069 /* Otherwise, see if this is an operation that we can split into two.
3070 If so, try to split that. */
3071 code = GET_CODE (SET_SRC (x));
3076 /* If we are AND'ing with a large constant that is only a single
3077 bit and the result is only being used in a context where we
3078 need to know if it is zero or nonzero, replace it with a bit
3079 extraction. This will avoid the large constant, which might
3080 have taken more than one insn to make. If the constant were
3081 not a valid argument to the AND but took only one insn to make,
3082 this is no worse, but if it took more than one insn, it will
3085 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3086 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3087 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3088 && GET_CODE (SET_DEST (x)) == REG
3089 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3090 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3091 && XEXP (*split, 0) == SET_DEST (x)
3092 && XEXP (*split, 1) == const0_rtx)
3094 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3095 XEXP (SET_SRC (x), 0),
3096 pos, NULL_RTX, 1, 1, 0, 0);
3097 if (extraction != 0)
3099 SUBST (SET_SRC (x), extraction);
3100 return find_split_point (loc, insn);
3106 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3107 is known to be on, this can be converted into a NEG of a shift. */
3108 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3109 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3110 && 1 <= (pos = exact_log2
3111 (nonzero_bits (XEXP (SET_SRC (x), 0),
3112 GET_MODE (XEXP (SET_SRC (x), 0))))))
3114 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3118 gen_rtx_LSHIFTRT (mode,
3119 XEXP (SET_SRC (x), 0),
3122 split = find_split_point (&SET_SRC (x), insn);
3123 if (split && split != &SET_SRC (x))
3129 inner = XEXP (SET_SRC (x), 0);
3131 /* We can't optimize if either mode is a partial integer
3132 mode as we don't know how many bits are significant
3134 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3135 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3139 len = GET_MODE_BITSIZE (GET_MODE (inner));
3145 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3146 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3148 inner = XEXP (SET_SRC (x), 0);
3149 len = INTVAL (XEXP (SET_SRC (x), 1));
3150 pos = INTVAL (XEXP (SET_SRC (x), 2));
3152 if (BITS_BIG_ENDIAN)
3153 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3154 unsignedp = (code == ZERO_EXTRACT);
3162 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3164 enum machine_mode mode = GET_MODE (SET_SRC (x));
3166 /* For unsigned, we have a choice of a shift followed by an
3167 AND or two shifts. Use two shifts for field sizes where the
3168 constant might be too large. We assume here that we can
3169 always at least get 8-bit constants in an AND insn, which is
3170 true for every current RISC. */
3172 if (unsignedp && len <= 8)
3177 (mode, gen_lowpart_for_combine (mode, inner),
3179 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3181 split = find_split_point (&SET_SRC (x), insn);
3182 if (split && split != &SET_SRC (x))
3189 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3190 gen_rtx_ASHIFT (mode,
3191 gen_lowpart_for_combine (mode, inner),
3192 GEN_INT (GET_MODE_BITSIZE (mode)
3194 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3196 split = find_split_point (&SET_SRC (x), insn);
3197 if (split && split != &SET_SRC (x))
3202 /* See if this is a simple operation with a constant as the second
3203 operand. It might be that this constant is out of range and hence
3204 could be used as a split point. */
3205 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3206 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3207 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3208 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3209 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3210 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3211 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3213 return &XEXP (SET_SRC (x), 1);
3215 /* Finally, see if this is a simple operation with its first operand
3216 not in a register. The operation might require this operand in a
3217 register, so return it as a split point. We can always do this
3218 because if the first operand were another operation, we would have
3219 already found it as a split point. */
3220 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3221 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3222 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3223 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3224 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3225 return &XEXP (SET_SRC (x), 0);
3231 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3232 it is better to write this as (not (ior A B)) so we can split it.
3233 Similarly for IOR. */
3234 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3237 gen_rtx_NOT (GET_MODE (x),
3238 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3240 XEXP (XEXP (x, 0), 0),
3241 XEXP (XEXP (x, 1), 0))));
3242 return find_split_point (loc, insn);
3245 /* Many RISC machines have a large set of logical insns. If the
3246 second operand is a NOT, put it first so we will try to split the
3247 other operand first. */
3248 if (GET_CODE (XEXP (x, 1)) == NOT)
3250 rtx tem = XEXP (x, 0);
3251 SUBST (XEXP (x, 0), XEXP (x, 1));
3252 SUBST (XEXP (x, 1), tem);
3260 /* Otherwise, select our actions depending on our rtx class. */
3261 switch (GET_RTX_CLASS (code))
3263 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3265 split = find_split_point (&XEXP (x, 2), insn);
3268 /* ... fall through ... */
3272 split = find_split_point (&XEXP (x, 1), insn);
3275 /* ... fall through ... */
3277 /* Some machines have (and (shift ...) ...) insns. If X is not
3278 an AND, but XEXP (X, 0) is, use it as our split point. */
3279 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3280 return &XEXP (x, 0);
3282 split = find_split_point (&XEXP (x, 0), insn);
3288 /* Otherwise, we don't have a split point. */
3292 /* Throughout X, replace FROM with TO, and return the result.
3293 The result is TO if X is FROM;
3294 otherwise the result is X, but its contents may have been modified.
3295 If they were modified, a record was made in undobuf so that
3296 undo_all will (among other things) return X to its original state.
3298 If the number of changes necessary is too much to record to undo,
3299 the excess changes are not made, so the result is invalid.
3300 The changes already made can still be undone.
3301 undobuf.num_undo is incremented for such changes, so by testing that
3302 the caller can tell whether the result is valid.
3304 `n_occurrences' is incremented each time FROM is replaced.
3306 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3308 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3309 by copying if `n_occurrences' is nonzero. */
3312 subst (x, from, to, in_dest, unique_copy)
3317 enum rtx_code code = GET_CODE (x);
3318 enum machine_mode op0_mode = VOIDmode;
3323 /* Two expressions are equal if they are identical copies of a shared
3324 RTX or if they are both registers with the same register number
3327 #define COMBINE_RTX_EQUAL_P(X,Y) \
3329 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3330 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3332 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3335 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3338 /* If X and FROM are the same register but different modes, they will
3339 not have been seen as equal above. However, flow.c will make a
3340 LOG_LINKS entry for that case. If we do nothing, we will try to
3341 rerecognize our original insn and, when it succeeds, we will
3342 delete the feeding insn, which is incorrect.
3344 So force this insn not to match in this (rare) case. */
3345 if (! in_dest && code == REG && GET_CODE (from) == REG
3346 && REGNO (x) == REGNO (from))
3347 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3349 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3350 of which may contain things that can be combined. */
3351 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3354 /* It is possible to have a subexpression appear twice in the insn.
3355 Suppose that FROM is a register that appears within TO.
3356 Then, after that subexpression has been scanned once by `subst',
3357 the second time it is scanned, TO may be found. If we were
3358 to scan TO here, we would find FROM within it and create a
3359 self-referent rtl structure which is completely wrong. */
3360 if (COMBINE_RTX_EQUAL_P (x, to))
3363 /* Parallel asm_operands need special attention because all of the
3364 inputs are shared across the arms. Furthermore, unsharing the
3365 rtl results in recognition failures. Failure to handle this case
3366 specially can result in circular rtl.
3368 Solve this by doing a normal pass across the first entry of the
3369 parallel, and only processing the SET_DESTs of the subsequent
3372 if (code == PARALLEL
3373 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3374 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3376 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3378 /* If this substitution failed, this whole thing fails. */
3379 if (GET_CODE (new) == CLOBBER
3380 && XEXP (new, 0) == const0_rtx)
3383 SUBST (XVECEXP (x, 0, 0), new);
3385 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3387 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3389 if (GET_CODE (dest) != REG
3390 && GET_CODE (dest) != CC0
3391 && GET_CODE (dest) != PC)
3393 new = subst (dest, from, to, 0, unique_copy);
3395 /* If this substitution failed, this whole thing fails. */
3396 if (GET_CODE (new) == CLOBBER
3397 && XEXP (new, 0) == const0_rtx)
3400 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3406 len = GET_RTX_LENGTH (code);
3407 fmt = GET_RTX_FORMAT (code);
3409 /* We don't need to process a SET_DEST that is a register, CC0,
3410 or PC, so set up to skip this common case. All other cases
3411 where we want to suppress replacing something inside a
3412 SET_SRC are handled via the IN_DEST operand. */
3414 && (GET_CODE (SET_DEST (x)) == REG
3415 || GET_CODE (SET_DEST (x)) == CC0
3416 || GET_CODE (SET_DEST (x)) == PC))
3419 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3422 op0_mode = GET_MODE (XEXP (x, 0));
3424 for (i = 0; i < len; i++)
3429 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3431 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3433 new = (unique_copy && n_occurrences
3434 ? copy_rtx (to) : to);
3439 new = subst (XVECEXP (x, i, j), from, to, 0,
3442 /* If this substitution failed, this whole thing
3444 if (GET_CODE (new) == CLOBBER
3445 && XEXP (new, 0) == const0_rtx)
3449 SUBST (XVECEXP (x, i, j), new);
3452 else if (fmt[i] == 'e')
3454 /* If this is a register being set, ignore it. */
3457 && (code == SUBREG || code == STRICT_LOW_PART
3458 || code == ZERO_EXTRACT)
3460 && GET_CODE (new) == REG)
3463 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3465 /* In general, don't install a subreg involving two
3466 modes not tieable. It can worsen register
3467 allocation, and can even make invalid reload
3468 insns, since the reg inside may need to be copied
3469 from in the outside mode, and that may be invalid
3470 if it is an fp reg copied in integer mode.
3472 We allow two exceptions to this: It is valid if
3473 it is inside another SUBREG and the mode of that
3474 SUBREG and the mode of the inside of TO is
3475 tieable and it is valid if X is a SET that copies
3478 if (GET_CODE (to) == SUBREG
3479 && ! MODES_TIEABLE_P (GET_MODE (to),
3480 GET_MODE (SUBREG_REG (to)))
3481 && ! (code == SUBREG
3482 && MODES_TIEABLE_P (GET_MODE (x),
3483 GET_MODE (SUBREG_REG (to))))
3485 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3488 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3490 #ifdef CANNOT_CHANGE_MODE_CLASS
3492 && GET_CODE (to) == REG
3493 && REGNO (to) < FIRST_PSEUDO_REGISTER
3494 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3497 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3500 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3504 /* If we are in a SET_DEST, suppress most cases unless we
3505 have gone inside a MEM, in which case we want to
3506 simplify the address. We assume here that things that
3507 are actually part of the destination have their inner
3508 parts in the first expression. This is true for SUBREG,
3509 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3510 things aside from REG and MEM that should appear in a
3512 new = subst (XEXP (x, i), from, to,
3514 && (code == SUBREG || code == STRICT_LOW_PART
3515 || code == ZERO_EXTRACT))
3517 && i == 0), unique_copy);
3519 /* If we found that we will have to reject this combination,
3520 indicate that by returning the CLOBBER ourselves, rather than
3521 an expression containing it. This will speed things up as
3522 well as prevent accidents where two CLOBBERs are considered
3523 to be equal, thus producing an incorrect simplification. */
3525 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3528 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3530 enum machine_mode mode = GET_MODE (x);
3532 x = simplify_subreg (GET_MODE (x), new,
3533 GET_MODE (SUBREG_REG (x)),
3536 x = gen_rtx_CLOBBER (mode, const0_rtx);
3538 else if (GET_CODE (new) == CONST_INT
3539 && GET_CODE (x) == ZERO_EXTEND)
3541 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3542 new, GET_MODE (XEXP (x, 0)));
3547 SUBST (XEXP (x, i), new);
3552 /* Try to simplify X. If the simplification changed the code, it is likely
3553 that further simplification will help, so loop, but limit the number
3554 of repetitions that will be performed. */
3556 for (i = 0; i < 4; i++)
3558 /* If X is sufficiently simple, don't bother trying to do anything
3560 if (code != CONST_INT && code != REG && code != CLOBBER)
3561 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3563 if (GET_CODE (x) == code)
3566 code = GET_CODE (x);
3568 /* We no longer know the original mode of operand 0 since we
3569 have changed the form of X) */
3570 op0_mode = VOIDmode;
3576 /* Simplify X, a piece of RTL. We just operate on the expression at the
3577 outer level; call `subst' to simplify recursively. Return the new
3580 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3581 will be the iteration even if an expression with a code different from
3582 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3585 combine_simplify_rtx (x, op0_mode, last, in_dest)
3587 enum machine_mode op0_mode;
3591 enum rtx_code code = GET_CODE (x);
3592 enum machine_mode mode = GET_MODE (x);
3597 /* If this is a commutative operation, put a constant last and a complex
3598 expression first. We don't need to do this for comparisons here. */
3599 if (GET_RTX_CLASS (code) == 'c'
3600 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3603 SUBST (XEXP (x, 0), XEXP (x, 1));
3604 SUBST (XEXP (x, 1), temp);
3607 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3608 sign extension of a PLUS with a constant, reverse the order of the sign
3609 extension and the addition. Note that this not the same as the original
3610 code, but overflow is undefined for signed values. Also note that the
3611 PLUS will have been partially moved "inside" the sign-extension, so that
3612 the first operand of X will really look like:
3613 (ashiftrt (plus (ashift A C4) C5) C4).
3615 (plus (ashiftrt (ashift A C4) C2) C4)
3616 and replace the first operand of X with that expression. Later parts
3617 of this function may simplify the expression further.
3619 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3620 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3621 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3623 We do this to simplify address expressions. */
3625 if ((code == PLUS || code == MINUS || code == MULT)
3626 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3627 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3628 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3629 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3630 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3631 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3632 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3633 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3634 XEXP (XEXP (XEXP (x, 0), 0), 1),
3635 XEXP (XEXP (x, 0), 1))) != 0)
3638 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3639 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3640 INTVAL (XEXP (XEXP (x, 0), 1)));
3642 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3643 INTVAL (XEXP (XEXP (x, 0), 1)));
3645 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3648 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3649 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3650 things. Check for cases where both arms are testing the same
3653 Don't do anything if all operands are very simple. */
3655 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3656 || GET_RTX_CLASS (code) == '<')
3657 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3658 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3659 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3661 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3662 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3663 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3665 || (GET_RTX_CLASS (code) == '1'
3666 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3667 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3668 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3671 rtx cond, true_rtx, false_rtx;
3673 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3675 /* If everything is a comparison, what we have is highly unlikely
3676 to be simpler, so don't use it. */
3677 && ! (GET_RTX_CLASS (code) == '<'
3678 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3679 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3681 rtx cop1 = const0_rtx;
3682 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3684 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3687 /* Simplify the alternative arms; this may collapse the true and
3688 false arms to store-flag values. */
3689 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3690 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3692 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3693 is unlikely to be simpler. */
3694 if (general_operand (true_rtx, VOIDmode)
3695 && general_operand (false_rtx, VOIDmode))
3697 enum rtx_code reversed;
3699 /* Restarting if we generate a store-flag expression will cause
3700 us to loop. Just drop through in this case. */
3702 /* If the result values are STORE_FLAG_VALUE and zero, we can
3703 just make the comparison operation. */
3704 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3705 x = gen_binary (cond_code, mode, cond, cop1);
3706 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3707 && ((reversed = reversed_comparison_code_parts
3708 (cond_code, cond, cop1, NULL))
3710 x = gen_binary (reversed, mode, cond, cop1);
3712 /* Likewise, we can make the negate of a comparison operation
3713 if the result values are - STORE_FLAG_VALUE and zero. */
3714 else if (GET_CODE (true_rtx) == CONST_INT
3715 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3716 && false_rtx == const0_rtx)
3717 x = simplify_gen_unary (NEG, mode,
3718 gen_binary (cond_code, mode, cond,
3721 else if (GET_CODE (false_rtx) == CONST_INT
3722 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3723 && true_rtx == const0_rtx
3724 && ((reversed = reversed_comparison_code_parts
3725 (cond_code, cond, cop1, NULL))
3727 x = simplify_gen_unary (NEG, mode,
3728 gen_binary (reversed, mode,
3732 return gen_rtx_IF_THEN_ELSE (mode,
3733 gen_binary (cond_code, VOIDmode,
3735 true_rtx, false_rtx);
3737 code = GET_CODE (x);
3738 op0_mode = VOIDmode;
3743 /* Try to fold this expression in case we have constants that weren't
3746 switch (GET_RTX_CLASS (code))
3749 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3753 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3754 if (cmp_mode == VOIDmode)
3756 cmp_mode = GET_MODE (XEXP (x, 1));
3757 if (cmp_mode == VOIDmode)
3758 cmp_mode = op0_mode;
3760 temp = simplify_relational_operation (code, cmp_mode,
3761 XEXP (x, 0), XEXP (x, 1));
3763 #ifdef FLOAT_STORE_FLAG_VALUE
3764 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3766 if (temp == const0_rtx)
3767 temp = CONST0_RTX (mode);
3769 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3776 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3780 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3781 XEXP (x, 1), XEXP (x, 2));
3788 code = GET_CODE (temp);
3789 op0_mode = VOIDmode;
3790 mode = GET_MODE (temp);
3793 /* First see if we can apply the inverse distributive law. */
3794 if (code == PLUS || code == MINUS
3795 || code == AND || code == IOR || code == XOR)
3797 x = apply_distributive_law (x);
3798 code = GET_CODE (x);
3799 op0_mode = VOIDmode;
3802 /* If CODE is an associative operation not otherwise handled, see if we
3803 can associate some operands. This can win if they are constants or
3804 if they are logically related (i.e. (a & b) & a). */
3805 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3806 || code == AND || code == IOR || code == XOR
3807 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3808 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3809 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3811 if (GET_CODE (XEXP (x, 0)) == code)
3813 rtx other = XEXP (XEXP (x, 0), 0);
3814 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3815 rtx inner_op1 = XEXP (x, 1);
3818 /* Make sure we pass the constant operand if any as the second
3819 one if this is a commutative operation. */
3820 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3822 rtx tem = inner_op0;
3823 inner_op0 = inner_op1;
3826 inner = simplify_binary_operation (code == MINUS ? PLUS
3827 : code == DIV ? MULT
3829 mode, inner_op0, inner_op1);
3831 /* For commutative operations, try the other pair if that one
3833 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3835 other = XEXP (XEXP (x, 0), 1);
3836 inner = simplify_binary_operation (code, mode,
3837 XEXP (XEXP (x, 0), 0),
3842 return gen_binary (code, mode, other, inner);
3846 /* A little bit of algebraic simplification here. */
3850 /* Ensure that our address has any ASHIFTs converted to MULT in case
3851 address-recognizing predicates are called later. */
3852 temp = make_compound_operation (XEXP (x, 0), MEM);
3853 SUBST (XEXP (x, 0), temp);
3857 if (op0_mode == VOIDmode)
3858 op0_mode = GET_MODE (SUBREG_REG (x));
3860 /* simplify_subreg can't use gen_lowpart_for_combine. */
3861 if (CONSTANT_P (SUBREG_REG (x))
3862 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3863 /* Don't call gen_lowpart_for_combine if the inner mode
3864 is VOIDmode and we cannot simplify it, as SUBREG without
3865 inner mode is invalid. */
3866 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3867 || gen_lowpart_common (mode, SUBREG_REG (x))))
3868 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3870 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3874 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3880 /* Don't change the mode of the MEM if that would change the meaning
3882 if (GET_CODE (SUBREG_REG (x)) == MEM
3883 && (MEM_VOLATILE_P (SUBREG_REG (x))
3884 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3885 return gen_rtx_CLOBBER (mode, const0_rtx);
3887 /* Note that we cannot do any narrowing for non-constants since
3888 we might have been counting on using the fact that some bits were
3889 zero. We now do this in the SET. */
3894 /* (not (plus X -1)) can become (neg X). */
3895 if (GET_CODE (XEXP (x, 0)) == PLUS
3896 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3897 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3899 /* Similarly, (not (neg X)) is (plus X -1). */
3900 if (GET_CODE (XEXP (x, 0)) == NEG)
3901 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3903 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3904 if (GET_CODE (XEXP (x, 0)) == XOR
3905 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3906 && (temp = simplify_unary_operation (NOT, mode,
3907 XEXP (XEXP (x, 0), 1),
3909 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3911 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3912 other than 1, but that is not valid. We could do a similar
3913 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3914 but this doesn't seem common enough to bother with. */
3915 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3916 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3917 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3919 XEXP (XEXP (x, 0), 1));
3921 if (GET_CODE (XEXP (x, 0)) == SUBREG
3922 && subreg_lowpart_p (XEXP (x, 0))
3923 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3924 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3925 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3926 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3928 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3930 x = gen_rtx_ROTATE (inner_mode,
3931 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3933 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3934 return gen_lowpart_for_combine (mode, x);
3937 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3938 reversing the comparison code if valid. */
3939 if (STORE_FLAG_VALUE == -1
3940 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3941 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3942 XEXP (XEXP (x, 0), 1))))
3945 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3946 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3947 perform the above simplification. */
3949 if (STORE_FLAG_VALUE == -1
3950 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3951 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3952 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3953 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3955 /* Apply De Morgan's laws to reduce number of patterns for machines
3956 with negating logical insns (and-not, nand, etc.). If result has
3957 only one NOT, put it first, since that is how the patterns are
3960 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3962 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3963 enum machine_mode op_mode;
3965 op_mode = GET_MODE (in1);
3966 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3968 op_mode = GET_MODE (in2);
3969 if (op_mode == VOIDmode)
3971 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3973 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3976 in2 = in1; in1 = tem;
3979 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3985 /* (neg (plus X 1)) can become (not X). */
3986 if (GET_CODE (XEXP (x, 0)) == PLUS
3987 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3988 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3990 /* Similarly, (neg (not X)) is (plus X 1). */
3991 if (GET_CODE (XEXP (x, 0)) == NOT)
3992 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3994 /* (neg (minus X Y)) can become (minus Y X). This transformation
3995 isn't safe for modes with signed zeros, since if X and Y are
3996 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3997 mode is towards +infinity (or -infinity) then the two expressions
3998 will be rounded differently. */
3999 if (GET_CODE (XEXP (x, 0)) == MINUS
4000 && !HONOR_SIGNED_ZEROS (mode)
4001 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4002 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4003 XEXP (XEXP (x, 0), 0));
4005 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
4006 if (GET_CODE (XEXP (x, 0)) == PLUS
4007 && !HONOR_SIGNED_ZEROS (mode)
4008 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4010 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4011 temp = combine_simplify_rtx (temp, mode, last, in_dest);
4012 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
4015 /* (neg (mult A B)) becomes (mult (neg A) B).
4016 This works even for floating-point values. */
4017 if (GET_CODE (XEXP (x, 0)) == MULT)
4019 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4020 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
4023 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4024 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4025 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4026 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4028 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4029 if we can then eliminate the NEG (e.g.,
4030 if the operand is a constant). */
4032 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4034 temp = simplify_unary_operation (NEG, mode,
4035 XEXP (XEXP (x, 0), 0), mode);
4037 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4040 temp = expand_compound_operation (XEXP (x, 0));
4042 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4043 replaced by (lshiftrt X C). This will convert
4044 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4046 if (GET_CODE (temp) == ASHIFTRT
4047 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4048 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4049 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4050 INTVAL (XEXP (temp, 1)));
4052 /* If X has only a single bit that might be nonzero, say, bit I, convert
4053 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4054 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4055 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4056 or a SUBREG of one since we'd be making the expression more
4057 complex if it was just a register. */
4059 if (GET_CODE (temp) != REG
4060 && ! (GET_CODE (temp) == SUBREG
4061 && GET_CODE (SUBREG_REG (temp)) == REG)
4062 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4064 rtx temp1 = simplify_shift_const
4065 (NULL_RTX, ASHIFTRT, mode,
4066 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4067 GET_MODE_BITSIZE (mode) - 1 - i),
4068 GET_MODE_BITSIZE (mode) - 1 - i);
4070 /* If all we did was surround TEMP with the two shifts, we
4071 haven't improved anything, so don't use it. Otherwise,
4072 we are better off with TEMP1. */
4073 if (GET_CODE (temp1) != ASHIFTRT
4074 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4075 || XEXP (XEXP (temp1, 0), 0) != temp)
4081 /* We can't handle truncation to a partial integer mode here
4082 because we don't know the real bitsize of the partial
4084 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4087 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4088 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4089 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4091 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4092 GET_MODE_MASK (mode), NULL_RTX, 0));
4094 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4095 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4096 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4097 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4098 return XEXP (XEXP (x, 0), 0);
4100 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4101 (OP:SI foo:SI) if OP is NEG or ABS. */
4102 if ((GET_CODE (XEXP (x, 0)) == ABS
4103 || GET_CODE (XEXP (x, 0)) == NEG)
4104 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4105 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4106 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4107 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4108 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4110 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4112 if (GET_CODE (XEXP (x, 0)) == SUBREG
4113 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4114 && subreg_lowpart_p (XEXP (x, 0)))
4115 return SUBREG_REG (XEXP (x, 0));
4117 /* If we know that the value is already truncated, we can
4118 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4119 is nonzero for the corresponding modes. But don't do this
4120 for an (LSHIFTRT (MULT ...)) since this will cause problems
4121 with the umulXi3_highpart patterns. */
4122 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4123 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4124 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4125 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4126 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4127 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4128 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4130 /* A truncate of a comparison can be replaced with a subreg if
4131 STORE_FLAG_VALUE permits. This is like the previous test,
4132 but it works even if the comparison is done in a mode larger
4133 than HOST_BITS_PER_WIDE_INT. */
4134 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4135 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4136 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4137 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4139 /* Similarly, a truncate of a register whose value is a
4140 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4142 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4143 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4144 && (temp = get_last_value (XEXP (x, 0)))
4145 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4146 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4150 case FLOAT_TRUNCATE:
4151 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4152 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4153 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4154 return XEXP (XEXP (x, 0), 0);
4156 /* (float_truncate:SF (float_truncate:DF foo:XF))
4157 = (float_truncate:SF foo:XF).
4158 This may elliminate double rounding, so it is unsafe.
4160 (float_truncate:SF (float_extend:XF foo:DF))
4161 = (float_truncate:SF foo:DF).
4163 (float_truncate:DF (float_extend:XF foo:SF))
4164 = (float_extend:SF foo:DF). */
4165 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4166 && flag_unsafe_math_optimizations)
4167 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4168 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4170 > GET_MODE_SIZE (mode)
4171 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4173 XEXP (XEXP (x, 0), 0), mode);
4175 /* (float_truncate (float x)) is (float x) */
4176 if (GET_CODE (XEXP (x, 0)) == FLOAT
4177 && (flag_unsafe_math_optimizations
4178 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4179 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4180 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4181 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4182 return simplify_gen_unary (FLOAT, mode,
4183 XEXP (XEXP (x, 0), 0),
4184 GET_MODE (XEXP (XEXP (x, 0), 0)));
4186 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4187 (OP:SF foo:SF) if OP is NEG or ABS. */
4188 if ((GET_CODE (XEXP (x, 0)) == ABS
4189 || GET_CODE (XEXP (x, 0)) == NEG)
4190 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4191 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4192 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4193 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4195 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4196 is (float_truncate:SF x). */
4197 if (GET_CODE (XEXP (x, 0)) == SUBREG
4198 && subreg_lowpart_p (XEXP (x, 0))
4199 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4200 return SUBREG_REG (XEXP (x, 0));
4203 /* (float_extend (float_extend x)) is (float_extend x)
4205 (float_extend (float x)) is (float x) assuming that double
4206 rounding can't happen.
4208 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4209 || (GET_CODE (XEXP (x, 0)) == FLOAT
4210 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4211 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4212 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4213 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4214 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4215 XEXP (XEXP (x, 0), 0),
4216 GET_MODE (XEXP (XEXP (x, 0), 0)));
4221 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4222 using cc0, in which case we want to leave it as a COMPARE
4223 so we can distinguish it from a register-register-copy. */
4224 if (XEXP (x, 1) == const0_rtx)
4227 /* x - 0 is the same as x unless x's mode has signed zeros and
4228 allows rounding towards -infinity. Under those conditions,
4230 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4231 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4232 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4238 /* (const (const X)) can become (const X). Do it this way rather than
4239 returning the inner CONST since CONST can be shared with a
4241 if (GET_CODE (XEXP (x, 0)) == CONST)
4242 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4247 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4248 can add in an offset. find_split_point will split this address up
4249 again if it doesn't match. */
4250 if (GET_CODE (XEXP (x, 0)) == HIGH
4251 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4257 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4259 if (GET_CODE (XEXP (x, 0)) == MULT
4260 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4264 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4265 in2 = XEXP (XEXP (x, 0), 1);
4266 return gen_binary (MINUS, mode, XEXP (x, 1),
4267 gen_binary (MULT, mode, in1, in2));
4270 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4271 outermost. That's because that's the way indexed addresses are
4272 supposed to appear. This code used to check many more cases, but
4273 they are now checked elsewhere. */
4274 if (GET_CODE (XEXP (x, 0)) == PLUS
4275 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4276 return gen_binary (PLUS, mode,
4277 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4279 XEXP (XEXP (x, 0), 1));
4281 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4282 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4283 bit-field and can be replaced by either a sign_extend or a
4284 sign_extract. The `and' may be a zero_extend and the two
4285 <c>, -<c> constants may be reversed. */
4286 if (GET_CODE (XEXP (x, 0)) == XOR
4287 && GET_CODE (XEXP (x, 1)) == CONST_INT
4288 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4289 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4290 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4291 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4292 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4293 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4294 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4295 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4296 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4297 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4298 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4299 == (unsigned int) i + 1))))
4300 return simplify_shift_const
4301 (NULL_RTX, ASHIFTRT, mode,
4302 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4303 XEXP (XEXP (XEXP (x, 0), 0), 0),
4304 GET_MODE_BITSIZE (mode) - (i + 1)),
4305 GET_MODE_BITSIZE (mode) - (i + 1));
4307 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4308 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4309 is 1. This produces better code than the alternative immediately
4311 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4312 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4313 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4314 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4315 XEXP (XEXP (x, 0), 0),
4316 XEXP (XEXP (x, 0), 1))))
4318 simplify_gen_unary (NEG, mode, reversed, mode);
4320 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4321 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4322 the bitsize of the mode - 1. This allows simplification of
4323 "a = (b & 8) == 0;" */
4324 if (XEXP (x, 1) == constm1_rtx
4325 && GET_CODE (XEXP (x, 0)) != REG
4326 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4327 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4328 && nonzero_bits (XEXP (x, 0), mode) == 1)
4329 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4330 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4331 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4332 GET_MODE_BITSIZE (mode) - 1),
4333 GET_MODE_BITSIZE (mode) - 1);
4335 /* If we are adding two things that have no bits in common, convert
4336 the addition into an IOR. This will often be further simplified,
4337 for example in cases like ((a & 1) + (a & 2)), which can
4340 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4341 && (nonzero_bits (XEXP (x, 0), mode)
4342 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4344 /* Try to simplify the expression further. */
4345 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4346 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4348 /* If we could, great. If not, do not go ahead with the IOR
4349 replacement, since PLUS appears in many special purpose
4350 address arithmetic instructions. */
4351 if (GET_CODE (temp) != CLOBBER && temp != tor)
4357 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4358 by reversing the comparison code if valid. */
4359 if (STORE_FLAG_VALUE == 1
4360 && XEXP (x, 0) == const1_rtx
4361 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4362 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4363 XEXP (XEXP (x, 1), 0),
4364 XEXP (XEXP (x, 1), 1))))
4367 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4368 (and <foo> (const_int pow2-1)) */
4369 if (GET_CODE (XEXP (x, 1)) == AND
4370 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4371 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4372 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4373 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4374 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4376 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4378 if (GET_CODE (XEXP (x, 1)) == MULT
4379 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4383 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4384 in2 = XEXP (XEXP (x, 1), 1);
4385 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4389 /* Canonicalize (minus (neg A) (mult B C)) to
4390 (minus (mult (neg B) C) A). */
4391 if (GET_CODE (XEXP (x, 1)) == MULT
4392 && GET_CODE (XEXP (x, 0)) == NEG)
4396 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4397 in2 = XEXP (XEXP (x, 1), 1);
4398 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4399 XEXP (XEXP (x, 0), 0));
4402 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4404 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4405 return gen_binary (MINUS, mode,
4406 gen_binary (MINUS, mode, XEXP (x, 0),
4407 XEXP (XEXP (x, 1), 0)),
4408 XEXP (XEXP (x, 1), 1));
4412 /* If we have (mult (plus A B) C), apply the distributive law and then
4413 the inverse distributive law to see if things simplify. This
4414 occurs mostly in addresses, often when unrolling loops. */
4416 if (GET_CODE (XEXP (x, 0)) == PLUS)
4418 x = apply_distributive_law
4419 (gen_binary (PLUS, mode,
4420 gen_binary (MULT, mode,
4421 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4422 gen_binary (MULT, mode,
4423 XEXP (XEXP (x, 0), 1),
4424 copy_rtx (XEXP (x, 1)))));
4426 if (GET_CODE (x) != MULT)
4429 /* Try simplify a*(b/c) as (a*b)/c. */
4430 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4431 && GET_CODE (XEXP (x, 0)) == DIV)
4433 rtx tem = simplify_binary_operation (MULT, mode,
4434 XEXP (XEXP (x, 0), 0),
4437 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4442 /* If this is a divide by a power of two, treat it as a shift if
4443 its first operand is a shift. */
4444 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4445 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4446 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4447 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4448 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4449 || GET_CODE (XEXP (x, 0)) == ROTATE
4450 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4451 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4455 case GT: case GTU: case GE: case GEU:
4456 case LT: case LTU: case LE: case LEU:
4457 case UNEQ: case LTGT:
4458 case UNGT: case UNGE:
4459 case UNLT: case UNLE:
4460 case UNORDERED: case ORDERED:
4461 /* If the first operand is a condition code, we can't do anything
4463 if (GET_CODE (XEXP (x, 0)) == COMPARE
4464 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4465 && ! CC0_P (XEXP (x, 0))))
4467 rtx op0 = XEXP (x, 0);
4468 rtx op1 = XEXP (x, 1);
4469 enum rtx_code new_code;
4471 if (GET_CODE (op0) == COMPARE)
4472 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4474 /* Simplify our comparison, if possible. */
4475 new_code = simplify_comparison (code, &op0, &op1);
4477 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4478 if only the low-order bit is possibly nonzero in X (such as when
4479 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4480 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4481 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4484 Remove any ZERO_EXTRACT we made when thinking this was a
4485 comparison. It may now be simpler to use, e.g., an AND. If a
4486 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4487 the call to make_compound_operation in the SET case. */
4489 if (STORE_FLAG_VALUE == 1
4490 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4491 && op1 == const0_rtx
4492 && mode == GET_MODE (op0)
4493 && nonzero_bits (op0, mode) == 1)
4494 return gen_lowpart_for_combine (mode,
4495 expand_compound_operation (op0));
4497 else if (STORE_FLAG_VALUE == 1
4498 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4499 && op1 == const0_rtx
4500 && mode == GET_MODE (op0)
4501 && (num_sign_bit_copies (op0, mode)
4502 == GET_MODE_BITSIZE (mode)))
4504 op0 = expand_compound_operation (op0);
4505 return simplify_gen_unary (NEG, mode,
4506 gen_lowpart_for_combine (mode, op0),
4510 else if (STORE_FLAG_VALUE == 1
4511 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4512 && op1 == const0_rtx
4513 && mode == GET_MODE (op0)
4514 && nonzero_bits (op0, mode) == 1)
4516 op0 = expand_compound_operation (op0);
4517 return gen_binary (XOR, mode,
4518 gen_lowpart_for_combine (mode, op0),
4522 else if (STORE_FLAG_VALUE == 1
4523 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4524 && op1 == const0_rtx
4525 && mode == GET_MODE (op0)
4526 && (num_sign_bit_copies (op0, mode)
4527 == GET_MODE_BITSIZE (mode)))
4529 op0 = expand_compound_operation (op0);
4530 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4533 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4535 if (STORE_FLAG_VALUE == -1
4536 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4537 && op1 == const0_rtx
4538 && (num_sign_bit_copies (op0, mode)
4539 == GET_MODE_BITSIZE (mode)))
4540 return gen_lowpart_for_combine (mode,
4541 expand_compound_operation (op0));
4543 else if (STORE_FLAG_VALUE == -1
4544 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4545 && op1 == const0_rtx
4546 && mode == GET_MODE (op0)
4547 && nonzero_bits (op0, mode) == 1)
4549 op0 = expand_compound_operation (op0);
4550 return simplify_gen_unary (NEG, mode,
4551 gen_lowpart_for_combine (mode, op0),
4555 else if (STORE_FLAG_VALUE == -1
4556 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4557 && op1 == const0_rtx
4558 && mode == GET_MODE (op0)
4559 && (num_sign_bit_copies (op0, mode)
4560 == GET_MODE_BITSIZE (mode)))
4562 op0 = expand_compound_operation (op0);
4563 return simplify_gen_unary (NOT, mode,
4564 gen_lowpart_for_combine (mode, op0),
4568 /* If X is 0/1, (eq X 0) is X-1. */
4569 else if (STORE_FLAG_VALUE == -1
4570 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4571 && op1 == const0_rtx
4572 && mode == GET_MODE (op0)
4573 && nonzero_bits (op0, mode) == 1)
4575 op0 = expand_compound_operation (op0);
4576 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4579 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4580 one bit that might be nonzero, we can convert (ne x 0) to
4581 (ashift x c) where C puts the bit in the sign bit. Remove any
4582 AND with STORE_FLAG_VALUE when we are done, since we are only
4583 going to test the sign bit. */
4584 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4585 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4586 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4587 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4588 && op1 == const0_rtx
4589 && mode == GET_MODE (op0)
4590 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4592 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4593 expand_compound_operation (op0),
4594 GET_MODE_BITSIZE (mode) - 1 - i);
4595 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4601 /* If the code changed, return a whole new comparison. */
4602 if (new_code != code)
4603 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4605 /* Otherwise, keep this operation, but maybe change its operands.
4606 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4607 SUBST (XEXP (x, 0), op0);
4608 SUBST (XEXP (x, 1), op1);
4613 return simplify_if_then_else (x);
4619 /* If we are processing SET_DEST, we are done. */
4623 return expand_compound_operation (x);
4626 return simplify_set (x);
4631 return simplify_logical (x, last);
4634 /* (abs (neg <foo>)) -> (abs <foo>) */
4635 if (GET_CODE (XEXP (x, 0)) == NEG)
4636 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4638 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4640 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4643 /* If operand is something known to be positive, ignore the ABS. */
4644 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4645 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4646 <= HOST_BITS_PER_WIDE_INT)
4647 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4648 & ((HOST_WIDE_INT) 1
4649 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4653 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4654 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4655 return gen_rtx_NEG (mode, XEXP (x, 0));
4660 /* (ffs (*_extend <X>)) = (ffs <X>) */
4661 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4662 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4663 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4668 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4669 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4670 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4674 /* (float (sign_extend <X>)) = (float <X>). */
4675 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4676 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4684 /* If this is a shift by a constant amount, simplify it. */
4685 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4686 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4687 INTVAL (XEXP (x, 1)));
4689 #ifdef SHIFT_COUNT_TRUNCATED
4690 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4692 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4694 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4703 rtx op0 = XEXP (x, 0);
4704 rtx op1 = XEXP (x, 1);
4707 if (GET_CODE (op1) != PARALLEL)
4709 len = XVECLEN (op1, 0);
4711 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4712 && GET_CODE (op0) == VEC_CONCAT)
4714 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4716 /* Try to find the element in the VEC_CONCAT. */
4719 if (GET_MODE (op0) == GET_MODE (x))
4721 if (GET_CODE (op0) == VEC_CONCAT)
4723 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4724 if (op0_size < offset)
4725 op0 = XEXP (op0, 0);
4729 op0 = XEXP (op0, 1);
4747 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4750 simplify_if_then_else (x)
4753 enum machine_mode mode = GET_MODE (x);
4754 rtx cond = XEXP (x, 0);
4755 rtx true_rtx = XEXP (x, 1);
4756 rtx false_rtx = XEXP (x, 2);
4757 enum rtx_code true_code = GET_CODE (cond);
4758 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4761 enum rtx_code false_code;
4764 /* Simplify storing of the truth value. */
4765 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4766 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4768 /* Also when the truth value has to be reversed. */
4770 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4771 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4775 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4776 in it is being compared against certain values. Get the true and false
4777 comparisons and see if that says anything about the value of each arm. */
4780 && ((false_code = combine_reversed_comparison_code (cond))
4782 && GET_CODE (XEXP (cond, 0)) == REG)
4785 rtx from = XEXP (cond, 0);
4786 rtx true_val = XEXP (cond, 1);
4787 rtx false_val = true_val;
4790 /* If FALSE_CODE is EQ, swap the codes and arms. */
4792 if (false_code == EQ)
4794 swapped = 1, true_code = EQ, false_code = NE;
4795 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4798 /* If we are comparing against zero and the expression being tested has
4799 only a single bit that might be nonzero, that is its value when it is
4800 not equal to zero. Similarly if it is known to be -1 or 0. */
4802 if (true_code == EQ && true_val == const0_rtx
4803 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4804 false_code = EQ, false_val = GEN_INT (nzb);
4805 else if (true_code == EQ && true_val == const0_rtx
4806 && (num_sign_bit_copies (from, GET_MODE (from))
4807 == GET_MODE_BITSIZE (GET_MODE (from))))
4808 false_code = EQ, false_val = constm1_rtx;
4810 /* Now simplify an arm if we know the value of the register in the
4811 branch and it is used in the arm. Be careful due to the potential
4812 of locally-shared RTL. */
4814 if (reg_mentioned_p (from, true_rtx))
4815 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4817 pc_rtx, pc_rtx, 0, 0);
4818 if (reg_mentioned_p (from, false_rtx))
4819 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4821 pc_rtx, pc_rtx, 0, 0);
4823 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4824 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4826 true_rtx = XEXP (x, 1);
4827 false_rtx = XEXP (x, 2);
4828 true_code = GET_CODE (cond);
4831 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4832 reversed, do so to avoid needing two sets of patterns for
4833 subtract-and-branch insns. Similarly if we have a constant in the true
4834 arm, the false arm is the same as the first operand of the comparison, or
4835 the false arm is more complicated than the true arm. */
4838 && combine_reversed_comparison_code (cond) != UNKNOWN
4839 && (true_rtx == pc_rtx
4840 || (CONSTANT_P (true_rtx)
4841 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4842 || true_rtx == const0_rtx
4843 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4844 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4845 || (GET_CODE (true_rtx) == SUBREG
4846 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4847 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4848 || reg_mentioned_p (true_rtx, false_rtx)
4849 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4851 true_code = reversed_comparison_code (cond, NULL);
4853 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4856 SUBST (XEXP (x, 1), false_rtx);
4857 SUBST (XEXP (x, 2), true_rtx);
4859 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4862 /* It is possible that the conditional has been simplified out. */
4863 true_code = GET_CODE (cond);
4864 comparison_p = GET_RTX_CLASS (true_code) == '<';
4867 /* If the two arms are identical, we don't need the comparison. */
4869 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4872 /* Convert a == b ? b : a to "a". */
4873 if (true_code == EQ && ! side_effects_p (cond)
4874 && !HONOR_NANS (mode)
4875 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4876 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4878 else if (true_code == NE && ! side_effects_p (cond)
4879 && !HONOR_NANS (mode)
4880 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4881 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4884 /* Look for cases where we have (abs x) or (neg (abs X)). */
4886 if (GET_MODE_CLASS (mode) == MODE_INT
4887 && GET_CODE (false_rtx) == NEG
4888 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4890 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4891 && ! side_effects_p (true_rtx))
4896 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4900 simplify_gen_unary (NEG, mode,
4901 simplify_gen_unary (ABS, mode, true_rtx, mode),
4907 /* Look for MIN or MAX. */
4909 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4911 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4912 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4913 && ! side_effects_p (cond))
4918 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4921 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4924 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4927 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4932 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4933 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4934 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4935 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4936 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4937 neither 1 or -1, but it isn't worth checking for. */
4939 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4941 && GET_MODE_CLASS (mode) == MODE_INT
4942 && ! side_effects_p (x))
4944 rtx t = make_compound_operation (true_rtx, SET);
4945 rtx f = make_compound_operation (false_rtx, SET);
4946 rtx cond_op0 = XEXP (cond, 0);
4947 rtx cond_op1 = XEXP (cond, 1);
4948 enum rtx_code op = NIL, extend_op = NIL;
4949 enum machine_mode m = mode;
4950 rtx z = 0, c1 = NULL_RTX;
4952 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4953 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4954 || GET_CODE (t) == ASHIFT
4955 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4956 && rtx_equal_p (XEXP (t, 0), f))
4957 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4959 /* If an identity-zero op is commutative, check whether there
4960 would be a match if we swapped the operands. */
4961 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4962 || GET_CODE (t) == XOR)
4963 && rtx_equal_p (XEXP (t, 1), f))
4964 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4965 else if (GET_CODE (t) == SIGN_EXTEND
4966 && (GET_CODE (XEXP (t, 0)) == PLUS
4967 || GET_CODE (XEXP (t, 0)) == MINUS
4968 || GET_CODE (XEXP (t, 0)) == IOR
4969 || GET_CODE (XEXP (t, 0)) == XOR
4970 || GET_CODE (XEXP (t, 0)) == ASHIFT
4971 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4972 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4973 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4974 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4975 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4976 && (num_sign_bit_copies (f, GET_MODE (f))
4978 (GET_MODE_BITSIZE (mode)
4979 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4981 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4982 extend_op = SIGN_EXTEND;
4983 m = GET_MODE (XEXP (t, 0));
4985 else if (GET_CODE (t) == SIGN_EXTEND
4986 && (GET_CODE (XEXP (t, 0)) == PLUS
4987 || GET_CODE (XEXP (t, 0)) == IOR
4988 || GET_CODE (XEXP (t, 0)) == XOR)
4989 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4990 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4991 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4992 && (num_sign_bit_copies (f, GET_MODE (f))
4994 (GET_MODE_BITSIZE (mode)
4995 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4997 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4998 extend_op = SIGN_EXTEND;
4999 m = GET_MODE (XEXP (t, 0));
5001 else if (GET_CODE (t) == ZERO_EXTEND
5002 && (GET_CODE (XEXP (t, 0)) == PLUS
5003 || GET_CODE (XEXP (t, 0)) == MINUS
5004 || GET_CODE (XEXP (t, 0)) == IOR
5005 || GET_CODE (XEXP (t, 0)) == XOR
5006 || GET_CODE (XEXP (t, 0)) == ASHIFT
5007 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5008 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5009 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5010 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5011 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5012 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5013 && ((nonzero_bits (f, GET_MODE (f))
5014 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5017 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5018 extend_op = ZERO_EXTEND;
5019 m = GET_MODE (XEXP (t, 0));
5021 else if (GET_CODE (t) == ZERO_EXTEND
5022 && (GET_CODE (XEXP (t, 0)) == PLUS
5023 || GET_CODE (XEXP (t, 0)) == IOR
5024 || GET_CODE (XEXP (t, 0)) == XOR)
5025 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5026 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5027 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5028 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5029 && ((nonzero_bits (f, GET_MODE (f))
5030 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5033 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5034 extend_op = ZERO_EXTEND;
5035 m = GET_MODE (XEXP (t, 0));
5040 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5041 pc_rtx, pc_rtx, 0, 0);
5042 temp = gen_binary (MULT, m, temp,
5043 gen_binary (MULT, m, c1, const_true_rtx));
5044 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5045 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
5047 if (extend_op != NIL)
5048 temp = simplify_gen_unary (extend_op, mode, temp, m);
5054 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5055 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5056 negation of a single bit, we can convert this operation to a shift. We
5057 can actually do this more generally, but it doesn't seem worth it. */
5059 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5060 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5061 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5062 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5063 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5064 == GET_MODE_BITSIZE (mode))
5065 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5067 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5068 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5073 /* Simplify X, a SET expression. Return the new expression. */
5079 rtx src = SET_SRC (x);
5080 rtx dest = SET_DEST (x);
5081 enum machine_mode mode
5082 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5086 /* (set (pc) (return)) gets written as (return). */
5087 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5090 /* Now that we know for sure which bits of SRC we are using, see if we can
5091 simplify the expression for the object knowing that we only need the
5094 if (GET_MODE_CLASS (mode) == MODE_INT
5095 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5097 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5098 SUBST (SET_SRC (x), src);
5101 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5102 the comparison result and try to simplify it unless we already have used
5103 undobuf.other_insn. */
5104 if ((GET_MODE_CLASS (mode) == MODE_CC
5105 || GET_CODE (src) == COMPARE
5107 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5108 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5109 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5110 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5112 enum rtx_code old_code = GET_CODE (*cc_use);
5113 enum rtx_code new_code;
5115 int other_changed = 0;
5116 enum machine_mode compare_mode = GET_MODE (dest);
5117 enum machine_mode tmp_mode;
5119 if (GET_CODE (src) == COMPARE)
5120 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5122 op0 = src, op1 = const0_rtx;
5124 /* Check whether the comparison is known at compile time. */
5125 if (GET_MODE (op0) != VOIDmode)
5126 tmp_mode = GET_MODE (op0);
5127 else if (GET_MODE (op1) != VOIDmode)
5128 tmp_mode = GET_MODE (op1);
5130 tmp_mode = compare_mode;
5131 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5132 if (tmp != NULL_RTX)
5134 rtx pat = PATTERN (other_insn);
5135 undobuf.other_insn = other_insn;
5136 SUBST (*cc_use, tmp);
5138 /* Attempt to simplify CC user. */
5139 if (GET_CODE (pat) == SET)
5141 rtx new = simplify_rtx (SET_SRC (pat));
5142 if (new != NULL_RTX)
5143 SUBST (SET_SRC (pat), new);
5146 /* Convert X into a no-op move. */
5147 SUBST (SET_DEST (x), pc_rtx);
5148 SUBST (SET_SRC (x), pc_rtx);
5152 /* Simplify our comparison, if possible. */
5153 new_code = simplify_comparison (old_code, &op0, &op1);
5155 #ifdef EXTRA_CC_MODES
5156 /* If this machine has CC modes other than CCmode, check to see if we
5157 need to use a different CC mode here. */
5158 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5159 #endif /* EXTRA_CC_MODES */
5161 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5162 /* If the mode changed, we have to change SET_DEST, the mode in the
5163 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5164 a hard register, just build new versions with the proper mode. If it
5165 is a pseudo, we lose unless it is only time we set the pseudo, in
5166 which case we can safely change its mode. */
5167 if (compare_mode != GET_MODE (dest))
5169 unsigned int regno = REGNO (dest);
5170 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5172 if (regno < FIRST_PSEUDO_REGISTER
5173 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5175 if (regno >= FIRST_PSEUDO_REGISTER)
5176 SUBST (regno_reg_rtx[regno], new_dest);
5178 SUBST (SET_DEST (x), new_dest);
5179 SUBST (XEXP (*cc_use, 0), new_dest);
5187 /* If the code changed, we have to build a new comparison in
5188 undobuf.other_insn. */
5189 if (new_code != old_code)
5191 unsigned HOST_WIDE_INT mask;
5193 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5196 /* If the only change we made was to change an EQ into an NE or
5197 vice versa, OP0 has only one bit that might be nonzero, and OP1
5198 is zero, check if changing the user of the condition code will
5199 produce a valid insn. If it won't, we can keep the original code
5200 in that insn by surrounding our operation with an XOR. */
5202 if (((old_code == NE && new_code == EQ)
5203 || (old_code == EQ && new_code == NE))
5204 && ! other_changed && op1 == const0_rtx
5205 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5206 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5208 rtx pat = PATTERN (other_insn), note = 0;
5210 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5211 && ! check_asm_operands (pat)))
5213 PUT_CODE (*cc_use, old_code);
5216 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5224 undobuf.other_insn = other_insn;
5227 /* If we are now comparing against zero, change our source if
5228 needed. If we do not use cc0, we always have a COMPARE. */
5229 if (op1 == const0_rtx && dest == cc0_rtx)
5231 SUBST (SET_SRC (x), op0);
5237 /* Otherwise, if we didn't previously have a COMPARE in the
5238 correct mode, we need one. */
5239 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5241 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5246 /* Otherwise, update the COMPARE if needed. */
5247 SUBST (XEXP (src, 0), op0);
5248 SUBST (XEXP (src, 1), op1);
5253 /* Get SET_SRC in a form where we have placed back any
5254 compound expressions. Then do the checks below. */
5255 src = make_compound_operation (src, SET);
5256 SUBST (SET_SRC (x), src);
5259 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5260 and X being a REG or (subreg (reg)), we may be able to convert this to
5261 (set (subreg:m2 x) (op)).
5263 We can always do this if M1 is narrower than M2 because that means that
5264 we only care about the low bits of the result.
5266 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5267 perform a narrower operation than requested since the high-order bits will
5268 be undefined. On machine where it is defined, this transformation is safe
5269 as long as M1 and M2 have the same number of words. */
5271 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5272 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5273 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5275 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5276 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5277 #ifndef WORD_REGISTER_OPERATIONS
5278 && (GET_MODE_SIZE (GET_MODE (src))
5279 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5281 #ifdef CANNOT_CHANGE_MODE_CLASS
5282 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5283 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5284 GET_MODE (SUBREG_REG (src)),
5287 && (GET_CODE (dest) == REG
5288 || (GET_CODE (dest) == SUBREG
5289 && GET_CODE (SUBREG_REG (dest)) == REG)))
5291 SUBST (SET_DEST (x),
5292 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5294 SUBST (SET_SRC (x), SUBREG_REG (src));
5296 src = SET_SRC (x), dest = SET_DEST (x);
5300 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5303 && GET_CODE (src) == SUBREG
5304 && subreg_lowpart_p (src)
5305 && (GET_MODE_BITSIZE (GET_MODE (src))
5306 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5308 rtx inner = SUBREG_REG (src);
5309 enum machine_mode inner_mode = GET_MODE (inner);
5311 /* Here we make sure that we don't have a sign bit on. */
5312 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5313 && (nonzero_bits (inner, inner_mode)
5314 < ((unsigned HOST_WIDE_INT) 1
5315 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5317 SUBST (SET_SRC (x), inner);
5323 #ifdef LOAD_EXTEND_OP
5324 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5325 would require a paradoxical subreg. Replace the subreg with a
5326 zero_extend to avoid the reload that would otherwise be required. */
5328 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5329 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5330 && SUBREG_BYTE (src) == 0
5331 && (GET_MODE_SIZE (GET_MODE (src))
5332 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5333 && GET_CODE (SUBREG_REG (src)) == MEM)
5336 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5337 GET_MODE (src), SUBREG_REG (src)));
5343 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5344 are comparing an item known to be 0 or -1 against 0, use a logical
5345 operation instead. Check for one of the arms being an IOR of the other
5346 arm with some value. We compute three terms to be IOR'ed together. In
5347 practice, at most two will be nonzero. Then we do the IOR's. */
5349 if (GET_CODE (dest) != PC
5350 && GET_CODE (src) == IF_THEN_ELSE
5351 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5352 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5353 && XEXP (XEXP (src, 0), 1) == const0_rtx
5354 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5355 #ifdef HAVE_conditional_move
5356 && ! can_conditionally_move_p (GET_MODE (src))
5358 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5359 GET_MODE (XEXP (XEXP (src, 0), 0)))
5360 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5361 && ! side_effects_p (src))
5363 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5364 ? XEXP (src, 1) : XEXP (src, 2));
5365 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5366 ? XEXP (src, 2) : XEXP (src, 1));
5367 rtx term1 = const0_rtx, term2, term3;
5369 if (GET_CODE (true_rtx) == IOR
5370 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5371 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5372 else if (GET_CODE (true_rtx) == IOR
5373 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5374 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5375 else if (GET_CODE (false_rtx) == IOR
5376 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5377 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5378 else if (GET_CODE (false_rtx) == IOR
5379 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5380 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5382 term2 = gen_binary (AND, GET_MODE (src),
5383 XEXP (XEXP (src, 0), 0), true_rtx);
5384 term3 = gen_binary (AND, GET_MODE (src),
5385 simplify_gen_unary (NOT, GET_MODE (src),
5386 XEXP (XEXP (src, 0), 0),
5391 gen_binary (IOR, GET_MODE (src),
5392 gen_binary (IOR, GET_MODE (src), term1, term2),
5398 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5399 whole thing fail. */
5400 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5402 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5405 /* Convert this into a field assignment operation, if possible. */
5406 return make_field_assignment (x);
5409 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5410 result. LAST is nonzero if this is the last retry. */
5413 simplify_logical (x, last)
5417 enum machine_mode mode = GET_MODE (x);
5418 rtx op0 = XEXP (x, 0);
5419 rtx op1 = XEXP (x, 1);
5422 switch (GET_CODE (x))
5425 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5426 insn (and may simplify more). */
5427 if (GET_CODE (op0) == XOR
5428 && rtx_equal_p (XEXP (op0, 0), op1)
5429 && ! side_effects_p (op1))
5430 x = gen_binary (AND, mode,
5431 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5434 if (GET_CODE (op0) == XOR
5435 && rtx_equal_p (XEXP (op0, 1), op1)
5436 && ! side_effects_p (op1))
5437 x = gen_binary (AND, mode,
5438 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5441 /* Similarly for (~(A ^ B)) & A. */
5442 if (GET_CODE (op0) == NOT
5443 && GET_CODE (XEXP (op0, 0)) == XOR
5444 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5445 && ! side_effects_p (op1))
5446 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5448 if (GET_CODE (op0) == NOT
5449 && GET_CODE (XEXP (op0, 0)) == XOR
5450 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5451 && ! side_effects_p (op1))
5452 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5454 /* We can call simplify_and_const_int only if we don't lose
5455 any (sign) bits when converting INTVAL (op1) to
5456 "unsigned HOST_WIDE_INT". */
5457 if (GET_CODE (op1) == CONST_INT
5458 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5459 || INTVAL (op1) > 0))
5461 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5463 /* If we have (ior (and (X C1) C2)) and the next restart would be
5464 the last, simplify this by making C1 as small as possible
5467 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5468 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5469 && GET_CODE (op1) == CONST_INT)
5470 return gen_binary (IOR, mode,
5471 gen_binary (AND, mode, XEXP (op0, 0),
5472 GEN_INT (INTVAL (XEXP (op0, 1))
5473 & ~INTVAL (op1))), op1);
5475 if (GET_CODE (x) != AND)
5478 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5479 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5480 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5483 /* Convert (A | B) & A to A. */
5484 if (GET_CODE (op0) == IOR
5485 && (rtx_equal_p (XEXP (op0, 0), op1)
5486 || rtx_equal_p (XEXP (op0, 1), op1))
5487 && ! side_effects_p (XEXP (op0, 0))
5488 && ! side_effects_p (XEXP (op0, 1)))
5491 /* In the following group of tests (and those in case IOR below),
5492 we start with some combination of logical operations and apply
5493 the distributive law followed by the inverse distributive law.
5494 Most of the time, this results in no change. However, if some of
5495 the operands are the same or inverses of each other, simplifications
5498 For example, (and (ior A B) (not B)) can occur as the result of
5499 expanding a bit field assignment. When we apply the distributive
5500 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5501 which then simplifies to (and (A (not B))).
5503 If we have (and (ior A B) C), apply the distributive law and then
5504 the inverse distributive law to see if things simplify. */
5506 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5508 x = apply_distributive_law
5509 (gen_binary (GET_CODE (op0), mode,
5510 gen_binary (AND, mode, XEXP (op0, 0), op1),
5511 gen_binary (AND, mode, XEXP (op0, 1),
5513 if (GET_CODE (x) != AND)
5517 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5518 return apply_distributive_law
5519 (gen_binary (GET_CODE (op1), mode,
5520 gen_binary (AND, mode, XEXP (op1, 0), op0),
5521 gen_binary (AND, mode, XEXP (op1, 1),
5524 /* Similarly, taking advantage of the fact that
5525 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5527 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5528 return apply_distributive_law
5529 (gen_binary (XOR, mode,
5530 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5531 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5534 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5535 return apply_distributive_law
5536 (gen_binary (XOR, mode,
5537 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5538 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5542 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5543 if (GET_CODE (op1) == CONST_INT
5544 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5545 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5548 /* Convert (A & B) | A to A. */
5549 if (GET_CODE (op0) == AND
5550 && (rtx_equal_p (XEXP (op0, 0), op1)
5551 || rtx_equal_p (XEXP (op0, 1), op1))
5552 && ! side_effects_p (XEXP (op0, 0))
5553 && ! side_effects_p (XEXP (op0, 1)))
5556 /* If we have (ior (and A B) C), apply the distributive law and then
5557 the inverse distributive law to see if things simplify. */
5559 if (GET_CODE (op0) == AND)
5561 x = apply_distributive_law
5562 (gen_binary (AND, mode,
5563 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5564 gen_binary (IOR, mode, XEXP (op0, 1),
5567 if (GET_CODE (x) != IOR)
5571 if (GET_CODE (op1) == AND)
5573 x = apply_distributive_law
5574 (gen_binary (AND, mode,
5575 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5576 gen_binary (IOR, mode, XEXP (op1, 1),
5579 if (GET_CODE (x) != IOR)
5583 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5584 mode size to (rotate A CX). */
5586 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5587 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5588 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5589 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5590 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5591 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5592 == GET_MODE_BITSIZE (mode)))
5593 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5594 (GET_CODE (op0) == ASHIFT
5595 ? XEXP (op0, 1) : XEXP (op1, 1)));
5597 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5598 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5599 does not affect any of the bits in OP1, it can really be done
5600 as a PLUS and we can associate. We do this by seeing if OP1
5601 can be safely shifted left C bits. */
5602 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5603 && GET_CODE (XEXP (op0, 0)) == PLUS
5604 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5605 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5606 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5608 int count = INTVAL (XEXP (op0, 1));
5609 HOST_WIDE_INT mask = INTVAL (op1) << count;
5611 if (mask >> count == INTVAL (op1)
5612 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5614 SUBST (XEXP (XEXP (op0, 0), 1),
5615 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5622 /* If we are XORing two things that have no bits in common,
5623 convert them into an IOR. This helps to detect rotation encoded
5624 using those methods and possibly other simplifications. */
5626 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5627 && (nonzero_bits (op0, mode)
5628 & nonzero_bits (op1, mode)) == 0)
5629 return (gen_binary (IOR, mode, op0, op1));
5631 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5632 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5635 int num_negated = 0;
5637 if (GET_CODE (op0) == NOT)
5638 num_negated++, op0 = XEXP (op0, 0);
5639 if (GET_CODE (op1) == NOT)
5640 num_negated++, op1 = XEXP (op1, 0);
5642 if (num_negated == 2)
5644 SUBST (XEXP (x, 0), op0);
5645 SUBST (XEXP (x, 1), op1);
5647 else if (num_negated == 1)
5649 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5653 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5654 correspond to a machine insn or result in further simplifications
5655 if B is a constant. */
5657 if (GET_CODE (op0) == AND
5658 && rtx_equal_p (XEXP (op0, 1), op1)
5659 && ! side_effects_p (op1))
5660 return gen_binary (AND, mode,
5661 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5664 else if (GET_CODE (op0) == AND
5665 && rtx_equal_p (XEXP (op0, 0), op1)
5666 && ! side_effects_p (op1))
5667 return gen_binary (AND, mode,
5668 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5671 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5672 comparison if STORE_FLAG_VALUE is 1. */
5673 if (STORE_FLAG_VALUE == 1
5674 && op1 == const1_rtx
5675 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5676 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5680 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5681 is (lt foo (const_int 0)), so we can perform the above
5682 simplification if STORE_FLAG_VALUE is 1. */
5684 if (STORE_FLAG_VALUE == 1
5685 && op1 == const1_rtx
5686 && GET_CODE (op0) == LSHIFTRT
5687 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5688 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5689 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5691 /* (xor (comparison foo bar) (const_int sign-bit))
5692 when STORE_FLAG_VALUE is the sign bit. */
5693 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5694 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5695 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5696 && op1 == const_true_rtx
5697 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5698 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5711 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5712 operations" because they can be replaced with two more basic operations.
5713 ZERO_EXTEND is also considered "compound" because it can be replaced with
5714 an AND operation, which is simpler, though only one operation.
5716 The function expand_compound_operation is called with an rtx expression
5717 and will convert it to the appropriate shifts and AND operations,
5718 simplifying at each stage.
5720 The function make_compound_operation is called to convert an expression
5721 consisting of shifts and ANDs into the equivalent compound expression.
5722 It is the inverse of this function, loosely speaking. */
5725 expand_compound_operation (x)
5728 unsigned HOST_WIDE_INT pos = 0, len;
5730 unsigned int modewidth;
5733 switch (GET_CODE (x))
5738 /* We can't necessarily use a const_int for a multiword mode;
5739 it depends on implicitly extending the value.
5740 Since we don't know the right way to extend it,
5741 we can't tell whether the implicit way is right.
5743 Even for a mode that is no wider than a const_int,
5744 we can't win, because we need to sign extend one of its bits through
5745 the rest of it, and we don't know which bit. */
5746 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5749 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5750 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5751 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5752 reloaded. If not for that, MEM's would very rarely be safe.
5754 Reject MODEs bigger than a word, because we might not be able
5755 to reference a two-register group starting with an arbitrary register
5756 (and currently gen_lowpart might crash for a SUBREG). */
5758 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5761 /* Reject MODEs that aren't scalar integers because turning vector
5762 or complex modes into shifts causes problems. */
5764 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5767 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5768 /* If the inner object has VOIDmode (the only way this can happen
5769 is if it is an ASM_OPERANDS), we can't do anything since we don't
5770 know how much masking to do. */
5779 /* If the operand is a CLOBBER, just return it. */
5780 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5783 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5784 || GET_CODE (XEXP (x, 2)) != CONST_INT
5785 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5788 /* Reject MODEs that aren't scalar integers because turning vector
5789 or complex modes into shifts causes problems. */
5791 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5794 len = INTVAL (XEXP (x, 1));
5795 pos = INTVAL (XEXP (x, 2));
5797 /* If this goes outside the object being extracted, replace the object
5798 with a (use (mem ...)) construct that only combine understands
5799 and is used only for this purpose. */
5800 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5801 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5803 if (BITS_BIG_ENDIAN)
5804 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5811 /* Convert sign extension to zero extension, if we know that the high
5812 bit is not set, as this is easier to optimize. It will be converted
5813 back to cheaper alternative in make_extraction. */
5814 if (GET_CODE (x) == SIGN_EXTEND
5815 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5816 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5817 & ~(((unsigned HOST_WIDE_INT)
5818 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5822 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5823 return expand_compound_operation (temp);
5826 /* We can optimize some special cases of ZERO_EXTEND. */
5827 if (GET_CODE (x) == ZERO_EXTEND)
5829 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5830 know that the last value didn't have any inappropriate bits
5832 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5833 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5834 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5835 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5836 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5837 return XEXP (XEXP (x, 0), 0);
5839 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5840 if (GET_CODE (XEXP (x, 0)) == SUBREG
5841 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5842 && subreg_lowpart_p (XEXP (x, 0))
5843 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5844 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5845 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5846 return SUBREG_REG (XEXP (x, 0));
5848 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5849 is a comparison and STORE_FLAG_VALUE permits. This is like
5850 the first case, but it works even when GET_MODE (x) is larger
5851 than HOST_WIDE_INT. */
5852 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5853 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5854 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5855 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5856 <= HOST_BITS_PER_WIDE_INT)
5857 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5858 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5859 return XEXP (XEXP (x, 0), 0);
5861 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5862 if (GET_CODE (XEXP (x, 0)) == SUBREG
5863 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5864 && subreg_lowpart_p (XEXP (x, 0))
5865 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5866 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5867 <= HOST_BITS_PER_WIDE_INT)
5868 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5869 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5870 return SUBREG_REG (XEXP (x, 0));
5874 /* If we reach here, we want to return a pair of shifts. The inner
5875 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5876 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5877 logical depending on the value of UNSIGNEDP.
5879 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5880 converted into an AND of a shift.
5882 We must check for the case where the left shift would have a negative
5883 count. This can happen in a case like (x >> 31) & 255 on machines
5884 that can't shift by a constant. On those machines, we would first
5885 combine the shift with the AND to produce a variable-position
5886 extraction. Then the constant of 31 would be substituted in to produce
5887 a such a position. */
5889 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5890 if (modewidth + len >= pos)
5891 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5893 simplify_shift_const (NULL_RTX, ASHIFT,
5896 modewidth - pos - len),
5899 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5900 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5901 simplify_shift_const (NULL_RTX, LSHIFTRT,
5904 ((HOST_WIDE_INT) 1 << len) - 1);
5906 /* Any other cases we can't handle. */
5909 /* If we couldn't do this for some reason, return the original
5911 if (GET_CODE (tem) == CLOBBER)
5917 /* X is a SET which contains an assignment of one object into
5918 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5919 or certain SUBREGS). If possible, convert it into a series of
5922 We half-heartedly support variable positions, but do not at all
5923 support variable lengths. */
5926 expand_field_assignment (x)
5930 rtx pos; /* Always counts from low bit. */
5933 enum machine_mode compute_mode;
5935 /* Loop until we find something we can't simplify. */
5938 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5939 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5941 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5942 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5943 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5945 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5946 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5948 inner = XEXP (SET_DEST (x), 0);
5949 len = INTVAL (XEXP (SET_DEST (x), 1));
5950 pos = XEXP (SET_DEST (x), 2);
5952 /* If the position is constant and spans the width of INNER,
5953 surround INNER with a USE to indicate this. */
5954 if (GET_CODE (pos) == CONST_INT
5955 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5956 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5958 if (BITS_BIG_ENDIAN)
5960 if (GET_CODE (pos) == CONST_INT)
5961 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5963 else if (GET_CODE (pos) == MINUS
5964 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5965 && (INTVAL (XEXP (pos, 1))
5966 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5967 /* If position is ADJUST - X, new position is X. */
5968 pos = XEXP (pos, 0);
5970 pos = gen_binary (MINUS, GET_MODE (pos),
5971 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5977 /* A SUBREG between two modes that occupy the same numbers of words
5978 can be done by moving the SUBREG to the source. */
5979 else if (GET_CODE (SET_DEST (x)) == SUBREG
5980 /* We need SUBREGs to compute nonzero_bits properly. */
5981 && nonzero_sign_valid
5982 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5983 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5984 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5985 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5987 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5988 gen_lowpart_for_combine
5989 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5996 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5997 inner = SUBREG_REG (inner);
5999 compute_mode = GET_MODE (inner);
6001 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6002 if (! SCALAR_INT_MODE_P (compute_mode))
6004 enum machine_mode imode;
6006 /* Don't do anything for vector or complex integral types. */
6007 if (! FLOAT_MODE_P (compute_mode))
6010 /* Try to find an integral mode to pun with. */
6011 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6012 if (imode == BLKmode)
6015 compute_mode = imode;
6016 inner = gen_lowpart_for_combine (imode, inner);
6019 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6020 if (len < HOST_BITS_PER_WIDE_INT)
6021 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6025 /* Now compute the equivalent expression. Make a copy of INNER
6026 for the SET_DEST in case it is a MEM into which we will substitute;
6027 we don't want shared RTL in that case. */
6029 (VOIDmode, copy_rtx (inner),
6030 gen_binary (IOR, compute_mode,
6031 gen_binary (AND, compute_mode,
6032 simplify_gen_unary (NOT, compute_mode,
6038 gen_binary (ASHIFT, compute_mode,
6039 gen_binary (AND, compute_mode,
6040 gen_lowpart_for_combine
6041 (compute_mode, SET_SRC (x)),
6049 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6050 it is an RTX that represents a variable starting position; otherwise,
6051 POS is the (constant) starting bit position (counted from the LSB).
6053 INNER may be a USE. This will occur when we started with a bitfield
6054 that went outside the boundary of the object in memory, which is
6055 allowed on most machines. To isolate this case, we produce a USE
6056 whose mode is wide enough and surround the MEM with it. The only
6057 code that understands the USE is this routine. If it is not removed,
6058 it will cause the resulting insn not to match.
6060 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6063 IN_DEST is nonzero if this is a reference in the destination of a
6064 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6065 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6068 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6069 ZERO_EXTRACT should be built even for bits starting at bit 0.
6071 MODE is the desired mode of the result (if IN_DEST == 0).
6073 The result is an RTX for the extraction or NULL_RTX if the target
6077 make_extraction (mode, inner, pos, pos_rtx, len,
6078 unsignedp, in_dest, in_compare)
6079 enum machine_mode mode;
6083 unsigned HOST_WIDE_INT len;
6085 int in_dest, in_compare;
6087 /* This mode describes the size of the storage area
6088 to fetch the overall value from. Within that, we
6089 ignore the POS lowest bits, etc. */
6090 enum machine_mode is_mode = GET_MODE (inner);
6091 enum machine_mode inner_mode;
6092 enum machine_mode wanted_inner_mode = byte_mode;
6093 enum machine_mode wanted_inner_reg_mode = word_mode;
6094 enum machine_mode pos_mode = word_mode;
6095 enum machine_mode extraction_mode = word_mode;
6096 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6099 rtx orig_pos_rtx = pos_rtx;
6100 HOST_WIDE_INT orig_pos;
6102 /* Get some information about INNER and get the innermost object. */
6103 if (GET_CODE (inner) == USE)
6104 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6105 /* We don't need to adjust the position because we set up the USE
6106 to pretend that it was a full-word object. */
6107 spans_byte = 1, inner = XEXP (inner, 0);
6108 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6110 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6111 consider just the QI as the memory to extract from.
6112 The subreg adds or removes high bits; its mode is
6113 irrelevant to the meaning of this extraction,
6114 since POS and LEN count from the lsb. */
6115 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6116 is_mode = GET_MODE (SUBREG_REG (inner));
6117 inner = SUBREG_REG (inner);
6119 else if (GET_CODE (inner) == ASHIFT
6120 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6121 && pos_rtx == 0 && pos == 0
6122 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6124 /* We're extracting the least significant bits of an rtx
6125 (ashift X (const_int C)), where LEN > C. Extract the
6126 least significant (LEN - C) bits of X, giving an rtx
6127 whose mode is MODE, then shift it left C times. */
6128 new = make_extraction (mode, XEXP (inner, 0),
6129 0, 0, len - INTVAL (XEXP (inner, 1)),
6130 unsignedp, in_dest, in_compare);
6132 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6135 inner_mode = GET_MODE (inner);
6137 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6138 pos = INTVAL (pos_rtx), pos_rtx = 0;
6140 /* See if this can be done without an extraction. We never can if the
6141 width of the field is not the same as that of some integer mode. For
6142 registers, we can only avoid the extraction if the position is at the
6143 low-order bit and this is either not in the destination or we have the
6144 appropriate STRICT_LOW_PART operation available.
6146 For MEM, we can avoid an extract if the field starts on an appropriate
6147 boundary and we can change the mode of the memory reference. However,
6148 we cannot directly access the MEM if we have a USE and the underlying
6149 MEM is not TMODE. This combination means that MEM was being used in a
6150 context where bits outside its mode were being referenced; that is only
6151 valid in bit-field insns. */
6153 if (tmode != BLKmode
6154 && ! (spans_byte && inner_mode != tmode)
6155 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6156 && GET_CODE (inner) != MEM
6158 || (GET_CODE (inner) == REG
6159 && have_insn_for (STRICT_LOW_PART, tmode))))
6160 || (GET_CODE (inner) == MEM && pos_rtx == 0
6162 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6163 : BITS_PER_UNIT)) == 0
6164 /* We can't do this if we are widening INNER_MODE (it
6165 may not be aligned, for one thing). */
6166 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6167 && (inner_mode == tmode
6168 || (! mode_dependent_address_p (XEXP (inner, 0))
6169 && ! MEM_VOLATILE_P (inner))))))
6171 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6172 field. If the original and current mode are the same, we need not
6173 adjust the offset. Otherwise, we do if bytes big endian.
6175 If INNER is not a MEM, get a piece consisting of just the field
6176 of interest (in this case POS % BITS_PER_WORD must be 0). */
6178 if (GET_CODE (inner) == MEM)
6180 HOST_WIDE_INT offset;
6182 /* POS counts from lsb, but make OFFSET count in memory order. */
6183 if (BYTES_BIG_ENDIAN)
6184 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6186 offset = pos / BITS_PER_UNIT;
6188 new = adjust_address_nv (inner, tmode, offset);
6190 else if (GET_CODE (inner) == REG)
6192 /* We can't call gen_lowpart_for_combine here since we always want
6193 a SUBREG and it would sometimes return a new hard register. */
6194 if (tmode != inner_mode)
6196 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6198 if (WORDS_BIG_ENDIAN
6199 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6200 final_word = ((GET_MODE_SIZE (inner_mode)
6201 - GET_MODE_SIZE (tmode))
6202 / UNITS_PER_WORD) - final_word;
6204 final_word *= UNITS_PER_WORD;
6205 if (BYTES_BIG_ENDIAN &&
6206 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6207 final_word += (GET_MODE_SIZE (inner_mode)
6208 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6210 /* Avoid creating invalid subregs, for example when
6211 simplifying (x>>32)&255. */
6212 if (final_word >= GET_MODE_SIZE (inner_mode))
6215 new = gen_rtx_SUBREG (tmode, inner, final_word);
6221 new = force_to_mode (inner, tmode,
6222 len >= HOST_BITS_PER_WIDE_INT
6223 ? ~(unsigned HOST_WIDE_INT) 0
6224 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6227 /* If this extraction is going into the destination of a SET,
6228 make a STRICT_LOW_PART unless we made a MEM. */
6231 return (GET_CODE (new) == MEM ? new
6232 : (GET_CODE (new) != SUBREG
6233 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6234 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6239 if (GET_CODE (new) == CONST_INT)
6240 return gen_int_mode (INTVAL (new), mode);
6242 /* If we know that no extraneous bits are set, and that the high
6243 bit is not set, convert the extraction to the cheaper of
6244 sign and zero extension, that are equivalent in these cases. */
6245 if (flag_expensive_optimizations
6246 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6247 && ((nonzero_bits (new, tmode)
6248 & ~(((unsigned HOST_WIDE_INT)
6249 GET_MODE_MASK (tmode))
6253 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6254 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6256 /* Prefer ZERO_EXTENSION, since it gives more information to
6258 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6263 /* Otherwise, sign- or zero-extend unless we already are in the
6266 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6270 /* Unless this is a COMPARE or we have a funny memory reference,
6271 don't do anything with zero-extending field extracts starting at
6272 the low-order bit since they are simple AND operations. */
6273 if (pos_rtx == 0 && pos == 0 && ! in_dest
6274 && ! in_compare && ! spans_byte && unsignedp)
6277 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6278 we would be spanning bytes or if the position is not a constant and the
6279 length is not 1. In all other cases, we would only be going outside
6280 our object in cases when an original shift would have been
6282 if (! spans_byte && GET_CODE (inner) == MEM
6283 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6284 || (pos_rtx != 0 && len != 1)))
6287 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6288 and the mode for the result. */
6289 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6291 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6292 pos_mode = mode_for_extraction (EP_insv, 2);
6293 extraction_mode = mode_for_extraction (EP_insv, 3);
6296 if (! in_dest && unsignedp
6297 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6299 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6300 pos_mode = mode_for_extraction (EP_extzv, 3);
6301 extraction_mode = mode_for_extraction (EP_extzv, 0);
6304 if (! in_dest && ! unsignedp
6305 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6307 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6308 pos_mode = mode_for_extraction (EP_extv, 3);
6309 extraction_mode = mode_for_extraction (EP_extv, 0);
6312 /* Never narrow an object, since that might not be safe. */
6314 if (mode != VOIDmode
6315 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6316 extraction_mode = mode;
6318 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6319 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6320 pos_mode = GET_MODE (pos_rtx);
6322 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6323 if we have to change the mode of memory and cannot, the desired mode is
6325 if (GET_CODE (inner) != MEM)
6326 wanted_inner_mode = wanted_inner_reg_mode;
6327 else if (inner_mode != wanted_inner_mode
6328 && (mode_dependent_address_p (XEXP (inner, 0))
6329 || MEM_VOLATILE_P (inner)))
6330 wanted_inner_mode = extraction_mode;
6334 if (BITS_BIG_ENDIAN)
6336 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6337 BITS_BIG_ENDIAN style. If position is constant, compute new
6338 position. Otherwise, build subtraction.
6339 Note that POS is relative to the mode of the original argument.
6340 If it's a MEM we need to recompute POS relative to that.
6341 However, if we're extracting from (or inserting into) a register,
6342 we want to recompute POS relative to wanted_inner_mode. */
6343 int width = (GET_CODE (inner) == MEM
6344 ? GET_MODE_BITSIZE (is_mode)
6345 : GET_MODE_BITSIZE (wanted_inner_mode));
6348 pos = width - len - pos;
6351 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6352 /* POS may be less than 0 now, but we check for that below.
6353 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6356 /* If INNER has a wider mode, make it smaller. If this is a constant
6357 extract, try to adjust the byte to point to the byte containing
6359 if (wanted_inner_mode != VOIDmode
6360 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6361 && ((GET_CODE (inner) == MEM
6362 && (inner_mode == wanted_inner_mode
6363 || (! mode_dependent_address_p (XEXP (inner, 0))
6364 && ! MEM_VOLATILE_P (inner))))))
6368 /* The computations below will be correct if the machine is big
6369 endian in both bits and bytes or little endian in bits and bytes.
6370 If it is mixed, we must adjust. */
6372 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6373 adjust OFFSET to compensate. */
6374 if (BYTES_BIG_ENDIAN
6376 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6377 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6379 /* If this is a constant position, we can move to the desired byte. */
6382 offset += pos / BITS_PER_UNIT;
6383 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6386 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6388 && is_mode != wanted_inner_mode)
6389 offset = (GET_MODE_SIZE (is_mode)
6390 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6392 if (offset != 0 || inner_mode != wanted_inner_mode)
6393 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6396 /* If INNER is not memory, we can always get it into the proper mode. If we
6397 are changing its mode, POS must be a constant and smaller than the size
6399 else if (GET_CODE (inner) != MEM)
6401 if (GET_MODE (inner) != wanted_inner_mode
6403 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6406 inner = force_to_mode (inner, wanted_inner_mode,
6408 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6409 ? ~(unsigned HOST_WIDE_INT) 0
6410 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6415 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6416 have to zero extend. Otherwise, we can just use a SUBREG. */
6418 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6420 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6422 /* If we know that no extraneous bits are set, and that the high
6423 bit is not set, convert extraction to cheaper one - either
6424 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6426 if (flag_expensive_optimizations
6427 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6428 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6429 & ~(((unsigned HOST_WIDE_INT)
6430 GET_MODE_MASK (GET_MODE (pos_rtx)))
6434 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6436 /* Prefer ZERO_EXTENSION, since it gives more information to
6438 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6443 else if (pos_rtx != 0
6444 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6445 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6447 /* Make POS_RTX unless we already have it and it is correct. If we don't
6448 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6450 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6451 pos_rtx = orig_pos_rtx;
6453 else if (pos_rtx == 0)
6454 pos_rtx = GEN_INT (pos);
6456 /* Make the required operation. See if we can use existing rtx. */
6457 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6458 extraction_mode, inner, GEN_INT (len), pos_rtx);
6460 new = gen_lowpart_for_combine (mode, new);
6465 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6466 with any other operations in X. Return X without that shift if so. */
6469 extract_left_shift (x, count)
6473 enum rtx_code code = GET_CODE (x);
6474 enum machine_mode mode = GET_MODE (x);
6480 /* This is the shift itself. If it is wide enough, we will return
6481 either the value being shifted if the shift count is equal to
6482 COUNT or a shift for the difference. */
6483 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6484 && INTVAL (XEXP (x, 1)) >= count)
6485 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6486 INTVAL (XEXP (x, 1)) - count);
6490 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6491 return simplify_gen_unary (code, mode, tem, mode);
6495 case PLUS: case IOR: case XOR: case AND:
6496 /* If we can safely shift this constant and we find the inner shift,
6497 make a new operation. */
6498 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6499 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6500 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6501 return gen_binary (code, mode, tem,
6502 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6513 /* Look at the expression rooted at X. Look for expressions
6514 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6515 Form these expressions.
6517 Return the new rtx, usually just X.
6519 Also, for machines like the VAX that don't have logical shift insns,
6520 try to convert logical to arithmetic shift operations in cases where
6521 they are equivalent. This undoes the canonicalizations to logical
6522 shifts done elsewhere.
6524 We try, as much as possible, to re-use rtl expressions to save memory.
6526 IN_CODE says what kind of expression we are processing. Normally, it is
6527 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6528 being kludges), it is MEM. When processing the arguments of a comparison
6529 or a COMPARE against zero, it is COMPARE. */
6532 make_compound_operation (x, in_code)
6534 enum rtx_code in_code;
6536 enum rtx_code code = GET_CODE (x);
6537 enum machine_mode mode = GET_MODE (x);
6538 int mode_width = GET_MODE_BITSIZE (mode);
6540 enum rtx_code next_code;
6546 /* Select the code to be used in recursive calls. Once we are inside an
6547 address, we stay there. If we have a comparison, set to COMPARE,
6548 but once inside, go back to our default of SET. */
6550 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6551 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6552 && XEXP (x, 1) == const0_rtx) ? COMPARE
6553 : in_code == COMPARE ? SET : in_code);
6555 /* Process depending on the code of this operation. If NEW is set
6556 nonzero, it will be returned. */
6561 /* Convert shifts by constants into multiplications if inside
6563 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6564 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6565 && INTVAL (XEXP (x, 1)) >= 0)
6567 new = make_compound_operation (XEXP (x, 0), next_code);
6568 new = gen_rtx_MULT (mode, new,
6569 GEN_INT ((HOST_WIDE_INT) 1
6570 << INTVAL (XEXP (x, 1))));
6575 /* If the second operand is not a constant, we can't do anything
6577 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6580 /* If the constant is a power of two minus one and the first operand
6581 is a logical right shift, make an extraction. */
6582 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6583 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6585 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6586 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6587 0, in_code == COMPARE);
6590 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6591 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6592 && subreg_lowpart_p (XEXP (x, 0))
6593 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6594 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6596 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6598 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6599 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6600 0, in_code == COMPARE);
6602 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6603 else if ((GET_CODE (XEXP (x, 0)) == XOR
6604 || GET_CODE (XEXP (x, 0)) == IOR)
6605 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6606 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6607 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6609 /* Apply the distributive law, and then try to make extractions. */
6610 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6611 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6613 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6615 new = make_compound_operation (new, in_code);
6618 /* If we are have (and (rotate X C) M) and C is larger than the number
6619 of bits in M, this is an extraction. */
6621 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6622 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6623 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6624 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6626 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6627 new = make_extraction (mode, new,
6628 (GET_MODE_BITSIZE (mode)
6629 - INTVAL (XEXP (XEXP (x, 0), 1))),
6630 NULL_RTX, i, 1, 0, in_code == COMPARE);
6633 /* On machines without logical shifts, if the operand of the AND is
6634 a logical shift and our mask turns off all the propagated sign
6635 bits, we can replace the logical shift with an arithmetic shift. */
6636 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6637 && !have_insn_for (LSHIFTRT, mode)
6638 && have_insn_for (ASHIFTRT, mode)
6639 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6640 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6641 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6642 && mode_width <= HOST_BITS_PER_WIDE_INT)
6644 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6646 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6647 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6649 gen_rtx_ASHIFTRT (mode,
6650 make_compound_operation
6651 (XEXP (XEXP (x, 0), 0), next_code),
6652 XEXP (XEXP (x, 0), 1)));
6655 /* If the constant is one less than a power of two, this might be
6656 representable by an extraction even if no shift is present.
6657 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6658 we are in a COMPARE. */
6659 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6660 new = make_extraction (mode,
6661 make_compound_operation (XEXP (x, 0),
6663 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6665 /* If we are in a comparison and this is an AND with a power of two,
6666 convert this into the appropriate bit extract. */
6667 else if (in_code == COMPARE
6668 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6669 new = make_extraction (mode,
6670 make_compound_operation (XEXP (x, 0),
6672 i, NULL_RTX, 1, 1, 0, 1);
6677 /* If the sign bit is known to be zero, replace this with an
6678 arithmetic shift. */
6679 if (have_insn_for (ASHIFTRT, mode)
6680 && ! have_insn_for (LSHIFTRT, mode)
6681 && mode_width <= HOST_BITS_PER_WIDE_INT
6682 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6684 new = gen_rtx_ASHIFTRT (mode,
6685 make_compound_operation (XEXP (x, 0),
6691 /* ... fall through ... */
6697 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6698 this is a SIGN_EXTRACT. */
6699 if (GET_CODE (rhs) == CONST_INT
6700 && GET_CODE (lhs) == ASHIFT
6701 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6702 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6704 new = make_compound_operation (XEXP (lhs, 0), next_code);
6705 new = make_extraction (mode, new,
6706 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6707 NULL_RTX, mode_width - INTVAL (rhs),
6708 code == LSHIFTRT, 0, in_code == COMPARE);
6712 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6713 If so, try to merge the shifts into a SIGN_EXTEND. We could
6714 also do this for some cases of SIGN_EXTRACT, but it doesn't
6715 seem worth the effort; the case checked for occurs on Alpha. */
6717 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6718 && ! (GET_CODE (lhs) == SUBREG
6719 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6720 && GET_CODE (rhs) == CONST_INT
6721 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6722 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6723 new = make_extraction (mode, make_compound_operation (new, next_code),
6724 0, NULL_RTX, mode_width - INTVAL (rhs),
6725 code == LSHIFTRT, 0, in_code == COMPARE);
6730 /* Call ourselves recursively on the inner expression. If we are
6731 narrowing the object and it has a different RTL code from
6732 what it originally did, do this SUBREG as a force_to_mode. */
6734 tem = make_compound_operation (SUBREG_REG (x), in_code);
6735 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6736 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6737 && subreg_lowpart_p (x))
6739 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6742 /* If we have something other than a SUBREG, we might have
6743 done an expansion, so rerun ourselves. */
6744 if (GET_CODE (newer) != SUBREG)
6745 newer = make_compound_operation (newer, in_code);
6750 /* If this is a paradoxical subreg, and the new code is a sign or
6751 zero extension, omit the subreg and widen the extension. If it
6752 is a regular subreg, we can still get rid of the subreg by not
6753 widening so much, or in fact removing the extension entirely. */
6754 if ((GET_CODE (tem) == SIGN_EXTEND
6755 || GET_CODE (tem) == ZERO_EXTEND)
6756 && subreg_lowpart_p (x))
6758 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6759 || (GET_MODE_SIZE (mode) >
6760 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6762 if (! SCALAR_INT_MODE_P (mode))
6764 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6767 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6778 x = gen_lowpart_for_combine (mode, new);
6779 code = GET_CODE (x);
6782 /* Now recursively process each operand of this operation. */
6783 fmt = GET_RTX_FORMAT (code);
6784 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6787 new = make_compound_operation (XEXP (x, i), next_code);
6788 SUBST (XEXP (x, i), new);
6794 /* Given M see if it is a value that would select a field of bits
6795 within an item, but not the entire word. Return -1 if not.
6796 Otherwise, return the starting position of the field, where 0 is the
6799 *PLEN is set to the length of the field. */
6802 get_pos_from_mask (m, plen)
6803 unsigned HOST_WIDE_INT m;
6804 unsigned HOST_WIDE_INT *plen;
6806 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6807 int pos = exact_log2 (m & -m);
6813 /* Now shift off the low-order zero bits and see if we have a power of
6815 len = exact_log2 ((m >> pos) + 1);
6824 /* See if X can be simplified knowing that we will only refer to it in
6825 MODE and will only refer to those bits that are nonzero in MASK.
6826 If other bits are being computed or if masking operations are done
6827 that select a superset of the bits in MASK, they can sometimes be
6830 Return a possibly simplified expression, but always convert X to
6831 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6833 Also, if REG is nonzero and X is a register equal in value to REG,
6836 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6837 are all off in X. This is used when X will be complemented, by either
6838 NOT, NEG, or XOR. */
6841 force_to_mode (x, mode, mask, reg, just_select)
6843 enum machine_mode mode;
6844 unsigned HOST_WIDE_INT mask;
6848 enum rtx_code code = GET_CODE (x);
6849 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6850 enum machine_mode op_mode;
6851 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6854 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6855 code below will do the wrong thing since the mode of such an
6856 expression is VOIDmode.
6858 Also do nothing if X is a CLOBBER; this can happen if X was
6859 the return value from a call to gen_lowpart_for_combine. */
6860 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6863 /* We want to perform the operation is its present mode unless we know
6864 that the operation is valid in MODE, in which case we do the operation
6866 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6867 && have_insn_for (code, mode))
6868 ? mode : GET_MODE (x));
6870 /* It is not valid to do a right-shift in a narrower mode
6871 than the one it came in with. */
6872 if ((code == LSHIFTRT || code == ASHIFTRT)
6873 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6874 op_mode = GET_MODE (x);
6876 /* Truncate MASK to fit OP_MODE. */
6878 mask &= GET_MODE_MASK (op_mode);
6880 /* When we have an arithmetic operation, or a shift whose count we
6881 do not know, we need to assume that all bit the up to the highest-order
6882 bit in MASK will be needed. This is how we form such a mask. */
6884 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6885 ? GET_MODE_MASK (op_mode)
6886 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6889 fuller_mask = ~(HOST_WIDE_INT) 0;
6891 /* Determine what bits of X are guaranteed to be (non)zero. */
6892 nonzero = nonzero_bits (x, mode);
6894 /* If none of the bits in X are needed, return a zero. */
6895 if (! just_select && (nonzero & mask) == 0)
6898 /* If X is a CONST_INT, return a new one. Do this here since the
6899 test below will fail. */
6900 if (GET_CODE (x) == CONST_INT)
6902 if (SCALAR_INT_MODE_P (mode))
6903 return gen_int_mode (INTVAL (x) & mask, mode);
6906 x = GEN_INT (INTVAL (x) & mask);
6907 return gen_lowpart_common (mode, x);
6911 /* If X is narrower than MODE and we want all the bits in X's mode, just
6912 get X in the proper mode. */
6913 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6914 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6915 return gen_lowpart_for_combine (mode, x);
6917 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6918 MASK are already known to be zero in X, we need not do anything. */
6919 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6925 /* If X is a (clobber (const_int)), return it since we know we are
6926 generating something that won't match. */
6930 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6931 spanned the boundary of the MEM. If we are now masking so it is
6932 within that boundary, we don't need the USE any more. */
6933 if (! BITS_BIG_ENDIAN
6934 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6935 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6942 x = expand_compound_operation (x);
6943 if (GET_CODE (x) != code)
6944 return force_to_mode (x, mode, mask, reg, next_select);
6948 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6949 || rtx_equal_p (reg, get_last_value (x))))
6954 if (subreg_lowpart_p (x)
6955 /* We can ignore the effect of this SUBREG if it narrows the mode or
6956 if the constant masks to zero all the bits the mode doesn't
6958 && ((GET_MODE_SIZE (GET_MODE (x))
6959 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6961 & GET_MODE_MASK (GET_MODE (x))
6962 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6963 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6967 /* If this is an AND with a constant, convert it into an AND
6968 whose constant is the AND of that constant with MASK. If it
6969 remains an AND of MASK, delete it since it is redundant. */
6971 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6973 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6974 mask & INTVAL (XEXP (x, 1)));
6976 /* If X is still an AND, see if it is an AND with a mask that
6977 is just some low-order bits. If so, and it is MASK, we don't
6980 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6981 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6985 /* If it remains an AND, try making another AND with the bits
6986 in the mode mask that aren't in MASK turned on. If the
6987 constant in the AND is wide enough, this might make a
6988 cheaper constant. */
6990 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6991 && GET_MODE_MASK (GET_MODE (x)) != mask
6992 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6994 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6995 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6996 int width = GET_MODE_BITSIZE (GET_MODE (x));
6999 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
7000 number, sign extend it. */
7001 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7002 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7003 cval |= (HOST_WIDE_INT) -1 << width;
7005 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
7006 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7016 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7017 low-order bits (as in an alignment operation) and FOO is already
7018 aligned to that boundary, mask C1 to that boundary as well.
7019 This may eliminate that PLUS and, later, the AND. */
7022 unsigned int width = GET_MODE_BITSIZE (mode);
7023 unsigned HOST_WIDE_INT smask = mask;
7025 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7026 number, sign extend it. */
7028 if (width < HOST_BITS_PER_WIDE_INT
7029 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7030 smask |= (HOST_WIDE_INT) -1 << width;
7032 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7033 && exact_log2 (- smask) >= 0
7034 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7035 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7036 return force_to_mode (plus_constant (XEXP (x, 0),
7037 (INTVAL (XEXP (x, 1)) & smask)),
7038 mode, smask, reg, next_select);
7041 /* ... fall through ... */
7044 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7045 most significant bit in MASK since carries from those bits will
7046 affect the bits we are interested in. */
7051 /* If X is (minus C Y) where C's least set bit is larger than any bit
7052 in the mask, then we may replace with (neg Y). */
7053 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7054 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7055 & -INTVAL (XEXP (x, 0))))
7058 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7060 return force_to_mode (x, mode, mask, reg, next_select);
7063 /* Similarly, if C contains every bit in the fuller_mask, then we may
7064 replace with (not Y). */
7065 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7066 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7067 == INTVAL (XEXP (x, 0))))
7069 x = simplify_gen_unary (NOT, GET_MODE (x),
7070 XEXP (x, 1), GET_MODE (x));
7071 return force_to_mode (x, mode, mask, reg, next_select);
7079 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7080 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7081 operation which may be a bitfield extraction. Ensure that the
7082 constant we form is not wider than the mode of X. */
7084 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7085 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7086 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7087 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7088 && GET_CODE (XEXP (x, 1)) == CONST_INT
7089 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7090 + floor_log2 (INTVAL (XEXP (x, 1))))
7091 < GET_MODE_BITSIZE (GET_MODE (x)))
7092 && (INTVAL (XEXP (x, 1))
7093 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7095 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7096 << INTVAL (XEXP (XEXP (x, 0), 1)));
7097 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7098 XEXP (XEXP (x, 0), 0), temp);
7099 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7100 XEXP (XEXP (x, 0), 1));
7101 return force_to_mode (x, mode, mask, reg, next_select);
7105 /* For most binary operations, just propagate into the operation and
7106 change the mode if we have an operation of that mode. */
7108 op0 = gen_lowpart_for_combine (op_mode,
7109 force_to_mode (XEXP (x, 0), mode, mask,
7111 op1 = gen_lowpart_for_combine (op_mode,
7112 force_to_mode (XEXP (x, 1), mode, mask,
7115 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7116 x = gen_binary (code, op_mode, op0, op1);
7120 /* For left shifts, do the same, but just for the first operand.
7121 However, we cannot do anything with shifts where we cannot
7122 guarantee that the counts are smaller than the size of the mode
7123 because such a count will have a different meaning in a
7126 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7127 && INTVAL (XEXP (x, 1)) >= 0
7128 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7129 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7130 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7131 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7134 /* If the shift count is a constant and we can do arithmetic in
7135 the mode of the shift, refine which bits we need. Otherwise, use the
7136 conservative form of the mask. */
7137 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7138 && INTVAL (XEXP (x, 1)) >= 0
7139 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7140 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7141 mask >>= INTVAL (XEXP (x, 1));
7145 op0 = gen_lowpart_for_combine (op_mode,
7146 force_to_mode (XEXP (x, 0), op_mode,
7147 mask, reg, next_select));
7149 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7150 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7154 /* Here we can only do something if the shift count is a constant,
7155 this shift constant is valid for the host, and we can do arithmetic
7158 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7159 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7160 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7162 rtx inner = XEXP (x, 0);
7163 unsigned HOST_WIDE_INT inner_mask;
7165 /* Select the mask of the bits we need for the shift operand. */
7166 inner_mask = mask << INTVAL (XEXP (x, 1));
7168 /* We can only change the mode of the shift if we can do arithmetic
7169 in the mode of the shift and INNER_MASK is no wider than the
7170 width of OP_MODE. */
7171 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7172 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7173 op_mode = GET_MODE (x);
7175 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7177 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7178 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7181 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7182 shift and AND produces only copies of the sign bit (C2 is one less
7183 than a power of two), we can do this with just a shift. */
7185 if (GET_CODE (x) == LSHIFTRT
7186 && GET_CODE (XEXP (x, 1)) == CONST_INT
7187 /* The shift puts one of the sign bit copies in the least significant
7189 && ((INTVAL (XEXP (x, 1))
7190 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7191 >= GET_MODE_BITSIZE (GET_MODE (x)))
7192 && exact_log2 (mask + 1) >= 0
7193 /* Number of bits left after the shift must be more than the mask
7195 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7196 <= GET_MODE_BITSIZE (GET_MODE (x)))
7197 /* Must be more sign bit copies than the mask needs. */
7198 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7199 >= exact_log2 (mask + 1)))
7200 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7201 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7202 - exact_log2 (mask + 1)));
7207 /* If we are just looking for the sign bit, we don't need this shift at
7208 all, even if it has a variable count. */
7209 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7210 && (mask == ((unsigned HOST_WIDE_INT) 1
7211 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7212 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7214 /* If this is a shift by a constant, get a mask that contains those bits
7215 that are not copies of the sign bit. We then have two cases: If
7216 MASK only includes those bits, this can be a logical shift, which may
7217 allow simplifications. If MASK is a single-bit field not within
7218 those bits, we are requesting a copy of the sign bit and hence can
7219 shift the sign bit to the appropriate location. */
7221 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7222 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7226 /* If the considered data is wider than HOST_WIDE_INT, we can't
7227 represent a mask for all its bits in a single scalar.
7228 But we only care about the lower bits, so calculate these. */
7230 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7232 nonzero = ~(HOST_WIDE_INT) 0;
7234 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7235 is the number of bits a full-width mask would have set.
7236 We need only shift if these are fewer than nonzero can
7237 hold. If not, we must keep all bits set in nonzero. */
7239 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7240 < HOST_BITS_PER_WIDE_INT)
7241 nonzero >>= INTVAL (XEXP (x, 1))
7242 + HOST_BITS_PER_WIDE_INT
7243 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7247 nonzero = GET_MODE_MASK (GET_MODE (x));
7248 nonzero >>= INTVAL (XEXP (x, 1));
7251 if ((mask & ~nonzero) == 0
7252 || (i = exact_log2 (mask)) >= 0)
7254 x = simplify_shift_const
7255 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7256 i < 0 ? INTVAL (XEXP (x, 1))
7257 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7259 if (GET_CODE (x) != ASHIFTRT)
7260 return force_to_mode (x, mode, mask, reg, next_select);
7264 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7265 even if the shift count isn't a constant. */
7267 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7271 /* If this is a zero- or sign-extension operation that just affects bits
7272 we don't care about, remove it. Be sure the call above returned
7273 something that is still a shift. */
7275 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7276 && GET_CODE (XEXP (x, 1)) == CONST_INT
7277 && INTVAL (XEXP (x, 1)) >= 0
7278 && (INTVAL (XEXP (x, 1))
7279 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7280 && GET_CODE (XEXP (x, 0)) == ASHIFT
7281 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7282 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7283 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7290 /* If the shift count is constant and we can do computations
7291 in the mode of X, compute where the bits we care about are.
7292 Otherwise, we can't do anything. Don't change the mode of
7293 the shift or propagate MODE into the shift, though. */
7294 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7295 && INTVAL (XEXP (x, 1)) >= 0)
7297 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7298 GET_MODE (x), GEN_INT (mask),
7300 if (temp && GET_CODE (temp) == CONST_INT)
7302 force_to_mode (XEXP (x, 0), GET_MODE (x),
7303 INTVAL (temp), reg, next_select));
7308 /* If we just want the low-order bit, the NEG isn't needed since it
7309 won't change the low-order bit. */
7311 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7313 /* We need any bits less significant than the most significant bit in
7314 MASK since carries from those bits will affect the bits we are
7320 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7321 same as the XOR case above. Ensure that the constant we form is not
7322 wider than the mode of X. */
7324 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7325 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7326 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7327 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7328 < GET_MODE_BITSIZE (GET_MODE (x)))
7329 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7331 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7333 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7334 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7336 return force_to_mode (x, mode, mask, reg, next_select);
7339 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7340 use the full mask inside the NOT. */
7344 op0 = gen_lowpart_for_combine (op_mode,
7345 force_to_mode (XEXP (x, 0), mode, mask,
7347 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7348 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7352 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7353 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7354 which is equal to STORE_FLAG_VALUE. */
7355 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7356 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7357 && (nonzero_bits (XEXP (x, 0), mode)
7358 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7359 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7364 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7365 written in a narrower mode. We play it safe and do not do so. */
7368 gen_lowpart_for_combine (GET_MODE (x),
7369 force_to_mode (XEXP (x, 1), mode,
7370 mask, reg, next_select)));
7372 gen_lowpart_for_combine (GET_MODE (x),
7373 force_to_mode (XEXP (x, 2), mode,
7374 mask, reg, next_select)));
7381 /* Ensure we return a value of the proper mode. */
7382 return gen_lowpart_for_combine (mode, x);
7385 /* Return nonzero if X is an expression that has one of two values depending on
7386 whether some other value is zero or nonzero. In that case, we return the
7387 value that is being tested, *PTRUE is set to the value if the rtx being
7388 returned has a nonzero value, and *PFALSE is set to the other alternative.
7390 If we return zero, we set *PTRUE and *PFALSE to X. */
7393 if_then_else_cond (x, ptrue, pfalse)
7395 rtx *ptrue, *pfalse;
7397 enum machine_mode mode = GET_MODE (x);
7398 enum rtx_code code = GET_CODE (x);
7399 rtx cond0, cond1, true0, true1, false0, false1;
7400 unsigned HOST_WIDE_INT nz;
7402 /* If we are comparing a value against zero, we are done. */
7403 if ((code == NE || code == EQ)
7404 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7406 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7407 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7411 /* If this is a unary operation whose operand has one of two values, apply
7412 our opcode to compute those values. */
7413 else if (GET_RTX_CLASS (code) == '1'
7414 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7416 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7417 *pfalse = simplify_gen_unary (code, mode, false0,
7418 GET_MODE (XEXP (x, 0)));
7422 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7423 make can't possibly match and would suppress other optimizations. */
7424 else if (code == COMPARE)
7427 /* If this is a binary operation, see if either side has only one of two
7428 values. If either one does or if both do and they are conditional on
7429 the same value, compute the new true and false values. */
7430 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7431 || GET_RTX_CLASS (code) == '<')
7433 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7434 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7436 if ((cond0 != 0 || cond1 != 0)
7437 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7439 /* If if_then_else_cond returned zero, then true/false are the
7440 same rtl. We must copy one of them to prevent invalid rtl
7443 true0 = copy_rtx (true0);
7444 else if (cond1 == 0)
7445 true1 = copy_rtx (true1);
7447 *ptrue = gen_binary (code, mode, true0, true1);
7448 *pfalse = gen_binary (code, mode, false0, false1);
7449 return cond0 ? cond0 : cond1;
7452 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7453 operands is zero when the other is nonzero, and vice-versa,
7454 and STORE_FLAG_VALUE is 1 or -1. */
7456 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7457 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7459 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7461 rtx op0 = XEXP (XEXP (x, 0), 1);
7462 rtx op1 = XEXP (XEXP (x, 1), 1);
7464 cond0 = XEXP (XEXP (x, 0), 0);
7465 cond1 = XEXP (XEXP (x, 1), 0);
7467 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7468 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7469 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7470 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7471 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7472 || ((swap_condition (GET_CODE (cond0))
7473 == combine_reversed_comparison_code (cond1))
7474 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7475 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7476 && ! side_effects_p (x))
7478 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7479 *pfalse = gen_binary (MULT, mode,
7481 ? simplify_gen_unary (NEG, mode, op1,
7489 /* Similarly for MULT, AND and UMIN, except that for these the result
7491 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7492 && (code == MULT || code == AND || code == UMIN)
7493 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7495 cond0 = XEXP (XEXP (x, 0), 0);
7496 cond1 = XEXP (XEXP (x, 1), 0);
7498 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7499 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7500 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7501 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7502 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7503 || ((swap_condition (GET_CODE (cond0))
7504 == combine_reversed_comparison_code (cond1))
7505 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7506 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7507 && ! side_effects_p (x))
7509 *ptrue = *pfalse = const0_rtx;
7515 else if (code == IF_THEN_ELSE)
7517 /* If we have IF_THEN_ELSE already, extract the condition and
7518 canonicalize it if it is NE or EQ. */
7519 cond0 = XEXP (x, 0);
7520 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7521 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7522 return XEXP (cond0, 0);
7523 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7525 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7526 return XEXP (cond0, 0);
7532 /* If X is a SUBREG, we can narrow both the true and false values
7533 if the inner expression, if there is a condition. */
7534 else if (code == SUBREG
7535 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7538 *ptrue = simplify_gen_subreg (mode, true0,
7539 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7540 *pfalse = simplify_gen_subreg (mode, false0,
7541 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7546 /* If X is a constant, this isn't special and will cause confusions
7547 if we treat it as such. Likewise if it is equivalent to a constant. */
7548 else if (CONSTANT_P (x)
7549 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7552 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7553 will be least confusing to the rest of the compiler. */
7554 else if (mode == BImode)
7556 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7560 /* If X is known to be either 0 or -1, those are the true and
7561 false values when testing X. */
7562 else if (x == constm1_rtx || x == const0_rtx
7563 || (mode != VOIDmode
7564 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7566 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7570 /* Likewise for 0 or a single bit. */
7571 else if (mode != VOIDmode
7572 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7573 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7575 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7579 /* Otherwise fail; show no condition with true and false values the same. */
7580 *ptrue = *pfalse = x;
7584 /* Return the value of expression X given the fact that condition COND
7585 is known to be true when applied to REG as its first operand and VAL
7586 as its second. X is known to not be shared and so can be modified in
7589 We only handle the simplest cases, and specifically those cases that
7590 arise with IF_THEN_ELSE expressions. */
7593 known_cond (x, cond, reg, val)
7598 enum rtx_code code = GET_CODE (x);
7603 if (side_effects_p (x))
7606 /* If either operand of the condition is a floating point value,
7607 then we have to avoid collapsing an EQ comparison. */
7609 && rtx_equal_p (x, reg)
7610 && ! FLOAT_MODE_P (GET_MODE (x))
7611 && ! FLOAT_MODE_P (GET_MODE (val)))
7614 if (cond == UNEQ && rtx_equal_p (x, reg))
7617 /* If X is (abs REG) and we know something about REG's relationship
7618 with zero, we may be able to simplify this. */
7620 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7623 case GE: case GT: case EQ:
7626 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7628 GET_MODE (XEXP (x, 0)));
7633 /* The only other cases we handle are MIN, MAX, and comparisons if the
7634 operands are the same as REG and VAL. */
7636 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7638 if (rtx_equal_p (XEXP (x, 0), val))
7639 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7641 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7643 if (GET_RTX_CLASS (code) == '<')
7645 if (comparison_dominates_p (cond, code))
7646 return const_true_rtx;
7648 code = combine_reversed_comparison_code (x);
7650 && comparison_dominates_p (cond, code))
7655 else if (code == SMAX || code == SMIN
7656 || code == UMIN || code == UMAX)
7658 int unsignedp = (code == UMIN || code == UMAX);
7660 /* Do not reverse the condition when it is NE or EQ.
7661 This is because we cannot conclude anything about
7662 the value of 'SMAX (x, y)' when x is not equal to y,
7663 but we can when x equals y. */
7664 if ((code == SMAX || code == UMAX)
7665 && ! (cond == EQ || cond == NE))
7666 cond = reverse_condition (cond);
7671 return unsignedp ? x : XEXP (x, 1);
7673 return unsignedp ? x : XEXP (x, 0);
7675 return unsignedp ? XEXP (x, 1) : x;
7677 return unsignedp ? XEXP (x, 0) : x;
7684 else if (code == SUBREG)
7686 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7687 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7689 if (SUBREG_REG (x) != r)
7691 /* We must simplify subreg here, before we lose track of the
7692 original inner_mode. */
7693 new = simplify_subreg (GET_MODE (x), r,
7694 inner_mode, SUBREG_BYTE (x));
7698 SUBST (SUBREG_REG (x), r);
7703 /* We don't have to handle SIGN_EXTEND here, because even in the
7704 case of replacing something with a modeless CONST_INT, a
7705 CONST_INT is already (supposed to be) a valid sign extension for
7706 its narrower mode, which implies it's already properly
7707 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7708 story is different. */
7709 else if (code == ZERO_EXTEND)
7711 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7712 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7714 if (XEXP (x, 0) != r)
7716 /* We must simplify the zero_extend here, before we lose
7717 track of the original inner_mode. */
7718 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7723 SUBST (XEXP (x, 0), r);
7729 fmt = GET_RTX_FORMAT (code);
7730 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7733 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7734 else if (fmt[i] == 'E')
7735 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7736 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7743 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7744 assignment as a field assignment. */
7747 rtx_equal_for_field_assignment_p (x, y)
7751 if (x == y || rtx_equal_p (x, y))
7754 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7757 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7758 Note that all SUBREGs of MEM are paradoxical; otherwise they
7759 would have been rewritten. */
7760 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7761 && GET_CODE (SUBREG_REG (y)) == MEM
7762 && rtx_equal_p (SUBREG_REG (y),
7763 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7766 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7767 && GET_CODE (SUBREG_REG (x)) == MEM
7768 && rtx_equal_p (SUBREG_REG (x),
7769 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7772 /* We used to see if get_last_value of X and Y were the same but that's
7773 not correct. In one direction, we'll cause the assignment to have
7774 the wrong destination and in the case, we'll import a register into this
7775 insn that might have already have been dead. So fail if none of the
7776 above cases are true. */
7780 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7781 Return that assignment if so.
7783 We only handle the most common cases. */
7786 make_field_assignment (x)
7789 rtx dest = SET_DEST (x);
7790 rtx src = SET_SRC (x);
7795 unsigned HOST_WIDE_INT len;
7797 enum machine_mode mode;
7799 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7800 a clear of a one-bit field. We will have changed it to
7801 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7804 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7805 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7806 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7807 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7809 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7812 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7816 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7817 && subreg_lowpart_p (XEXP (src, 0))
7818 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7819 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7820 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7821 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7822 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7824 assign = make_extraction (VOIDmode, dest, 0,
7825 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7828 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7832 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7834 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7835 && XEXP (XEXP (src, 0), 0) == const1_rtx
7836 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7838 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7841 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7845 /* The other case we handle is assignments into a constant-position
7846 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7847 a mask that has all one bits except for a group of zero bits and
7848 OTHER is known to have zeros where C1 has ones, this is such an
7849 assignment. Compute the position and length from C1. Shift OTHER
7850 to the appropriate position, force it to the required mode, and
7851 make the extraction. Check for the AND in both operands. */
7853 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7856 rhs = expand_compound_operation (XEXP (src, 0));
7857 lhs = expand_compound_operation (XEXP (src, 1));
7859 if (GET_CODE (rhs) == AND
7860 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7861 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7862 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7863 else if (GET_CODE (lhs) == AND
7864 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7865 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7866 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7870 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7871 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7872 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7873 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7876 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7880 /* The mode to use for the source is the mode of the assignment, or of
7881 what is inside a possible STRICT_LOW_PART. */
7882 mode = (GET_CODE (assign) == STRICT_LOW_PART
7883 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7885 /* Shift OTHER right POS places and make it the source, restricting it
7886 to the proper length and mode. */
7888 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7889 GET_MODE (src), other, pos),
7891 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7892 ? ~(unsigned HOST_WIDE_INT) 0
7893 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7896 /* If SRC is masked by an AND that does not make a difference in
7897 the value being stored, strip it. */
7898 if (GET_CODE (assign) == ZERO_EXTRACT
7899 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7900 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7901 && GET_CODE (src) == AND
7902 && GET_CODE (XEXP (src, 1)) == CONST_INT
7903 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7904 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7905 src = XEXP (src, 0);
7907 return gen_rtx_SET (VOIDmode, assign, src);
7910 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7914 apply_distributive_law (x)
7917 enum rtx_code code = GET_CODE (x);
7918 rtx lhs, rhs, other;
7920 enum rtx_code inner_code;
7922 /* Distributivity is not true for floating point.
7923 It can change the value. So don't do it.
7924 -- rms and moshier@world.std.com. */
7925 if (FLOAT_MODE_P (GET_MODE (x)))
7928 /* The outer operation can only be one of the following: */
7929 if (code != IOR && code != AND && code != XOR
7930 && code != PLUS && code != MINUS)
7933 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7935 /* If either operand is a primitive we can't do anything, so get out
7937 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7938 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7941 lhs = expand_compound_operation (lhs);
7942 rhs = expand_compound_operation (rhs);
7943 inner_code = GET_CODE (lhs);
7944 if (inner_code != GET_CODE (rhs))
7947 /* See if the inner and outer operations distribute. */
7954 /* These all distribute except over PLUS. */
7955 if (code == PLUS || code == MINUS)
7960 if (code != PLUS && code != MINUS)
7965 /* This is also a multiply, so it distributes over everything. */
7969 /* Non-paradoxical SUBREGs distributes over all operations, provided
7970 the inner modes and byte offsets are the same, this is an extraction
7971 of a low-order part, we don't convert an fp operation to int or
7972 vice versa, and we would not be converting a single-word
7973 operation into a multi-word operation. The latter test is not
7974 required, but it prevents generating unneeded multi-word operations.
7975 Some of the previous tests are redundant given the latter test, but
7976 are retained because they are required for correctness.
7978 We produce the result slightly differently in this case. */
7980 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7981 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7982 || ! subreg_lowpart_p (lhs)
7983 || (GET_MODE_CLASS (GET_MODE (lhs))
7984 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7985 || (GET_MODE_SIZE (GET_MODE (lhs))
7986 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7987 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7990 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7991 SUBREG_REG (lhs), SUBREG_REG (rhs));
7992 return gen_lowpart_for_combine (GET_MODE (x), tem);
7998 /* Set LHS and RHS to the inner operands (A and B in the example
7999 above) and set OTHER to the common operand (C in the example).
8000 These is only one way to do this unless the inner operation is
8002 if (GET_RTX_CLASS (inner_code) == 'c'
8003 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8004 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8005 else if (GET_RTX_CLASS (inner_code) == 'c'
8006 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8007 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8008 else if (GET_RTX_CLASS (inner_code) == 'c'
8009 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8010 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8011 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8012 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8016 /* Form the new inner operation, seeing if it simplifies first. */
8017 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
8019 /* There is one exception to the general way of distributing:
8020 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
8021 if (code == XOR && inner_code == IOR)
8024 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8027 /* We may be able to continuing distributing the result, so call
8028 ourselves recursively on the inner operation before forming the
8029 outer operation, which we return. */
8030 return gen_binary (inner_code, GET_MODE (x),
8031 apply_distributive_law (tem), other);
8034 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8037 Return an equivalent form, if different from X. Otherwise, return X. If
8038 X is zero, we are to always construct the equivalent form. */
8041 simplify_and_const_int (x, mode, varop, constop)
8043 enum machine_mode mode;
8045 unsigned HOST_WIDE_INT constop;
8047 unsigned HOST_WIDE_INT nonzero;
8050 /* Simplify VAROP knowing that we will be only looking at some of the
8053 Note by passing in CONSTOP, we guarantee that the bits not set in
8054 CONSTOP are not significant and will never be examined. We must
8055 ensure that is the case by explicitly masking out those bits
8056 before returning. */
8057 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8059 /* If VAROP is a CLOBBER, we will fail so return it. */
8060 if (GET_CODE (varop) == CLOBBER)
8063 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8064 to VAROP and return the new constant. */
8065 if (GET_CODE (varop) == CONST_INT)
8066 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8068 /* See what bits may be nonzero in VAROP. Unlike the general case of
8069 a call to nonzero_bits, here we don't care about bits outside
8072 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8074 /* Turn off all bits in the constant that are known to already be zero.
8075 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8076 which is tested below. */
8080 /* If we don't have any bits left, return zero. */
8084 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8085 a power of two, we can replace this with an ASHIFT. */
8086 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8087 && (i = exact_log2 (constop)) >= 0)
8088 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8090 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8091 or XOR, then try to apply the distributive law. This may eliminate
8092 operations if either branch can be simplified because of the AND.
8093 It may also make some cases more complex, but those cases probably
8094 won't match a pattern either with or without this. */
8096 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8098 gen_lowpart_for_combine
8100 apply_distributive_law
8101 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8102 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8103 XEXP (varop, 0), constop),
8104 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8105 XEXP (varop, 1), constop))));
8107 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8108 the AND and see if one of the operands simplifies to zero. If so, we
8109 may eliminate it. */
8111 if (GET_CODE (varop) == PLUS
8112 && exact_log2 (constop + 1) >= 0)
8116 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8117 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8118 if (o0 == const0_rtx)
8120 if (o1 == const0_rtx)
8124 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8125 if we already had one (just check for the simplest cases). */
8126 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8127 && GET_MODE (XEXP (x, 0)) == mode
8128 && SUBREG_REG (XEXP (x, 0)) == varop)
8129 varop = XEXP (x, 0);
8131 varop = gen_lowpart_for_combine (mode, varop);
8133 /* If we can't make the SUBREG, try to return what we were given. */
8134 if (GET_CODE (varop) == CLOBBER)
8135 return x ? x : varop;
8137 /* If we are only masking insignificant bits, return VAROP. */
8138 if (constop == nonzero)
8142 /* Otherwise, return an AND. */
8143 constop = trunc_int_for_mode (constop, mode);
8144 /* See how much, if any, of X we can use. */
8145 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8146 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8150 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8151 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8152 SUBST (XEXP (x, 1), GEN_INT (constop));
8154 SUBST (XEXP (x, 0), varop);
8161 #define nonzero_bits_with_known(X, MODE) \
8162 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8164 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8165 It avoids exponential behavior in nonzero_bits1 when X has
8166 identical subexpressions on the first or the second level. */
8168 static unsigned HOST_WIDE_INT
8169 cached_nonzero_bits (x, mode, known_x, known_mode, known_ret)
8171 enum machine_mode mode;
8173 enum machine_mode known_mode;
8174 unsigned HOST_WIDE_INT known_ret;
8176 if (x == known_x && mode == known_mode)
8179 /* Try to find identical subexpressions. If found call
8180 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8181 precomputed value for the subexpression as KNOWN_RET. */
8183 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8184 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8186 rtx x0 = XEXP (x, 0);
8187 rtx x1 = XEXP (x, 1);
8189 /* Check the first level. */
8191 return nonzero_bits1 (x, mode, x0, mode,
8192 nonzero_bits_with_known (x0, mode));
8194 /* Check the second level. */
8195 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8196 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8197 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8198 return nonzero_bits1 (x, mode, x1, mode,
8199 nonzero_bits_with_known (x1, mode));
8201 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8202 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8203 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8204 return nonzero_bits1 (x, mode, x0, mode,
8205 nonzero_bits_with_known (x0, mode));
8208 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8211 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8212 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8213 is less useful. We can't allow both, because that results in exponential
8214 run time recursion. There is a nullstone testcase that triggered
8215 this. This macro avoids accidental uses of num_sign_bit_copies. */
8216 #define cached_num_sign_bit_copies()
8218 /* Given an expression, X, compute which bits in X can be nonzero.
8219 We don't care about bits outside of those defined in MODE.
8221 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8222 a shift, AND, or zero_extract, we can do better. */
8224 static unsigned HOST_WIDE_INT
8225 nonzero_bits1 (x, mode, known_x, known_mode, known_ret)
8227 enum machine_mode mode;
8229 enum machine_mode known_mode;
8230 unsigned HOST_WIDE_INT known_ret;
8232 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8233 unsigned HOST_WIDE_INT inner_nz;
8235 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8238 /* For floating-point values, assume all bits are needed. */
8239 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8242 /* If X is wider than MODE, use its mode instead. */
8243 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8245 mode = GET_MODE (x);
8246 nonzero = GET_MODE_MASK (mode);
8247 mode_width = GET_MODE_BITSIZE (mode);
8250 if (mode_width > HOST_BITS_PER_WIDE_INT)
8251 /* Our only callers in this case look for single bit values. So
8252 just return the mode mask. Those tests will then be false. */
8255 #ifndef WORD_REGISTER_OPERATIONS
8256 /* If MODE is wider than X, but both are a single word for both the host
8257 and target machines, we can compute this from which bits of the
8258 object might be nonzero in its own mode, taking into account the fact
8259 that on many CISC machines, accessing an object in a wider mode
8260 causes the high-order bits to become undefined. So they are
8261 not known to be zero. */
8263 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8264 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8265 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8266 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8268 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8269 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8274 code = GET_CODE (x);
8278 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8279 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8280 all the bits above ptr_mode are known to be zero. */
8281 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8283 nonzero &= GET_MODE_MASK (ptr_mode);
8286 /* Include declared information about alignment of pointers. */
8287 /* ??? We don't properly preserve REG_POINTER changes across
8288 pointer-to-integer casts, so we can't trust it except for
8289 things that we know must be pointers. See execute/960116-1.c. */
8290 if ((x == stack_pointer_rtx
8291 || x == frame_pointer_rtx
8292 || x == arg_pointer_rtx)
8293 && REGNO_POINTER_ALIGN (REGNO (x)))
8295 unsigned HOST_WIDE_INT alignment
8296 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8298 #ifdef PUSH_ROUNDING
8299 /* If PUSH_ROUNDING is defined, it is possible for the
8300 stack to be momentarily aligned only to that amount,
8301 so we pick the least alignment. */
8302 if (x == stack_pointer_rtx && PUSH_ARGS)
8303 alignment = MIN (PUSH_ROUNDING (1), alignment);
8306 nonzero &= ~(alignment - 1);
8309 /* If X is a register whose nonzero bits value is current, use it.
8310 Otherwise, if X is a register whose value we can find, use that
8311 value. Otherwise, use the previously-computed global nonzero bits
8312 for this register. */
8314 if (reg_last_set_value[REGNO (x)] != 0
8315 && (reg_last_set_mode[REGNO (x)] == mode
8316 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8317 && GET_MODE_CLASS (mode) == MODE_INT))
8318 && (reg_last_set_label[REGNO (x)] == label_tick
8319 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8320 && REG_N_SETS (REGNO (x)) == 1
8321 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8323 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8324 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8326 tem = get_last_value (x);
8330 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8331 /* If X is narrower than MODE and TEM is a non-negative
8332 constant that would appear negative in the mode of X,
8333 sign-extend it for use in reg_nonzero_bits because some
8334 machines (maybe most) will actually do the sign-extension
8335 and this is the conservative approach.
8337 ??? For 2.5, try to tighten up the MD files in this regard
8338 instead of this kludge. */
8340 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8341 && GET_CODE (tem) == CONST_INT
8343 && 0 != (INTVAL (tem)
8344 & ((HOST_WIDE_INT) 1
8345 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8346 tem = GEN_INT (INTVAL (tem)
8347 | ((HOST_WIDE_INT) (-1)
8348 << GET_MODE_BITSIZE (GET_MODE (x))));
8350 return nonzero_bits_with_known (tem, mode) & nonzero;
8352 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8354 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8356 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8357 /* We don't know anything about the upper bits. */
8358 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8359 return nonzero & mask;
8365 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8366 /* If X is negative in MODE, sign-extend the value. */
8367 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8368 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8369 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8375 #ifdef LOAD_EXTEND_OP
8376 /* In many, if not most, RISC machines, reading a byte from memory
8377 zeros the rest of the register. Noticing that fact saves a lot
8378 of extra zero-extends. */
8379 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8380 nonzero &= GET_MODE_MASK (GET_MODE (x));
8385 case UNEQ: case LTGT:
8386 case GT: case GTU: case UNGT:
8387 case LT: case LTU: case UNLT:
8388 case GE: case GEU: case UNGE:
8389 case LE: case LEU: case UNLE:
8390 case UNORDERED: case ORDERED:
8392 /* If this produces an integer result, we know which bits are set.
8393 Code here used to clear bits outside the mode of X, but that is
8396 if (GET_MODE_CLASS (mode) == MODE_INT
8397 && mode_width <= HOST_BITS_PER_WIDE_INT)
8398 nonzero = STORE_FLAG_VALUE;
8403 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8404 and num_sign_bit_copies. */
8405 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8406 == GET_MODE_BITSIZE (GET_MODE (x)))
8410 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8411 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8416 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8417 and num_sign_bit_copies. */
8418 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8419 == GET_MODE_BITSIZE (GET_MODE (x)))
8425 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8426 & GET_MODE_MASK (mode));
8430 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8431 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8432 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8436 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8437 Otherwise, show all the bits in the outer mode but not the inner
8439 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8440 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8442 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8444 & (((HOST_WIDE_INT) 1
8445 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8446 inner_nz |= (GET_MODE_MASK (mode)
8447 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8450 nonzero &= inner_nz;
8454 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8455 & nonzero_bits_with_known (XEXP (x, 1), mode));
8459 case UMIN: case UMAX: case SMIN: case SMAX:
8461 unsigned HOST_WIDE_INT nonzero0 =
8462 nonzero_bits_with_known (XEXP (x, 0), mode);
8464 /* Don't call nonzero_bits for the second time if it cannot change
8466 if ((nonzero & nonzero0) != nonzero)
8467 nonzero &= (nonzero0
8468 | nonzero_bits_with_known (XEXP (x, 1), mode));
8472 case PLUS: case MINUS:
8474 case DIV: case UDIV:
8475 case MOD: case UMOD:
8476 /* We can apply the rules of arithmetic to compute the number of
8477 high- and low-order zero bits of these operations. We start by
8478 computing the width (position of the highest-order nonzero bit)
8479 and the number of low-order zero bits for each value. */
8481 unsigned HOST_WIDE_INT nz0 =
8482 nonzero_bits_with_known (XEXP (x, 0), mode);
8483 unsigned HOST_WIDE_INT nz1 =
8484 nonzero_bits_with_known (XEXP (x, 1), mode);
8485 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8486 int width0 = floor_log2 (nz0) + 1;
8487 int width1 = floor_log2 (nz1) + 1;
8488 int low0 = floor_log2 (nz0 & -nz0);
8489 int low1 = floor_log2 (nz1 & -nz1);
8490 HOST_WIDE_INT op0_maybe_minusp
8491 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8492 HOST_WIDE_INT op1_maybe_minusp
8493 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8494 unsigned int result_width = mode_width;
8500 result_width = MAX (width0, width1) + 1;
8501 result_low = MIN (low0, low1);
8504 result_low = MIN (low0, low1);
8507 result_width = width0 + width1;
8508 result_low = low0 + low1;
8513 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8514 result_width = width0;
8519 result_width = width0;
8524 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8525 result_width = MIN (width0, width1);
8526 result_low = MIN (low0, low1);
8531 result_width = MIN (width0, width1);
8532 result_low = MIN (low0, low1);
8538 if (result_width < mode_width)
8539 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8542 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8544 #ifdef POINTERS_EXTEND_UNSIGNED
8545 /* If pointers extend unsigned and this is an addition or subtraction
8546 to a pointer in Pmode, all the bits above ptr_mode are known to be
8548 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8549 && (code == PLUS || code == MINUS)
8550 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8551 nonzero &= GET_MODE_MASK (ptr_mode);
8557 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8558 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8559 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8563 /* If this is a SUBREG formed for a promoted variable that has
8564 been zero-extended, we know that at least the high-order bits
8565 are zero, though others might be too. */
8567 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8568 nonzero = (GET_MODE_MASK (GET_MODE (x))
8569 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8571 /* If the inner mode is a single word for both the host and target
8572 machines, we can compute this from which bits of the inner
8573 object might be nonzero. */
8574 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8575 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8576 <= HOST_BITS_PER_WIDE_INT))
8578 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8580 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8581 /* If this is a typical RISC machine, we only have to worry
8582 about the way loads are extended. */
8583 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8585 & (((unsigned HOST_WIDE_INT) 1
8586 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8588 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8589 || GET_CODE (SUBREG_REG (x)) != MEM)
8592 /* On many CISC machines, accessing an object in a wider mode
8593 causes the high-order bits to become undefined. So they are
8594 not known to be zero. */
8595 if (GET_MODE_SIZE (GET_MODE (x))
8596 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8597 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8598 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8607 /* The nonzero bits are in two classes: any bits within MODE
8608 that aren't in GET_MODE (x) are always significant. The rest of the
8609 nonzero bits are those that are significant in the operand of
8610 the shift when shifted the appropriate number of bits. This
8611 shows that high-order bits are cleared by the right shift and
8612 low-order bits by left shifts. */
8613 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8614 && INTVAL (XEXP (x, 1)) >= 0
8615 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8617 enum machine_mode inner_mode = GET_MODE (x);
8618 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8619 int count = INTVAL (XEXP (x, 1));
8620 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8621 unsigned HOST_WIDE_INT op_nonzero =
8622 nonzero_bits_with_known (XEXP (x, 0), mode);
8623 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8624 unsigned HOST_WIDE_INT outer = 0;
8626 if (mode_width > width)
8627 outer = (op_nonzero & nonzero & ~mode_mask);
8629 if (code == LSHIFTRT)
8631 else if (code == ASHIFTRT)
8635 /* If the sign bit may have been nonzero before the shift, we
8636 need to mark all the places it could have been copied to
8637 by the shift as possibly nonzero. */
8638 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8639 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8641 else if (code == ASHIFT)
8644 inner = ((inner << (count % width)
8645 | (inner >> (width - (count % width)))) & mode_mask);
8647 nonzero &= (outer | inner);
8653 /* This is at most the number of bits in the mode. */
8654 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8658 /* If CLZ has a known value at zero, then the nonzero bits are
8659 that value, plus the number of bits in the mode minus one. */
8660 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8661 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8667 /* If CTZ has a known value at zero, then the nonzero bits are
8668 that value, plus the number of bits in the mode minus one. */
8669 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8670 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8680 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8681 | nonzero_bits_with_known (XEXP (x, 2), mode));
8691 /* See the macro definition above. */
8692 #undef cached_num_sign_bit_copies
8694 #define num_sign_bit_copies_with_known(X, M) \
8695 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8697 /* The function cached_num_sign_bit_copies is a wrapper around
8698 num_sign_bit_copies1. It avoids exponential behavior in
8699 num_sign_bit_copies1 when X has identical subexpressions on the
8700 first or the second level. */
8703 cached_num_sign_bit_copies (x, mode, known_x, known_mode, known_ret)
8705 enum machine_mode mode;
8707 enum machine_mode known_mode;
8708 unsigned int known_ret;
8710 if (x == known_x && mode == known_mode)
8713 /* Try to find identical subexpressions. If found call
8714 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8715 the precomputed value for the subexpression as KNOWN_RET. */
8717 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8718 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8720 rtx x0 = XEXP (x, 0);
8721 rtx x1 = XEXP (x, 1);
8723 /* Check the first level. */
8726 num_sign_bit_copies1 (x, mode, x0, mode,
8727 num_sign_bit_copies_with_known (x0, mode));
8729 /* Check the second level. */
8730 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8731 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8732 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8734 num_sign_bit_copies1 (x, mode, x1, mode,
8735 num_sign_bit_copies_with_known (x1, mode));
8737 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8738 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8739 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8741 num_sign_bit_copies1 (x, mode, x0, mode,
8742 num_sign_bit_copies_with_known (x0, mode));
8745 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8748 /* Return the number of bits at the high-order end of X that are known to
8749 be equal to the sign bit. X will be used in mode MODE; if MODE is
8750 VOIDmode, X will be used in its own mode. The returned value will always
8751 be between 1 and the number of bits in MODE. */
8754 num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret)
8756 enum machine_mode mode;
8758 enum machine_mode known_mode;
8759 unsigned int known_ret;
8761 enum rtx_code code = GET_CODE (x);
8762 unsigned int bitwidth;
8763 int num0, num1, result;
8764 unsigned HOST_WIDE_INT nonzero;
8767 /* If we weren't given a mode, use the mode of X. If the mode is still
8768 VOIDmode, we don't know anything. Likewise if one of the modes is
8771 if (mode == VOIDmode)
8772 mode = GET_MODE (x);
8774 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8777 bitwidth = GET_MODE_BITSIZE (mode);
8779 /* For a smaller object, just ignore the high bits. */
8780 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8782 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8784 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8787 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8789 #ifndef WORD_REGISTER_OPERATIONS
8790 /* If this machine does not do all register operations on the entire
8791 register and MODE is wider than the mode of X, we can say nothing
8792 at all about the high-order bits. */
8795 /* Likewise on machines that do, if the mode of the object is smaller
8796 than a word and loads of that size don't sign extend, we can say
8797 nothing about the high order bits. */
8798 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8799 #ifdef LOAD_EXTEND_OP
8800 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8811 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8812 /* If pointers extend signed and this is a pointer in Pmode, say that
8813 all the bits above ptr_mode are known to be sign bit copies. */
8814 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8816 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8819 if (reg_last_set_value[REGNO (x)] != 0
8820 && reg_last_set_mode[REGNO (x)] == mode
8821 && (reg_last_set_label[REGNO (x)] == label_tick
8822 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8823 && REG_N_SETS (REGNO (x)) == 1
8824 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8826 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8827 return reg_last_set_sign_bit_copies[REGNO (x)];
8829 tem = get_last_value (x);
8831 return num_sign_bit_copies_with_known (tem, mode);
8833 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8834 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8835 return reg_sign_bit_copies[REGNO (x)];
8839 #ifdef LOAD_EXTEND_OP
8840 /* Some RISC machines sign-extend all loads of smaller than a word. */
8841 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8842 return MAX (1, ((int) bitwidth
8843 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8848 /* If the constant is negative, take its 1's complement and remask.
8849 Then see how many zero bits we have. */
8850 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8851 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8852 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8853 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8855 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8858 /* If this is a SUBREG for a promoted object that is sign-extended
8859 and we are looking at it in a wider mode, we know that at least the
8860 high-order bits are known to be sign bit copies. */
8862 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8864 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8865 return MAX ((int) bitwidth
8866 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8870 /* For a smaller object, just ignore the high bits. */
8871 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8873 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8874 return MAX (1, (num0
8875 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8879 #ifdef WORD_REGISTER_OPERATIONS
8880 #ifdef LOAD_EXTEND_OP
8881 /* For paradoxical SUBREGs on machines where all register operations
8882 affect the entire register, just look inside. Note that we are
8883 passing MODE to the recursive call, so the number of sign bit copies
8884 will remain relative to that mode, not the inner mode. */
8886 /* This works only if loads sign extend. Otherwise, if we get a
8887 reload for the inner part, it may be loaded from the stack, and
8888 then we lose all sign bit copies that existed before the store
8891 if ((GET_MODE_SIZE (GET_MODE (x))
8892 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8893 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8894 && GET_CODE (SUBREG_REG (x)) == MEM)
8895 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8901 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8902 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8906 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8907 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8910 /* For a smaller object, just ignore the high bits. */
8911 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8912 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8916 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8918 case ROTATE: case ROTATERT:
8919 /* If we are rotating left by a number of bits less than the number
8920 of sign bit copies, we can just subtract that amount from the
8922 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8923 && INTVAL (XEXP (x, 1)) >= 0
8924 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8926 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8927 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8928 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8933 /* In general, this subtracts one sign bit copy. But if the value
8934 is known to be positive, the number of sign bit copies is the
8935 same as that of the input. Finally, if the input has just one bit
8936 that might be nonzero, all the bits are copies of the sign bit. */
8937 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8938 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8939 return num0 > 1 ? num0 - 1 : 1;
8941 nonzero = nonzero_bits (XEXP (x, 0), mode);
8946 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8951 case IOR: case AND: case XOR:
8952 case SMIN: case SMAX: case UMIN: case UMAX:
8953 /* Logical operations will preserve the number of sign-bit copies.
8954 MIN and MAX operations always return one of the operands. */
8955 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8956 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8957 return MIN (num0, num1);
8959 case PLUS: case MINUS:
8960 /* For addition and subtraction, we can have a 1-bit carry. However,
8961 if we are subtracting 1 from a positive number, there will not
8962 be such a carry. Furthermore, if the positive number is known to
8963 be 0 or 1, we know the result is either -1 or 0. */
8965 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8966 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8968 nonzero = nonzero_bits (XEXP (x, 0), mode);
8969 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8970 return (nonzero == 1 || nonzero == 0 ? bitwidth
8971 : bitwidth - floor_log2 (nonzero) - 1);
8974 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8975 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8976 result = MAX (1, MIN (num0, num1) - 1);
8978 #ifdef POINTERS_EXTEND_UNSIGNED
8979 /* If pointers extend signed and this is an addition or subtraction
8980 to a pointer in Pmode, all the bits above ptr_mode are known to be
8982 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8983 && (code == PLUS || code == MINUS)
8984 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8985 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8986 - GET_MODE_BITSIZE (ptr_mode) + 1),
8992 /* The number of bits of the product is the sum of the number of
8993 bits of both terms. However, unless one of the terms if known
8994 to be positive, we must allow for an additional bit since negating
8995 a negative number can remove one sign bit copy. */
8997 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8998 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9000 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
9002 && (bitwidth > HOST_BITS_PER_WIDE_INT
9003 || (((nonzero_bits (XEXP (x, 0), mode)
9004 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9005 && ((nonzero_bits (XEXP (x, 1), mode)
9006 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
9009 return MAX (1, result);
9012 /* The result must be <= the first operand. If the first operand
9013 has the high bit set, we know nothing about the number of sign
9015 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9017 else if ((nonzero_bits (XEXP (x, 0), mode)
9018 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9021 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9024 /* The result must be <= the second operand. */
9025 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9028 /* Similar to unsigned division, except that we have to worry about
9029 the case where the divisor is negative, in which case we have
9031 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9033 && (bitwidth > HOST_BITS_PER_WIDE_INT
9034 || (nonzero_bits (XEXP (x, 1), mode)
9035 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
9041 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9043 && (bitwidth > HOST_BITS_PER_WIDE_INT
9044 || (nonzero_bits (XEXP (x, 1), mode)
9045 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
9051 /* Shifts by a constant add to the number of bits equal to the
9053 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9054 if (GET_CODE (XEXP (x, 1)) == CONST_INT
9055 && INTVAL (XEXP (x, 1)) > 0)
9056 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
9061 /* Left shifts destroy copies. */
9062 if (GET_CODE (XEXP (x, 1)) != CONST_INT
9063 || INTVAL (XEXP (x, 1)) < 0
9064 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
9067 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9068 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
9071 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9072 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
9073 return MIN (num0, num1);
9075 case EQ: case NE: case GE: case GT: case LE: case LT:
9076 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
9077 case GEU: case GTU: case LEU: case LTU:
9078 case UNORDERED: case ORDERED:
9079 /* If the constant is negative, take its 1's complement and remask.
9080 Then see how many zero bits we have. */
9081 nonzero = STORE_FLAG_VALUE;
9082 if (bitwidth <= HOST_BITS_PER_WIDE_INT
9083 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9084 nonzero = (~nonzero) & GET_MODE_MASK (mode);
9086 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
9093 /* If we haven't been able to figure it out by one of the above rules,
9094 see if some of the high-order bits are known to be zero. If so,
9095 count those bits and return one less than that amount. If we can't
9096 safely compute the mask for this mode, always return BITWIDTH. */
9098 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9101 nonzero = nonzero_bits (x, mode);
9102 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
9103 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
9106 /* Return the number of "extended" bits there are in X, when interpreted
9107 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9108 unsigned quantities, this is the number of high-order zero bits.
9109 For signed quantities, this is the number of copies of the sign bit
9110 minus 1. In both case, this function returns the number of "spare"
9111 bits. For example, if two quantities for which this function returns
9112 at least 1 are added, the addition is known not to overflow.
9114 This function will always return 0 unless called during combine, which
9115 implies that it must be called from a define_split. */
9118 extended_count (x, mode, unsignedp)
9120 enum machine_mode mode;
9123 if (nonzero_sign_valid == 0)
9127 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9128 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9129 - floor_log2 (nonzero_bits (x, mode)))
9131 : num_sign_bit_copies (x, mode) - 1);
9134 /* This function is called from `simplify_shift_const' to merge two
9135 outer operations. Specifically, we have already found that we need
9136 to perform operation *POP0 with constant *PCONST0 at the outermost
9137 position. We would now like to also perform OP1 with constant CONST1
9138 (with *POP0 being done last).
9140 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9141 the resulting operation. *PCOMP_P is set to 1 if we would need to
9142 complement the innermost operand, otherwise it is unchanged.
9144 MODE is the mode in which the operation will be done. No bits outside
9145 the width of this mode matter. It is assumed that the width of this mode
9146 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9148 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9149 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9150 result is simply *PCONST0.
9152 If the resulting operation cannot be expressed as one operation, we
9153 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9156 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
9157 enum rtx_code *pop0;
9158 HOST_WIDE_INT *pconst0;
9160 HOST_WIDE_INT const1;
9161 enum machine_mode mode;
9164 enum rtx_code op0 = *pop0;
9165 HOST_WIDE_INT const0 = *pconst0;
9167 const0 &= GET_MODE_MASK (mode);
9168 const1 &= GET_MODE_MASK (mode);
9170 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9174 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9177 if (op1 == NIL || op0 == SET)
9180 else if (op0 == NIL)
9181 op0 = op1, const0 = const1;
9183 else if (op0 == op1)
9207 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9208 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9211 /* If the two constants aren't the same, we can't do anything. The
9212 remaining six cases can all be done. */
9213 else if (const0 != const1)
9221 /* (a & b) | b == b */
9223 else /* op1 == XOR */
9224 /* (a ^ b) | b == a | b */
9230 /* (a & b) ^ b == (~a) & b */
9231 op0 = AND, *pcomp_p = 1;
9232 else /* op1 == IOR */
9233 /* (a | b) ^ b == a & ~b */
9234 op0 = AND, const0 = ~const0;
9239 /* (a | b) & b == b */
9241 else /* op1 == XOR */
9242 /* (a ^ b) & b) == (~a) & b */
9249 /* Check for NO-OP cases. */
9250 const0 &= GET_MODE_MASK (mode);
9252 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9254 else if (const0 == 0 && op0 == AND)
9256 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9260 /* ??? Slightly redundant with the above mask, but not entirely.
9261 Moving this above means we'd have to sign-extend the mode mask
9262 for the final test. */
9263 const0 = trunc_int_for_mode (const0, mode);
9271 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9272 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9273 that we started with.
9275 The shift is normally computed in the widest mode we find in VAROP, as
9276 long as it isn't a different number of words than RESULT_MODE. Exceptions
9277 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9280 simplify_shift_const (x, code, result_mode, varop, orig_count)
9283 enum machine_mode result_mode;
9287 enum rtx_code orig_code = code;
9290 enum machine_mode mode = result_mode;
9291 enum machine_mode shift_mode, tmode;
9292 unsigned int mode_words
9293 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9294 /* We form (outer_op (code varop count) (outer_const)). */
9295 enum rtx_code outer_op = NIL;
9296 HOST_WIDE_INT outer_const = 0;
9298 int complement_p = 0;
9301 /* Make sure and truncate the "natural" shift on the way in. We don't
9302 want to do this inside the loop as it makes it more difficult to
9304 #ifdef SHIFT_COUNT_TRUNCATED
9305 if (SHIFT_COUNT_TRUNCATED)
9306 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9309 /* If we were given an invalid count, don't do anything except exactly
9310 what was requested. */
9312 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9317 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9322 /* Unless one of the branches of the `if' in this loop does a `continue',
9323 we will `break' the loop after the `if'. */
9327 /* If we have an operand of (clobber (const_int 0)), just return that
9329 if (GET_CODE (varop) == CLOBBER)
9332 /* If we discovered we had to complement VAROP, leave. Making a NOT
9333 here would cause an infinite loop. */
9337 /* Convert ROTATERT to ROTATE. */
9338 if (code == ROTATERT)
9340 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9342 if (VECTOR_MODE_P (result_mode))
9343 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9345 count = bitsize - count;
9348 /* We need to determine what mode we will do the shift in. If the
9349 shift is a right shift or a ROTATE, we must always do it in the mode
9350 it was originally done in. Otherwise, we can do it in MODE, the
9351 widest mode encountered. */
9353 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9354 ? result_mode : mode);
9356 /* Handle cases where the count is greater than the size of the mode
9357 minus 1. For ASHIFT, use the size minus one as the count (this can
9358 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9359 take the count modulo the size. For other shifts, the result is
9362 Since these shifts are being produced by the compiler by combining
9363 multiple operations, each of which are defined, we know what the
9364 result is supposed to be. */
9366 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9368 if (code == ASHIFTRT)
9369 count = GET_MODE_BITSIZE (shift_mode) - 1;
9370 else if (code == ROTATE || code == ROTATERT)
9371 count %= GET_MODE_BITSIZE (shift_mode);
9374 /* We can't simply return zero because there may be an
9382 /* An arithmetic right shift of a quantity known to be -1 or 0
9384 if (code == ASHIFTRT
9385 && (num_sign_bit_copies (varop, shift_mode)
9386 == GET_MODE_BITSIZE (shift_mode)))
9392 /* If we are doing an arithmetic right shift and discarding all but
9393 the sign bit copies, this is equivalent to doing a shift by the
9394 bitsize minus one. Convert it into that shift because it will often
9395 allow other simplifications. */
9397 if (code == ASHIFTRT
9398 && (count + num_sign_bit_copies (varop, shift_mode)
9399 >= GET_MODE_BITSIZE (shift_mode)))
9400 count = GET_MODE_BITSIZE (shift_mode) - 1;
9402 /* We simplify the tests below and elsewhere by converting
9403 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9404 `make_compound_operation' will convert it to an ASHIFTRT for
9405 those machines (such as VAX) that don't have an LSHIFTRT. */
9406 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9408 && ((nonzero_bits (varop, shift_mode)
9409 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9413 if (code == LSHIFTRT
9414 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9415 && !(nonzero_bits (varop, shift_mode) >> count))
9418 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9419 && !((nonzero_bits (varop, shift_mode) << count)
9420 & GET_MODE_MASK (shift_mode)))
9423 switch (GET_CODE (varop))
9429 new = expand_compound_operation (varop);
9438 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9439 minus the width of a smaller mode, we can do this with a
9440 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9441 if ((code == ASHIFTRT || code == LSHIFTRT)
9442 && ! mode_dependent_address_p (XEXP (varop, 0))
9443 && ! MEM_VOLATILE_P (varop)
9444 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9445 MODE_INT, 1)) != BLKmode)
9447 new = adjust_address_nv (varop, tmode,
9448 BYTES_BIG_ENDIAN ? 0
9449 : count / BITS_PER_UNIT);
9451 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9452 : ZERO_EXTEND, mode, new);
9459 /* Similar to the case above, except that we can only do this if
9460 the resulting mode is the same as that of the underlying
9461 MEM and adjust the address depending on the *bits* endianness
9462 because of the way that bit-field extract insns are defined. */
9463 if ((code == ASHIFTRT || code == LSHIFTRT)
9464 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9465 MODE_INT, 1)) != BLKmode
9466 && tmode == GET_MODE (XEXP (varop, 0)))
9468 if (BITS_BIG_ENDIAN)
9469 new = XEXP (varop, 0);
9472 new = copy_rtx (XEXP (varop, 0));
9473 SUBST (XEXP (new, 0),
9474 plus_constant (XEXP (new, 0),
9475 count / BITS_PER_UNIT));
9478 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9479 : ZERO_EXTEND, mode, new);
9486 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9487 the same number of words as what we've seen so far. Then store
9488 the widest mode in MODE. */
9489 if (subreg_lowpart_p (varop)
9490 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9491 > GET_MODE_SIZE (GET_MODE (varop)))
9492 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9493 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9496 varop = SUBREG_REG (varop);
9497 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9498 mode = GET_MODE (varop);
9504 /* Some machines use MULT instead of ASHIFT because MULT
9505 is cheaper. But it is still better on those machines to
9506 merge two shifts into one. */
9507 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9508 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9511 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9512 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9518 /* Similar, for when divides are cheaper. */
9519 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9520 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9523 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9524 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9530 /* If we are extracting just the sign bit of an arithmetic
9531 right shift, that shift is not needed. However, the sign
9532 bit of a wider mode may be different from what would be
9533 interpreted as the sign bit in a narrower mode, so, if
9534 the result is narrower, don't discard the shift. */
9535 if (code == LSHIFTRT
9536 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9537 && (GET_MODE_BITSIZE (result_mode)
9538 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9540 varop = XEXP (varop, 0);
9544 /* ... fall through ... */
9549 /* Here we have two nested shifts. The result is usually the
9550 AND of a new shift with a mask. We compute the result below. */
9551 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9552 && INTVAL (XEXP (varop, 1)) >= 0
9553 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9554 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9555 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9557 enum rtx_code first_code = GET_CODE (varop);
9558 unsigned int first_count = INTVAL (XEXP (varop, 1));
9559 unsigned HOST_WIDE_INT mask;
9562 /* We have one common special case. We can't do any merging if
9563 the inner code is an ASHIFTRT of a smaller mode. However, if
9564 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9565 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9566 we can convert it to
9567 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9568 This simplifies certain SIGN_EXTEND operations. */
9569 if (code == ASHIFT && first_code == ASHIFTRT
9570 && count == (unsigned int)
9571 (GET_MODE_BITSIZE (result_mode)
9572 - GET_MODE_BITSIZE (GET_MODE (varop))))
9574 /* C3 has the low-order C1 bits zero. */
9576 mask = (GET_MODE_MASK (mode)
9577 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9579 varop = simplify_and_const_int (NULL_RTX, result_mode,
9580 XEXP (varop, 0), mask);
9581 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9583 count = first_count;
9588 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9589 than C1 high-order bits equal to the sign bit, we can convert
9590 this to either an ASHIFT or an ASHIFTRT depending on the
9593 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9595 if (code == ASHIFTRT && first_code == ASHIFT
9596 && GET_MODE (varop) == shift_mode
9597 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9600 varop = XEXP (varop, 0);
9602 signed_count = count - first_count;
9603 if (signed_count < 0)
9604 count = -signed_count, code = ASHIFT;
9606 count = signed_count;
9611 /* There are some cases we can't do. If CODE is ASHIFTRT,
9612 we can only do this if FIRST_CODE is also ASHIFTRT.
9614 We can't do the case when CODE is ROTATE and FIRST_CODE is
9617 If the mode of this shift is not the mode of the outer shift,
9618 we can't do this if either shift is a right shift or ROTATE.
9620 Finally, we can't do any of these if the mode is too wide
9621 unless the codes are the same.
9623 Handle the case where the shift codes are the same
9626 if (code == first_code)
9628 if (GET_MODE (varop) != result_mode
9629 && (code == ASHIFTRT || code == LSHIFTRT
9633 count += first_count;
9634 varop = XEXP (varop, 0);
9638 if (code == ASHIFTRT
9639 || (code == ROTATE && first_code == ASHIFTRT)
9640 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9641 || (GET_MODE (varop) != result_mode
9642 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9643 || first_code == ROTATE
9644 || code == ROTATE)))
9647 /* To compute the mask to apply after the shift, shift the
9648 nonzero bits of the inner shift the same way the
9649 outer shift will. */
9651 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9654 = simplify_binary_operation (code, result_mode, mask_rtx,
9657 /* Give up if we can't compute an outer operation to use. */
9659 || GET_CODE (mask_rtx) != CONST_INT
9660 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9662 result_mode, &complement_p))
9665 /* If the shifts are in the same direction, we add the
9666 counts. Otherwise, we subtract them. */
9667 signed_count = count;
9668 if ((code == ASHIFTRT || code == LSHIFTRT)
9669 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9670 signed_count += first_count;
9672 signed_count -= first_count;
9674 /* If COUNT is positive, the new shift is usually CODE,
9675 except for the two exceptions below, in which case it is
9676 FIRST_CODE. If the count is negative, FIRST_CODE should
9678 if (signed_count > 0
9679 && ((first_code == ROTATE && code == ASHIFT)
9680 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9681 code = first_code, count = signed_count;
9682 else if (signed_count < 0)
9683 code = first_code, count = -signed_count;
9685 count = signed_count;
9687 varop = XEXP (varop, 0);
9691 /* If we have (A << B << C) for any shift, we can convert this to
9692 (A << C << B). This wins if A is a constant. Only try this if
9693 B is not a constant. */
9695 else if (GET_CODE (varop) == code
9696 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9698 = simplify_binary_operation (code, mode,
9702 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9709 /* Make this fit the case below. */
9710 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9711 GEN_INT (GET_MODE_MASK (mode)));
9717 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9718 with C the size of VAROP - 1 and the shift is logical if
9719 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9720 we have an (le X 0) operation. If we have an arithmetic shift
9721 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9722 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9724 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9725 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9726 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9727 && (code == LSHIFTRT || code == ASHIFTRT)
9728 && count == (unsigned int)
9729 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9730 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9733 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9736 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9737 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9742 /* If we have (shift (logical)), move the logical to the outside
9743 to allow it to possibly combine with another logical and the
9744 shift to combine with another shift. This also canonicalizes to
9745 what a ZERO_EXTRACT looks like. Also, some machines have
9746 (and (shift)) insns. */
9748 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9749 && (new = simplify_binary_operation (code, result_mode,
9751 GEN_INT (count))) != 0
9752 && GET_CODE (new) == CONST_INT
9753 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9754 INTVAL (new), result_mode, &complement_p))
9756 varop = XEXP (varop, 0);
9760 /* If we can't do that, try to simplify the shift in each arm of the
9761 logical expression, make a new logical expression, and apply
9762 the inverse distributive law. */
9764 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9765 XEXP (varop, 0), count);
9766 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9767 XEXP (varop, 1), count);
9769 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9770 varop = apply_distributive_law (varop);
9777 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9778 says that the sign bit can be tested, FOO has mode MODE, C is
9779 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9780 that may be nonzero. */
9781 if (code == LSHIFTRT
9782 && XEXP (varop, 1) == const0_rtx
9783 && GET_MODE (XEXP (varop, 0)) == result_mode
9784 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9785 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9786 && ((STORE_FLAG_VALUE
9787 & ((HOST_WIDE_INT) 1
9788 < (GET_MODE_BITSIZE (result_mode) - 1))))
9789 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9790 && merge_outer_ops (&outer_op, &outer_const, XOR,
9791 (HOST_WIDE_INT) 1, result_mode,
9794 varop = XEXP (varop, 0);
9801 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9802 than the number of bits in the mode is equivalent to A. */
9803 if (code == LSHIFTRT
9804 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9805 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9807 varop = XEXP (varop, 0);
9812 /* NEG commutes with ASHIFT since it is multiplication. Move the
9813 NEG outside to allow shifts to combine. */
9815 && merge_outer_ops (&outer_op, &outer_const, NEG,
9816 (HOST_WIDE_INT) 0, result_mode,
9819 varop = XEXP (varop, 0);
9825 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9826 is one less than the number of bits in the mode is
9827 equivalent to (xor A 1). */
9828 if (code == LSHIFTRT
9829 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9830 && XEXP (varop, 1) == constm1_rtx
9831 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9832 && merge_outer_ops (&outer_op, &outer_const, XOR,
9833 (HOST_WIDE_INT) 1, result_mode,
9837 varop = XEXP (varop, 0);
9841 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9842 that might be nonzero in BAR are those being shifted out and those
9843 bits are known zero in FOO, we can replace the PLUS with FOO.
9844 Similarly in the other operand order. This code occurs when
9845 we are computing the size of a variable-size array. */
9847 if ((code == ASHIFTRT || code == LSHIFTRT)
9848 && count < HOST_BITS_PER_WIDE_INT
9849 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9850 && (nonzero_bits (XEXP (varop, 1), result_mode)
9851 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9853 varop = XEXP (varop, 0);
9856 else if ((code == ASHIFTRT || code == LSHIFTRT)
9857 && count < HOST_BITS_PER_WIDE_INT
9858 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9859 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9861 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9862 & nonzero_bits (XEXP (varop, 1),
9865 varop = XEXP (varop, 1);
9869 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9871 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9872 && (new = simplify_binary_operation (ASHIFT, result_mode,
9874 GEN_INT (count))) != 0
9875 && GET_CODE (new) == CONST_INT
9876 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9877 INTVAL (new), result_mode, &complement_p))
9879 varop = XEXP (varop, 0);
9885 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9886 with C the size of VAROP - 1 and the shift is logical if
9887 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9888 we have a (gt X 0) operation. If the shift is arithmetic with
9889 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9890 we have a (neg (gt X 0)) operation. */
9892 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9893 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9894 && count == (unsigned int)
9895 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9896 && (code == LSHIFTRT || code == ASHIFTRT)
9897 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9898 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9900 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9903 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9906 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9907 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9914 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9915 if the truncate does not affect the value. */
9916 if (code == LSHIFTRT
9917 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9918 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9919 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9920 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9921 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9923 rtx varop_inner = XEXP (varop, 0);
9926 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9927 XEXP (varop_inner, 0),
9929 (count + INTVAL (XEXP (varop_inner, 1))));
9930 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9943 /* We need to determine what mode to do the shift in. If the shift is
9944 a right shift or ROTATE, we must always do it in the mode it was
9945 originally done in. Otherwise, we can do it in MODE, the widest mode
9946 encountered. The code we care about is that of the shift that will
9947 actually be done, not the shift that was originally requested. */
9949 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9950 ? result_mode : mode);
9952 /* We have now finished analyzing the shift. The result should be
9953 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9954 OUTER_OP is non-NIL, it is an operation that needs to be applied
9955 to the result of the shift. OUTER_CONST is the relevant constant,
9956 but we must turn off all bits turned off in the shift.
9958 If we were passed a value for X, see if we can use any pieces of
9959 it. If not, make new rtx. */
9961 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9962 && GET_CODE (XEXP (x, 1)) == CONST_INT
9963 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9964 const_rtx = XEXP (x, 1);
9966 const_rtx = GEN_INT (count);
9968 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9969 && GET_MODE (XEXP (x, 0)) == shift_mode
9970 && SUBREG_REG (XEXP (x, 0)) == varop)
9971 varop = XEXP (x, 0);
9972 else if (GET_MODE (varop) != shift_mode)
9973 varop = gen_lowpart_for_combine (shift_mode, varop);
9975 /* If we can't make the SUBREG, try to return what we were given. */
9976 if (GET_CODE (varop) == CLOBBER)
9977 return x ? x : varop;
9979 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9983 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9985 /* If we have an outer operation and we just made a shift, it is
9986 possible that we could have simplified the shift were it not
9987 for the outer operation. So try to do the simplification
9990 if (outer_op != NIL && GET_CODE (x) == code
9991 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9992 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9993 INTVAL (XEXP (x, 1)));
9995 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9996 turn off all the bits that the shift would have turned off. */
9997 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9998 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9999 GET_MODE_MASK (result_mode) >> orig_count);
10001 /* Do the remainder of the processing in RESULT_MODE. */
10002 x = gen_lowpart_for_combine (result_mode, x);
10004 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10007 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10009 if (outer_op != NIL)
10011 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10012 outer_const = trunc_int_for_mode (outer_const, result_mode);
10014 if (outer_op == AND)
10015 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10016 else if (outer_op == SET)
10017 /* This means that we have determined that the result is
10018 equivalent to a constant. This should be rare. */
10019 x = GEN_INT (outer_const);
10020 else if (GET_RTX_CLASS (outer_op) == '1')
10021 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10023 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
10029 /* Like recog, but we receive the address of a pointer to a new pattern.
10030 We try to match the rtx that the pointer points to.
10031 If that fails, we may try to modify or replace the pattern,
10032 storing the replacement into the same pointer object.
10034 Modifications include deletion or addition of CLOBBERs.
10036 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10037 the CLOBBERs are placed.
10039 The value is the final insn code from the pattern ultimately matched,
10043 recog_for_combine (pnewpat, insn, pnotes)
10048 rtx pat = *pnewpat;
10049 int insn_code_number;
10050 int num_clobbers_to_add = 0;
10055 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10056 we use to indicate that something didn't match. If we find such a
10057 thing, force rejection. */
10058 if (GET_CODE (pat) == PARALLEL)
10059 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10060 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10061 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10064 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
10065 instruction for pattern recognition. */
10066 dummy_insn = shallow_copy_rtx (insn);
10067 PATTERN (dummy_insn) = pat;
10068 REG_NOTES (dummy_insn) = 0;
10070 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10072 /* If it isn't, there is the possibility that we previously had an insn
10073 that clobbered some register as a side effect, but the combined
10074 insn doesn't need to do that. So try once more without the clobbers
10075 unless this represents an ASM insn. */
10077 if (insn_code_number < 0 && ! check_asm_operands (pat)
10078 && GET_CODE (pat) == PARALLEL)
10082 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10083 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10086 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10090 SUBST_INT (XVECLEN (pat, 0), pos);
10093 pat = XVECEXP (pat, 0, 0);
10095 PATTERN (dummy_insn) = pat;
10096 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10099 /* Recognize all noop sets, these will be killed by followup pass. */
10100 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10101 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10103 /* If we had any clobbers to add, make a new pattern than contains
10104 them. Then check to make sure that all of them are dead. */
10105 if (num_clobbers_to_add)
10107 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10108 rtvec_alloc (GET_CODE (pat) == PARALLEL
10109 ? (XVECLEN (pat, 0)
10110 + num_clobbers_to_add)
10111 : num_clobbers_to_add + 1));
10113 if (GET_CODE (pat) == PARALLEL)
10114 for (i = 0; i < XVECLEN (pat, 0); i++)
10115 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10117 XVECEXP (newpat, 0, 0) = pat;
10119 add_clobbers (newpat, insn_code_number);
10121 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10122 i < XVECLEN (newpat, 0); i++)
10124 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
10125 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10127 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
10128 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10136 return insn_code_number;
10139 /* Like gen_lowpart but for use by combine. In combine it is not possible
10140 to create any new pseudoregs. However, it is safe to create
10141 invalid memory addresses, because combine will try to recognize
10142 them and all they will do is make the combine attempt fail.
10144 If for some reason this cannot do its job, an rtx
10145 (clobber (const_int 0)) is returned.
10146 An insn containing that will not be recognized. */
10151 gen_lowpart_for_combine (mode, x)
10152 enum machine_mode mode;
10157 if (GET_MODE (x) == mode)
10160 /* We can only support MODE being wider than a word if X is a
10161 constant integer or has a mode the same size. */
10163 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10164 && ! ((GET_MODE (x) == VOIDmode
10165 && (GET_CODE (x) == CONST_INT
10166 || GET_CODE (x) == CONST_DOUBLE))
10167 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10168 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10170 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10171 won't know what to do. So we will strip off the SUBREG here and
10172 process normally. */
10173 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10175 x = SUBREG_REG (x);
10176 if (GET_MODE (x) == mode)
10180 result = gen_lowpart_common (mode, x);
10181 #ifdef CANNOT_CHANGE_MODE_CLASS
10183 && GET_CODE (result) == SUBREG
10184 && GET_CODE (SUBREG_REG (result)) == REG
10185 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10186 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10188 + GET_MODE (result));
10194 if (GET_CODE (x) == MEM)
10198 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10200 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10201 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10203 /* If we want to refer to something bigger than the original memref,
10204 generate a perverse subreg instead. That will force a reload
10205 of the original memref X. */
10206 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10207 return gen_rtx_SUBREG (mode, x, 0);
10209 if (WORDS_BIG_ENDIAN)
10210 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10211 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10213 if (BYTES_BIG_ENDIAN)
10215 /* Adjust the address so that the address-after-the-data is
10217 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10218 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10221 return adjust_address_nv (x, mode, offset);
10224 /* If X is a comparison operator, rewrite it in a new mode. This
10225 probably won't match, but may allow further simplifications. */
10226 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10227 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10229 /* If we couldn't simplify X any other way, just enclose it in a
10230 SUBREG. Normally, this SUBREG won't match, but some patterns may
10231 include an explicit SUBREG or we may simplify it further in combine. */
10236 enum machine_mode sub_mode = GET_MODE (x);
10238 offset = subreg_lowpart_offset (mode, sub_mode);
10239 if (sub_mode == VOIDmode)
10241 sub_mode = int_mode_for_mode (mode);
10242 x = gen_lowpart_common (sub_mode, x);
10244 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10247 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10251 /* These routines make binary and unary operations by first seeing if they
10252 fold; if not, a new expression is allocated. */
10255 gen_binary (code, mode, op0, op1)
10256 enum rtx_code code;
10257 enum machine_mode mode;
10263 if (GET_RTX_CLASS (code) == 'c'
10264 && swap_commutative_operands_p (op0, op1))
10265 tem = op0, op0 = op1, op1 = tem;
10267 if (GET_RTX_CLASS (code) == '<')
10269 enum machine_mode op_mode = GET_MODE (op0);
10271 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10272 just (REL_OP X Y). */
10273 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10275 op1 = XEXP (op0, 1);
10276 op0 = XEXP (op0, 0);
10277 op_mode = GET_MODE (op0);
10280 if (op_mode == VOIDmode)
10281 op_mode = GET_MODE (op1);
10282 result = simplify_relational_operation (code, op_mode, op0, op1);
10285 result = simplify_binary_operation (code, mode, op0, op1);
10290 /* Put complex operands first and constants second. */
10291 if (GET_RTX_CLASS (code) == 'c'
10292 && swap_commutative_operands_p (op0, op1))
10293 return gen_rtx_fmt_ee (code, mode, op1, op0);
10295 /* If we are turning off bits already known off in OP0, we need not do
10297 else if (code == AND && GET_CODE (op1) == CONST_INT
10298 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10299 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10302 return gen_rtx_fmt_ee (code, mode, op0, op1);
10305 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10306 comparison code that will be tested.
10308 The result is a possibly different comparison code to use. *POP0 and
10309 *POP1 may be updated.
10311 It is possible that we might detect that a comparison is either always
10312 true or always false. However, we do not perform general constant
10313 folding in combine, so this knowledge isn't useful. Such tautologies
10314 should have been detected earlier. Hence we ignore all such cases. */
10316 static enum rtx_code
10317 simplify_comparison (code, pop0, pop1)
10318 enum rtx_code code;
10326 enum machine_mode mode, tmode;
10328 /* Try a few ways of applying the same transformation to both operands. */
10331 #ifndef WORD_REGISTER_OPERATIONS
10332 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10333 so check specially. */
10334 if (code != GTU && code != GEU && code != LTU && code != LEU
10335 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10336 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10337 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10338 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10339 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10340 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10341 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10342 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10343 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10344 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10345 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10346 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10347 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10348 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10349 && (INTVAL (XEXP (op0, 1))
10350 == (GET_MODE_BITSIZE (GET_MODE (op0))
10351 - (GET_MODE_BITSIZE
10352 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10354 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10355 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10359 /* If both operands are the same constant shift, see if we can ignore the
10360 shift. We can if the shift is a rotate or if the bits shifted out of
10361 this shift are known to be zero for both inputs and if the type of
10362 comparison is compatible with the shift. */
10363 if (GET_CODE (op0) == GET_CODE (op1)
10364 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10365 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10366 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10367 && (code != GT && code != LT && code != GE && code != LE))
10368 || (GET_CODE (op0) == ASHIFTRT
10369 && (code != GTU && code != LTU
10370 && code != GEU && code != LEU)))
10371 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10372 && INTVAL (XEXP (op0, 1)) >= 0
10373 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10374 && XEXP (op0, 1) == XEXP (op1, 1))
10376 enum machine_mode mode = GET_MODE (op0);
10377 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10378 int shift_count = INTVAL (XEXP (op0, 1));
10380 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10381 mask &= (mask >> shift_count) << shift_count;
10382 else if (GET_CODE (op0) == ASHIFT)
10383 mask = (mask & (mask << shift_count)) >> shift_count;
10385 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10386 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10387 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10392 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10393 SUBREGs are of the same mode, and, in both cases, the AND would
10394 be redundant if the comparison was done in the narrower mode,
10395 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10396 and the operand's possibly nonzero bits are 0xffffff01; in that case
10397 if we only care about QImode, we don't need the AND). This case
10398 occurs if the output mode of an scc insn is not SImode and
10399 STORE_FLAG_VALUE == 1 (e.g., the 386).
10401 Similarly, check for a case where the AND's are ZERO_EXTEND
10402 operations from some narrower mode even though a SUBREG is not
10405 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10406 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10407 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10409 rtx inner_op0 = XEXP (op0, 0);
10410 rtx inner_op1 = XEXP (op1, 0);
10411 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10412 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10415 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10416 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10417 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10418 && (GET_MODE (SUBREG_REG (inner_op0))
10419 == GET_MODE (SUBREG_REG (inner_op1)))
10420 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10421 <= HOST_BITS_PER_WIDE_INT)
10422 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10423 GET_MODE (SUBREG_REG (inner_op0)))))
10424 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10425 GET_MODE (SUBREG_REG (inner_op1))))))
10427 op0 = SUBREG_REG (inner_op0);
10428 op1 = SUBREG_REG (inner_op1);
10430 /* The resulting comparison is always unsigned since we masked
10431 off the original sign bit. */
10432 code = unsigned_condition (code);
10438 for (tmode = GET_CLASS_NARROWEST_MODE
10439 (GET_MODE_CLASS (GET_MODE (op0)));
10440 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10441 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10443 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10444 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10445 code = unsigned_condition (code);
10454 /* If both operands are NOT, we can strip off the outer operation
10455 and adjust the comparison code for swapped operands; similarly for
10456 NEG, except that this must be an equality comparison. */
10457 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10458 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10459 && (code == EQ || code == NE)))
10460 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10466 /* If the first operand is a constant, swap the operands and adjust the
10467 comparison code appropriately, but don't do this if the second operand
10468 is already a constant integer. */
10469 if (swap_commutative_operands_p (op0, op1))
10471 tem = op0, op0 = op1, op1 = tem;
10472 code = swap_condition (code);
10475 /* We now enter a loop during which we will try to simplify the comparison.
10476 For the most part, we only are concerned with comparisons with zero,
10477 but some things may really be comparisons with zero but not start
10478 out looking that way. */
10480 while (GET_CODE (op1) == CONST_INT)
10482 enum machine_mode mode = GET_MODE (op0);
10483 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10484 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10485 int equality_comparison_p;
10486 int sign_bit_comparison_p;
10487 int unsigned_comparison_p;
10488 HOST_WIDE_INT const_op;
10490 /* We only want to handle integral modes. This catches VOIDmode,
10491 CCmode, and the floating-point modes. An exception is that we
10492 can handle VOIDmode if OP0 is a COMPARE or a comparison
10495 if (GET_MODE_CLASS (mode) != MODE_INT
10496 && ! (mode == VOIDmode
10497 && (GET_CODE (op0) == COMPARE
10498 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10501 /* Get the constant we are comparing against and turn off all bits
10502 not on in our mode. */
10503 const_op = INTVAL (op1);
10504 if (mode != VOIDmode)
10505 const_op = trunc_int_for_mode (const_op, mode);
10506 op1 = GEN_INT (const_op);
10508 /* If we are comparing against a constant power of two and the value
10509 being compared can only have that single bit nonzero (e.g., it was
10510 `and'ed with that bit), we can replace this with a comparison
10513 && (code == EQ || code == NE || code == GE || code == GEU
10514 || code == LT || code == LTU)
10515 && mode_width <= HOST_BITS_PER_WIDE_INT
10516 && exact_log2 (const_op) >= 0
10517 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10519 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10520 op1 = const0_rtx, const_op = 0;
10523 /* Similarly, if we are comparing a value known to be either -1 or
10524 0 with -1, change it to the opposite comparison against zero. */
10527 && (code == EQ || code == NE || code == GT || code == LE
10528 || code == GEU || code == LTU)
10529 && num_sign_bit_copies (op0, mode) == mode_width)
10531 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10532 op1 = const0_rtx, const_op = 0;
10535 /* Do some canonicalizations based on the comparison code. We prefer
10536 comparisons against zero and then prefer equality comparisons.
10537 If we can reduce the size of a constant, we will do that too. */
10542 /* < C is equivalent to <= (C - 1) */
10546 op1 = GEN_INT (const_op);
10548 /* ... fall through to LE case below. */
10554 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10558 op1 = GEN_INT (const_op);
10562 /* If we are doing a <= 0 comparison on a value known to have
10563 a zero sign bit, we can replace this with == 0. */
10564 else if (const_op == 0
10565 && mode_width <= HOST_BITS_PER_WIDE_INT
10566 && (nonzero_bits (op0, mode)
10567 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10572 /* >= C is equivalent to > (C - 1). */
10576 op1 = GEN_INT (const_op);
10578 /* ... fall through to GT below. */
10584 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10588 op1 = GEN_INT (const_op);
10592 /* If we are doing a > 0 comparison on a value known to have
10593 a zero sign bit, we can replace this with != 0. */
10594 else if (const_op == 0
10595 && mode_width <= HOST_BITS_PER_WIDE_INT
10596 && (nonzero_bits (op0, mode)
10597 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10602 /* < C is equivalent to <= (C - 1). */
10606 op1 = GEN_INT (const_op);
10608 /* ... fall through ... */
10611 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10612 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10613 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10615 const_op = 0, op1 = const0_rtx;
10623 /* unsigned <= 0 is equivalent to == 0 */
10627 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10628 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10629 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10631 const_op = 0, op1 = const0_rtx;
10637 /* >= C is equivalent to < (C - 1). */
10641 op1 = GEN_INT (const_op);
10643 /* ... fall through ... */
10646 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10647 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10648 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10650 const_op = 0, op1 = const0_rtx;
10658 /* unsigned > 0 is equivalent to != 0 */
10662 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10663 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10664 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10666 const_op = 0, op1 = const0_rtx;
10675 /* Compute some predicates to simplify code below. */
10677 equality_comparison_p = (code == EQ || code == NE);
10678 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10679 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10682 /* If this is a sign bit comparison and we can do arithmetic in
10683 MODE, say that we will only be needing the sign bit of OP0. */
10684 if (sign_bit_comparison_p
10685 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10686 op0 = force_to_mode (op0, mode,
10688 << (GET_MODE_BITSIZE (mode) - 1)),
10691 /* Now try cases based on the opcode of OP0. If none of the cases
10692 does a "continue", we exit this loop immediately after the
10695 switch (GET_CODE (op0))
10698 /* If we are extracting a single bit from a variable position in
10699 a constant that has only a single bit set and are comparing it
10700 with zero, we can convert this into an equality comparison
10701 between the position and the location of the single bit. */
10703 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10704 && XEXP (op0, 1) == const1_rtx
10705 && equality_comparison_p && const_op == 0
10706 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10708 if (BITS_BIG_ENDIAN)
10710 enum machine_mode new_mode
10711 = mode_for_extraction (EP_extzv, 1);
10712 if (new_mode == MAX_MACHINE_MODE)
10713 i = BITS_PER_WORD - 1 - i;
10717 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10721 op0 = XEXP (op0, 2);
10725 /* Result is nonzero iff shift count is equal to I. */
10726 code = reverse_condition (code);
10730 /* ... fall through ... */
10733 tem = expand_compound_operation (op0);
10742 /* If testing for equality, we can take the NOT of the constant. */
10743 if (equality_comparison_p
10744 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10746 op0 = XEXP (op0, 0);
10751 /* If just looking at the sign bit, reverse the sense of the
10753 if (sign_bit_comparison_p)
10755 op0 = XEXP (op0, 0);
10756 code = (code == GE ? LT : GE);
10762 /* If testing for equality, we can take the NEG of the constant. */
10763 if (equality_comparison_p
10764 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10766 op0 = XEXP (op0, 0);
10771 /* The remaining cases only apply to comparisons with zero. */
10775 /* When X is ABS or is known positive,
10776 (neg X) is < 0 if and only if X != 0. */
10778 if (sign_bit_comparison_p
10779 && (GET_CODE (XEXP (op0, 0)) == ABS
10780 || (mode_width <= HOST_BITS_PER_WIDE_INT
10781 && (nonzero_bits (XEXP (op0, 0), mode)
10782 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10784 op0 = XEXP (op0, 0);
10785 code = (code == LT ? NE : EQ);
10789 /* If we have NEG of something whose two high-order bits are the
10790 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10791 if (num_sign_bit_copies (op0, mode) >= 2)
10793 op0 = XEXP (op0, 0);
10794 code = swap_condition (code);
10800 /* If we are testing equality and our count is a constant, we
10801 can perform the inverse operation on our RHS. */
10802 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10803 && (tem = simplify_binary_operation (ROTATERT, mode,
10804 op1, XEXP (op0, 1))) != 0)
10806 op0 = XEXP (op0, 0);
10811 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10812 a particular bit. Convert it to an AND of a constant of that
10813 bit. This will be converted into a ZERO_EXTRACT. */
10814 if (const_op == 0 && sign_bit_comparison_p
10815 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10816 && mode_width <= HOST_BITS_PER_WIDE_INT)
10818 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10821 - INTVAL (XEXP (op0, 1)))));
10822 code = (code == LT ? NE : EQ);
10826 /* Fall through. */
10829 /* ABS is ignorable inside an equality comparison with zero. */
10830 if (const_op == 0 && equality_comparison_p)
10832 op0 = XEXP (op0, 0);
10838 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10839 to (compare FOO CONST) if CONST fits in FOO's mode and we
10840 are either testing inequality or have an unsigned comparison
10841 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10842 if (! unsigned_comparison_p
10843 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10844 <= HOST_BITS_PER_WIDE_INT)
10845 && ((unsigned HOST_WIDE_INT) const_op
10846 < (((unsigned HOST_WIDE_INT) 1
10847 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10849 op0 = XEXP (op0, 0);
10855 /* Check for the case where we are comparing A - C1 with C2,
10856 both constants are smaller than 1/2 the maximum positive
10857 value in MODE, and the comparison is equality or unsigned.
10858 In that case, if A is either zero-extended to MODE or has
10859 sufficient sign bits so that the high-order bit in MODE
10860 is a copy of the sign in the inner mode, we can prove that it is
10861 safe to do the operation in the wider mode. This simplifies
10862 many range checks. */
10864 if (mode_width <= HOST_BITS_PER_WIDE_INT
10865 && subreg_lowpart_p (op0)
10866 && GET_CODE (SUBREG_REG (op0)) == PLUS
10867 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10868 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10869 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10870 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10871 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10872 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10873 GET_MODE (SUBREG_REG (op0)))
10874 & ~GET_MODE_MASK (mode))
10875 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10876 GET_MODE (SUBREG_REG (op0)))
10878 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10879 - GET_MODE_BITSIZE (mode)))))
10881 op0 = SUBREG_REG (op0);
10885 /* If the inner mode is narrower and we are extracting the low part,
10886 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10887 if (subreg_lowpart_p (op0)
10888 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10889 /* Fall through */ ;
10893 /* ... fall through ... */
10896 if ((unsigned_comparison_p || equality_comparison_p)
10897 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10898 <= HOST_BITS_PER_WIDE_INT)
10899 && ((unsigned HOST_WIDE_INT) const_op
10900 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10902 op0 = XEXP (op0, 0);
10908 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10909 this for equality comparisons due to pathological cases involving
10911 if (equality_comparison_p
10912 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10913 op1, XEXP (op0, 1))))
10915 op0 = XEXP (op0, 0);
10920 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10921 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10922 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10924 op0 = XEXP (XEXP (op0, 0), 0);
10925 code = (code == LT ? EQ : NE);
10931 /* We used to optimize signed comparisons against zero, but that
10932 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10933 arrive here as equality comparisons, or (GEU, LTU) are
10934 optimized away. No need to special-case them. */
10936 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10937 (eq B (minus A C)), whichever simplifies. We can only do
10938 this for equality comparisons due to pathological cases involving
10940 if (equality_comparison_p
10941 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10942 XEXP (op0, 1), op1)))
10944 op0 = XEXP (op0, 0);
10949 if (equality_comparison_p
10950 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10951 XEXP (op0, 0), op1)))
10953 op0 = XEXP (op0, 1);
10958 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10959 of bits in X minus 1, is one iff X > 0. */
10960 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10961 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10962 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10964 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10966 op0 = XEXP (op0, 1);
10967 code = (code == GE ? LE : GT);
10973 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10974 if C is zero or B is a constant. */
10975 if (equality_comparison_p
10976 && 0 != (tem = simplify_binary_operation (XOR, mode,
10977 XEXP (op0, 1), op1)))
10979 op0 = XEXP (op0, 0);
10986 case UNEQ: case LTGT:
10987 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10988 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10989 case UNORDERED: case ORDERED:
10990 /* We can't do anything if OP0 is a condition code value, rather
10991 than an actual data value. */
10993 || CC0_P (XEXP (op0, 0))
10994 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10997 /* Get the two operands being compared. */
10998 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10999 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11001 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11003 /* Check for the cases where we simply want the result of the
11004 earlier test or the opposite of that result. */
11005 if (code == NE || code == EQ
11006 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11007 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11008 && (STORE_FLAG_VALUE
11009 & (((HOST_WIDE_INT) 1
11010 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11011 && (code == LT || code == GE)))
11013 enum rtx_code new_code;
11014 if (code == LT || code == NE)
11015 new_code = GET_CODE (op0);
11017 new_code = combine_reversed_comparison_code (op0);
11019 if (new_code != UNKNOWN)
11030 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11032 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11033 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11034 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11036 op0 = XEXP (op0, 1);
11037 code = (code == GE ? GT : LE);
11043 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11044 will be converted to a ZERO_EXTRACT later. */
11045 if (const_op == 0 && equality_comparison_p
11046 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11047 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11049 op0 = simplify_and_const_int
11050 (op0, mode, gen_rtx_LSHIFTRT (mode,
11052 XEXP (XEXP (op0, 0), 1)),
11053 (HOST_WIDE_INT) 1);
11057 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11058 zero and X is a comparison and C1 and C2 describe only bits set
11059 in STORE_FLAG_VALUE, we can compare with X. */
11060 if (const_op == 0 && equality_comparison_p
11061 && mode_width <= HOST_BITS_PER_WIDE_INT
11062 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11063 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11064 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11065 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11066 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11068 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11069 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11070 if ((~STORE_FLAG_VALUE & mask) == 0
11071 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
11072 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11073 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
11075 op0 = XEXP (XEXP (op0, 0), 0);
11080 /* If we are doing an equality comparison of an AND of a bit equal
11081 to the sign bit, replace this with a LT or GE comparison of
11082 the underlying value. */
11083 if (equality_comparison_p
11085 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11086 && mode_width <= HOST_BITS_PER_WIDE_INT
11087 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11088 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11090 op0 = XEXP (op0, 0);
11091 code = (code == EQ ? GE : LT);
11095 /* If this AND operation is really a ZERO_EXTEND from a narrower
11096 mode, the constant fits within that mode, and this is either an
11097 equality or unsigned comparison, try to do this comparison in
11098 the narrower mode. */
11099 if ((equality_comparison_p || unsigned_comparison_p)
11100 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11101 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11102 & GET_MODE_MASK (mode))
11104 && const_op >> i == 0
11105 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
11107 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
11111 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11112 fits in both M1 and M2 and the SUBREG is either paradoxical
11113 or represents the low part, permute the SUBREG and the AND
11115 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11117 unsigned HOST_WIDE_INT c1;
11118 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11119 /* Require an integral mode, to avoid creating something like
11121 if (SCALAR_INT_MODE_P (tmode)
11122 /* It is unsafe to commute the AND into the SUBREG if the
11123 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11124 not defined. As originally written the upper bits
11125 have a defined value due to the AND operation.
11126 However, if we commute the AND inside the SUBREG then
11127 they no longer have defined values and the meaning of
11128 the code has been changed. */
11130 #ifdef WORD_REGISTER_OPERATIONS
11131 || (mode_width > GET_MODE_BITSIZE (tmode)
11132 && mode_width <= BITS_PER_WORD)
11134 || (mode_width <= GET_MODE_BITSIZE (tmode)
11135 && subreg_lowpart_p (XEXP (op0, 0))))
11136 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11137 && mode_width <= HOST_BITS_PER_WIDE_INT
11138 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11139 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11140 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11142 && c1 != GET_MODE_MASK (tmode))
11144 op0 = gen_binary (AND, tmode,
11145 SUBREG_REG (XEXP (op0, 0)),
11146 gen_int_mode (c1, tmode));
11147 op0 = gen_lowpart_for_combine (mode, op0);
11152 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11153 (eq (and (lshiftrt X) 1) 0). */
11154 if (const_op == 0 && equality_comparison_p
11155 && XEXP (op0, 1) == const1_rtx
11156 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11157 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
11159 op0 = simplify_and_const_int
11161 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
11162 XEXP (XEXP (op0, 0), 1)),
11163 (HOST_WIDE_INT) 1);
11164 code = (code == NE ? EQ : NE);
11170 /* If we have (compare (ashift FOO N) (const_int C)) and
11171 the high order N bits of FOO (N+1 if an inequality comparison)
11172 are known to be zero, we can do this by comparing FOO with C
11173 shifted right N bits so long as the low-order N bits of C are
11175 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11176 && INTVAL (XEXP (op0, 1)) >= 0
11177 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11178 < HOST_BITS_PER_WIDE_INT)
11180 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11181 && mode_width <= HOST_BITS_PER_WIDE_INT
11182 && (nonzero_bits (XEXP (op0, 0), mode)
11183 & ~(mask >> (INTVAL (XEXP (op0, 1))
11184 + ! equality_comparison_p))) == 0)
11186 /* We must perform a logical shift, not an arithmetic one,
11187 as we want the top N bits of C to be zero. */
11188 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11190 temp >>= INTVAL (XEXP (op0, 1));
11191 op1 = gen_int_mode (temp, mode);
11192 op0 = XEXP (op0, 0);
11196 /* If we are doing a sign bit comparison, it means we are testing
11197 a particular bit. Convert it to the appropriate AND. */
11198 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11199 && mode_width <= HOST_BITS_PER_WIDE_INT)
11201 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11204 - INTVAL (XEXP (op0, 1)))));
11205 code = (code == LT ? NE : EQ);
11209 /* If this an equality comparison with zero and we are shifting
11210 the low bit to the sign bit, we can convert this to an AND of the
11212 if (const_op == 0 && equality_comparison_p
11213 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11214 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11217 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11218 (HOST_WIDE_INT) 1);
11224 /* If this is an equality comparison with zero, we can do this
11225 as a logical shift, which might be much simpler. */
11226 if (equality_comparison_p && const_op == 0
11227 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11229 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11231 INTVAL (XEXP (op0, 1)));
11235 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11236 do the comparison in a narrower mode. */
11237 if (! unsigned_comparison_p
11238 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11239 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11240 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11241 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11242 MODE_INT, 1)) != BLKmode
11243 && (((unsigned HOST_WIDE_INT) const_op
11244 + (GET_MODE_MASK (tmode) >> 1) + 1)
11245 <= GET_MODE_MASK (tmode)))
11247 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11251 /* Likewise if OP0 is a PLUS of a sign extension with a
11252 constant, which is usually represented with the PLUS
11253 between the shifts. */
11254 if (! unsigned_comparison_p
11255 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11256 && GET_CODE (XEXP (op0, 0)) == PLUS
11257 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11258 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11259 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11260 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11261 MODE_INT, 1)) != BLKmode
11262 && (((unsigned HOST_WIDE_INT) const_op
11263 + (GET_MODE_MASK (tmode) >> 1) + 1)
11264 <= GET_MODE_MASK (tmode)))
11266 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11267 rtx add_const = XEXP (XEXP (op0, 0), 1);
11268 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11271 op0 = gen_binary (PLUS, tmode,
11272 gen_lowpart_for_combine (tmode, inner),
11277 /* ... fall through ... */
11279 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11280 the low order N bits of FOO are known to be zero, we can do this
11281 by comparing FOO with C shifted left N bits so long as no
11282 overflow occurs. */
11283 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11284 && INTVAL (XEXP (op0, 1)) >= 0
11285 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11286 && mode_width <= HOST_BITS_PER_WIDE_INT
11287 && (nonzero_bits (XEXP (op0, 0), mode)
11288 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11289 && (((unsigned HOST_WIDE_INT) const_op
11290 + (GET_CODE (op0) != LSHIFTRT
11291 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11294 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11296 /* If the shift was logical, then we must make the condition
11298 if (GET_CODE (op0) == LSHIFTRT)
11299 code = unsigned_condition (code);
11301 const_op <<= INTVAL (XEXP (op0, 1));
11302 op1 = GEN_INT (const_op);
11303 op0 = XEXP (op0, 0);
11307 /* If we are using this shift to extract just the sign bit, we
11308 can replace this with an LT or GE comparison. */
11310 && (equality_comparison_p || sign_bit_comparison_p)
11311 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11312 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11315 op0 = XEXP (op0, 0);
11316 code = (code == NE || code == GT ? LT : GE);
11328 /* Now make any compound operations involved in this comparison. Then,
11329 check for an outmost SUBREG on OP0 that is not doing anything or is
11330 paradoxical. The latter transformation must only be performed when
11331 it is known that the "extra" bits will be the same in op0 and op1 or
11332 that they don't matter. There are three cases to consider:
11334 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11335 care bits and we can assume they have any convenient value. So
11336 making the transformation is safe.
11338 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11339 In this case the upper bits of op0 are undefined. We should not make
11340 the simplification in that case as we do not know the contents of
11343 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11344 NIL. In that case we know those bits are zeros or ones. We must
11345 also be sure that they are the same as the upper bits of op1.
11347 We can never remove a SUBREG for a non-equality comparison because
11348 the sign bit is in a different place in the underlying object. */
11350 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11351 op1 = make_compound_operation (op1, SET);
11353 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11354 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11356 && GET_CODE (SUBREG_REG (op0)) == REG
11357 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11358 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11359 && (code == NE || code == EQ))
11361 if (GET_MODE_SIZE (GET_MODE (op0))
11362 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11364 op0 = SUBREG_REG (op0);
11365 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11367 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11368 <= HOST_BITS_PER_WIDE_INT)
11369 && (nonzero_bits (SUBREG_REG (op0),
11370 GET_MODE (SUBREG_REG (op0)))
11371 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11373 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11375 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11376 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11377 op0 = SUBREG_REG (op0), op1 = tem;
11381 /* We now do the opposite procedure: Some machines don't have compare
11382 insns in all modes. If OP0's mode is an integer mode smaller than a
11383 word and we can't do a compare in that mode, see if there is a larger
11384 mode for which we can do the compare. There are a number of cases in
11385 which we can use the wider mode. */
11387 mode = GET_MODE (op0);
11388 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11389 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11390 && ! have_insn_for (COMPARE, mode))
11391 for (tmode = GET_MODE_WIDER_MODE (mode);
11393 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11394 tmode = GET_MODE_WIDER_MODE (tmode))
11395 if (have_insn_for (COMPARE, tmode))
11399 /* If the only nonzero bits in OP0 and OP1 are those in the
11400 narrower mode and this is an equality or unsigned comparison,
11401 we can use the wider mode. Similarly for sign-extended
11402 values, in which case it is true for all comparisons. */
11403 zero_extended = ((code == EQ || code == NE
11404 || code == GEU || code == GTU
11405 || code == LEU || code == LTU)
11406 && (nonzero_bits (op0, tmode)
11407 & ~GET_MODE_MASK (mode)) == 0
11408 && ((GET_CODE (op1) == CONST_INT
11409 || (nonzero_bits (op1, tmode)
11410 & ~GET_MODE_MASK (mode)) == 0)));
11413 || ((num_sign_bit_copies (op0, tmode)
11414 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11415 - GET_MODE_BITSIZE (mode)))
11416 && (num_sign_bit_copies (op1, tmode)
11417 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11418 - GET_MODE_BITSIZE (mode)))))
11420 /* If OP0 is an AND and we don't have an AND in MODE either,
11421 make a new AND in the proper mode. */
11422 if (GET_CODE (op0) == AND
11423 && !have_insn_for (AND, mode))
11424 op0 = gen_binary (AND, tmode,
11425 gen_lowpart_for_combine (tmode,
11427 gen_lowpart_for_combine (tmode,
11430 op0 = gen_lowpart_for_combine (tmode, op0);
11431 if (zero_extended && GET_CODE (op1) == CONST_INT)
11432 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11433 op1 = gen_lowpart_for_combine (tmode, op1);
11437 /* If this is a test for negative, we can make an explicit
11438 test of the sign bit. */
11440 if (op1 == const0_rtx && (code == LT || code == GE)
11441 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11443 op0 = gen_binary (AND, tmode,
11444 gen_lowpart_for_combine (tmode, op0),
11445 GEN_INT ((HOST_WIDE_INT) 1
11446 << (GET_MODE_BITSIZE (mode) - 1)));
11447 code = (code == LT) ? NE : EQ;
11452 #ifdef CANONICALIZE_COMPARISON
11453 /* If this machine only supports a subset of valid comparisons, see if we
11454 can convert an unsupported one into a supported one. */
11455 CANONICALIZE_COMPARISON (code, op0, op1);
11464 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11465 searching backward. */
11466 static enum rtx_code
11467 combine_reversed_comparison_code (exp)
11470 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11473 if (code1 != UNKNOWN
11474 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11476 /* Otherwise try and find where the condition codes were last set and
11478 x = get_last_value (XEXP (exp, 0));
11479 if (!x || GET_CODE (x) != COMPARE)
11481 return reversed_comparison_code_parts (GET_CODE (exp),
11482 XEXP (x, 0), XEXP (x, 1), NULL);
11485 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11486 Return NULL_RTX in case we fail to do the reversal. */
11488 reversed_comparison (exp, mode, op0, op1)
11490 enum machine_mode mode;
11492 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11493 if (reversed_code == UNKNOWN)
11496 return gen_binary (reversed_code, mode, op0, op1);
11499 /* Utility function for following routine. Called when X is part of a value
11500 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11501 for each register mentioned. Similar to mention_regs in cse.c */
11504 update_table_tick (x)
11507 enum rtx_code code = GET_CODE (x);
11508 const char *fmt = GET_RTX_FORMAT (code);
11513 unsigned int regno = REGNO (x);
11514 unsigned int endregno
11515 = regno + (regno < FIRST_PSEUDO_REGISTER
11516 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11519 for (r = regno; r < endregno; r++)
11520 reg_last_set_table_tick[r] = label_tick;
11525 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11526 /* Note that we can't have an "E" in values stored; see
11527 get_last_value_validate. */
11530 /* Check for identical subexpressions. If x contains
11531 identical subexpression we only have to traverse one of
11534 && (GET_RTX_CLASS (code) == '2'
11535 || GET_RTX_CLASS (code) == 'c'))
11537 /* Note that at this point x1 has already been
11539 rtx x0 = XEXP (x, 0);
11540 rtx x1 = XEXP (x, 1);
11542 /* If x0 and x1 are identical then there is no need to
11547 /* If x0 is identical to a subexpression of x1 then while
11548 processing x1, x0 has already been processed. Thus we
11549 are done with x. */
11550 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11551 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11552 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11555 /* If x1 is identical to a subexpression of x0 then we
11556 still have to process the rest of x0. */
11557 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11558 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11559 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11561 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11566 update_table_tick (XEXP (x, i));
11570 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11571 are saying that the register is clobbered and we no longer know its
11572 value. If INSN is zero, don't update reg_last_set; this is only permitted
11573 with VALUE also zero and is used to invalidate the register. */
11576 record_value_for_reg (reg, insn, value)
11581 unsigned int regno = REGNO (reg);
11582 unsigned int endregno
11583 = regno + (regno < FIRST_PSEUDO_REGISTER
11584 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11587 /* If VALUE contains REG and we have a previous value for REG, substitute
11588 the previous value. */
11589 if (value && insn && reg_overlap_mentioned_p (reg, value))
11593 /* Set things up so get_last_value is allowed to see anything set up to
11595 subst_low_cuid = INSN_CUID (insn);
11596 tem = get_last_value (reg);
11598 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11599 it isn't going to be useful and will take a lot of time to process,
11600 so just use the CLOBBER. */
11604 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11605 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11606 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11607 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11608 tem = XEXP (tem, 0);
11610 value = replace_rtx (copy_rtx (value), reg, tem);
11614 /* For each register modified, show we don't know its value, that
11615 we don't know about its bitwise content, that its value has been
11616 updated, and that we don't know the location of the death of the
11618 for (i = regno; i < endregno; i++)
11621 reg_last_set[i] = insn;
11623 reg_last_set_value[i] = 0;
11624 reg_last_set_mode[i] = 0;
11625 reg_last_set_nonzero_bits[i] = 0;
11626 reg_last_set_sign_bit_copies[i] = 0;
11627 reg_last_death[i] = 0;
11630 /* Mark registers that are being referenced in this value. */
11632 update_table_tick (value);
11634 /* Now update the status of each register being set.
11635 If someone is using this register in this block, set this register
11636 to invalid since we will get confused between the two lives in this
11637 basic block. This makes using this register always invalid. In cse, we
11638 scan the table to invalidate all entries using this register, but this
11639 is too much work for us. */
11641 for (i = regno; i < endregno; i++)
11643 reg_last_set_label[i] = label_tick;
11644 if (value && reg_last_set_table_tick[i] == label_tick)
11645 reg_last_set_invalid[i] = 1;
11647 reg_last_set_invalid[i] = 0;
11650 /* The value being assigned might refer to X (like in "x++;"). In that
11651 case, we must replace it with (clobber (const_int 0)) to prevent
11653 if (value && ! get_last_value_validate (&value, insn,
11654 reg_last_set_label[regno], 0))
11656 value = copy_rtx (value);
11657 if (! get_last_value_validate (&value, insn,
11658 reg_last_set_label[regno], 1))
11662 /* For the main register being modified, update the value, the mode, the
11663 nonzero bits, and the number of sign bit copies. */
11665 reg_last_set_value[regno] = value;
11669 enum machine_mode mode = GET_MODE (reg);
11670 subst_low_cuid = INSN_CUID (insn);
11671 reg_last_set_mode[regno] = mode;
11672 if (GET_MODE_CLASS (mode) == MODE_INT
11673 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11674 mode = nonzero_bits_mode;
11675 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11676 reg_last_set_sign_bit_copies[regno]
11677 = num_sign_bit_copies (value, GET_MODE (reg));
11681 /* Called via note_stores from record_dead_and_set_regs to handle one
11682 SET or CLOBBER in an insn. DATA is the instruction in which the
11683 set is occurring. */
11686 record_dead_and_set_regs_1 (dest, setter, data)
11690 rtx record_dead_insn = (rtx) data;
11692 if (GET_CODE (dest) == SUBREG)
11693 dest = SUBREG_REG (dest);
11695 if (GET_CODE (dest) == REG)
11697 /* If we are setting the whole register, we know its value. Otherwise
11698 show that we don't know the value. We can handle SUBREG in
11700 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11701 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11702 else if (GET_CODE (setter) == SET
11703 && GET_CODE (SET_DEST (setter)) == SUBREG
11704 && SUBREG_REG (SET_DEST (setter)) == dest
11705 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11706 && subreg_lowpart_p (SET_DEST (setter)))
11707 record_value_for_reg (dest, record_dead_insn,
11708 gen_lowpart_for_combine (GET_MODE (dest),
11709 SET_SRC (setter)));
11711 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11713 else if (GET_CODE (dest) == MEM
11714 /* Ignore pushes, they clobber nothing. */
11715 && ! push_operand (dest, GET_MODE (dest)))
11716 mem_last_set = INSN_CUID (record_dead_insn);
11719 /* Update the records of when each REG was most recently set or killed
11720 for the things done by INSN. This is the last thing done in processing
11721 INSN in the combiner loop.
11723 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11724 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11725 and also the similar information mem_last_set (which insn most recently
11726 modified memory) and last_call_cuid (which insn was the most recent
11727 subroutine call). */
11730 record_dead_and_set_regs (insn)
11736 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11738 if (REG_NOTE_KIND (link) == REG_DEAD
11739 && GET_CODE (XEXP (link, 0)) == REG)
11741 unsigned int regno = REGNO (XEXP (link, 0));
11742 unsigned int endregno
11743 = regno + (regno < FIRST_PSEUDO_REGISTER
11744 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11747 for (i = regno; i < endregno; i++)
11748 reg_last_death[i] = insn;
11750 else if (REG_NOTE_KIND (link) == REG_INC)
11751 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11754 if (GET_CODE (insn) == CALL_INSN)
11756 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11757 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11759 reg_last_set_value[i] = 0;
11760 reg_last_set_mode[i] = 0;
11761 reg_last_set_nonzero_bits[i] = 0;
11762 reg_last_set_sign_bit_copies[i] = 0;
11763 reg_last_death[i] = 0;
11766 last_call_cuid = mem_last_set = INSN_CUID (insn);
11768 /* Don't bother recording what this insn does. It might set the
11769 return value register, but we can't combine into a call
11770 pattern anyway, so there's no point trying (and it may cause
11771 a crash, if e.g. we wind up asking for last_set_value of a
11772 SUBREG of the return value register). */
11776 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11779 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11780 register present in the SUBREG, so for each such SUBREG go back and
11781 adjust nonzero and sign bit information of the registers that are
11782 known to have some zero/sign bits set.
11784 This is needed because when combine blows the SUBREGs away, the
11785 information on zero/sign bits is lost and further combines can be
11786 missed because of that. */
11789 record_promoted_value (insn, subreg)
11794 unsigned int regno = REGNO (SUBREG_REG (subreg));
11795 enum machine_mode mode = GET_MODE (subreg);
11797 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11800 for (links = LOG_LINKS (insn); links;)
11802 insn = XEXP (links, 0);
11803 set = single_set (insn);
11805 if (! set || GET_CODE (SET_DEST (set)) != REG
11806 || REGNO (SET_DEST (set)) != regno
11807 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11809 links = XEXP (links, 1);
11813 if (reg_last_set[regno] == insn)
11815 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11816 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11819 if (GET_CODE (SET_SRC (set)) == REG)
11821 regno = REGNO (SET_SRC (set));
11822 links = LOG_LINKS (insn);
11829 /* Scan X for promoted SUBREGs. For each one found,
11830 note what it implies to the registers used in it. */
11833 check_promoted_subreg (insn, x)
11837 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11838 && GET_CODE (SUBREG_REG (x)) == REG)
11839 record_promoted_value (insn, x);
11842 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11845 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11849 check_promoted_subreg (insn, XEXP (x, i));
11853 if (XVEC (x, i) != 0)
11854 for (j = 0; j < XVECLEN (x, i); j++)
11855 check_promoted_subreg (insn, XVECEXP (x, i, j));
11861 /* Utility routine for the following function. Verify that all the registers
11862 mentioned in *LOC are valid when *LOC was part of a value set when
11863 label_tick == TICK. Return 0 if some are not.
11865 If REPLACE is nonzero, replace the invalid reference with
11866 (clobber (const_int 0)) and return 1. This replacement is useful because
11867 we often can get useful information about the form of a value (e.g., if
11868 it was produced by a shift that always produces -1 or 0) even though
11869 we don't know exactly what registers it was produced from. */
11872 get_last_value_validate (loc, insn, tick, replace)
11879 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11880 int len = GET_RTX_LENGTH (GET_CODE (x));
11883 if (GET_CODE (x) == REG)
11885 unsigned int regno = REGNO (x);
11886 unsigned int endregno
11887 = regno + (regno < FIRST_PSEUDO_REGISTER
11888 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11891 for (j = regno; j < endregno; j++)
11892 if (reg_last_set_invalid[j]
11893 /* If this is a pseudo-register that was only set once and not
11894 live at the beginning of the function, it is always valid. */
11895 || (! (regno >= FIRST_PSEUDO_REGISTER
11896 && REG_N_SETS (regno) == 1
11897 && (! REGNO_REG_SET_P
11898 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11899 && reg_last_set_label[j] > tick))
11902 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11908 /* If this is a memory reference, make sure that there were
11909 no stores after it that might have clobbered the value. We don't
11910 have alias info, so we assume any store invalidates it. */
11911 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11912 && INSN_CUID (insn) <= mem_last_set)
11915 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11919 for (i = 0; i < len; i++)
11923 /* Check for identical subexpressions. If x contains
11924 identical subexpression we only have to traverse one of
11927 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11928 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11930 /* Note that at this point x0 has already been checked
11931 and found valid. */
11932 rtx x0 = XEXP (x, 0);
11933 rtx x1 = XEXP (x, 1);
11935 /* If x0 and x1 are identical then x is also valid. */
11939 /* If x1 is identical to a subexpression of x0 then
11940 while checking x0, x1 has already been checked. Thus
11941 it is valid and so as x. */
11942 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11943 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11944 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11947 /* If x0 is identical to a subexpression of x1 then x is
11948 valid iff the rest of x1 is valid. */
11949 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11950 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11951 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11953 get_last_value_validate (&XEXP (x1,
11954 x0 == XEXP (x1, 0) ? 1 : 0),
11955 insn, tick, replace);
11958 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11962 /* Don't bother with these. They shouldn't occur anyway. */
11963 else if (fmt[i] == 'E')
11967 /* If we haven't found a reason for it to be invalid, it is valid. */
11971 /* Get the last value assigned to X, if known. Some registers
11972 in the value may be replaced with (clobber (const_int 0)) if their value
11973 is known longer known reliably. */
11979 unsigned int regno;
11982 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11983 then convert it to the desired mode. If this is a paradoxical SUBREG,
11984 we cannot predict what values the "extra" bits might have. */
11985 if (GET_CODE (x) == SUBREG
11986 && subreg_lowpart_p (x)
11987 && (GET_MODE_SIZE (GET_MODE (x))
11988 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11989 && (value = get_last_value (SUBREG_REG (x))) != 0)
11990 return gen_lowpart_for_combine (GET_MODE (x), value);
11992 if (GET_CODE (x) != REG)
11996 value = reg_last_set_value[regno];
11998 /* If we don't have a value, or if it isn't for this basic block and
11999 it's either a hard register, set more than once, or it's a live
12000 at the beginning of the function, return 0.
12002 Because if it's not live at the beginning of the function then the reg
12003 is always set before being used (is never used without being set).
12004 And, if it's set only once, and it's always set before use, then all
12005 uses must have the same last value, even if it's not from this basic
12009 || (reg_last_set_label[regno] != label_tick
12010 && (regno < FIRST_PSEUDO_REGISTER
12011 || REG_N_SETS (regno) != 1
12012 || (REGNO_REG_SET_P
12013 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
12016 /* If the value was set in a later insn than the ones we are processing,
12017 we can't use it even if the register was only set once. */
12018 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
12021 /* If the value has all its registers valid, return it. */
12022 if (get_last_value_validate (&value, reg_last_set[regno],
12023 reg_last_set_label[regno], 0))
12026 /* Otherwise, make a copy and replace any invalid register with
12027 (clobber (const_int 0)). If that fails for some reason, return 0. */
12029 value = copy_rtx (value);
12030 if (get_last_value_validate (&value, reg_last_set[regno],
12031 reg_last_set_label[regno], 1))
12037 /* Return nonzero if expression X refers to a REG or to memory
12038 that is set in an instruction more recent than FROM_CUID. */
12041 use_crosses_set_p (x, from_cuid)
12047 enum rtx_code code = GET_CODE (x);
12051 unsigned int regno = REGNO (x);
12052 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
12053 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12055 #ifdef PUSH_ROUNDING
12056 /* Don't allow uses of the stack pointer to be moved,
12057 because we don't know whether the move crosses a push insn. */
12058 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12061 for (; regno < endreg; regno++)
12062 if (reg_last_set[regno]
12063 && INSN_CUID (reg_last_set[regno]) > from_cuid)
12068 if (code == MEM && mem_last_set > from_cuid)
12071 fmt = GET_RTX_FORMAT (code);
12073 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12078 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12079 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
12082 else if (fmt[i] == 'e'
12083 && use_crosses_set_p (XEXP (x, i), from_cuid))
12089 /* Define three variables used for communication between the following
12092 static unsigned int reg_dead_regno, reg_dead_endregno;
12093 static int reg_dead_flag;
12095 /* Function called via note_stores from reg_dead_at_p.
12097 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12098 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12101 reg_dead_at_p_1 (dest, x, data)
12104 void *data ATTRIBUTE_UNUSED;
12106 unsigned int regno, endregno;
12108 if (GET_CODE (dest) != REG)
12111 regno = REGNO (dest);
12112 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
12113 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
12115 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12116 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12119 /* Return nonzero if REG is known to be dead at INSN.
12121 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12122 referencing REG, it is dead. If we hit a SET referencing REG, it is
12123 live. Otherwise, see if it is live or dead at the start of the basic
12124 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12125 must be assumed to be always live. */
12128 reg_dead_at_p (reg, insn)
12135 /* Set variables for reg_dead_at_p_1. */
12136 reg_dead_regno = REGNO (reg);
12137 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
12138 ? HARD_REGNO_NREGS (reg_dead_regno,
12144 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12145 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12147 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12148 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
12152 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12153 beginning of function. */
12154 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
12155 insn = prev_nonnote_insn (insn))
12157 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12159 return reg_dead_flag == 1 ? 1 : 0;
12161 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12165 /* Get the basic block that we were in. */
12167 block = ENTRY_BLOCK_PTR->next_bb;
12170 FOR_EACH_BB (block)
12171 if (insn == block->head)
12174 if (block == EXIT_BLOCK_PTR)
12178 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12179 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12185 /* Note hard registers in X that are used. This code is similar to
12186 that in flow.c, but much simpler since we don't care about pseudos. */
12189 mark_used_regs_combine (x)
12192 RTX_CODE code = GET_CODE (x);
12193 unsigned int regno;
12206 case ADDR_DIFF_VEC:
12209 /* CC0 must die in the insn after it is set, so we don't need to take
12210 special note of it here. */
12216 /* If we are clobbering a MEM, mark any hard registers inside the
12217 address as used. */
12218 if (GET_CODE (XEXP (x, 0)) == MEM)
12219 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12224 /* A hard reg in a wide mode may really be multiple registers.
12225 If so, mark all of them just like the first. */
12226 if (regno < FIRST_PSEUDO_REGISTER)
12228 unsigned int endregno, r;
12230 /* None of this applies to the stack, frame or arg pointers. */
12231 if (regno == STACK_POINTER_REGNUM
12232 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12233 || regno == HARD_FRAME_POINTER_REGNUM
12235 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12236 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12238 || regno == FRAME_POINTER_REGNUM)
12241 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12242 for (r = regno; r < endregno; r++)
12243 SET_HARD_REG_BIT (newpat_used_regs, r);
12249 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12251 rtx testreg = SET_DEST (x);
12253 while (GET_CODE (testreg) == SUBREG
12254 || GET_CODE (testreg) == ZERO_EXTRACT
12255 || GET_CODE (testreg) == SIGN_EXTRACT
12256 || GET_CODE (testreg) == STRICT_LOW_PART)
12257 testreg = XEXP (testreg, 0);
12259 if (GET_CODE (testreg) == MEM)
12260 mark_used_regs_combine (XEXP (testreg, 0));
12262 mark_used_regs_combine (SET_SRC (x));
12270 /* Recursively scan the operands of this expression. */
12273 const char *fmt = GET_RTX_FORMAT (code);
12275 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12278 mark_used_regs_combine (XEXP (x, i));
12279 else if (fmt[i] == 'E')
12283 for (j = 0; j < XVECLEN (x, i); j++)
12284 mark_used_regs_combine (XVECEXP (x, i, j));
12290 /* Remove register number REGNO from the dead registers list of INSN.
12292 Return the note used to record the death, if there was one. */
12295 remove_death (regno, insn)
12296 unsigned int regno;
12299 rtx note = find_regno_note (insn, REG_DEAD, regno);
12303 REG_N_DEATHS (regno)--;
12304 remove_note (insn, note);
12310 /* For each register (hardware or pseudo) used within expression X, if its
12311 death is in an instruction with cuid between FROM_CUID (inclusive) and
12312 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12313 list headed by PNOTES.
12315 That said, don't move registers killed by maybe_kill_insn.
12317 This is done when X is being merged by combination into TO_INSN. These
12318 notes will then be distributed as needed. */
12321 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
12323 rtx maybe_kill_insn;
12330 enum rtx_code code = GET_CODE (x);
12334 unsigned int regno = REGNO (x);
12335 rtx where_dead = reg_last_death[regno];
12336 rtx before_dead, after_dead;
12338 /* Don't move the register if it gets killed in between from and to. */
12339 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12340 && ! reg_referenced_p (x, maybe_kill_insn))
12343 /* WHERE_DEAD could be a USE insn made by combine, so first we
12344 make sure that we have insns with valid INSN_CUID values. */
12345 before_dead = where_dead;
12346 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12347 before_dead = PREV_INSN (before_dead);
12349 after_dead = where_dead;
12350 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12351 after_dead = NEXT_INSN (after_dead);
12353 if (before_dead && after_dead
12354 && INSN_CUID (before_dead) >= from_cuid
12355 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12356 || (where_dead != after_dead
12357 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12359 rtx note = remove_death (regno, where_dead);
12361 /* It is possible for the call above to return 0. This can occur
12362 when reg_last_death points to I2 or I1 that we combined with.
12363 In that case make a new note.
12365 We must also check for the case where X is a hard register
12366 and NOTE is a death note for a range of hard registers
12367 including X. In that case, we must put REG_DEAD notes for
12368 the remaining registers in place of NOTE. */
12370 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12371 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12372 > GET_MODE_SIZE (GET_MODE (x))))
12374 unsigned int deadregno = REGNO (XEXP (note, 0));
12375 unsigned int deadend
12376 = (deadregno + HARD_REGNO_NREGS (deadregno,
12377 GET_MODE (XEXP (note, 0))));
12378 unsigned int ourend
12379 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12382 for (i = deadregno; i < deadend; i++)
12383 if (i < regno || i >= ourend)
12384 REG_NOTES (where_dead)
12385 = gen_rtx_EXPR_LIST (REG_DEAD,
12387 REG_NOTES (where_dead));
12390 /* If we didn't find any note, or if we found a REG_DEAD note that
12391 covers only part of the given reg, and we have a multi-reg hard
12392 register, then to be safe we must check for REG_DEAD notes
12393 for each register other than the first. They could have
12394 their own REG_DEAD notes lying around. */
12395 else if ((note == 0
12397 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12398 < GET_MODE_SIZE (GET_MODE (x)))))
12399 && regno < FIRST_PSEUDO_REGISTER
12400 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12402 unsigned int ourend
12403 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12404 unsigned int i, offset;
12408 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12412 for (i = regno + offset; i < ourend; i++)
12413 move_deaths (regno_reg_rtx[i],
12414 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12417 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12419 XEXP (note, 1) = *pnotes;
12423 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12425 REG_N_DEATHS (regno)++;
12431 else if (GET_CODE (x) == SET)
12433 rtx dest = SET_DEST (x);
12435 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12437 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12438 that accesses one word of a multi-word item, some
12439 piece of everything register in the expression is used by
12440 this insn, so remove any old death. */
12441 /* ??? So why do we test for equality of the sizes? */
12443 if (GET_CODE (dest) == ZERO_EXTRACT
12444 || GET_CODE (dest) == STRICT_LOW_PART
12445 || (GET_CODE (dest) == SUBREG
12446 && (((GET_MODE_SIZE (GET_MODE (dest))
12447 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12448 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12449 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12451 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12455 /* If this is some other SUBREG, we know it replaces the entire
12456 value, so use that as the destination. */
12457 if (GET_CODE (dest) == SUBREG)
12458 dest = SUBREG_REG (dest);
12460 /* If this is a MEM, adjust deaths of anything used in the address.
12461 For a REG (the only other possibility), the entire value is
12462 being replaced so the old value is not used in this insn. */
12464 if (GET_CODE (dest) == MEM)
12465 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12470 else if (GET_CODE (x) == CLOBBER)
12473 len = GET_RTX_LENGTH (code);
12474 fmt = GET_RTX_FORMAT (code);
12476 for (i = 0; i < len; i++)
12481 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12482 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12485 else if (fmt[i] == 'e')
12486 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12490 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12491 pattern of an insn. X must be a REG. */
12494 reg_bitfield_target_p (x, body)
12500 if (GET_CODE (body) == SET)
12502 rtx dest = SET_DEST (body);
12504 unsigned int regno, tregno, endregno, endtregno;
12506 if (GET_CODE (dest) == ZERO_EXTRACT)
12507 target = XEXP (dest, 0);
12508 else if (GET_CODE (dest) == STRICT_LOW_PART)
12509 target = SUBREG_REG (XEXP (dest, 0));
12513 if (GET_CODE (target) == SUBREG)
12514 target = SUBREG_REG (target);
12516 if (GET_CODE (target) != REG)
12519 tregno = REGNO (target), regno = REGNO (x);
12520 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12521 return target == x;
12523 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12524 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12526 return endregno > tregno && regno < endtregno;
12529 else if (GET_CODE (body) == PARALLEL)
12530 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12531 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12537 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12538 as appropriate. I3 and I2 are the insns resulting from the combination
12539 insns including FROM (I2 may be zero).
12541 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12542 not need REG_DEAD notes because they are being substituted for. This
12543 saves searching in the most common cases.
12545 Each note in the list is either ignored or placed on some insns, depending
12546 on the type of note. */
12549 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12553 rtx elim_i2, elim_i1;
12555 rtx note, next_note;
12558 for (note = notes; note; note = next_note)
12560 rtx place = 0, place2 = 0;
12562 /* If this NOTE references a pseudo register, ensure it references
12563 the latest copy of that register. */
12564 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12565 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12566 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12568 next_note = XEXP (note, 1);
12569 switch (REG_NOTE_KIND (note))
12573 /* Doesn't matter much where we put this, as long as it's somewhere.
12574 It is preferable to keep these notes on branches, which is most
12575 likely to be i3. */
12579 case REG_VTABLE_REF:
12580 /* ??? Should remain with *a particular* memory load. Given the
12581 nature of vtable data, the last insn seems relatively safe. */
12585 case REG_NON_LOCAL_GOTO:
12586 if (GET_CODE (i3) == JUMP_INSN)
12588 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12594 case REG_EH_REGION:
12595 /* These notes must remain with the call or trapping instruction. */
12596 if (GET_CODE (i3) == CALL_INSN)
12598 else if (i2 && GET_CODE (i2) == CALL_INSN)
12600 else if (flag_non_call_exceptions)
12602 if (may_trap_p (i3))
12604 else if (i2 && may_trap_p (i2))
12606 /* ??? Otherwise assume we've combined things such that we
12607 can now prove that the instructions can't trap. Drop the
12608 note in this case. */
12616 /* These notes must remain with the call. It should not be
12617 possible for both I2 and I3 to be a call. */
12618 if (GET_CODE (i3) == CALL_INSN)
12620 else if (i2 && GET_CODE (i2) == CALL_INSN)
12627 /* Any clobbers for i3 may still exist, and so we must process
12628 REG_UNUSED notes from that insn.
12630 Any clobbers from i2 or i1 can only exist if they were added by
12631 recog_for_combine. In that case, recog_for_combine created the
12632 necessary REG_UNUSED notes. Trying to keep any original
12633 REG_UNUSED notes from these insns can cause incorrect output
12634 if it is for the same register as the original i3 dest.
12635 In that case, we will notice that the register is set in i3,
12636 and then add a REG_UNUSED note for the destination of i3, which
12637 is wrong. However, it is possible to have REG_UNUSED notes from
12638 i2 or i1 for register which were both used and clobbered, so
12639 we keep notes from i2 or i1 if they will turn into REG_DEAD
12642 /* If this register is set or clobbered in I3, put the note there
12643 unless there is one already. */
12644 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12646 if (from_insn != i3)
12649 if (! (GET_CODE (XEXP (note, 0)) == REG
12650 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12651 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12654 /* Otherwise, if this register is used by I3, then this register
12655 now dies here, so we must put a REG_DEAD note here unless there
12657 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12658 && ! (GET_CODE (XEXP (note, 0)) == REG
12659 ? find_regno_note (i3, REG_DEAD,
12660 REGNO (XEXP (note, 0)))
12661 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12663 PUT_REG_NOTE_KIND (note, REG_DEAD);
12671 /* These notes say something about results of an insn. We can
12672 only support them if they used to be on I3 in which case they
12673 remain on I3. Otherwise they are ignored.
12675 If the note refers to an expression that is not a constant, we
12676 must also ignore the note since we cannot tell whether the
12677 equivalence is still true. It might be possible to do
12678 slightly better than this (we only have a problem if I2DEST
12679 or I1DEST is present in the expression), but it doesn't
12680 seem worth the trouble. */
12682 if (from_insn == i3
12683 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12688 case REG_NO_CONFLICT:
12689 /* These notes say something about how a register is used. They must
12690 be present on any use of the register in I2 or I3. */
12691 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12694 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12704 /* This can show up in several ways -- either directly in the
12705 pattern, or hidden off in the constant pool with (or without?)
12706 a REG_EQUAL note. */
12707 /* ??? Ignore the without-reg_equal-note problem for now. */
12708 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12709 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12710 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12711 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12715 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12716 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12717 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12718 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12726 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12727 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12728 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12730 if (JUMP_LABEL (place) != XEXP (note, 0))
12732 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12733 LABEL_NUSES (JUMP_LABEL (place))--;
12736 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12738 if (JUMP_LABEL (place2) != XEXP (note, 0))
12740 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12741 LABEL_NUSES (JUMP_LABEL (place2))--;
12748 /* These notes say something about the value of a register prior
12749 to the execution of an insn. It is too much trouble to see
12750 if the note is still correct in all situations. It is better
12751 to simply delete it. */
12755 /* If the insn previously containing this note still exists,
12756 put it back where it was. Otherwise move it to the previous
12757 insn. Adjust the corresponding REG_LIBCALL note. */
12758 if (GET_CODE (from_insn) != NOTE)
12762 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12763 place = prev_real_insn (from_insn);
12765 XEXP (tem, 0) = place;
12766 /* If we're deleting the last remaining instruction of a
12767 libcall sequence, don't add the notes. */
12768 else if (XEXP (note, 0) == from_insn)
12774 /* This is handled similarly to REG_RETVAL. */
12775 if (GET_CODE (from_insn) != NOTE)
12779 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12780 place = next_real_insn (from_insn);
12782 XEXP (tem, 0) = place;
12783 /* If we're deleting the last remaining instruction of a
12784 libcall sequence, don't add the notes. */
12785 else if (XEXP (note, 0) == from_insn)
12791 /* If the register is used as an input in I3, it dies there.
12792 Similarly for I2, if it is nonzero and adjacent to I3.
12794 If the register is not used as an input in either I3 or I2
12795 and it is not one of the registers we were supposed to eliminate,
12796 there are two possibilities. We might have a non-adjacent I2
12797 or we might have somehow eliminated an additional register
12798 from a computation. For example, we might have had A & B where
12799 we discover that B will always be zero. In this case we will
12800 eliminate the reference to A.
12802 In both cases, we must search to see if we can find a previous
12803 use of A and put the death note there. */
12806 && GET_CODE (from_insn) == CALL_INSN
12807 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12809 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12811 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12812 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12815 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12816 || rtx_equal_p (XEXP (note, 0), elim_i1))
12821 basic_block bb = this_basic_block;
12823 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12825 if (! INSN_P (tem))
12827 if (tem == bb->head)
12832 /* If the register is being set at TEM, see if that is all
12833 TEM is doing. If so, delete TEM. Otherwise, make this
12834 into a REG_UNUSED note instead. */
12835 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12837 rtx set = single_set (tem);
12838 rtx inner_dest = 0;
12840 rtx cc0_setter = NULL_RTX;
12844 for (inner_dest = SET_DEST (set);
12845 (GET_CODE (inner_dest) == STRICT_LOW_PART
12846 || GET_CODE (inner_dest) == SUBREG
12847 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12848 inner_dest = XEXP (inner_dest, 0))
12851 /* Verify that it was the set, and not a clobber that
12852 modified the register.
12854 CC0 targets must be careful to maintain setter/user
12855 pairs. If we cannot delete the setter due to side
12856 effects, mark the user with an UNUSED note instead
12859 if (set != 0 && ! side_effects_p (SET_SRC (set))
12860 && rtx_equal_p (XEXP (note, 0), inner_dest)
12862 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12863 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12864 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12868 /* Move the notes and links of TEM elsewhere.
12869 This might delete other dead insns recursively.
12870 First set the pattern to something that won't use
12873 PATTERN (tem) = pc_rtx;
12875 distribute_notes (REG_NOTES (tem), tem, tem,
12876 NULL_RTX, NULL_RTX, NULL_RTX);
12877 distribute_links (LOG_LINKS (tem));
12879 PUT_CODE (tem, NOTE);
12880 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12881 NOTE_SOURCE_FILE (tem) = 0;
12884 /* Delete the setter too. */
12887 PATTERN (cc0_setter) = pc_rtx;
12889 distribute_notes (REG_NOTES (cc0_setter),
12890 cc0_setter, cc0_setter,
12891 NULL_RTX, NULL_RTX, NULL_RTX);
12892 distribute_links (LOG_LINKS (cc0_setter));
12894 PUT_CODE (cc0_setter, NOTE);
12895 NOTE_LINE_NUMBER (cc0_setter)
12896 = NOTE_INSN_DELETED;
12897 NOTE_SOURCE_FILE (cc0_setter) = 0;
12901 /* If the register is both set and used here, put the
12902 REG_DEAD note here, but place a REG_UNUSED note
12903 here too unless there already is one. */
12904 else if (reg_referenced_p (XEXP (note, 0),
12909 if (! find_regno_note (tem, REG_UNUSED,
12910 REGNO (XEXP (note, 0))))
12912 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12917 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12919 /* If there isn't already a REG_UNUSED note, put one
12921 if (! find_regno_note (tem, REG_UNUSED,
12922 REGNO (XEXP (note, 0))))
12927 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12928 || (GET_CODE (tem) == CALL_INSN
12929 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12933 /* If we are doing a 3->2 combination, and we have a
12934 register which formerly died in i3 and was not used
12935 by i2, which now no longer dies in i3 and is used in
12936 i2 but does not die in i2, and place is between i2
12937 and i3, then we may need to move a link from place to
12939 if (i2 && INSN_UID (place) <= max_uid_cuid
12940 && INSN_CUID (place) > INSN_CUID (i2)
12942 && INSN_CUID (from_insn) > INSN_CUID (i2)
12943 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12945 rtx links = LOG_LINKS (place);
12946 LOG_LINKS (place) = 0;
12947 distribute_links (links);
12952 if (tem == bb->head)
12956 /* We haven't found an insn for the death note and it
12957 is still a REG_DEAD note, but we have hit the beginning
12958 of the block. If the existing life info says the reg
12959 was dead, there's nothing left to do. Otherwise, we'll
12960 need to do a global life update after combine. */
12961 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12962 && REGNO_REG_SET_P (bb->global_live_at_start,
12963 REGNO (XEXP (note, 0))))
12964 SET_BIT (refresh_blocks, this_basic_block->index);
12967 /* If the register is set or already dead at PLACE, we needn't do
12968 anything with this note if it is still a REG_DEAD note.
12969 We can here if it is set at all, not if is it totally replace,
12970 which is what `dead_or_set_p' checks, so also check for it being
12973 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12975 unsigned int regno = REGNO (XEXP (note, 0));
12977 /* Similarly, if the instruction on which we want to place
12978 the note is a noop, we'll need do a global live update
12979 after we remove them in delete_noop_moves. */
12980 if (noop_move_p (place))
12981 SET_BIT (refresh_blocks, this_basic_block->index);
12983 if (dead_or_set_p (place, XEXP (note, 0))
12984 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12986 /* Unless the register previously died in PLACE, clear
12987 reg_last_death. [I no longer understand why this is
12989 if (reg_last_death[regno] != place)
12990 reg_last_death[regno] = 0;
12994 reg_last_death[regno] = place;
12996 /* If this is a death note for a hard reg that is occupying
12997 multiple registers, ensure that we are still using all
12998 parts of the object. If we find a piece of the object
12999 that is unused, we must arrange for an appropriate REG_DEAD
13000 note to be added for it. However, we can't just emit a USE
13001 and tag the note to it, since the register might actually
13002 be dead; so we recourse, and the recursive call then finds
13003 the previous insn that used this register. */
13005 if (place && regno < FIRST_PSEUDO_REGISTER
13006 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
13008 unsigned int endregno
13009 = regno + HARD_REGNO_NREGS (regno,
13010 GET_MODE (XEXP (note, 0)));
13014 for (i = regno; i < endregno; i++)
13015 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13016 && ! find_regno_fusage (place, USE, i))
13017 || dead_or_set_regno_p (place, i))
13022 /* Put only REG_DEAD notes for pieces that are
13023 not already dead or set. */
13025 for (i = regno; i < endregno;
13026 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
13028 rtx piece = regno_reg_rtx[i];
13029 basic_block bb = this_basic_block;
13031 if (! dead_or_set_p (place, piece)
13032 && ! reg_bitfield_target_p (piece,
13036 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
13038 distribute_notes (new_note, place, place,
13039 NULL_RTX, NULL_RTX, NULL_RTX);
13041 else if (! refers_to_regno_p (i, i + 1,
13042 PATTERN (place), 0)
13043 && ! find_regno_fusage (place, USE, i))
13044 for (tem = PREV_INSN (place); ;
13045 tem = PREV_INSN (tem))
13047 if (! INSN_P (tem))
13049 if (tem == bb->head)
13051 SET_BIT (refresh_blocks,
13052 this_basic_block->index);
13057 if (dead_or_set_p (tem, piece)
13058 || reg_bitfield_target_p (piece,
13062 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
13077 /* Any other notes should not be present at this point in the
13084 XEXP (note, 1) = REG_NOTES (place);
13085 REG_NOTES (place) = note;
13087 else if ((REG_NOTE_KIND (note) == REG_DEAD
13088 || REG_NOTE_KIND (note) == REG_UNUSED)
13089 && GET_CODE (XEXP (note, 0)) == REG)
13090 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
13094 if ((REG_NOTE_KIND (note) == REG_DEAD
13095 || REG_NOTE_KIND (note) == REG_UNUSED)
13096 && GET_CODE (XEXP (note, 0)) == REG)
13097 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
13099 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
13100 REG_NOTE_KIND (note),
13102 REG_NOTES (place2));
13107 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13108 I3, I2, and I1 to new locations. This is also called in one case to
13109 add a link pointing at I3 when I3's destination is changed. */
13112 distribute_links (links)
13115 rtx link, next_link;
13117 for (link = links; link; link = next_link)
13123 next_link = XEXP (link, 1);
13125 /* If the insn that this link points to is a NOTE or isn't a single
13126 set, ignore it. In the latter case, it isn't clear what we
13127 can do other than ignore the link, since we can't tell which
13128 register it was for. Such links wouldn't be used by combine
13131 It is not possible for the destination of the target of the link to
13132 have been changed by combine. The only potential of this is if we
13133 replace I3, I2, and I1 by I3 and I2. But in that case the
13134 destination of I2 also remains unchanged. */
13136 if (GET_CODE (XEXP (link, 0)) == NOTE
13137 || (set = single_set (XEXP (link, 0))) == 0)
13140 reg = SET_DEST (set);
13141 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13142 || GET_CODE (reg) == SIGN_EXTRACT
13143 || GET_CODE (reg) == STRICT_LOW_PART)
13144 reg = XEXP (reg, 0);
13146 /* A LOG_LINK is defined as being placed on the first insn that uses
13147 a register and points to the insn that sets the register. Start
13148 searching at the next insn after the target of the link and stop
13149 when we reach a set of the register or the end of the basic block.
13151 Note that this correctly handles the link that used to point from
13152 I3 to I2. Also note that not much searching is typically done here
13153 since most links don't point very far away. */
13155 for (insn = NEXT_INSN (XEXP (link, 0));
13156 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13157 || this_basic_block->next_bb->head != insn));
13158 insn = NEXT_INSN (insn))
13159 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13161 if (reg_referenced_p (reg, PATTERN (insn)))
13165 else if (GET_CODE (insn) == CALL_INSN
13166 && find_reg_fusage (insn, USE, reg))
13172 /* If we found a place to put the link, place it there unless there
13173 is already a link to the same insn as LINK at that point. */
13179 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13180 if (XEXP (link2, 0) == XEXP (link, 0))
13185 XEXP (link, 1) = LOG_LINKS (place);
13186 LOG_LINKS (place) = link;
13188 /* Set added_links_insn to the earliest insn we added a
13190 if (added_links_insn == 0
13191 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13192 added_links_insn = place;
13198 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13204 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13205 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13206 insn = NEXT_INSN (insn);
13208 if (INSN_UID (insn) > max_uid_cuid)
13211 return INSN_CUID (insn);
13215 dump_combine_stats (file)
13220 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13221 combine_attempts, combine_merges, combine_extras, combine_successes);
13225 dump_combine_total_stats (file)
13230 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13231 total_attempts, total_merges, total_extras, total_successes);