1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1017 /* Main entry point for combiner. F is the first insn of the function.
1018 NREGS is the first unused pseudo-reg number.
1020 Return nonzero if the combiner has turned an indirect jump
1021 instruction into a direct jump. */
1023 combine_instructions (rtx f, unsigned int nregs)
1029 rtx links, nextlinks;
1032 int new_direct_jump_p = 0;
1034 for (first = f; first && !INSN_P (first); )
1035 first = NEXT_INSN (first);
1039 combine_attempts = 0;
1042 combine_successes = 0;
1044 rtl_hooks = combine_rtl_hooks;
1046 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1048 init_recog_no_volatile ();
1050 /* Allocate array for insn info. */
1051 max_uid_known = get_max_uid ();
1052 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1053 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1055 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1057 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1058 problems when, for example, we have j <<= 1 in a loop. */
1060 nonzero_sign_valid = 0;
1062 /* Scan all SETs and see if we can deduce anything about what
1063 bits are known to be zero for some registers and how many copies
1064 of the sign bit are known to exist for those registers.
1066 Also set any known values so that we can use it while searching
1067 for what bits are known to be set. */
1069 setup_incoming_promotions (first);
1071 create_log_links ();
1072 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1073 FOR_EACH_BB (this_basic_block)
1075 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1078 label_tick = this_basic_block->index;
1079 if (!single_pred_p (this_basic_block)
1080 || single_pred (this_basic_block)->index != label_tick - 1)
1081 label_tick_ebb_start = label_tick;
1082 FOR_BB_INSNS (this_basic_block, insn)
1083 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1085 subst_low_luid = DF_INSN_LUID (insn);
1088 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1090 record_dead_and_set_regs (insn);
1093 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1094 if (REG_NOTE_KIND (links) == REG_INC)
1095 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1099 /* Record the current insn_rtx_cost of this instruction. */
1100 if (NONJUMP_INSN_P (insn))
1101 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1102 optimize_this_for_speed_p);
1104 fprintf(dump_file, "insn_cost %d: %d\n",
1105 INSN_UID (insn), INSN_COST (insn));
1109 nonzero_sign_valid = 1;
1111 /* Now scan all the insns in forward order. */
1113 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1115 setup_incoming_promotions (first);
1117 FOR_EACH_BB (this_basic_block)
1119 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1122 label_tick = this_basic_block->index;
1123 if (!single_pred_p (this_basic_block)
1124 || single_pred (this_basic_block)->index != label_tick - 1)
1125 label_tick_ebb_start = label_tick;
1126 rtl_profile_for_bb (this_basic_block);
1127 for (insn = BB_HEAD (this_basic_block);
1128 insn != NEXT_INSN (BB_END (this_basic_block));
1129 insn = next ? next : NEXT_INSN (insn))
1134 /* See if we know about function return values before this
1135 insn based upon SUBREG flags. */
1136 check_promoted_subreg (insn, PATTERN (insn));
1138 /* See if we can find hardregs and subreg of pseudos in
1139 narrower modes. This could help turning TRUNCATEs
1141 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1143 /* Try this insn with each insn it links back to. */
1145 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1146 if ((next = try_combine (insn, XEXP (links, 0),
1147 NULL_RTX, &new_direct_jump_p)) != 0)
1150 /* Try each sequence of three linked insns ending with this one. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1154 rtx link = XEXP (links, 0);
1156 /* If the linked insn has been replaced by a note, then there
1157 is no point in pursuing this chain any further. */
1161 for (nextlinks = LOG_LINKS (link);
1163 nextlinks = XEXP (nextlinks, 1))
1164 if ((next = try_combine (insn, link,
1165 XEXP (nextlinks, 0),
1166 &new_direct_jump_p)) != 0)
1171 /* Try to combine a jump insn that uses CC0
1172 with a preceding insn that sets CC0, and maybe with its
1173 logical predecessor as well.
1174 This is how we make decrement-and-branch insns.
1175 We need this special code because data flow connections
1176 via CC0 do not get entered in LOG_LINKS. */
1179 && (prev = prev_nonnote_insn (insn)) != 0
1180 && NONJUMP_INSN_P (prev)
1181 && sets_cc0_p (PATTERN (prev)))
1183 if ((next = try_combine (insn, prev,
1184 NULL_RTX, &new_direct_jump_p)) != 0)
1187 for (nextlinks = LOG_LINKS (prev); nextlinks;
1188 nextlinks = XEXP (nextlinks, 1))
1189 if ((next = try_combine (insn, prev,
1190 XEXP (nextlinks, 0),
1191 &new_direct_jump_p)) != 0)
1195 /* Do the same for an insn that explicitly references CC0. */
1196 if (NONJUMP_INSN_P (insn)
1197 && (prev = prev_nonnote_insn (insn)) != 0
1198 && NONJUMP_INSN_P (prev)
1199 && sets_cc0_p (PATTERN (prev))
1200 && GET_CODE (PATTERN (insn)) == SET
1201 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1203 if ((next = try_combine (insn, prev,
1204 NULL_RTX, &new_direct_jump_p)) != 0)
1207 for (nextlinks = LOG_LINKS (prev); nextlinks;
1208 nextlinks = XEXP (nextlinks, 1))
1209 if ((next = try_combine (insn, prev,
1210 XEXP (nextlinks, 0),
1211 &new_direct_jump_p)) != 0)
1215 /* Finally, see if any of the insns that this insn links to
1216 explicitly references CC0. If so, try this insn, that insn,
1217 and its predecessor if it sets CC0. */
1218 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1219 if (NONJUMP_INSN_P (XEXP (links, 0))
1220 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1221 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1222 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1223 && NONJUMP_INSN_P (prev)
1224 && sets_cc0_p (PATTERN (prev))
1225 && (next = try_combine (insn, XEXP (links, 0),
1226 prev, &new_direct_jump_p)) != 0)
1230 /* Try combining an insn with two different insns whose results it
1232 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1233 for (nextlinks = XEXP (links, 1); nextlinks;
1234 nextlinks = XEXP (nextlinks, 1))
1235 if ((next = try_combine (insn, XEXP (links, 0),
1236 XEXP (nextlinks, 0),
1237 &new_direct_jump_p)) != 0)
1240 /* Try this insn with each REG_EQUAL note it links back to. */
1241 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1244 rtx temp = XEXP (links, 0);
1245 if ((set = single_set (temp)) != 0
1246 && (note = find_reg_equal_equiv_note (temp)) != 0
1247 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1248 /* Avoid using a register that may already been marked
1249 dead by an earlier instruction. */
1250 && ! unmentioned_reg_p (note, SET_SRC (set))
1251 && (GET_MODE (note) == VOIDmode
1252 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1253 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1255 /* Temporarily replace the set's source with the
1256 contents of the REG_EQUAL note. The insn will
1257 be deleted or recognized by try_combine. */
1258 rtx orig = SET_SRC (set);
1259 SET_SRC (set) = note;
1261 i2mod_old_rhs = copy_rtx (orig);
1262 i2mod_new_rhs = copy_rtx (note);
1263 next = try_combine (insn, i2mod, NULL_RTX,
1264 &new_direct_jump_p);
1268 SET_SRC (set) = orig;
1273 record_dead_and_set_regs (insn);
1281 default_rtl_profile ();
1284 new_direct_jump_p |= purge_all_dead_edges ();
1285 delete_noop_moves ();
1288 free (uid_log_links);
1289 free (uid_insn_cost);
1290 VEC_free (reg_stat_type, heap, reg_stat);
1293 struct undo *undo, *next;
1294 for (undo = undobuf.frees; undo; undo = next)
1302 total_attempts += combine_attempts;
1303 total_merges += combine_merges;
1304 total_extras += combine_extras;
1305 total_successes += combine_successes;
1307 nonzero_sign_valid = 0;
1308 rtl_hooks = general_rtl_hooks;
1310 /* Make recognizer allow volatile MEMs again. */
1313 return new_direct_jump_p;
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1319 init_reg_last (void)
1324 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1325 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1328 /* Set up any promoted values for incoming argument registers. */
1331 setup_incoming_promotions (rtx first)
1334 bool strictly_local = false;
1336 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1339 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1340 arg = TREE_CHAIN (arg))
1342 rtx reg = DECL_INCOMING_RTL (arg);
1344 enum machine_mode mode1, mode2, mode3, mode4;
1346 /* Only continue if the incoming argument is in a register. */
1350 /* Determine, if possible, whether all call sites of the current
1351 function lie within the current compilation unit. (This does
1352 take into account the exporting of a function via taking its
1353 address, and so forth.) */
1354 strictly_local = cgraph_local_info (current_function_decl)->local;
1356 /* The mode and signedness of the argument before any promotions happen
1357 (equal to the mode of the pseudo holding it at that stage). */
1358 mode1 = TYPE_MODE (TREE_TYPE (arg));
1359 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1361 /* The mode and signedness of the argument after any source language and
1362 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1363 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1364 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1366 /* The mode and signedness of the argument as it is actually passed,
1367 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1368 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1370 /* The mode of the register in which the argument is being passed. */
1371 mode4 = GET_MODE (reg);
1373 /* Eliminate sign extensions in the callee when possible. Only
1375 (a) a mode promotion has occurred;
1376 (b) the mode of the register is the same as the mode of
1377 the argument as it is passed; and
1378 (c) the signedness does not change across any of the promotions; and
1379 (d) when no language-level promotions (which we cannot guarantee
1380 will have been done by an external caller) are necessary,
1381 unless we know that this function is only ever called from
1382 the current compilation unit -- all of whose call sites will
1383 do the mode1 --> mode2 promotion. */
1387 && (mode1 == mode2 || strictly_local))
1389 /* Record that the value was promoted from mode1 to mode3,
1390 so that any sign extension at the head of the current
1391 function may be eliminated. */
1393 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1394 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1395 record_value_for_reg (reg, first, x);
1400 /* Called via note_stores. If X is a pseudo that is narrower than
1401 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1403 If we are setting only a portion of X and we can't figure out what
1404 portion, assume all bits will be used since we don't know what will
1407 Similarly, set how many bits of X are known to be copies of the sign bit
1408 at all locations in the function. This is the smallest number implied
1412 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1414 rtx insn = (rtx) data;
1418 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1419 /* If this register is undefined at the start of the file, we can't
1420 say what its contents were. */
1421 && ! REGNO_REG_SET_P
1422 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1423 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1425 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1427 if (set == 0 || GET_CODE (set) == CLOBBER)
1429 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1430 rsp->sign_bit_copies = 1;
1434 /* If this register is being initialized using itself, and the
1435 register is uninitialized in this basic block, and there are
1436 no LOG_LINKS which set the register, then part of the
1437 register is uninitialized. In that case we can't assume
1438 anything about the number of nonzero bits.
1440 ??? We could do better if we checked this in
1441 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1442 could avoid making assumptions about the insn which initially
1443 sets the register, while still using the information in other
1444 insns. We would have to be careful to check every insn
1445 involved in the combination. */
1448 && reg_referenced_p (x, PATTERN (insn))
1449 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1454 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1456 if (dead_or_set_p (XEXP (link, 0), x))
1461 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1462 rsp->sign_bit_copies = 1;
1467 /* If this is a complex assignment, see if we can convert it into a
1468 simple assignment. */
1469 set = expand_field_assignment (set);
1471 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1472 set what we know about X. */
1474 if (SET_DEST (set) == x
1475 || (GET_CODE (SET_DEST (set)) == SUBREG
1476 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1477 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1478 && SUBREG_REG (SET_DEST (set)) == x))
1480 rtx src = SET_SRC (set);
1482 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1483 /* If X is narrower than a word and SRC is a non-negative
1484 constant that would appear negative in the mode of X,
1485 sign-extend it for use in reg_stat[].nonzero_bits because some
1486 machines (maybe most) will actually do the sign-extension
1487 and this is the conservative approach.
1489 ??? For 2.5, try to tighten up the MD files in this regard
1490 instead of this kludge. */
1492 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1493 && CONST_INT_P (src)
1495 && 0 != (INTVAL (src)
1496 & ((HOST_WIDE_INT) 1
1497 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1498 src = GEN_INT (INTVAL (src)
1499 | ((HOST_WIDE_INT) (-1)
1500 << GET_MODE_BITSIZE (GET_MODE (x))));
1503 /* Don't call nonzero_bits if it cannot change anything. */
1504 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1505 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1506 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1507 if (rsp->sign_bit_copies == 0
1508 || rsp->sign_bit_copies > num)
1509 rsp->sign_bit_copies = num;
1513 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1514 rsp->sign_bit_copies = 1;
1519 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1520 insns that were previously combined into I3 or that will be combined
1521 into the merger of INSN and I3.
1523 Return 0 if the combination is not allowed for any reason.
1525 If the combination is allowed, *PDEST will be set to the single
1526 destination of INSN and *PSRC to the single source, and this function
1530 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1531 rtx *pdest, rtx *psrc)
1540 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1541 && next_active_insn (succ) == i3)
1542 : next_active_insn (insn) == i3);
1544 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1545 or a PARALLEL consisting of such a SET and CLOBBERs.
1547 If INSN has CLOBBER parallel parts, ignore them for our processing.
1548 By definition, these happen during the execution of the insn. When it
1549 is merged with another insn, all bets are off. If they are, in fact,
1550 needed and aren't also supplied in I3, they may be added by
1551 recog_for_combine. Otherwise, it won't match.
1553 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1556 Get the source and destination of INSN. If more than one, can't
1559 if (GET_CODE (PATTERN (insn)) == SET)
1560 set = PATTERN (insn);
1561 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1562 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1564 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1566 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1569 switch (GET_CODE (elt))
1571 /* This is important to combine floating point insns
1572 for the SH4 port. */
1574 /* Combining an isolated USE doesn't make sense.
1575 We depend here on combinable_i3pat to reject them. */
1576 /* The code below this loop only verifies that the inputs of
1577 the SET in INSN do not change. We call reg_set_between_p
1578 to verify that the REG in the USE does not change between
1580 If the USE in INSN was for a pseudo register, the matching
1581 insn pattern will likely match any register; combining this
1582 with any other USE would only be safe if we knew that the
1583 used registers have identical values, or if there was
1584 something to tell them apart, e.g. different modes. For
1585 now, we forgo such complicated tests and simply disallow
1586 combining of USES of pseudo registers with any other USE. */
1587 if (REG_P (XEXP (elt, 0))
1588 && GET_CODE (PATTERN (i3)) == PARALLEL)
1590 rtx i3pat = PATTERN (i3);
1591 int i = XVECLEN (i3pat, 0) - 1;
1592 unsigned int regno = REGNO (XEXP (elt, 0));
1596 rtx i3elt = XVECEXP (i3pat, 0, i);
1598 if (GET_CODE (i3elt) == USE
1599 && REG_P (XEXP (i3elt, 0))
1600 && (REGNO (XEXP (i3elt, 0)) == regno
1601 ? reg_set_between_p (XEXP (elt, 0),
1602 PREV_INSN (insn), i3)
1603 : regno >= FIRST_PSEUDO_REGISTER))
1610 /* We can ignore CLOBBERs. */
1615 /* Ignore SETs whose result isn't used but not those that
1616 have side-effects. */
1617 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1618 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1619 || INTVAL (XEXP (note, 0)) <= 0)
1620 && ! side_effects_p (elt))
1623 /* If we have already found a SET, this is a second one and
1624 so we cannot combine with this insn. */
1632 /* Anything else means we can't combine. */
1638 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1639 so don't do anything with it. */
1640 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1649 set = expand_field_assignment (set);
1650 src = SET_SRC (set), dest = SET_DEST (set);
1652 /* Don't eliminate a store in the stack pointer. */
1653 if (dest == stack_pointer_rtx
1654 /* Don't combine with an insn that sets a register to itself if it has
1655 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1656 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1657 /* Can't merge an ASM_OPERANDS. */
1658 || GET_CODE (src) == ASM_OPERANDS
1659 /* Can't merge a function call. */
1660 || GET_CODE (src) == CALL
1661 /* Don't eliminate a function call argument. */
1663 && (find_reg_fusage (i3, USE, dest)
1665 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1666 && global_regs[REGNO (dest)])))
1667 /* Don't substitute into an incremented register. */
1668 || FIND_REG_INC_NOTE (i3, dest)
1669 || (succ && FIND_REG_INC_NOTE (succ, dest))
1670 /* Don't substitute into a non-local goto, this confuses CFG. */
1671 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1672 /* Make sure that DEST is not used after SUCC but before I3. */
1673 || (succ && ! all_adjacent
1674 && reg_used_between_p (dest, succ, i3))
1675 /* Make sure that the value that is to be substituted for the register
1676 does not use any registers whose values alter in between. However,
1677 If the insns are adjacent, a use can't cross a set even though we
1678 think it might (this can happen for a sequence of insns each setting
1679 the same destination; last_set of that register might point to
1680 a NOTE). If INSN has a REG_EQUIV note, the register is always
1681 equivalent to the memory so the substitution is valid even if there
1682 are intervening stores. Also, don't move a volatile asm or
1683 UNSPEC_VOLATILE across any other insns. */
1686 || ! find_reg_note (insn, REG_EQUIV, src))
1687 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1688 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1689 || GET_CODE (src) == UNSPEC_VOLATILE))
1690 /* Don't combine across a CALL_INSN, because that would possibly
1691 change whether the life span of some REGs crosses calls or not,
1692 and it is a pain to update that information.
1693 Exception: if source is a constant, moving it later can't hurt.
1694 Accept that as a special case. */
1695 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1698 /* DEST must either be a REG or CC0. */
1701 /* If register alignment is being enforced for multi-word items in all
1702 cases except for parameters, it is possible to have a register copy
1703 insn referencing a hard register that is not allowed to contain the
1704 mode being copied and which would not be valid as an operand of most
1705 insns. Eliminate this problem by not combining with such an insn.
1707 Also, on some machines we don't want to extend the life of a hard
1711 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1712 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1713 /* Don't extend the life of a hard register unless it is
1714 user variable (if we have few registers) or it can't
1715 fit into the desired register (meaning something special
1717 Also avoid substituting a return register into I3, because
1718 reload can't handle a conflict with constraints of other
1720 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1721 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1724 else if (GET_CODE (dest) != CC0)
1728 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1729 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1730 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1732 /* Don't substitute for a register intended as a clobberable
1734 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1735 if (rtx_equal_p (reg, dest))
1738 /* If the clobber represents an earlyclobber operand, we must not
1739 substitute an expression containing the clobbered register.
1740 As we do not analyze the constraint strings here, we have to
1741 make the conservative assumption. However, if the register is
1742 a fixed hard reg, the clobber cannot represent any operand;
1743 we leave it up to the machine description to either accept or
1744 reject use-and-clobber patterns. */
1746 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1747 || !fixed_regs[REGNO (reg)])
1748 if (reg_overlap_mentioned_p (reg, src))
1752 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1753 or not), reject, unless nothing volatile comes between it and I3 */
1755 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1757 /* Make sure succ doesn't contain a volatile reference. */
1758 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1761 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1762 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1766 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1767 to be an explicit register variable, and was chosen for a reason. */
1769 if (GET_CODE (src) == ASM_OPERANDS
1770 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1773 /* If there are any volatile insns between INSN and I3, reject, because
1774 they might affect machine state. */
1776 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1777 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1780 /* If INSN contains an autoincrement or autodecrement, make sure that
1781 register is not used between there and I3, and not already used in
1782 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1783 Also insist that I3 not be a jump; if it were one
1784 and the incremented register were spilled, we would lose. */
1787 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1788 if (REG_NOTE_KIND (link) == REG_INC
1790 || reg_used_between_p (XEXP (link, 0), insn, i3)
1791 || (pred != NULL_RTX
1792 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1793 || (succ != NULL_RTX
1794 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1795 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1800 /* Don't combine an insn that follows a CC0-setting insn.
1801 An insn that uses CC0 must not be separated from the one that sets it.
1802 We do, however, allow I2 to follow a CC0-setting insn if that insn
1803 is passed as I1; in that case it will be deleted also.
1804 We also allow combining in this case if all the insns are adjacent
1805 because that would leave the two CC0 insns adjacent as well.
1806 It would be more logical to test whether CC0 occurs inside I1 or I2,
1807 but that would be much slower, and this ought to be equivalent. */
1809 p = prev_nonnote_insn (insn);
1810 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1815 /* If we get here, we have passed all the tests and the combination is
1824 /* LOC is the location within I3 that contains its pattern or the component
1825 of a PARALLEL of the pattern. We validate that it is valid for combining.
1827 One problem is if I3 modifies its output, as opposed to replacing it
1828 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1829 so would produce an insn that is not equivalent to the original insns.
1833 (set (reg:DI 101) (reg:DI 100))
1834 (set (subreg:SI (reg:DI 101) 0) <foo>)
1836 This is NOT equivalent to:
1838 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1839 (set (reg:DI 101) (reg:DI 100))])
1841 Not only does this modify 100 (in which case it might still be valid
1842 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1844 We can also run into a problem if I2 sets a register that I1
1845 uses and I1 gets directly substituted into I3 (not via I2). In that
1846 case, we would be getting the wrong value of I2DEST into I3, so we
1847 must reject the combination. This case occurs when I2 and I1 both
1848 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1849 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1850 of a SET must prevent combination from occurring.
1852 Before doing the above check, we first try to expand a field assignment
1853 into a set of logical operations.
1855 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1856 we place a register that is both set and used within I3. If more than one
1857 such register is detected, we fail.
1859 Return 1 if the combination is valid, zero otherwise. */
1862 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1863 int i1_not_in_src, rtx *pi3dest_killed)
1867 if (GET_CODE (x) == SET)
1870 rtx dest = SET_DEST (set);
1871 rtx src = SET_SRC (set);
1872 rtx inner_dest = dest;
1875 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1876 || GET_CODE (inner_dest) == SUBREG
1877 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1878 inner_dest = XEXP (inner_dest, 0);
1880 /* Check for the case where I3 modifies its output, as discussed
1881 above. We don't want to prevent pseudos from being combined
1882 into the address of a MEM, so only prevent the combination if
1883 i1 or i2 set the same MEM. */
1884 if ((inner_dest != dest &&
1885 (!MEM_P (inner_dest)
1886 || rtx_equal_p (i2dest, inner_dest)
1887 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1888 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1889 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1891 /* This is the same test done in can_combine_p except we can't test
1892 all_adjacent; we don't have to, since this instruction will stay
1893 in place, thus we are not considering increasing the lifetime of
1896 Also, if this insn sets a function argument, combining it with
1897 something that might need a spill could clobber a previous
1898 function argument; the all_adjacent test in can_combine_p also
1899 checks this; here, we do a more specific test for this case. */
1901 || (REG_P (inner_dest)
1902 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1903 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1904 GET_MODE (inner_dest))))
1905 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1908 /* If DEST is used in I3, it is being killed in this insn, so
1909 record that for later. We have to consider paradoxical
1910 subregs here, since they kill the whole register, but we
1911 ignore partial subregs, STRICT_LOW_PART, etc.
1912 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1913 STACK_POINTER_REGNUM, since these are always considered to be
1914 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1916 if (GET_CODE (subdest) == SUBREG
1917 && (GET_MODE_SIZE (GET_MODE (subdest))
1918 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1919 subdest = SUBREG_REG (subdest);
1922 && reg_referenced_p (subdest, PATTERN (i3))
1923 && REGNO (subdest) != FRAME_POINTER_REGNUM
1924 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1925 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1927 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1928 && (REGNO (subdest) != ARG_POINTER_REGNUM
1929 || ! fixed_regs [REGNO (subdest)])
1931 && REGNO (subdest) != STACK_POINTER_REGNUM)
1933 if (*pi3dest_killed)
1936 *pi3dest_killed = subdest;
1940 else if (GET_CODE (x) == PARALLEL)
1944 for (i = 0; i < XVECLEN (x, 0); i++)
1945 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1946 i1_not_in_src, pi3dest_killed))
1953 /* Return 1 if X is an arithmetic expression that contains a multiplication
1954 and division. We don't count multiplications by powers of two here. */
1957 contains_muldiv (rtx x)
1959 switch (GET_CODE (x))
1961 case MOD: case DIV: case UMOD: case UDIV:
1965 return ! (CONST_INT_P (XEXP (x, 1))
1966 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1969 return contains_muldiv (XEXP (x, 0))
1970 || contains_muldiv (XEXP (x, 1));
1973 return contains_muldiv (XEXP (x, 0));
1979 /* Determine whether INSN can be used in a combination. Return nonzero if
1980 not. This is used in try_combine to detect early some cases where we
1981 can't perform combinations. */
1984 cant_combine_insn_p (rtx insn)
1989 /* If this isn't really an insn, we can't do anything.
1990 This can occur when flow deletes an insn that it has merged into an
1991 auto-increment address. */
1992 if (! INSN_P (insn))
1995 /* Never combine loads and stores involving hard regs that are likely
1996 to be spilled. The register allocator can usually handle such
1997 reg-reg moves by tying. If we allow the combiner to make
1998 substitutions of likely-spilled regs, reload might die.
1999 As an exception, we allow combinations involving fixed regs; these are
2000 not available to the register allocator so there's no risk involved. */
2002 set = single_set (insn);
2005 src = SET_SRC (set);
2006 dest = SET_DEST (set);
2007 if (GET_CODE (src) == SUBREG)
2008 src = SUBREG_REG (src);
2009 if (GET_CODE (dest) == SUBREG)
2010 dest = SUBREG_REG (dest);
2011 if (REG_P (src) && REG_P (dest)
2012 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2013 && ! fixed_regs[REGNO (src)]
2014 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2015 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2016 && ! fixed_regs[REGNO (dest)]
2017 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2023 struct likely_spilled_retval_info
2025 unsigned regno, nregs;
2029 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2030 hard registers that are known to be written to / clobbered in full. */
2032 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2034 struct likely_spilled_retval_info *const info =
2035 (struct likely_spilled_retval_info *) data;
2036 unsigned regno, nregs;
2039 if (!REG_P (XEXP (set, 0)))
2042 if (regno >= info->regno + info->nregs)
2044 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2045 if (regno + nregs <= info->regno)
2047 new_mask = (2U << (nregs - 1)) - 1;
2048 if (regno < info->regno)
2049 new_mask >>= info->regno - regno;
2051 new_mask <<= regno - info->regno;
2052 info->mask &= ~new_mask;
2055 /* Return nonzero iff part of the return value is live during INSN, and
2056 it is likely spilled. This can happen when more than one insn is needed
2057 to copy the return value, e.g. when we consider to combine into the
2058 second copy insn for a complex value. */
2061 likely_spilled_retval_p (rtx insn)
2063 rtx use = BB_END (this_basic_block);
2065 unsigned regno, nregs;
2066 /* We assume here that no machine mode needs more than
2067 32 hard registers when the value overlaps with a register
2068 for which FUNCTION_VALUE_REGNO_P is true. */
2070 struct likely_spilled_retval_info info;
2072 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2074 reg = XEXP (PATTERN (use), 0);
2075 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2077 regno = REGNO (reg);
2078 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2081 mask = (2U << (nregs - 1)) - 1;
2083 /* Disregard parts of the return value that are set later. */
2087 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2089 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2092 /* Check if any of the (probably) live return value registers is
2097 if ((mask & 1 << nregs)
2098 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2104 /* Adjust INSN after we made a change to its destination.
2106 Changing the destination can invalidate notes that say something about
2107 the results of the insn and a LOG_LINK pointing to the insn. */
2110 adjust_for_new_dest (rtx insn)
2112 /* For notes, be conservative and simply remove them. */
2113 remove_reg_equal_equiv_notes (insn);
2115 /* The new insn will have a destination that was previously the destination
2116 of an insn just above it. Call distribute_links to make a LOG_LINK from
2117 the next use of that destination. */
2118 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2120 df_insn_rescan (insn);
2123 /* Return TRUE if combine can reuse reg X in mode MODE.
2124 ADDED_SETS is nonzero if the original set is still required. */
2126 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2134 /* Allow hard registers if the new mode is legal, and occupies no more
2135 registers than the old mode. */
2136 if (regno < FIRST_PSEUDO_REGISTER)
2137 return (HARD_REGNO_MODE_OK (regno, mode)
2138 && (hard_regno_nregs[regno][GET_MODE (x)]
2139 >= hard_regno_nregs[regno][mode]));
2141 /* Or a pseudo that is only used once. */
2142 return (REG_N_SETS (regno) == 1 && !added_sets
2143 && !REG_USERVAR_P (x));
2147 /* Check whether X, the destination of a set, refers to part of
2148 the register specified by REG. */
2151 reg_subword_p (rtx x, rtx reg)
2153 /* Check that reg is an integer mode register. */
2154 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2157 if (GET_CODE (x) == STRICT_LOW_PART
2158 || GET_CODE (x) == ZERO_EXTRACT)
2161 return GET_CODE (x) == SUBREG
2162 && SUBREG_REG (x) == reg
2163 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2167 /* Delete the conditional jump INSN and adjust the CFG correspondingly.
2168 Note that the INSN should be deleted *after* removing dead edges, so
2169 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2170 but not for a (set (pc) (label_ref FOO)). */
2173 update_cfg_for_uncondjump (rtx insn)
2175 basic_block bb = BLOCK_FOR_INSN (insn);
2177 if (BB_END (bb) == insn)
2178 purge_dead_edges (bb);
2181 if (EDGE_COUNT (bb->succs) == 1)
2182 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2186 /* Try to combine the insns I1 and I2 into I3.
2187 Here I1 and I2 appear earlier than I3.
2188 I1 can be zero; then we combine just I2 into I3.
2190 If we are combining three insns and the resulting insn is not recognized,
2191 try splitting it into two insns. If that happens, I2 and I3 are retained
2192 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2195 Return 0 if the combination does not work. Then nothing is changed.
2196 If we did the combination, return the insn at which combine should
2199 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2200 new direct jump instruction. */
2203 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2205 /* New patterns for I3 and I2, respectively. */
2206 rtx newpat, newi2pat = 0;
2207 rtvec newpat_vec_with_clobbers = 0;
2208 int substed_i2 = 0, substed_i1 = 0;
2209 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2210 int added_sets_1, added_sets_2;
2211 /* Total number of SETs to put into I3. */
2213 /* Nonzero if I2's body now appears in I3. */
2215 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2216 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2217 /* Contains I3 if the destination of I3 is used in its source, which means
2218 that the old life of I3 is being killed. If that usage is placed into
2219 I2 and not in I3, a REG_DEAD note must be made. */
2220 rtx i3dest_killed = 0;
2221 /* SET_DEST and SET_SRC of I2 and I1. */
2222 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2223 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2224 rtx i1pat = 0, i2pat = 0;
2225 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2226 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2227 int i2dest_killed = 0, i1dest_killed = 0;
2228 int i1_feeds_i3 = 0;
2229 /* Notes that must be added to REG_NOTES in I3 and I2. */
2230 rtx new_i3_notes, new_i2_notes;
2231 /* Notes that we substituted I3 into I2 instead of the normal case. */
2232 int i3_subst_into_i2 = 0;
2233 /* Notes that I1, I2 or I3 is a MULT operation. */
2236 int changed_i3_dest = 0;
2242 rtx new_other_notes;
2245 /* Exit early if one of the insns involved can't be used for
2247 if (cant_combine_insn_p (i3)
2248 || cant_combine_insn_p (i2)
2249 || (i1 && cant_combine_insn_p (i1))
2250 || likely_spilled_retval_p (i3))
2254 undobuf.other_insn = 0;
2256 /* Reset the hard register usage information. */
2257 CLEAR_HARD_REG_SET (newpat_used_regs);
2259 if (dump_file && (dump_flags & TDF_DETAILS))
2262 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2263 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2265 fprintf (dump_file, "\nTrying %d -> %d:\n",
2266 INSN_UID (i2), INSN_UID (i3));
2269 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2270 code below, set I1 to be the earlier of the two insns. */
2271 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2272 temp = i1, i1 = i2, i2 = temp;
2274 added_links_insn = 0;
2276 /* First check for one important special-case that the code below will
2277 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2278 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2279 we may be able to replace that destination with the destination of I3.
2280 This occurs in the common code where we compute both a quotient and
2281 remainder into a structure, in which case we want to do the computation
2282 directly into the structure to avoid register-register copies.
2284 Note that this case handles both multiple sets in I2 and also
2285 cases where I2 has a number of CLOBBER or PARALLELs.
2287 We make very conservative checks below and only try to handle the
2288 most common cases of this. For example, we only handle the case
2289 where I2 and I3 are adjacent to avoid making difficult register
2292 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2293 && REG_P (SET_SRC (PATTERN (i3)))
2294 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2295 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2296 && GET_CODE (PATTERN (i2)) == PARALLEL
2297 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2298 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2299 below would need to check what is inside (and reg_overlap_mentioned_p
2300 doesn't support those codes anyway). Don't allow those destinations;
2301 the resulting insn isn't likely to be recognized anyway. */
2302 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2303 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2304 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2305 SET_DEST (PATTERN (i3)))
2306 && next_real_insn (i2) == i3)
2308 rtx p2 = PATTERN (i2);
2310 /* Make sure that the destination of I3,
2311 which we are going to substitute into one output of I2,
2312 is not used within another output of I2. We must avoid making this:
2313 (parallel [(set (mem (reg 69)) ...)
2314 (set (reg 69) ...)])
2315 which is not well-defined as to order of actions.
2316 (Besides, reload can't handle output reloads for this.)
2318 The problem can also happen if the dest of I3 is a memory ref,
2319 if another dest in I2 is an indirect memory ref. */
2320 for (i = 0; i < XVECLEN (p2, 0); i++)
2321 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2322 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2323 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2324 SET_DEST (XVECEXP (p2, 0, i))))
2327 if (i == XVECLEN (p2, 0))
2328 for (i = 0; i < XVECLEN (p2, 0); i++)
2329 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2330 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2331 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2336 subst_low_luid = DF_INSN_LUID (i2);
2338 added_sets_2 = added_sets_1 = 0;
2339 i2dest = SET_SRC (PATTERN (i3));
2340 i2dest_killed = dead_or_set_p (i2, i2dest);
2342 /* Replace the dest in I2 with our dest and make the resulting
2343 insn the new pattern for I3. Then skip to where we
2344 validate the pattern. Everything was set up above. */
2345 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2346 SET_DEST (PATTERN (i3)));
2349 i3_subst_into_i2 = 1;
2350 goto validate_replacement;
2354 /* If I2 is setting a pseudo to a constant and I3 is setting some
2355 sub-part of it to another constant, merge them by making a new
2358 && (temp = single_set (i2)) != 0
2359 && (CONST_INT_P (SET_SRC (temp))
2360 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2361 && GET_CODE (PATTERN (i3)) == SET
2362 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2363 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2364 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2366 rtx dest = SET_DEST (PATTERN (i3));
2370 if (GET_CODE (dest) == ZERO_EXTRACT)
2372 if (CONST_INT_P (XEXP (dest, 1))
2373 && CONST_INT_P (XEXP (dest, 2)))
2375 width = INTVAL (XEXP (dest, 1));
2376 offset = INTVAL (XEXP (dest, 2));
2377 dest = XEXP (dest, 0);
2378 if (BITS_BIG_ENDIAN)
2379 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2384 if (GET_CODE (dest) == STRICT_LOW_PART)
2385 dest = XEXP (dest, 0);
2386 width = GET_MODE_BITSIZE (GET_MODE (dest));
2392 /* If this is the low part, we're done. */
2393 if (subreg_lowpart_p (dest))
2395 /* Handle the case where inner is twice the size of outer. */
2396 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2397 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2398 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2399 /* Otherwise give up for now. */
2405 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2406 <= HOST_BITS_PER_WIDE_INT * 2))
2408 HOST_WIDE_INT mhi, ohi, ihi;
2409 HOST_WIDE_INT mlo, olo, ilo;
2410 rtx inner = SET_SRC (PATTERN (i3));
2411 rtx outer = SET_SRC (temp);
2413 if (CONST_INT_P (outer))
2415 olo = INTVAL (outer);
2416 ohi = olo < 0 ? -1 : 0;
2420 olo = CONST_DOUBLE_LOW (outer);
2421 ohi = CONST_DOUBLE_HIGH (outer);
2424 if (CONST_INT_P (inner))
2426 ilo = INTVAL (inner);
2427 ihi = ilo < 0 ? -1 : 0;
2431 ilo = CONST_DOUBLE_LOW (inner);
2432 ihi = CONST_DOUBLE_HIGH (inner);
2435 if (width < HOST_BITS_PER_WIDE_INT)
2437 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2440 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2442 mhi = ((unsigned HOST_WIDE_INT) 1
2443 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2455 if (offset >= HOST_BITS_PER_WIDE_INT)
2457 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2459 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2462 else if (offset > 0)
2464 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2465 >> (HOST_BITS_PER_WIDE_INT - offset));
2466 mlo = mlo << offset;
2467 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2468 >> (HOST_BITS_PER_WIDE_INT - offset));
2469 ilo = ilo << offset;
2472 olo = (olo & ~mlo) | ilo;
2473 ohi = (ohi & ~mhi) | ihi;
2477 subst_low_luid = DF_INSN_LUID (i2);
2478 added_sets_2 = added_sets_1 = 0;
2479 i2dest = SET_DEST (temp);
2480 i2dest_killed = dead_or_set_p (i2, i2dest);
2482 SUBST (SET_SRC (temp),
2483 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2485 newpat = PATTERN (i2);
2486 goto validate_replacement;
2491 /* If we have no I1 and I2 looks like:
2492 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2494 make up a dummy I1 that is
2497 (set (reg:CC X) (compare:CC Y (const_int 0)))
2499 (We can ignore any trailing CLOBBERs.)
2501 This undoes a previous combination and allows us to match a branch-and-
2504 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2505 && XVECLEN (PATTERN (i2), 0) >= 2
2506 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2507 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2509 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2510 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2511 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2512 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2513 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2514 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2516 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2517 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2522 /* We make I1 with the same INSN_UID as I2. This gives it
2523 the same DF_INSN_LUID for value tracking. Our fake I1 will
2524 never appear in the insn stream so giving it the same INSN_UID
2525 as I2 will not cause a problem. */
2527 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2528 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2529 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2531 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2532 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2533 SET_DEST (PATTERN (i1)));
2538 /* Verify that I2 and I1 are valid for combining. */
2539 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2540 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2546 /* Record whether I2DEST is used in I2SRC and similarly for the other
2547 cases. Knowing this will help in register status updating below. */
2548 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2549 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2550 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2551 i2dest_killed = dead_or_set_p (i2, i2dest);
2552 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2554 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2556 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2558 /* Ensure that I3's pattern can be the destination of combines. */
2559 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2560 i1 && i2dest_in_i1src && i1_feeds_i3,
2567 /* See if any of the insns is a MULT operation. Unless one is, we will
2568 reject a combination that is, since it must be slower. Be conservative
2570 if (GET_CODE (i2src) == MULT
2571 || (i1 != 0 && GET_CODE (i1src) == MULT)
2572 || (GET_CODE (PATTERN (i3)) == SET
2573 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2576 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2577 We used to do this EXCEPT in one case: I3 has a post-inc in an
2578 output operand. However, that exception can give rise to insns like
2580 which is a famous insn on the PDP-11 where the value of r3 used as the
2581 source was model-dependent. Avoid this sort of thing. */
2584 if (!(GET_CODE (PATTERN (i3)) == SET
2585 && REG_P (SET_SRC (PATTERN (i3)))
2586 && MEM_P (SET_DEST (PATTERN (i3)))
2587 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2588 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2589 /* It's not the exception. */
2592 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2593 if (REG_NOTE_KIND (link) == REG_INC
2594 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2596 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2603 /* See if the SETs in I1 or I2 need to be kept around in the merged
2604 instruction: whenever the value set there is still needed past I3.
2605 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2607 For the SET in I1, we have two cases: If I1 and I2 independently
2608 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2609 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2610 in I1 needs to be kept around unless I1DEST dies or is set in either
2611 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2612 I1DEST. If so, we know I1 feeds into I2. */
2614 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2617 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2618 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2620 /* If the set in I2 needs to be kept around, we must make a copy of
2621 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2622 PATTERN (I2), we are only substituting for the original I1DEST, not into
2623 an already-substituted copy. This also prevents making self-referential
2624 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2629 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2630 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2632 i2pat = copy_rtx (PATTERN (i2));
2637 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2638 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2640 i1pat = copy_rtx (PATTERN (i1));
2645 /* Substitute in the latest insn for the regs set by the earlier ones. */
2647 maxreg = max_reg_num ();
2652 /* Many machines that don't use CC0 have insns that can both perform an
2653 arithmetic operation and set the condition code. These operations will
2654 be represented as a PARALLEL with the first element of the vector
2655 being a COMPARE of an arithmetic operation with the constant zero.
2656 The second element of the vector will set some pseudo to the result
2657 of the same arithmetic operation. If we simplify the COMPARE, we won't
2658 match such a pattern and so will generate an extra insn. Here we test
2659 for this case, where both the comparison and the operation result are
2660 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2661 I2SRC. Later we will make the PARALLEL that contains I2. */
2663 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2664 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2665 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2666 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2668 #ifdef SELECT_CC_MODE
2670 enum machine_mode compare_mode;
2673 newpat = PATTERN (i3);
2674 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2678 #ifdef SELECT_CC_MODE
2679 /* See if a COMPARE with the operand we substituted in should be done
2680 with the mode that is currently being used. If not, do the same
2681 processing we do in `subst' for a SET; namely, if the destination
2682 is used only once, try to replace it with a register of the proper
2683 mode and also replace the COMPARE. */
2684 if (undobuf.other_insn == 0
2685 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2686 &undobuf.other_insn))
2687 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2689 != GET_MODE (SET_DEST (newpat))))
2691 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2694 unsigned int regno = REGNO (SET_DEST (newpat));
2697 if (regno < FIRST_PSEUDO_REGISTER)
2698 new_dest = gen_rtx_REG (compare_mode, regno);
2701 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2702 new_dest = regno_reg_rtx[regno];
2705 SUBST (SET_DEST (newpat), new_dest);
2706 SUBST (XEXP (*cc_use, 0), new_dest);
2707 SUBST (SET_SRC (newpat),
2708 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2711 undobuf.other_insn = 0;
2718 /* It is possible that the source of I2 or I1 may be performing
2719 an unneeded operation, such as a ZERO_EXTEND of something
2720 that is known to have the high part zero. Handle that case
2721 by letting subst look at the innermost one of them.
2723 Another way to do this would be to have a function that tries
2724 to simplify a single insn instead of merging two or more
2725 insns. We don't do this because of the potential of infinite
2726 loops and because of the potential extra memory required.
2727 However, doing it the way we are is a bit of a kludge and
2728 doesn't catch all cases.
2730 But only do this if -fexpensive-optimizations since it slows
2731 things down and doesn't usually win.
2733 This is not done in the COMPARE case above because the
2734 unmodified I2PAT is used in the PARALLEL and so a pattern
2735 with a modified I2SRC would not match. */
2737 if (flag_expensive_optimizations)
2739 /* Pass pc_rtx so no substitutions are done, just
2743 subst_low_luid = DF_INSN_LUID (i1);
2744 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2748 subst_low_luid = DF_INSN_LUID (i2);
2749 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2753 n_occurrences = 0; /* `subst' counts here */
2755 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2756 need to make a unique copy of I2SRC each time we substitute it
2757 to avoid self-referential rtl. */
2759 subst_low_luid = DF_INSN_LUID (i2);
2760 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2761 ! i1_feeds_i3 && i1dest_in_i1src);
2764 /* Record whether i2's body now appears within i3's body. */
2765 i2_is_used = n_occurrences;
2768 /* If we already got a failure, don't try to do more. Otherwise,
2769 try to substitute in I1 if we have it. */
2771 if (i1 && GET_CODE (newpat) != CLOBBER)
2773 /* Check that an autoincrement side-effect on I1 has not been lost.
2774 This happens if I1DEST is mentioned in I2 and dies there, and
2775 has disappeared from the new pattern. */
2776 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2778 && dead_or_set_p (i2, i1dest)
2779 && !reg_overlap_mentioned_p (i1dest, newpat))
2780 /* Before we can do this substitution, we must redo the test done
2781 above (see detailed comments there) that ensures that I1DEST
2782 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2783 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2790 subst_low_luid = DF_INSN_LUID (i1);
2791 newpat = subst (newpat, i1dest, i1src, 0, 0);
2795 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2796 to count all the ways that I2SRC and I1SRC can be used. */
2797 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2798 && i2_is_used + added_sets_2 > 1)
2799 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2800 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2802 /* Fail if we tried to make a new register. */
2803 || max_reg_num () != maxreg
2804 /* Fail if we couldn't do something and have a CLOBBER. */
2805 || GET_CODE (newpat) == CLOBBER
2806 /* Fail if this new pattern is a MULT and we didn't have one before
2807 at the outer level. */
2808 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2815 /* If the actions of the earlier insns must be kept
2816 in addition to substituting them into the latest one,
2817 we must make a new PARALLEL for the latest insn
2818 to hold additional the SETs. */
2820 if (added_sets_1 || added_sets_2)
2824 if (GET_CODE (newpat) == PARALLEL)
2826 rtvec old = XVEC (newpat, 0);
2827 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2828 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2829 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2830 sizeof (old->elem[0]) * old->num_elem);
2835 total_sets = 1 + added_sets_1 + added_sets_2;
2836 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2837 XVECEXP (newpat, 0, 0) = old;
2841 XVECEXP (newpat, 0, --total_sets) = i1pat;
2845 /* If there is no I1, use I2's body as is. We used to also not do
2846 the subst call below if I2 was substituted into I3,
2847 but that could lose a simplification. */
2849 XVECEXP (newpat, 0, --total_sets) = i2pat;
2851 /* See comment where i2pat is assigned. */
2852 XVECEXP (newpat, 0, --total_sets)
2853 = subst (i2pat, i1dest, i1src, 0, 0);
2857 /* We come here when we are replacing a destination in I2 with the
2858 destination of I3. */
2859 validate_replacement:
2861 /* Note which hard regs this insn has as inputs. */
2862 mark_used_regs_combine (newpat);
2864 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2865 consider splitting this pattern, we might need these clobbers. */
2866 if (i1 && GET_CODE (newpat) == PARALLEL
2867 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2869 int len = XVECLEN (newpat, 0);
2871 newpat_vec_with_clobbers = rtvec_alloc (len);
2872 for (i = 0; i < len; i++)
2873 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2876 /* Is the result of combination a valid instruction? */
2877 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2879 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2880 the second SET's destination is a register that is unused and isn't
2881 marked as an instruction that might trap in an EH region. In that case,
2882 we just need the first SET. This can occur when simplifying a divmod
2883 insn. We *must* test for this case here because the code below that
2884 splits two independent SETs doesn't handle this case correctly when it
2885 updates the register status.
2887 It's pointless doing this if we originally had two sets, one from
2888 i3, and one from i2. Combining then splitting the parallel results
2889 in the original i2 again plus an invalid insn (which we delete).
2890 The net effect is only to move instructions around, which makes
2891 debug info less accurate.
2893 Also check the case where the first SET's destination is unused.
2894 That would not cause incorrect code, but does cause an unneeded
2897 if (insn_code_number < 0
2898 && !(added_sets_2 && i1 == 0)
2899 && GET_CODE (newpat) == PARALLEL
2900 && XVECLEN (newpat, 0) == 2
2901 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2902 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2903 && asm_noperands (newpat) < 0)
2905 rtx set0 = XVECEXP (newpat, 0, 0);
2906 rtx set1 = XVECEXP (newpat, 0, 1);
2909 if (((REG_P (SET_DEST (set1))
2910 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2911 || (GET_CODE (SET_DEST (set1)) == SUBREG
2912 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2913 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2914 || INTVAL (XEXP (note, 0)) <= 0)
2915 && ! side_effects_p (SET_SRC (set1)))
2918 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2921 else if (((REG_P (SET_DEST (set0))
2922 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2923 || (GET_CODE (SET_DEST (set0)) == SUBREG
2924 && find_reg_note (i3, REG_UNUSED,
2925 SUBREG_REG (SET_DEST (set0)))))
2926 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2927 || INTVAL (XEXP (note, 0)) <= 0)
2928 && ! side_effects_p (SET_SRC (set0)))
2931 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2933 if (insn_code_number >= 0)
2934 changed_i3_dest = 1;
2938 /* If we were combining three insns and the result is a simple SET
2939 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2940 insns. There are two ways to do this. It can be split using a
2941 machine-specific method (like when you have an addition of a large
2942 constant) or by combine in the function find_split_point. */
2944 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2945 && asm_noperands (newpat) < 0)
2947 rtx parallel, m_split, *split;
2949 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2950 use I2DEST as a scratch register will help. In the latter case,
2951 convert I2DEST to the mode of the source of NEWPAT if we can. */
2953 m_split = combine_split_insns (newpat, i3);
2955 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2956 inputs of NEWPAT. */
2958 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2959 possible to try that as a scratch reg. This would require adding
2960 more code to make it work though. */
2962 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2964 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2966 /* First try to split using the original register as a
2967 scratch register. */
2968 parallel = gen_rtx_PARALLEL (VOIDmode,
2969 gen_rtvec (2, newpat,
2970 gen_rtx_CLOBBER (VOIDmode,
2972 m_split = combine_split_insns (parallel, i3);
2974 /* If that didn't work, try changing the mode of I2DEST if
2977 && new_mode != GET_MODE (i2dest)
2978 && new_mode != VOIDmode
2979 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2981 enum machine_mode old_mode = GET_MODE (i2dest);
2984 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2985 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2988 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2989 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2992 parallel = (gen_rtx_PARALLEL
2994 gen_rtvec (2, newpat,
2995 gen_rtx_CLOBBER (VOIDmode,
2997 m_split = combine_split_insns (parallel, i3);
3000 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3004 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3005 buf = undobuf.undos;
3006 undobuf.undos = buf->next;
3007 buf->next = undobuf.frees;
3008 undobuf.frees = buf;
3013 /* If recog_for_combine has discarded clobbers, try to use them
3014 again for the split. */
3015 if (m_split == 0 && newpat_vec_with_clobbers)
3017 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3018 m_split = combine_split_insns (parallel, i3);
3021 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3023 m_split = PATTERN (m_split);
3024 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3025 if (insn_code_number >= 0)
3028 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3029 && (next_real_insn (i2) == i3
3030 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3033 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3034 newi2pat = PATTERN (m_split);
3036 i3set = single_set (NEXT_INSN (m_split));
3037 i2set = single_set (m_split);
3039 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3041 /* If I2 or I3 has multiple SETs, we won't know how to track
3042 register status, so don't use these insns. If I2's destination
3043 is used between I2 and I3, we also can't use these insns. */
3045 if (i2_code_number >= 0 && i2set && i3set
3046 && (next_real_insn (i2) == i3
3047 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3048 insn_code_number = recog_for_combine (&newi3pat, i3,
3050 if (insn_code_number >= 0)
3053 /* It is possible that both insns now set the destination of I3.
3054 If so, we must show an extra use of it. */
3056 if (insn_code_number >= 0)
3058 rtx new_i3_dest = SET_DEST (i3set);
3059 rtx new_i2_dest = SET_DEST (i2set);
3061 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3062 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3063 || GET_CODE (new_i3_dest) == SUBREG)
3064 new_i3_dest = XEXP (new_i3_dest, 0);
3066 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3067 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3068 || GET_CODE (new_i2_dest) == SUBREG)
3069 new_i2_dest = XEXP (new_i2_dest, 0);
3071 if (REG_P (new_i3_dest)
3072 && REG_P (new_i2_dest)
3073 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3074 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3078 /* If we can split it and use I2DEST, go ahead and see if that
3079 helps things be recognized. Verify that none of the registers
3080 are set between I2 and I3. */
3081 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3085 /* We need I2DEST in the proper mode. If it is a hard register
3086 or the only use of a pseudo, we can change its mode.
3087 Make sure we don't change a hard register to have a mode that
3088 isn't valid for it, or change the number of registers. */
3089 && (GET_MODE (*split) == GET_MODE (i2dest)
3090 || GET_MODE (*split) == VOIDmode
3091 || can_change_dest_mode (i2dest, added_sets_2,
3093 && (next_real_insn (i2) == i3
3094 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3095 /* We can't overwrite I2DEST if its value is still used by
3097 && ! reg_referenced_p (i2dest, newpat))
3099 rtx newdest = i2dest;
3100 enum rtx_code split_code = GET_CODE (*split);
3101 enum machine_mode split_mode = GET_MODE (*split);
3102 bool subst_done = false;
3103 newi2pat = NULL_RTX;
3105 /* Get NEWDEST as a register in the proper mode. We have already
3106 validated that we can do this. */
3107 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3109 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3110 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3113 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3114 newdest = regno_reg_rtx[REGNO (i2dest)];
3118 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3119 an ASHIFT. This can occur if it was inside a PLUS and hence
3120 appeared to be a memory address. This is a kludge. */
3121 if (split_code == MULT
3122 && CONST_INT_P (XEXP (*split, 1))
3123 && INTVAL (XEXP (*split, 1)) > 0
3124 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3126 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3127 XEXP (*split, 0), GEN_INT (i)));
3128 /* Update split_code because we may not have a multiply
3130 split_code = GET_CODE (*split);
3133 #ifdef INSN_SCHEDULING
3134 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3135 be written as a ZERO_EXTEND. */
3136 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3138 #ifdef LOAD_EXTEND_OP
3139 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3140 what it really is. */
3141 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3143 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3144 SUBREG_REG (*split)));
3147 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3148 SUBREG_REG (*split)));
3152 /* Attempt to split binary operators using arithmetic identities. */
3153 if (BINARY_P (SET_SRC (newpat))
3154 && split_mode == GET_MODE (SET_SRC (newpat))
3155 && ! side_effects_p (SET_SRC (newpat)))
3157 rtx setsrc = SET_SRC (newpat);
3158 enum machine_mode mode = GET_MODE (setsrc);
3159 enum rtx_code code = GET_CODE (setsrc);
3160 rtx src_op0 = XEXP (setsrc, 0);
3161 rtx src_op1 = XEXP (setsrc, 1);
3163 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3164 if (rtx_equal_p (src_op0, src_op1))
3166 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3167 SUBST (XEXP (setsrc, 0), newdest);
3168 SUBST (XEXP (setsrc, 1), newdest);
3171 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3172 else if ((code == PLUS || code == MULT)
3173 && GET_CODE (src_op0) == code
3174 && GET_CODE (XEXP (src_op0, 0)) == code
3175 && (INTEGRAL_MODE_P (mode)
3176 || (FLOAT_MODE_P (mode)
3177 && flag_unsafe_math_optimizations)))
3179 rtx p = XEXP (XEXP (src_op0, 0), 0);
3180 rtx q = XEXP (XEXP (src_op0, 0), 1);
3181 rtx r = XEXP (src_op0, 1);
3184 /* Split both "((X op Y) op X) op Y" and
3185 "((X op Y) op Y) op X" as "T op T" where T is
3187 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3188 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3190 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3192 SUBST (XEXP (setsrc, 0), newdest);
3193 SUBST (XEXP (setsrc, 1), newdest);
3196 /* Split "((X op X) op Y) op Y)" as "T op T" where
3198 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3200 rtx tmp = simplify_gen_binary (code, mode, p, r);
3201 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3202 SUBST (XEXP (setsrc, 0), newdest);
3203 SUBST (XEXP (setsrc, 1), newdest);
3211 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3212 SUBST (*split, newdest);
3215 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3217 /* recog_for_combine might have added CLOBBERs to newi2pat.
3218 Make sure NEWPAT does not depend on the clobbered regs. */
3219 if (GET_CODE (newi2pat) == PARALLEL)
3220 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3221 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3223 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3224 if (reg_overlap_mentioned_p (reg, newpat))
3231 /* If the split point was a MULT and we didn't have one before,
3232 don't use one now. */
3233 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3234 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3238 /* Check for a case where we loaded from memory in a narrow mode and
3239 then sign extended it, but we need both registers. In that case,
3240 we have a PARALLEL with both loads from the same memory location.
3241 We can split this into a load from memory followed by a register-register
3242 copy. This saves at least one insn, more if register allocation can
3245 We cannot do this if the destination of the first assignment is a
3246 condition code register or cc0. We eliminate this case by making sure
3247 the SET_DEST and SET_SRC have the same mode.
3249 We cannot do this if the destination of the second assignment is
3250 a register that we have already assumed is zero-extended. Similarly
3251 for a SUBREG of such a register. */
3253 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3254 && GET_CODE (newpat) == PARALLEL
3255 && XVECLEN (newpat, 0) == 2
3256 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3257 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3258 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3259 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3260 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3261 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3262 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3263 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3265 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3266 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3267 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3269 && VEC_index (reg_stat_type, reg_stat,
3270 REGNO (temp))->nonzero_bits != 0
3271 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3272 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3273 && (VEC_index (reg_stat_type, reg_stat,
3274 REGNO (temp))->nonzero_bits
3275 != GET_MODE_MASK (word_mode))))
3276 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3277 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3279 && VEC_index (reg_stat_type, reg_stat,
3280 REGNO (temp))->nonzero_bits != 0
3281 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3282 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3283 && (VEC_index (reg_stat_type, reg_stat,
3284 REGNO (temp))->nonzero_bits
3285 != GET_MODE_MASK (word_mode)))))
3286 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3287 SET_SRC (XVECEXP (newpat, 0, 1)))
3288 && ! find_reg_note (i3, REG_UNUSED,
3289 SET_DEST (XVECEXP (newpat, 0, 0))))
3293 newi2pat = XVECEXP (newpat, 0, 0);
3294 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3295 newpat = XVECEXP (newpat, 0, 1);
3296 SUBST (SET_SRC (newpat),
3297 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3298 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3300 if (i2_code_number >= 0)
3301 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3303 if (insn_code_number >= 0)
3307 /* Similarly, check for a case where we have a PARALLEL of two independent
3308 SETs but we started with three insns. In this case, we can do the sets
3309 as two separate insns. This case occurs when some SET allows two
3310 other insns to combine, but the destination of that SET is still live. */
3312 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3313 && GET_CODE (newpat) == PARALLEL
3314 && XVECLEN (newpat, 0) == 2
3315 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3316 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3317 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3318 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3319 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3320 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3321 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3323 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3324 XVECEXP (newpat, 0, 0))
3325 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3326 XVECEXP (newpat, 0, 1))
3327 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3328 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3330 /* We cannot split the parallel into two sets if both sets
3332 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3333 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3337 /* Normally, it doesn't matter which of the two is done first,
3338 but it does if one references cc0. In that case, it has to
3341 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3343 newi2pat = XVECEXP (newpat, 0, 0);
3344 newpat = XVECEXP (newpat, 0, 1);
3349 newi2pat = XVECEXP (newpat, 0, 1);
3350 newpat = XVECEXP (newpat, 0, 0);
3353 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3355 if (i2_code_number >= 0)
3356 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3359 /* If it still isn't recognized, fail and change things back the way they
3361 if ((insn_code_number < 0
3362 /* Is the result a reasonable ASM_OPERANDS? */
3363 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3369 /* If we had to change another insn, make sure it is valid also. */
3370 if (undobuf.other_insn)
3372 CLEAR_HARD_REG_SET (newpat_used_regs);
3374 other_pat = PATTERN (undobuf.other_insn);
3375 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3378 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3386 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3387 they are adjacent to each other or not. */
3389 rtx p = prev_nonnote_insn (i3);
3390 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3391 && sets_cc0_p (newi2pat))
3399 /* Only allow this combination if insn_rtx_costs reports that the
3400 replacement instructions are cheaper than the originals. */
3401 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3407 /* If we will be able to accept this, we have made a
3408 change to the destination of I3. This requires us to
3409 do a few adjustments. */
3411 if (changed_i3_dest)
3413 PATTERN (i3) = newpat;
3414 adjust_for_new_dest (i3);
3417 /* We now know that we can do this combination. Merge the insns and
3418 update the status of registers and LOG_LINKS. */
3420 if (undobuf.other_insn)
3424 PATTERN (undobuf.other_insn) = other_pat;
3426 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3427 are still valid. Then add any non-duplicate notes added by
3428 recog_for_combine. */
3429 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3431 next = XEXP (note, 1);
3433 if (REG_NOTE_KIND (note) == REG_UNUSED
3434 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3435 remove_note (undobuf.other_insn, note);
3438 distribute_notes (new_other_notes, undobuf.other_insn,
3439 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3448 /* I3 now uses what used to be its destination and which is now
3449 I2's destination. This requires us to do a few adjustments. */
3450 PATTERN (i3) = newpat;
3451 adjust_for_new_dest (i3);
3453 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3456 However, some later insn might be using I2's dest and have
3457 a LOG_LINK pointing at I3. We must remove this link.
3458 The simplest way to remove the link is to point it at I1,
3459 which we know will be a NOTE. */
3461 /* newi2pat is usually a SET here; however, recog_for_combine might
3462 have added some clobbers. */
3463 if (GET_CODE (newi2pat) == PARALLEL)
3464 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3466 ni2dest = SET_DEST (newi2pat);
3468 for (insn = NEXT_INSN (i3);
3469 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3470 || insn != BB_HEAD (this_basic_block->next_bb));
3471 insn = NEXT_INSN (insn))
3473 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3475 for (link = LOG_LINKS (insn); link;
3476 link = XEXP (link, 1))
3477 if (XEXP (link, 0) == i3)
3478 XEXP (link, 0) = i1;
3486 rtx i3notes, i2notes, i1notes = 0;
3487 rtx i3links, i2links, i1links = 0;
3490 /* Compute which registers we expect to eliminate. newi2pat may be setting
3491 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3492 same as i3dest, in which case newi2pat may be setting i1dest. */
3493 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3494 || i2dest_in_i2src || i2dest_in_i1src
3497 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3498 || (newi2pat && reg_set_p (i1dest, newi2pat))
3502 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3504 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3505 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3507 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3509 /* Ensure that we do not have something that should not be shared but
3510 occurs multiple times in the new insns. Check this by first
3511 resetting all the `used' flags and then copying anything is shared. */
3513 reset_used_flags (i3notes);
3514 reset_used_flags (i2notes);
3515 reset_used_flags (i1notes);
3516 reset_used_flags (newpat);
3517 reset_used_flags (newi2pat);
3518 if (undobuf.other_insn)
3519 reset_used_flags (PATTERN (undobuf.other_insn));
3521 i3notes = copy_rtx_if_shared (i3notes);
3522 i2notes = copy_rtx_if_shared (i2notes);
3523 i1notes = copy_rtx_if_shared (i1notes);
3524 newpat = copy_rtx_if_shared (newpat);
3525 newi2pat = copy_rtx_if_shared (newi2pat);
3526 if (undobuf.other_insn)
3527 reset_used_flags (PATTERN (undobuf.other_insn));
3529 INSN_CODE (i3) = insn_code_number;
3530 PATTERN (i3) = newpat;
3532 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3534 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3536 reset_used_flags (call_usage);
3537 call_usage = copy_rtx (call_usage);
3540 replace_rtx (call_usage, i2dest, i2src);
3543 replace_rtx (call_usage, i1dest, i1src);
3545 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3548 if (undobuf.other_insn)
3549 INSN_CODE (undobuf.other_insn) = other_code_number;
3551 /* We had one special case above where I2 had more than one set and
3552 we replaced a destination of one of those sets with the destination
3553 of I3. In that case, we have to update LOG_LINKS of insns later
3554 in this basic block. Note that this (expensive) case is rare.
3556 Also, in this case, we must pretend that all REG_NOTEs for I2
3557 actually came from I3, so that REG_UNUSED notes from I2 will be
3558 properly handled. */
3560 if (i3_subst_into_i2)
3562 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3563 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3564 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3565 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3566 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3567 && ! find_reg_note (i2, REG_UNUSED,
3568 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3569 for (temp = NEXT_INSN (i2);
3570 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3571 || BB_HEAD (this_basic_block) != temp);
3572 temp = NEXT_INSN (temp))
3573 if (temp != i3 && INSN_P (temp))
3574 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3575 if (XEXP (link, 0) == i2)
3576 XEXP (link, 0) = i3;
3581 while (XEXP (link, 1))
3582 link = XEXP (link, 1);
3583 XEXP (link, 1) = i2notes;
3597 INSN_CODE (i2) = i2_code_number;
3598 PATTERN (i2) = newi2pat;
3601 SET_INSN_DELETED (i2);
3607 SET_INSN_DELETED (i1);
3610 /* Get death notes for everything that is now used in either I3 or
3611 I2 and used to die in a previous insn. If we built two new
3612 patterns, move from I1 to I2 then I2 to I3 so that we get the
3613 proper movement on registers that I2 modifies. */
3617 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3618 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3621 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3624 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3626 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3629 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3632 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3635 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3638 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3639 know these are REG_UNUSED and want them to go to the desired insn,
3640 so we always pass it as i3. */
3642 if (newi2pat && new_i2_notes)
3643 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3646 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3648 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3649 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3650 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3651 in that case, it might delete I2. Similarly for I2 and I1.
3652 Show an additional death due to the REG_DEAD note we make here. If
3653 we discard it in distribute_notes, we will decrement it again. */
3657 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3658 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3660 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3662 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3664 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3668 if (i2dest_in_i2src)
3670 if (newi2pat && reg_set_p (i2dest, newi2pat))
3671 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3672 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3674 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3675 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3676 NULL_RTX, NULL_RTX);
3679 if (i1dest_in_i1src)
3681 if (newi2pat && reg_set_p (i1dest, newi2pat))
3682 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3683 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3685 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3686 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3687 NULL_RTX, NULL_RTX);
3690 distribute_links (i3links);
3691 distribute_links (i2links);
3692 distribute_links (i1links);
3697 rtx i2_insn = 0, i2_val = 0, set;
3699 /* The insn that used to set this register doesn't exist, and
3700 this life of the register may not exist either. See if one of
3701 I3's links points to an insn that sets I2DEST. If it does,
3702 that is now the last known value for I2DEST. If we don't update
3703 this and I2 set the register to a value that depended on its old
3704 contents, we will get confused. If this insn is used, thing
3705 will be set correctly in combine_instructions. */
3707 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3708 if ((set = single_set (XEXP (link, 0))) != 0
3709 && rtx_equal_p (i2dest, SET_DEST (set)))
3710 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3712 record_value_for_reg (i2dest, i2_insn, i2_val);
3714 /* If the reg formerly set in I2 died only once and that was in I3,
3715 zero its use count so it won't make `reload' do any work. */
3717 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3718 && ! i2dest_in_i2src)
3720 regno = REGNO (i2dest);
3721 INC_REG_N_SETS (regno, -1);
3725 if (i1 && REG_P (i1dest))
3728 rtx i1_insn = 0, i1_val = 0, set;
3730 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3731 if ((set = single_set (XEXP (link, 0))) != 0
3732 && rtx_equal_p (i1dest, SET_DEST (set)))
3733 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3735 record_value_for_reg (i1dest, i1_insn, i1_val);
3737 regno = REGNO (i1dest);
3738 if (! added_sets_1 && ! i1dest_in_i1src)
3739 INC_REG_N_SETS (regno, -1);
3742 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3743 been made to this insn. The order of
3744 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3745 can affect nonzero_bits of newpat */
3747 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3748 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3751 if (undobuf.other_insn != NULL_RTX)
3755 fprintf (dump_file, "modifying other_insn ");
3756 dump_insn_slim (dump_file, undobuf.other_insn);
3758 df_insn_rescan (undobuf.other_insn);
3761 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3765 fprintf (dump_file, "modifying insn i1 ");
3766 dump_insn_slim (dump_file, i1);
3768 df_insn_rescan (i1);
3771 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3775 fprintf (dump_file, "modifying insn i2 ");
3776 dump_insn_slim (dump_file, i2);
3778 df_insn_rescan (i2);
3781 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3785 fprintf (dump_file, "modifying insn i3 ");
3786 dump_insn_slim (dump_file, i3);
3788 df_insn_rescan (i3);
3791 /* Set new_direct_jump_p if a new return or simple jump instruction
3792 has been created. Adjust the CFG accordingly. */
3794 if (returnjump_p (i3) || any_uncondjump_p (i3))
3796 *new_direct_jump_p = 1;
3797 mark_jump_label (PATTERN (i3), i3, 0);
3798 update_cfg_for_uncondjump (i3);
3801 if (undobuf.other_insn != NULL_RTX
3802 && (returnjump_p (undobuf.other_insn)
3803 || any_uncondjump_p (undobuf.other_insn)))
3805 *new_direct_jump_p = 1;
3806 update_cfg_for_uncondjump (undobuf.other_insn);
3809 /* A noop might also need cleaning up of CFG, if it comes from the
3810 simplification of a jump. */
3811 if (GET_CODE (newpat) == SET
3812 && SET_SRC (newpat) == pc_rtx
3813 && SET_DEST (newpat) == pc_rtx)
3815 *new_direct_jump_p = 1;
3816 update_cfg_for_uncondjump (i3);
3819 combine_successes++;
3822 if (added_links_insn
3823 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3824 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3825 return added_links_insn;
3827 return newi2pat ? i2 : i3;
3830 /* Undo all the modifications recorded in undobuf. */
3835 struct undo *undo, *next;
3837 for (undo = undobuf.undos; undo; undo = next)
3843 *undo->where.r = undo->old_contents.r;
3846 *undo->where.i = undo->old_contents.i;
3849 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3855 undo->next = undobuf.frees;
3856 undobuf.frees = undo;
3862 /* We've committed to accepting the changes we made. Move all
3863 of the undos to the free list. */
3868 struct undo *undo, *next;
3870 for (undo = undobuf.undos; undo; undo = next)
3873 undo->next = undobuf.frees;
3874 undobuf.frees = undo;
3879 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3880 where we have an arithmetic expression and return that point. LOC will
3883 try_combine will call this function to see if an insn can be split into
3887 find_split_point (rtx *loc, rtx insn)
3890 enum rtx_code code = GET_CODE (x);
3892 unsigned HOST_WIDE_INT len = 0;
3893 HOST_WIDE_INT pos = 0;
3895 rtx inner = NULL_RTX;
3897 /* First special-case some codes. */
3901 #ifdef INSN_SCHEDULING
3902 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3904 if (MEM_P (SUBREG_REG (x)))
3907 return find_split_point (&SUBREG_REG (x), insn);
3911 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3912 using LO_SUM and HIGH. */
3913 if (GET_CODE (XEXP (x, 0)) == CONST
3914 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3917 gen_rtx_LO_SUM (Pmode,
3918 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3920 return &XEXP (XEXP (x, 0), 0);
3924 /* If we have a PLUS whose second operand is a constant and the
3925 address is not valid, perhaps will can split it up using
3926 the machine-specific way to split large constants. We use
3927 the first pseudo-reg (one of the virtual regs) as a placeholder;
3928 it will not remain in the result. */
3929 if (GET_CODE (XEXP (x, 0)) == PLUS
3930 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3931 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3933 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3934 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3938 /* This should have produced two insns, each of which sets our
3939 placeholder. If the source of the second is a valid address,
3940 we can make put both sources together and make a split point
3944 && NEXT_INSN (seq) != NULL_RTX
3945 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3946 && NONJUMP_INSN_P (seq)
3947 && GET_CODE (PATTERN (seq)) == SET
3948 && SET_DEST (PATTERN (seq)) == reg
3949 && ! reg_mentioned_p (reg,
3950 SET_SRC (PATTERN (seq)))
3951 && NONJUMP_INSN_P (NEXT_INSN (seq))
3952 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3953 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3954 && memory_address_p (GET_MODE (x),
3955 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3957 rtx src1 = SET_SRC (PATTERN (seq));
3958 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3960 /* Replace the placeholder in SRC2 with SRC1. If we can
3961 find where in SRC2 it was placed, that can become our
3962 split point and we can replace this address with SRC2.
3963 Just try two obvious places. */
3965 src2 = replace_rtx (src2, reg, src1);
3967 if (XEXP (src2, 0) == src1)
3968 split = &XEXP (src2, 0);
3969 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3970 && XEXP (XEXP (src2, 0), 0) == src1)
3971 split = &XEXP (XEXP (src2, 0), 0);
3975 SUBST (XEXP (x, 0), src2);
3980 /* If that didn't work, perhaps the first operand is complex and
3981 needs to be computed separately, so make a split point there.
3982 This will occur on machines that just support REG + CONST
3983 and have a constant moved through some previous computation. */
3985 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3986 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3987 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3988 return &XEXP (XEXP (x, 0), 0);
3991 /* If we have a PLUS whose first operand is complex, try computing it
3992 separately by making a split there. */
3993 if (GET_CODE (XEXP (x, 0)) == PLUS
3994 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3995 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3996 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3997 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3998 return &XEXP (XEXP (x, 0), 0);
4003 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4004 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4005 we need to put the operand into a register. So split at that
4008 if (SET_DEST (x) == cc0_rtx
4009 && GET_CODE (SET_SRC (x)) != COMPARE
4010 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4011 && !OBJECT_P (SET_SRC (x))
4012 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4013 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4014 return &SET_SRC (x);
4017 /* See if we can split SET_SRC as it stands. */
4018 split = find_split_point (&SET_SRC (x), insn);
4019 if (split && split != &SET_SRC (x))
4022 /* See if we can split SET_DEST as it stands. */
4023 split = find_split_point (&SET_DEST (x), insn);
4024 if (split && split != &SET_DEST (x))
4027 /* See if this is a bitfield assignment with everything constant. If
4028 so, this is an IOR of an AND, so split it into that. */
4029 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4030 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4031 <= HOST_BITS_PER_WIDE_INT)
4032 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4033 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4034 && CONST_INT_P (SET_SRC (x))
4035 && ((INTVAL (XEXP (SET_DEST (x), 1))
4036 + INTVAL (XEXP (SET_DEST (x), 2)))
4037 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4038 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4040 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4041 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4042 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4043 rtx dest = XEXP (SET_DEST (x), 0);
4044 enum machine_mode mode = GET_MODE (dest);
4045 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4048 if (BITS_BIG_ENDIAN)
4049 pos = GET_MODE_BITSIZE (mode) - len - pos;
4051 or_mask = gen_int_mode (src << pos, mode);
4054 simplify_gen_binary (IOR, mode, dest, or_mask));
4057 rtx negmask = gen_int_mode (~(mask << pos), mode);
4059 simplify_gen_binary (IOR, mode,
4060 simplify_gen_binary (AND, mode,
4065 SUBST (SET_DEST (x), dest);
4067 split = find_split_point (&SET_SRC (x), insn);
4068 if (split && split != &SET_SRC (x))
4072 /* Otherwise, see if this is an operation that we can split into two.
4073 If so, try to split that. */
4074 code = GET_CODE (SET_SRC (x));
4079 /* If we are AND'ing with a large constant that is only a single
4080 bit and the result is only being used in a context where we
4081 need to know if it is zero or nonzero, replace it with a bit
4082 extraction. This will avoid the large constant, which might
4083 have taken more than one insn to make. If the constant were
4084 not a valid argument to the AND but took only one insn to make,
4085 this is no worse, but if it took more than one insn, it will
4088 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4089 && REG_P (XEXP (SET_SRC (x), 0))
4090 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4091 && REG_P (SET_DEST (x))
4092 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4093 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4094 && XEXP (*split, 0) == SET_DEST (x)
4095 && XEXP (*split, 1) == const0_rtx)
4097 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4098 XEXP (SET_SRC (x), 0),
4099 pos, NULL_RTX, 1, 1, 0, 0);
4100 if (extraction != 0)
4102 SUBST (SET_SRC (x), extraction);
4103 return find_split_point (loc, insn);
4109 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4110 is known to be on, this can be converted into a NEG of a shift. */
4111 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4112 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4113 && 1 <= (pos = exact_log2
4114 (nonzero_bits (XEXP (SET_SRC (x), 0),
4115 GET_MODE (XEXP (SET_SRC (x), 0))))))
4117 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4121 gen_rtx_LSHIFTRT (mode,
4122 XEXP (SET_SRC (x), 0),
4125 split = find_split_point (&SET_SRC (x), insn);
4126 if (split && split != &SET_SRC (x))
4132 inner = XEXP (SET_SRC (x), 0);
4134 /* We can't optimize if either mode is a partial integer
4135 mode as we don't know how many bits are significant
4137 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4138 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4142 len = GET_MODE_BITSIZE (GET_MODE (inner));
4148 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4149 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4151 inner = XEXP (SET_SRC (x), 0);
4152 len = INTVAL (XEXP (SET_SRC (x), 1));
4153 pos = INTVAL (XEXP (SET_SRC (x), 2));
4155 if (BITS_BIG_ENDIAN)
4156 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4157 unsignedp = (code == ZERO_EXTRACT);
4165 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4167 enum machine_mode mode = GET_MODE (SET_SRC (x));
4169 /* For unsigned, we have a choice of a shift followed by an
4170 AND or two shifts. Use two shifts for field sizes where the
4171 constant might be too large. We assume here that we can
4172 always at least get 8-bit constants in an AND insn, which is
4173 true for every current RISC. */
4175 if (unsignedp && len <= 8)
4180 (mode, gen_lowpart (mode, inner),
4182 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4184 split = find_split_point (&SET_SRC (x), insn);
4185 if (split && split != &SET_SRC (x))
4192 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4193 gen_rtx_ASHIFT (mode,
4194 gen_lowpart (mode, inner),
4195 GEN_INT (GET_MODE_BITSIZE (mode)
4197 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4199 split = find_split_point (&SET_SRC (x), insn);
4200 if (split && split != &SET_SRC (x))
4205 /* See if this is a simple operation with a constant as the second
4206 operand. It might be that this constant is out of range and hence
4207 could be used as a split point. */
4208 if (BINARY_P (SET_SRC (x))
4209 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4210 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4211 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4212 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4213 return &XEXP (SET_SRC (x), 1);
4215 /* Finally, see if this is a simple operation with its first operand
4216 not in a register. The operation might require this operand in a
4217 register, so return it as a split point. We can always do this
4218 because if the first operand were another operation, we would have
4219 already found it as a split point. */
4220 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4221 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4222 return &XEXP (SET_SRC (x), 0);
4228 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4229 it is better to write this as (not (ior A B)) so we can split it.
4230 Similarly for IOR. */
4231 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4234 gen_rtx_NOT (GET_MODE (x),
4235 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4237 XEXP (XEXP (x, 0), 0),
4238 XEXP (XEXP (x, 1), 0))));
4239 return find_split_point (loc, insn);
4242 /* Many RISC machines have a large set of logical insns. If the
4243 second operand is a NOT, put it first so we will try to split the
4244 other operand first. */
4245 if (GET_CODE (XEXP (x, 1)) == NOT)
4247 rtx tem = XEXP (x, 0);
4248 SUBST (XEXP (x, 0), XEXP (x, 1));
4249 SUBST (XEXP (x, 1), tem);
4257 /* Otherwise, select our actions depending on our rtx class. */
4258 switch (GET_RTX_CLASS (code))
4260 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4262 split = find_split_point (&XEXP (x, 2), insn);
4265 /* ... fall through ... */
4267 case RTX_COMM_ARITH:
4269 case RTX_COMM_COMPARE:
4270 split = find_split_point (&XEXP (x, 1), insn);
4273 /* ... fall through ... */
4275 /* Some machines have (and (shift ...) ...) insns. If X is not
4276 an AND, but XEXP (X, 0) is, use it as our split point. */
4277 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4278 return &XEXP (x, 0);
4280 split = find_split_point (&XEXP (x, 0), insn);
4286 /* Otherwise, we don't have a split point. */
4291 /* Throughout X, replace FROM with TO, and return the result.
4292 The result is TO if X is FROM;
4293 otherwise the result is X, but its contents may have been modified.
4294 If they were modified, a record was made in undobuf so that
4295 undo_all will (among other things) return X to its original state.
4297 If the number of changes necessary is too much to record to undo,
4298 the excess changes are not made, so the result is invalid.
4299 The changes already made can still be undone.
4300 undobuf.num_undo is incremented for such changes, so by testing that
4301 the caller can tell whether the result is valid.
4303 `n_occurrences' is incremented each time FROM is replaced.
4305 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4307 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4308 by copying if `n_occurrences' is nonzero. */
4311 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4313 enum rtx_code code = GET_CODE (x);
4314 enum machine_mode op0_mode = VOIDmode;
4319 /* Two expressions are equal if they are identical copies of a shared
4320 RTX or if they are both registers with the same register number
4323 #define COMBINE_RTX_EQUAL_P(X,Y) \
4325 || (REG_P (X) && REG_P (Y) \
4326 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4328 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4331 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4334 /* If X and FROM are the same register but different modes, they
4335 will not have been seen as equal above. However, the log links code
4336 will make a LOG_LINKS entry for that case. If we do nothing, we
4337 will try to rerecognize our original insn and, when it succeeds,
4338 we will delete the feeding insn, which is incorrect.
4340 So force this insn not to match in this (rare) case. */
4341 if (! in_dest && code == REG && REG_P (from)
4342 && reg_overlap_mentioned_p (x, from))
4343 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4345 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4346 of which may contain things that can be combined. */
4347 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4350 /* It is possible to have a subexpression appear twice in the insn.
4351 Suppose that FROM is a register that appears within TO.
4352 Then, after that subexpression has been scanned once by `subst',
4353 the second time it is scanned, TO may be found. If we were
4354 to scan TO here, we would find FROM within it and create a
4355 self-referent rtl structure which is completely wrong. */
4356 if (COMBINE_RTX_EQUAL_P (x, to))
4359 /* Parallel asm_operands need special attention because all of the
4360 inputs are shared across the arms. Furthermore, unsharing the
4361 rtl results in recognition failures. Failure to handle this case
4362 specially can result in circular rtl.
4364 Solve this by doing a normal pass across the first entry of the
4365 parallel, and only processing the SET_DESTs of the subsequent
4368 if (code == PARALLEL
4369 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4370 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4372 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4374 /* If this substitution failed, this whole thing fails. */
4375 if (GET_CODE (new_rtx) == CLOBBER
4376 && XEXP (new_rtx, 0) == const0_rtx)
4379 SUBST (XVECEXP (x, 0, 0), new_rtx);
4381 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4383 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4386 && GET_CODE (dest) != CC0
4387 && GET_CODE (dest) != PC)
4389 new_rtx = subst (dest, from, to, 0, unique_copy);
4391 /* If this substitution failed, this whole thing fails. */
4392 if (GET_CODE (new_rtx) == CLOBBER
4393 && XEXP (new_rtx, 0) == const0_rtx)
4396 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4402 len = GET_RTX_LENGTH (code);
4403 fmt = GET_RTX_FORMAT (code);
4405 /* We don't need to process a SET_DEST that is a register, CC0,
4406 or PC, so set up to skip this common case. All other cases
4407 where we want to suppress replacing something inside a
4408 SET_SRC are handled via the IN_DEST operand. */
4410 && (REG_P (SET_DEST (x))
4411 || GET_CODE (SET_DEST (x)) == CC0
4412 || GET_CODE (SET_DEST (x)) == PC))
4415 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4418 op0_mode = GET_MODE (XEXP (x, 0));
4420 for (i = 0; i < len; i++)
4425 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4427 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4429 new_rtx = (unique_copy && n_occurrences
4430 ? copy_rtx (to) : to);
4435 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4438 /* If this substitution failed, this whole thing
4440 if (GET_CODE (new_rtx) == CLOBBER
4441 && XEXP (new_rtx, 0) == const0_rtx)
4445 SUBST (XVECEXP (x, i, j), new_rtx);
4448 else if (fmt[i] == 'e')
4450 /* If this is a register being set, ignore it. */
4451 new_rtx = XEXP (x, i);
4454 && (((code == SUBREG || code == ZERO_EXTRACT)
4456 || code == STRICT_LOW_PART))
4459 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4461 /* In general, don't install a subreg involving two
4462 modes not tieable. It can worsen register
4463 allocation, and can even make invalid reload
4464 insns, since the reg inside may need to be copied
4465 from in the outside mode, and that may be invalid
4466 if it is an fp reg copied in integer mode.
4468 We allow two exceptions to this: It is valid if
4469 it is inside another SUBREG and the mode of that
4470 SUBREG and the mode of the inside of TO is
4471 tieable and it is valid if X is a SET that copies
4474 if (GET_CODE (to) == SUBREG
4475 && ! MODES_TIEABLE_P (GET_MODE (to),
4476 GET_MODE (SUBREG_REG (to)))
4477 && ! (code == SUBREG
4478 && MODES_TIEABLE_P (GET_MODE (x),
4479 GET_MODE (SUBREG_REG (to))))
4481 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4484 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4486 #ifdef CANNOT_CHANGE_MODE_CLASS
4489 && REGNO (to) < FIRST_PSEUDO_REGISTER
4490 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4493 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4496 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4500 /* If we are in a SET_DEST, suppress most cases unless we
4501 have gone inside a MEM, in which case we want to
4502 simplify the address. We assume here that things that
4503 are actually part of the destination have their inner
4504 parts in the first expression. This is true for SUBREG,
4505 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4506 things aside from REG and MEM that should appear in a
4508 new_rtx = subst (XEXP (x, i), from, to,
4510 && (code == SUBREG || code == STRICT_LOW_PART
4511 || code == ZERO_EXTRACT))
4513 && i == 0), unique_copy);
4515 /* If we found that we will have to reject this combination,
4516 indicate that by returning the CLOBBER ourselves, rather than
4517 an expression containing it. This will speed things up as
4518 well as prevent accidents where two CLOBBERs are considered
4519 to be equal, thus producing an incorrect simplification. */
4521 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4524 if (GET_CODE (x) == SUBREG
4525 && (CONST_INT_P (new_rtx)
4526 || GET_CODE (new_rtx) == CONST_DOUBLE))
4528 enum machine_mode mode = GET_MODE (x);
4530 x = simplify_subreg (GET_MODE (x), new_rtx,
4531 GET_MODE (SUBREG_REG (x)),
4534 x = gen_rtx_CLOBBER (mode, const0_rtx);
4536 else if (CONST_INT_P (new_rtx)
4537 && GET_CODE (x) == ZERO_EXTEND)
4539 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4540 new_rtx, GET_MODE (XEXP (x, 0)));
4544 SUBST (XEXP (x, i), new_rtx);
4549 /* Check if we are loading something from the constant pool via float
4550 extension; in this case we would undo compress_float_constant
4551 optimization and degenerate constant load to an immediate value. */
4552 if (GET_CODE (x) == FLOAT_EXTEND
4553 && MEM_P (XEXP (x, 0))
4554 && MEM_READONLY_P (XEXP (x, 0)))
4556 rtx tmp = avoid_constant_pool_reference (x);
4561 /* Try to simplify X. If the simplification changed the code, it is likely
4562 that further simplification will help, so loop, but limit the number
4563 of repetitions that will be performed. */
4565 for (i = 0; i < 4; i++)
4567 /* If X is sufficiently simple, don't bother trying to do anything
4569 if (code != CONST_INT && code != REG && code != CLOBBER)
4570 x = combine_simplify_rtx (x, op0_mode, in_dest);
4572 if (GET_CODE (x) == code)
4575 code = GET_CODE (x);
4577 /* We no longer know the original mode of operand 0 since we
4578 have changed the form of X) */
4579 op0_mode = VOIDmode;
4585 /* Simplify X, a piece of RTL. We just operate on the expression at the
4586 outer level; call `subst' to simplify recursively. Return the new
4589 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4590 if we are inside a SET_DEST. */
4593 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4595 enum rtx_code code = GET_CODE (x);
4596 enum machine_mode mode = GET_MODE (x);
4600 /* If this is a commutative operation, put a constant last and a complex
4601 expression first. We don't need to do this for comparisons here. */
4602 if (COMMUTATIVE_ARITH_P (x)
4603 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4606 SUBST (XEXP (x, 0), XEXP (x, 1));
4607 SUBST (XEXP (x, 1), temp);
4610 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4611 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4612 things. Check for cases where both arms are testing the same
4615 Don't do anything if all operands are very simple. */
4618 && ((!OBJECT_P (XEXP (x, 0))
4619 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4620 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4621 || (!OBJECT_P (XEXP (x, 1))
4622 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4623 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4625 && (!OBJECT_P (XEXP (x, 0))
4626 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4627 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4629 rtx cond, true_rtx, false_rtx;
4631 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4633 /* If everything is a comparison, what we have is highly unlikely
4634 to be simpler, so don't use it. */
4635 && ! (COMPARISON_P (x)
4636 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4638 rtx cop1 = const0_rtx;
4639 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4641 if (cond_code == NE && COMPARISON_P (cond))
4644 /* Simplify the alternative arms; this may collapse the true and
4645 false arms to store-flag values. Be careful to use copy_rtx
4646 here since true_rtx or false_rtx might share RTL with x as a
4647 result of the if_then_else_cond call above. */
4648 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4649 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4651 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4652 is unlikely to be simpler. */
4653 if (general_operand (true_rtx, VOIDmode)
4654 && general_operand (false_rtx, VOIDmode))
4656 enum rtx_code reversed;
4658 /* Restarting if we generate a store-flag expression will cause
4659 us to loop. Just drop through in this case. */
4661 /* If the result values are STORE_FLAG_VALUE and zero, we can
4662 just make the comparison operation. */
4663 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4664 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4666 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4667 && ((reversed = reversed_comparison_code_parts
4668 (cond_code, cond, cop1, NULL))
4670 x = simplify_gen_relational (reversed, mode, VOIDmode,
4673 /* Likewise, we can make the negate of a comparison operation
4674 if the result values are - STORE_FLAG_VALUE and zero. */
4675 else if (CONST_INT_P (true_rtx)
4676 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4677 && false_rtx == const0_rtx)
4678 x = simplify_gen_unary (NEG, mode,
4679 simplify_gen_relational (cond_code,
4683 else if (CONST_INT_P (false_rtx)
4684 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4685 && true_rtx == const0_rtx
4686 && ((reversed = reversed_comparison_code_parts
4687 (cond_code, cond, cop1, NULL))
4689 x = simplify_gen_unary (NEG, mode,
4690 simplify_gen_relational (reversed,
4695 return gen_rtx_IF_THEN_ELSE (mode,
4696 simplify_gen_relational (cond_code,
4701 true_rtx, false_rtx);
4703 code = GET_CODE (x);
4704 op0_mode = VOIDmode;
4709 /* Try to fold this expression in case we have constants that weren't
4712 switch (GET_RTX_CLASS (code))
4715 if (op0_mode == VOIDmode)
4716 op0_mode = GET_MODE (XEXP (x, 0));
4717 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4720 case RTX_COMM_COMPARE:
4722 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4723 if (cmp_mode == VOIDmode)
4725 cmp_mode = GET_MODE (XEXP (x, 1));
4726 if (cmp_mode == VOIDmode)
4727 cmp_mode = op0_mode;
4729 temp = simplify_relational_operation (code, mode, cmp_mode,
4730 XEXP (x, 0), XEXP (x, 1));
4733 case RTX_COMM_ARITH:
4735 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4737 case RTX_BITFIELD_OPS:
4739 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4740 XEXP (x, 1), XEXP (x, 2));
4749 code = GET_CODE (temp);
4750 op0_mode = VOIDmode;
4751 mode = GET_MODE (temp);
4754 /* First see if we can apply the inverse distributive law. */
4755 if (code == PLUS || code == MINUS
4756 || code == AND || code == IOR || code == XOR)
4758 x = apply_distributive_law (x);
4759 code = GET_CODE (x);
4760 op0_mode = VOIDmode;
4763 /* If CODE is an associative operation not otherwise handled, see if we
4764 can associate some operands. This can win if they are constants or
4765 if they are logically related (i.e. (a & b) & a). */
4766 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4767 || code == AND || code == IOR || code == XOR
4768 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4769 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4770 || (flag_associative_math && FLOAT_MODE_P (mode))))
4772 if (GET_CODE (XEXP (x, 0)) == code)
4774 rtx other = XEXP (XEXP (x, 0), 0);
4775 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4776 rtx inner_op1 = XEXP (x, 1);
4779 /* Make sure we pass the constant operand if any as the second
4780 one if this is a commutative operation. */
4781 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4783 rtx tem = inner_op0;
4784 inner_op0 = inner_op1;
4787 inner = simplify_binary_operation (code == MINUS ? PLUS
4788 : code == DIV ? MULT
4790 mode, inner_op0, inner_op1);
4792 /* For commutative operations, try the other pair if that one
4794 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4796 other = XEXP (XEXP (x, 0), 1);
4797 inner = simplify_binary_operation (code, mode,
4798 XEXP (XEXP (x, 0), 0),
4803 return simplify_gen_binary (code, mode, other, inner);
4807 /* A little bit of algebraic simplification here. */
4811 /* Ensure that our address has any ASHIFTs converted to MULT in case
4812 address-recognizing predicates are called later. */
4813 temp = make_compound_operation (XEXP (x, 0), MEM);
4814 SUBST (XEXP (x, 0), temp);
4818 if (op0_mode == VOIDmode)
4819 op0_mode = GET_MODE (SUBREG_REG (x));
4821 /* See if this can be moved to simplify_subreg. */
4822 if (CONSTANT_P (SUBREG_REG (x))
4823 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4824 /* Don't call gen_lowpart if the inner mode
4825 is VOIDmode and we cannot simplify it, as SUBREG without
4826 inner mode is invalid. */
4827 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4828 || gen_lowpart_common (mode, SUBREG_REG (x))))
4829 return gen_lowpart (mode, SUBREG_REG (x));
4831 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4835 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4841 /* Don't change the mode of the MEM if that would change the meaning
4843 if (MEM_P (SUBREG_REG (x))
4844 && (MEM_VOLATILE_P (SUBREG_REG (x))
4845 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4846 return gen_rtx_CLOBBER (mode, const0_rtx);
4848 /* Note that we cannot do any narrowing for non-constants since
4849 we might have been counting on using the fact that some bits were
4850 zero. We now do this in the SET. */
4855 temp = expand_compound_operation (XEXP (x, 0));
4857 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4858 replaced by (lshiftrt X C). This will convert
4859 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4861 if (GET_CODE (temp) == ASHIFTRT
4862 && CONST_INT_P (XEXP (temp, 1))
4863 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4864 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4865 INTVAL (XEXP (temp, 1)));
4867 /* If X has only a single bit that might be nonzero, say, bit I, convert
4868 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4869 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4870 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4871 or a SUBREG of one since we'd be making the expression more
4872 complex if it was just a register. */
4875 && ! (GET_CODE (temp) == SUBREG
4876 && REG_P (SUBREG_REG (temp)))
4877 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4879 rtx temp1 = simplify_shift_const
4880 (NULL_RTX, ASHIFTRT, mode,
4881 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4882 GET_MODE_BITSIZE (mode) - 1 - i),
4883 GET_MODE_BITSIZE (mode) - 1 - i);
4885 /* If all we did was surround TEMP with the two shifts, we
4886 haven't improved anything, so don't use it. Otherwise,
4887 we are better off with TEMP1. */
4888 if (GET_CODE (temp1) != ASHIFTRT
4889 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4890 || XEXP (XEXP (temp1, 0), 0) != temp)
4896 /* We can't handle truncation to a partial integer mode here
4897 because we don't know the real bitsize of the partial
4899 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4902 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4904 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4905 GET_MODE_MASK (mode), 0));
4907 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4908 whose value is a comparison can be replaced with a subreg if
4909 STORE_FLAG_VALUE permits. */
4910 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4911 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4912 && (temp = get_last_value (XEXP (x, 0)))
4913 && COMPARISON_P (temp))
4914 return gen_lowpart (mode, XEXP (x, 0));
4918 /* (const (const X)) can become (const X). Do it this way rather than
4919 returning the inner CONST since CONST can be shared with a
4921 if (GET_CODE (XEXP (x, 0)) == CONST)
4922 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4927 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4928 can add in an offset. find_split_point will split this address up
4929 again if it doesn't match. */
4930 if (GET_CODE (XEXP (x, 0)) == HIGH
4931 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4937 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4938 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4939 bit-field and can be replaced by either a sign_extend or a
4940 sign_extract. The `and' may be a zero_extend and the two
4941 <c>, -<c> constants may be reversed. */
4942 if (GET_CODE (XEXP (x, 0)) == XOR
4943 && CONST_INT_P (XEXP (x, 1))
4944 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4945 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4946 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4947 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4948 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4949 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4950 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4951 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4952 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4953 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4954 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4955 == (unsigned int) i + 1))))
4956 return simplify_shift_const
4957 (NULL_RTX, ASHIFTRT, mode,
4958 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4959 XEXP (XEXP (XEXP (x, 0), 0), 0),
4960 GET_MODE_BITSIZE (mode) - (i + 1)),
4961 GET_MODE_BITSIZE (mode) - (i + 1));
4963 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4964 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4965 the bitsize of the mode - 1. This allows simplification of
4966 "a = (b & 8) == 0;" */
4967 if (XEXP (x, 1) == constm1_rtx
4968 && !REG_P (XEXP (x, 0))
4969 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4970 && REG_P (SUBREG_REG (XEXP (x, 0))))
4971 && nonzero_bits (XEXP (x, 0), mode) == 1)
4972 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4973 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4974 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4975 GET_MODE_BITSIZE (mode) - 1),
4976 GET_MODE_BITSIZE (mode) - 1);
4978 /* If we are adding two things that have no bits in common, convert
4979 the addition into an IOR. This will often be further simplified,
4980 for example in cases like ((a & 1) + (a & 2)), which can
4983 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4984 && (nonzero_bits (XEXP (x, 0), mode)
4985 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4987 /* Try to simplify the expression further. */
4988 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4989 temp = combine_simplify_rtx (tor, mode, in_dest);
4991 /* If we could, great. If not, do not go ahead with the IOR
4992 replacement, since PLUS appears in many special purpose
4993 address arithmetic instructions. */
4994 if (GET_CODE (temp) != CLOBBER && temp != tor)
5000 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5001 (and <foo> (const_int pow2-1)) */
5002 if (GET_CODE (XEXP (x, 1)) == AND
5003 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5004 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5005 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5006 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5007 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5011 /* If we have (mult (plus A B) C), apply the distributive law and then
5012 the inverse distributive law to see if things simplify. This
5013 occurs mostly in addresses, often when unrolling loops. */
5015 if (GET_CODE (XEXP (x, 0)) == PLUS)
5017 rtx result = distribute_and_simplify_rtx (x, 0);
5022 /* Try simplify a*(b/c) as (a*b)/c. */
5023 if (FLOAT_MODE_P (mode) && flag_associative_math
5024 && GET_CODE (XEXP (x, 0)) == DIV)
5026 rtx tem = simplify_binary_operation (MULT, mode,
5027 XEXP (XEXP (x, 0), 0),
5030 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5035 /* If this is a divide by a power of two, treat it as a shift if
5036 its first operand is a shift. */
5037 if (CONST_INT_P (XEXP (x, 1))
5038 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5039 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5040 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5041 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5042 || GET_CODE (XEXP (x, 0)) == ROTATE
5043 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5044 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5048 case GT: case GTU: case GE: case GEU:
5049 case LT: case LTU: case LE: case LEU:
5050 case UNEQ: case LTGT:
5051 case UNGT: case UNGE:
5052 case UNLT: case UNLE:
5053 case UNORDERED: case ORDERED:
5054 /* If the first operand is a condition code, we can't do anything
5056 if (GET_CODE (XEXP (x, 0)) == COMPARE
5057 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5058 && ! CC0_P (XEXP (x, 0))))
5060 rtx op0 = XEXP (x, 0);
5061 rtx op1 = XEXP (x, 1);
5062 enum rtx_code new_code;
5064 if (GET_CODE (op0) == COMPARE)
5065 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5067 /* Simplify our comparison, if possible. */
5068 new_code = simplify_comparison (code, &op0, &op1);
5070 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5071 if only the low-order bit is possibly nonzero in X (such as when
5072 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5073 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5074 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5077 Remove any ZERO_EXTRACT we made when thinking this was a
5078 comparison. It may now be simpler to use, e.g., an AND. If a
5079 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5080 the call to make_compound_operation in the SET case. */
5082 if (STORE_FLAG_VALUE == 1
5083 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5084 && op1 == const0_rtx
5085 && mode == GET_MODE (op0)
5086 && nonzero_bits (op0, mode) == 1)
5087 return gen_lowpart (mode,
5088 expand_compound_operation (op0));
5090 else if (STORE_FLAG_VALUE == 1
5091 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5092 && op1 == const0_rtx
5093 && mode == GET_MODE (op0)
5094 && (num_sign_bit_copies (op0, mode)
5095 == GET_MODE_BITSIZE (mode)))
5097 op0 = expand_compound_operation (op0);
5098 return simplify_gen_unary (NEG, mode,
5099 gen_lowpart (mode, op0),
5103 else if (STORE_FLAG_VALUE == 1
5104 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5105 && op1 == const0_rtx
5106 && mode == GET_MODE (op0)
5107 && nonzero_bits (op0, mode) == 1)
5109 op0 = expand_compound_operation (op0);
5110 return simplify_gen_binary (XOR, mode,
5111 gen_lowpart (mode, op0),
5115 else if (STORE_FLAG_VALUE == 1
5116 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5117 && op1 == const0_rtx
5118 && mode == GET_MODE (op0)
5119 && (num_sign_bit_copies (op0, mode)
5120 == GET_MODE_BITSIZE (mode)))
5122 op0 = expand_compound_operation (op0);
5123 return plus_constant (gen_lowpart (mode, op0), 1);
5126 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5128 if (STORE_FLAG_VALUE == -1
5129 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5130 && op1 == const0_rtx
5131 && (num_sign_bit_copies (op0, mode)
5132 == GET_MODE_BITSIZE (mode)))
5133 return gen_lowpart (mode,
5134 expand_compound_operation (op0));
5136 else if (STORE_FLAG_VALUE == -1
5137 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5138 && op1 == const0_rtx
5139 && mode == GET_MODE (op0)
5140 && nonzero_bits (op0, mode) == 1)
5142 op0 = expand_compound_operation (op0);
5143 return simplify_gen_unary (NEG, mode,
5144 gen_lowpart (mode, op0),
5148 else if (STORE_FLAG_VALUE == -1
5149 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5150 && op1 == const0_rtx
5151 && mode == GET_MODE (op0)
5152 && (num_sign_bit_copies (op0, mode)
5153 == GET_MODE_BITSIZE (mode)))
5155 op0 = expand_compound_operation (op0);
5156 return simplify_gen_unary (NOT, mode,
5157 gen_lowpart (mode, op0),
5161 /* If X is 0/1, (eq X 0) is X-1. */
5162 else if (STORE_FLAG_VALUE == -1
5163 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5164 && op1 == const0_rtx
5165 && mode == GET_MODE (op0)
5166 && nonzero_bits (op0, mode) == 1)
5168 op0 = expand_compound_operation (op0);
5169 return plus_constant (gen_lowpart (mode, op0), -1);
5172 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5173 one bit that might be nonzero, we can convert (ne x 0) to
5174 (ashift x c) where C puts the bit in the sign bit. Remove any
5175 AND with STORE_FLAG_VALUE when we are done, since we are only
5176 going to test the sign bit. */
5177 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5178 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5179 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5180 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5181 && op1 == const0_rtx
5182 && mode == GET_MODE (op0)
5183 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5185 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5186 expand_compound_operation (op0),
5187 GET_MODE_BITSIZE (mode) - 1 - i);
5188 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5194 /* If the code changed, return a whole new comparison. */
5195 if (new_code != code)
5196 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5198 /* Otherwise, keep this operation, but maybe change its operands.
5199 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5200 SUBST (XEXP (x, 0), op0);
5201 SUBST (XEXP (x, 1), op1);
5206 return simplify_if_then_else (x);
5212 /* If we are processing SET_DEST, we are done. */
5216 return expand_compound_operation (x);
5219 return simplify_set (x);
5223 return simplify_logical (x);
5230 /* If this is a shift by a constant amount, simplify it. */
5231 if (CONST_INT_P (XEXP (x, 1)))
5232 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5233 INTVAL (XEXP (x, 1)));
5235 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5237 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5239 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5251 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5254 simplify_if_then_else (rtx x)
5256 enum machine_mode mode = GET_MODE (x);
5257 rtx cond = XEXP (x, 0);
5258 rtx true_rtx = XEXP (x, 1);
5259 rtx false_rtx = XEXP (x, 2);
5260 enum rtx_code true_code = GET_CODE (cond);
5261 int comparison_p = COMPARISON_P (cond);
5264 enum rtx_code false_code;
5267 /* Simplify storing of the truth value. */
5268 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5269 return simplify_gen_relational (true_code, mode, VOIDmode,
5270 XEXP (cond, 0), XEXP (cond, 1));
5272 /* Also when the truth value has to be reversed. */
5274 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5275 && (reversed = reversed_comparison (cond, mode)))
5278 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5279 in it is being compared against certain values. Get the true and false
5280 comparisons and see if that says anything about the value of each arm. */
5283 && ((false_code = reversed_comparison_code (cond, NULL))
5285 && REG_P (XEXP (cond, 0)))
5288 rtx from = XEXP (cond, 0);
5289 rtx true_val = XEXP (cond, 1);
5290 rtx false_val = true_val;
5293 /* If FALSE_CODE is EQ, swap the codes and arms. */
5295 if (false_code == EQ)
5297 swapped = 1, true_code = EQ, false_code = NE;
5298 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5301 /* If we are comparing against zero and the expression being tested has
5302 only a single bit that might be nonzero, that is its value when it is
5303 not equal to zero. Similarly if it is known to be -1 or 0. */
5305 if (true_code == EQ && true_val == const0_rtx
5306 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5309 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5311 else if (true_code == EQ && true_val == const0_rtx
5312 && (num_sign_bit_copies (from, GET_MODE (from))
5313 == GET_MODE_BITSIZE (GET_MODE (from))))
5316 false_val = constm1_rtx;
5319 /* Now simplify an arm if we know the value of the register in the
5320 branch and it is used in the arm. Be careful due to the potential
5321 of locally-shared RTL. */
5323 if (reg_mentioned_p (from, true_rtx))
5324 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5326 pc_rtx, pc_rtx, 0, 0);
5327 if (reg_mentioned_p (from, false_rtx))
5328 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5330 pc_rtx, pc_rtx, 0, 0);
5332 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5333 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5335 true_rtx = XEXP (x, 1);
5336 false_rtx = XEXP (x, 2);
5337 true_code = GET_CODE (cond);
5340 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5341 reversed, do so to avoid needing two sets of patterns for
5342 subtract-and-branch insns. Similarly if we have a constant in the true
5343 arm, the false arm is the same as the first operand of the comparison, or
5344 the false arm is more complicated than the true arm. */
5347 && reversed_comparison_code (cond, NULL) != UNKNOWN
5348 && (true_rtx == pc_rtx
5349 || (CONSTANT_P (true_rtx)
5350 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5351 || true_rtx == const0_rtx
5352 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5353 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5354 && !OBJECT_P (false_rtx))
5355 || reg_mentioned_p (true_rtx, false_rtx)
5356 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5358 true_code = reversed_comparison_code (cond, NULL);
5359 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5360 SUBST (XEXP (x, 1), false_rtx);
5361 SUBST (XEXP (x, 2), true_rtx);
5363 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5366 /* It is possible that the conditional has been simplified out. */
5367 true_code = GET_CODE (cond);
5368 comparison_p = COMPARISON_P (cond);
5371 /* If the two arms are identical, we don't need the comparison. */
5373 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5376 /* Convert a == b ? b : a to "a". */
5377 if (true_code == EQ && ! side_effects_p (cond)
5378 && !HONOR_NANS (mode)
5379 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5380 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5382 else if (true_code == NE && ! side_effects_p (cond)
5383 && !HONOR_NANS (mode)
5384 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5385 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5388 /* Look for cases where we have (abs x) or (neg (abs X)). */
5390 if (GET_MODE_CLASS (mode) == MODE_INT
5392 && XEXP (cond, 1) == const0_rtx
5393 && GET_CODE (false_rtx) == NEG
5394 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5395 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5396 && ! side_effects_p (true_rtx))
5401 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5405 simplify_gen_unary (NEG, mode,
5406 simplify_gen_unary (ABS, mode, true_rtx, mode),
5412 /* Look for MIN or MAX. */
5414 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5416 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5417 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5418 && ! side_effects_p (cond))
5423 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5426 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5429 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5432 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5437 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5438 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5439 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5440 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5441 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5442 neither 1 or -1, but it isn't worth checking for. */
5444 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5446 && GET_MODE_CLASS (mode) == MODE_INT
5447 && ! side_effects_p (x))
5449 rtx t = make_compound_operation (true_rtx, SET);
5450 rtx f = make_compound_operation (false_rtx, SET);
5451 rtx cond_op0 = XEXP (cond, 0);
5452 rtx cond_op1 = XEXP (cond, 1);
5453 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5454 enum machine_mode m = mode;
5455 rtx z = 0, c1 = NULL_RTX;
5457 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5458 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5459 || GET_CODE (t) == ASHIFT
5460 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5461 && rtx_equal_p (XEXP (t, 0), f))
5462 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5464 /* If an identity-zero op is commutative, check whether there
5465 would be a match if we swapped the operands. */
5466 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5467 || GET_CODE (t) == XOR)
5468 && rtx_equal_p (XEXP (t, 1), f))
5469 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5470 else if (GET_CODE (t) == SIGN_EXTEND
5471 && (GET_CODE (XEXP (t, 0)) == PLUS
5472 || GET_CODE (XEXP (t, 0)) == MINUS
5473 || GET_CODE (XEXP (t, 0)) == IOR
5474 || GET_CODE (XEXP (t, 0)) == XOR
5475 || GET_CODE (XEXP (t, 0)) == ASHIFT
5476 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5477 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5478 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5479 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5480 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5481 && (num_sign_bit_copies (f, GET_MODE (f))
5483 (GET_MODE_BITSIZE (mode)
5484 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5486 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5487 extend_op = SIGN_EXTEND;
5488 m = GET_MODE (XEXP (t, 0));
5490 else if (GET_CODE (t) == SIGN_EXTEND
5491 && (GET_CODE (XEXP (t, 0)) == PLUS
5492 || GET_CODE (XEXP (t, 0)) == IOR
5493 || GET_CODE (XEXP (t, 0)) == XOR)
5494 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5495 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5496 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5497 && (num_sign_bit_copies (f, GET_MODE (f))
5499 (GET_MODE_BITSIZE (mode)
5500 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5502 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5503 extend_op = SIGN_EXTEND;
5504 m = GET_MODE (XEXP (t, 0));
5506 else if (GET_CODE (t) == ZERO_EXTEND
5507 && (GET_CODE (XEXP (t, 0)) == PLUS
5508 || GET_CODE (XEXP (t, 0)) == MINUS
5509 || GET_CODE (XEXP (t, 0)) == IOR
5510 || GET_CODE (XEXP (t, 0)) == XOR
5511 || GET_CODE (XEXP (t, 0)) == ASHIFT
5512 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5513 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5514 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5515 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5516 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5517 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5518 && ((nonzero_bits (f, GET_MODE (f))
5519 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5522 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5523 extend_op = ZERO_EXTEND;
5524 m = GET_MODE (XEXP (t, 0));
5526 else if (GET_CODE (t) == ZERO_EXTEND
5527 && (GET_CODE (XEXP (t, 0)) == PLUS
5528 || GET_CODE (XEXP (t, 0)) == IOR
5529 || GET_CODE (XEXP (t, 0)) == XOR)
5530 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5531 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5532 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5533 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5534 && ((nonzero_bits (f, GET_MODE (f))
5535 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5538 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5539 extend_op = ZERO_EXTEND;
5540 m = GET_MODE (XEXP (t, 0));
5545 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5546 cond_op0, cond_op1),
5547 pc_rtx, pc_rtx, 0, 0);
5548 temp = simplify_gen_binary (MULT, m, temp,
5549 simplify_gen_binary (MULT, m, c1,
5551 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5552 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5554 if (extend_op != UNKNOWN)
5555 temp = simplify_gen_unary (extend_op, mode, temp, m);
5561 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5562 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5563 negation of a single bit, we can convert this operation to a shift. We
5564 can actually do this more generally, but it doesn't seem worth it. */
5566 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5567 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5568 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5569 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5570 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5571 == GET_MODE_BITSIZE (mode))
5572 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5574 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5575 gen_lowpart (mode, XEXP (cond, 0)), i);
5577 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5578 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5579 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5580 && GET_MODE (XEXP (cond, 0)) == mode
5581 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5582 == nonzero_bits (XEXP (cond, 0), mode)
5583 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5584 return XEXP (cond, 0);
5589 /* Simplify X, a SET expression. Return the new expression. */
5592 simplify_set (rtx x)
5594 rtx src = SET_SRC (x);
5595 rtx dest = SET_DEST (x);
5596 enum machine_mode mode
5597 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5601 /* (set (pc) (return)) gets written as (return). */
5602 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5605 /* Now that we know for sure which bits of SRC we are using, see if we can
5606 simplify the expression for the object knowing that we only need the
5609 if (GET_MODE_CLASS (mode) == MODE_INT
5610 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5612 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5613 SUBST (SET_SRC (x), src);
5616 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5617 the comparison result and try to simplify it unless we already have used
5618 undobuf.other_insn. */
5619 if ((GET_MODE_CLASS (mode) == MODE_CC
5620 || GET_CODE (src) == COMPARE
5622 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5623 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5624 && COMPARISON_P (*cc_use)
5625 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5627 enum rtx_code old_code = GET_CODE (*cc_use);
5628 enum rtx_code new_code;
5630 int other_changed = 0;
5631 enum machine_mode compare_mode = GET_MODE (dest);
5633 if (GET_CODE (src) == COMPARE)
5634 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5636 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5638 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5641 new_code = old_code;
5642 else if (!CONSTANT_P (tmp))
5644 new_code = GET_CODE (tmp);
5645 op0 = XEXP (tmp, 0);
5646 op1 = XEXP (tmp, 1);
5650 rtx pat = PATTERN (other_insn);
5651 undobuf.other_insn = other_insn;
5652 SUBST (*cc_use, tmp);
5654 /* Attempt to simplify CC user. */
5655 if (GET_CODE (pat) == SET)
5657 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5658 if (new_rtx != NULL_RTX)
5659 SUBST (SET_SRC (pat), new_rtx);
5662 /* Convert X into a no-op move. */
5663 SUBST (SET_DEST (x), pc_rtx);
5664 SUBST (SET_SRC (x), pc_rtx);
5668 /* Simplify our comparison, if possible. */
5669 new_code = simplify_comparison (new_code, &op0, &op1);
5671 #ifdef SELECT_CC_MODE
5672 /* If this machine has CC modes other than CCmode, check to see if we
5673 need to use a different CC mode here. */
5674 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5675 compare_mode = GET_MODE (op0);
5677 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5680 /* If the mode changed, we have to change SET_DEST, the mode in the
5681 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5682 a hard register, just build new versions with the proper mode. If it
5683 is a pseudo, we lose unless it is only time we set the pseudo, in
5684 which case we can safely change its mode. */
5685 if (compare_mode != GET_MODE (dest))
5687 if (can_change_dest_mode (dest, 0, compare_mode))
5689 unsigned int regno = REGNO (dest);
5692 if (regno < FIRST_PSEUDO_REGISTER)
5693 new_dest = gen_rtx_REG (compare_mode, regno);
5696 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5697 new_dest = regno_reg_rtx[regno];
5700 SUBST (SET_DEST (x), new_dest);
5701 SUBST (XEXP (*cc_use, 0), new_dest);
5708 #endif /* SELECT_CC_MODE */
5710 /* If the code changed, we have to build a new comparison in
5711 undobuf.other_insn. */
5712 if (new_code != old_code)
5714 int other_changed_previously = other_changed;
5715 unsigned HOST_WIDE_INT mask;
5716 rtx old_cc_use = *cc_use;
5718 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5722 /* If the only change we made was to change an EQ into an NE or
5723 vice versa, OP0 has only one bit that might be nonzero, and OP1
5724 is zero, check if changing the user of the condition code will
5725 produce a valid insn. If it won't, we can keep the original code
5726 in that insn by surrounding our operation with an XOR. */
5728 if (((old_code == NE && new_code == EQ)
5729 || (old_code == EQ && new_code == NE))
5730 && ! other_changed_previously && op1 == const0_rtx
5731 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5732 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5734 rtx pat = PATTERN (other_insn), note = 0;
5736 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5737 && ! check_asm_operands (pat)))
5739 *cc_use = old_cc_use;
5742 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5743 op0, GEN_INT (mask));
5749 undobuf.other_insn = other_insn;
5751 /* Otherwise, if we didn't previously have a COMPARE in the
5752 correct mode, we need one. */
5753 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5755 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5758 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5760 SUBST (SET_SRC (x), op0);
5763 /* Otherwise, update the COMPARE if needed. */
5764 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5766 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5772 /* Get SET_SRC in a form where we have placed back any
5773 compound expressions. Then do the checks below. */
5774 src = make_compound_operation (src, SET);
5775 SUBST (SET_SRC (x), src);
5778 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5779 and X being a REG or (subreg (reg)), we may be able to convert this to
5780 (set (subreg:m2 x) (op)).
5782 We can always do this if M1 is narrower than M2 because that means that
5783 we only care about the low bits of the result.
5785 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5786 perform a narrower operation than requested since the high-order bits will
5787 be undefined. On machine where it is defined, this transformation is safe
5788 as long as M1 and M2 have the same number of words. */
5790 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5791 && !OBJECT_P (SUBREG_REG (src))
5792 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5794 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5795 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5796 #ifndef WORD_REGISTER_OPERATIONS
5797 && (GET_MODE_SIZE (GET_MODE (src))
5798 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5800 #ifdef CANNOT_CHANGE_MODE_CLASS
5801 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5802 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5803 GET_MODE (SUBREG_REG (src)),
5807 || (GET_CODE (dest) == SUBREG
5808 && REG_P (SUBREG_REG (dest)))))
5810 SUBST (SET_DEST (x),
5811 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5813 SUBST (SET_SRC (x), SUBREG_REG (src));
5815 src = SET_SRC (x), dest = SET_DEST (x);
5819 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5822 && GET_CODE (src) == SUBREG
5823 && subreg_lowpart_p (src)
5824 && (GET_MODE_BITSIZE (GET_MODE (src))
5825 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5827 rtx inner = SUBREG_REG (src);
5828 enum machine_mode inner_mode = GET_MODE (inner);
5830 /* Here we make sure that we don't have a sign bit on. */
5831 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5832 && (nonzero_bits (inner, inner_mode)
5833 < ((unsigned HOST_WIDE_INT) 1
5834 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5836 SUBST (SET_SRC (x), inner);
5842 #ifdef LOAD_EXTEND_OP
5843 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5844 would require a paradoxical subreg. Replace the subreg with a
5845 zero_extend to avoid the reload that would otherwise be required. */
5847 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5848 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
5849 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5850 && SUBREG_BYTE (src) == 0
5851 && (GET_MODE_SIZE (GET_MODE (src))
5852 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5853 && MEM_P (SUBREG_REG (src)))
5856 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5857 GET_MODE (src), SUBREG_REG (src)));
5863 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5864 are comparing an item known to be 0 or -1 against 0, use a logical
5865 operation instead. Check for one of the arms being an IOR of the other
5866 arm with some value. We compute three terms to be IOR'ed together. In
5867 practice, at most two will be nonzero. Then we do the IOR's. */
5869 if (GET_CODE (dest) != PC
5870 && GET_CODE (src) == IF_THEN_ELSE
5871 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5872 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5873 && XEXP (XEXP (src, 0), 1) == const0_rtx
5874 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5875 #ifdef HAVE_conditional_move
5876 && ! can_conditionally_move_p (GET_MODE (src))
5878 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5879 GET_MODE (XEXP (XEXP (src, 0), 0)))
5880 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5881 && ! side_effects_p (src))
5883 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5884 ? XEXP (src, 1) : XEXP (src, 2));
5885 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5886 ? XEXP (src, 2) : XEXP (src, 1));
5887 rtx term1 = const0_rtx, term2, term3;
5889 if (GET_CODE (true_rtx) == IOR
5890 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5891 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5892 else if (GET_CODE (true_rtx) == IOR
5893 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5894 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5895 else if (GET_CODE (false_rtx) == IOR
5896 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5897 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5898 else if (GET_CODE (false_rtx) == IOR
5899 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5900 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5902 term2 = simplify_gen_binary (AND, GET_MODE (src),
5903 XEXP (XEXP (src, 0), 0), true_rtx);
5904 term3 = simplify_gen_binary (AND, GET_MODE (src),
5905 simplify_gen_unary (NOT, GET_MODE (src),
5906 XEXP (XEXP (src, 0), 0),
5911 simplify_gen_binary (IOR, GET_MODE (src),
5912 simplify_gen_binary (IOR, GET_MODE (src),
5919 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5920 whole thing fail. */
5921 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5923 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5926 /* Convert this into a field assignment operation, if possible. */
5927 return make_field_assignment (x);
5930 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5934 simplify_logical (rtx x)
5936 enum machine_mode mode = GET_MODE (x);
5937 rtx op0 = XEXP (x, 0);
5938 rtx op1 = XEXP (x, 1);
5940 switch (GET_CODE (x))
5943 /* We can call simplify_and_const_int only if we don't lose
5944 any (sign) bits when converting INTVAL (op1) to
5945 "unsigned HOST_WIDE_INT". */
5946 if (CONST_INT_P (op1)
5947 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5948 || INTVAL (op1) > 0))
5950 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5951 if (GET_CODE (x) != AND)
5958 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5959 apply the distributive law and then the inverse distributive
5960 law to see if things simplify. */
5961 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5963 rtx result = distribute_and_simplify_rtx (x, 0);
5967 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5969 rtx result = distribute_and_simplify_rtx (x, 1);
5976 /* If we have (ior (and A B) C), apply the distributive law and then
5977 the inverse distributive law to see if things simplify. */
5979 if (GET_CODE (op0) == AND)
5981 rtx result = distribute_and_simplify_rtx (x, 0);
5986 if (GET_CODE (op1) == AND)
5988 rtx result = distribute_and_simplify_rtx (x, 1);
6001 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6002 operations" because they can be replaced with two more basic operations.
6003 ZERO_EXTEND is also considered "compound" because it can be replaced with
6004 an AND operation, which is simpler, though only one operation.
6006 The function expand_compound_operation is called with an rtx expression
6007 and will convert it to the appropriate shifts and AND operations,
6008 simplifying at each stage.
6010 The function make_compound_operation is called to convert an expression
6011 consisting of shifts and ANDs into the equivalent compound expression.
6012 It is the inverse of this function, loosely speaking. */
6015 expand_compound_operation (rtx x)
6017 unsigned HOST_WIDE_INT pos = 0, len;
6019 unsigned int modewidth;
6022 switch (GET_CODE (x))
6027 /* We can't necessarily use a const_int for a multiword mode;
6028 it depends on implicitly extending the value.
6029 Since we don't know the right way to extend it,
6030 we can't tell whether the implicit way is right.
6032 Even for a mode that is no wider than a const_int,
6033 we can't win, because we need to sign extend one of its bits through
6034 the rest of it, and we don't know which bit. */
6035 if (CONST_INT_P (XEXP (x, 0)))
6038 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6039 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6040 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6041 reloaded. If not for that, MEM's would very rarely be safe.
6043 Reject MODEs bigger than a word, because we might not be able
6044 to reference a two-register group starting with an arbitrary register
6045 (and currently gen_lowpart might crash for a SUBREG). */
6047 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6050 /* Reject MODEs that aren't scalar integers because turning vector
6051 or complex modes into shifts causes problems. */
6053 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6056 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6057 /* If the inner object has VOIDmode (the only way this can happen
6058 is if it is an ASM_OPERANDS), we can't do anything since we don't
6059 know how much masking to do. */
6068 /* ... fall through ... */
6071 /* If the operand is a CLOBBER, just return it. */
6072 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6075 if (!CONST_INT_P (XEXP (x, 1))
6076 || !CONST_INT_P (XEXP (x, 2))
6077 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6080 /* Reject MODEs that aren't scalar integers because turning vector
6081 or complex modes into shifts causes problems. */
6083 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6086 len = INTVAL (XEXP (x, 1));
6087 pos = INTVAL (XEXP (x, 2));
6089 /* This should stay within the object being extracted, fail otherwise. */
6090 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6093 if (BITS_BIG_ENDIAN)
6094 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6101 /* Convert sign extension to zero extension, if we know that the high
6102 bit is not set, as this is easier to optimize. It will be converted
6103 back to cheaper alternative in make_extraction. */
6104 if (GET_CODE (x) == SIGN_EXTEND
6105 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6106 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6107 & ~(((unsigned HOST_WIDE_INT)
6108 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6112 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6113 rtx temp2 = expand_compound_operation (temp);
6115 /* Make sure this is a profitable operation. */
6116 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6117 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6119 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6120 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6126 /* We can optimize some special cases of ZERO_EXTEND. */
6127 if (GET_CODE (x) == ZERO_EXTEND)
6129 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6130 know that the last value didn't have any inappropriate bits
6132 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6133 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6134 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6135 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6136 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6137 return XEXP (XEXP (x, 0), 0);
6139 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6140 if (GET_CODE (XEXP (x, 0)) == SUBREG
6141 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6142 && subreg_lowpart_p (XEXP (x, 0))
6143 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6144 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6145 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6146 return SUBREG_REG (XEXP (x, 0));
6148 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6149 is a comparison and STORE_FLAG_VALUE permits. This is like
6150 the first case, but it works even when GET_MODE (x) is larger
6151 than HOST_WIDE_INT. */
6152 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6153 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6154 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6155 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6156 <= HOST_BITS_PER_WIDE_INT)
6157 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6158 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6159 return XEXP (XEXP (x, 0), 0);
6161 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6162 if (GET_CODE (XEXP (x, 0)) == SUBREG
6163 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6164 && subreg_lowpart_p (XEXP (x, 0))
6165 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6166 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6167 <= HOST_BITS_PER_WIDE_INT)
6168 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6169 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6170 return SUBREG_REG (XEXP (x, 0));
6174 /* If we reach here, we want to return a pair of shifts. The inner
6175 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6176 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6177 logical depending on the value of UNSIGNEDP.
6179 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6180 converted into an AND of a shift.
6182 We must check for the case where the left shift would have a negative
6183 count. This can happen in a case like (x >> 31) & 255 on machines
6184 that can't shift by a constant. On those machines, we would first
6185 combine the shift with the AND to produce a variable-position
6186 extraction. Then the constant of 31 would be substituted in to produce
6187 a such a position. */
6189 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6190 if (modewidth + len >= pos)
6192 enum machine_mode mode = GET_MODE (x);
6193 tem = gen_lowpart (mode, XEXP (x, 0));
6194 if (!tem || GET_CODE (tem) == CLOBBER)
6196 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6197 tem, modewidth - pos - len);
6198 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6199 mode, tem, modewidth - len);
6201 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6202 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6203 simplify_shift_const (NULL_RTX, LSHIFTRT,
6206 ((HOST_WIDE_INT) 1 << len) - 1);
6208 /* Any other cases we can't handle. */
6211 /* If we couldn't do this for some reason, return the original
6213 if (GET_CODE (tem) == CLOBBER)
6219 /* X is a SET which contains an assignment of one object into
6220 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6221 or certain SUBREGS). If possible, convert it into a series of
6224 We half-heartedly support variable positions, but do not at all
6225 support variable lengths. */
6228 expand_field_assignment (const_rtx x)
6231 rtx pos; /* Always counts from low bit. */
6233 rtx mask, cleared, masked;
6234 enum machine_mode compute_mode;
6236 /* Loop until we find something we can't simplify. */
6239 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6240 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6242 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6243 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6244 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6246 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6247 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6249 inner = XEXP (SET_DEST (x), 0);
6250 len = INTVAL (XEXP (SET_DEST (x), 1));
6251 pos = XEXP (SET_DEST (x), 2);
6253 /* A constant position should stay within the width of INNER. */
6254 if (CONST_INT_P (pos)
6255 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6258 if (BITS_BIG_ENDIAN)
6260 if (CONST_INT_P (pos))
6261 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6263 else if (GET_CODE (pos) == MINUS
6264 && CONST_INT_P (XEXP (pos, 1))
6265 && (INTVAL (XEXP (pos, 1))
6266 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6267 /* If position is ADJUST - X, new position is X. */
6268 pos = XEXP (pos, 0);
6270 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6271 GEN_INT (GET_MODE_BITSIZE (
6278 /* A SUBREG between two modes that occupy the same numbers of words
6279 can be done by moving the SUBREG to the source. */
6280 else if (GET_CODE (SET_DEST (x)) == SUBREG
6281 /* We need SUBREGs to compute nonzero_bits properly. */
6282 && nonzero_sign_valid
6283 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6284 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6285 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6286 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6288 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6290 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6297 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6298 inner = SUBREG_REG (inner);
6300 compute_mode = GET_MODE (inner);
6302 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6303 if (! SCALAR_INT_MODE_P (compute_mode))
6305 enum machine_mode imode;
6307 /* Don't do anything for vector or complex integral types. */
6308 if (! FLOAT_MODE_P (compute_mode))
6311 /* Try to find an integral mode to pun with. */
6312 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6313 if (imode == BLKmode)
6316 compute_mode = imode;
6317 inner = gen_lowpart (imode, inner);
6320 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6321 if (len >= HOST_BITS_PER_WIDE_INT)
6324 /* Now compute the equivalent expression. Make a copy of INNER
6325 for the SET_DEST in case it is a MEM into which we will substitute;
6326 we don't want shared RTL in that case. */
6327 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6328 cleared = simplify_gen_binary (AND, compute_mode,
6329 simplify_gen_unary (NOT, compute_mode,
6330 simplify_gen_binary (ASHIFT,
6335 masked = simplify_gen_binary (ASHIFT, compute_mode,
6336 simplify_gen_binary (
6338 gen_lowpart (compute_mode, SET_SRC (x)),
6342 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6343 simplify_gen_binary (IOR, compute_mode,
6350 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6351 it is an RTX that represents a variable starting position; otherwise,
6352 POS is the (constant) starting bit position (counted from the LSB).
6354 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6357 IN_DEST is nonzero if this is a reference in the destination of a
6358 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6359 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6362 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6363 ZERO_EXTRACT should be built even for bits starting at bit 0.
6365 MODE is the desired mode of the result (if IN_DEST == 0).
6367 The result is an RTX for the extraction or NULL_RTX if the target
6371 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6372 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6373 int in_dest, int in_compare)
6375 /* This mode describes the size of the storage area
6376 to fetch the overall value from. Within that, we
6377 ignore the POS lowest bits, etc. */
6378 enum machine_mode is_mode = GET_MODE (inner);
6379 enum machine_mode inner_mode;
6380 enum machine_mode wanted_inner_mode;
6381 enum machine_mode wanted_inner_reg_mode = word_mode;
6382 enum machine_mode pos_mode = word_mode;
6383 enum machine_mode extraction_mode = word_mode;
6384 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6386 rtx orig_pos_rtx = pos_rtx;
6387 HOST_WIDE_INT orig_pos;
6389 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6391 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6392 consider just the QI as the memory to extract from.
6393 The subreg adds or removes high bits; its mode is
6394 irrelevant to the meaning of this extraction,
6395 since POS and LEN count from the lsb. */
6396 if (MEM_P (SUBREG_REG (inner)))
6397 is_mode = GET_MODE (SUBREG_REG (inner));
6398 inner = SUBREG_REG (inner);
6400 else if (GET_CODE (inner) == ASHIFT
6401 && CONST_INT_P (XEXP (inner, 1))
6402 && pos_rtx == 0 && pos == 0
6403 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6405 /* We're extracting the least significant bits of an rtx
6406 (ashift X (const_int C)), where LEN > C. Extract the
6407 least significant (LEN - C) bits of X, giving an rtx
6408 whose mode is MODE, then shift it left C times. */
6409 new_rtx = make_extraction (mode, XEXP (inner, 0),
6410 0, 0, len - INTVAL (XEXP (inner, 1)),
6411 unsignedp, in_dest, in_compare);
6413 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6416 inner_mode = GET_MODE (inner);
6418 if (pos_rtx && CONST_INT_P (pos_rtx))
6419 pos = INTVAL (pos_rtx), pos_rtx = 0;
6421 /* See if this can be done without an extraction. We never can if the
6422 width of the field is not the same as that of some integer mode. For
6423 registers, we can only avoid the extraction if the position is at the
6424 low-order bit and this is either not in the destination or we have the
6425 appropriate STRICT_LOW_PART operation available.
6427 For MEM, we can avoid an extract if the field starts on an appropriate
6428 boundary and we can change the mode of the memory reference. */
6430 if (tmode != BLKmode
6431 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6433 && (inner_mode == tmode
6435 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6436 GET_MODE_BITSIZE (inner_mode))
6437 || reg_truncated_to_mode (tmode, inner))
6440 && have_insn_for (STRICT_LOW_PART, tmode))))
6441 || (MEM_P (inner) && pos_rtx == 0
6443 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6444 : BITS_PER_UNIT)) == 0
6445 /* We can't do this if we are widening INNER_MODE (it
6446 may not be aligned, for one thing). */
6447 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6448 && (inner_mode == tmode
6449 || (! mode_dependent_address_p (XEXP (inner, 0))
6450 && ! MEM_VOLATILE_P (inner))))))
6452 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6453 field. If the original and current mode are the same, we need not
6454 adjust the offset. Otherwise, we do if bytes big endian.
6456 If INNER is not a MEM, get a piece consisting of just the field
6457 of interest (in this case POS % BITS_PER_WORD must be 0). */
6461 HOST_WIDE_INT offset;
6463 /* POS counts from lsb, but make OFFSET count in memory order. */
6464 if (BYTES_BIG_ENDIAN)
6465 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6467 offset = pos / BITS_PER_UNIT;
6469 new_rtx = adjust_address_nv (inner, tmode, offset);
6471 else if (REG_P (inner))
6473 if (tmode != inner_mode)
6475 /* We can't call gen_lowpart in a DEST since we
6476 always want a SUBREG (see below) and it would sometimes
6477 return a new hard register. */
6480 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6482 if (WORDS_BIG_ENDIAN
6483 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6484 final_word = ((GET_MODE_SIZE (inner_mode)
6485 - GET_MODE_SIZE (tmode))
6486 / UNITS_PER_WORD) - final_word;
6488 final_word *= UNITS_PER_WORD;
6489 if (BYTES_BIG_ENDIAN &&
6490 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6491 final_word += (GET_MODE_SIZE (inner_mode)
6492 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6494 /* Avoid creating invalid subregs, for example when
6495 simplifying (x>>32)&255. */
6496 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6499 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6502 new_rtx = gen_lowpart (tmode, inner);
6508 new_rtx = force_to_mode (inner, tmode,
6509 len >= HOST_BITS_PER_WIDE_INT
6510 ? ~(unsigned HOST_WIDE_INT) 0
6511 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6514 /* If this extraction is going into the destination of a SET,
6515 make a STRICT_LOW_PART unless we made a MEM. */
6518 return (MEM_P (new_rtx) ? new_rtx
6519 : (GET_CODE (new_rtx) != SUBREG
6520 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6521 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6526 if (CONST_INT_P (new_rtx))
6527 return gen_int_mode (INTVAL (new_rtx), mode);
6529 /* If we know that no extraneous bits are set, and that the high
6530 bit is not set, convert the extraction to the cheaper of
6531 sign and zero extension, that are equivalent in these cases. */
6532 if (flag_expensive_optimizations
6533 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6534 && ((nonzero_bits (new_rtx, tmode)
6535 & ~(((unsigned HOST_WIDE_INT)
6536 GET_MODE_MASK (tmode))
6540 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6541 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6543 /* Prefer ZERO_EXTENSION, since it gives more information to
6545 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6546 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6551 /* Otherwise, sign- or zero-extend unless we already are in the
6554 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6558 /* Unless this is a COMPARE or we have a funny memory reference,
6559 don't do anything with zero-extending field extracts starting at
6560 the low-order bit since they are simple AND operations. */
6561 if (pos_rtx == 0 && pos == 0 && ! in_dest
6562 && ! in_compare && unsignedp)
6565 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6566 if the position is not a constant and the length is not 1. In all
6567 other cases, we would only be going outside our object in cases when
6568 an original shift would have been undefined. */
6570 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6571 || (pos_rtx != 0 && len != 1)))
6574 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6575 and the mode for the result. */
6576 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6578 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6579 pos_mode = mode_for_extraction (EP_insv, 2);
6580 extraction_mode = mode_for_extraction (EP_insv, 3);
6583 if (! in_dest && unsignedp
6584 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6586 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6587 pos_mode = mode_for_extraction (EP_extzv, 3);
6588 extraction_mode = mode_for_extraction (EP_extzv, 0);
6591 if (! in_dest && ! unsignedp
6592 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6594 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6595 pos_mode = mode_for_extraction (EP_extv, 3);
6596 extraction_mode = mode_for_extraction (EP_extv, 0);
6599 /* Never narrow an object, since that might not be safe. */
6601 if (mode != VOIDmode
6602 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6603 extraction_mode = mode;
6605 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6606 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6607 pos_mode = GET_MODE (pos_rtx);
6609 /* If this is not from memory, the desired mode is the preferred mode
6610 for an extraction pattern's first input operand, or word_mode if there
6613 wanted_inner_mode = wanted_inner_reg_mode;
6616 /* Be careful not to go beyond the extracted object and maintain the
6617 natural alignment of the memory. */
6618 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6619 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6620 > GET_MODE_BITSIZE (wanted_inner_mode))
6622 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6623 gcc_assert (wanted_inner_mode != VOIDmode);
6626 /* If we have to change the mode of memory and cannot, the desired mode
6627 is EXTRACTION_MODE. */
6628 if (inner_mode != wanted_inner_mode
6629 && (mode_dependent_address_p (XEXP (inner, 0))
6630 || MEM_VOLATILE_P (inner)
6632 wanted_inner_mode = extraction_mode;
6637 if (BITS_BIG_ENDIAN)
6639 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6640 BITS_BIG_ENDIAN style. If position is constant, compute new
6641 position. Otherwise, build subtraction.
6642 Note that POS is relative to the mode of the original argument.
6643 If it's a MEM we need to recompute POS relative to that.
6644 However, if we're extracting from (or inserting into) a register,
6645 we want to recompute POS relative to wanted_inner_mode. */
6646 int width = (MEM_P (inner)
6647 ? GET_MODE_BITSIZE (is_mode)
6648 : GET_MODE_BITSIZE (wanted_inner_mode));
6651 pos = width - len - pos;
6654 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6655 /* POS may be less than 0 now, but we check for that below.
6656 Note that it can only be less than 0 if !MEM_P (inner). */
6659 /* If INNER has a wider mode, and this is a constant extraction, try to
6660 make it smaller and adjust the byte to point to the byte containing
6662 if (wanted_inner_mode != VOIDmode
6663 && inner_mode != wanted_inner_mode
6665 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6667 && ! mode_dependent_address_p (XEXP (inner, 0))
6668 && ! MEM_VOLATILE_P (inner))
6672 /* The computations below will be correct if the machine is big
6673 endian in both bits and bytes or little endian in bits and bytes.
6674 If it is mixed, we must adjust. */
6676 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6677 adjust OFFSET to compensate. */
6678 if (BYTES_BIG_ENDIAN
6679 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6680 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6682 /* We can now move to the desired byte. */
6683 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6684 * GET_MODE_SIZE (wanted_inner_mode);
6685 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6687 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6688 && is_mode != wanted_inner_mode)
6689 offset = (GET_MODE_SIZE (is_mode)
6690 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6692 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6695 /* If INNER is not memory, get it into the proper mode. If we are changing
6696 its mode, POS must be a constant and smaller than the size of the new
6698 else if (!MEM_P (inner))
6700 /* On the LHS, don't create paradoxical subregs implicitely truncating
6701 the register unless TRULY_NOOP_TRUNCATION. */
6703 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6704 GET_MODE_BITSIZE (wanted_inner_mode)))
6707 if (GET_MODE (inner) != wanted_inner_mode
6709 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6715 inner = force_to_mode (inner, wanted_inner_mode,
6717 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6718 ? ~(unsigned HOST_WIDE_INT) 0
6719 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6724 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6725 have to zero extend. Otherwise, we can just use a SUBREG. */
6727 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6729 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6731 /* If we know that no extraneous bits are set, and that the high
6732 bit is not set, convert extraction to cheaper one - either
6733 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6735 if (flag_expensive_optimizations
6736 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6737 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6738 & ~(((unsigned HOST_WIDE_INT)
6739 GET_MODE_MASK (GET_MODE (pos_rtx)))
6743 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6745 /* Prefer ZERO_EXTENSION, since it gives more information to
6747 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6748 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6753 else if (pos_rtx != 0
6754 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6755 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6757 /* Make POS_RTX unless we already have it and it is correct. If we don't
6758 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6760 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6761 pos_rtx = orig_pos_rtx;
6763 else if (pos_rtx == 0)
6764 pos_rtx = GEN_INT (pos);
6766 /* Make the required operation. See if we can use existing rtx. */
6767 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6768 extraction_mode, inner, GEN_INT (len), pos_rtx);
6770 new_rtx = gen_lowpart (mode, new_rtx);
6775 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6776 with any other operations in X. Return X without that shift if so. */
6779 extract_left_shift (rtx x, int count)
6781 enum rtx_code code = GET_CODE (x);
6782 enum machine_mode mode = GET_MODE (x);
6788 /* This is the shift itself. If it is wide enough, we will return
6789 either the value being shifted if the shift count is equal to
6790 COUNT or a shift for the difference. */
6791 if (CONST_INT_P (XEXP (x, 1))
6792 && INTVAL (XEXP (x, 1)) >= count)
6793 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6794 INTVAL (XEXP (x, 1)) - count);
6798 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6799 return simplify_gen_unary (code, mode, tem, mode);
6803 case PLUS: case IOR: case XOR: case AND:
6804 /* If we can safely shift this constant and we find the inner shift,
6805 make a new operation. */
6806 if (CONST_INT_P (XEXP (x, 1))
6807 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6808 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6809 return simplify_gen_binary (code, mode, tem,
6810 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6821 /* Look at the expression rooted at X. Look for expressions
6822 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6823 Form these expressions.
6825 Return the new rtx, usually just X.
6827 Also, for machines like the VAX that don't have logical shift insns,
6828 try to convert logical to arithmetic shift operations in cases where
6829 they are equivalent. This undoes the canonicalizations to logical
6830 shifts done elsewhere.
6832 We try, as much as possible, to re-use rtl expressions to save memory.
6834 IN_CODE says what kind of expression we are processing. Normally, it is
6835 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6836 being kludges), it is MEM. When processing the arguments of a comparison
6837 or a COMPARE against zero, it is COMPARE. */
6840 make_compound_operation (rtx x, enum rtx_code in_code)
6842 enum rtx_code code = GET_CODE (x);
6843 enum machine_mode mode = GET_MODE (x);
6844 int mode_width = GET_MODE_BITSIZE (mode);
6846 enum rtx_code next_code;
6852 /* Select the code to be used in recursive calls. Once we are inside an
6853 address, we stay there. If we have a comparison, set to COMPARE,
6854 but once inside, go back to our default of SET. */
6856 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6857 : ((code == COMPARE || COMPARISON_P (x))
6858 && XEXP (x, 1) == const0_rtx) ? COMPARE
6859 : in_code == COMPARE ? SET : in_code);
6861 /* Process depending on the code of this operation. If NEW is set
6862 nonzero, it will be returned. */
6867 /* Convert shifts by constants into multiplications if inside
6869 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
6870 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6871 && INTVAL (XEXP (x, 1)) >= 0)
6873 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6874 new_rtx = gen_rtx_MULT (mode, new_rtx,
6875 GEN_INT ((HOST_WIDE_INT) 1
6876 << INTVAL (XEXP (x, 1))));
6881 /* If the second operand is not a constant, we can't do anything
6883 if (!CONST_INT_P (XEXP (x, 1)))
6886 /* If the constant is a power of two minus one and the first operand
6887 is a logical right shift, make an extraction. */
6888 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6889 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6891 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6892 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6893 0, in_code == COMPARE);
6896 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6897 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6898 && subreg_lowpart_p (XEXP (x, 0))
6899 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6900 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6902 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6904 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6905 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6906 0, in_code == COMPARE);
6908 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6909 else if ((GET_CODE (XEXP (x, 0)) == XOR
6910 || GET_CODE (XEXP (x, 0)) == IOR)
6911 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6912 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6913 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6915 /* Apply the distributive law, and then try to make extractions. */
6916 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6917 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6919 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6921 new_rtx = make_compound_operation (new_rtx, in_code);
6924 /* If we are have (and (rotate X C) M) and C is larger than the number
6925 of bits in M, this is an extraction. */
6927 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6928 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6929 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6930 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6932 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6933 new_rtx = make_extraction (mode, new_rtx,
6934 (GET_MODE_BITSIZE (mode)
6935 - INTVAL (XEXP (XEXP (x, 0), 1))),
6936 NULL_RTX, i, 1, 0, in_code == COMPARE);
6939 /* On machines without logical shifts, if the operand of the AND is
6940 a logical shift and our mask turns off all the propagated sign
6941 bits, we can replace the logical shift with an arithmetic shift. */
6942 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6943 && !have_insn_for (LSHIFTRT, mode)
6944 && have_insn_for (ASHIFTRT, mode)
6945 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6946 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6947 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6948 && mode_width <= HOST_BITS_PER_WIDE_INT)
6950 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6952 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6953 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6955 gen_rtx_ASHIFTRT (mode,
6956 make_compound_operation
6957 (XEXP (XEXP (x, 0), 0), next_code),
6958 XEXP (XEXP (x, 0), 1)));
6961 /* If the constant is one less than a power of two, this might be
6962 representable by an extraction even if no shift is present.
6963 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6964 we are in a COMPARE. */
6965 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6966 new_rtx = make_extraction (mode,
6967 make_compound_operation (XEXP (x, 0),
6969 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6971 /* If we are in a comparison and this is an AND with a power of two,
6972 convert this into the appropriate bit extract. */
6973 else if (in_code == COMPARE
6974 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6975 new_rtx = make_extraction (mode,
6976 make_compound_operation (XEXP (x, 0),
6978 i, NULL_RTX, 1, 1, 0, 1);
6983 /* If the sign bit is known to be zero, replace this with an
6984 arithmetic shift. */
6985 if (have_insn_for (ASHIFTRT, mode)
6986 && ! have_insn_for (LSHIFTRT, mode)
6987 && mode_width <= HOST_BITS_PER_WIDE_INT
6988 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6990 new_rtx = gen_rtx_ASHIFTRT (mode,
6991 make_compound_operation (XEXP (x, 0),
6997 /* ... fall through ... */
7003 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7004 this is a SIGN_EXTRACT. */
7005 if (CONST_INT_P (rhs)
7006 && GET_CODE (lhs) == ASHIFT
7007 && CONST_INT_P (XEXP (lhs, 1))
7008 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7009 && INTVAL (rhs) < mode_width)
7011 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7012 new_rtx = make_extraction (mode, new_rtx,
7013 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7014 NULL_RTX, mode_width - INTVAL (rhs),
7015 code == LSHIFTRT, 0, in_code == COMPARE);
7019 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7020 If so, try to merge the shifts into a SIGN_EXTEND. We could
7021 also do this for some cases of SIGN_EXTRACT, but it doesn't
7022 seem worth the effort; the case checked for occurs on Alpha. */
7025 && ! (GET_CODE (lhs) == SUBREG
7026 && (OBJECT_P (SUBREG_REG (lhs))))
7027 && CONST_INT_P (rhs)
7028 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7029 && INTVAL (rhs) < mode_width
7030 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7031 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7032 0, NULL_RTX, mode_width - INTVAL (rhs),
7033 code == LSHIFTRT, 0, in_code == COMPARE);
7038 /* Call ourselves recursively on the inner expression. If we are
7039 narrowing the object and it has a different RTL code from
7040 what it originally did, do this SUBREG as a force_to_mode. */
7042 tem = make_compound_operation (SUBREG_REG (x), in_code);
7046 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7052 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7053 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7054 && subreg_lowpart_p (x))
7056 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7059 /* If we have something other than a SUBREG, we might have
7060 done an expansion, so rerun ourselves. */
7061 if (GET_CODE (newer) != SUBREG)
7062 newer = make_compound_operation (newer, in_code);
7078 x = gen_lowpart (mode, new_rtx);
7079 code = GET_CODE (x);
7082 /* Now recursively process each operand of this operation. */
7083 fmt = GET_RTX_FORMAT (code);
7084 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7087 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7088 SUBST (XEXP (x, i), new_rtx);
7090 else if (fmt[i] == 'E')
7091 for (j = 0; j < XVECLEN (x, i); j++)
7093 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7094 SUBST (XVECEXP (x, i, j), new_rtx);
7097 /* If this is a commutative operation, the changes to the operands
7098 may have made it noncanonical. */
7099 if (COMMUTATIVE_ARITH_P (x)
7100 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7103 SUBST (XEXP (x, 0), XEXP (x, 1));
7104 SUBST (XEXP (x, 1), tem);
7110 /* Given M see if it is a value that would select a field of bits
7111 within an item, but not the entire word. Return -1 if not.
7112 Otherwise, return the starting position of the field, where 0 is the
7115 *PLEN is set to the length of the field. */
7118 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7120 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7121 int pos = exact_log2 (m & -m);
7125 /* Now shift off the low-order zero bits and see if we have a
7126 power of two minus 1. */
7127 len = exact_log2 ((m >> pos) + 1);
7136 /* If X refers to a register that equals REG in value, replace these
7137 references with REG. */
7139 canon_reg_for_combine (rtx x, rtx reg)
7146 enum rtx_code code = GET_CODE (x);
7147 switch (GET_RTX_CLASS (code))
7150 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7151 if (op0 != XEXP (x, 0))
7152 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7157 case RTX_COMM_ARITH:
7158 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7159 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7160 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7161 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7165 case RTX_COMM_COMPARE:
7166 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7167 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7168 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7169 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7170 GET_MODE (op0), op0, op1);
7174 case RTX_BITFIELD_OPS:
7175 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7176 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7177 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7178 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7179 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7180 GET_MODE (op0), op0, op1, op2);
7185 if (rtx_equal_p (get_last_value (reg), x)
7186 || rtx_equal_p (reg, get_last_value (x)))
7195 fmt = GET_RTX_FORMAT (code);
7197 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7200 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7201 if (op != XEXP (x, i))
7211 else if (fmt[i] == 'E')
7214 for (j = 0; j < XVECLEN (x, i); j++)
7216 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7217 if (op != XVECEXP (x, i, j))
7224 XVECEXP (x, i, j) = op;
7235 /* Return X converted to MODE. If the value is already truncated to
7236 MODE we can just return a subreg even though in the general case we
7237 would need an explicit truncation. */
7240 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7242 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7243 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7244 GET_MODE_BITSIZE (GET_MODE (x)))
7245 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7246 return gen_lowpart (mode, x);
7248 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7251 /* See if X can be simplified knowing that we will only refer to it in
7252 MODE and will only refer to those bits that are nonzero in MASK.
7253 If other bits are being computed or if masking operations are done
7254 that select a superset of the bits in MASK, they can sometimes be
7257 Return a possibly simplified expression, but always convert X to
7258 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7260 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7261 are all off in X. This is used when X will be complemented, by either
7262 NOT, NEG, or XOR. */
7265 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7268 enum rtx_code code = GET_CODE (x);
7269 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7270 enum machine_mode op_mode;
7271 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7274 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7275 code below will do the wrong thing since the mode of such an
7276 expression is VOIDmode.
7278 Also do nothing if X is a CLOBBER; this can happen if X was
7279 the return value from a call to gen_lowpart. */
7280 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7283 /* We want to perform the operation is its present mode unless we know
7284 that the operation is valid in MODE, in which case we do the operation
7286 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7287 && have_insn_for (code, mode))
7288 ? mode : GET_MODE (x));
7290 /* It is not valid to do a right-shift in a narrower mode
7291 than the one it came in with. */
7292 if ((code == LSHIFTRT || code == ASHIFTRT)
7293 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7294 op_mode = GET_MODE (x);
7296 /* Truncate MASK to fit OP_MODE. */
7298 mask &= GET_MODE_MASK (op_mode);
7300 /* When we have an arithmetic operation, or a shift whose count we
7301 do not know, we need to assume that all bits up to the highest-order
7302 bit in MASK will be needed. This is how we form such a mask. */
7303 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7304 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7306 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7309 /* Determine what bits of X are guaranteed to be (non)zero. */
7310 nonzero = nonzero_bits (x, mode);
7312 /* If none of the bits in X are needed, return a zero. */
7313 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7316 /* If X is a CONST_INT, return a new one. Do this here since the
7317 test below will fail. */
7318 if (CONST_INT_P (x))
7320 if (SCALAR_INT_MODE_P (mode))
7321 return gen_int_mode (INTVAL (x) & mask, mode);
7324 x = GEN_INT (INTVAL (x) & mask);
7325 return gen_lowpart_common (mode, x);
7329 /* If X is narrower than MODE and we want all the bits in X's mode, just
7330 get X in the proper mode. */
7331 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7332 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7333 return gen_lowpart (mode, x);
7335 /* The arithmetic simplifications here do the wrong thing on vector modes. */
7336 if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x)))
7337 return gen_lowpart (mode, x);
7342 /* If X is a (clobber (const_int)), return it since we know we are
7343 generating something that won't match. */
7350 x = expand_compound_operation (x);
7351 if (GET_CODE (x) != code)
7352 return force_to_mode (x, mode, mask, next_select);
7356 if (subreg_lowpart_p (x)
7357 /* We can ignore the effect of this SUBREG if it narrows the mode or
7358 if the constant masks to zero all the bits the mode doesn't
7360 && ((GET_MODE_SIZE (GET_MODE (x))
7361 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7363 & GET_MODE_MASK (GET_MODE (x))
7364 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7365 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7369 /* Similarly for a truncate. */
7370 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7373 /* If this is an AND with a constant, convert it into an AND
7374 whose constant is the AND of that constant with MASK. If it
7375 remains an AND of MASK, delete it since it is redundant. */
7377 if (CONST_INT_P (XEXP (x, 1)))
7379 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7380 mask & INTVAL (XEXP (x, 1)));
7382 /* If X is still an AND, see if it is an AND with a mask that
7383 is just some low-order bits. If so, and it is MASK, we don't
7386 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7387 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7391 /* If it remains an AND, try making another AND with the bits
7392 in the mode mask that aren't in MASK turned on. If the
7393 constant in the AND is wide enough, this might make a
7394 cheaper constant. */
7396 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7397 && GET_MODE_MASK (GET_MODE (x)) != mask
7398 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7400 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7401 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7402 int width = GET_MODE_BITSIZE (GET_MODE (x));
7405 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7406 number, sign extend it. */
7407 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7408 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7409 cval |= (HOST_WIDE_INT) -1 << width;
7411 y = simplify_gen_binary (AND, GET_MODE (x),
7412 XEXP (x, 0), GEN_INT (cval));
7413 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7414 < rtx_cost (x, SET, optimize_this_for_speed_p))
7424 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7425 low-order bits (as in an alignment operation) and FOO is already
7426 aligned to that boundary, mask C1 to that boundary as well.
7427 This may eliminate that PLUS and, later, the AND. */
7430 unsigned int width = GET_MODE_BITSIZE (mode);
7431 unsigned HOST_WIDE_INT smask = mask;
7433 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7434 number, sign extend it. */
7436 if (width < HOST_BITS_PER_WIDE_INT
7437 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7438 smask |= (HOST_WIDE_INT) -1 << width;
7440 if (CONST_INT_P (XEXP (x, 1))
7441 && exact_log2 (- smask) >= 0
7442 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7443 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7444 return force_to_mode (plus_constant (XEXP (x, 0),
7445 (INTVAL (XEXP (x, 1)) & smask)),
7446 mode, smask, next_select);
7449 /* ... fall through ... */
7452 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7453 most significant bit in MASK since carries from those bits will
7454 affect the bits we are interested in. */
7459 /* If X is (minus C Y) where C's least set bit is larger than any bit
7460 in the mask, then we may replace with (neg Y). */
7461 if (CONST_INT_P (XEXP (x, 0))
7462 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7463 & -INTVAL (XEXP (x, 0))))
7466 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7468 return force_to_mode (x, mode, mask, next_select);
7471 /* Similarly, if C contains every bit in the fuller_mask, then we may
7472 replace with (not Y). */
7473 if (CONST_INT_P (XEXP (x, 0))
7474 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7475 == INTVAL (XEXP (x, 0))))
7477 x = simplify_gen_unary (NOT, GET_MODE (x),
7478 XEXP (x, 1), GET_MODE (x));
7479 return force_to_mode (x, mode, mask, next_select);
7487 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7488 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7489 operation which may be a bitfield extraction. Ensure that the
7490 constant we form is not wider than the mode of X. */
7492 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7493 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7494 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7495 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7496 && CONST_INT_P (XEXP (x, 1))
7497 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7498 + floor_log2 (INTVAL (XEXP (x, 1))))
7499 < GET_MODE_BITSIZE (GET_MODE (x)))
7500 && (INTVAL (XEXP (x, 1))
7501 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7503 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7504 << INTVAL (XEXP (XEXP (x, 0), 1)));
7505 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7506 XEXP (XEXP (x, 0), 0), temp);
7507 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7508 XEXP (XEXP (x, 0), 1));
7509 return force_to_mode (x, mode, mask, next_select);
7513 /* For most binary operations, just propagate into the operation and
7514 change the mode if we have an operation of that mode. */
7516 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7517 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7519 /* If we ended up truncating both operands, truncate the result of the
7520 operation instead. */
7521 if (GET_CODE (op0) == TRUNCATE
7522 && GET_CODE (op1) == TRUNCATE)
7524 op0 = XEXP (op0, 0);
7525 op1 = XEXP (op1, 0);
7528 op0 = gen_lowpart_or_truncate (op_mode, op0);
7529 op1 = gen_lowpart_or_truncate (op_mode, op1);
7531 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7532 x = simplify_gen_binary (code, op_mode, op0, op1);
7536 /* For left shifts, do the same, but just for the first operand.
7537 However, we cannot do anything with shifts where we cannot
7538 guarantee that the counts are smaller than the size of the mode
7539 because such a count will have a different meaning in a
7542 if (! (CONST_INT_P (XEXP (x, 1))
7543 && INTVAL (XEXP (x, 1)) >= 0
7544 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7545 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7546 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7547 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7550 /* If the shift count is a constant and we can do arithmetic in
7551 the mode of the shift, refine which bits we need. Otherwise, use the
7552 conservative form of the mask. */
7553 if (CONST_INT_P (XEXP (x, 1))
7554 && INTVAL (XEXP (x, 1)) >= 0
7555 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7556 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7557 mask >>= INTVAL (XEXP (x, 1));
7561 op0 = gen_lowpart_or_truncate (op_mode,
7562 force_to_mode (XEXP (x, 0), op_mode,
7563 mask, next_select));
7565 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7566 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7570 /* Here we can only do something if the shift count is a constant,
7571 this shift constant is valid for the host, and we can do arithmetic
7574 if (CONST_INT_P (XEXP (x, 1))
7575 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7576 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7578 rtx inner = XEXP (x, 0);
7579 unsigned HOST_WIDE_INT inner_mask;
7581 /* Select the mask of the bits we need for the shift operand. */
7582 inner_mask = mask << INTVAL (XEXP (x, 1));
7584 /* We can only change the mode of the shift if we can do arithmetic
7585 in the mode of the shift and INNER_MASK is no wider than the
7586 width of X's mode. */
7587 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7588 op_mode = GET_MODE (x);
7590 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7592 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7593 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7596 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7597 shift and AND produces only copies of the sign bit (C2 is one less
7598 than a power of two), we can do this with just a shift. */
7600 if (GET_CODE (x) == LSHIFTRT
7601 && CONST_INT_P (XEXP (x, 1))
7602 /* The shift puts one of the sign bit copies in the least significant
7604 && ((INTVAL (XEXP (x, 1))
7605 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7606 >= GET_MODE_BITSIZE (GET_MODE (x)))
7607 && exact_log2 (mask + 1) >= 0
7608 /* Number of bits left after the shift must be more than the mask
7610 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7611 <= GET_MODE_BITSIZE (GET_MODE (x)))
7612 /* Must be more sign bit copies than the mask needs. */
7613 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7614 >= exact_log2 (mask + 1)))
7615 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7616 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7617 - exact_log2 (mask + 1)));
7622 /* If we are just looking for the sign bit, we don't need this shift at
7623 all, even if it has a variable count. */
7624 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7625 && (mask == ((unsigned HOST_WIDE_INT) 1
7626 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7627 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7629 /* If this is a shift by a constant, get a mask that contains those bits
7630 that are not copies of the sign bit. We then have two cases: If
7631 MASK only includes those bits, this can be a logical shift, which may
7632 allow simplifications. If MASK is a single-bit field not within
7633 those bits, we are requesting a copy of the sign bit and hence can
7634 shift the sign bit to the appropriate location. */
7636 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7637 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7641 /* If the considered data is wider than HOST_WIDE_INT, we can't
7642 represent a mask for all its bits in a single scalar.
7643 But we only care about the lower bits, so calculate these. */
7645 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7647 nonzero = ~(HOST_WIDE_INT) 0;
7649 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7650 is the number of bits a full-width mask would have set.
7651 We need only shift if these are fewer than nonzero can
7652 hold. If not, we must keep all bits set in nonzero. */
7654 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7655 < HOST_BITS_PER_WIDE_INT)
7656 nonzero >>= INTVAL (XEXP (x, 1))
7657 + HOST_BITS_PER_WIDE_INT
7658 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7662 nonzero = GET_MODE_MASK (GET_MODE (x));
7663 nonzero >>= INTVAL (XEXP (x, 1));
7666 if ((mask & ~nonzero) == 0)
7668 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7669 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7670 if (GET_CODE (x) != ASHIFTRT)
7671 return force_to_mode (x, mode, mask, next_select);
7674 else if ((i = exact_log2 (mask)) >= 0)
7676 x = simplify_shift_const
7677 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7678 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7680 if (GET_CODE (x) != ASHIFTRT)
7681 return force_to_mode (x, mode, mask, next_select);
7685 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7686 even if the shift count isn't a constant. */
7688 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7689 XEXP (x, 0), XEXP (x, 1));
7693 /* If this is a zero- or sign-extension operation that just affects bits
7694 we don't care about, remove it. Be sure the call above returned
7695 something that is still a shift. */
7697 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7698 && CONST_INT_P (XEXP (x, 1))
7699 && INTVAL (XEXP (x, 1)) >= 0
7700 && (INTVAL (XEXP (x, 1))
7701 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7702 && GET_CODE (XEXP (x, 0)) == ASHIFT
7703 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7704 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7711 /* If the shift count is constant and we can do computations
7712 in the mode of X, compute where the bits we care about are.
7713 Otherwise, we can't do anything. Don't change the mode of
7714 the shift or propagate MODE into the shift, though. */
7715 if (CONST_INT_P (XEXP (x, 1))
7716 && INTVAL (XEXP (x, 1)) >= 0)
7718 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7719 GET_MODE (x), GEN_INT (mask),
7721 if (temp && CONST_INT_P (temp))
7723 force_to_mode (XEXP (x, 0), GET_MODE (x),
7724 INTVAL (temp), next_select));
7729 /* If we just want the low-order bit, the NEG isn't needed since it
7730 won't change the low-order bit. */
7732 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7734 /* We need any bits less significant than the most significant bit in
7735 MASK since carries from those bits will affect the bits we are
7741 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7742 same as the XOR case above. Ensure that the constant we form is not
7743 wider than the mode of X. */
7745 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7746 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7747 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7748 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7749 < GET_MODE_BITSIZE (GET_MODE (x)))
7750 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7752 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7754 temp = simplify_gen_binary (XOR, GET_MODE (x),
7755 XEXP (XEXP (x, 0), 0), temp);
7756 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7757 temp, XEXP (XEXP (x, 0), 1));
7759 return force_to_mode (x, mode, mask, next_select);
7762 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7763 use the full mask inside the NOT. */
7767 op0 = gen_lowpart_or_truncate (op_mode,
7768 force_to_mode (XEXP (x, 0), mode, mask,
7770 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7771 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7775 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7776 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7777 which is equal to STORE_FLAG_VALUE. */
7778 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7779 && GET_MODE (XEXP (x, 0)) == mode
7780 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7781 && (nonzero_bits (XEXP (x, 0), mode)
7782 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7783 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7788 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7789 written in a narrower mode. We play it safe and do not do so. */
7792 gen_lowpart_or_truncate (GET_MODE (x),
7793 force_to_mode (XEXP (x, 1), mode,
7794 mask, next_select)));
7796 gen_lowpart_or_truncate (GET_MODE (x),
7797 force_to_mode (XEXP (x, 2), mode,
7798 mask, next_select)));
7805 /* Ensure we return a value of the proper mode. */
7806 return gen_lowpart_or_truncate (mode, x);
7809 /* Return nonzero if X is an expression that has one of two values depending on
7810 whether some other value is zero or nonzero. In that case, we return the
7811 value that is being tested, *PTRUE is set to the value if the rtx being
7812 returned has a nonzero value, and *PFALSE is set to the other alternative.
7814 If we return zero, we set *PTRUE and *PFALSE to X. */
7817 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7819 enum machine_mode mode = GET_MODE (x);
7820 enum rtx_code code = GET_CODE (x);
7821 rtx cond0, cond1, true0, true1, false0, false1;
7822 unsigned HOST_WIDE_INT nz;
7824 /* If we are comparing a value against zero, we are done. */
7825 if ((code == NE || code == EQ)
7826 && XEXP (x, 1) == const0_rtx)
7828 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7829 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7833 /* If this is a unary operation whose operand has one of two values, apply
7834 our opcode to compute those values. */
7835 else if (UNARY_P (x)
7836 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7838 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7839 *pfalse = simplify_gen_unary (code, mode, false0,
7840 GET_MODE (XEXP (x, 0)));
7844 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7845 make can't possibly match and would suppress other optimizations. */
7846 else if (code == COMPARE)
7849 /* If this is a binary operation, see if either side has only one of two
7850 values. If either one does or if both do and they are conditional on
7851 the same value, compute the new true and false values. */
7852 else if (BINARY_P (x))
7854 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7855 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7857 if ((cond0 != 0 || cond1 != 0)
7858 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7860 /* If if_then_else_cond returned zero, then true/false are the
7861 same rtl. We must copy one of them to prevent invalid rtl
7864 true0 = copy_rtx (true0);
7865 else if (cond1 == 0)
7866 true1 = copy_rtx (true1);
7868 if (COMPARISON_P (x))
7870 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7872 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7877 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7878 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7881 return cond0 ? cond0 : cond1;
7884 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7885 operands is zero when the other is nonzero, and vice-versa,
7886 and STORE_FLAG_VALUE is 1 or -1. */
7888 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7889 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7891 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7893 rtx op0 = XEXP (XEXP (x, 0), 1);
7894 rtx op1 = XEXP (XEXP (x, 1), 1);
7896 cond0 = XEXP (XEXP (x, 0), 0);
7897 cond1 = XEXP (XEXP (x, 1), 0);
7899 if (COMPARISON_P (cond0)
7900 && COMPARISON_P (cond1)
7901 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7902 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7903 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7904 || ((swap_condition (GET_CODE (cond0))
7905 == reversed_comparison_code (cond1, NULL))
7906 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7907 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7908 && ! side_effects_p (x))
7910 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7911 *pfalse = simplify_gen_binary (MULT, mode,
7913 ? simplify_gen_unary (NEG, mode,
7921 /* Similarly for MULT, AND and UMIN, except that for these the result
7923 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7924 && (code == MULT || code == AND || code == UMIN)
7925 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7927 cond0 = XEXP (XEXP (x, 0), 0);
7928 cond1 = XEXP (XEXP (x, 1), 0);
7930 if (COMPARISON_P (cond0)
7931 && COMPARISON_P (cond1)
7932 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7933 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7934 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7935 || ((swap_condition (GET_CODE (cond0))
7936 == reversed_comparison_code (cond1, NULL))
7937 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7938 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7939 && ! side_effects_p (x))
7941 *ptrue = *pfalse = const0_rtx;
7947 else if (code == IF_THEN_ELSE)
7949 /* If we have IF_THEN_ELSE already, extract the condition and
7950 canonicalize it if it is NE or EQ. */
7951 cond0 = XEXP (x, 0);
7952 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7953 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7954 return XEXP (cond0, 0);
7955 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7957 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7958 return XEXP (cond0, 0);
7964 /* If X is a SUBREG, we can narrow both the true and false values
7965 if the inner expression, if there is a condition. */
7966 else if (code == SUBREG
7967 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7970 true0 = simplify_gen_subreg (mode, true0,
7971 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7972 false0 = simplify_gen_subreg (mode, false0,
7973 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7974 if (true0 && false0)
7982 /* If X is a constant, this isn't special and will cause confusions
7983 if we treat it as such. Likewise if it is equivalent to a constant. */
7984 else if (CONSTANT_P (x)
7985 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7988 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7989 will be least confusing to the rest of the compiler. */
7990 else if (mode == BImode)
7992 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7996 /* If X is known to be either 0 or -1, those are the true and
7997 false values when testing X. */
7998 else if (x == constm1_rtx || x == const0_rtx
7999 || (mode != VOIDmode
8000 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8002 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8006 /* Likewise for 0 or a single bit. */
8007 else if (SCALAR_INT_MODE_P (mode)
8008 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8009 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8011 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8015 /* Otherwise fail; show no condition with true and false values the same. */
8016 *ptrue = *pfalse = x;
8020 /* Return the value of expression X given the fact that condition COND
8021 is known to be true when applied to REG as its first operand and VAL
8022 as its second. X is known to not be shared and so can be modified in
8025 We only handle the simplest cases, and specifically those cases that
8026 arise with IF_THEN_ELSE expressions. */
8029 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8031 enum rtx_code code = GET_CODE (x);
8036 if (side_effects_p (x))
8039 /* If either operand of the condition is a floating point value,
8040 then we have to avoid collapsing an EQ comparison. */
8042 && rtx_equal_p (x, reg)
8043 && ! FLOAT_MODE_P (GET_MODE (x))
8044 && ! FLOAT_MODE_P (GET_MODE (val)))
8047 if (cond == UNEQ && rtx_equal_p (x, reg))
8050 /* If X is (abs REG) and we know something about REG's relationship
8051 with zero, we may be able to simplify this. */
8053 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8056 case GE: case GT: case EQ:
8059 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8061 GET_MODE (XEXP (x, 0)));
8066 /* The only other cases we handle are MIN, MAX, and comparisons if the
8067 operands are the same as REG and VAL. */
8069 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8071 if (rtx_equal_p (XEXP (x, 0), val))
8072 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8074 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8076 if (COMPARISON_P (x))
8078 if (comparison_dominates_p (cond, code))
8079 return const_true_rtx;
8081 code = reversed_comparison_code (x, NULL);
8083 && comparison_dominates_p (cond, code))
8088 else if (code == SMAX || code == SMIN
8089 || code == UMIN || code == UMAX)
8091 int unsignedp = (code == UMIN || code == UMAX);
8093 /* Do not reverse the condition when it is NE or EQ.
8094 This is because we cannot conclude anything about
8095 the value of 'SMAX (x, y)' when x is not equal to y,
8096 but we can when x equals y. */
8097 if ((code == SMAX || code == UMAX)
8098 && ! (cond == EQ || cond == NE))
8099 cond = reverse_condition (cond);
8104 return unsignedp ? x : XEXP (x, 1);
8106 return unsignedp ? x : XEXP (x, 0);
8108 return unsignedp ? XEXP (x, 1) : x;
8110 return unsignedp ? XEXP (x, 0) : x;
8117 else if (code == SUBREG)
8119 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8120 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8122 if (SUBREG_REG (x) != r)
8124 /* We must simplify subreg here, before we lose track of the
8125 original inner_mode. */
8126 new_rtx = simplify_subreg (GET_MODE (x), r,
8127 inner_mode, SUBREG_BYTE (x));
8131 SUBST (SUBREG_REG (x), r);
8136 /* We don't have to handle SIGN_EXTEND here, because even in the
8137 case of replacing something with a modeless CONST_INT, a
8138 CONST_INT is already (supposed to be) a valid sign extension for
8139 its narrower mode, which implies it's already properly
8140 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8141 story is different. */
8142 else if (code == ZERO_EXTEND)
8144 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8145 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8147 if (XEXP (x, 0) != r)
8149 /* We must simplify the zero_extend here, before we lose
8150 track of the original inner_mode. */
8151 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8156 SUBST (XEXP (x, 0), r);
8162 fmt = GET_RTX_FORMAT (code);
8163 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8166 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8167 else if (fmt[i] == 'E')
8168 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8169 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8176 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8177 assignment as a field assignment. */
8180 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8182 if (x == y || rtx_equal_p (x, y))
8185 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8188 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8189 Note that all SUBREGs of MEM are paradoxical; otherwise they
8190 would have been rewritten. */
8191 if (MEM_P (x) && GET_CODE (y) == SUBREG
8192 && MEM_P (SUBREG_REG (y))
8193 && rtx_equal_p (SUBREG_REG (y),
8194 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8197 if (MEM_P (y) && GET_CODE (x) == SUBREG
8198 && MEM_P (SUBREG_REG (x))
8199 && rtx_equal_p (SUBREG_REG (x),
8200 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8203 /* We used to see if get_last_value of X and Y were the same but that's
8204 not correct. In one direction, we'll cause the assignment to have
8205 the wrong destination and in the case, we'll import a register into this
8206 insn that might have already have been dead. So fail if none of the
8207 above cases are true. */
8211 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8212 Return that assignment if so.
8214 We only handle the most common cases. */
8217 make_field_assignment (rtx x)
8219 rtx dest = SET_DEST (x);
8220 rtx src = SET_SRC (x);
8225 unsigned HOST_WIDE_INT len;
8227 enum machine_mode mode;
8229 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8230 a clear of a one-bit field. We will have changed it to
8231 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8234 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8235 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8236 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8237 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8239 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8242 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8246 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8247 && subreg_lowpart_p (XEXP (src, 0))
8248 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8249 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8250 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8251 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8252 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8253 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8255 assign = make_extraction (VOIDmode, dest, 0,
8256 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8259 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8263 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8265 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8266 && XEXP (XEXP (src, 0), 0) == const1_rtx
8267 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8269 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8272 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8276 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8277 SRC is an AND with all bits of that field set, then we can discard
8279 if (GET_CODE (dest) == ZERO_EXTRACT
8280 && CONST_INT_P (XEXP (dest, 1))
8281 && GET_CODE (src) == AND
8282 && CONST_INT_P (XEXP (src, 1)))
8284 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8285 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8286 unsigned HOST_WIDE_INT ze_mask;
8288 if (width >= HOST_BITS_PER_WIDE_INT)
8291 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8293 /* Complete overlap. We can remove the source AND. */
8294 if ((and_mask & ze_mask) == ze_mask)
8295 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8297 /* Partial overlap. We can reduce the source AND. */
8298 if ((and_mask & ze_mask) != and_mask)
8300 mode = GET_MODE (src);
8301 src = gen_rtx_AND (mode, XEXP (src, 0),
8302 gen_int_mode (and_mask & ze_mask, mode));
8303 return gen_rtx_SET (VOIDmode, dest, src);
8307 /* The other case we handle is assignments into a constant-position
8308 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8309 a mask that has all one bits except for a group of zero bits and
8310 OTHER is known to have zeros where C1 has ones, this is such an
8311 assignment. Compute the position and length from C1. Shift OTHER
8312 to the appropriate position, force it to the required mode, and
8313 make the extraction. Check for the AND in both operands. */
8315 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8318 rhs = expand_compound_operation (XEXP (src, 0));
8319 lhs = expand_compound_operation (XEXP (src, 1));
8321 if (GET_CODE (rhs) == AND
8322 && CONST_INT_P (XEXP (rhs, 1))
8323 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8324 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8325 else if (GET_CODE (lhs) == AND
8326 && CONST_INT_P (XEXP (lhs, 1))
8327 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8328 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8332 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8333 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8334 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8335 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8338 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8342 /* The mode to use for the source is the mode of the assignment, or of
8343 what is inside a possible STRICT_LOW_PART. */
8344 mode = (GET_CODE (assign) == STRICT_LOW_PART
8345 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8347 /* Shift OTHER right POS places and make it the source, restricting it
8348 to the proper length and mode. */
8350 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8354 src = force_to_mode (src, mode,
8355 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8356 ? ~(unsigned HOST_WIDE_INT) 0
8357 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8360 /* If SRC is masked by an AND that does not make a difference in
8361 the value being stored, strip it. */
8362 if (GET_CODE (assign) == ZERO_EXTRACT
8363 && CONST_INT_P (XEXP (assign, 1))
8364 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8365 && GET_CODE (src) == AND
8366 && CONST_INT_P (XEXP (src, 1))
8367 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8368 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8369 src = XEXP (src, 0);
8371 return gen_rtx_SET (VOIDmode, assign, src);
8374 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8378 apply_distributive_law (rtx x)
8380 enum rtx_code code = GET_CODE (x);
8381 enum rtx_code inner_code;
8382 rtx lhs, rhs, other;
8385 /* Distributivity is not true for floating point as it can change the
8386 value. So we don't do it unless -funsafe-math-optimizations. */
8387 if (FLOAT_MODE_P (GET_MODE (x))
8388 && ! flag_unsafe_math_optimizations)
8391 /* The outer operation can only be one of the following: */
8392 if (code != IOR && code != AND && code != XOR
8393 && code != PLUS && code != MINUS)
8399 /* If either operand is a primitive we can't do anything, so get out
8401 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8404 lhs = expand_compound_operation (lhs);
8405 rhs = expand_compound_operation (rhs);
8406 inner_code = GET_CODE (lhs);
8407 if (inner_code != GET_CODE (rhs))
8410 /* See if the inner and outer operations distribute. */
8417 /* These all distribute except over PLUS. */
8418 if (code == PLUS || code == MINUS)
8423 if (code != PLUS && code != MINUS)
8428 /* This is also a multiply, so it distributes over everything. */
8432 /* Non-paradoxical SUBREGs distributes over all operations,
8433 provided the inner modes and byte offsets are the same, this
8434 is an extraction of a low-order part, we don't convert an fp
8435 operation to int or vice versa, this is not a vector mode,
8436 and we would not be converting a single-word operation into a
8437 multi-word operation. The latter test is not required, but
8438 it prevents generating unneeded multi-word operations. Some
8439 of the previous tests are redundant given the latter test,
8440 but are retained because they are required for correctness.
8442 We produce the result slightly differently in this case. */
8444 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8445 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8446 || ! subreg_lowpart_p (lhs)
8447 || (GET_MODE_CLASS (GET_MODE (lhs))
8448 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8449 || (GET_MODE_SIZE (GET_MODE (lhs))
8450 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8451 || VECTOR_MODE_P (GET_MODE (lhs))
8452 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8453 /* Result might need to be truncated. Don't change mode if
8454 explicit truncation is needed. */
8455 || !TRULY_NOOP_TRUNCATION
8456 (GET_MODE_BITSIZE (GET_MODE (x)),
8457 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8460 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8461 SUBREG_REG (lhs), SUBREG_REG (rhs));
8462 return gen_lowpart (GET_MODE (x), tem);
8468 /* Set LHS and RHS to the inner operands (A and B in the example
8469 above) and set OTHER to the common operand (C in the example).
8470 There is only one way to do this unless the inner operation is
8472 if (COMMUTATIVE_ARITH_P (lhs)
8473 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8474 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8475 else if (COMMUTATIVE_ARITH_P (lhs)
8476 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8477 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8478 else if (COMMUTATIVE_ARITH_P (lhs)
8479 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8480 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8481 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8482 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8486 /* Form the new inner operation, seeing if it simplifies first. */
8487 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8489 /* There is one exception to the general way of distributing:
8490 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8491 if (code == XOR && inner_code == IOR)
8494 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8497 /* We may be able to continuing distributing the result, so call
8498 ourselves recursively on the inner operation before forming the
8499 outer operation, which we return. */
8500 return simplify_gen_binary (inner_code, GET_MODE (x),
8501 apply_distributive_law (tem), other);
8504 /* See if X is of the form (* (+ A B) C), and if so convert to
8505 (+ (* A C) (* B C)) and try to simplify.
8507 Most of the time, this results in no change. However, if some of
8508 the operands are the same or inverses of each other, simplifications
8511 For example, (and (ior A B) (not B)) can occur as the result of
8512 expanding a bit field assignment. When we apply the distributive
8513 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8514 which then simplifies to (and (A (not B))).
8516 Note that no checks happen on the validity of applying the inverse
8517 distributive law. This is pointless since we can do it in the
8518 few places where this routine is called.
8520 N is the index of the term that is decomposed (the arithmetic operation,
8521 i.e. (+ A B) in the first example above). !N is the index of the term that
8522 is distributed, i.e. of C in the first example above. */
8524 distribute_and_simplify_rtx (rtx x, int n)
8526 enum machine_mode mode;
8527 enum rtx_code outer_code, inner_code;
8528 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8530 decomposed = XEXP (x, n);
8531 if (!ARITHMETIC_P (decomposed))
8534 mode = GET_MODE (x);
8535 outer_code = GET_CODE (x);
8536 distributed = XEXP (x, !n);
8538 inner_code = GET_CODE (decomposed);
8539 inner_op0 = XEXP (decomposed, 0);
8540 inner_op1 = XEXP (decomposed, 1);
8542 /* Special case (and (xor B C) (not A)), which is equivalent to
8543 (xor (ior A B) (ior A C)) */
8544 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8546 distributed = XEXP (distributed, 0);
8552 /* Distribute the second term. */
8553 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8554 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8558 /* Distribute the first term. */
8559 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8560 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8563 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8565 if (GET_CODE (tmp) != outer_code
8566 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8567 < rtx_cost (x, SET, optimize_this_for_speed_p))
8573 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8574 in MODE. Return an equivalent form, if different from (and VAROP
8575 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8578 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8579 unsigned HOST_WIDE_INT constop)
8581 unsigned HOST_WIDE_INT nonzero;
8582 unsigned HOST_WIDE_INT orig_constop;
8587 orig_constop = constop;
8588 if (GET_CODE (varop) == CLOBBER)
8591 /* Simplify VAROP knowing that we will be only looking at some of the
8594 Note by passing in CONSTOP, we guarantee that the bits not set in
8595 CONSTOP are not significant and will never be examined. We must
8596 ensure that is the case by explicitly masking out those bits
8597 before returning. */
8598 varop = force_to_mode (varop, mode, constop, 0);
8600 /* If VAROP is a CLOBBER, we will fail so return it. */
8601 if (GET_CODE (varop) == CLOBBER)
8604 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8605 to VAROP and return the new constant. */
8606 if (CONST_INT_P (varop))
8607 return gen_int_mode (INTVAL (varop) & constop, mode);
8609 /* See what bits may be nonzero in VAROP. Unlike the general case of
8610 a call to nonzero_bits, here we don't care about bits outside
8613 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8615 /* Turn off all bits in the constant that are known to already be zero.
8616 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8617 which is tested below. */
8621 /* If we don't have any bits left, return zero. */
8625 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8626 a power of two, we can replace this with an ASHIFT. */
8627 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8628 && (i = exact_log2 (constop)) >= 0)
8629 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8631 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8632 or XOR, then try to apply the distributive law. This may eliminate
8633 operations if either branch can be simplified because of the AND.
8634 It may also make some cases more complex, but those cases probably
8635 won't match a pattern either with or without this. */
8637 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8641 apply_distributive_law
8642 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8643 simplify_and_const_int (NULL_RTX,
8647 simplify_and_const_int (NULL_RTX,
8652 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8653 the AND and see if one of the operands simplifies to zero. If so, we
8654 may eliminate it. */
8656 if (GET_CODE (varop) == PLUS
8657 && exact_log2 (constop + 1) >= 0)
8661 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8662 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8663 if (o0 == const0_rtx)
8665 if (o1 == const0_rtx)
8669 /* Make a SUBREG if necessary. If we can't make it, fail. */
8670 varop = gen_lowpart (mode, varop);
8671 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8674 /* If we are only masking insignificant bits, return VAROP. */
8675 if (constop == nonzero)
8678 if (varop == orig_varop && constop == orig_constop)
8681 /* Otherwise, return an AND. */
8682 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8686 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8689 Return an equivalent form, if different from X. Otherwise, return X. If
8690 X is zero, we are to always construct the equivalent form. */
8693 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8694 unsigned HOST_WIDE_INT constop)
8696 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8701 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8702 gen_int_mode (constop, mode));
8703 if (GET_MODE (x) != mode)
8704 x = gen_lowpart (mode, x);
8708 /* Given a REG, X, compute which bits in X can be nonzero.
8709 We don't care about bits outside of those defined in MODE.
8711 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8712 a shift, AND, or zero_extract, we can do better. */
8715 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8716 const_rtx known_x ATTRIBUTE_UNUSED,
8717 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8718 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8719 unsigned HOST_WIDE_INT *nonzero)
8724 /* If X is a register whose nonzero bits value is current, use it.
8725 Otherwise, if X is a register whose value we can find, use that
8726 value. Otherwise, use the previously-computed global nonzero bits
8727 for this register. */
8729 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8730 if (rsp->last_set_value != 0
8731 && (rsp->last_set_mode == mode
8732 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8733 && GET_MODE_CLASS (mode) == MODE_INT))
8734 && ((rsp->last_set_label >= label_tick_ebb_start
8735 && rsp->last_set_label < label_tick)
8736 || (rsp->last_set_label == label_tick
8737 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8738 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8739 && REG_N_SETS (REGNO (x)) == 1
8741 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8743 *nonzero &= rsp->last_set_nonzero_bits;
8747 tem = get_last_value (x);
8751 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8752 /* If X is narrower than MODE and TEM is a non-negative
8753 constant that would appear negative in the mode of X,
8754 sign-extend it for use in reg_nonzero_bits because some
8755 machines (maybe most) will actually do the sign-extension
8756 and this is the conservative approach.
8758 ??? For 2.5, try to tighten up the MD files in this regard
8759 instead of this kludge. */
8761 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8762 && CONST_INT_P (tem)
8764 && 0 != (INTVAL (tem)
8765 & ((HOST_WIDE_INT) 1
8766 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8767 tem = GEN_INT (INTVAL (tem)
8768 | ((HOST_WIDE_INT) (-1)
8769 << GET_MODE_BITSIZE (GET_MODE (x))));
8773 else if (nonzero_sign_valid && rsp->nonzero_bits)
8775 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8777 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8778 /* We don't know anything about the upper bits. */
8779 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8786 /* Return the number of bits at the high-order end of X that are known to
8787 be equal to the sign bit. X will be used in mode MODE; if MODE is
8788 VOIDmode, X will be used in its own mode. The returned value will always
8789 be between 1 and the number of bits in MODE. */
8792 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8793 const_rtx known_x ATTRIBUTE_UNUSED,
8794 enum machine_mode known_mode
8796 unsigned int known_ret ATTRIBUTE_UNUSED,
8797 unsigned int *result)
8802 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8803 if (rsp->last_set_value != 0
8804 && rsp->last_set_mode == mode
8805 && ((rsp->last_set_label >= label_tick_ebb_start
8806 && rsp->last_set_label < label_tick)
8807 || (rsp->last_set_label == label_tick
8808 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8809 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8810 && REG_N_SETS (REGNO (x)) == 1
8812 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8814 *result = rsp->last_set_sign_bit_copies;
8818 tem = get_last_value (x);
8822 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8823 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8824 *result = rsp->sign_bit_copies;
8829 /* Return the number of "extended" bits there are in X, when interpreted
8830 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8831 unsigned quantities, this is the number of high-order zero bits.
8832 For signed quantities, this is the number of copies of the sign bit
8833 minus 1. In both case, this function returns the number of "spare"
8834 bits. For example, if two quantities for which this function returns
8835 at least 1 are added, the addition is known not to overflow.
8837 This function will always return 0 unless called during combine, which
8838 implies that it must be called from a define_split. */
8841 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8843 if (nonzero_sign_valid == 0)
8847 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8848 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8849 - floor_log2 (nonzero_bits (x, mode)))
8851 : num_sign_bit_copies (x, mode) - 1);
8854 /* This function is called from `simplify_shift_const' to merge two
8855 outer operations. Specifically, we have already found that we need
8856 to perform operation *POP0 with constant *PCONST0 at the outermost
8857 position. We would now like to also perform OP1 with constant CONST1
8858 (with *POP0 being done last).
8860 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8861 the resulting operation. *PCOMP_P is set to 1 if we would need to
8862 complement the innermost operand, otherwise it is unchanged.
8864 MODE is the mode in which the operation will be done. No bits outside
8865 the width of this mode matter. It is assumed that the width of this mode
8866 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8868 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8869 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8870 result is simply *PCONST0.
8872 If the resulting operation cannot be expressed as one operation, we
8873 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8876 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8878 enum rtx_code op0 = *pop0;
8879 HOST_WIDE_INT const0 = *pconst0;
8881 const0 &= GET_MODE_MASK (mode);
8882 const1 &= GET_MODE_MASK (mode);
8884 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8888 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8891 if (op1 == UNKNOWN || op0 == SET)
8894 else if (op0 == UNKNOWN)
8895 op0 = op1, const0 = const1;
8897 else if (op0 == op1)
8921 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8922 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8925 /* If the two constants aren't the same, we can't do anything. The
8926 remaining six cases can all be done. */
8927 else if (const0 != const1)
8935 /* (a & b) | b == b */
8937 else /* op1 == XOR */
8938 /* (a ^ b) | b == a | b */
8944 /* (a & b) ^ b == (~a) & b */
8945 op0 = AND, *pcomp_p = 1;
8946 else /* op1 == IOR */
8947 /* (a | b) ^ b == a & ~b */
8948 op0 = AND, const0 = ~const0;
8953 /* (a | b) & b == b */
8955 else /* op1 == XOR */
8956 /* (a ^ b) & b) == (~a) & b */
8963 /* Check for NO-OP cases. */
8964 const0 &= GET_MODE_MASK (mode);
8966 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8968 else if (const0 == 0 && op0 == AND)
8970 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8976 /* ??? Slightly redundant with the above mask, but not entirely.
8977 Moving this above means we'd have to sign-extend the mode mask
8978 for the final test. */
8979 if (op0 != UNKNOWN && op0 != NEG)
8980 *pconst0 = trunc_int_for_mode (const0, mode);
8985 /* A helper to simplify_shift_const_1 to determine the mode we can perform
8986 the shift in. The original shift operation CODE is performed on OP in
8987 ORIG_MODE. Return the wider mode MODE if we can perform the operation
8988 in that mode. Return ORIG_MODE otherwise. */
8990 static enum machine_mode
8991 try_widen_shift_mode (enum rtx_code code, rtx op,
8992 enum machine_mode orig_mode, enum machine_mode mode)
8994 if (orig_mode == mode)
8996 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
8998 /* In general we can't perform in wider mode for right shift and rotate. */
9002 /* We can still widen if the bits brought in from the left are identical
9003 to the sign bit of ORIG_MODE. */
9004 if (num_sign_bit_copies (op, mode)
9005 > (unsigned) (GET_MODE_BITSIZE (mode)
9006 - GET_MODE_BITSIZE (orig_mode)))
9011 /* Similarly here but with zero bits. */
9012 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9013 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9028 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9029 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9030 simplify it. Otherwise, return a simplified value.
9032 The shift is normally computed in the widest mode we find in VAROP, as
9033 long as it isn't a different number of words than RESULT_MODE. Exceptions
9034 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9037 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9038 rtx varop, int orig_count)
9040 enum rtx_code orig_code = code;
9041 rtx orig_varop = varop;
9043 enum machine_mode mode = result_mode;
9044 enum machine_mode shift_mode, tmode;
9045 unsigned int mode_words
9046 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9047 /* We form (outer_op (code varop count) (outer_const)). */
9048 enum rtx_code outer_op = UNKNOWN;
9049 HOST_WIDE_INT outer_const = 0;
9050 int complement_p = 0;
9053 /* Make sure and truncate the "natural" shift on the way in. We don't
9054 want to do this inside the loop as it makes it more difficult to
9056 if (SHIFT_COUNT_TRUNCATED)
9057 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9059 /* If we were given an invalid count, don't do anything except exactly
9060 what was requested. */
9062 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9067 /* Unless one of the branches of the `if' in this loop does a `continue',
9068 we will `break' the loop after the `if'. */
9072 /* If we have an operand of (clobber (const_int 0)), fail. */
9073 if (GET_CODE (varop) == CLOBBER)
9076 /* Convert ROTATERT to ROTATE. */
9077 if (code == ROTATERT)
9079 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9081 if (VECTOR_MODE_P (result_mode))
9082 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9084 count = bitsize - count;
9087 shift_mode = try_widen_shift_mode (code, varop, result_mode, mode);
9089 /* Handle cases where the count is greater than the size of the mode
9090 minus 1. For ASHIFT, use the size minus one as the count (this can
9091 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9092 take the count modulo the size. For other shifts, the result is
9095 Since these shifts are being produced by the compiler by combining
9096 multiple operations, each of which are defined, we know what the
9097 result is supposed to be. */
9099 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9101 if (code == ASHIFTRT)
9102 count = GET_MODE_BITSIZE (shift_mode) - 1;
9103 else if (code == ROTATE || code == ROTATERT)
9104 count %= GET_MODE_BITSIZE (shift_mode);
9107 /* We can't simply return zero because there may be an
9115 /* If we discovered we had to complement VAROP, leave. Making a NOT
9116 here would cause an infinite loop. */
9120 /* An arithmetic right shift of a quantity known to be -1 or 0
9122 if (code == ASHIFTRT
9123 && (num_sign_bit_copies (varop, shift_mode)
9124 == GET_MODE_BITSIZE (shift_mode)))
9130 /* If we are doing an arithmetic right shift and discarding all but
9131 the sign bit copies, this is equivalent to doing a shift by the
9132 bitsize minus one. Convert it into that shift because it will often
9133 allow other simplifications. */
9135 if (code == ASHIFTRT
9136 && (count + num_sign_bit_copies (varop, shift_mode)
9137 >= GET_MODE_BITSIZE (shift_mode)))
9138 count = GET_MODE_BITSIZE (shift_mode) - 1;
9140 /* We simplify the tests below and elsewhere by converting
9141 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9142 `make_compound_operation' will convert it to an ASHIFTRT for
9143 those machines (such as VAX) that don't have an LSHIFTRT. */
9144 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9146 && ((nonzero_bits (varop, shift_mode)
9147 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9151 if (((code == LSHIFTRT
9152 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9153 && !(nonzero_bits (varop, shift_mode) >> count))
9155 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9156 && !((nonzero_bits (varop, shift_mode) << count)
9157 & GET_MODE_MASK (shift_mode))))
9158 && !side_effects_p (varop))
9161 switch (GET_CODE (varop))
9167 new_rtx = expand_compound_operation (varop);
9168 if (new_rtx != varop)
9176 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9177 minus the width of a smaller mode, we can do this with a
9178 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9179 if ((code == ASHIFTRT || code == LSHIFTRT)
9180 && ! mode_dependent_address_p (XEXP (varop, 0))
9181 && ! MEM_VOLATILE_P (varop)
9182 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9183 MODE_INT, 1)) != BLKmode)
9185 new_rtx = adjust_address_nv (varop, tmode,
9186 BYTES_BIG_ENDIAN ? 0
9187 : count / BITS_PER_UNIT);
9189 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9190 : ZERO_EXTEND, mode, new_rtx);
9197 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9198 the same number of words as what we've seen so far. Then store
9199 the widest mode in MODE. */
9200 if (subreg_lowpart_p (varop)
9201 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9202 > GET_MODE_SIZE (GET_MODE (varop)))
9203 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9204 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9207 varop = SUBREG_REG (varop);
9208 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9209 mode = GET_MODE (varop);
9215 /* Some machines use MULT instead of ASHIFT because MULT
9216 is cheaper. But it is still better on those machines to
9217 merge two shifts into one. */
9218 if (CONST_INT_P (XEXP (varop, 1))
9219 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9222 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9224 GEN_INT (exact_log2 (
9225 INTVAL (XEXP (varop, 1)))));
9231 /* Similar, for when divides are cheaper. */
9232 if (CONST_INT_P (XEXP (varop, 1))
9233 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9236 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9238 GEN_INT (exact_log2 (
9239 INTVAL (XEXP (varop, 1)))));
9245 /* If we are extracting just the sign bit of an arithmetic
9246 right shift, that shift is not needed. However, the sign
9247 bit of a wider mode may be different from what would be
9248 interpreted as the sign bit in a narrower mode, so, if
9249 the result is narrower, don't discard the shift. */
9250 if (code == LSHIFTRT
9251 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9252 && (GET_MODE_BITSIZE (result_mode)
9253 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9255 varop = XEXP (varop, 0);
9259 /* ... fall through ... */
9264 /* Here we have two nested shifts. The result is usually the
9265 AND of a new shift with a mask. We compute the result below. */
9266 if (CONST_INT_P (XEXP (varop, 1))
9267 && INTVAL (XEXP (varop, 1)) >= 0
9268 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9269 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9270 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9271 && !VECTOR_MODE_P (result_mode))
9273 enum rtx_code first_code = GET_CODE (varop);
9274 unsigned int first_count = INTVAL (XEXP (varop, 1));
9275 unsigned HOST_WIDE_INT mask;
9278 /* We have one common special case. We can't do any merging if
9279 the inner code is an ASHIFTRT of a smaller mode. However, if
9280 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9281 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9282 we can convert it to
9283 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9284 This simplifies certain SIGN_EXTEND operations. */
9285 if (code == ASHIFT && first_code == ASHIFTRT
9286 && count == (GET_MODE_BITSIZE (result_mode)
9287 - GET_MODE_BITSIZE (GET_MODE (varop))))
9289 /* C3 has the low-order C1 bits zero. */
9291 mask = (GET_MODE_MASK (mode)
9292 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9294 varop = simplify_and_const_int (NULL_RTX, result_mode,
9295 XEXP (varop, 0), mask);
9296 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9298 count = first_count;
9303 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9304 than C1 high-order bits equal to the sign bit, we can convert
9305 this to either an ASHIFT or an ASHIFTRT depending on the
9308 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9310 if (code == ASHIFTRT && first_code == ASHIFT
9311 && GET_MODE (varop) == shift_mode
9312 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9315 varop = XEXP (varop, 0);
9316 count -= first_count;
9326 /* There are some cases we can't do. If CODE is ASHIFTRT,
9327 we can only do this if FIRST_CODE is also ASHIFTRT.
9329 We can't do the case when CODE is ROTATE and FIRST_CODE is
9332 If the mode of this shift is not the mode of the outer shift,
9333 we can't do this if either shift is a right shift or ROTATE.
9335 Finally, we can't do any of these if the mode is too wide
9336 unless the codes are the same.
9338 Handle the case where the shift codes are the same
9341 if (code == first_code)
9343 if (GET_MODE (varop) != result_mode
9344 && (code == ASHIFTRT || code == LSHIFTRT
9348 count += first_count;
9349 varop = XEXP (varop, 0);
9353 if (code == ASHIFTRT
9354 || (code == ROTATE && first_code == ASHIFTRT)
9355 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9356 || (GET_MODE (varop) != result_mode
9357 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9358 || first_code == ROTATE
9359 || code == ROTATE)))
9362 /* To compute the mask to apply after the shift, shift the
9363 nonzero bits of the inner shift the same way the
9364 outer shift will. */
9366 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9369 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9372 /* Give up if we can't compute an outer operation to use. */
9374 || !CONST_INT_P (mask_rtx)
9375 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9377 result_mode, &complement_p))
9380 /* If the shifts are in the same direction, we add the
9381 counts. Otherwise, we subtract them. */
9382 if ((code == ASHIFTRT || code == LSHIFTRT)
9383 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9384 count += first_count;
9386 count -= first_count;
9388 /* If COUNT is positive, the new shift is usually CODE,
9389 except for the two exceptions below, in which case it is
9390 FIRST_CODE. If the count is negative, FIRST_CODE should
9393 && ((first_code == ROTATE && code == ASHIFT)
9394 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9397 code = first_code, count = -count;
9399 varop = XEXP (varop, 0);
9403 /* If we have (A << B << C) for any shift, we can convert this to
9404 (A << C << B). This wins if A is a constant. Only try this if
9405 B is not a constant. */
9407 else if (GET_CODE (varop) == code
9408 && CONST_INT_P (XEXP (varop, 0))
9409 && !CONST_INT_P (XEXP (varop, 1)))
9411 rtx new_rtx = simplify_const_binary_operation (code, mode,
9414 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9421 if (VECTOR_MODE_P (mode))
9424 /* Make this fit the case below. */
9425 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9426 GEN_INT (GET_MODE_MASK (mode)));
9432 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9433 with C the size of VAROP - 1 and the shift is logical if
9434 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9435 we have an (le X 0) operation. If we have an arithmetic shift
9436 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9437 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9439 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9440 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9441 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9442 && (code == LSHIFTRT || code == ASHIFTRT)
9443 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9444 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9447 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9450 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9451 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9456 /* If we have (shift (logical)), move the logical to the outside
9457 to allow it to possibly combine with another logical and the
9458 shift to combine with another shift. This also canonicalizes to
9459 what a ZERO_EXTRACT looks like. Also, some machines have
9460 (and (shift)) insns. */
9462 if (CONST_INT_P (XEXP (varop, 1))
9463 /* We can't do this if we have (ashiftrt (xor)) and the
9464 constant has its sign bit set in shift_mode. */
9465 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9466 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9468 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9470 GEN_INT (count))) != 0
9471 && CONST_INT_P (new_rtx)
9472 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9473 INTVAL (new_rtx), result_mode, &complement_p))
9475 varop = XEXP (varop, 0);
9479 /* If we can't do that, try to simplify the shift in each arm of the
9480 logical expression, make a new logical expression, and apply
9481 the inverse distributive law. This also can't be done
9482 for some (ashiftrt (xor)). */
9483 if (CONST_INT_P (XEXP (varop, 1))
9484 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9485 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9488 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9489 XEXP (varop, 0), count);
9490 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9491 XEXP (varop, 1), count);
9493 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9495 varop = apply_distributive_law (varop);
9503 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9504 says that the sign bit can be tested, FOO has mode MODE, C is
9505 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9506 that may be nonzero. */
9507 if (code == LSHIFTRT
9508 && XEXP (varop, 1) == const0_rtx
9509 && GET_MODE (XEXP (varop, 0)) == result_mode
9510 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9511 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9512 && STORE_FLAG_VALUE == -1
9513 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9514 && merge_outer_ops (&outer_op, &outer_const, XOR,
9515 (HOST_WIDE_INT) 1, result_mode,
9518 varop = XEXP (varop, 0);
9525 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9526 than the number of bits in the mode is equivalent to A. */
9527 if (code == LSHIFTRT
9528 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9529 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9531 varop = XEXP (varop, 0);
9536 /* NEG commutes with ASHIFT since it is multiplication. Move the
9537 NEG outside to allow shifts to combine. */
9539 && merge_outer_ops (&outer_op, &outer_const, NEG,
9540 (HOST_WIDE_INT) 0, result_mode,
9543 varop = XEXP (varop, 0);
9549 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9550 is one less than the number of bits in the mode is
9551 equivalent to (xor A 1). */
9552 if (code == LSHIFTRT
9553 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9554 && XEXP (varop, 1) == constm1_rtx
9555 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9556 && merge_outer_ops (&outer_op, &outer_const, XOR,
9557 (HOST_WIDE_INT) 1, result_mode,
9561 varop = XEXP (varop, 0);
9565 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9566 that might be nonzero in BAR are those being shifted out and those
9567 bits are known zero in FOO, we can replace the PLUS with FOO.
9568 Similarly in the other operand order. This code occurs when
9569 we are computing the size of a variable-size array. */
9571 if ((code == ASHIFTRT || code == LSHIFTRT)
9572 && count < HOST_BITS_PER_WIDE_INT
9573 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9574 && (nonzero_bits (XEXP (varop, 1), result_mode)
9575 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9577 varop = XEXP (varop, 0);
9580 else if ((code == ASHIFTRT || code == LSHIFTRT)
9581 && count < HOST_BITS_PER_WIDE_INT
9582 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9583 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9585 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9586 & nonzero_bits (XEXP (varop, 1),
9589 varop = XEXP (varop, 1);
9593 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9595 && CONST_INT_P (XEXP (varop, 1))
9596 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9598 GEN_INT (count))) != 0
9599 && CONST_INT_P (new_rtx)
9600 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9601 INTVAL (new_rtx), result_mode, &complement_p))
9603 varop = XEXP (varop, 0);
9607 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9608 signbit', and attempt to change the PLUS to an XOR and move it to
9609 the outer operation as is done above in the AND/IOR/XOR case
9610 leg for shift(logical). See details in logical handling above
9611 for reasoning in doing so. */
9612 if (code == LSHIFTRT
9613 && CONST_INT_P (XEXP (varop, 1))
9614 && mode_signbit_p (result_mode, XEXP (varop, 1))
9615 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9617 GEN_INT (count))) != 0
9618 && CONST_INT_P (new_rtx)
9619 && merge_outer_ops (&outer_op, &outer_const, XOR,
9620 INTVAL (new_rtx), result_mode, &complement_p))
9622 varop = XEXP (varop, 0);
9629 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9630 with C the size of VAROP - 1 and the shift is logical if
9631 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9632 we have a (gt X 0) operation. If the shift is arithmetic with
9633 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9634 we have a (neg (gt X 0)) operation. */
9636 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9637 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9638 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9639 && (code == LSHIFTRT || code == ASHIFTRT)
9640 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9641 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9642 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9645 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9648 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9649 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9656 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9657 if the truncate does not affect the value. */
9658 if (code == LSHIFTRT
9659 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9660 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9661 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9662 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9663 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9665 rtx varop_inner = XEXP (varop, 0);
9668 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9669 XEXP (varop_inner, 0),
9671 (count + INTVAL (XEXP (varop_inner, 1))));
9672 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9685 shift_mode = try_widen_shift_mode (code, varop, result_mode, mode);
9687 /* We have now finished analyzing the shift. The result should be
9688 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9689 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9690 to the result of the shift. OUTER_CONST is the relevant constant,
9691 but we must turn off all bits turned off in the shift. */
9693 if (outer_op == UNKNOWN
9694 && orig_code == code && orig_count == count
9695 && varop == orig_varop
9696 && shift_mode == GET_MODE (varop))
9699 /* Make a SUBREG if necessary. If we can't make it, fail. */
9700 varop = gen_lowpart (shift_mode, varop);
9701 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9704 /* If we have an outer operation and we just made a shift, it is
9705 possible that we could have simplified the shift were it not
9706 for the outer operation. So try to do the simplification
9709 if (outer_op != UNKNOWN)
9710 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9715 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9717 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9718 turn off all the bits that the shift would have turned off. */
9719 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9720 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9721 GET_MODE_MASK (result_mode) >> orig_count);
9723 /* Do the remainder of the processing in RESULT_MODE. */
9724 x = gen_lowpart_or_truncate (result_mode, x);
9726 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9729 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9731 if (outer_op != UNKNOWN)
9733 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
9734 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9735 outer_const = trunc_int_for_mode (outer_const, result_mode);
9737 if (outer_op == AND)
9738 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9739 else if (outer_op == SET)
9741 /* This means that we have determined that the result is
9742 equivalent to a constant. This should be rare. */
9743 if (!side_effects_p (x))
9744 x = GEN_INT (outer_const);
9746 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9747 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9749 x = simplify_gen_binary (outer_op, result_mode, x,
9750 GEN_INT (outer_const));
9756 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9757 The result of the shift is RESULT_MODE. If we cannot simplify it,
9758 return X or, if it is NULL, synthesize the expression with
9759 simplify_gen_binary. Otherwise, return a simplified value.
9761 The shift is normally computed in the widest mode we find in VAROP, as
9762 long as it isn't a different number of words than RESULT_MODE. Exceptions
9763 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9766 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9767 rtx varop, int count)
9769 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9774 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9775 if (GET_MODE (x) != result_mode)
9776 x = gen_lowpart (result_mode, x);
9781 /* Like recog, but we receive the address of a pointer to a new pattern.
9782 We try to match the rtx that the pointer points to.
9783 If that fails, we may try to modify or replace the pattern,
9784 storing the replacement into the same pointer object.
9786 Modifications include deletion or addition of CLOBBERs.
9788 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9789 the CLOBBERs are placed.
9791 The value is the final insn code from the pattern ultimately matched,
9795 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9798 int insn_code_number;
9799 int num_clobbers_to_add = 0;
9802 rtx old_notes, old_pat;
9804 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9805 we use to indicate that something didn't match. If we find such a
9806 thing, force rejection. */
9807 if (GET_CODE (pat) == PARALLEL)
9808 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9809 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9810 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9813 old_pat = PATTERN (insn);
9814 old_notes = REG_NOTES (insn);
9815 PATTERN (insn) = pat;
9816 REG_NOTES (insn) = 0;
9818 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9819 if (dump_file && (dump_flags & TDF_DETAILS))
9821 if (insn_code_number < 0)
9822 fputs ("Failed to match this instruction:\n", dump_file);
9824 fputs ("Successfully matched this instruction:\n", dump_file);
9825 print_rtl_single (dump_file, pat);
9828 /* If it isn't, there is the possibility that we previously had an insn
9829 that clobbered some register as a side effect, but the combined
9830 insn doesn't need to do that. So try once more without the clobbers
9831 unless this represents an ASM insn. */
9833 if (insn_code_number < 0 && ! check_asm_operands (pat)
9834 && GET_CODE (pat) == PARALLEL)
9838 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9839 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9842 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9846 SUBST_INT (XVECLEN (pat, 0), pos);
9849 pat = XVECEXP (pat, 0, 0);
9851 PATTERN (insn) = pat;
9852 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9853 if (dump_file && (dump_flags & TDF_DETAILS))
9855 if (insn_code_number < 0)
9856 fputs ("Failed to match this instruction:\n", dump_file);
9858 fputs ("Successfully matched this instruction:\n", dump_file);
9859 print_rtl_single (dump_file, pat);
9862 PATTERN (insn) = old_pat;
9863 REG_NOTES (insn) = old_notes;
9865 /* Recognize all noop sets, these will be killed by followup pass. */
9866 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9867 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9869 /* If we had any clobbers to add, make a new pattern than contains
9870 them. Then check to make sure that all of them are dead. */
9871 if (num_clobbers_to_add)
9873 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9874 rtvec_alloc (GET_CODE (pat) == PARALLEL
9876 + num_clobbers_to_add)
9877 : num_clobbers_to_add + 1));
9879 if (GET_CODE (pat) == PARALLEL)
9880 for (i = 0; i < XVECLEN (pat, 0); i++)
9881 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9883 XVECEXP (newpat, 0, 0) = pat;
9885 add_clobbers (newpat, insn_code_number);
9887 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9888 i < XVECLEN (newpat, 0); i++)
9890 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9891 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9893 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9895 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9896 notes = alloc_reg_note (REG_UNUSED,
9897 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9906 return insn_code_number;
9909 /* Like gen_lowpart_general but for use by combine. In combine it
9910 is not possible to create any new pseudoregs. However, it is
9911 safe to create invalid memory addresses, because combine will
9912 try to recognize them and all they will do is make the combine
9915 If for some reason this cannot do its job, an rtx
9916 (clobber (const_int 0)) is returned.
9917 An insn containing that will not be recognized. */
9920 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9922 enum machine_mode imode = GET_MODE (x);
9923 unsigned int osize = GET_MODE_SIZE (omode);
9924 unsigned int isize = GET_MODE_SIZE (imode);
9930 /* Return identity if this is a CONST or symbolic reference. */
9932 && (GET_CODE (x) == CONST
9933 || GET_CODE (x) == SYMBOL_REF
9934 || GET_CODE (x) == LABEL_REF))
9937 /* We can only support MODE being wider than a word if X is a
9938 constant integer or has a mode the same size. */
9939 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9940 && ! ((imode == VOIDmode
9942 || GET_CODE (x) == CONST_DOUBLE))
9946 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9947 won't know what to do. So we will strip off the SUBREG here and
9948 process normally. */
9949 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9953 /* For use in case we fall down into the address adjustments
9954 further below, we need to adjust the known mode and size of
9955 x; imode and isize, since we just adjusted x. */
9956 imode = GET_MODE (x);
9961 isize = GET_MODE_SIZE (imode);
9964 result = gen_lowpart_common (omode, x);
9973 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9975 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9978 /* If we want to refer to something bigger than the original memref,
9979 generate a paradoxical subreg instead. That will force a reload
9980 of the original memref X. */
9982 return gen_rtx_SUBREG (omode, x, 0);
9984 if (WORDS_BIG_ENDIAN)
9985 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9987 /* Adjust the address so that the address-after-the-data is
9989 if (BYTES_BIG_ENDIAN)
9990 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9992 return adjust_address_nv (x, omode, offset);
9995 /* If X is a comparison operator, rewrite it in a new mode. This
9996 probably won't match, but may allow further simplifications. */
9997 else if (COMPARISON_P (x))
9998 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10000 /* If we couldn't simplify X any other way, just enclose it in a
10001 SUBREG. Normally, this SUBREG won't match, but some patterns may
10002 include an explicit SUBREG or we may simplify it further in combine. */
10008 offset = subreg_lowpart_offset (omode, imode);
10009 if (imode == VOIDmode)
10011 imode = int_mode_for_mode (omode);
10012 x = gen_lowpart_common (imode, x);
10016 res = simplify_gen_subreg (omode, x, imode, offset);
10022 return gen_rtx_CLOBBER (omode, const0_rtx);
10025 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10026 comparison code that will be tested.
10028 The result is a possibly different comparison code to use. *POP0 and
10029 *POP1 may be updated.
10031 It is possible that we might detect that a comparison is either always
10032 true or always false. However, we do not perform general constant
10033 folding in combine, so this knowledge isn't useful. Such tautologies
10034 should have been detected earlier. Hence we ignore all such cases. */
10036 static enum rtx_code
10037 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10043 enum machine_mode mode, tmode;
10045 /* Try a few ways of applying the same transformation to both operands. */
10048 #ifndef WORD_REGISTER_OPERATIONS
10049 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10050 so check specially. */
10051 if (code != GTU && code != GEU && code != LTU && code != LEU
10052 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10053 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10054 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10055 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10056 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10057 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10058 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10059 && CONST_INT_P (XEXP (op0, 1))
10060 && XEXP (op0, 1) == XEXP (op1, 1)
10061 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10062 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10063 && (INTVAL (XEXP (op0, 1))
10064 == (GET_MODE_BITSIZE (GET_MODE (op0))
10065 - (GET_MODE_BITSIZE
10066 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10068 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10069 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10073 /* If both operands are the same constant shift, see if we can ignore the
10074 shift. We can if the shift is a rotate or if the bits shifted out of
10075 this shift are known to be zero for both inputs and if the type of
10076 comparison is compatible with the shift. */
10077 if (GET_CODE (op0) == GET_CODE (op1)
10078 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10079 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10080 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10081 && (code != GT && code != LT && code != GE && code != LE))
10082 || (GET_CODE (op0) == ASHIFTRT
10083 && (code != GTU && code != LTU
10084 && code != GEU && code != LEU)))
10085 && CONST_INT_P (XEXP (op0, 1))
10086 && INTVAL (XEXP (op0, 1)) >= 0
10087 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10088 && XEXP (op0, 1) == XEXP (op1, 1))
10090 enum machine_mode mode = GET_MODE (op0);
10091 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10092 int shift_count = INTVAL (XEXP (op0, 1));
10094 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10095 mask &= (mask >> shift_count) << shift_count;
10096 else if (GET_CODE (op0) == ASHIFT)
10097 mask = (mask & (mask << shift_count)) >> shift_count;
10099 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10100 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10101 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10106 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10107 SUBREGs are of the same mode, and, in both cases, the AND would
10108 be redundant if the comparison was done in the narrower mode,
10109 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10110 and the operand's possibly nonzero bits are 0xffffff01; in that case
10111 if we only care about QImode, we don't need the AND). This case
10112 occurs if the output mode of an scc insn is not SImode and
10113 STORE_FLAG_VALUE == 1 (e.g., the 386).
10115 Similarly, check for a case where the AND's are ZERO_EXTEND
10116 operations from some narrower mode even though a SUBREG is not
10119 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10120 && CONST_INT_P (XEXP (op0, 1))
10121 && CONST_INT_P (XEXP (op1, 1)))
10123 rtx inner_op0 = XEXP (op0, 0);
10124 rtx inner_op1 = XEXP (op1, 0);
10125 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10126 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10129 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10130 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10131 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10132 && (GET_MODE (SUBREG_REG (inner_op0))
10133 == GET_MODE (SUBREG_REG (inner_op1)))
10134 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10135 <= HOST_BITS_PER_WIDE_INT)
10136 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10137 GET_MODE (SUBREG_REG (inner_op0)))))
10138 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10139 GET_MODE (SUBREG_REG (inner_op1))))))
10141 op0 = SUBREG_REG (inner_op0);
10142 op1 = SUBREG_REG (inner_op1);
10144 /* The resulting comparison is always unsigned since we masked
10145 off the original sign bit. */
10146 code = unsigned_condition (code);
10152 for (tmode = GET_CLASS_NARROWEST_MODE
10153 (GET_MODE_CLASS (GET_MODE (op0)));
10154 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10155 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10157 op0 = gen_lowpart (tmode, inner_op0);
10158 op1 = gen_lowpart (tmode, inner_op1);
10159 code = unsigned_condition (code);
10168 /* If both operands are NOT, we can strip off the outer operation
10169 and adjust the comparison code for swapped operands; similarly for
10170 NEG, except that this must be an equality comparison. */
10171 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10172 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10173 && (code == EQ || code == NE)))
10174 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10180 /* If the first operand is a constant, swap the operands and adjust the
10181 comparison code appropriately, but don't do this if the second operand
10182 is already a constant integer. */
10183 if (swap_commutative_operands_p (op0, op1))
10185 tem = op0, op0 = op1, op1 = tem;
10186 code = swap_condition (code);
10189 /* We now enter a loop during which we will try to simplify the comparison.
10190 For the most part, we only are concerned with comparisons with zero,
10191 but some things may really be comparisons with zero but not start
10192 out looking that way. */
10194 while (CONST_INT_P (op1))
10196 enum machine_mode mode = GET_MODE (op0);
10197 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10198 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10199 int equality_comparison_p;
10200 int sign_bit_comparison_p;
10201 int unsigned_comparison_p;
10202 HOST_WIDE_INT const_op;
10204 /* We only want to handle integral modes. This catches VOIDmode,
10205 CCmode, and the floating-point modes. An exception is that we
10206 can handle VOIDmode if OP0 is a COMPARE or a comparison
10209 if (GET_MODE_CLASS (mode) != MODE_INT
10210 && ! (mode == VOIDmode
10211 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10214 /* Get the constant we are comparing against and turn off all bits
10215 not on in our mode. */
10216 const_op = INTVAL (op1);
10217 if (mode != VOIDmode)
10218 const_op = trunc_int_for_mode (const_op, mode);
10219 op1 = GEN_INT (const_op);
10221 /* If we are comparing against a constant power of two and the value
10222 being compared can only have that single bit nonzero (e.g., it was
10223 `and'ed with that bit), we can replace this with a comparison
10226 && (code == EQ || code == NE || code == GE || code == GEU
10227 || code == LT || code == LTU)
10228 && mode_width <= HOST_BITS_PER_WIDE_INT
10229 && exact_log2 (const_op) >= 0
10230 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10232 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10233 op1 = const0_rtx, const_op = 0;
10236 /* Similarly, if we are comparing a value known to be either -1 or
10237 0 with -1, change it to the opposite comparison against zero. */
10240 && (code == EQ || code == NE || code == GT || code == LE
10241 || code == GEU || code == LTU)
10242 && num_sign_bit_copies (op0, mode) == mode_width)
10244 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10245 op1 = const0_rtx, const_op = 0;
10248 /* Do some canonicalizations based on the comparison code. We prefer
10249 comparisons against zero and then prefer equality comparisons.
10250 If we can reduce the size of a constant, we will do that too. */
10255 /* < C is equivalent to <= (C - 1) */
10259 op1 = GEN_INT (const_op);
10261 /* ... fall through to LE case below. */
10267 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10271 op1 = GEN_INT (const_op);
10275 /* If we are doing a <= 0 comparison on a value known to have
10276 a zero sign bit, we can replace this with == 0. */
10277 else if (const_op == 0
10278 && mode_width <= HOST_BITS_PER_WIDE_INT
10279 && (nonzero_bits (op0, mode)
10280 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10285 /* >= C is equivalent to > (C - 1). */
10289 op1 = GEN_INT (const_op);
10291 /* ... fall through to GT below. */
10297 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10301 op1 = GEN_INT (const_op);
10305 /* If we are doing a > 0 comparison on a value known to have
10306 a zero sign bit, we can replace this with != 0. */
10307 else if (const_op == 0
10308 && mode_width <= HOST_BITS_PER_WIDE_INT
10309 && (nonzero_bits (op0, mode)
10310 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10315 /* < C is equivalent to <= (C - 1). */
10319 op1 = GEN_INT (const_op);
10321 /* ... fall through ... */
10324 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10325 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10326 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10328 const_op = 0, op1 = const0_rtx;
10336 /* unsigned <= 0 is equivalent to == 0 */
10340 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10341 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10342 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10344 const_op = 0, op1 = const0_rtx;
10350 /* >= C is equivalent to > (C - 1). */
10354 op1 = GEN_INT (const_op);
10356 /* ... fall through ... */
10359 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10360 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10361 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10363 const_op = 0, op1 = const0_rtx;
10371 /* unsigned > 0 is equivalent to != 0 */
10375 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10376 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10377 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10379 const_op = 0, op1 = const0_rtx;
10388 /* Compute some predicates to simplify code below. */
10390 equality_comparison_p = (code == EQ || code == NE);
10391 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10392 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10395 /* If this is a sign bit comparison and we can do arithmetic in
10396 MODE, say that we will only be needing the sign bit of OP0. */
10397 if (sign_bit_comparison_p
10398 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10399 op0 = force_to_mode (op0, mode,
10401 << (GET_MODE_BITSIZE (mode) - 1)),
10404 /* Now try cases based on the opcode of OP0. If none of the cases
10405 does a "continue", we exit this loop immediately after the
10408 switch (GET_CODE (op0))
10411 /* If we are extracting a single bit from a variable position in
10412 a constant that has only a single bit set and are comparing it
10413 with zero, we can convert this into an equality comparison
10414 between the position and the location of the single bit. */
10415 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10416 have already reduced the shift count modulo the word size. */
10417 if (!SHIFT_COUNT_TRUNCATED
10418 && CONST_INT_P (XEXP (op0, 0))
10419 && XEXP (op0, 1) == const1_rtx
10420 && equality_comparison_p && const_op == 0
10421 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10423 if (BITS_BIG_ENDIAN)
10425 enum machine_mode new_mode
10426 = mode_for_extraction (EP_extzv, 1);
10427 if (new_mode == MAX_MACHINE_MODE)
10428 i = BITS_PER_WORD - 1 - i;
10432 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10436 op0 = XEXP (op0, 2);
10440 /* Result is nonzero iff shift count is equal to I. */
10441 code = reverse_condition (code);
10445 /* ... fall through ... */
10448 tem = expand_compound_operation (op0);
10457 /* If testing for equality, we can take the NOT of the constant. */
10458 if (equality_comparison_p
10459 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10461 op0 = XEXP (op0, 0);
10466 /* If just looking at the sign bit, reverse the sense of the
10468 if (sign_bit_comparison_p)
10470 op0 = XEXP (op0, 0);
10471 code = (code == GE ? LT : GE);
10477 /* If testing for equality, we can take the NEG of the constant. */
10478 if (equality_comparison_p
10479 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10481 op0 = XEXP (op0, 0);
10486 /* The remaining cases only apply to comparisons with zero. */
10490 /* When X is ABS or is known positive,
10491 (neg X) is < 0 if and only if X != 0. */
10493 if (sign_bit_comparison_p
10494 && (GET_CODE (XEXP (op0, 0)) == ABS
10495 || (mode_width <= HOST_BITS_PER_WIDE_INT
10496 && (nonzero_bits (XEXP (op0, 0), mode)
10497 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10499 op0 = XEXP (op0, 0);
10500 code = (code == LT ? NE : EQ);
10504 /* If we have NEG of something whose two high-order bits are the
10505 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10506 if (num_sign_bit_copies (op0, mode) >= 2)
10508 op0 = XEXP (op0, 0);
10509 code = swap_condition (code);
10515 /* If we are testing equality and our count is a constant, we
10516 can perform the inverse operation on our RHS. */
10517 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10518 && (tem = simplify_binary_operation (ROTATERT, mode,
10519 op1, XEXP (op0, 1))) != 0)
10521 op0 = XEXP (op0, 0);
10526 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10527 a particular bit. Convert it to an AND of a constant of that
10528 bit. This will be converted into a ZERO_EXTRACT. */
10529 if (const_op == 0 && sign_bit_comparison_p
10530 && CONST_INT_P (XEXP (op0, 1))
10531 && mode_width <= HOST_BITS_PER_WIDE_INT)
10533 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10536 - INTVAL (XEXP (op0, 1)))));
10537 code = (code == LT ? NE : EQ);
10541 /* Fall through. */
10544 /* ABS is ignorable inside an equality comparison with zero. */
10545 if (const_op == 0 && equality_comparison_p)
10547 op0 = XEXP (op0, 0);
10553 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10554 (compare FOO CONST) if CONST fits in FOO's mode and we
10555 are either testing inequality or have an unsigned
10556 comparison with ZERO_EXTEND or a signed comparison with
10557 SIGN_EXTEND. But don't do it if we don't have a compare
10558 insn of the given mode, since we'd have to revert it
10559 later on, and then we wouldn't know whether to sign- or
10561 mode = GET_MODE (XEXP (op0, 0));
10562 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10563 && ! unsigned_comparison_p
10564 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10565 && ((unsigned HOST_WIDE_INT) const_op
10566 < (((unsigned HOST_WIDE_INT) 1
10567 << (GET_MODE_BITSIZE (mode) - 1))))
10568 && have_insn_for (COMPARE, mode))
10570 op0 = XEXP (op0, 0);
10576 /* Check for the case where we are comparing A - C1 with C2, that is
10578 (subreg:MODE (plus (A) (-C1))) op (C2)
10580 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10581 comparison in the wider mode. One of the following two conditions
10582 must be true in order for this to be valid:
10584 1. The mode extension results in the same bit pattern being added
10585 on both sides and the comparison is equality or unsigned. As
10586 C2 has been truncated to fit in MODE, the pattern can only be
10589 2. The mode extension results in the sign bit being copied on
10592 The difficulty here is that we have predicates for A but not for
10593 (A - C1) so we need to check that C1 is within proper bounds so
10594 as to perturbate A as little as possible. */
10596 if (mode_width <= HOST_BITS_PER_WIDE_INT
10597 && subreg_lowpart_p (op0)
10598 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10599 && GET_CODE (SUBREG_REG (op0)) == PLUS
10600 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10602 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10603 rtx a = XEXP (SUBREG_REG (op0), 0);
10604 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10607 && (unsigned HOST_WIDE_INT) c1
10608 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10609 && (equality_comparison_p || unsigned_comparison_p)
10610 /* (A - C1) zero-extends if it is positive and sign-extends
10611 if it is negative, C2 both zero- and sign-extends. */
10612 && ((0 == (nonzero_bits (a, inner_mode)
10613 & ~GET_MODE_MASK (mode))
10615 /* (A - C1) sign-extends if it is positive and 1-extends
10616 if it is negative, C2 both sign- and 1-extends. */
10617 || (num_sign_bit_copies (a, inner_mode)
10618 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10621 || ((unsigned HOST_WIDE_INT) c1
10622 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10623 /* (A - C1) always sign-extends, like C2. */
10624 && num_sign_bit_copies (a, inner_mode)
10625 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10626 - (mode_width - 1))))
10628 op0 = SUBREG_REG (op0);
10633 /* If the inner mode is narrower and we are extracting the low part,
10634 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10635 if (subreg_lowpart_p (op0)
10636 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10637 /* Fall through */ ;
10641 /* ... fall through ... */
10644 mode = GET_MODE (XEXP (op0, 0));
10645 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10646 && (unsigned_comparison_p || equality_comparison_p)
10647 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10648 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10649 && have_insn_for (COMPARE, mode))
10651 op0 = XEXP (op0, 0);
10657 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10658 this for equality comparisons due to pathological cases involving
10660 if (equality_comparison_p
10661 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10662 op1, XEXP (op0, 1))))
10664 op0 = XEXP (op0, 0);
10669 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10670 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10671 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10673 op0 = XEXP (XEXP (op0, 0), 0);
10674 code = (code == LT ? EQ : NE);
10680 /* We used to optimize signed comparisons against zero, but that
10681 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10682 arrive here as equality comparisons, or (GEU, LTU) are
10683 optimized away. No need to special-case them. */
10685 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10686 (eq B (minus A C)), whichever simplifies. We can only do
10687 this for equality comparisons due to pathological cases involving
10689 if (equality_comparison_p
10690 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10691 XEXP (op0, 1), op1)))
10693 op0 = XEXP (op0, 0);
10698 if (equality_comparison_p
10699 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10700 XEXP (op0, 0), op1)))
10702 op0 = XEXP (op0, 1);
10707 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10708 of bits in X minus 1, is one iff X > 0. */
10709 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10710 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10711 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10713 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10715 op0 = XEXP (op0, 1);
10716 code = (code == GE ? LE : GT);
10722 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10723 if C is zero or B is a constant. */
10724 if (equality_comparison_p
10725 && 0 != (tem = simplify_binary_operation (XOR, mode,
10726 XEXP (op0, 1), op1)))
10728 op0 = XEXP (op0, 0);
10735 case UNEQ: case LTGT:
10736 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10737 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10738 case UNORDERED: case ORDERED:
10739 /* We can't do anything if OP0 is a condition code value, rather
10740 than an actual data value. */
10742 || CC0_P (XEXP (op0, 0))
10743 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10746 /* Get the two operands being compared. */
10747 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10748 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10750 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10752 /* Check for the cases where we simply want the result of the
10753 earlier test or the opposite of that result. */
10754 if (code == NE || code == EQ
10755 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10756 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10757 && (STORE_FLAG_VALUE
10758 & (((HOST_WIDE_INT) 1
10759 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10760 && (code == LT || code == GE)))
10762 enum rtx_code new_code;
10763 if (code == LT || code == NE)
10764 new_code = GET_CODE (op0);
10766 new_code = reversed_comparison_code (op0, NULL);
10768 if (new_code != UNKNOWN)
10779 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10781 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10782 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10783 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10785 op0 = XEXP (op0, 1);
10786 code = (code == GE ? GT : LE);
10792 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10793 will be converted to a ZERO_EXTRACT later. */
10794 if (const_op == 0 && equality_comparison_p
10795 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10796 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10798 op0 = simplify_and_const_int
10799 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10801 XEXP (XEXP (op0, 0), 1)),
10802 (HOST_WIDE_INT) 1);
10806 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10807 zero and X is a comparison and C1 and C2 describe only bits set
10808 in STORE_FLAG_VALUE, we can compare with X. */
10809 if (const_op == 0 && equality_comparison_p
10810 && mode_width <= HOST_BITS_PER_WIDE_INT
10811 && CONST_INT_P (XEXP (op0, 1))
10812 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10813 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10814 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10815 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10817 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10818 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10819 if ((~STORE_FLAG_VALUE & mask) == 0
10820 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10821 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10822 && COMPARISON_P (tem))))
10824 op0 = XEXP (XEXP (op0, 0), 0);
10829 /* If we are doing an equality comparison of an AND of a bit equal
10830 to the sign bit, replace this with a LT or GE comparison of
10831 the underlying value. */
10832 if (equality_comparison_p
10834 && CONST_INT_P (XEXP (op0, 1))
10835 && mode_width <= HOST_BITS_PER_WIDE_INT
10836 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10837 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10839 op0 = XEXP (op0, 0);
10840 code = (code == EQ ? GE : LT);
10844 /* If this AND operation is really a ZERO_EXTEND from a narrower
10845 mode, the constant fits within that mode, and this is either an
10846 equality or unsigned comparison, try to do this comparison in
10851 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10852 -> (ne:DI (reg:SI 4) (const_int 0))
10854 unless TRULY_NOOP_TRUNCATION allows it or the register is
10855 known to hold a value of the required mode the
10856 transformation is invalid. */
10857 if ((equality_comparison_p || unsigned_comparison_p)
10858 && CONST_INT_P (XEXP (op0, 1))
10859 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10860 & GET_MODE_MASK (mode))
10862 && const_op >> i == 0
10863 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10864 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10865 GET_MODE_BITSIZE (GET_MODE (op0)))
10866 || (REG_P (XEXP (op0, 0))
10867 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10869 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10873 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10874 fits in both M1 and M2 and the SUBREG is either paradoxical
10875 or represents the low part, permute the SUBREG and the AND
10877 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10879 unsigned HOST_WIDE_INT c1;
10880 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10881 /* Require an integral mode, to avoid creating something like
10883 if (SCALAR_INT_MODE_P (tmode)
10884 /* It is unsafe to commute the AND into the SUBREG if the
10885 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10886 not defined. As originally written the upper bits
10887 have a defined value due to the AND operation.
10888 However, if we commute the AND inside the SUBREG then
10889 they no longer have defined values and the meaning of
10890 the code has been changed. */
10892 #ifdef WORD_REGISTER_OPERATIONS
10893 || (mode_width > GET_MODE_BITSIZE (tmode)
10894 && mode_width <= BITS_PER_WORD)
10896 || (mode_width <= GET_MODE_BITSIZE (tmode)
10897 && subreg_lowpart_p (XEXP (op0, 0))))
10898 && CONST_INT_P (XEXP (op0, 1))
10899 && mode_width <= HOST_BITS_PER_WIDE_INT
10900 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10901 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10902 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10904 && c1 != GET_MODE_MASK (tmode))
10906 op0 = simplify_gen_binary (AND, tmode,
10907 SUBREG_REG (XEXP (op0, 0)),
10908 gen_int_mode (c1, tmode));
10909 op0 = gen_lowpart (mode, op0);
10914 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10915 if (const_op == 0 && equality_comparison_p
10916 && XEXP (op0, 1) == const1_rtx
10917 && GET_CODE (XEXP (op0, 0)) == NOT)
10919 op0 = simplify_and_const_int
10920 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10921 code = (code == NE ? EQ : NE);
10925 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10926 (eq (and (lshiftrt X) 1) 0).
10927 Also handle the case where (not X) is expressed using xor. */
10928 if (const_op == 0 && equality_comparison_p
10929 && XEXP (op0, 1) == const1_rtx
10930 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10932 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10933 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10935 if (GET_CODE (shift_op) == NOT
10936 || (GET_CODE (shift_op) == XOR
10937 && CONST_INT_P (XEXP (shift_op, 1))
10938 && CONST_INT_P (shift_count)
10939 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10940 && (INTVAL (XEXP (shift_op, 1))
10941 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10943 op0 = simplify_and_const_int
10945 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10946 (HOST_WIDE_INT) 1);
10947 code = (code == NE ? EQ : NE);
10954 /* If we have (compare (ashift FOO N) (const_int C)) and
10955 the high order N bits of FOO (N+1 if an inequality comparison)
10956 are known to be zero, we can do this by comparing FOO with C
10957 shifted right N bits so long as the low-order N bits of C are
10959 if (CONST_INT_P (XEXP (op0, 1))
10960 && INTVAL (XEXP (op0, 1)) >= 0
10961 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10962 < HOST_BITS_PER_WIDE_INT)
10964 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10965 && mode_width <= HOST_BITS_PER_WIDE_INT
10966 && (nonzero_bits (XEXP (op0, 0), mode)
10967 & ~(mask >> (INTVAL (XEXP (op0, 1))
10968 + ! equality_comparison_p))) == 0)
10970 /* We must perform a logical shift, not an arithmetic one,
10971 as we want the top N bits of C to be zero. */
10972 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10974 temp >>= INTVAL (XEXP (op0, 1));
10975 op1 = gen_int_mode (temp, mode);
10976 op0 = XEXP (op0, 0);
10980 /* If we are doing a sign bit comparison, it means we are testing
10981 a particular bit. Convert it to the appropriate AND. */
10982 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
10983 && mode_width <= HOST_BITS_PER_WIDE_INT)
10985 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10988 - INTVAL (XEXP (op0, 1)))));
10989 code = (code == LT ? NE : EQ);
10993 /* If this an equality comparison with zero and we are shifting
10994 the low bit to the sign bit, we can convert this to an AND of the
10996 if (const_op == 0 && equality_comparison_p
10997 && CONST_INT_P (XEXP (op0, 1))
10998 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11001 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11002 (HOST_WIDE_INT) 1);
11008 /* If this is an equality comparison with zero, we can do this
11009 as a logical shift, which might be much simpler. */
11010 if (equality_comparison_p && const_op == 0
11011 && CONST_INT_P (XEXP (op0, 1)))
11013 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11015 INTVAL (XEXP (op0, 1)));
11019 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11020 do the comparison in a narrower mode. */
11021 if (! unsigned_comparison_p
11022 && CONST_INT_P (XEXP (op0, 1))
11023 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11024 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11025 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11026 MODE_INT, 1)) != BLKmode
11027 && (((unsigned HOST_WIDE_INT) const_op
11028 + (GET_MODE_MASK (tmode) >> 1) + 1)
11029 <= GET_MODE_MASK (tmode)))
11031 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11035 /* Likewise if OP0 is a PLUS of a sign extension with a
11036 constant, which is usually represented with the PLUS
11037 between the shifts. */
11038 if (! unsigned_comparison_p
11039 && CONST_INT_P (XEXP (op0, 1))
11040 && GET_CODE (XEXP (op0, 0)) == PLUS
11041 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11042 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11043 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11044 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11045 MODE_INT, 1)) != BLKmode
11046 && (((unsigned HOST_WIDE_INT) const_op
11047 + (GET_MODE_MASK (tmode) >> 1) + 1)
11048 <= GET_MODE_MASK (tmode)))
11050 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11051 rtx add_const = XEXP (XEXP (op0, 0), 1);
11052 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11053 add_const, XEXP (op0, 1));
11055 op0 = simplify_gen_binary (PLUS, tmode,
11056 gen_lowpart (tmode, inner),
11061 /* ... fall through ... */
11063 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11064 the low order N bits of FOO are known to be zero, we can do this
11065 by comparing FOO with C shifted left N bits so long as no
11066 overflow occurs. */
11067 if (CONST_INT_P (XEXP (op0, 1))
11068 && INTVAL (XEXP (op0, 1)) >= 0
11069 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11070 && mode_width <= HOST_BITS_PER_WIDE_INT
11071 && (nonzero_bits (XEXP (op0, 0), mode)
11072 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11073 && (((unsigned HOST_WIDE_INT) const_op
11074 + (GET_CODE (op0) != LSHIFTRT
11075 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11078 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11080 /* If the shift was logical, then we must make the condition
11082 if (GET_CODE (op0) == LSHIFTRT)
11083 code = unsigned_condition (code);
11085 const_op <<= INTVAL (XEXP (op0, 1));
11086 op1 = GEN_INT (const_op);
11087 op0 = XEXP (op0, 0);
11091 /* If we are using this shift to extract just the sign bit, we
11092 can replace this with an LT or GE comparison. */
11094 && (equality_comparison_p || sign_bit_comparison_p)
11095 && CONST_INT_P (XEXP (op0, 1))
11096 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11099 op0 = XEXP (op0, 0);
11100 code = (code == NE || code == GT ? LT : GE);
11112 /* Now make any compound operations involved in this comparison. Then,
11113 check for an outmost SUBREG on OP0 that is not doing anything or is
11114 paradoxical. The latter transformation must only be performed when
11115 it is known that the "extra" bits will be the same in op0 and op1 or
11116 that they don't matter. There are three cases to consider:
11118 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11119 care bits and we can assume they have any convenient value. So
11120 making the transformation is safe.
11122 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11123 In this case the upper bits of op0 are undefined. We should not make
11124 the simplification in that case as we do not know the contents of
11127 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11128 UNKNOWN. In that case we know those bits are zeros or ones. We must
11129 also be sure that they are the same as the upper bits of op1.
11131 We can never remove a SUBREG for a non-equality comparison because
11132 the sign bit is in a different place in the underlying object. */
11134 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11135 op1 = make_compound_operation (op1, SET);
11137 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11138 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11139 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11140 && (code == NE || code == EQ))
11142 if (GET_MODE_SIZE (GET_MODE (op0))
11143 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11145 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11147 if (REG_P (SUBREG_REG (op0)))
11149 op0 = SUBREG_REG (op0);
11150 op1 = gen_lowpart (GET_MODE (op0), op1);
11153 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11154 <= HOST_BITS_PER_WIDE_INT)
11155 && (nonzero_bits (SUBREG_REG (op0),
11156 GET_MODE (SUBREG_REG (op0)))
11157 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11159 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11161 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11162 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11163 op0 = SUBREG_REG (op0), op1 = tem;
11167 /* We now do the opposite procedure: Some machines don't have compare
11168 insns in all modes. If OP0's mode is an integer mode smaller than a
11169 word and we can't do a compare in that mode, see if there is a larger
11170 mode for which we can do the compare. There are a number of cases in
11171 which we can use the wider mode. */
11173 mode = GET_MODE (op0);
11174 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11175 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11176 && ! have_insn_for (COMPARE, mode))
11177 for (tmode = GET_MODE_WIDER_MODE (mode);
11179 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11180 tmode = GET_MODE_WIDER_MODE (tmode))
11181 if (have_insn_for (COMPARE, tmode))
11185 /* If the only nonzero bits in OP0 and OP1 are those in the
11186 narrower mode and this is an equality or unsigned comparison,
11187 we can use the wider mode. Similarly for sign-extended
11188 values, in which case it is true for all comparisons. */
11189 zero_extended = ((code == EQ || code == NE
11190 || code == GEU || code == GTU
11191 || code == LEU || code == LTU)
11192 && (nonzero_bits (op0, tmode)
11193 & ~GET_MODE_MASK (mode)) == 0
11194 && ((CONST_INT_P (op1)
11195 || (nonzero_bits (op1, tmode)
11196 & ~GET_MODE_MASK (mode)) == 0)));
11199 || ((num_sign_bit_copies (op0, tmode)
11200 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11201 - GET_MODE_BITSIZE (mode)))
11202 && (num_sign_bit_copies (op1, tmode)
11203 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11204 - GET_MODE_BITSIZE (mode)))))
11206 /* If OP0 is an AND and we don't have an AND in MODE either,
11207 make a new AND in the proper mode. */
11208 if (GET_CODE (op0) == AND
11209 && !have_insn_for (AND, mode))
11210 op0 = simplify_gen_binary (AND, tmode,
11211 gen_lowpart (tmode,
11213 gen_lowpart (tmode,
11216 op0 = gen_lowpart (tmode, op0);
11217 if (zero_extended && CONST_INT_P (op1))
11218 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11219 op1 = gen_lowpart (tmode, op1);
11223 /* If this is a test for negative, we can make an explicit
11224 test of the sign bit. */
11226 if (op1 == const0_rtx && (code == LT || code == GE)
11227 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11229 op0 = simplify_gen_binary (AND, tmode,
11230 gen_lowpart (tmode, op0),
11231 GEN_INT ((HOST_WIDE_INT) 1
11232 << (GET_MODE_BITSIZE (mode)
11234 code = (code == LT) ? NE : EQ;
11239 #ifdef CANONICALIZE_COMPARISON
11240 /* If this machine only supports a subset of valid comparisons, see if we
11241 can convert an unsupported one into a supported one. */
11242 CANONICALIZE_COMPARISON (code, op0, op1);
11251 /* Utility function for record_value_for_reg. Count number of
11256 enum rtx_code code = GET_CODE (x);
11260 if (GET_RTX_CLASS (code) == '2'
11261 || GET_RTX_CLASS (code) == 'c')
11263 rtx x0 = XEXP (x, 0);
11264 rtx x1 = XEXP (x, 1);
11267 return 1 + 2 * count_rtxs (x0);
11269 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11270 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11271 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11272 return 2 + 2 * count_rtxs (x0)
11273 + count_rtxs (x == XEXP (x1, 0)
11274 ? XEXP (x1, 1) : XEXP (x1, 0));
11276 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11277 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11278 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11279 return 2 + 2 * count_rtxs (x1)
11280 + count_rtxs (x == XEXP (x0, 0)
11281 ? XEXP (x0, 1) : XEXP (x0, 0));
11284 fmt = GET_RTX_FORMAT (code);
11285 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11287 ret += count_rtxs (XEXP (x, i));
11288 else if (fmt[i] == 'E')
11289 for (j = 0; j < XVECLEN (x, i); j++)
11290 ret += count_rtxs (XVECEXP (x, i, j));
11295 /* Utility function for following routine. Called when X is part of a value
11296 being stored into last_set_value. Sets last_set_table_tick
11297 for each register mentioned. Similar to mention_regs in cse.c */
11300 update_table_tick (rtx x)
11302 enum rtx_code code = GET_CODE (x);
11303 const char *fmt = GET_RTX_FORMAT (code);
11308 unsigned int regno = REGNO (x);
11309 unsigned int endregno = END_REGNO (x);
11312 for (r = regno; r < endregno; r++)
11314 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11315 rsp->last_set_table_tick = label_tick;
11321 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11324 /* Check for identical subexpressions. If x contains
11325 identical subexpression we only have to traverse one of
11327 if (i == 0 && ARITHMETIC_P (x))
11329 /* Note that at this point x1 has already been
11331 rtx x0 = XEXP (x, 0);
11332 rtx x1 = XEXP (x, 1);
11334 /* If x0 and x1 are identical then there is no need to
11339 /* If x0 is identical to a subexpression of x1 then while
11340 processing x1, x0 has already been processed. Thus we
11341 are done with x. */
11342 if (ARITHMETIC_P (x1)
11343 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11346 /* If x1 is identical to a subexpression of x0 then we
11347 still have to process the rest of x0. */
11348 if (ARITHMETIC_P (x0)
11349 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11351 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11356 update_table_tick (XEXP (x, i));
11358 else if (fmt[i] == 'E')
11359 for (j = 0; j < XVECLEN (x, i); j++)
11360 update_table_tick (XVECEXP (x, i, j));
11363 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11364 are saying that the register is clobbered and we no longer know its
11365 value. If INSN is zero, don't update reg_stat[].last_set; this is
11366 only permitted with VALUE also zero and is used to invalidate the
11370 record_value_for_reg (rtx reg, rtx insn, rtx value)
11372 unsigned int regno = REGNO (reg);
11373 unsigned int endregno = END_REGNO (reg);
11375 reg_stat_type *rsp;
11377 /* If VALUE contains REG and we have a previous value for REG, substitute
11378 the previous value. */
11379 if (value && insn && reg_overlap_mentioned_p (reg, value))
11383 /* Set things up so get_last_value is allowed to see anything set up to
11385 subst_low_luid = DF_INSN_LUID (insn);
11386 tem = get_last_value (reg);
11388 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11389 it isn't going to be useful and will take a lot of time to process,
11390 so just use the CLOBBER. */
11394 if (ARITHMETIC_P (tem)
11395 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11396 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11397 tem = XEXP (tem, 0);
11398 else if (count_occurrences (value, reg, 1) >= 2)
11400 /* If there are two or more occurrences of REG in VALUE,
11401 prevent the value from growing too much. */
11402 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11403 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11406 value = replace_rtx (copy_rtx (value), reg, tem);
11410 /* For each register modified, show we don't know its value, that
11411 we don't know about its bitwise content, that its value has been
11412 updated, and that we don't know the location of the death of the
11414 for (i = regno; i < endregno; i++)
11416 rsp = VEC_index (reg_stat_type, reg_stat, i);
11419 rsp->last_set = insn;
11421 rsp->last_set_value = 0;
11422 rsp->last_set_mode = VOIDmode;
11423 rsp->last_set_nonzero_bits = 0;
11424 rsp->last_set_sign_bit_copies = 0;
11425 rsp->last_death = 0;
11426 rsp->truncated_to_mode = VOIDmode;
11429 /* Mark registers that are being referenced in this value. */
11431 update_table_tick (value);
11433 /* Now update the status of each register being set.
11434 If someone is using this register in this block, set this register
11435 to invalid since we will get confused between the two lives in this
11436 basic block. This makes using this register always invalid. In cse, we
11437 scan the table to invalidate all entries using this register, but this
11438 is too much work for us. */
11440 for (i = regno; i < endregno; i++)
11442 rsp = VEC_index (reg_stat_type, reg_stat, i);
11443 rsp->last_set_label = label_tick;
11445 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11446 rsp->last_set_invalid = 1;
11448 rsp->last_set_invalid = 0;
11451 /* The value being assigned might refer to X (like in "x++;"). In that
11452 case, we must replace it with (clobber (const_int 0)) to prevent
11454 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11455 if (value && ! get_last_value_validate (&value, insn,
11456 rsp->last_set_label, 0))
11458 value = copy_rtx (value);
11459 if (! get_last_value_validate (&value, insn,
11460 rsp->last_set_label, 1))
11464 /* For the main register being modified, update the value, the mode, the
11465 nonzero bits, and the number of sign bit copies. */
11467 rsp->last_set_value = value;
11471 enum machine_mode mode = GET_MODE (reg);
11472 subst_low_luid = DF_INSN_LUID (insn);
11473 rsp->last_set_mode = mode;
11474 if (GET_MODE_CLASS (mode) == MODE_INT
11475 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11476 mode = nonzero_bits_mode;
11477 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11478 rsp->last_set_sign_bit_copies
11479 = num_sign_bit_copies (value, GET_MODE (reg));
11483 /* Called via note_stores from record_dead_and_set_regs to handle one
11484 SET or CLOBBER in an insn. DATA is the instruction in which the
11485 set is occurring. */
11488 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11490 rtx record_dead_insn = (rtx) data;
11492 if (GET_CODE (dest) == SUBREG)
11493 dest = SUBREG_REG (dest);
11495 if (!record_dead_insn)
11498 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11504 /* If we are setting the whole register, we know its value. Otherwise
11505 show that we don't know the value. We can handle SUBREG in
11507 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11508 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11509 else if (GET_CODE (setter) == SET
11510 && GET_CODE (SET_DEST (setter)) == SUBREG
11511 && SUBREG_REG (SET_DEST (setter)) == dest
11512 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11513 && subreg_lowpart_p (SET_DEST (setter)))
11514 record_value_for_reg (dest, record_dead_insn,
11515 gen_lowpart (GET_MODE (dest),
11516 SET_SRC (setter)));
11518 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11520 else if (MEM_P (dest)
11521 /* Ignore pushes, they clobber nothing. */
11522 && ! push_operand (dest, GET_MODE (dest)))
11523 mem_last_set = DF_INSN_LUID (record_dead_insn);
11526 /* Update the records of when each REG was most recently set or killed
11527 for the things done by INSN. This is the last thing done in processing
11528 INSN in the combiner loop.
11530 We update reg_stat[], in particular fields last_set, last_set_value,
11531 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11532 last_death, and also the similar information mem_last_set (which insn
11533 most recently modified memory) and last_call_luid (which insn was the
11534 most recent subroutine call). */
11537 record_dead_and_set_regs (rtx insn)
11542 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11544 if (REG_NOTE_KIND (link) == REG_DEAD
11545 && REG_P (XEXP (link, 0)))
11547 unsigned int regno = REGNO (XEXP (link, 0));
11548 unsigned int endregno = END_REGNO (XEXP (link, 0));
11550 for (i = regno; i < endregno; i++)
11552 reg_stat_type *rsp;
11554 rsp = VEC_index (reg_stat_type, reg_stat, i);
11555 rsp->last_death = insn;
11558 else if (REG_NOTE_KIND (link) == REG_INC)
11559 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11564 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11565 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11567 reg_stat_type *rsp;
11569 rsp = VEC_index (reg_stat_type, reg_stat, i);
11570 rsp->last_set_invalid = 1;
11571 rsp->last_set = insn;
11572 rsp->last_set_value = 0;
11573 rsp->last_set_mode = VOIDmode;
11574 rsp->last_set_nonzero_bits = 0;
11575 rsp->last_set_sign_bit_copies = 0;
11576 rsp->last_death = 0;
11577 rsp->truncated_to_mode = VOIDmode;
11580 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11582 /* We can't combine into a call pattern. Remember, though, that
11583 the return value register is set at this LUID. We could
11584 still replace a register with the return value from the
11585 wrong subroutine call! */
11586 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11589 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11592 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11593 register present in the SUBREG, so for each such SUBREG go back and
11594 adjust nonzero and sign bit information of the registers that are
11595 known to have some zero/sign bits set.
11597 This is needed because when combine blows the SUBREGs away, the
11598 information on zero/sign bits is lost and further combines can be
11599 missed because of that. */
11602 record_promoted_value (rtx insn, rtx subreg)
11605 unsigned int regno = REGNO (SUBREG_REG (subreg));
11606 enum machine_mode mode = GET_MODE (subreg);
11608 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11611 for (links = LOG_LINKS (insn); links;)
11613 reg_stat_type *rsp;
11615 insn = XEXP (links, 0);
11616 set = single_set (insn);
11618 if (! set || !REG_P (SET_DEST (set))
11619 || REGNO (SET_DEST (set)) != regno
11620 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11622 links = XEXP (links, 1);
11626 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11627 if (rsp->last_set == insn)
11629 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11630 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11633 if (REG_P (SET_SRC (set)))
11635 regno = REGNO (SET_SRC (set));
11636 links = LOG_LINKS (insn);
11643 /* Check if X, a register, is known to contain a value already
11644 truncated to MODE. In this case we can use a subreg to refer to
11645 the truncated value even though in the generic case we would need
11646 an explicit truncation. */
11649 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11651 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11652 enum machine_mode truncated = rsp->truncated_to_mode;
11655 || rsp->truncation_label < label_tick_ebb_start)
11657 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11659 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11660 GET_MODE_BITSIZE (truncated)))
11665 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11666 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11667 might be able to turn a truncate into a subreg using this information.
11668 Return -1 if traversing *P is complete or 0 otherwise. */
11671 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11674 enum machine_mode truncated_mode;
11675 reg_stat_type *rsp;
11677 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11679 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11680 truncated_mode = GET_MODE (x);
11682 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11685 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11686 GET_MODE_BITSIZE (original_mode)))
11689 x = SUBREG_REG (x);
11691 /* ??? For hard-regs we now record everything. We might be able to
11692 optimize this using last_set_mode. */
11693 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11694 truncated_mode = GET_MODE (x);
11698 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11699 if (rsp->truncated_to_mode == 0
11700 || rsp->truncation_label < label_tick_ebb_start
11701 || (GET_MODE_SIZE (truncated_mode)
11702 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11704 rsp->truncated_to_mode = truncated_mode;
11705 rsp->truncation_label = label_tick;
11711 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11712 the modes they are used in. This can help truning TRUNCATEs into
11716 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11718 for_each_rtx (x, record_truncated_value, NULL);
11721 /* Scan X for promoted SUBREGs. For each one found,
11722 note what it implies to the registers used in it. */
11725 check_promoted_subreg (rtx insn, rtx x)
11727 if (GET_CODE (x) == SUBREG
11728 && SUBREG_PROMOTED_VAR_P (x)
11729 && REG_P (SUBREG_REG (x)))
11730 record_promoted_value (insn, x);
11733 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11736 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11740 check_promoted_subreg (insn, XEXP (x, i));
11744 if (XVEC (x, i) != 0)
11745 for (j = 0; j < XVECLEN (x, i); j++)
11746 check_promoted_subreg (insn, XVECEXP (x, i, j));
11752 /* Utility routine for the following function. Verify that all the registers
11753 mentioned in *LOC are valid when *LOC was part of a value set when
11754 label_tick == TICK. Return 0 if some are not.
11756 If REPLACE is nonzero, replace the invalid reference with
11757 (clobber (const_int 0)) and return 1. This replacement is useful because
11758 we often can get useful information about the form of a value (e.g., if
11759 it was produced by a shift that always produces -1 or 0) even though
11760 we don't know exactly what registers it was produced from. */
11763 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11766 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11767 int len = GET_RTX_LENGTH (GET_CODE (x));
11772 unsigned int regno = REGNO (x);
11773 unsigned int endregno = END_REGNO (x);
11776 for (j = regno; j < endregno; j++)
11778 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11779 if (rsp->last_set_invalid
11780 /* If this is a pseudo-register that was only set once and not
11781 live at the beginning of the function, it is always valid. */
11782 || (! (regno >= FIRST_PSEUDO_REGISTER
11783 && REG_N_SETS (regno) == 1
11784 && (!REGNO_REG_SET_P
11785 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11786 && rsp->last_set_label > tick))
11789 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11796 /* If this is a memory reference, make sure that there were
11797 no stores after it that might have clobbered the value. We don't
11798 have alias info, so we assume any store invalidates it. */
11799 else if (MEM_P (x) && !MEM_READONLY_P (x)
11800 && DF_INSN_LUID (insn) <= mem_last_set)
11803 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11807 for (i = 0; i < len; i++)
11811 /* Check for identical subexpressions. If x contains
11812 identical subexpression we only have to traverse one of
11814 if (i == 1 && ARITHMETIC_P (x))
11816 /* Note that at this point x0 has already been checked
11817 and found valid. */
11818 rtx x0 = XEXP (x, 0);
11819 rtx x1 = XEXP (x, 1);
11821 /* If x0 and x1 are identical then x is also valid. */
11825 /* If x1 is identical to a subexpression of x0 then
11826 while checking x0, x1 has already been checked. Thus
11827 it is valid and so as x. */
11828 if (ARITHMETIC_P (x0)
11829 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11832 /* If x0 is identical to a subexpression of x1 then x is
11833 valid iff the rest of x1 is valid. */
11834 if (ARITHMETIC_P (x1)
11835 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11837 get_last_value_validate (&XEXP (x1,
11838 x0 == XEXP (x1, 0) ? 1 : 0),
11839 insn, tick, replace);
11842 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11846 else if (fmt[i] == 'E')
11847 for (j = 0; j < XVECLEN (x, i); j++)
11848 if (get_last_value_validate (&XVECEXP (x, i, j),
11849 insn, tick, replace) == 0)
11853 /* If we haven't found a reason for it to be invalid, it is valid. */
11857 /* Get the last value assigned to X, if known. Some registers
11858 in the value may be replaced with (clobber (const_int 0)) if their value
11859 is known longer known reliably. */
11862 get_last_value (const_rtx x)
11864 unsigned int regno;
11866 reg_stat_type *rsp;
11868 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11869 then convert it to the desired mode. If this is a paradoxical SUBREG,
11870 we cannot predict what values the "extra" bits might have. */
11871 if (GET_CODE (x) == SUBREG
11872 && subreg_lowpart_p (x)
11873 && (GET_MODE_SIZE (GET_MODE (x))
11874 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11875 && (value = get_last_value (SUBREG_REG (x))) != 0)
11876 return gen_lowpart (GET_MODE (x), value);
11882 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11883 value = rsp->last_set_value;
11885 /* If we don't have a value, or if it isn't for this basic block and
11886 it's either a hard register, set more than once, or it's a live
11887 at the beginning of the function, return 0.
11889 Because if it's not live at the beginning of the function then the reg
11890 is always set before being used (is never used without being set).
11891 And, if it's set only once, and it's always set before use, then all
11892 uses must have the same last value, even if it's not from this basic
11896 || (rsp->last_set_label < label_tick_ebb_start
11897 && (regno < FIRST_PSEUDO_REGISTER
11898 || REG_N_SETS (regno) != 1
11900 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11903 /* If the value was set in a later insn than the ones we are processing,
11904 we can't use it even if the register was only set once. */
11905 if (rsp->last_set_label == label_tick
11906 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11909 /* If the value has all its registers valid, return it. */
11910 if (get_last_value_validate (&value, rsp->last_set,
11911 rsp->last_set_label, 0))
11914 /* Otherwise, make a copy and replace any invalid register with
11915 (clobber (const_int 0)). If that fails for some reason, return 0. */
11917 value = copy_rtx (value);
11918 if (get_last_value_validate (&value, rsp->last_set,
11919 rsp->last_set_label, 1))
11925 /* Return nonzero if expression X refers to a REG or to memory
11926 that is set in an instruction more recent than FROM_LUID. */
11929 use_crosses_set_p (const_rtx x, int from_luid)
11933 enum rtx_code code = GET_CODE (x);
11937 unsigned int regno = REGNO (x);
11938 unsigned endreg = END_REGNO (x);
11940 #ifdef PUSH_ROUNDING
11941 /* Don't allow uses of the stack pointer to be moved,
11942 because we don't know whether the move crosses a push insn. */
11943 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11946 for (; regno < endreg; regno++)
11948 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11950 && rsp->last_set_label == label_tick
11951 && DF_INSN_LUID (rsp->last_set) > from_luid)
11957 if (code == MEM && mem_last_set > from_luid)
11960 fmt = GET_RTX_FORMAT (code);
11962 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11967 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11968 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11971 else if (fmt[i] == 'e'
11972 && use_crosses_set_p (XEXP (x, i), from_luid))
11978 /* Define three variables used for communication between the following
11981 static unsigned int reg_dead_regno, reg_dead_endregno;
11982 static int reg_dead_flag;
11984 /* Function called via note_stores from reg_dead_at_p.
11986 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11987 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11990 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11992 unsigned int regno, endregno;
11997 regno = REGNO (dest);
11998 endregno = END_REGNO (dest);
11999 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12000 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12003 /* Return nonzero if REG is known to be dead at INSN.
12005 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12006 referencing REG, it is dead. If we hit a SET referencing REG, it is
12007 live. Otherwise, see if it is live or dead at the start of the basic
12008 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12009 must be assumed to be always live. */
12012 reg_dead_at_p (rtx reg, rtx insn)
12017 /* Set variables for reg_dead_at_p_1. */
12018 reg_dead_regno = REGNO (reg);
12019 reg_dead_endregno = END_REGNO (reg);
12023 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12024 we allow the machine description to decide whether use-and-clobber
12025 patterns are OK. */
12026 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12028 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12029 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12033 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12034 beginning of basic block. */
12035 block = BLOCK_FOR_INSN (insn);
12040 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12042 return reg_dead_flag == 1 ? 1 : 0;
12044 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12048 if (insn == BB_HEAD (block))
12051 insn = PREV_INSN (insn);
12054 /* Look at live-in sets for the basic block that we were in. */
12055 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12056 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12062 /* Note hard registers in X that are used. */
12065 mark_used_regs_combine (rtx x)
12067 RTX_CODE code = GET_CODE (x);
12068 unsigned int regno;
12081 case ADDR_DIFF_VEC:
12084 /* CC0 must die in the insn after it is set, so we don't need to take
12085 special note of it here. */
12091 /* If we are clobbering a MEM, mark any hard registers inside the
12092 address as used. */
12093 if (MEM_P (XEXP (x, 0)))
12094 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12099 /* A hard reg in a wide mode may really be multiple registers.
12100 If so, mark all of them just like the first. */
12101 if (regno < FIRST_PSEUDO_REGISTER)
12103 /* None of this applies to the stack, frame or arg pointers. */
12104 if (regno == STACK_POINTER_REGNUM
12105 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12106 || regno == HARD_FRAME_POINTER_REGNUM
12108 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12109 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12111 || regno == FRAME_POINTER_REGNUM)
12114 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12120 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12122 rtx testreg = SET_DEST (x);
12124 while (GET_CODE (testreg) == SUBREG
12125 || GET_CODE (testreg) == ZERO_EXTRACT
12126 || GET_CODE (testreg) == STRICT_LOW_PART)
12127 testreg = XEXP (testreg, 0);
12129 if (MEM_P (testreg))
12130 mark_used_regs_combine (XEXP (testreg, 0));
12132 mark_used_regs_combine (SET_SRC (x));
12140 /* Recursively scan the operands of this expression. */
12143 const char *fmt = GET_RTX_FORMAT (code);
12145 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12148 mark_used_regs_combine (XEXP (x, i));
12149 else if (fmt[i] == 'E')
12153 for (j = 0; j < XVECLEN (x, i); j++)
12154 mark_used_regs_combine (XVECEXP (x, i, j));
12160 /* Remove register number REGNO from the dead registers list of INSN.
12162 Return the note used to record the death, if there was one. */
12165 remove_death (unsigned int regno, rtx insn)
12167 rtx note = find_regno_note (insn, REG_DEAD, regno);
12170 remove_note (insn, note);
12175 /* For each register (hardware or pseudo) used within expression X, if its
12176 death is in an instruction with luid between FROM_LUID (inclusive) and
12177 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12178 list headed by PNOTES.
12180 That said, don't move registers killed by maybe_kill_insn.
12182 This is done when X is being merged by combination into TO_INSN. These
12183 notes will then be distributed as needed. */
12186 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12191 enum rtx_code code = GET_CODE (x);
12195 unsigned int regno = REGNO (x);
12196 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12198 /* Don't move the register if it gets killed in between from and to. */
12199 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12200 && ! reg_referenced_p (x, maybe_kill_insn))
12204 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12205 && DF_INSN_LUID (where_dead) >= from_luid
12206 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12208 rtx note = remove_death (regno, where_dead);
12210 /* It is possible for the call above to return 0. This can occur
12211 when last_death points to I2 or I1 that we combined with.
12212 In that case make a new note.
12214 We must also check for the case where X is a hard register
12215 and NOTE is a death note for a range of hard registers
12216 including X. In that case, we must put REG_DEAD notes for
12217 the remaining registers in place of NOTE. */
12219 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12220 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12221 > GET_MODE_SIZE (GET_MODE (x))))
12223 unsigned int deadregno = REGNO (XEXP (note, 0));
12224 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12225 unsigned int ourend = END_HARD_REGNO (x);
12228 for (i = deadregno; i < deadend; i++)
12229 if (i < regno || i >= ourend)
12230 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12233 /* If we didn't find any note, or if we found a REG_DEAD note that
12234 covers only part of the given reg, and we have a multi-reg hard
12235 register, then to be safe we must check for REG_DEAD notes
12236 for each register other than the first. They could have
12237 their own REG_DEAD notes lying around. */
12238 else if ((note == 0
12240 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12241 < GET_MODE_SIZE (GET_MODE (x)))))
12242 && regno < FIRST_PSEUDO_REGISTER
12243 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12245 unsigned int ourend = END_HARD_REGNO (x);
12246 unsigned int i, offset;
12250 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12254 for (i = regno + offset; i < ourend; i++)
12255 move_deaths (regno_reg_rtx[i],
12256 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12259 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12261 XEXP (note, 1) = *pnotes;
12265 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12271 else if (GET_CODE (x) == SET)
12273 rtx dest = SET_DEST (x);
12275 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12277 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12278 that accesses one word of a multi-word item, some
12279 piece of everything register in the expression is used by
12280 this insn, so remove any old death. */
12281 /* ??? So why do we test for equality of the sizes? */
12283 if (GET_CODE (dest) == ZERO_EXTRACT
12284 || GET_CODE (dest) == STRICT_LOW_PART
12285 || (GET_CODE (dest) == SUBREG
12286 && (((GET_MODE_SIZE (GET_MODE (dest))
12287 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12288 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12289 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12291 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12295 /* If this is some other SUBREG, we know it replaces the entire
12296 value, so use that as the destination. */
12297 if (GET_CODE (dest) == SUBREG)
12298 dest = SUBREG_REG (dest);
12300 /* If this is a MEM, adjust deaths of anything used in the address.
12301 For a REG (the only other possibility), the entire value is
12302 being replaced so the old value is not used in this insn. */
12305 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12310 else if (GET_CODE (x) == CLOBBER)
12313 len = GET_RTX_LENGTH (code);
12314 fmt = GET_RTX_FORMAT (code);
12316 for (i = 0; i < len; i++)
12321 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12322 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12325 else if (fmt[i] == 'e')
12326 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12330 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12331 pattern of an insn. X must be a REG. */
12334 reg_bitfield_target_p (rtx x, rtx body)
12338 if (GET_CODE (body) == SET)
12340 rtx dest = SET_DEST (body);
12342 unsigned int regno, tregno, endregno, endtregno;
12344 if (GET_CODE (dest) == ZERO_EXTRACT)
12345 target = XEXP (dest, 0);
12346 else if (GET_CODE (dest) == STRICT_LOW_PART)
12347 target = SUBREG_REG (XEXP (dest, 0));
12351 if (GET_CODE (target) == SUBREG)
12352 target = SUBREG_REG (target);
12354 if (!REG_P (target))
12357 tregno = REGNO (target), regno = REGNO (x);
12358 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12359 return target == x;
12361 endtregno = end_hard_regno (GET_MODE (target), tregno);
12362 endregno = end_hard_regno (GET_MODE (x), regno);
12364 return endregno > tregno && regno < endtregno;
12367 else if (GET_CODE (body) == PARALLEL)
12368 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12369 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12375 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12376 as appropriate. I3 and I2 are the insns resulting from the combination
12377 insns including FROM (I2 may be zero).
12379 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12380 not need REG_DEAD notes because they are being substituted for. This
12381 saves searching in the most common cases.
12383 Each note in the list is either ignored or placed on some insns, depending
12384 on the type of note. */
12387 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12390 rtx note, next_note;
12393 for (note = notes; note; note = next_note)
12395 rtx place = 0, place2 = 0;
12397 next_note = XEXP (note, 1);
12398 switch (REG_NOTE_KIND (note))
12402 /* Doesn't matter much where we put this, as long as it's somewhere.
12403 It is preferable to keep these notes on branches, which is most
12404 likely to be i3. */
12408 case REG_VALUE_PROFILE:
12409 /* Just get rid of this note, as it is unused later anyway. */
12412 case REG_NON_LOCAL_GOTO:
12417 gcc_assert (i2 && JUMP_P (i2));
12422 case REG_EH_REGION:
12423 /* These notes must remain with the call or trapping instruction. */
12426 else if (i2 && CALL_P (i2))
12430 gcc_assert (flag_non_call_exceptions);
12431 if (may_trap_p (i3))
12433 else if (i2 && may_trap_p (i2))
12435 /* ??? Otherwise assume we've combined things such that we
12436 can now prove that the instructions can't trap. Drop the
12437 note in this case. */
12443 /* These notes must remain with the call. It should not be
12444 possible for both I2 and I3 to be a call. */
12449 gcc_assert (i2 && CALL_P (i2));
12455 /* Any clobbers for i3 may still exist, and so we must process
12456 REG_UNUSED notes from that insn.
12458 Any clobbers from i2 or i1 can only exist if they were added by
12459 recog_for_combine. In that case, recog_for_combine created the
12460 necessary REG_UNUSED notes. Trying to keep any original
12461 REG_UNUSED notes from these insns can cause incorrect output
12462 if it is for the same register as the original i3 dest.
12463 In that case, we will notice that the register is set in i3,
12464 and then add a REG_UNUSED note for the destination of i3, which
12465 is wrong. However, it is possible to have REG_UNUSED notes from
12466 i2 or i1 for register which were both used and clobbered, so
12467 we keep notes from i2 or i1 if they will turn into REG_DEAD
12470 /* If this register is set or clobbered in I3, put the note there
12471 unless there is one already. */
12472 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12474 if (from_insn != i3)
12477 if (! (REG_P (XEXP (note, 0))
12478 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12479 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12482 /* Otherwise, if this register is used by I3, then this register
12483 now dies here, so we must put a REG_DEAD note here unless there
12485 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12486 && ! (REG_P (XEXP (note, 0))
12487 ? find_regno_note (i3, REG_DEAD,
12488 REGNO (XEXP (note, 0)))
12489 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12491 PUT_REG_NOTE_KIND (note, REG_DEAD);
12499 /* These notes say something about results of an insn. We can
12500 only support them if they used to be on I3 in which case they
12501 remain on I3. Otherwise they are ignored.
12503 If the note refers to an expression that is not a constant, we
12504 must also ignore the note since we cannot tell whether the
12505 equivalence is still true. It might be possible to do
12506 slightly better than this (we only have a problem if I2DEST
12507 or I1DEST is present in the expression), but it doesn't
12508 seem worth the trouble. */
12510 if (from_insn == i3
12511 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12516 /* These notes say something about how a register is used. They must
12517 be present on any use of the register in I2 or I3. */
12518 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12521 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12530 case REG_LABEL_TARGET:
12531 case REG_LABEL_OPERAND:
12532 /* This can show up in several ways -- either directly in the
12533 pattern, or hidden off in the constant pool with (or without?)
12534 a REG_EQUAL note. */
12535 /* ??? Ignore the without-reg_equal-note problem for now. */
12536 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12537 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12538 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12539 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12543 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12544 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12545 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12546 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12554 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12555 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12557 if (place && JUMP_P (place)
12558 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12559 && (JUMP_LABEL (place) == NULL
12560 || JUMP_LABEL (place) == XEXP (note, 0)))
12562 rtx label = JUMP_LABEL (place);
12565 JUMP_LABEL (place) = XEXP (note, 0);
12566 else if (LABEL_P (label))
12567 LABEL_NUSES (label)--;
12570 if (place2 && JUMP_P (place2)
12571 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12572 && (JUMP_LABEL (place2) == NULL
12573 || JUMP_LABEL (place2) == XEXP (note, 0)))
12575 rtx label = JUMP_LABEL (place2);
12578 JUMP_LABEL (place2) = XEXP (note, 0);
12579 else if (LABEL_P (label))
12580 LABEL_NUSES (label)--;
12586 /* This note says something about the value of a register prior
12587 to the execution of an insn. It is too much trouble to see
12588 if the note is still correct in all situations. It is better
12589 to simply delete it. */
12593 /* If we replaced the right hand side of FROM_INSN with a
12594 REG_EQUAL note, the original use of the dying register
12595 will not have been combined into I3 and I2. In such cases,
12596 FROM_INSN is guaranteed to be the first of the combined
12597 instructions, so we simply need to search back before
12598 FROM_INSN for the previous use or set of this register,
12599 then alter the notes there appropriately.
12601 If the register is used as an input in I3, it dies there.
12602 Similarly for I2, if it is nonzero and adjacent to I3.
12604 If the register is not used as an input in either I3 or I2
12605 and it is not one of the registers we were supposed to eliminate,
12606 there are two possibilities. We might have a non-adjacent I2
12607 or we might have somehow eliminated an additional register
12608 from a computation. For example, we might have had A & B where
12609 we discover that B will always be zero. In this case we will
12610 eliminate the reference to A.
12612 In both cases, we must search to see if we can find a previous
12613 use of A and put the death note there. */
12616 && from_insn == i2mod
12617 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12622 && CALL_P (from_insn)
12623 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12625 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12627 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12628 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12630 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12632 && reg_overlap_mentioned_p (XEXP (note, 0),
12634 || rtx_equal_p (XEXP (note, 0), elim_i1))
12641 basic_block bb = this_basic_block;
12643 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12645 if (! INSN_P (tem))
12647 if (tem == BB_HEAD (bb))
12652 /* If the register is being set at TEM, see if that is all
12653 TEM is doing. If so, delete TEM. Otherwise, make this
12654 into a REG_UNUSED note instead. Don't delete sets to
12655 global register vars. */
12656 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12657 || !global_regs[REGNO (XEXP (note, 0))])
12658 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12660 rtx set = single_set (tem);
12661 rtx inner_dest = 0;
12663 rtx cc0_setter = NULL_RTX;
12667 for (inner_dest = SET_DEST (set);
12668 (GET_CODE (inner_dest) == STRICT_LOW_PART
12669 || GET_CODE (inner_dest) == SUBREG
12670 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12671 inner_dest = XEXP (inner_dest, 0))
12674 /* Verify that it was the set, and not a clobber that
12675 modified the register.
12677 CC0 targets must be careful to maintain setter/user
12678 pairs. If we cannot delete the setter due to side
12679 effects, mark the user with an UNUSED note instead
12682 if (set != 0 && ! side_effects_p (SET_SRC (set))
12683 && rtx_equal_p (XEXP (note, 0), inner_dest)
12685 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12686 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12687 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12691 /* Move the notes and links of TEM elsewhere.
12692 This might delete other dead insns recursively.
12693 First set the pattern to something that won't use
12695 rtx old_notes = REG_NOTES (tem);
12697 PATTERN (tem) = pc_rtx;
12698 REG_NOTES (tem) = NULL;
12700 distribute_notes (old_notes, tem, tem, NULL_RTX,
12701 NULL_RTX, NULL_RTX);
12702 distribute_links (LOG_LINKS (tem));
12704 SET_INSN_DELETED (tem);
12709 /* Delete the setter too. */
12712 PATTERN (cc0_setter) = pc_rtx;
12713 old_notes = REG_NOTES (cc0_setter);
12714 REG_NOTES (cc0_setter) = NULL;
12716 distribute_notes (old_notes, cc0_setter,
12717 cc0_setter, NULL_RTX,
12718 NULL_RTX, NULL_RTX);
12719 distribute_links (LOG_LINKS (cc0_setter));
12721 SET_INSN_DELETED (cc0_setter);
12722 if (cc0_setter == i2)
12729 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12731 /* If there isn't already a REG_UNUSED note, put one
12732 here. Do not place a REG_DEAD note, even if
12733 the register is also used here; that would not
12734 match the algorithm used in lifetime analysis
12735 and can cause the consistency check in the
12736 scheduler to fail. */
12737 if (! find_regno_note (tem, REG_UNUSED,
12738 REGNO (XEXP (note, 0))))
12743 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12745 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12749 /* If we are doing a 3->2 combination, and we have a
12750 register which formerly died in i3 and was not used
12751 by i2, which now no longer dies in i3 and is used in
12752 i2 but does not die in i2, and place is between i2
12753 and i3, then we may need to move a link from place to
12755 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12757 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12758 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12760 rtx links = LOG_LINKS (place);
12761 LOG_LINKS (place) = 0;
12762 distribute_links (links);
12767 if (tem == BB_HEAD (bb))
12773 /* If the register is set or already dead at PLACE, we needn't do
12774 anything with this note if it is still a REG_DEAD note.
12775 We check here if it is set at all, not if is it totally replaced,
12776 which is what `dead_or_set_p' checks, so also check for it being
12779 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12781 unsigned int regno = REGNO (XEXP (note, 0));
12782 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12784 if (dead_or_set_p (place, XEXP (note, 0))
12785 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12787 /* Unless the register previously died in PLACE, clear
12788 last_death. [I no longer understand why this is
12790 if (rsp->last_death != place)
12791 rsp->last_death = 0;
12795 rsp->last_death = place;
12797 /* If this is a death note for a hard reg that is occupying
12798 multiple registers, ensure that we are still using all
12799 parts of the object. If we find a piece of the object
12800 that is unused, we must arrange for an appropriate REG_DEAD
12801 note to be added for it. However, we can't just emit a USE
12802 and tag the note to it, since the register might actually
12803 be dead; so we recourse, and the recursive call then finds
12804 the previous insn that used this register. */
12806 if (place && regno < FIRST_PSEUDO_REGISTER
12807 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12809 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12813 for (i = regno; i < endregno; i++)
12814 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12815 && ! find_regno_fusage (place, USE, i))
12816 || dead_or_set_regno_p (place, i))
12821 /* Put only REG_DEAD notes for pieces that are
12822 not already dead or set. */
12824 for (i = regno; i < endregno;
12825 i += hard_regno_nregs[i][reg_raw_mode[i]])
12827 rtx piece = regno_reg_rtx[i];
12828 basic_block bb = this_basic_block;
12830 if (! dead_or_set_p (place, piece)
12831 && ! reg_bitfield_target_p (piece,
12834 rtx new_note = alloc_reg_note (REG_DEAD, piece,
12837 distribute_notes (new_note, place, place,
12838 NULL_RTX, NULL_RTX, NULL_RTX);
12840 else if (! refers_to_regno_p (i, i + 1,
12841 PATTERN (place), 0)
12842 && ! find_regno_fusage (place, USE, i))
12843 for (tem = PREV_INSN (place); ;
12844 tem = PREV_INSN (tem))
12846 if (! INSN_P (tem))
12848 if (tem == BB_HEAD (bb))
12852 if (dead_or_set_p (tem, piece)
12853 || reg_bitfield_target_p (piece,
12856 add_reg_note (tem, REG_UNUSED, piece);
12870 /* Any other notes should not be present at this point in the
12872 gcc_unreachable ();
12877 XEXP (note, 1) = REG_NOTES (place);
12878 REG_NOTES (place) = note;
12882 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
12886 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12887 I3, I2, and I1 to new locations. This is also called to add a link
12888 pointing at I3 when I3's destination is changed. */
12891 distribute_links (rtx links)
12893 rtx link, next_link;
12895 for (link = links; link; link = next_link)
12901 next_link = XEXP (link, 1);
12903 /* If the insn that this link points to is a NOTE or isn't a single
12904 set, ignore it. In the latter case, it isn't clear what we
12905 can do other than ignore the link, since we can't tell which
12906 register it was for. Such links wouldn't be used by combine
12909 It is not possible for the destination of the target of the link to
12910 have been changed by combine. The only potential of this is if we
12911 replace I3, I2, and I1 by I3 and I2. But in that case the
12912 destination of I2 also remains unchanged. */
12914 if (NOTE_P (XEXP (link, 0))
12915 || (set = single_set (XEXP (link, 0))) == 0)
12918 reg = SET_DEST (set);
12919 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12920 || GET_CODE (reg) == STRICT_LOW_PART)
12921 reg = XEXP (reg, 0);
12923 /* A LOG_LINK is defined as being placed on the first insn that uses
12924 a register and points to the insn that sets the register. Start
12925 searching at the next insn after the target of the link and stop
12926 when we reach a set of the register or the end of the basic block.
12928 Note that this correctly handles the link that used to point from
12929 I3 to I2. Also note that not much searching is typically done here
12930 since most links don't point very far away. */
12932 for (insn = NEXT_INSN (XEXP (link, 0));
12933 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12934 || BB_HEAD (this_basic_block->next_bb) != insn));
12935 insn = NEXT_INSN (insn))
12936 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12938 if (reg_referenced_p (reg, PATTERN (insn)))
12942 else if (CALL_P (insn)
12943 && find_reg_fusage (insn, USE, reg))
12948 else if (INSN_P (insn) && reg_set_p (reg, insn))
12951 /* If we found a place to put the link, place it there unless there
12952 is already a link to the same insn as LINK at that point. */
12958 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12959 if (XEXP (link2, 0) == XEXP (link, 0))
12964 XEXP (link, 1) = LOG_LINKS (place);
12965 LOG_LINKS (place) = link;
12967 /* Set added_links_insn to the earliest insn we added a
12969 if (added_links_insn == 0
12970 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12971 added_links_insn = place;
12977 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12978 Check whether the expression pointer to by LOC is a register or
12979 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12980 Otherwise return zero. */
12983 unmentioned_reg_p_1 (rtx *loc, void *expr)
12988 && (REG_P (x) || MEM_P (x))
12989 && ! reg_mentioned_p (x, (rtx) expr))
12994 /* Check for any register or memory mentioned in EQUIV that is not
12995 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12996 of EXPR where some registers may have been replaced by constants. */
12999 unmentioned_reg_p (rtx equiv, rtx expr)
13001 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13005 dump_combine_stats (FILE *file)
13009 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13010 combine_attempts, combine_merges, combine_extras, combine_successes);
13014 dump_combine_total_stats (FILE *file)
13018 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13019 total_attempts, total_merges, total_extras, total_successes);
13023 gate_handle_combine (void)
13025 return (optimize > 0);
13028 /* Try combining insns through substitution. */
13029 static unsigned int
13030 rest_of_handle_combine (void)
13032 int rebuild_jump_labels_after_combine;
13034 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13035 df_note_add_problem ();
13038 regstat_init_n_sets_and_refs ();
13040 rebuild_jump_labels_after_combine
13041 = combine_instructions (get_insns (), max_reg_num ());
13043 /* Combining insns may have turned an indirect jump into a
13044 direct jump. Rebuild the JUMP_LABEL fields of jumping
13046 if (rebuild_jump_labels_after_combine)
13048 timevar_push (TV_JUMP);
13049 rebuild_jump_labels (get_insns ());
13051 timevar_pop (TV_JUMP);
13054 regstat_free_n_sets_and_refs ();
13058 struct rtl_opt_pass pass_combine =
13062 "combine", /* name */
13063 gate_handle_combine, /* gate */
13064 rest_of_handle_combine, /* execute */
13067 0, /* static_pass_number */
13068 TV_COMBINE, /* tv_id */
13069 PROP_cfglayout, /* properties_required */
13070 0, /* properties_provided */
13071 0, /* properties_destroyed */
13072 0, /* todo_flags_start */
13074 TODO_df_finish | TODO_verify_rtl_sharing |
13075 TODO_ggc_collect, /* todo_flags_finish */
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