1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
427 /* We'd like to catch as many invalid transformations here as
428 possible. Unfortunately, there are way too many mode changes
429 that are perfectly valid, so we'd waste too much effort for
430 little gain doing the checks here. Focus on catching invalid
431 transformations involving integer constants. */
432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
433 && GET_CODE (newval) == CONST_INT)
435 /* Sanity check that we're replacing oldval with a CONST_INT
436 that is a valid sign-extension for the original mode. */
437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
442 CONST_INT is not valid, because after the replacement, the
443 original mode would be gone. Unfortunately, we can't tell
444 when do_SUBST is called to replace the operand thereof, so we
445 perform this test on oldval instead, checking whether an
446 invalid replacement took place before we got here. */
447 if ((GET_CODE (oldval) == SUBREG
448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
449 || (GET_CODE (oldval) == ZERO_EXTEND
450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
475 unsigned int *into, newval;
478 unsigned int oldval = *into;
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (last_basic_block);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
616 init_reg_last_arrays ();
617 setup_incoming_promotions ();
619 FOR_EACH_BB (this_basic_block)
621 for (insn = this_basic_block->head;
622 insn != NEXT_INSN (this_basic_block->end);
623 insn = next ? next : NEXT_INSN (insn))
627 if (GET_CODE (insn) == CODE_LABEL)
630 else if (INSN_P (insn))
632 /* See if we know about function return values before this
633 insn based upon SUBREG flags. */
634 check_promoted_subreg (insn, PATTERN (insn));
636 /* Try this insn with each insn it links back to. */
638 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
639 if ((next = try_combine (insn, XEXP (links, 0),
640 NULL_RTX, &new_direct_jump_p)) != 0)
643 /* Try each sequence of three linked insns ending with this one. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
647 rtx link = XEXP (links, 0);
649 /* If the linked insn has been replaced by a note, then there
650 is no point in pursuing this chain any further. */
651 if (GET_CODE (link) == NOTE)
654 for (nextlinks = LOG_LINKS (link);
656 nextlinks = XEXP (nextlinks, 1))
657 if ((next = try_combine (insn, link,
659 &new_direct_jump_p)) != 0)
664 /* Try to combine a jump insn that uses CC0
665 with a preceding insn that sets CC0, and maybe with its
666 logical predecessor as well.
667 This is how we make decrement-and-branch insns.
668 We need this special code because data flow connections
669 via CC0 do not get entered in LOG_LINKS. */
671 if (GET_CODE (insn) == JUMP_INSN
672 && (prev = prev_nonnote_insn (insn)) != 0
673 && GET_CODE (prev) == INSN
674 && sets_cc0_p (PATTERN (prev)))
676 if ((next = try_combine (insn, prev,
677 NULL_RTX, &new_direct_jump_p)) != 0)
680 for (nextlinks = LOG_LINKS (prev); nextlinks;
681 nextlinks = XEXP (nextlinks, 1))
682 if ((next = try_combine (insn, prev,
684 &new_direct_jump_p)) != 0)
688 /* Do the same for an insn that explicitly references CC0. */
689 if (GET_CODE (insn) == INSN
690 && (prev = prev_nonnote_insn (insn)) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev))
693 && GET_CODE (PATTERN (insn)) == SET
694 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
696 if ((next = try_combine (insn, prev,
697 NULL_RTX, &new_direct_jump_p)) != 0)
700 for (nextlinks = LOG_LINKS (prev); nextlinks;
701 nextlinks = XEXP (nextlinks, 1))
702 if ((next = try_combine (insn, prev,
704 &new_direct_jump_p)) != 0)
708 /* Finally, see if any of the insns that this insn links to
709 explicitly references CC0. If so, try this insn, that insn,
710 and its predecessor if it sets CC0. */
711 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
712 if (GET_CODE (XEXP (links, 0)) == INSN
713 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
714 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
715 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
716 && GET_CODE (prev) == INSN
717 && sets_cc0_p (PATTERN (prev))
718 && (next = try_combine (insn, XEXP (links, 0),
719 prev, &new_direct_jump_p)) != 0)
723 /* Try combining an insn with two different insns whose results it
725 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
726 for (nextlinks = XEXP (links, 1); nextlinks;
727 nextlinks = XEXP (nextlinks, 1))
728 if ((next = try_combine (insn, XEXP (links, 0),
730 &new_direct_jump_p)) != 0)
733 if (GET_CODE (insn) != NOTE)
734 record_dead_and_set_regs (insn);
743 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
744 BASIC_BLOCK (i)->flags |= BB_DIRTY);
745 new_direct_jump_p |= purge_all_dead_edges (0);
746 delete_noop_moves (f);
748 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
749 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
750 | PROP_KILL_DEAD_CODE);
753 sbitmap_free (refresh_blocks);
754 free (reg_nonzero_bits);
755 free (reg_sign_bit_copies);
756 free (reg_last_death);
758 free (reg_last_set_value);
759 free (reg_last_set_table_tick);
760 free (reg_last_set_label);
761 free (reg_last_set_invalid);
762 free (reg_last_set_mode);
763 free (reg_last_set_nonzero_bits);
764 free (reg_last_set_sign_bit_copies);
768 struct undo *undo, *next;
769 for (undo = undobuf.frees; undo; undo = next)
777 total_attempts += combine_attempts;
778 total_merges += combine_merges;
779 total_extras += combine_extras;
780 total_successes += combine_successes;
782 nonzero_sign_valid = 0;
784 /* Make recognizer allow volatile MEMs again. */
787 return new_direct_jump_p;
790 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
793 init_reg_last_arrays ()
795 unsigned int nregs = combine_max_regno;
797 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
798 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
800 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
801 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
802 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
803 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
804 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
805 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
808 /* Set up any promoted values for incoming argument registers. */
811 setup_incoming_promotions ()
813 #ifdef PROMOTE_FUNCTION_ARGS
816 enum machine_mode mode;
818 rtx first = get_insns ();
820 #ifndef OUTGOING_REGNO
821 #define OUTGOING_REGNO(N) N
823 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
824 /* Check whether this register can hold an incoming pointer
825 argument. FUNCTION_ARG_REGNO_P tests outgoing register
826 numbers, so translate if necessary due to register windows. */
827 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
828 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
831 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
834 gen_rtx_CLOBBER (mode, const0_rtx)));
839 /* Called via note_stores. If X is a pseudo that is narrower than
840 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
842 If we are setting only a portion of X and we can't figure out what
843 portion, assume all bits will be used since we don't know what will
846 Similarly, set how many bits of X are known to be copies of the sign bit
847 at all locations in the function. This is the smallest number implied
851 set_nonzero_bits_and_sign_copies (x, set, data)
854 void *data ATTRIBUTE_UNUSED;
858 if (GET_CODE (x) == REG
859 && REGNO (x) >= FIRST_PSEUDO_REGISTER
860 /* If this register is undefined at the start of the file, we can't
861 say what its contents were. */
862 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
863 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
865 if (set == 0 || GET_CODE (set) == CLOBBER)
867 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
868 reg_sign_bit_copies[REGNO (x)] = 1;
872 /* If this is a complex assignment, see if we can convert it into a
873 simple assignment. */
874 set = expand_field_assignment (set);
876 /* If this is a simple assignment, or we have a paradoxical SUBREG,
877 set what we know about X. */
879 if (SET_DEST (set) == x
880 || (GET_CODE (SET_DEST (set)) == SUBREG
881 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
882 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
883 && SUBREG_REG (SET_DEST (set)) == x))
885 rtx src = SET_SRC (set);
887 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
888 /* If X is narrower than a word and SRC is a non-negative
889 constant that would appear negative in the mode of X,
890 sign-extend it for use in reg_nonzero_bits because some
891 machines (maybe most) will actually do the sign-extension
892 and this is the conservative approach.
894 ??? For 2.5, try to tighten up the MD files in this regard
895 instead of this kludge. */
897 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
898 && GET_CODE (src) == CONST_INT
900 && 0 != (INTVAL (src)
902 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
903 src = GEN_INT (INTVAL (src)
904 | ((HOST_WIDE_INT) (-1)
905 << GET_MODE_BITSIZE (GET_MODE (x))));
908 /* Don't call nonzero_bits if it cannot change anything. */
909 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
910 reg_nonzero_bits[REGNO (x)]
911 |= nonzero_bits (src, nonzero_bits_mode);
912 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
913 if (reg_sign_bit_copies[REGNO (x)] == 0
914 || reg_sign_bit_copies[REGNO (x)] > num)
915 reg_sign_bit_copies[REGNO (x)] = num;
919 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
920 reg_sign_bit_copies[REGNO (x)] = 1;
925 /* See if INSN can be combined into I3. PRED and SUCC are optionally
926 insns that were previously combined into I3 or that will be combined
927 into the merger of INSN and I3.
929 Return 0 if the combination is not allowed for any reason.
931 If the combination is allowed, *PDEST will be set to the single
932 destination of INSN and *PSRC to the single source, and this function
936 can_combine_p (insn, i3, pred, succ, pdest, psrc)
939 rtx pred ATTRIBUTE_UNUSED;
944 rtx set = 0, src, dest;
949 int all_adjacent = (succ ? (next_active_insn (insn) == succ
950 && next_active_insn (succ) == i3)
951 : next_active_insn (insn) == i3);
953 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
954 or a PARALLEL consisting of such a SET and CLOBBERs.
956 If INSN has CLOBBER parallel parts, ignore them for our processing.
957 By definition, these happen during the execution of the insn. When it
958 is merged with another insn, all bets are off. If they are, in fact,
959 needed and aren't also supplied in I3, they may be added by
960 recog_for_combine. Otherwise, it won't match.
962 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
965 Get the source and destination of INSN. If more than one, can't
968 if (GET_CODE (PATTERN (insn)) == SET)
969 set = PATTERN (insn);
970 else if (GET_CODE (PATTERN (insn)) == PARALLEL
971 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
973 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
975 rtx elt = XVECEXP (PATTERN (insn), 0, i);
977 switch (GET_CODE (elt))
979 /* This is important to combine floating point insns
982 /* Combining an isolated USE doesn't make sense.
983 We depend here on combinable_i3pat to reject them. */
984 /* The code below this loop only verifies that the inputs of
985 the SET in INSN do not change. We call reg_set_between_p
986 to verify that the REG in the USE does not change between
988 If the USE in INSN was for a pseudo register, the matching
989 insn pattern will likely match any register; combining this
990 with any other USE would only be safe if we knew that the
991 used registers have identical values, or if there was
992 something to tell them apart, e.g. different modes. For
993 now, we forgo such complicated tests and simply disallow
994 combining of USES of pseudo registers with any other USE. */
995 if (GET_CODE (XEXP (elt, 0)) == REG
996 && GET_CODE (PATTERN (i3)) == PARALLEL)
998 rtx i3pat = PATTERN (i3);
999 int i = XVECLEN (i3pat, 0) - 1;
1000 unsigned int regno = REGNO (XEXP (elt, 0));
1004 rtx i3elt = XVECEXP (i3pat, 0, i);
1006 if (GET_CODE (i3elt) == USE
1007 && GET_CODE (XEXP (i3elt, 0)) == REG
1008 && (REGNO (XEXP (i3elt, 0)) == regno
1009 ? reg_set_between_p (XEXP (elt, 0),
1010 PREV_INSN (insn), i3)
1011 : regno >= FIRST_PSEUDO_REGISTER))
1018 /* We can ignore CLOBBERs. */
1023 /* Ignore SETs whose result isn't used but not those that
1024 have side-effects. */
1025 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1026 && ! side_effects_p (elt))
1029 /* If we have already found a SET, this is a second one and
1030 so we cannot combine with this insn. */
1038 /* Anything else means we can't combine. */
1044 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1045 so don't do anything with it. */
1046 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1055 set = expand_field_assignment (set);
1056 src = SET_SRC (set), dest = SET_DEST (set);
1058 /* Don't eliminate a store in the stack pointer. */
1059 if (dest == stack_pointer_rtx
1060 /* If we couldn't eliminate a field assignment, we can't combine. */
1061 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1062 /* Don't combine with an insn that sets a register to itself if it has
1063 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1064 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1065 /* Can't merge an ASM_OPERANDS. */
1066 || GET_CODE (src) == ASM_OPERANDS
1067 /* Can't merge a function call. */
1068 || GET_CODE (src) == CALL
1069 /* Don't eliminate a function call argument. */
1070 || (GET_CODE (i3) == CALL_INSN
1071 && (find_reg_fusage (i3, USE, dest)
1072 || (GET_CODE (dest) == REG
1073 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1074 && global_regs[REGNO (dest)])))
1075 /* Don't substitute into an incremented register. */
1076 || FIND_REG_INC_NOTE (i3, dest)
1077 || (succ && FIND_REG_INC_NOTE (succ, dest))
1079 /* Don't combine the end of a libcall into anything. */
1080 /* ??? This gives worse code, and appears to be unnecessary, since no
1081 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1082 use REG_RETVAL notes for noconflict blocks, but other code here
1083 makes sure that those insns don't disappear. */
1084 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1086 /* Make sure that DEST is not used after SUCC but before I3. */
1087 || (succ && ! all_adjacent
1088 && reg_used_between_p (dest, succ, i3))
1089 /* Make sure that the value that is to be substituted for the register
1090 does not use any registers whose values alter in between. However,
1091 If the insns are adjacent, a use can't cross a set even though we
1092 think it might (this can happen for a sequence of insns each setting
1093 the same destination; reg_last_set of that register might point to
1094 a NOTE). If INSN has a REG_EQUIV note, the register is always
1095 equivalent to the memory so the substitution is valid even if there
1096 are intervening stores. Also, don't move a volatile asm or
1097 UNSPEC_VOLATILE across any other insns. */
1099 && (((GET_CODE (src) != MEM
1100 || ! find_reg_note (insn, REG_EQUIV, src))
1101 && use_crosses_set_p (src, INSN_CUID (insn)))
1102 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1103 || GET_CODE (src) == UNSPEC_VOLATILE))
1104 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1105 better register allocation by not doing the combine. */
1106 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1107 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1108 /* Don't combine across a CALL_INSN, because that would possibly
1109 change whether the life span of some REGs crosses calls or not,
1110 and it is a pain to update that information.
1111 Exception: if source is a constant, moving it later can't hurt.
1112 Accept that special case, because it helps -fforce-addr a lot. */
1113 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1116 /* DEST must either be a REG or CC0. */
1117 if (GET_CODE (dest) == REG)
1119 /* If register alignment is being enforced for multi-word items in all
1120 cases except for parameters, it is possible to have a register copy
1121 insn referencing a hard register that is not allowed to contain the
1122 mode being copied and which would not be valid as an operand of most
1123 insns. Eliminate this problem by not combining with such an insn.
1125 Also, on some machines we don't want to extend the life of a hard
1128 if (GET_CODE (src) == REG
1129 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1130 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1131 /* Don't extend the life of a hard register unless it is
1132 user variable (if we have few registers) or it can't
1133 fit into the desired register (meaning something special
1135 Also avoid substituting a return register into I3, because
1136 reload can't handle a conflict with constraints of other
1138 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1139 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1142 else if (GET_CODE (dest) != CC0)
1145 /* Don't substitute for a register intended as a clobberable operand.
1146 Similarly, don't substitute an expression containing a register that
1147 will be clobbered in I3. */
1148 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1149 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1150 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1151 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1153 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1156 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1157 or not), reject, unless nothing volatile comes between it and I3 */
1159 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1161 /* Make sure succ doesn't contain a volatile reference. */
1162 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1165 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1166 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1170 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1171 to be an explicit register variable, and was chosen for a reason. */
1173 if (GET_CODE (src) == ASM_OPERANDS
1174 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1177 /* If there are any volatile insns between INSN and I3, reject, because
1178 they might affect machine state. */
1180 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1181 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1184 /* If INSN or I2 contains an autoincrement or autodecrement,
1185 make sure that register is not used between there and I3,
1186 and not already used in I3 either.
1187 Also insist that I3 not be a jump; if it were one
1188 and the incremented register were spilled, we would lose. */
1191 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1192 if (REG_NOTE_KIND (link) == REG_INC
1193 && (GET_CODE (i3) == JUMP_INSN
1194 || reg_used_between_p (XEXP (link, 0), insn, i3)
1195 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1200 /* Don't combine an insn that follows a CC0-setting insn.
1201 An insn that uses CC0 must not be separated from the one that sets it.
1202 We do, however, allow I2 to follow a CC0-setting insn if that insn
1203 is passed as I1; in that case it will be deleted also.
1204 We also allow combining in this case if all the insns are adjacent
1205 because that would leave the two CC0 insns adjacent as well.
1206 It would be more logical to test whether CC0 occurs inside I1 or I2,
1207 but that would be much slower, and this ought to be equivalent. */
1209 p = prev_nonnote_insn (insn);
1210 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1215 /* If we get here, we have passed all the tests and the combination is
1224 /* Check if PAT is an insn - or a part of it - used to set up an
1225 argument for a function in a hard register. */
1228 sets_function_arg_p (pat)
1234 switch (GET_CODE (pat))
1237 return sets_function_arg_p (PATTERN (pat));
1240 for (i = XVECLEN (pat, 0); --i >= 0;)
1241 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1247 inner_dest = SET_DEST (pat);
1248 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1249 || GET_CODE (inner_dest) == SUBREG
1250 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1251 inner_dest = XEXP (inner_dest, 0);
1253 return (GET_CODE (inner_dest) == REG
1254 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1255 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1264 /* LOC is the location within I3 that contains its pattern or the component
1265 of a PARALLEL of the pattern. We validate that it is valid for combining.
1267 One problem is if I3 modifies its output, as opposed to replacing it
1268 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1269 so would produce an insn that is not equivalent to the original insns.
1273 (set (reg:DI 101) (reg:DI 100))
1274 (set (subreg:SI (reg:DI 101) 0) <foo>)
1276 This is NOT equivalent to:
1278 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1279 (set (reg:DI 101) (reg:DI 100))])
1281 Not only does this modify 100 (in which case it might still be valid
1282 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1284 We can also run into a problem if I2 sets a register that I1
1285 uses and I1 gets directly substituted into I3 (not via I2). In that
1286 case, we would be getting the wrong value of I2DEST into I3, so we
1287 must reject the combination. This case occurs when I2 and I1 both
1288 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1289 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1290 of a SET must prevent combination from occurring.
1292 Before doing the above check, we first try to expand a field assignment
1293 into a set of logical operations.
1295 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1296 we place a register that is both set and used within I3. If more than one
1297 such register is detected, we fail.
1299 Return 1 if the combination is valid, zero otherwise. */
1302 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1308 rtx *pi3dest_killed;
1312 if (GET_CODE (x) == SET)
1314 rtx set = expand_field_assignment (x);
1315 rtx dest = SET_DEST (set);
1316 rtx src = SET_SRC (set);
1317 rtx inner_dest = dest;
1320 rtx inner_src = src;
1325 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1326 || GET_CODE (inner_dest) == SUBREG
1327 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1328 inner_dest = XEXP (inner_dest, 0);
1330 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1333 while (GET_CODE (inner_src) == STRICT_LOW_PART
1334 || GET_CODE (inner_src) == SUBREG
1335 || GET_CODE (inner_src) == ZERO_EXTRACT)
1336 inner_src = XEXP (inner_src, 0);
1338 /* If it is better that two different modes keep two different pseudos,
1339 avoid combining them. This avoids producing the following pattern
1341 (set (subreg:SI (reg/v:QI 21) 0)
1342 (lshiftrt:SI (reg/v:SI 20)
1344 If that were made, reload could not handle the pair of
1345 reg 20/21, since it would try to get any GENERAL_REGS
1346 but some of them don't handle QImode. */
1348 if (rtx_equal_p (inner_src, i2dest)
1349 && GET_CODE (inner_dest) == REG
1350 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1354 /* Check for the case where I3 modifies its output, as
1356 if ((inner_dest != dest
1357 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1358 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1360 /* This is the same test done in can_combine_p except we can't test
1361 all_adjacent; we don't have to, since this instruction will stay
1362 in place, thus we are not considering increasing the lifetime of
1365 Also, if this insn sets a function argument, combining it with
1366 something that might need a spill could clobber a previous
1367 function argument; the all_adjacent test in can_combine_p also
1368 checks this; here, we do a more specific test for this case. */
1370 || (GET_CODE (inner_dest) == REG
1371 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1372 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1373 GET_MODE (inner_dest))))
1374 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1377 /* If DEST is used in I3, it is being killed in this insn,
1378 so record that for later.
1379 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1380 STACK_POINTER_REGNUM, since these are always considered to be
1381 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1382 if (pi3dest_killed && GET_CODE (dest) == REG
1383 && reg_referenced_p (dest, PATTERN (i3))
1384 && REGNO (dest) != FRAME_POINTER_REGNUM
1385 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1386 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1388 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1389 && (REGNO (dest) != ARG_POINTER_REGNUM
1390 || ! fixed_regs [REGNO (dest)])
1392 && REGNO (dest) != STACK_POINTER_REGNUM)
1394 if (*pi3dest_killed)
1397 *pi3dest_killed = dest;
1401 else if (GET_CODE (x) == PARALLEL)
1405 for (i = 0; i < XVECLEN (x, 0); i++)
1406 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1407 i1_not_in_src, pi3dest_killed))
1414 /* Return 1 if X is an arithmetic expression that contains a multiplication
1415 and division. We don't count multiplications by powers of two here. */
1421 switch (GET_CODE (x))
1423 case MOD: case DIV: case UMOD: case UDIV:
1427 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1428 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1430 switch (GET_RTX_CLASS (GET_CODE (x)))
1432 case 'c': case '<': case '2':
1433 return contains_muldiv (XEXP (x, 0))
1434 || contains_muldiv (XEXP (x, 1));
1437 return contains_muldiv (XEXP (x, 0));
1445 /* Determine whether INSN can be used in a combination. Return nonzero if
1446 not. This is used in try_combine to detect early some cases where we
1447 can't perform combinations. */
1450 cant_combine_insn_p (insn)
1456 /* If this isn't really an insn, we can't do anything.
1457 This can occur when flow deletes an insn that it has merged into an
1458 auto-increment address. */
1459 if (! INSN_P (insn))
1462 /* Never combine loads and stores involving hard regs. The register
1463 allocator can usually handle such reg-reg moves by tying. If we allow
1464 the combiner to make substitutions of hard regs, we risk aborting in
1465 reload on machines that have SMALL_REGISTER_CLASSES.
1466 As an exception, we allow combinations involving fixed regs; these are
1467 not available to the register allocator so there's no risk involved. */
1469 set = single_set (insn);
1472 src = SET_SRC (set);
1473 dest = SET_DEST (set);
1474 if (GET_CODE (src) == SUBREG)
1475 src = SUBREG_REG (src);
1476 if (GET_CODE (dest) == SUBREG)
1477 dest = SUBREG_REG (dest);
1478 if (REG_P (src) && REG_P (dest)
1479 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1480 && ! fixed_regs[REGNO (src)])
1481 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1482 && ! fixed_regs[REGNO (dest)])))
1488 /* Try to combine the insns I1 and I2 into I3.
1489 Here I1 and I2 appear earlier than I3.
1490 I1 can be zero; then we combine just I2 into I3.
1492 If we are combining three insns and the resulting insn is not recognized,
1493 try splitting it into two insns. If that happens, I2 and I3 are retained
1494 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1497 Return 0 if the combination does not work. Then nothing is changed.
1498 If we did the combination, return the insn at which combine should
1501 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1502 new direct jump instruction. */
1505 try_combine (i3, i2, i1, new_direct_jump_p)
1507 int *new_direct_jump_p;
1509 /* New patterns for I3 and I2, respectively. */
1510 rtx newpat, newi2pat = 0;
1511 int substed_i2 = 0, substed_i1 = 0;
1512 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1513 int added_sets_1, added_sets_2;
1514 /* Total number of SETs to put into I3. */
1516 /* Nonzero is I2's body now appears in I3. */
1518 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1519 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1520 /* Contains I3 if the destination of I3 is used in its source, which means
1521 that the old life of I3 is being killed. If that usage is placed into
1522 I2 and not in I3, a REG_DEAD note must be made. */
1523 rtx i3dest_killed = 0;
1524 /* SET_DEST and SET_SRC of I2 and I1. */
1525 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1526 /* PATTERN (I2), or a copy of it in certain cases. */
1528 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1529 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1530 int i1_feeds_i3 = 0;
1531 /* Notes that must be added to REG_NOTES in I3 and I2. */
1532 rtx new_i3_notes, new_i2_notes;
1533 /* Notes that we substituted I3 into I2 instead of the normal case. */
1534 int i3_subst_into_i2 = 0;
1535 /* Notes that I1, I2 or I3 is a MULT operation. */
1543 /* Exit early if one of the insns involved can't be used for
1545 if (cant_combine_insn_p (i3)
1546 || cant_combine_insn_p (i2)
1547 || (i1 && cant_combine_insn_p (i1))
1548 /* We also can't do anything if I3 has a
1549 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1552 /* ??? This gives worse code, and appears to be unnecessary, since no
1553 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1554 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1560 undobuf.other_insn = 0;
1562 /* Reset the hard register usage information. */
1563 CLEAR_HARD_REG_SET (newpat_used_regs);
1565 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1566 code below, set I1 to be the earlier of the two insns. */
1567 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1568 temp = i1, i1 = i2, i2 = temp;
1570 added_links_insn = 0;
1572 /* First check for one important special-case that the code below will
1573 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1574 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1575 we may be able to replace that destination with the destination of I3.
1576 This occurs in the common code where we compute both a quotient and
1577 remainder into a structure, in which case we want to do the computation
1578 directly into the structure to avoid register-register copies.
1580 Note that this case handles both multiple sets in I2 and also
1581 cases where I2 has a number of CLOBBER or PARALLELs.
1583 We make very conservative checks below and only try to handle the
1584 most common cases of this. For example, we only handle the case
1585 where I2 and I3 are adjacent to avoid making difficult register
1588 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1589 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1590 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1591 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1592 && GET_CODE (PATTERN (i2)) == PARALLEL
1593 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1594 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1595 below would need to check what is inside (and reg_overlap_mentioned_p
1596 doesn't support those codes anyway). Don't allow those destinations;
1597 the resulting insn isn't likely to be recognized anyway. */
1598 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1599 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1600 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1601 SET_DEST (PATTERN (i3)))
1602 && next_real_insn (i2) == i3)
1604 rtx p2 = PATTERN (i2);
1606 /* Make sure that the destination of I3,
1607 which we are going to substitute into one output of I2,
1608 is not used within another output of I2. We must avoid making this:
1609 (parallel [(set (mem (reg 69)) ...)
1610 (set (reg 69) ...)])
1611 which is not well-defined as to order of actions.
1612 (Besides, reload can't handle output reloads for this.)
1614 The problem can also happen if the dest of I3 is a memory ref,
1615 if another dest in I2 is an indirect memory ref. */
1616 for (i = 0; i < XVECLEN (p2, 0); i++)
1617 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1618 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1619 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1620 SET_DEST (XVECEXP (p2, 0, i))))
1623 if (i == XVECLEN (p2, 0))
1624 for (i = 0; i < XVECLEN (p2, 0); i++)
1625 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1626 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1627 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1632 subst_low_cuid = INSN_CUID (i2);
1634 added_sets_2 = added_sets_1 = 0;
1635 i2dest = SET_SRC (PATTERN (i3));
1637 /* Replace the dest in I2 with our dest and make the resulting
1638 insn the new pattern for I3. Then skip to where we
1639 validate the pattern. Everything was set up above. */
1640 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1641 SET_DEST (PATTERN (i3)));
1644 i3_subst_into_i2 = 1;
1645 goto validate_replacement;
1649 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1650 one of those words to another constant, merge them by making a new
1653 && (temp = single_set (i2)) != 0
1654 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1655 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1656 && GET_CODE (SET_DEST (temp)) == REG
1657 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1658 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1659 && GET_CODE (PATTERN (i3)) == SET
1660 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1661 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1662 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1663 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1664 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1666 HOST_WIDE_INT lo, hi;
1668 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1669 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1672 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1673 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1676 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1678 /* We don't handle the case of the target word being wider
1679 than a host wide int. */
1680 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1683 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1684 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1685 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1687 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1688 hi = INTVAL (SET_SRC (PATTERN (i3)));
1689 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1691 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1692 >> (HOST_BITS_PER_WIDE_INT - 1));
1694 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1695 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1696 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1697 (INTVAL (SET_SRC (PATTERN (i3)))));
1699 hi = lo < 0 ? -1 : 0;
1702 /* We don't handle the case of the higher word not fitting
1703 entirely in either hi or lo. */
1708 subst_low_cuid = INSN_CUID (i2);
1709 added_sets_2 = added_sets_1 = 0;
1710 i2dest = SET_DEST (temp);
1712 SUBST (SET_SRC (temp),
1713 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1715 newpat = PATTERN (i2);
1716 goto validate_replacement;
1720 /* If we have no I1 and I2 looks like:
1721 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1723 make up a dummy I1 that is
1726 (set (reg:CC X) (compare:CC Y (const_int 0)))
1728 (We can ignore any trailing CLOBBERs.)
1730 This undoes a previous combination and allows us to match a branch-and-
1733 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1734 && XVECLEN (PATTERN (i2), 0) >= 2
1735 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1736 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1738 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1739 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1740 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1741 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1742 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1743 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1745 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1746 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1751 /* We make I1 with the same INSN_UID as I2. This gives it
1752 the same INSN_CUID for value tracking. Our fake I1 will
1753 never appear in the insn stream so giving it the same INSN_UID
1754 as I2 will not cause a problem. */
1756 subst_prev_insn = i1
1757 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1758 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1759 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1762 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1763 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1764 SET_DEST (PATTERN (i1)));
1769 /* Verify that I2 and I1 are valid for combining. */
1770 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1771 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1777 /* Record whether I2DEST is used in I2SRC and similarly for the other
1778 cases. Knowing this will help in register status updating below. */
1779 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1780 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1781 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1783 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1785 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1787 /* Ensure that I3's pattern can be the destination of combines. */
1788 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1789 i1 && i2dest_in_i1src && i1_feeds_i3,
1796 /* See if any of the insns is a MULT operation. Unless one is, we will
1797 reject a combination that is, since it must be slower. Be conservative
1799 if (GET_CODE (i2src) == MULT
1800 || (i1 != 0 && GET_CODE (i1src) == MULT)
1801 || (GET_CODE (PATTERN (i3)) == SET
1802 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1805 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1806 We used to do this EXCEPT in one case: I3 has a post-inc in an
1807 output operand. However, that exception can give rise to insns like
1809 which is a famous insn on the PDP-11 where the value of r3 used as the
1810 source was model-dependent. Avoid this sort of thing. */
1813 if (!(GET_CODE (PATTERN (i3)) == SET
1814 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1815 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1816 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1817 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1818 /* It's not the exception. */
1821 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1822 if (REG_NOTE_KIND (link) == REG_INC
1823 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1825 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1832 /* See if the SETs in I1 or I2 need to be kept around in the merged
1833 instruction: whenever the value set there is still needed past I3.
1834 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1836 For the SET in I1, we have two cases: If I1 and I2 independently
1837 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1838 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1839 in I1 needs to be kept around unless I1DEST dies or is set in either
1840 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1841 I1DEST. If so, we know I1 feeds into I2. */
1843 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1846 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1847 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1849 /* If the set in I2 needs to be kept around, we must make a copy of
1850 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1851 PATTERN (I2), we are only substituting for the original I1DEST, not into
1852 an already-substituted copy. This also prevents making self-referential
1853 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1856 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1857 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1861 i2pat = copy_rtx (i2pat);
1865 /* Substitute in the latest insn for the regs set by the earlier ones. */
1867 maxreg = max_reg_num ();
1871 /* It is possible that the source of I2 or I1 may be performing an
1872 unneeded operation, such as a ZERO_EXTEND of something that is known
1873 to have the high part zero. Handle that case by letting subst look at
1874 the innermost one of them.
1876 Another way to do this would be to have a function that tries to
1877 simplify a single insn instead of merging two or more insns. We don't
1878 do this because of the potential of infinite loops and because
1879 of the potential extra memory required. However, doing it the way
1880 we are is a bit of a kludge and doesn't catch all cases.
1882 But only do this if -fexpensive-optimizations since it slows things down
1883 and doesn't usually win. */
1885 if (flag_expensive_optimizations)
1887 /* Pass pc_rtx so no substitutions are done, just simplifications.
1888 The cases that we are interested in here do not involve the few
1889 cases were is_replaced is checked. */
1892 subst_low_cuid = INSN_CUID (i1);
1893 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1897 subst_low_cuid = INSN_CUID (i2);
1898 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1903 /* Many machines that don't use CC0 have insns that can both perform an
1904 arithmetic operation and set the condition code. These operations will
1905 be represented as a PARALLEL with the first element of the vector
1906 being a COMPARE of an arithmetic operation with the constant zero.
1907 The second element of the vector will set some pseudo to the result
1908 of the same arithmetic operation. If we simplify the COMPARE, we won't
1909 match such a pattern and so will generate an extra insn. Here we test
1910 for this case, where both the comparison and the operation result are
1911 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1912 I2SRC. Later we will make the PARALLEL that contains I2. */
1914 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1915 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1916 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1917 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1919 #ifdef EXTRA_CC_MODES
1921 enum machine_mode compare_mode;
1924 newpat = PATTERN (i3);
1925 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1929 #ifdef EXTRA_CC_MODES
1930 /* See if a COMPARE with the operand we substituted in should be done
1931 with the mode that is currently being used. If not, do the same
1932 processing we do in `subst' for a SET; namely, if the destination
1933 is used only once, try to replace it with a register of the proper
1934 mode and also replace the COMPARE. */
1935 if (undobuf.other_insn == 0
1936 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1937 &undobuf.other_insn))
1938 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1940 != GET_MODE (SET_DEST (newpat))))
1942 unsigned int regno = REGNO (SET_DEST (newpat));
1943 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1945 if (regno < FIRST_PSEUDO_REGISTER
1946 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1947 && ! REG_USERVAR_P (SET_DEST (newpat))))
1949 if (regno >= FIRST_PSEUDO_REGISTER)
1950 SUBST (regno_reg_rtx[regno], new_dest);
1952 SUBST (SET_DEST (newpat), new_dest);
1953 SUBST (XEXP (*cc_use, 0), new_dest);
1954 SUBST (SET_SRC (newpat),
1955 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1958 undobuf.other_insn = 0;
1965 n_occurrences = 0; /* `subst' counts here */
1967 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1968 need to make a unique copy of I2SRC each time we substitute it
1969 to avoid self-referential rtl. */
1971 subst_low_cuid = INSN_CUID (i2);
1972 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1973 ! i1_feeds_i3 && i1dest_in_i1src);
1976 /* Record whether i2's body now appears within i3's body. */
1977 i2_is_used = n_occurrences;
1980 /* If we already got a failure, don't try to do more. Otherwise,
1981 try to substitute in I1 if we have it. */
1983 if (i1 && GET_CODE (newpat) != CLOBBER)
1985 /* Before we can do this substitution, we must redo the test done
1986 above (see detailed comments there) that ensures that I1DEST
1987 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1989 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1997 subst_low_cuid = INSN_CUID (i1);
1998 newpat = subst (newpat, i1dest, i1src, 0, 0);
2002 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2003 to count all the ways that I2SRC and I1SRC can be used. */
2004 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2005 && i2_is_used + added_sets_2 > 1)
2006 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2007 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2009 /* Fail if we tried to make a new register (we used to abort, but there's
2010 really no reason to). */
2011 || max_reg_num () != maxreg
2012 /* Fail if we couldn't do something and have a CLOBBER. */
2013 || GET_CODE (newpat) == CLOBBER
2014 /* Fail if this new pattern is a MULT and we didn't have one before
2015 at the outer level. */
2016 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2023 /* If the actions of the earlier insns must be kept
2024 in addition to substituting them into the latest one,
2025 we must make a new PARALLEL for the latest insn
2026 to hold additional the SETs. */
2028 if (added_sets_1 || added_sets_2)
2032 if (GET_CODE (newpat) == PARALLEL)
2034 rtvec old = XVEC (newpat, 0);
2035 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2036 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2037 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2038 sizeof (old->elem[0]) * old->num_elem);
2043 total_sets = 1 + added_sets_1 + added_sets_2;
2044 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2045 XVECEXP (newpat, 0, 0) = old;
2049 XVECEXP (newpat, 0, --total_sets)
2050 = (GET_CODE (PATTERN (i1)) == PARALLEL
2051 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2055 /* If there is no I1, use I2's body as is. We used to also not do
2056 the subst call below if I2 was substituted into I3,
2057 but that could lose a simplification. */
2059 XVECEXP (newpat, 0, --total_sets) = i2pat;
2061 /* See comment where i2pat is assigned. */
2062 XVECEXP (newpat, 0, --total_sets)
2063 = subst (i2pat, i1dest, i1src, 0, 0);
2067 /* We come here when we are replacing a destination in I2 with the
2068 destination of I3. */
2069 validate_replacement:
2071 /* Note which hard regs this insn has as inputs. */
2072 mark_used_regs_combine (newpat);
2074 /* Is the result of combination a valid instruction? */
2075 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2077 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2078 the second SET's destination is a register that is unused. In that case,
2079 we just need the first SET. This can occur when simplifying a divmod
2080 insn. We *must* test for this case here because the code below that
2081 splits two independent SETs doesn't handle this case correctly when it
2082 updates the register status. Also check the case where the first
2083 SET's destination is unused. That would not cause incorrect code, but
2084 does cause an unneeded insn to remain. */
2086 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2087 && XVECLEN (newpat, 0) == 2
2088 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2089 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2090 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2091 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2092 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2093 && asm_noperands (newpat) < 0)
2095 newpat = XVECEXP (newpat, 0, 0);
2096 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2099 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2100 && XVECLEN (newpat, 0) == 2
2101 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2102 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2103 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2104 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2105 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2106 && asm_noperands (newpat) < 0)
2108 newpat = XVECEXP (newpat, 0, 1);
2109 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2112 /* If we were combining three insns and the result is a simple SET
2113 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2114 insns. There are two ways to do this. It can be split using a
2115 machine-specific method (like when you have an addition of a large
2116 constant) or by combine in the function find_split_point. */
2118 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2119 && asm_noperands (newpat) < 0)
2121 rtx m_split, *split;
2122 rtx ni2dest = i2dest;
2124 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2125 use I2DEST as a scratch register will help. In the latter case,
2126 convert I2DEST to the mode of the source of NEWPAT if we can. */
2128 m_split = split_insns (newpat, i3);
2130 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2131 inputs of NEWPAT. */
2133 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2134 possible to try that as a scratch reg. This would require adding
2135 more code to make it work though. */
2137 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2139 /* If I2DEST is a hard register or the only use of a pseudo,
2140 we can change its mode. */
2141 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2142 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2143 && GET_CODE (i2dest) == REG
2144 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2145 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2146 && ! REG_USERVAR_P (i2dest))))
2147 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2150 m_split = split_insns (gen_rtx_PARALLEL
2152 gen_rtvec (2, newpat,
2153 gen_rtx_CLOBBER (VOIDmode,
2156 /* If the split with the mode-changed register didn't work, try
2157 the original register. */
2158 if (! m_split && ni2dest != i2dest)
2161 m_split = split_insns (gen_rtx_PARALLEL
2163 gen_rtvec (2, newpat,
2164 gen_rtx_CLOBBER (VOIDmode,
2170 /* If we've split a jump pattern, we'll wind up with a sequence even
2171 with one instruction. We can handle that below, so extract it. */
2172 if (m_split && GET_CODE (m_split) == SEQUENCE
2173 && XVECLEN (m_split, 0) == 1)
2174 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2176 if (m_split && GET_CODE (m_split) != SEQUENCE)
2178 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2179 if (insn_code_number >= 0)
2182 else if (m_split && GET_CODE (m_split) == SEQUENCE
2183 && XVECLEN (m_split, 0) == 2
2184 && (next_real_insn (i2) == i3
2185 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2189 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2190 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2192 i3set = single_set (XVECEXP (m_split, 0, 1));
2193 i2set = single_set (XVECEXP (m_split, 0, 0));
2195 /* In case we changed the mode of I2DEST, replace it in the
2196 pseudo-register table here. We can't do it above in case this
2197 code doesn't get executed and we do a split the other way. */
2199 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2200 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2202 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2204 /* If I2 or I3 has multiple SETs, we won't know how to track
2205 register status, so don't use these insns. If I2's destination
2206 is used between I2 and I3, we also can't use these insns. */
2208 if (i2_code_number >= 0 && i2set && i3set
2209 && (next_real_insn (i2) == i3
2210 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2211 insn_code_number = recog_for_combine (&newi3pat, i3,
2213 if (insn_code_number >= 0)
2216 /* It is possible that both insns now set the destination of I3.
2217 If so, we must show an extra use of it. */
2219 if (insn_code_number >= 0)
2221 rtx new_i3_dest = SET_DEST (i3set);
2222 rtx new_i2_dest = SET_DEST (i2set);
2224 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2225 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2226 || GET_CODE (new_i3_dest) == SUBREG)
2227 new_i3_dest = XEXP (new_i3_dest, 0);
2229 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2230 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2231 || GET_CODE (new_i2_dest) == SUBREG)
2232 new_i2_dest = XEXP (new_i2_dest, 0);
2234 if (GET_CODE (new_i3_dest) == REG
2235 && GET_CODE (new_i2_dest) == REG
2236 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2237 REG_N_SETS (REGNO (new_i2_dest))++;
2241 /* If we can split it and use I2DEST, go ahead and see if that
2242 helps things be recognized. Verify that none of the registers
2243 are set between I2 and I3. */
2244 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2246 && GET_CODE (i2dest) == REG
2248 /* We need I2DEST in the proper mode. If it is a hard register
2249 or the only use of a pseudo, we can change its mode. */
2250 && (GET_MODE (*split) == GET_MODE (i2dest)
2251 || GET_MODE (*split) == VOIDmode
2252 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2253 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2254 && ! REG_USERVAR_P (i2dest)))
2255 && (next_real_insn (i2) == i3
2256 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2257 /* We can't overwrite I2DEST if its value is still used by
2259 && ! reg_referenced_p (i2dest, newpat))
2261 rtx newdest = i2dest;
2262 enum rtx_code split_code = GET_CODE (*split);
2263 enum machine_mode split_mode = GET_MODE (*split);
2265 /* Get NEWDEST as a register in the proper mode. We have already
2266 validated that we can do this. */
2267 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2269 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2271 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2272 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2275 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2276 an ASHIFT. This can occur if it was inside a PLUS and hence
2277 appeared to be a memory address. This is a kludge. */
2278 if (split_code == MULT
2279 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2280 && INTVAL (XEXP (*split, 1)) > 0
2281 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2283 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2284 XEXP (*split, 0), GEN_INT (i)));
2285 /* Update split_code because we may not have a multiply
2287 split_code = GET_CODE (*split);
2290 #ifdef INSN_SCHEDULING
2291 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2292 be written as a ZERO_EXTEND. */
2293 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2294 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2295 SUBREG_REG (*split)));
2298 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2299 SUBST (*split, newdest);
2300 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2302 /* If the split point was a MULT and we didn't have one before,
2303 don't use one now. */
2304 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2305 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2309 /* Check for a case where we loaded from memory in a narrow mode and
2310 then sign extended it, but we need both registers. In that case,
2311 we have a PARALLEL with both loads from the same memory location.
2312 We can split this into a load from memory followed by a register-register
2313 copy. This saves at least one insn, more if register allocation can
2316 We cannot do this if the destination of the second assignment is
2317 a register that we have already assumed is zero-extended. Similarly
2318 for a SUBREG of such a register. */
2320 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2321 && GET_CODE (newpat) == PARALLEL
2322 && XVECLEN (newpat, 0) == 2
2323 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2324 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2325 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2326 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2327 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2328 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2330 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2331 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2332 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2333 (GET_CODE (temp) == REG
2334 && reg_nonzero_bits[REGNO (temp)] != 0
2335 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2336 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2337 && (reg_nonzero_bits[REGNO (temp)]
2338 != GET_MODE_MASK (word_mode))))
2339 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2340 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2341 (GET_CODE (temp) == REG
2342 && reg_nonzero_bits[REGNO (temp)] != 0
2343 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2344 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2345 && (reg_nonzero_bits[REGNO (temp)]
2346 != GET_MODE_MASK (word_mode)))))
2347 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2348 SET_SRC (XVECEXP (newpat, 0, 1)))
2349 && ! find_reg_note (i3, REG_UNUSED,
2350 SET_DEST (XVECEXP (newpat, 0, 0))))
2354 newi2pat = XVECEXP (newpat, 0, 0);
2355 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2356 newpat = XVECEXP (newpat, 0, 1);
2357 SUBST (SET_SRC (newpat),
2358 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2359 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2361 if (i2_code_number >= 0)
2362 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2364 if (insn_code_number >= 0)
2369 /* If we will be able to accept this, we have made a change to the
2370 destination of I3. This can invalidate a LOG_LINKS pointing
2371 to I3. No other part of combine.c makes such a transformation.
2373 The new I3 will have a destination that was previously the
2374 destination of I1 or I2 and which was used in i2 or I3. Call
2375 distribute_links to make a LOG_LINK from the next use of
2376 that destination. */
2378 PATTERN (i3) = newpat;
2379 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2381 /* I3 now uses what used to be its destination and which is
2382 now I2's destination. That means we need a LOG_LINK from
2383 I3 to I2. But we used to have one, so we still will.
2385 However, some later insn might be using I2's dest and have
2386 a LOG_LINK pointing at I3. We must remove this link.
2387 The simplest way to remove the link is to point it at I1,
2388 which we know will be a NOTE. */
2390 for (insn = NEXT_INSN (i3);
2391 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2392 || insn != this_basic_block->next_bb->head);
2393 insn = NEXT_INSN (insn))
2395 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2397 for (link = LOG_LINKS (insn); link;
2398 link = XEXP (link, 1))
2399 if (XEXP (link, 0) == i3)
2400 XEXP (link, 0) = i1;
2408 /* Similarly, check for a case where we have a PARALLEL of two independent
2409 SETs but we started with three insns. In this case, we can do the sets
2410 as two separate insns. This case occurs when some SET allows two
2411 other insns to combine, but the destination of that SET is still live. */
2413 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2414 && GET_CODE (newpat) == PARALLEL
2415 && XVECLEN (newpat, 0) == 2
2416 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2417 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2419 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2420 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2421 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2422 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2424 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2425 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2426 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2427 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2428 XVECEXP (newpat, 0, 0))
2429 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2430 XVECEXP (newpat, 0, 1))
2431 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2432 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2434 /* Normally, it doesn't matter which of the two is done first,
2435 but it does if one references cc0. In that case, it has to
2438 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2440 newi2pat = XVECEXP (newpat, 0, 0);
2441 newpat = XVECEXP (newpat, 0, 1);
2446 newi2pat = XVECEXP (newpat, 0, 1);
2447 newpat = XVECEXP (newpat, 0, 0);
2450 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2452 if (i2_code_number >= 0)
2453 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2456 /* If it still isn't recognized, fail and change things back the way they
2458 if ((insn_code_number < 0
2459 /* Is the result a reasonable ASM_OPERANDS? */
2460 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2466 /* If we had to change another insn, make sure it is valid also. */
2467 if (undobuf.other_insn)
2469 rtx other_pat = PATTERN (undobuf.other_insn);
2470 rtx new_other_notes;
2473 CLEAR_HARD_REG_SET (newpat_used_regs);
2475 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2478 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2484 PATTERN (undobuf.other_insn) = other_pat;
2486 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2487 are still valid. Then add any non-duplicate notes added by
2488 recog_for_combine. */
2489 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2491 next = XEXP (note, 1);
2493 if (REG_NOTE_KIND (note) == REG_UNUSED
2494 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2496 if (GET_CODE (XEXP (note, 0)) == REG)
2497 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2499 remove_note (undobuf.other_insn, note);
2503 for (note = new_other_notes; note; note = XEXP (note, 1))
2504 if (GET_CODE (XEXP (note, 0)) == REG)
2505 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2507 distribute_notes (new_other_notes, undobuf.other_insn,
2508 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2511 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2512 they are adjacent to each other or not. */
2514 rtx p = prev_nonnote_insn (i3);
2515 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2516 && sets_cc0_p (newi2pat))
2524 /* We now know that we can do this combination. Merge the insns and
2525 update the status of registers and LOG_LINKS. */
2528 rtx i3notes, i2notes, i1notes = 0;
2529 rtx i3links, i2links, i1links = 0;
2532 /* Compute which registers we expect to eliminate. newi2pat may be setting
2533 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2534 same as i3dest, in which case newi2pat may be setting i1dest. */
2535 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2536 || i2dest_in_i2src || i2dest_in_i1src
2538 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2539 || (newi2pat && reg_set_p (i1dest, newi2pat))
2542 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2544 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2545 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2547 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2549 /* Ensure that we do not have something that should not be shared but
2550 occurs multiple times in the new insns. Check this by first
2551 resetting all the `used' flags and then copying anything is shared. */
2553 reset_used_flags (i3notes);
2554 reset_used_flags (i2notes);
2555 reset_used_flags (i1notes);
2556 reset_used_flags (newpat);
2557 reset_used_flags (newi2pat);
2558 if (undobuf.other_insn)
2559 reset_used_flags (PATTERN (undobuf.other_insn));
2561 i3notes = copy_rtx_if_shared (i3notes);
2562 i2notes = copy_rtx_if_shared (i2notes);
2563 i1notes = copy_rtx_if_shared (i1notes);
2564 newpat = copy_rtx_if_shared (newpat);
2565 newi2pat = copy_rtx_if_shared (newi2pat);
2566 if (undobuf.other_insn)
2567 reset_used_flags (PATTERN (undobuf.other_insn));
2569 INSN_CODE (i3) = insn_code_number;
2570 PATTERN (i3) = newpat;
2572 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2574 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2576 reset_used_flags (call_usage);
2577 call_usage = copy_rtx (call_usage);
2580 replace_rtx (call_usage, i2dest, i2src);
2583 replace_rtx (call_usage, i1dest, i1src);
2585 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2588 if (undobuf.other_insn)
2589 INSN_CODE (undobuf.other_insn) = other_code_number;
2591 /* We had one special case above where I2 had more than one set and
2592 we replaced a destination of one of those sets with the destination
2593 of I3. In that case, we have to update LOG_LINKS of insns later
2594 in this basic block. Note that this (expensive) case is rare.
2596 Also, in this case, we must pretend that all REG_NOTEs for I2
2597 actually came from I3, so that REG_UNUSED notes from I2 will be
2598 properly handled. */
2600 if (i3_subst_into_i2)
2602 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2603 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2604 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2605 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2606 && ! find_reg_note (i2, REG_UNUSED,
2607 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2608 for (temp = NEXT_INSN (i2);
2609 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2610 || this_basic_block->head != temp);
2611 temp = NEXT_INSN (temp))
2612 if (temp != i3 && INSN_P (temp))
2613 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2614 if (XEXP (link, 0) == i2)
2615 XEXP (link, 0) = i3;
2620 while (XEXP (link, 1))
2621 link = XEXP (link, 1);
2622 XEXP (link, 1) = i2notes;
2636 INSN_CODE (i2) = i2_code_number;
2637 PATTERN (i2) = newi2pat;
2641 PUT_CODE (i2, NOTE);
2642 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2643 NOTE_SOURCE_FILE (i2) = 0;
2650 PUT_CODE (i1, NOTE);
2651 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2652 NOTE_SOURCE_FILE (i1) = 0;
2655 /* Get death notes for everything that is now used in either I3 or
2656 I2 and used to die in a previous insn. If we built two new
2657 patterns, move from I1 to I2 then I2 to I3 so that we get the
2658 proper movement on registers that I2 modifies. */
2662 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2663 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2666 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2669 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2671 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2674 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2677 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2680 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2683 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2684 know these are REG_UNUSED and want them to go to the desired insn,
2685 so we always pass it as i3. We have not counted the notes in
2686 reg_n_deaths yet, so we need to do so now. */
2688 if (newi2pat && new_i2_notes)
2690 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2691 if (GET_CODE (XEXP (temp, 0)) == REG)
2692 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2694 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2699 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2700 if (GET_CODE (XEXP (temp, 0)) == REG)
2701 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2703 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2706 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2707 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2708 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2709 in that case, it might delete I2. Similarly for I2 and I1.
2710 Show an additional death due to the REG_DEAD note we make here. If
2711 we discard it in distribute_notes, we will decrement it again. */
2715 if (GET_CODE (i3dest_killed) == REG)
2716 REG_N_DEATHS (REGNO (i3dest_killed))++;
2718 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2719 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2721 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2723 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2725 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2729 if (i2dest_in_i2src)
2731 if (GET_CODE (i2dest) == REG)
2732 REG_N_DEATHS (REGNO (i2dest))++;
2734 if (newi2pat && reg_set_p (i2dest, newi2pat))
2735 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2736 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2738 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2739 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2740 NULL_RTX, NULL_RTX);
2743 if (i1dest_in_i1src)
2745 if (GET_CODE (i1dest) == REG)
2746 REG_N_DEATHS (REGNO (i1dest))++;
2748 if (newi2pat && reg_set_p (i1dest, newi2pat))
2749 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2750 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2752 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2753 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2754 NULL_RTX, NULL_RTX);
2757 distribute_links (i3links);
2758 distribute_links (i2links);
2759 distribute_links (i1links);
2761 if (GET_CODE (i2dest) == REG)
2764 rtx i2_insn = 0, i2_val = 0, set;
2766 /* The insn that used to set this register doesn't exist, and
2767 this life of the register may not exist either. See if one of
2768 I3's links points to an insn that sets I2DEST. If it does,
2769 that is now the last known value for I2DEST. If we don't update
2770 this and I2 set the register to a value that depended on its old
2771 contents, we will get confused. If this insn is used, thing
2772 will be set correctly in combine_instructions. */
2774 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2775 if ((set = single_set (XEXP (link, 0))) != 0
2776 && rtx_equal_p (i2dest, SET_DEST (set)))
2777 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2779 record_value_for_reg (i2dest, i2_insn, i2_val);
2781 /* If the reg formerly set in I2 died only once and that was in I3,
2782 zero its use count so it won't make `reload' do any work. */
2784 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2785 && ! i2dest_in_i2src)
2787 regno = REGNO (i2dest);
2788 REG_N_SETS (regno)--;
2792 if (i1 && GET_CODE (i1dest) == REG)
2795 rtx i1_insn = 0, i1_val = 0, set;
2797 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2798 if ((set = single_set (XEXP (link, 0))) != 0
2799 && rtx_equal_p (i1dest, SET_DEST (set)))
2800 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2802 record_value_for_reg (i1dest, i1_insn, i1_val);
2804 regno = REGNO (i1dest);
2805 if (! added_sets_1 && ! i1dest_in_i1src)
2806 REG_N_SETS (regno)--;
2809 /* Update reg_nonzero_bits et al for any changes that may have been made
2810 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2811 important. Because newi2pat can affect nonzero_bits of newpat */
2813 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2814 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2816 /* Set new_direct_jump_p if a new return or simple jump instruction
2819 If I3 is now an unconditional jump, ensure that it has a
2820 BARRIER following it since it may have initially been a
2821 conditional jump. It may also be the last nonnote insn. */
2823 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2825 *new_direct_jump_p = 1;
2827 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2828 || GET_CODE (temp) != BARRIER)
2829 emit_barrier_after (i3);
2831 /* An NOOP jump does not need barrier, but it does need cleaning up
2833 if (GET_CODE (newpat) == SET
2834 && SET_SRC (newpat) == pc_rtx
2835 && SET_DEST (newpat) == pc_rtx)
2836 *new_direct_jump_p = 1;
2839 combine_successes++;
2842 /* Clear this here, so that subsequent get_last_value calls are not
2844 subst_prev_insn = NULL_RTX;
2846 if (added_links_insn
2847 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2848 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2849 return added_links_insn;
2851 return newi2pat ? i2 : i3;
2854 /* Undo all the modifications recorded in undobuf. */
2859 struct undo *undo, *next;
2861 for (undo = undobuf.undos; undo; undo = next)
2865 *undo->where.i = undo->old_contents.i;
2867 *undo->where.r = undo->old_contents.r;
2869 undo->next = undobuf.frees;
2870 undobuf.frees = undo;
2875 /* Clear this here, so that subsequent get_last_value calls are not
2877 subst_prev_insn = NULL_RTX;
2880 /* We've committed to accepting the changes we made. Move all
2881 of the undos to the free list. */
2886 struct undo *undo, *next;
2888 for (undo = undobuf.undos; undo; undo = next)
2891 undo->next = undobuf.frees;
2892 undobuf.frees = undo;
2898 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2899 where we have an arithmetic expression and return that point. LOC will
2902 try_combine will call this function to see if an insn can be split into
2906 find_split_point (loc, insn)
2911 enum rtx_code code = GET_CODE (x);
2913 unsigned HOST_WIDE_INT len = 0;
2914 HOST_WIDE_INT pos = 0;
2916 rtx inner = NULL_RTX;
2918 /* First special-case some codes. */
2922 #ifdef INSN_SCHEDULING
2923 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2925 if (GET_CODE (SUBREG_REG (x)) == MEM)
2928 return find_split_point (&SUBREG_REG (x), insn);
2932 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2933 using LO_SUM and HIGH. */
2934 if (GET_CODE (XEXP (x, 0)) == CONST
2935 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2938 gen_rtx_LO_SUM (Pmode,
2939 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2941 return &XEXP (XEXP (x, 0), 0);
2945 /* If we have a PLUS whose second operand is a constant and the
2946 address is not valid, perhaps will can split it up using
2947 the machine-specific way to split large constants. We use
2948 the first pseudo-reg (one of the virtual regs) as a placeholder;
2949 it will not remain in the result. */
2950 if (GET_CODE (XEXP (x, 0)) == PLUS
2951 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2952 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2954 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2955 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2958 /* This should have produced two insns, each of which sets our
2959 placeholder. If the source of the second is a valid address,
2960 we can make put both sources together and make a split point
2963 if (seq && XVECLEN (seq, 0) == 2
2964 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2965 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2966 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2967 && ! reg_mentioned_p (reg,
2968 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2969 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2970 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2971 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2972 && memory_address_p (GET_MODE (x),
2973 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2975 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2976 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2978 /* Replace the placeholder in SRC2 with SRC1. If we can
2979 find where in SRC2 it was placed, that can become our
2980 split point and we can replace this address with SRC2.
2981 Just try two obvious places. */
2983 src2 = replace_rtx (src2, reg, src1);
2985 if (XEXP (src2, 0) == src1)
2986 split = &XEXP (src2, 0);
2987 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2988 && XEXP (XEXP (src2, 0), 0) == src1)
2989 split = &XEXP (XEXP (src2, 0), 0);
2993 SUBST (XEXP (x, 0), src2);
2998 /* If that didn't work, perhaps the first operand is complex and
2999 needs to be computed separately, so make a split point there.
3000 This will occur on machines that just support REG + CONST
3001 and have a constant moved through some previous computation. */
3003 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3004 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3005 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3007 return &XEXP (XEXP (x, 0), 0);
3013 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3014 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3015 we need to put the operand into a register. So split at that
3018 if (SET_DEST (x) == cc0_rtx
3019 && GET_CODE (SET_SRC (x)) != COMPARE
3020 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3021 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3022 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3023 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3024 return &SET_SRC (x);
3027 /* See if we can split SET_SRC as it stands. */
3028 split = find_split_point (&SET_SRC (x), insn);
3029 if (split && split != &SET_SRC (x))
3032 /* See if we can split SET_DEST as it stands. */
3033 split = find_split_point (&SET_DEST (x), insn);
3034 if (split && split != &SET_DEST (x))
3037 /* See if this is a bitfield assignment with everything constant. If
3038 so, this is an IOR of an AND, so split it into that. */
3039 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3040 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3041 <= HOST_BITS_PER_WIDE_INT)
3042 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3043 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3044 && GET_CODE (SET_SRC (x)) == CONST_INT
3045 && ((INTVAL (XEXP (SET_DEST (x), 1))
3046 + INTVAL (XEXP (SET_DEST (x), 2)))
3047 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3048 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3050 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3051 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3052 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3053 rtx dest = XEXP (SET_DEST (x), 0);
3054 enum machine_mode mode = GET_MODE (dest);
3055 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3057 if (BITS_BIG_ENDIAN)
3058 pos = GET_MODE_BITSIZE (mode) - len - pos;
3062 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3065 gen_binary (IOR, mode,
3066 gen_binary (AND, mode, dest,
3067 gen_int_mode (~(mask << pos),
3069 GEN_INT (src << pos)));
3071 SUBST (SET_DEST (x), dest);
3073 split = find_split_point (&SET_SRC (x), insn);
3074 if (split && split != &SET_SRC (x))
3078 /* Otherwise, see if this is an operation that we can split into two.
3079 If so, try to split that. */
3080 code = GET_CODE (SET_SRC (x));
3085 /* If we are AND'ing with a large constant that is only a single
3086 bit and the result is only being used in a context where we
3087 need to know if it is zero or non-zero, replace it with a bit
3088 extraction. This will avoid the large constant, which might
3089 have taken more than one insn to make. If the constant were
3090 not a valid argument to the AND but took only one insn to make,
3091 this is no worse, but if it took more than one insn, it will
3094 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3095 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3096 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3097 && GET_CODE (SET_DEST (x)) == REG
3098 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3099 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3100 && XEXP (*split, 0) == SET_DEST (x)
3101 && XEXP (*split, 1) == const0_rtx)
3103 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3104 XEXP (SET_SRC (x), 0),
3105 pos, NULL_RTX, 1, 1, 0, 0);
3106 if (extraction != 0)
3108 SUBST (SET_SRC (x), extraction);
3109 return find_split_point (loc, insn);
3115 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3116 is known to be on, this can be converted into a NEG of a shift. */
3117 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3118 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3119 && 1 <= (pos = exact_log2
3120 (nonzero_bits (XEXP (SET_SRC (x), 0),
3121 GET_MODE (XEXP (SET_SRC (x), 0))))))
3123 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3127 gen_rtx_LSHIFTRT (mode,
3128 XEXP (SET_SRC (x), 0),
3131 split = find_split_point (&SET_SRC (x), insn);
3132 if (split && split != &SET_SRC (x))
3138 inner = XEXP (SET_SRC (x), 0);
3140 /* We can't optimize if either mode is a partial integer
3141 mode as we don't know how many bits are significant
3143 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3144 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3148 len = GET_MODE_BITSIZE (GET_MODE (inner));
3154 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3155 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3157 inner = XEXP (SET_SRC (x), 0);
3158 len = INTVAL (XEXP (SET_SRC (x), 1));
3159 pos = INTVAL (XEXP (SET_SRC (x), 2));
3161 if (BITS_BIG_ENDIAN)
3162 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3163 unsignedp = (code == ZERO_EXTRACT);
3171 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3173 enum machine_mode mode = GET_MODE (SET_SRC (x));
3175 /* For unsigned, we have a choice of a shift followed by an
3176 AND or two shifts. Use two shifts for field sizes where the
3177 constant might be too large. We assume here that we can
3178 always at least get 8-bit constants in an AND insn, which is
3179 true for every current RISC. */
3181 if (unsignedp && len <= 8)
3186 (mode, gen_lowpart_for_combine (mode, inner),
3188 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3190 split = find_split_point (&SET_SRC (x), insn);
3191 if (split && split != &SET_SRC (x))
3198 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3199 gen_rtx_ASHIFT (mode,
3200 gen_lowpart_for_combine (mode, inner),
3201 GEN_INT (GET_MODE_BITSIZE (mode)
3203 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3205 split = find_split_point (&SET_SRC (x), insn);
3206 if (split && split != &SET_SRC (x))
3211 /* See if this is a simple operation with a constant as the second
3212 operand. It might be that this constant is out of range and hence
3213 could be used as a split point. */
3214 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3215 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3216 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3217 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3218 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3219 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3220 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3222 return &XEXP (SET_SRC (x), 1);
3224 /* Finally, see if this is a simple operation with its first operand
3225 not in a register. The operation might require this operand in a
3226 register, so return it as a split point. We can always do this
3227 because if the first operand were another operation, we would have
3228 already found it as a split point. */
3229 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3230 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3231 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3232 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3233 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3234 return &XEXP (SET_SRC (x), 0);
3240 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3241 it is better to write this as (not (ior A B)) so we can split it.
3242 Similarly for IOR. */
3243 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3246 gen_rtx_NOT (GET_MODE (x),
3247 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3249 XEXP (XEXP (x, 0), 0),
3250 XEXP (XEXP (x, 1), 0))));
3251 return find_split_point (loc, insn);
3254 /* Many RISC machines have a large set of logical insns. If the
3255 second operand is a NOT, put it first so we will try to split the
3256 other operand first. */
3257 if (GET_CODE (XEXP (x, 1)) == NOT)
3259 rtx tem = XEXP (x, 0);
3260 SUBST (XEXP (x, 0), XEXP (x, 1));
3261 SUBST (XEXP (x, 1), tem);
3269 /* Otherwise, select our actions depending on our rtx class. */
3270 switch (GET_RTX_CLASS (code))
3272 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3274 split = find_split_point (&XEXP (x, 2), insn);
3277 /* ... fall through ... */
3281 split = find_split_point (&XEXP (x, 1), insn);
3284 /* ... fall through ... */
3286 /* Some machines have (and (shift ...) ...) insns. If X is not
3287 an AND, but XEXP (X, 0) is, use it as our split point. */
3288 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3289 return &XEXP (x, 0);
3291 split = find_split_point (&XEXP (x, 0), insn);
3297 /* Otherwise, we don't have a split point. */
3301 /* Throughout X, replace FROM with TO, and return the result.
3302 The result is TO if X is FROM;
3303 otherwise the result is X, but its contents may have been modified.
3304 If they were modified, a record was made in undobuf so that
3305 undo_all will (among other things) return X to its original state.
3307 If the number of changes necessary is too much to record to undo,
3308 the excess changes are not made, so the result is invalid.
3309 The changes already made can still be undone.
3310 undobuf.num_undo is incremented for such changes, so by testing that
3311 the caller can tell whether the result is valid.
3313 `n_occurrences' is incremented each time FROM is replaced.
3315 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3317 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3318 by copying if `n_occurrences' is non-zero. */
3321 subst (x, from, to, in_dest, unique_copy)
3326 enum rtx_code code = GET_CODE (x);
3327 enum machine_mode op0_mode = VOIDmode;
3332 /* Two expressions are equal if they are identical copies of a shared
3333 RTX or if they are both registers with the same register number
3336 #define COMBINE_RTX_EQUAL_P(X,Y) \
3338 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3339 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3341 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3344 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3347 /* If X and FROM are the same register but different modes, they will
3348 not have been seen as equal above. However, flow.c will make a
3349 LOG_LINKS entry for that case. If we do nothing, we will try to
3350 rerecognize our original insn and, when it succeeds, we will
3351 delete the feeding insn, which is incorrect.
3353 So force this insn not to match in this (rare) case. */
3354 if (! in_dest && code == REG && GET_CODE (from) == REG
3355 && REGNO (x) == REGNO (from))
3356 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3358 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3359 of which may contain things that can be combined. */
3360 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3363 /* It is possible to have a subexpression appear twice in the insn.
3364 Suppose that FROM is a register that appears within TO.
3365 Then, after that subexpression has been scanned once by `subst',
3366 the second time it is scanned, TO may be found. If we were
3367 to scan TO here, we would find FROM within it and create a
3368 self-referent rtl structure which is completely wrong. */
3369 if (COMBINE_RTX_EQUAL_P (x, to))
3372 /* Parallel asm_operands need special attention because all of the
3373 inputs are shared across the arms. Furthermore, unsharing the
3374 rtl results in recognition failures. Failure to handle this case
3375 specially can result in circular rtl.
3377 Solve this by doing a normal pass across the first entry of the
3378 parallel, and only processing the SET_DESTs of the subsequent
3381 if (code == PARALLEL
3382 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3383 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3385 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3387 /* If this substitution failed, this whole thing fails. */
3388 if (GET_CODE (new) == CLOBBER
3389 && XEXP (new, 0) == const0_rtx)
3392 SUBST (XVECEXP (x, 0, 0), new);
3394 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3396 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3398 if (GET_CODE (dest) != REG
3399 && GET_CODE (dest) != CC0
3400 && GET_CODE (dest) != PC)
3402 new = subst (dest, from, to, 0, unique_copy);
3404 /* If this substitution failed, this whole thing fails. */
3405 if (GET_CODE (new) == CLOBBER
3406 && XEXP (new, 0) == const0_rtx)
3409 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3415 len = GET_RTX_LENGTH (code);
3416 fmt = GET_RTX_FORMAT (code);
3418 /* We don't need to process a SET_DEST that is a register, CC0,
3419 or PC, so set up to skip this common case. All other cases
3420 where we want to suppress replacing something inside a
3421 SET_SRC are handled via the IN_DEST operand. */
3423 && (GET_CODE (SET_DEST (x)) == REG
3424 || GET_CODE (SET_DEST (x)) == CC0
3425 || GET_CODE (SET_DEST (x)) == PC))
3428 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3431 op0_mode = GET_MODE (XEXP (x, 0));
3433 for (i = 0; i < len; i++)
3438 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3440 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3442 new = (unique_copy && n_occurrences
3443 ? copy_rtx (to) : to);
3448 new = subst (XVECEXP (x, i, j), from, to, 0,
3451 /* If this substitution failed, this whole thing
3453 if (GET_CODE (new) == CLOBBER
3454 && XEXP (new, 0) == const0_rtx)
3458 SUBST (XVECEXP (x, i, j), new);
3461 else if (fmt[i] == 'e')
3463 /* If this is a register being set, ignore it. */
3466 && (code == SUBREG || code == STRICT_LOW_PART
3467 || code == ZERO_EXTRACT)
3469 && GET_CODE (new) == REG)
3472 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3474 /* In general, don't install a subreg involving two
3475 modes not tieable. It can worsen register
3476 allocation, and can even make invalid reload
3477 insns, since the reg inside may need to be copied
3478 from in the outside mode, and that may be invalid
3479 if it is an fp reg copied in integer mode.
3481 We allow two exceptions to this: It is valid if
3482 it is inside another SUBREG and the mode of that
3483 SUBREG and the mode of the inside of TO is
3484 tieable and it is valid if X is a SET that copies
3487 if (GET_CODE (to) == SUBREG
3488 && ! MODES_TIEABLE_P (GET_MODE (to),
3489 GET_MODE (SUBREG_REG (to)))
3490 && ! (code == SUBREG
3491 && MODES_TIEABLE_P (GET_MODE (x),
3492 GET_MODE (SUBREG_REG (to))))
3494 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3497 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3499 #ifdef CLASS_CANNOT_CHANGE_MODE
3501 && GET_CODE (to) == REG
3502 && REGNO (to) < FIRST_PSEUDO_REGISTER
3503 && (TEST_HARD_REG_BIT
3504 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3506 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3508 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3511 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3515 /* If we are in a SET_DEST, suppress most cases unless we
3516 have gone inside a MEM, in which case we want to
3517 simplify the address. We assume here that things that
3518 are actually part of the destination have their inner
3519 parts in the first expression. This is true for SUBREG,
3520 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3521 things aside from REG and MEM that should appear in a
3523 new = subst (XEXP (x, i), from, to,
3525 && (code == SUBREG || code == STRICT_LOW_PART
3526 || code == ZERO_EXTRACT))
3528 && i == 0), unique_copy);
3530 /* If we found that we will have to reject this combination,
3531 indicate that by returning the CLOBBER ourselves, rather than
3532 an expression containing it. This will speed things up as
3533 well as prevent accidents where two CLOBBERs are considered
3534 to be equal, thus producing an incorrect simplification. */
3536 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3539 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3541 if (VECTOR_MODE_P (GET_MODE (x)))
3542 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3544 x = simplify_subreg (GET_MODE (x), new,
3545 GET_MODE (SUBREG_REG (x)),
3550 else if (GET_CODE (new) == CONST_INT
3551 && GET_CODE (x) == ZERO_EXTEND)
3553 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3554 new, GET_MODE (XEXP (x, 0)));
3559 SUBST (XEXP (x, i), new);
3564 /* Try to simplify X. If the simplification changed the code, it is likely
3565 that further simplification will help, so loop, but limit the number
3566 of repetitions that will be performed. */
3568 for (i = 0; i < 4; i++)
3570 /* If X is sufficiently simple, don't bother trying to do anything
3572 if (code != CONST_INT && code != REG && code != CLOBBER)
3573 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3575 if (GET_CODE (x) == code)
3578 code = GET_CODE (x);
3580 /* We no longer know the original mode of operand 0 since we
3581 have changed the form of X) */
3582 op0_mode = VOIDmode;
3588 /* Simplify X, a piece of RTL. We just operate on the expression at the
3589 outer level; call `subst' to simplify recursively. Return the new
3592 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3593 will be the iteration even if an expression with a code different from
3594 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3597 combine_simplify_rtx (x, op0_mode, last, in_dest)
3599 enum machine_mode op0_mode;
3603 enum rtx_code code = GET_CODE (x);
3604 enum machine_mode mode = GET_MODE (x);
3609 /* If this is a commutative operation, put a constant last and a complex
3610 expression first. We don't need to do this for comparisons here. */
3611 if (GET_RTX_CLASS (code) == 'c'
3612 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3615 SUBST (XEXP (x, 0), XEXP (x, 1));
3616 SUBST (XEXP (x, 1), temp);
3619 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3620 sign extension of a PLUS with a constant, reverse the order of the sign
3621 extension and the addition. Note that this not the same as the original
3622 code, but overflow is undefined for signed values. Also note that the
3623 PLUS will have been partially moved "inside" the sign-extension, so that
3624 the first operand of X will really look like:
3625 (ashiftrt (plus (ashift A C4) C5) C4).
3627 (plus (ashiftrt (ashift A C4) C2) C4)
3628 and replace the first operand of X with that expression. Later parts
3629 of this function may simplify the expression further.
3631 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3632 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3633 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3635 We do this to simplify address expressions. */
3637 if ((code == PLUS || code == MINUS || code == MULT)
3638 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3639 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3640 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3641 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3642 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3643 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3644 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3645 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3646 XEXP (XEXP (XEXP (x, 0), 0), 1),
3647 XEXP (XEXP (x, 0), 1))) != 0)
3650 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3651 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3652 INTVAL (XEXP (XEXP (x, 0), 1)));
3654 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3655 INTVAL (XEXP (XEXP (x, 0), 1)));
3657 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3660 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3661 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3662 things. Check for cases where both arms are testing the same
3665 Don't do anything if all operands are very simple. */
3667 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3668 || GET_RTX_CLASS (code) == '<')
3669 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3670 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3671 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3673 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3674 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3675 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3677 || (GET_RTX_CLASS (code) == '1'
3678 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3679 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3680 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3683 rtx cond, true_rtx, false_rtx;
3685 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3687 /* If everything is a comparison, what we have is highly unlikely
3688 to be simpler, so don't use it. */
3689 && ! (GET_RTX_CLASS (code) == '<'
3690 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3691 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3693 rtx cop1 = const0_rtx;
3694 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3696 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3699 /* Simplify the alternative arms; this may collapse the true and
3700 false arms to store-flag values. */
3701 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3702 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3704 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3705 is unlikely to be simpler. */
3706 if (general_operand (true_rtx, VOIDmode)
3707 && general_operand (false_rtx, VOIDmode))
3709 /* Restarting if we generate a store-flag expression will cause
3710 us to loop. Just drop through in this case. */
3712 /* If the result values are STORE_FLAG_VALUE and zero, we can
3713 just make the comparison operation. */
3714 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3715 x = gen_binary (cond_code, mode, cond, cop1);
3716 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3717 && reverse_condition (cond_code) != UNKNOWN)
3718 x = gen_binary (reverse_condition (cond_code),
3721 /* Likewise, we can make the negate of a comparison operation
3722 if the result values are - STORE_FLAG_VALUE and zero. */
3723 else if (GET_CODE (true_rtx) == CONST_INT
3724 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3725 && false_rtx == const0_rtx)
3726 x = simplify_gen_unary (NEG, mode,
3727 gen_binary (cond_code, mode, cond,
3730 else if (GET_CODE (false_rtx) == CONST_INT
3731 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3732 && true_rtx == const0_rtx)
3733 x = simplify_gen_unary (NEG, mode,
3734 gen_binary (reverse_condition
3739 return gen_rtx_IF_THEN_ELSE (mode,
3740 gen_binary (cond_code, VOIDmode,
3742 true_rtx, false_rtx);
3744 code = GET_CODE (x);
3745 op0_mode = VOIDmode;
3750 /* Try to fold this expression in case we have constants that weren't
3753 switch (GET_RTX_CLASS (code))
3756 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3760 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3761 if (cmp_mode == VOIDmode)
3763 cmp_mode = GET_MODE (XEXP (x, 1));
3764 if (cmp_mode == VOIDmode)
3765 cmp_mode = op0_mode;
3767 temp = simplify_relational_operation (code, cmp_mode,
3768 XEXP (x, 0), XEXP (x, 1));
3770 #ifdef FLOAT_STORE_FLAG_VALUE
3771 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3773 if (temp == const0_rtx)
3774 temp = CONST0_RTX (mode);
3776 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3783 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3787 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3788 XEXP (x, 1), XEXP (x, 2));
3795 code = GET_CODE (temp);
3796 op0_mode = VOIDmode;
3797 mode = GET_MODE (temp);
3800 /* First see if we can apply the inverse distributive law. */
3801 if (code == PLUS || code == MINUS
3802 || code == AND || code == IOR || code == XOR)
3804 x = apply_distributive_law (x);
3805 code = GET_CODE (x);
3806 op0_mode = VOIDmode;
3809 /* If CODE is an associative operation not otherwise handled, see if we
3810 can associate some operands. This can win if they are constants or
3811 if they are logically related (i.e. (a & b) & a). */
3812 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3813 || code == AND || code == IOR || code == XOR
3814 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3815 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3816 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3818 if (GET_CODE (XEXP (x, 0)) == code)
3820 rtx other = XEXP (XEXP (x, 0), 0);
3821 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3822 rtx inner_op1 = XEXP (x, 1);
3825 /* Make sure we pass the constant operand if any as the second
3826 one if this is a commutative operation. */
3827 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3829 rtx tem = inner_op0;
3830 inner_op0 = inner_op1;
3833 inner = simplify_binary_operation (code == MINUS ? PLUS
3834 : code == DIV ? MULT
3836 mode, inner_op0, inner_op1);
3838 /* For commutative operations, try the other pair if that one
3840 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3842 other = XEXP (XEXP (x, 0), 1);
3843 inner = simplify_binary_operation (code, mode,
3844 XEXP (XEXP (x, 0), 0),
3849 return gen_binary (code, mode, other, inner);
3853 /* A little bit of algebraic simplification here. */
3857 /* Ensure that our address has any ASHIFTs converted to MULT in case
3858 address-recognizing predicates are called later. */
3859 temp = make_compound_operation (XEXP (x, 0), MEM);
3860 SUBST (XEXP (x, 0), temp);
3864 if (op0_mode == VOIDmode)
3865 op0_mode = GET_MODE (SUBREG_REG (x));
3867 /* simplify_subreg can't use gen_lowpart_for_combine. */
3868 if (CONSTANT_P (SUBREG_REG (x))
3869 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3870 /* Don't call gen_lowpart_for_combine if the inner mode
3871 is VOIDmode and we cannot simplify it, as SUBREG without
3872 inner mode is invalid. */
3873 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3874 || gen_lowpart_common (mode, SUBREG_REG (x))))
3875 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3877 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3881 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3887 /* Don't change the mode of the MEM if that would change the meaning
3889 if (GET_CODE (SUBREG_REG (x)) == MEM
3890 && (MEM_VOLATILE_P (SUBREG_REG (x))
3891 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3892 return gen_rtx_CLOBBER (mode, const0_rtx);
3894 /* Note that we cannot do any narrowing for non-constants since
3895 we might have been counting on using the fact that some bits were
3896 zero. We now do this in the SET. */
3901 /* (not (plus X -1)) can become (neg X). */
3902 if (GET_CODE (XEXP (x, 0)) == PLUS
3903 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3904 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3906 /* Similarly, (not (neg X)) is (plus X -1). */
3907 if (GET_CODE (XEXP (x, 0)) == NEG)
3908 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3910 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3911 if (GET_CODE (XEXP (x, 0)) == XOR
3912 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3913 && (temp = simplify_unary_operation (NOT, mode,
3914 XEXP (XEXP (x, 0), 1),
3916 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3918 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3919 other than 1, but that is not valid. We could do a similar
3920 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3921 but this doesn't seem common enough to bother with. */
3922 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3923 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3924 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3926 XEXP (XEXP (x, 0), 1));
3928 if (GET_CODE (XEXP (x, 0)) == SUBREG
3929 && subreg_lowpart_p (XEXP (x, 0))
3930 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3931 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3932 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3933 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3935 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3937 x = gen_rtx_ROTATE (inner_mode,
3938 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3940 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3941 return gen_lowpart_for_combine (mode, x);
3944 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3945 reversing the comparison code if valid. */
3946 if (STORE_FLAG_VALUE == -1
3947 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3948 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3949 XEXP (XEXP (x, 0), 1))))
3952 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3953 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3954 perform the above simplification. */
3956 if (STORE_FLAG_VALUE == -1
3957 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3958 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3959 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3960 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3962 /* Apply De Morgan's laws to reduce number of patterns for machines
3963 with negating logical insns (and-not, nand, etc.). If result has
3964 only one NOT, put it first, since that is how the patterns are
3967 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3969 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3970 enum machine_mode op_mode;
3972 op_mode = GET_MODE (in1);
3973 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3975 op_mode = GET_MODE (in2);
3976 if (op_mode == VOIDmode)
3978 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3980 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3983 in2 = in1; in1 = tem;
3986 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3992 /* (neg (plus X 1)) can become (not X). */
3993 if (GET_CODE (XEXP (x, 0)) == PLUS
3994 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3995 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3997 /* Similarly, (neg (not X)) is (plus X 1). */
3998 if (GET_CODE (XEXP (x, 0)) == NOT)
3999 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
4001 /* (neg (minus X Y)) can become (minus Y X). This transformation
4002 isn't safe for modes with signed zeros, since if X and Y are
4003 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4004 mode is towards +infinity (or -infinity) then the two expressions
4005 will be rounded differently. */
4006 if (GET_CODE (XEXP (x, 0)) == MINUS
4007 && !HONOR_SIGNED_ZEROS (mode)
4008 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4009 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4010 XEXP (XEXP (x, 0), 0));
4012 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4013 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4014 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4015 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4017 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4018 if we can then eliminate the NEG (e.g.,
4019 if the operand is a constant). */
4021 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4023 temp = simplify_unary_operation (NEG, mode,
4024 XEXP (XEXP (x, 0), 0), mode);
4026 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4029 temp = expand_compound_operation (XEXP (x, 0));
4031 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4032 replaced by (lshiftrt X C). This will convert
4033 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4035 if (GET_CODE (temp) == ASHIFTRT
4036 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4037 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4038 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4039 INTVAL (XEXP (temp, 1)));
4041 /* If X has only a single bit that might be nonzero, say, bit I, convert
4042 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4043 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4044 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4045 or a SUBREG of one since we'd be making the expression more
4046 complex if it was just a register. */
4048 if (GET_CODE (temp) != REG
4049 && ! (GET_CODE (temp) == SUBREG
4050 && GET_CODE (SUBREG_REG (temp)) == REG)
4051 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4053 rtx temp1 = simplify_shift_const
4054 (NULL_RTX, ASHIFTRT, mode,
4055 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4056 GET_MODE_BITSIZE (mode) - 1 - i),
4057 GET_MODE_BITSIZE (mode) - 1 - i);
4059 /* If all we did was surround TEMP with the two shifts, we
4060 haven't improved anything, so don't use it. Otherwise,
4061 we are better off with TEMP1. */
4062 if (GET_CODE (temp1) != ASHIFTRT
4063 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4064 || XEXP (XEXP (temp1, 0), 0) != temp)
4070 /* We can't handle truncation to a partial integer mode here
4071 because we don't know the real bitsize of the partial
4073 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4076 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4077 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4078 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4080 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4081 GET_MODE_MASK (mode), NULL_RTX, 0));
4083 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4084 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4085 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4086 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4087 return XEXP (XEXP (x, 0), 0);
4089 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4090 (OP:SI foo:SI) if OP is NEG or ABS. */
4091 if ((GET_CODE (XEXP (x, 0)) == ABS
4092 || GET_CODE (XEXP (x, 0)) == NEG)
4093 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4094 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4095 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4096 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4097 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4099 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4101 if (GET_CODE (XEXP (x, 0)) == SUBREG
4102 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4103 && subreg_lowpart_p (XEXP (x, 0)))
4104 return SUBREG_REG (XEXP (x, 0));
4106 /* If we know that the value is already truncated, we can
4107 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4108 is nonzero for the corresponding modes. But don't do this
4109 for an (LSHIFTRT (MULT ...)) since this will cause problems
4110 with the umulXi3_highpart patterns. */
4111 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4112 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4113 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4114 >= GET_MODE_BITSIZE (mode) + 1
4115 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4116 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4117 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4119 /* A truncate of a comparison can be replaced with a subreg if
4120 STORE_FLAG_VALUE permits. This is like the previous test,
4121 but it works even if the comparison is done in a mode larger
4122 than HOST_BITS_PER_WIDE_INT. */
4123 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4124 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4125 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4126 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4128 /* Similarly, a truncate of a register whose value is a
4129 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4131 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4132 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4133 && (temp = get_last_value (XEXP (x, 0)))
4134 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4135 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4139 case FLOAT_TRUNCATE:
4140 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4141 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4142 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4143 return XEXP (XEXP (x, 0), 0);
4145 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4146 (OP:SF foo:SF) if OP is NEG or ABS. */
4147 if ((GET_CODE (XEXP (x, 0)) == ABS
4148 || GET_CODE (XEXP (x, 0)) == NEG)
4149 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4150 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4151 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4152 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4154 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4155 is (float_truncate:SF x). */
4156 if (GET_CODE (XEXP (x, 0)) == SUBREG
4157 && subreg_lowpart_p (XEXP (x, 0))
4158 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4159 return SUBREG_REG (XEXP (x, 0));
4164 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4165 using cc0, in which case we want to leave it as a COMPARE
4166 so we can distinguish it from a register-register-copy. */
4167 if (XEXP (x, 1) == const0_rtx)
4170 /* x - 0 is the same as x unless x's mode has signed zeros and
4171 allows rounding towards -infinity. Under those conditions,
4173 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4174 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4175 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4181 /* (const (const X)) can become (const X). Do it this way rather than
4182 returning the inner CONST since CONST can be shared with a
4184 if (GET_CODE (XEXP (x, 0)) == CONST)
4185 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4190 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4191 can add in an offset. find_split_point will split this address up
4192 again if it doesn't match. */
4193 if (GET_CODE (XEXP (x, 0)) == HIGH
4194 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4200 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4201 outermost. That's because that's the way indexed addresses are
4202 supposed to appear. This code used to check many more cases, but
4203 they are now checked elsewhere. */
4204 if (GET_CODE (XEXP (x, 0)) == PLUS
4205 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4206 return gen_binary (PLUS, mode,
4207 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4209 XEXP (XEXP (x, 0), 1));
4211 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4212 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4213 bit-field and can be replaced by either a sign_extend or a
4214 sign_extract. The `and' may be a zero_extend and the two
4215 <c>, -<c> constants may be reversed. */
4216 if (GET_CODE (XEXP (x, 0)) == XOR
4217 && GET_CODE (XEXP (x, 1)) == CONST_INT
4218 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4219 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4220 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4221 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4222 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4223 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4224 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4225 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4226 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4227 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4228 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4229 == (unsigned int) i + 1))))
4230 return simplify_shift_const
4231 (NULL_RTX, ASHIFTRT, mode,
4232 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4233 XEXP (XEXP (XEXP (x, 0), 0), 0),
4234 GET_MODE_BITSIZE (mode) - (i + 1)),
4235 GET_MODE_BITSIZE (mode) - (i + 1));
4237 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4238 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4239 is 1. This produces better code than the alternative immediately
4241 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4242 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4243 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4244 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4245 XEXP (XEXP (x, 0), 0),
4246 XEXP (XEXP (x, 0), 1))))
4248 simplify_gen_unary (NEG, mode, reversed, mode);
4250 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4251 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4252 the bitsize of the mode - 1. This allows simplification of
4253 "a = (b & 8) == 0;" */
4254 if (XEXP (x, 1) == constm1_rtx
4255 && GET_CODE (XEXP (x, 0)) != REG
4256 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4257 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4258 && nonzero_bits (XEXP (x, 0), mode) == 1)
4259 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4260 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4261 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4262 GET_MODE_BITSIZE (mode) - 1),
4263 GET_MODE_BITSIZE (mode) - 1);
4265 /* If we are adding two things that have no bits in common, convert
4266 the addition into an IOR. This will often be further simplified,
4267 for example in cases like ((a & 1) + (a & 2)), which can
4270 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4271 && (nonzero_bits (XEXP (x, 0), mode)
4272 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4274 /* Try to simplify the expression further. */
4275 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4276 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4278 /* If we could, great. If not, do not go ahead with the IOR
4279 replacement, since PLUS appears in many special purpose
4280 address arithmetic instructions. */
4281 if (GET_CODE (temp) != CLOBBER && temp != tor)
4287 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4288 by reversing the comparison code if valid. */
4289 if (STORE_FLAG_VALUE == 1
4290 && XEXP (x, 0) == const1_rtx
4291 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4292 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4293 XEXP (XEXP (x, 1), 0),
4294 XEXP (XEXP (x, 1), 1))))
4297 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4298 (and <foo> (const_int pow2-1)) */
4299 if (GET_CODE (XEXP (x, 1)) == AND
4300 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4301 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4302 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4303 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4304 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4306 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4308 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4309 return gen_binary (MINUS, mode,
4310 gen_binary (MINUS, mode, XEXP (x, 0),
4311 XEXP (XEXP (x, 1), 0)),
4312 XEXP (XEXP (x, 1), 1));
4316 /* If we have (mult (plus A B) C), apply the distributive law and then
4317 the inverse distributive law to see if things simplify. This
4318 occurs mostly in addresses, often when unrolling loops. */
4320 if (GET_CODE (XEXP (x, 0)) == PLUS)
4322 x = apply_distributive_law
4323 (gen_binary (PLUS, mode,
4324 gen_binary (MULT, mode,
4325 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4326 gen_binary (MULT, mode,
4327 XEXP (XEXP (x, 0), 1),
4328 copy_rtx (XEXP (x, 1)))));
4330 if (GET_CODE (x) != MULT)
4333 /* Try simplify a*(b/c) as (a*b)/c. */
4334 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4335 && GET_CODE (XEXP (x, 0)) == DIV)
4337 rtx tem = simplify_binary_operation (MULT, mode,
4338 XEXP (XEXP (x, 0), 0),
4341 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4346 /* If this is a divide by a power of two, treat it as a shift if
4347 its first operand is a shift. */
4348 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4349 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4350 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4351 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4352 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4353 || GET_CODE (XEXP (x, 0)) == ROTATE
4354 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4355 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4359 case GT: case GTU: case GE: case GEU:
4360 case LT: case LTU: case LE: case LEU:
4361 case UNEQ: case LTGT:
4362 case UNGT: case UNGE:
4363 case UNLT: case UNLE:
4364 case UNORDERED: case ORDERED:
4365 /* If the first operand is a condition code, we can't do anything
4367 if (GET_CODE (XEXP (x, 0)) == COMPARE
4368 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4370 && XEXP (x, 0) != cc0_rtx
4374 rtx op0 = XEXP (x, 0);
4375 rtx op1 = XEXP (x, 1);
4376 enum rtx_code new_code;
4378 if (GET_CODE (op0) == COMPARE)
4379 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4381 /* Simplify our comparison, if possible. */
4382 new_code = simplify_comparison (code, &op0, &op1);
4384 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4385 if only the low-order bit is possibly nonzero in X (such as when
4386 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4387 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4388 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4391 Remove any ZERO_EXTRACT we made when thinking this was a
4392 comparison. It may now be simpler to use, e.g., an AND. If a
4393 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4394 the call to make_compound_operation in the SET case. */
4396 if (STORE_FLAG_VALUE == 1
4397 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4398 && op1 == const0_rtx
4399 && mode == GET_MODE (op0)
4400 && nonzero_bits (op0, mode) == 1)
4401 return gen_lowpart_for_combine (mode,
4402 expand_compound_operation (op0));
4404 else if (STORE_FLAG_VALUE == 1
4405 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4406 && op1 == const0_rtx
4407 && mode == GET_MODE (op0)
4408 && (num_sign_bit_copies (op0, mode)
4409 == GET_MODE_BITSIZE (mode)))
4411 op0 = expand_compound_operation (op0);
4412 return simplify_gen_unary (NEG, mode,
4413 gen_lowpart_for_combine (mode, op0),
4417 else if (STORE_FLAG_VALUE == 1
4418 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4419 && op1 == const0_rtx
4420 && mode == GET_MODE (op0)
4421 && nonzero_bits (op0, mode) == 1)
4423 op0 = expand_compound_operation (op0);
4424 return gen_binary (XOR, mode,
4425 gen_lowpart_for_combine (mode, op0),
4429 else if (STORE_FLAG_VALUE == 1
4430 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4431 && op1 == const0_rtx
4432 && mode == GET_MODE (op0)
4433 && (num_sign_bit_copies (op0, mode)
4434 == GET_MODE_BITSIZE (mode)))
4436 op0 = expand_compound_operation (op0);
4437 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4440 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4442 if (STORE_FLAG_VALUE == -1
4443 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4444 && op1 == const0_rtx
4445 && (num_sign_bit_copies (op0, mode)
4446 == GET_MODE_BITSIZE (mode)))
4447 return gen_lowpart_for_combine (mode,
4448 expand_compound_operation (op0));
4450 else if (STORE_FLAG_VALUE == -1
4451 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4452 && op1 == const0_rtx
4453 && mode == GET_MODE (op0)
4454 && nonzero_bits (op0, mode) == 1)
4456 op0 = expand_compound_operation (op0);
4457 return simplify_gen_unary (NEG, mode,
4458 gen_lowpart_for_combine (mode, op0),
4462 else if (STORE_FLAG_VALUE == -1
4463 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4464 && op1 == const0_rtx
4465 && mode == GET_MODE (op0)
4466 && (num_sign_bit_copies (op0, mode)
4467 == GET_MODE_BITSIZE (mode)))
4469 op0 = expand_compound_operation (op0);
4470 return simplify_gen_unary (NOT, mode,
4471 gen_lowpart_for_combine (mode, op0),
4475 /* If X is 0/1, (eq X 0) is X-1. */
4476 else if (STORE_FLAG_VALUE == -1
4477 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4478 && op1 == const0_rtx
4479 && mode == GET_MODE (op0)
4480 && nonzero_bits (op0, mode) == 1)
4482 op0 = expand_compound_operation (op0);
4483 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4486 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4487 one bit that might be nonzero, we can convert (ne x 0) to
4488 (ashift x c) where C puts the bit in the sign bit. Remove any
4489 AND with STORE_FLAG_VALUE when we are done, since we are only
4490 going to test the sign bit. */
4491 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4492 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4493 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4494 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4495 && op1 == const0_rtx
4496 && mode == GET_MODE (op0)
4497 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4499 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4500 expand_compound_operation (op0),
4501 GET_MODE_BITSIZE (mode) - 1 - i);
4502 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4508 /* If the code changed, return a whole new comparison. */
4509 if (new_code != code)
4510 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4512 /* Otherwise, keep this operation, but maybe change its operands.
4513 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4514 SUBST (XEXP (x, 0), op0);
4515 SUBST (XEXP (x, 1), op1);
4520 return simplify_if_then_else (x);
4526 /* If we are processing SET_DEST, we are done. */
4530 return expand_compound_operation (x);
4533 return simplify_set (x);
4538 return simplify_logical (x, last);
4541 /* (abs (neg <foo>)) -> (abs <foo>) */
4542 if (GET_CODE (XEXP (x, 0)) == NEG)
4543 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4545 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4547 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4550 /* If operand is something known to be positive, ignore the ABS. */
4551 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4552 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4553 <= HOST_BITS_PER_WIDE_INT)
4554 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4555 & ((HOST_WIDE_INT) 1
4556 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4560 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4561 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4562 return gen_rtx_NEG (mode, XEXP (x, 0));
4567 /* (ffs (*_extend <X>)) = (ffs <X>) */
4568 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4569 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4570 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4574 /* (float (sign_extend <X>)) = (float <X>). */
4575 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4576 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4584 /* If this is a shift by a constant amount, simplify it. */
4585 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4586 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4587 INTVAL (XEXP (x, 1)));
4589 #ifdef SHIFT_COUNT_TRUNCATED
4590 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4592 force_to_mode (XEXP (x, 1), GET_MODE (x),
4594 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4603 rtx op0 = XEXP (x, 0);
4604 rtx op1 = XEXP (x, 1);
4607 if (GET_CODE (op1) != PARALLEL)
4609 len = XVECLEN (op1, 0);
4611 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4612 && GET_CODE (op0) == VEC_CONCAT)
4614 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4616 /* Try to find the element in the VEC_CONCAT. */
4619 if (GET_MODE (op0) == GET_MODE (x))
4621 if (GET_CODE (op0) == VEC_CONCAT)
4623 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4624 if (op0_size < offset)
4625 op0 = XEXP (op0, 0);
4629 op0 = XEXP (op0, 1);
4647 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4650 simplify_if_then_else (x)
4653 enum machine_mode mode = GET_MODE (x);
4654 rtx cond = XEXP (x, 0);
4655 rtx true_rtx = XEXP (x, 1);
4656 rtx false_rtx = XEXP (x, 2);
4657 enum rtx_code true_code = GET_CODE (cond);
4658 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4661 enum rtx_code false_code;
4664 /* Simplify storing of the truth value. */
4665 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4666 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4668 /* Also when the truth value has to be reversed. */
4670 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4671 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4675 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4676 in it is being compared against certain values. Get the true and false
4677 comparisons and see if that says anything about the value of each arm. */
4680 && ((false_code = combine_reversed_comparison_code (cond))
4682 && GET_CODE (XEXP (cond, 0)) == REG)
4685 rtx from = XEXP (cond, 0);
4686 rtx true_val = XEXP (cond, 1);
4687 rtx false_val = true_val;
4690 /* If FALSE_CODE is EQ, swap the codes and arms. */
4692 if (false_code == EQ)
4694 swapped = 1, true_code = EQ, false_code = NE;
4695 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4698 /* If we are comparing against zero and the expression being tested has
4699 only a single bit that might be nonzero, that is its value when it is
4700 not equal to zero. Similarly if it is known to be -1 or 0. */
4702 if (true_code == EQ && true_val == const0_rtx
4703 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4704 false_code = EQ, false_val = GEN_INT (nzb);
4705 else if (true_code == EQ && true_val == const0_rtx
4706 && (num_sign_bit_copies (from, GET_MODE (from))
4707 == GET_MODE_BITSIZE (GET_MODE (from))))
4708 false_code = EQ, false_val = constm1_rtx;
4710 /* Now simplify an arm if we know the value of the register in the
4711 branch and it is used in the arm. Be careful due to the potential
4712 of locally-shared RTL. */
4714 if (reg_mentioned_p (from, true_rtx))
4715 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4717 pc_rtx, pc_rtx, 0, 0);
4718 if (reg_mentioned_p (from, false_rtx))
4719 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4721 pc_rtx, pc_rtx, 0, 0);
4723 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4724 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4726 true_rtx = XEXP (x, 1);
4727 false_rtx = XEXP (x, 2);
4728 true_code = GET_CODE (cond);
4731 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4732 reversed, do so to avoid needing two sets of patterns for
4733 subtract-and-branch insns. Similarly if we have a constant in the true
4734 arm, the false arm is the same as the first operand of the comparison, or
4735 the false arm is more complicated than the true arm. */
4738 && combine_reversed_comparison_code (cond) != UNKNOWN
4739 && (true_rtx == pc_rtx
4740 || (CONSTANT_P (true_rtx)
4741 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4742 || true_rtx == const0_rtx
4743 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4744 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4745 || (GET_CODE (true_rtx) == SUBREG
4746 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4747 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4748 || reg_mentioned_p (true_rtx, false_rtx)
4749 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4751 true_code = reversed_comparison_code (cond, NULL);
4753 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4756 SUBST (XEXP (x, 1), false_rtx);
4757 SUBST (XEXP (x, 2), true_rtx);
4759 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4762 /* It is possible that the conditional has been simplified out. */
4763 true_code = GET_CODE (cond);
4764 comparison_p = GET_RTX_CLASS (true_code) == '<';
4767 /* If the two arms are identical, we don't need the comparison. */
4769 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4772 /* Convert a == b ? b : a to "a". */
4773 if (true_code == EQ && ! side_effects_p (cond)
4774 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4775 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4776 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4778 else if (true_code == NE && ! side_effects_p (cond)
4779 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4780 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4781 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4784 /* Look for cases where we have (abs x) or (neg (abs X)). */
4786 if (GET_MODE_CLASS (mode) == MODE_INT
4787 && GET_CODE (false_rtx) == NEG
4788 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4790 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4791 && ! side_effects_p (true_rtx))
4796 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4800 simplify_gen_unary (NEG, mode,
4801 simplify_gen_unary (ABS, mode, true_rtx, mode),
4807 /* Look for MIN or MAX. */
4809 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4811 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4812 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4813 && ! side_effects_p (cond))
4818 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4821 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4824 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4827 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4832 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4833 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4834 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4835 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4836 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4837 neither 1 or -1, but it isn't worth checking for. */
4839 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4840 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4842 rtx t = make_compound_operation (true_rtx, SET);
4843 rtx f = make_compound_operation (false_rtx, SET);
4844 rtx cond_op0 = XEXP (cond, 0);
4845 rtx cond_op1 = XEXP (cond, 1);
4846 enum rtx_code op = NIL, extend_op = NIL;
4847 enum machine_mode m = mode;
4848 rtx z = 0, c1 = NULL_RTX;
4850 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4851 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4852 || GET_CODE (t) == ASHIFT
4853 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4854 && rtx_equal_p (XEXP (t, 0), f))
4855 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4857 /* If an identity-zero op is commutative, check whether there
4858 would be a match if we swapped the operands. */
4859 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4860 || GET_CODE (t) == XOR)
4861 && rtx_equal_p (XEXP (t, 1), f))
4862 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4863 else if (GET_CODE (t) == SIGN_EXTEND
4864 && (GET_CODE (XEXP (t, 0)) == PLUS
4865 || GET_CODE (XEXP (t, 0)) == MINUS
4866 || GET_CODE (XEXP (t, 0)) == IOR
4867 || GET_CODE (XEXP (t, 0)) == XOR
4868 || GET_CODE (XEXP (t, 0)) == ASHIFT
4869 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4870 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4871 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4872 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4873 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4874 && (num_sign_bit_copies (f, GET_MODE (f))
4875 > (GET_MODE_BITSIZE (mode)
4876 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4878 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4879 extend_op = SIGN_EXTEND;
4880 m = GET_MODE (XEXP (t, 0));
4882 else if (GET_CODE (t) == SIGN_EXTEND
4883 && (GET_CODE (XEXP (t, 0)) == PLUS
4884 || GET_CODE (XEXP (t, 0)) == IOR
4885 || GET_CODE (XEXP (t, 0)) == XOR)
4886 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4887 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4888 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4889 && (num_sign_bit_copies (f, GET_MODE (f))
4890 > (GET_MODE_BITSIZE (mode)
4891 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4893 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4894 extend_op = SIGN_EXTEND;
4895 m = GET_MODE (XEXP (t, 0));
4897 else if (GET_CODE (t) == ZERO_EXTEND
4898 && (GET_CODE (XEXP (t, 0)) == PLUS
4899 || GET_CODE (XEXP (t, 0)) == MINUS
4900 || GET_CODE (XEXP (t, 0)) == IOR
4901 || GET_CODE (XEXP (t, 0)) == XOR
4902 || GET_CODE (XEXP (t, 0)) == ASHIFT
4903 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4904 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4905 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4906 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4907 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4908 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4909 && ((nonzero_bits (f, GET_MODE (f))
4910 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4913 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4914 extend_op = ZERO_EXTEND;
4915 m = GET_MODE (XEXP (t, 0));
4917 else if (GET_CODE (t) == ZERO_EXTEND
4918 && (GET_CODE (XEXP (t, 0)) == PLUS
4919 || GET_CODE (XEXP (t, 0)) == IOR
4920 || GET_CODE (XEXP (t, 0)) == XOR)
4921 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4922 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4923 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4924 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4925 && ((nonzero_bits (f, GET_MODE (f))
4926 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4929 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4930 extend_op = ZERO_EXTEND;
4931 m = GET_MODE (XEXP (t, 0));
4936 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4937 pc_rtx, pc_rtx, 0, 0);
4938 temp = gen_binary (MULT, m, temp,
4939 gen_binary (MULT, m, c1, const_true_rtx));
4940 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4941 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4943 if (extend_op != NIL)
4944 temp = simplify_gen_unary (extend_op, mode, temp, m);
4950 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4951 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4952 negation of a single bit, we can convert this operation to a shift. We
4953 can actually do this more generally, but it doesn't seem worth it. */
4955 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4956 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4957 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4958 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4959 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4960 == GET_MODE_BITSIZE (mode))
4961 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4963 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4964 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4969 /* Simplify X, a SET expression. Return the new expression. */
4975 rtx src = SET_SRC (x);
4976 rtx dest = SET_DEST (x);
4977 enum machine_mode mode
4978 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4982 /* (set (pc) (return)) gets written as (return). */
4983 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4986 /* Now that we know for sure which bits of SRC we are using, see if we can
4987 simplify the expression for the object knowing that we only need the
4990 if (GET_MODE_CLASS (mode) == MODE_INT)
4992 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4993 SUBST (SET_SRC (x), src);
4996 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4997 the comparison result and try to simplify it unless we already have used
4998 undobuf.other_insn. */
4999 if ((GET_CODE (src) == COMPARE
5004 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5005 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5006 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5007 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5009 enum rtx_code old_code = GET_CODE (*cc_use);
5010 enum rtx_code new_code;
5012 int other_changed = 0;
5013 enum machine_mode compare_mode = GET_MODE (dest);
5015 if (GET_CODE (src) == COMPARE)
5016 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5018 op0 = src, op1 = const0_rtx;
5020 /* Simplify our comparison, if possible. */
5021 new_code = simplify_comparison (old_code, &op0, &op1);
5023 #ifdef EXTRA_CC_MODES
5024 /* If this machine has CC modes other than CCmode, check to see if we
5025 need to use a different CC mode here. */
5026 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5027 #endif /* EXTRA_CC_MODES */
5029 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5030 /* If the mode changed, we have to change SET_DEST, the mode in the
5031 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5032 a hard register, just build new versions with the proper mode. If it
5033 is a pseudo, we lose unless it is only time we set the pseudo, in
5034 which case we can safely change its mode. */
5035 if (compare_mode != GET_MODE (dest))
5037 unsigned int regno = REGNO (dest);
5038 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5040 if (regno < FIRST_PSEUDO_REGISTER
5041 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5043 if (regno >= FIRST_PSEUDO_REGISTER)
5044 SUBST (regno_reg_rtx[regno], new_dest);
5046 SUBST (SET_DEST (x), new_dest);
5047 SUBST (XEXP (*cc_use, 0), new_dest);
5055 /* If the code changed, we have to build a new comparison in
5056 undobuf.other_insn. */
5057 if (new_code != old_code)
5059 unsigned HOST_WIDE_INT mask;
5061 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5064 /* If the only change we made was to change an EQ into an NE or
5065 vice versa, OP0 has only one bit that might be nonzero, and OP1
5066 is zero, check if changing the user of the condition code will
5067 produce a valid insn. If it won't, we can keep the original code
5068 in that insn by surrounding our operation with an XOR. */
5070 if (((old_code == NE && new_code == EQ)
5071 || (old_code == EQ && new_code == NE))
5072 && ! other_changed && op1 == const0_rtx
5073 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5074 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5076 rtx pat = PATTERN (other_insn), note = 0;
5078 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5079 && ! check_asm_operands (pat)))
5081 PUT_CODE (*cc_use, old_code);
5084 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5092 undobuf.other_insn = other_insn;
5095 /* If we are now comparing against zero, change our source if
5096 needed. If we do not use cc0, we always have a COMPARE. */
5097 if (op1 == const0_rtx && dest == cc0_rtx)
5099 SUBST (SET_SRC (x), op0);
5105 /* Otherwise, if we didn't previously have a COMPARE in the
5106 correct mode, we need one. */
5107 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5109 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5114 /* Otherwise, update the COMPARE if needed. */
5115 SUBST (XEXP (src, 0), op0);
5116 SUBST (XEXP (src, 1), op1);
5121 /* Get SET_SRC in a form where we have placed back any
5122 compound expressions. Then do the checks below. */
5123 src = make_compound_operation (src, SET);
5124 SUBST (SET_SRC (x), src);
5127 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5128 and X being a REG or (subreg (reg)), we may be able to convert this to
5129 (set (subreg:m2 x) (op)).
5131 We can always do this if M1 is narrower than M2 because that means that
5132 we only care about the low bits of the result.
5134 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5135 perform a narrower operation than requested since the high-order bits will
5136 be undefined. On machine where it is defined, this transformation is safe
5137 as long as M1 and M2 have the same number of words. */
5139 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5140 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5141 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5143 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5144 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5145 #ifndef WORD_REGISTER_OPERATIONS
5146 && (GET_MODE_SIZE (GET_MODE (src))
5147 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5149 #ifdef CLASS_CANNOT_CHANGE_MODE
5150 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5151 && (TEST_HARD_REG_BIT
5152 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5154 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5155 GET_MODE (SUBREG_REG (src))))
5157 && (GET_CODE (dest) == REG
5158 || (GET_CODE (dest) == SUBREG
5159 && GET_CODE (SUBREG_REG (dest)) == REG)))
5161 SUBST (SET_DEST (x),
5162 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5164 SUBST (SET_SRC (x), SUBREG_REG (src));
5166 src = SET_SRC (x), dest = SET_DEST (x);
5170 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5173 && GET_CODE (src) == SUBREG
5174 && subreg_lowpart_p (src)
5175 && (GET_MODE_BITSIZE (GET_MODE (src))
5176 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5178 rtx inner = SUBREG_REG (src);
5179 enum machine_mode inner_mode = GET_MODE (inner);
5181 /* Here we make sure that we don't have a sign bit on. */
5182 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5183 && (nonzero_bits (inner, inner_mode)
5184 < ((unsigned HOST_WIDE_INT) 1
5185 << (GET_MODE_BITSIZE (inner_mode) - 1))))
5187 SUBST (SET_SRC (x), inner);
5193 #ifdef LOAD_EXTEND_OP
5194 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5195 would require a paradoxical subreg. Replace the subreg with a
5196 zero_extend to avoid the reload that would otherwise be required. */
5198 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5199 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5200 && SUBREG_BYTE (src) == 0
5201 && (GET_MODE_SIZE (GET_MODE (src))
5202 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5203 && GET_CODE (SUBREG_REG (src)) == MEM)
5206 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5207 GET_MODE (src), SUBREG_REG (src)));
5213 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5214 are comparing an item known to be 0 or -1 against 0, use a logical
5215 operation instead. Check for one of the arms being an IOR of the other
5216 arm with some value. We compute three terms to be IOR'ed together. In
5217 practice, at most two will be nonzero. Then we do the IOR's. */
5219 if (GET_CODE (dest) != PC
5220 && GET_CODE (src) == IF_THEN_ELSE
5221 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5222 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5223 && XEXP (XEXP (src, 0), 1) == const0_rtx
5224 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5225 #ifdef HAVE_conditional_move
5226 && ! can_conditionally_move_p (GET_MODE (src))
5228 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5229 GET_MODE (XEXP (XEXP (src, 0), 0)))
5230 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5231 && ! side_effects_p (src))
5233 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5234 ? XEXP (src, 1) : XEXP (src, 2));
5235 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5236 ? XEXP (src, 2) : XEXP (src, 1));
5237 rtx term1 = const0_rtx, term2, term3;
5239 if (GET_CODE (true_rtx) == IOR
5240 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5241 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5242 else if (GET_CODE (true_rtx) == IOR
5243 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5244 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5245 else if (GET_CODE (false_rtx) == IOR
5246 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5247 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5248 else if (GET_CODE (false_rtx) == IOR
5249 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5250 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5252 term2 = gen_binary (AND, GET_MODE (src),
5253 XEXP (XEXP (src, 0), 0), true_rtx);
5254 term3 = gen_binary (AND, GET_MODE (src),
5255 simplify_gen_unary (NOT, GET_MODE (src),
5256 XEXP (XEXP (src, 0), 0),
5261 gen_binary (IOR, GET_MODE (src),
5262 gen_binary (IOR, GET_MODE (src), term1, term2),
5268 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5269 whole thing fail. */
5270 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5272 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5275 /* Convert this into a field assignment operation, if possible. */
5276 return make_field_assignment (x);
5279 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5280 result. LAST is nonzero if this is the last retry. */
5283 simplify_logical (x, last)
5287 enum machine_mode mode = GET_MODE (x);
5288 rtx op0 = XEXP (x, 0);
5289 rtx op1 = XEXP (x, 1);
5292 switch (GET_CODE (x))
5295 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5296 insn (and may simplify more). */
5297 if (GET_CODE (op0) == XOR
5298 && rtx_equal_p (XEXP (op0, 0), op1)
5299 && ! side_effects_p (op1))
5300 x = gen_binary (AND, mode,
5301 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5304 if (GET_CODE (op0) == XOR
5305 && rtx_equal_p (XEXP (op0, 1), op1)
5306 && ! side_effects_p (op1))
5307 x = gen_binary (AND, mode,
5308 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5311 /* Similarly for (~(A ^ B)) & A. */
5312 if (GET_CODE (op0) == NOT
5313 && GET_CODE (XEXP (op0, 0)) == XOR
5314 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5315 && ! side_effects_p (op1))
5316 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5318 if (GET_CODE (op0) == NOT
5319 && GET_CODE (XEXP (op0, 0)) == XOR
5320 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5321 && ! side_effects_p (op1))
5322 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5324 /* We can call simplify_and_const_int only if we don't lose
5325 any (sign) bits when converting INTVAL (op1) to
5326 "unsigned HOST_WIDE_INT". */
5327 if (GET_CODE (op1) == CONST_INT
5328 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5329 || INTVAL (op1) > 0))
5331 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5333 /* If we have (ior (and (X C1) C2)) and the next restart would be
5334 the last, simplify this by making C1 as small as possible
5337 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5338 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5339 && GET_CODE (op1) == CONST_INT)
5340 return gen_binary (IOR, mode,
5341 gen_binary (AND, mode, XEXP (op0, 0),
5342 GEN_INT (INTVAL (XEXP (op0, 1))
5343 & ~INTVAL (op1))), op1);
5345 if (GET_CODE (x) != AND)
5348 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5349 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5350 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5353 /* Convert (A | B) & A to A. */
5354 if (GET_CODE (op0) == IOR
5355 && (rtx_equal_p (XEXP (op0, 0), op1)
5356 || rtx_equal_p (XEXP (op0, 1), op1))
5357 && ! side_effects_p (XEXP (op0, 0))
5358 && ! side_effects_p (XEXP (op0, 1)))
5361 /* In the following group of tests (and those in case IOR below),
5362 we start with some combination of logical operations and apply
5363 the distributive law followed by the inverse distributive law.
5364 Most of the time, this results in no change. However, if some of
5365 the operands are the same or inverses of each other, simplifications
5368 For example, (and (ior A B) (not B)) can occur as the result of
5369 expanding a bit field assignment. When we apply the distributive
5370 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5371 which then simplifies to (and (A (not B))).
5373 If we have (and (ior A B) C), apply the distributive law and then
5374 the inverse distributive law to see if things simplify. */
5376 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5378 x = apply_distributive_law
5379 (gen_binary (GET_CODE (op0), mode,
5380 gen_binary (AND, mode, XEXP (op0, 0), op1),
5381 gen_binary (AND, mode, XEXP (op0, 1),
5383 if (GET_CODE (x) != AND)
5387 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5388 return apply_distributive_law
5389 (gen_binary (GET_CODE (op1), mode,
5390 gen_binary (AND, mode, XEXP (op1, 0), op0),
5391 gen_binary (AND, mode, XEXP (op1, 1),
5394 /* Similarly, taking advantage of the fact that
5395 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5397 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5398 return apply_distributive_law
5399 (gen_binary (XOR, mode,
5400 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5401 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5404 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5405 return apply_distributive_law
5406 (gen_binary (XOR, mode,
5407 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5408 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5412 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5413 if (GET_CODE (op1) == CONST_INT
5414 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5415 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5418 /* Convert (A & B) | A to A. */
5419 if (GET_CODE (op0) == AND
5420 && (rtx_equal_p (XEXP (op0, 0), op1)
5421 || rtx_equal_p (XEXP (op0, 1), op1))
5422 && ! side_effects_p (XEXP (op0, 0))
5423 && ! side_effects_p (XEXP (op0, 1)))
5426 /* If we have (ior (and A B) C), apply the distributive law and then
5427 the inverse distributive law to see if things simplify. */
5429 if (GET_CODE (op0) == AND)
5431 x = apply_distributive_law
5432 (gen_binary (AND, mode,
5433 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5434 gen_binary (IOR, mode, XEXP (op0, 1),
5437 if (GET_CODE (x) != IOR)
5441 if (GET_CODE (op1) == AND)
5443 x = apply_distributive_law
5444 (gen_binary (AND, mode,
5445 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5446 gen_binary (IOR, mode, XEXP (op1, 1),
5449 if (GET_CODE (x) != IOR)
5453 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5454 mode size to (rotate A CX). */
5456 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5457 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5458 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5459 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5460 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5461 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5462 == GET_MODE_BITSIZE (mode)))
5463 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5464 (GET_CODE (op0) == ASHIFT
5465 ? XEXP (op0, 1) : XEXP (op1, 1)));
5467 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5468 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5469 does not affect any of the bits in OP1, it can really be done
5470 as a PLUS and we can associate. We do this by seeing if OP1
5471 can be safely shifted left C bits. */
5472 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5473 && GET_CODE (XEXP (op0, 0)) == PLUS
5474 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5475 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5476 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5478 int count = INTVAL (XEXP (op0, 1));
5479 HOST_WIDE_INT mask = INTVAL (op1) << count;
5481 if (mask >> count == INTVAL (op1)
5482 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5484 SUBST (XEXP (XEXP (op0, 0), 1),
5485 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5492 /* If we are XORing two things that have no bits in common,
5493 convert them into an IOR. This helps to detect rotation encoded
5494 using those methods and possibly other simplifications. */
5496 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5497 && (nonzero_bits (op0, mode)
5498 & nonzero_bits (op1, mode)) == 0)
5499 return (gen_binary (IOR, mode, op0, op1));
5501 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5502 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5505 int num_negated = 0;
5507 if (GET_CODE (op0) == NOT)
5508 num_negated++, op0 = XEXP (op0, 0);
5509 if (GET_CODE (op1) == NOT)
5510 num_negated++, op1 = XEXP (op1, 0);
5512 if (num_negated == 2)
5514 SUBST (XEXP (x, 0), op0);
5515 SUBST (XEXP (x, 1), op1);
5517 else if (num_negated == 1)
5519 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5523 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5524 correspond to a machine insn or result in further simplifications
5525 if B is a constant. */
5527 if (GET_CODE (op0) == AND
5528 && rtx_equal_p (XEXP (op0, 1), op1)
5529 && ! side_effects_p (op1))
5530 return gen_binary (AND, mode,
5531 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5534 else if (GET_CODE (op0) == AND
5535 && rtx_equal_p (XEXP (op0, 0), op1)
5536 && ! side_effects_p (op1))
5537 return gen_binary (AND, mode,
5538 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5541 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5542 comparison if STORE_FLAG_VALUE is 1. */
5543 if (STORE_FLAG_VALUE == 1
5544 && op1 == const1_rtx
5545 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5546 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5550 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5551 is (lt foo (const_int 0)), so we can perform the above
5552 simplification if STORE_FLAG_VALUE is 1. */
5554 if (STORE_FLAG_VALUE == 1
5555 && op1 == const1_rtx
5556 && GET_CODE (op0) == LSHIFTRT
5557 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5558 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5559 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5561 /* (xor (comparison foo bar) (const_int sign-bit))
5562 when STORE_FLAG_VALUE is the sign bit. */
5563 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5564 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5565 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5566 && op1 == const_true_rtx
5567 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5568 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5581 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5582 operations" because they can be replaced with two more basic operations.
5583 ZERO_EXTEND is also considered "compound" because it can be replaced with
5584 an AND operation, which is simpler, though only one operation.
5586 The function expand_compound_operation is called with an rtx expression
5587 and will convert it to the appropriate shifts and AND operations,
5588 simplifying at each stage.
5590 The function make_compound_operation is called to convert an expression
5591 consisting of shifts and ANDs into the equivalent compound expression.
5592 It is the inverse of this function, loosely speaking. */
5595 expand_compound_operation (x)
5598 unsigned HOST_WIDE_INT pos = 0, len;
5600 unsigned int modewidth;
5603 switch (GET_CODE (x))
5608 /* We can't necessarily use a const_int for a multiword mode;
5609 it depends on implicitly extending the value.
5610 Since we don't know the right way to extend it,
5611 we can't tell whether the implicit way is right.
5613 Even for a mode that is no wider than a const_int,
5614 we can't win, because we need to sign extend one of its bits through
5615 the rest of it, and we don't know which bit. */
5616 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5619 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5620 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5621 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5622 reloaded. If not for that, MEM's would very rarely be safe.
5624 Reject MODEs bigger than a word, because we might not be able
5625 to reference a two-register group starting with an arbitrary register
5626 (and currently gen_lowpart might crash for a SUBREG). */
5628 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5631 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5632 /* If the inner object has VOIDmode (the only way this can happen
5633 is if it is an ASM_OPERANDS), we can't do anything since we don't
5634 know how much masking to do. */
5643 /* If the operand is a CLOBBER, just return it. */
5644 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5647 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5648 || GET_CODE (XEXP (x, 2)) != CONST_INT
5649 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5652 len = INTVAL (XEXP (x, 1));
5653 pos = INTVAL (XEXP (x, 2));
5655 /* If this goes outside the object being extracted, replace the object
5656 with a (use (mem ...)) construct that only combine understands
5657 and is used only for this purpose. */
5658 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5659 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5661 if (BITS_BIG_ENDIAN)
5662 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5669 /* Convert sign extension to zero extension, if we know that the high
5670 bit is not set, as this is easier to optimize. It will be converted
5671 back to cheaper alternative in make_extraction. */
5672 if (GET_CODE (x) == SIGN_EXTEND
5673 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5674 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5675 & ~(((unsigned HOST_WIDE_INT)
5676 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5680 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5681 return expand_compound_operation (temp);
5684 /* We can optimize some special cases of ZERO_EXTEND. */
5685 if (GET_CODE (x) == ZERO_EXTEND)
5687 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5688 know that the last value didn't have any inappropriate bits
5690 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5691 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5692 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5693 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5694 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5695 return XEXP (XEXP (x, 0), 0);
5697 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5698 if (GET_CODE (XEXP (x, 0)) == SUBREG
5699 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5700 && subreg_lowpart_p (XEXP (x, 0))
5701 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5702 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5703 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5704 return SUBREG_REG (XEXP (x, 0));
5706 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5707 is a comparison and STORE_FLAG_VALUE permits. This is like
5708 the first case, but it works even when GET_MODE (x) is larger
5709 than HOST_WIDE_INT. */
5710 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5711 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5712 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5713 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5714 <= HOST_BITS_PER_WIDE_INT)
5715 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5716 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5717 return XEXP (XEXP (x, 0), 0);
5719 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5720 if (GET_CODE (XEXP (x, 0)) == SUBREG
5721 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5722 && subreg_lowpart_p (XEXP (x, 0))
5723 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5724 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5725 <= HOST_BITS_PER_WIDE_INT)
5726 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5727 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5728 return SUBREG_REG (XEXP (x, 0));
5732 /* If we reach here, we want to return a pair of shifts. The inner
5733 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5734 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5735 logical depending on the value of UNSIGNEDP.
5737 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5738 converted into an AND of a shift.
5740 We must check for the case where the left shift would have a negative
5741 count. This can happen in a case like (x >> 31) & 255 on machines
5742 that can't shift by a constant. On those machines, we would first
5743 combine the shift with the AND to produce a variable-position
5744 extraction. Then the constant of 31 would be substituted in to produce
5745 a such a position. */
5747 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5748 if (modewidth + len >= pos)
5749 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5751 simplify_shift_const (NULL_RTX, ASHIFT,
5754 modewidth - pos - len),
5757 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5758 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5759 simplify_shift_const (NULL_RTX, LSHIFTRT,
5762 ((HOST_WIDE_INT) 1 << len) - 1);
5764 /* Any other cases we can't handle. */
5767 /* If we couldn't do this for some reason, return the original
5769 if (GET_CODE (tem) == CLOBBER)
5775 /* X is a SET which contains an assignment of one object into
5776 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5777 or certain SUBREGS). If possible, convert it into a series of
5780 We half-heartedly support variable positions, but do not at all
5781 support variable lengths. */
5784 expand_field_assignment (x)
5788 rtx pos; /* Always counts from low bit. */
5791 enum machine_mode compute_mode;
5793 /* Loop until we find something we can't simplify. */
5796 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5797 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5799 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5800 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5801 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5803 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5804 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5806 inner = XEXP (SET_DEST (x), 0);
5807 len = INTVAL (XEXP (SET_DEST (x), 1));
5808 pos = XEXP (SET_DEST (x), 2);
5810 /* If the position is constant and spans the width of INNER,
5811 surround INNER with a USE to indicate this. */
5812 if (GET_CODE (pos) == CONST_INT
5813 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5814 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5816 if (BITS_BIG_ENDIAN)
5818 if (GET_CODE (pos) == CONST_INT)
5819 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5821 else if (GET_CODE (pos) == MINUS
5822 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5823 && (INTVAL (XEXP (pos, 1))
5824 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5825 /* If position is ADJUST - X, new position is X. */
5826 pos = XEXP (pos, 0);
5828 pos = gen_binary (MINUS, GET_MODE (pos),
5829 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5835 /* A SUBREG between two modes that occupy the same numbers of words
5836 can be done by moving the SUBREG to the source. */
5837 else if (GET_CODE (SET_DEST (x)) == SUBREG
5838 /* We need SUBREGs to compute nonzero_bits properly. */
5839 && nonzero_sign_valid
5840 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5841 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5842 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5843 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5845 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5846 gen_lowpart_for_combine
5847 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5854 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5855 inner = SUBREG_REG (inner);
5857 compute_mode = GET_MODE (inner);
5859 /* Don't attempt bitwise arithmetic on non-integral modes. */
5860 if (! INTEGRAL_MODE_P (compute_mode))
5862 enum machine_mode imode;
5864 /* Something is probably seriously wrong if this matches. */
5865 if (! FLOAT_MODE_P (compute_mode))
5868 /* Try to find an integral mode to pun with. */
5869 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5870 if (imode == BLKmode)
5873 compute_mode = imode;
5874 inner = gen_lowpart_for_combine (imode, inner);
5877 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5878 if (len < HOST_BITS_PER_WIDE_INT)
5879 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5883 /* Now compute the equivalent expression. Make a copy of INNER
5884 for the SET_DEST in case it is a MEM into which we will substitute;
5885 we don't want shared RTL in that case. */
5887 (VOIDmode, copy_rtx (inner),
5888 gen_binary (IOR, compute_mode,
5889 gen_binary (AND, compute_mode,
5890 simplify_gen_unary (NOT, compute_mode,
5896 gen_binary (ASHIFT, compute_mode,
5897 gen_binary (AND, compute_mode,
5898 gen_lowpart_for_combine
5899 (compute_mode, SET_SRC (x)),
5907 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5908 it is an RTX that represents a variable starting position; otherwise,
5909 POS is the (constant) starting bit position (counted from the LSB).
5911 INNER may be a USE. This will occur when we started with a bitfield
5912 that went outside the boundary of the object in memory, which is
5913 allowed on most machines. To isolate this case, we produce a USE
5914 whose mode is wide enough and surround the MEM with it. The only
5915 code that understands the USE is this routine. If it is not removed,
5916 it will cause the resulting insn not to match.
5918 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5921 IN_DEST is non-zero if this is a reference in the destination of a
5922 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5923 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5926 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5927 ZERO_EXTRACT should be built even for bits starting at bit 0.
5929 MODE is the desired mode of the result (if IN_DEST == 0).
5931 The result is an RTX for the extraction or NULL_RTX if the target
5935 make_extraction (mode, inner, pos, pos_rtx, len,
5936 unsignedp, in_dest, in_compare)
5937 enum machine_mode mode;
5941 unsigned HOST_WIDE_INT len;
5943 int in_dest, in_compare;
5945 /* This mode describes the size of the storage area
5946 to fetch the overall value from. Within that, we
5947 ignore the POS lowest bits, etc. */
5948 enum machine_mode is_mode = GET_MODE (inner);
5949 enum machine_mode inner_mode;
5950 enum machine_mode wanted_inner_mode = byte_mode;
5951 enum machine_mode wanted_inner_reg_mode = word_mode;
5952 enum machine_mode pos_mode = word_mode;
5953 enum machine_mode extraction_mode = word_mode;
5954 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5957 rtx orig_pos_rtx = pos_rtx;
5958 HOST_WIDE_INT orig_pos;
5960 /* Get some information about INNER and get the innermost object. */
5961 if (GET_CODE (inner) == USE)
5962 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5963 /* We don't need to adjust the position because we set up the USE
5964 to pretend that it was a full-word object. */
5965 spans_byte = 1, inner = XEXP (inner, 0);
5966 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5968 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5969 consider just the QI as the memory to extract from.
5970 The subreg adds or removes high bits; its mode is
5971 irrelevant to the meaning of this extraction,
5972 since POS and LEN count from the lsb. */
5973 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5974 is_mode = GET_MODE (SUBREG_REG (inner));
5975 inner = SUBREG_REG (inner);
5978 inner_mode = GET_MODE (inner);
5980 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5981 pos = INTVAL (pos_rtx), pos_rtx = 0;
5983 /* See if this can be done without an extraction. We never can if the
5984 width of the field is not the same as that of some integer mode. For
5985 registers, we can only avoid the extraction if the position is at the
5986 low-order bit and this is either not in the destination or we have the
5987 appropriate STRICT_LOW_PART operation available.
5989 For MEM, we can avoid an extract if the field starts on an appropriate
5990 boundary and we can change the mode of the memory reference. However,
5991 we cannot directly access the MEM if we have a USE and the underlying
5992 MEM is not TMODE. This combination means that MEM was being used in a
5993 context where bits outside its mode were being referenced; that is only
5994 valid in bit-field insns. */
5996 if (tmode != BLKmode
5997 && ! (spans_byte && inner_mode != tmode)
5998 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5999 && GET_CODE (inner) != MEM
6001 || (GET_CODE (inner) == REG
6002 && have_insn_for (STRICT_LOW_PART, tmode))))
6003 || (GET_CODE (inner) == MEM && pos_rtx == 0
6005 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6006 : BITS_PER_UNIT)) == 0
6007 /* We can't do this if we are widening INNER_MODE (it
6008 may not be aligned, for one thing). */
6009 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6010 && (inner_mode == tmode
6011 || (! mode_dependent_address_p (XEXP (inner, 0))
6012 && ! MEM_VOLATILE_P (inner))))))
6014 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6015 field. If the original and current mode are the same, we need not
6016 adjust the offset. Otherwise, we do if bytes big endian.
6018 If INNER is not a MEM, get a piece consisting of just the field
6019 of interest (in this case POS % BITS_PER_WORD must be 0). */
6021 if (GET_CODE (inner) == MEM)
6023 HOST_WIDE_INT offset;
6025 /* POS counts from lsb, but make OFFSET count in memory order. */
6026 if (BYTES_BIG_ENDIAN)
6027 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6029 offset = pos / BITS_PER_UNIT;
6031 new = adjust_address_nv (inner, tmode, offset);
6033 else if (GET_CODE (inner) == REG)
6035 /* We can't call gen_lowpart_for_combine here since we always want
6036 a SUBREG and it would sometimes return a new hard register. */
6037 if (tmode != inner_mode)
6039 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6041 if (WORDS_BIG_ENDIAN
6042 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6043 final_word = ((GET_MODE_SIZE (inner_mode)
6044 - GET_MODE_SIZE (tmode))
6045 / UNITS_PER_WORD) - final_word;
6047 final_word *= UNITS_PER_WORD;
6048 if (BYTES_BIG_ENDIAN &&
6049 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6050 final_word += (GET_MODE_SIZE (inner_mode)
6051 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6053 new = gen_rtx_SUBREG (tmode, inner, final_word);
6059 new = force_to_mode (inner, tmode,
6060 len >= HOST_BITS_PER_WIDE_INT
6061 ? ~(unsigned HOST_WIDE_INT) 0
6062 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6065 /* If this extraction is going into the destination of a SET,
6066 make a STRICT_LOW_PART unless we made a MEM. */
6069 return (GET_CODE (new) == MEM ? new
6070 : (GET_CODE (new) != SUBREG
6071 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6072 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6077 if (GET_CODE (new) == CONST_INT)
6078 return gen_int_mode (INTVAL (new), mode);
6080 /* If we know that no extraneous bits are set, and that the high
6081 bit is not set, convert the extraction to the cheaper of
6082 sign and zero extension, that are equivalent in these cases. */
6083 if (flag_expensive_optimizations
6084 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6085 && ((nonzero_bits (new, tmode)
6086 & ~(((unsigned HOST_WIDE_INT)
6087 GET_MODE_MASK (tmode))
6091 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6092 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6094 /* Prefer ZERO_EXTENSION, since it gives more information to
6096 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6101 /* Otherwise, sign- or zero-extend unless we already are in the
6104 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6108 /* Unless this is a COMPARE or we have a funny memory reference,
6109 don't do anything with zero-extending field extracts starting at
6110 the low-order bit since they are simple AND operations. */
6111 if (pos_rtx == 0 && pos == 0 && ! in_dest
6112 && ! in_compare && ! spans_byte && unsignedp)
6115 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6116 we would be spanning bytes or if the position is not a constant and the
6117 length is not 1. In all other cases, we would only be going outside
6118 our object in cases when an original shift would have been
6120 if (! spans_byte && GET_CODE (inner) == MEM
6121 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6122 || (pos_rtx != 0 && len != 1)))
6125 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6126 and the mode for the result. */
6127 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6129 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6130 pos_mode = mode_for_extraction (EP_insv, 2);
6131 extraction_mode = mode_for_extraction (EP_insv, 3);
6134 if (! in_dest && unsignedp
6135 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6137 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6138 pos_mode = mode_for_extraction (EP_extzv, 3);
6139 extraction_mode = mode_for_extraction (EP_extzv, 0);
6142 if (! in_dest && ! unsignedp
6143 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6145 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6146 pos_mode = mode_for_extraction (EP_extv, 3);
6147 extraction_mode = mode_for_extraction (EP_extv, 0);
6150 /* Never narrow an object, since that might not be safe. */
6152 if (mode != VOIDmode
6153 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6154 extraction_mode = mode;
6156 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6157 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6158 pos_mode = GET_MODE (pos_rtx);
6160 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6161 if we have to change the mode of memory and cannot, the desired mode is
6163 if (GET_CODE (inner) != MEM)
6164 wanted_inner_mode = wanted_inner_reg_mode;
6165 else if (inner_mode != wanted_inner_mode
6166 && (mode_dependent_address_p (XEXP (inner, 0))
6167 || MEM_VOLATILE_P (inner)))
6168 wanted_inner_mode = extraction_mode;
6172 if (BITS_BIG_ENDIAN)
6174 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6175 BITS_BIG_ENDIAN style. If position is constant, compute new
6176 position. Otherwise, build subtraction.
6177 Note that POS is relative to the mode of the original argument.
6178 If it's a MEM we need to recompute POS relative to that.
6179 However, if we're extracting from (or inserting into) a register,
6180 we want to recompute POS relative to wanted_inner_mode. */
6181 int width = (GET_CODE (inner) == MEM
6182 ? GET_MODE_BITSIZE (is_mode)
6183 : GET_MODE_BITSIZE (wanted_inner_mode));
6186 pos = width - len - pos;
6189 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6190 /* POS may be less than 0 now, but we check for that below.
6191 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6194 /* If INNER has a wider mode, make it smaller. If this is a constant
6195 extract, try to adjust the byte to point to the byte containing
6197 if (wanted_inner_mode != VOIDmode
6198 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6199 && ((GET_CODE (inner) == MEM
6200 && (inner_mode == wanted_inner_mode
6201 || (! mode_dependent_address_p (XEXP (inner, 0))
6202 && ! MEM_VOLATILE_P (inner))))))
6206 /* The computations below will be correct if the machine is big
6207 endian in both bits and bytes or little endian in bits and bytes.
6208 If it is mixed, we must adjust. */
6210 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6211 adjust OFFSET to compensate. */
6212 if (BYTES_BIG_ENDIAN
6214 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6215 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6217 /* If this is a constant position, we can move to the desired byte. */
6220 offset += pos / BITS_PER_UNIT;
6221 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6224 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6226 && is_mode != wanted_inner_mode)
6227 offset = (GET_MODE_SIZE (is_mode)
6228 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6230 if (offset != 0 || inner_mode != wanted_inner_mode)
6231 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6234 /* If INNER is not memory, we can always get it into the proper mode. If we
6235 are changing its mode, POS must be a constant and smaller than the size
6237 else if (GET_CODE (inner) != MEM)
6239 if (GET_MODE (inner) != wanted_inner_mode
6241 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6244 inner = force_to_mode (inner, wanted_inner_mode,
6246 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6247 ? ~(unsigned HOST_WIDE_INT) 0
6248 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6253 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6254 have to zero extend. Otherwise, we can just use a SUBREG. */
6256 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6258 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6260 /* If we know that no extraneous bits are set, and that the high
6261 bit is not set, convert extraction to cheaper one - either
6262 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6264 if (flag_expensive_optimizations
6265 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6266 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6267 & ~(((unsigned HOST_WIDE_INT)
6268 GET_MODE_MASK (GET_MODE (pos_rtx)))
6272 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6274 /* Prefer ZERO_EXTENSION, since it gives more information to
6276 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6281 else if (pos_rtx != 0
6282 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6283 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6285 /* Make POS_RTX unless we already have it and it is correct. If we don't
6286 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6288 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6289 pos_rtx = orig_pos_rtx;
6291 else if (pos_rtx == 0)
6292 pos_rtx = GEN_INT (pos);
6294 /* Make the required operation. See if we can use existing rtx. */
6295 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6296 extraction_mode, inner, GEN_INT (len), pos_rtx);
6298 new = gen_lowpart_for_combine (mode, new);
6303 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6304 with any other operations in X. Return X without that shift if so. */
6307 extract_left_shift (x, count)
6311 enum rtx_code code = GET_CODE (x);
6312 enum machine_mode mode = GET_MODE (x);
6318 /* This is the shift itself. If it is wide enough, we will return
6319 either the value being shifted if the shift count is equal to
6320 COUNT or a shift for the difference. */
6321 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6322 && INTVAL (XEXP (x, 1)) >= count)
6323 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6324 INTVAL (XEXP (x, 1)) - count);
6328 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6329 return simplify_gen_unary (code, mode, tem, mode);
6333 case PLUS: case IOR: case XOR: case AND:
6334 /* If we can safely shift this constant and we find the inner shift,
6335 make a new operation. */
6336 if (GET_CODE (XEXP (x,1)) == CONST_INT
6337 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6338 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6339 return gen_binary (code, mode, tem,
6340 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6351 /* Look at the expression rooted at X. Look for expressions
6352 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6353 Form these expressions.
6355 Return the new rtx, usually just X.
6357 Also, for machines like the VAX that don't have logical shift insns,
6358 try to convert logical to arithmetic shift operations in cases where
6359 they are equivalent. This undoes the canonicalizations to logical
6360 shifts done elsewhere.
6362 We try, as much as possible, to re-use rtl expressions to save memory.
6364 IN_CODE says what kind of expression we are processing. Normally, it is
6365 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6366 being kludges), it is MEM. When processing the arguments of a comparison
6367 or a COMPARE against zero, it is COMPARE. */
6370 make_compound_operation (x, in_code)
6372 enum rtx_code in_code;
6374 enum rtx_code code = GET_CODE (x);
6375 enum machine_mode mode = GET_MODE (x);
6376 int mode_width = GET_MODE_BITSIZE (mode);
6378 enum rtx_code next_code;
6384 /* Select the code to be used in recursive calls. Once we are inside an
6385 address, we stay there. If we have a comparison, set to COMPARE,
6386 but once inside, go back to our default of SET. */
6388 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6389 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6390 && XEXP (x, 1) == const0_rtx) ? COMPARE
6391 : in_code == COMPARE ? SET : in_code);
6393 /* Process depending on the code of this operation. If NEW is set
6394 non-zero, it will be returned. */
6399 /* Convert shifts by constants into multiplications if inside
6401 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6402 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6403 && INTVAL (XEXP (x, 1)) >= 0)
6405 new = make_compound_operation (XEXP (x, 0), next_code);
6406 new = gen_rtx_MULT (mode, new,
6407 GEN_INT ((HOST_WIDE_INT) 1
6408 << INTVAL (XEXP (x, 1))));
6413 /* If the second operand is not a constant, we can't do anything
6415 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6418 /* If the constant is a power of two minus one and the first operand
6419 is a logical right shift, make an extraction. */
6420 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6421 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6423 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6424 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6425 0, in_code == COMPARE);
6428 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6429 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6430 && subreg_lowpart_p (XEXP (x, 0))
6431 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6432 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6434 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6436 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6437 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6438 0, in_code == COMPARE);
6440 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6441 else if ((GET_CODE (XEXP (x, 0)) == XOR
6442 || GET_CODE (XEXP (x, 0)) == IOR)
6443 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6444 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6445 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6447 /* Apply the distributive law, and then try to make extractions. */
6448 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6449 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6451 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6453 new = make_compound_operation (new, in_code);
6456 /* If we are have (and (rotate X C) M) and C is larger than the number
6457 of bits in M, this is an extraction. */
6459 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6460 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6461 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6462 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6464 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6465 new = make_extraction (mode, new,
6466 (GET_MODE_BITSIZE (mode)
6467 - INTVAL (XEXP (XEXP (x, 0), 1))),
6468 NULL_RTX, i, 1, 0, in_code == COMPARE);
6471 /* On machines without logical shifts, if the operand of the AND is
6472 a logical shift and our mask turns off all the propagated sign
6473 bits, we can replace the logical shift with an arithmetic shift. */
6474 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6475 && !have_insn_for (LSHIFTRT, mode)
6476 && have_insn_for (ASHIFTRT, mode)
6477 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6478 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6479 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6480 && mode_width <= HOST_BITS_PER_WIDE_INT)
6482 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6484 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6485 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6487 gen_rtx_ASHIFTRT (mode,
6488 make_compound_operation
6489 (XEXP (XEXP (x, 0), 0), next_code),
6490 XEXP (XEXP (x, 0), 1)));
6493 /* If the constant is one less than a power of two, this might be
6494 representable by an extraction even if no shift is present.
6495 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6496 we are in a COMPARE. */
6497 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6498 new = make_extraction (mode,
6499 make_compound_operation (XEXP (x, 0),
6501 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6503 /* If we are in a comparison and this is an AND with a power of two,
6504 convert this into the appropriate bit extract. */
6505 else if (in_code == COMPARE
6506 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6507 new = make_extraction (mode,
6508 make_compound_operation (XEXP (x, 0),
6510 i, NULL_RTX, 1, 1, 0, 1);
6515 /* If the sign bit is known to be zero, replace this with an
6516 arithmetic shift. */
6517 if (have_insn_for (ASHIFTRT, mode)
6518 && ! have_insn_for (LSHIFTRT, mode)
6519 && mode_width <= HOST_BITS_PER_WIDE_INT
6520 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6522 new = gen_rtx_ASHIFTRT (mode,
6523 make_compound_operation (XEXP (x, 0),
6529 /* ... fall through ... */
6535 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6536 this is a SIGN_EXTRACT. */
6537 if (GET_CODE (rhs) == CONST_INT
6538 && GET_CODE (lhs) == ASHIFT
6539 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6540 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6542 new = make_compound_operation (XEXP (lhs, 0), next_code);
6543 new = make_extraction (mode, new,
6544 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6545 NULL_RTX, mode_width - INTVAL (rhs),
6546 code == LSHIFTRT, 0, in_code == COMPARE);
6550 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6551 If so, try to merge the shifts into a SIGN_EXTEND. We could
6552 also do this for some cases of SIGN_EXTRACT, but it doesn't
6553 seem worth the effort; the case checked for occurs on Alpha. */
6555 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6556 && ! (GET_CODE (lhs) == SUBREG
6557 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6558 && GET_CODE (rhs) == CONST_INT
6559 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6560 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6561 new = make_extraction (mode, make_compound_operation (new, next_code),
6562 0, NULL_RTX, mode_width - INTVAL (rhs),
6563 code == LSHIFTRT, 0, in_code == COMPARE);
6568 /* Call ourselves recursively on the inner expression. If we are
6569 narrowing the object and it has a different RTL code from
6570 what it originally did, do this SUBREG as a force_to_mode. */
6572 tem = make_compound_operation (SUBREG_REG (x), in_code);
6573 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6574 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6575 && subreg_lowpart_p (x))
6577 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6580 /* If we have something other than a SUBREG, we might have
6581 done an expansion, so rerun ourselves. */
6582 if (GET_CODE (newer) != SUBREG)
6583 newer = make_compound_operation (newer, in_code);
6588 /* If this is a paradoxical subreg, and the new code is a sign or
6589 zero extension, omit the subreg and widen the extension. If it
6590 is a regular subreg, we can still get rid of the subreg by not
6591 widening so much, or in fact removing the extension entirely. */
6592 if ((GET_CODE (tem) == SIGN_EXTEND
6593 || GET_CODE (tem) == ZERO_EXTEND)
6594 && subreg_lowpart_p (x))
6596 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6597 || (GET_MODE_SIZE (mode) >
6598 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6599 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6601 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6612 x = gen_lowpart_for_combine (mode, new);
6613 code = GET_CODE (x);
6616 /* Now recursively process each operand of this operation. */
6617 fmt = GET_RTX_FORMAT (code);
6618 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6621 new = make_compound_operation (XEXP (x, i), next_code);
6622 SUBST (XEXP (x, i), new);
6628 /* Given M see if it is a value that would select a field of bits
6629 within an item, but not the entire word. Return -1 if not.
6630 Otherwise, return the starting position of the field, where 0 is the
6633 *PLEN is set to the length of the field. */
6636 get_pos_from_mask (m, plen)
6637 unsigned HOST_WIDE_INT m;
6638 unsigned HOST_WIDE_INT *plen;
6640 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6641 int pos = exact_log2 (m & -m);
6647 /* Now shift off the low-order zero bits and see if we have a power of
6649 len = exact_log2 ((m >> pos) + 1);
6658 /* See if X can be simplified knowing that we will only refer to it in
6659 MODE and will only refer to those bits that are nonzero in MASK.
6660 If other bits are being computed or if masking operations are done
6661 that select a superset of the bits in MASK, they can sometimes be
6664 Return a possibly simplified expression, but always convert X to
6665 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6667 Also, if REG is non-zero and X is a register equal in value to REG,
6670 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6671 are all off in X. This is used when X will be complemented, by either
6672 NOT, NEG, or XOR. */
6675 force_to_mode (x, mode, mask, reg, just_select)
6677 enum machine_mode mode;
6678 unsigned HOST_WIDE_INT mask;
6682 enum rtx_code code = GET_CODE (x);
6683 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6684 enum machine_mode op_mode;
6685 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6688 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6689 code below will do the wrong thing since the mode of such an
6690 expression is VOIDmode.
6692 Also do nothing if X is a CLOBBER; this can happen if X was
6693 the return value from a call to gen_lowpart_for_combine. */
6694 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6697 /* We want to perform the operation is its present mode unless we know
6698 that the operation is valid in MODE, in which case we do the operation
6700 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6701 && have_insn_for (code, mode))
6702 ? mode : GET_MODE (x));
6704 /* It is not valid to do a right-shift in a narrower mode
6705 than the one it came in with. */
6706 if ((code == LSHIFTRT || code == ASHIFTRT)
6707 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6708 op_mode = GET_MODE (x);
6710 /* Truncate MASK to fit OP_MODE. */
6712 mask &= GET_MODE_MASK (op_mode);
6714 /* When we have an arithmetic operation, or a shift whose count we
6715 do not know, we need to assume that all bit the up to the highest-order
6716 bit in MASK will be needed. This is how we form such a mask. */
6718 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6719 ? GET_MODE_MASK (op_mode)
6720 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6723 fuller_mask = ~(HOST_WIDE_INT) 0;
6725 /* Determine what bits of X are guaranteed to be (non)zero. */
6726 nonzero = nonzero_bits (x, mode);
6728 /* If none of the bits in X are needed, return a zero. */
6729 if (! just_select && (nonzero & mask) == 0)
6732 /* If X is a CONST_INT, return a new one. Do this here since the
6733 test below will fail. */
6734 if (GET_CODE (x) == CONST_INT)
6735 return gen_int_mode (INTVAL (x) & mask, mode);
6737 /* If X is narrower than MODE and we want all the bits in X's mode, just
6738 get X in the proper mode. */
6739 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6740 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6741 return gen_lowpart_for_combine (mode, x);
6743 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6744 MASK are already known to be zero in X, we need not do anything. */
6745 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6751 /* If X is a (clobber (const_int)), return it since we know we are
6752 generating something that won't match. */
6756 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6757 spanned the boundary of the MEM. If we are now masking so it is
6758 within that boundary, we don't need the USE any more. */
6759 if (! BITS_BIG_ENDIAN
6760 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6761 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6768 x = expand_compound_operation (x);
6769 if (GET_CODE (x) != code)
6770 return force_to_mode (x, mode, mask, reg, next_select);
6774 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6775 || rtx_equal_p (reg, get_last_value (x))))
6780 if (subreg_lowpart_p (x)
6781 /* We can ignore the effect of this SUBREG if it narrows the mode or
6782 if the constant masks to zero all the bits the mode doesn't
6784 && ((GET_MODE_SIZE (GET_MODE (x))
6785 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6787 & GET_MODE_MASK (GET_MODE (x))
6788 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6789 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6793 /* If this is an AND with a constant, convert it into an AND
6794 whose constant is the AND of that constant with MASK. If it
6795 remains an AND of MASK, delete it since it is redundant. */
6797 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6799 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6800 mask & INTVAL (XEXP (x, 1)));
6802 /* If X is still an AND, see if it is an AND with a mask that
6803 is just some low-order bits. If so, and it is MASK, we don't
6806 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6807 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6808 == (HOST_WIDE_INT) mask))
6811 /* If it remains an AND, try making another AND with the bits
6812 in the mode mask that aren't in MASK turned on. If the
6813 constant in the AND is wide enough, this might make a
6814 cheaper constant. */
6816 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6817 && GET_MODE_MASK (GET_MODE (x)) != mask
6818 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6820 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6821 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6822 int width = GET_MODE_BITSIZE (GET_MODE (x));
6825 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6826 number, sign extend it. */
6827 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6828 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6829 cval |= (HOST_WIDE_INT) -1 << width;
6831 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6832 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6842 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6843 low-order bits (as in an alignment operation) and FOO is already
6844 aligned to that boundary, mask C1 to that boundary as well.
6845 This may eliminate that PLUS and, later, the AND. */
6848 unsigned int width = GET_MODE_BITSIZE (mode);
6849 unsigned HOST_WIDE_INT smask = mask;
6851 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6852 number, sign extend it. */
6854 if (width < HOST_BITS_PER_WIDE_INT
6855 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6856 smask |= (HOST_WIDE_INT) -1 << width;
6858 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6859 && exact_log2 (- smask) >= 0
6860 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6861 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6862 return force_to_mode (plus_constant (XEXP (x, 0),
6863 (INTVAL (XEXP (x, 1)) & smask)),
6864 mode, smask, reg, next_select);
6867 /* ... fall through ... */
6870 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6871 most significant bit in MASK since carries from those bits will
6872 affect the bits we are interested in. */
6877 /* If X is (minus C Y) where C's least set bit is larger than any bit
6878 in the mask, then we may replace with (neg Y). */
6879 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6880 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6881 & -INTVAL (XEXP (x, 0))))
6884 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6886 return force_to_mode (x, mode, mask, reg, next_select);
6889 /* Similarly, if C contains every bit in the mask, then we may
6890 replace with (not Y). */
6891 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6892 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6893 == INTVAL (XEXP (x, 0))))
6895 x = simplify_gen_unary (NOT, GET_MODE (x),
6896 XEXP (x, 1), GET_MODE (x));
6897 return force_to_mode (x, mode, mask, reg, next_select);
6905 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6906 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6907 operation which may be a bitfield extraction. Ensure that the
6908 constant we form is not wider than the mode of X. */
6910 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6911 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6912 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6913 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6914 && GET_CODE (XEXP (x, 1)) == CONST_INT
6915 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6916 + floor_log2 (INTVAL (XEXP (x, 1))))
6917 < GET_MODE_BITSIZE (GET_MODE (x)))
6918 && (INTVAL (XEXP (x, 1))
6919 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6921 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6922 << INTVAL (XEXP (XEXP (x, 0), 1)));
6923 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6924 XEXP (XEXP (x, 0), 0), temp);
6925 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6926 XEXP (XEXP (x, 0), 1));
6927 return force_to_mode (x, mode, mask, reg, next_select);
6931 /* For most binary operations, just propagate into the operation and
6932 change the mode if we have an operation of that mode. */
6934 op0 = gen_lowpart_for_combine (op_mode,
6935 force_to_mode (XEXP (x, 0), mode, mask,
6937 op1 = gen_lowpart_for_combine (op_mode,
6938 force_to_mode (XEXP (x, 1), mode, mask,
6941 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6942 x = gen_binary (code, op_mode, op0, op1);
6946 /* For left shifts, do the same, but just for the first operand.
6947 However, we cannot do anything with shifts where we cannot
6948 guarantee that the counts are smaller than the size of the mode
6949 because such a count will have a different meaning in a
6952 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6953 && INTVAL (XEXP (x, 1)) >= 0
6954 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6955 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6956 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6957 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6960 /* If the shift count is a constant and we can do arithmetic in
6961 the mode of the shift, refine which bits we need. Otherwise, use the
6962 conservative form of the mask. */
6963 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6964 && INTVAL (XEXP (x, 1)) >= 0
6965 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6966 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6967 mask >>= INTVAL (XEXP (x, 1));
6971 op0 = gen_lowpart_for_combine (op_mode,
6972 force_to_mode (XEXP (x, 0), op_mode,
6973 mask, reg, next_select));
6975 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6976 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6980 /* Here we can only do something if the shift count is a constant,
6981 this shift constant is valid for the host, and we can do arithmetic
6984 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6985 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6986 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6988 rtx inner = XEXP (x, 0);
6989 unsigned HOST_WIDE_INT inner_mask;
6991 /* Select the mask of the bits we need for the shift operand. */
6992 inner_mask = mask << INTVAL (XEXP (x, 1));
6994 /* We can only change the mode of the shift if we can do arithmetic
6995 in the mode of the shift and INNER_MASK is no wider than the
6996 width of OP_MODE. */
6997 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6998 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6999 op_mode = GET_MODE (x);
7001 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7003 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7004 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7007 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7008 shift and AND produces only copies of the sign bit (C2 is one less
7009 than a power of two), we can do this with just a shift. */
7011 if (GET_CODE (x) == LSHIFTRT
7012 && GET_CODE (XEXP (x, 1)) == CONST_INT
7013 /* The shift puts one of the sign bit copies in the least significant
7015 && ((INTVAL (XEXP (x, 1))
7016 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7017 >= GET_MODE_BITSIZE (GET_MODE (x)))
7018 && exact_log2 (mask + 1) >= 0
7019 /* Number of bits left after the shift must be more than the mask
7021 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7022 <= GET_MODE_BITSIZE (GET_MODE (x)))
7023 /* Must be more sign bit copies than the mask needs. */
7024 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7025 >= exact_log2 (mask + 1)))
7026 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7027 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7028 - exact_log2 (mask + 1)));
7033 /* If we are just looking for the sign bit, we don't need this shift at
7034 all, even if it has a variable count. */
7035 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7036 && (mask == ((unsigned HOST_WIDE_INT) 1
7037 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7038 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7040 /* If this is a shift by a constant, get a mask that contains those bits
7041 that are not copies of the sign bit. We then have two cases: If
7042 MASK only includes those bits, this can be a logical shift, which may
7043 allow simplifications. If MASK is a single-bit field not within
7044 those bits, we are requesting a copy of the sign bit and hence can
7045 shift the sign bit to the appropriate location. */
7047 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7048 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7052 /* If the considered data is wider than HOST_WIDE_INT, we can't
7053 represent a mask for all its bits in a single scalar.
7054 But we only care about the lower bits, so calculate these. */
7056 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7058 nonzero = ~(HOST_WIDE_INT) 0;
7060 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7061 is the number of bits a full-width mask would have set.
7062 We need only shift if these are fewer than nonzero can
7063 hold. If not, we must keep all bits set in nonzero. */
7065 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7066 < HOST_BITS_PER_WIDE_INT)
7067 nonzero >>= INTVAL (XEXP (x, 1))
7068 + HOST_BITS_PER_WIDE_INT
7069 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7073 nonzero = GET_MODE_MASK (GET_MODE (x));
7074 nonzero >>= INTVAL (XEXP (x, 1));
7077 if ((mask & ~nonzero) == 0
7078 || (i = exact_log2 (mask)) >= 0)
7080 x = simplify_shift_const
7081 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7082 i < 0 ? INTVAL (XEXP (x, 1))
7083 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7085 if (GET_CODE (x) != ASHIFTRT)
7086 return force_to_mode (x, mode, mask, reg, next_select);
7090 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7091 even if the shift count isn't a constant. */
7093 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7097 /* If this is a zero- or sign-extension operation that just affects bits
7098 we don't care about, remove it. Be sure the call above returned
7099 something that is still a shift. */
7101 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7102 && GET_CODE (XEXP (x, 1)) == CONST_INT
7103 && INTVAL (XEXP (x, 1)) >= 0
7104 && (INTVAL (XEXP (x, 1))
7105 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7106 && GET_CODE (XEXP (x, 0)) == ASHIFT
7107 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7108 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7109 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7116 /* If the shift count is constant and we can do computations
7117 in the mode of X, compute where the bits we care about are.
7118 Otherwise, we can't do anything. Don't change the mode of
7119 the shift or propagate MODE into the shift, though. */
7120 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7121 && INTVAL (XEXP (x, 1)) >= 0)
7123 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7124 GET_MODE (x), GEN_INT (mask),
7126 if (temp && GET_CODE(temp) == CONST_INT)
7128 force_to_mode (XEXP (x, 0), GET_MODE (x),
7129 INTVAL (temp), reg, next_select));
7134 /* If we just want the low-order bit, the NEG isn't needed since it
7135 won't change the low-order bit. */
7137 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7139 /* We need any bits less significant than the most significant bit in
7140 MASK since carries from those bits will affect the bits we are
7146 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7147 same as the XOR case above. Ensure that the constant we form is not
7148 wider than the mode of X. */
7150 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7151 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7152 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7153 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7154 < GET_MODE_BITSIZE (GET_MODE (x)))
7155 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7157 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7158 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7159 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7161 return force_to_mode (x, mode, mask, reg, next_select);
7164 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7165 use the full mask inside the NOT. */
7169 op0 = gen_lowpart_for_combine (op_mode,
7170 force_to_mode (XEXP (x, 0), mode, mask,
7172 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7173 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7177 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7178 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7179 which is equal to STORE_FLAG_VALUE. */
7180 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7181 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7182 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7183 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7188 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7189 written in a narrower mode. We play it safe and do not do so. */
7192 gen_lowpart_for_combine (GET_MODE (x),
7193 force_to_mode (XEXP (x, 1), mode,
7194 mask, reg, next_select)));
7196 gen_lowpart_for_combine (GET_MODE (x),
7197 force_to_mode (XEXP (x, 2), mode,
7198 mask, reg,next_select)));
7205 /* Ensure we return a value of the proper mode. */
7206 return gen_lowpart_for_combine (mode, x);
7209 /* Return nonzero if X is an expression that has one of two values depending on
7210 whether some other value is zero or nonzero. In that case, we return the
7211 value that is being tested, *PTRUE is set to the value if the rtx being
7212 returned has a nonzero value, and *PFALSE is set to the other alternative.
7214 If we return zero, we set *PTRUE and *PFALSE to X. */
7217 if_then_else_cond (x, ptrue, pfalse)
7219 rtx *ptrue, *pfalse;
7221 enum machine_mode mode = GET_MODE (x);
7222 enum rtx_code code = GET_CODE (x);
7223 rtx cond0, cond1, true0, true1, false0, false1;
7224 unsigned HOST_WIDE_INT nz;
7226 /* If we are comparing a value against zero, we are done. */
7227 if ((code == NE || code == EQ)
7228 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7230 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7231 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7235 /* If this is a unary operation whose operand has one of two values, apply
7236 our opcode to compute those values. */
7237 else if (GET_RTX_CLASS (code) == '1'
7238 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7240 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7241 *pfalse = simplify_gen_unary (code, mode, false0,
7242 GET_MODE (XEXP (x, 0)));
7246 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7247 make can't possibly match and would suppress other optimizations. */
7248 else if (code == COMPARE)
7251 /* If this is a binary operation, see if either side has only one of two
7252 values. If either one does or if both do and they are conditional on
7253 the same value, compute the new true and false values. */
7254 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7255 || GET_RTX_CLASS (code) == '<')
7257 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7258 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7260 if ((cond0 != 0 || cond1 != 0)
7261 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7263 /* If if_then_else_cond returned zero, then true/false are the
7264 same rtl. We must copy one of them to prevent invalid rtl
7267 true0 = copy_rtx (true0);
7268 else if (cond1 == 0)
7269 true1 = copy_rtx (true1);
7271 *ptrue = gen_binary (code, mode, true0, true1);
7272 *pfalse = gen_binary (code, mode, false0, false1);
7273 return cond0 ? cond0 : cond1;
7276 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7277 operands is zero when the other is non-zero, and vice-versa,
7278 and STORE_FLAG_VALUE is 1 or -1. */
7280 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7281 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7283 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7285 rtx op0 = XEXP (XEXP (x, 0), 1);
7286 rtx op1 = XEXP (XEXP (x, 1), 1);
7288 cond0 = XEXP (XEXP (x, 0), 0);
7289 cond1 = XEXP (XEXP (x, 1), 0);
7291 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7292 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7293 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7294 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7295 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7296 || ((swap_condition (GET_CODE (cond0))
7297 == combine_reversed_comparison_code (cond1))
7298 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7299 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7300 && ! side_effects_p (x))
7302 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7303 *pfalse = gen_binary (MULT, mode,
7305 ? simplify_gen_unary (NEG, mode, op1,
7313 /* Similarly for MULT, AND and UMIN, except that for these the result
7315 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7316 && (code == MULT || code == AND || code == UMIN)
7317 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7319 cond0 = XEXP (XEXP (x, 0), 0);
7320 cond1 = XEXP (XEXP (x, 1), 0);
7322 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7323 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7324 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7325 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7326 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7327 || ((swap_condition (GET_CODE (cond0))
7328 == combine_reversed_comparison_code (cond1))
7329 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7330 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7331 && ! side_effects_p (x))
7333 *ptrue = *pfalse = const0_rtx;
7339 else if (code == IF_THEN_ELSE)
7341 /* If we have IF_THEN_ELSE already, extract the condition and
7342 canonicalize it if it is NE or EQ. */
7343 cond0 = XEXP (x, 0);
7344 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7345 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7346 return XEXP (cond0, 0);
7347 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7349 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7350 return XEXP (cond0, 0);
7356 /* If X is a SUBREG, we can narrow both the true and false values
7357 if the inner expression, if there is a condition. */
7358 else if (code == SUBREG
7359 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7362 *ptrue = simplify_gen_subreg (mode, true0,
7363 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7364 *pfalse = simplify_gen_subreg (mode, false0,
7365 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7370 /* If X is a constant, this isn't special and will cause confusions
7371 if we treat it as such. Likewise if it is equivalent to a constant. */
7372 else if (CONSTANT_P (x)
7373 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7376 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7377 will be least confusing to the rest of the compiler. */
7378 else if (mode == BImode)
7380 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7384 /* If X is known to be either 0 or -1, those are the true and
7385 false values when testing X. */
7386 else if (x == constm1_rtx || x == const0_rtx
7387 || (mode != VOIDmode
7388 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7390 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7394 /* Likewise for 0 or a single bit. */
7395 else if (mode != VOIDmode
7396 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7397 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7399 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7403 /* Otherwise fail; show no condition with true and false values the same. */
7404 *ptrue = *pfalse = x;
7408 /* Return the value of expression X given the fact that condition COND
7409 is known to be true when applied to REG as its first operand and VAL
7410 as its second. X is known to not be shared and so can be modified in
7413 We only handle the simplest cases, and specifically those cases that
7414 arise with IF_THEN_ELSE expressions. */
7417 known_cond (x, cond, reg, val)
7422 enum rtx_code code = GET_CODE (x);
7427 if (side_effects_p (x))
7430 /* If either operand of the condition is a floating point value,
7431 then we have to avoid collapsing an EQ comparison. */
7433 && rtx_equal_p (x, reg)
7434 && ! FLOAT_MODE_P (GET_MODE (x))
7435 && ! FLOAT_MODE_P (GET_MODE (val)))
7438 if (cond == UNEQ && rtx_equal_p (x, reg))
7441 /* If X is (abs REG) and we know something about REG's relationship
7442 with zero, we may be able to simplify this. */
7444 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7447 case GE: case GT: case EQ:
7450 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7452 GET_MODE (XEXP (x, 0)));
7457 /* The only other cases we handle are MIN, MAX, and comparisons if the
7458 operands are the same as REG and VAL. */
7460 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7462 if (rtx_equal_p (XEXP (x, 0), val))
7463 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7465 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7467 if (GET_RTX_CLASS (code) == '<')
7469 if (comparison_dominates_p (cond, code))
7470 return const_true_rtx;
7472 code = combine_reversed_comparison_code (x);
7474 && comparison_dominates_p (cond, code))
7479 else if (code == SMAX || code == SMIN
7480 || code == UMIN || code == UMAX)
7482 int unsignedp = (code == UMIN || code == UMAX);
7484 /* Do not reverse the condition when it is NE or EQ.
7485 This is because we cannot conclude anything about
7486 the value of 'SMAX (x, y)' when x is not equal to y,
7487 but we can when x equals y. */
7488 if ((code == SMAX || code == UMAX)
7489 && ! (cond == EQ || cond == NE))
7490 cond = reverse_condition (cond);
7495 return unsignedp ? x : XEXP (x, 1);
7497 return unsignedp ? x : XEXP (x, 0);
7499 return unsignedp ? XEXP (x, 1) : x;
7501 return unsignedp ? XEXP (x, 0) : x;
7508 else if (code == SUBREG)
7510 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7511 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7513 if (SUBREG_REG (x) != r)
7515 /* We must simplify subreg here, before we lose track of the
7516 original inner_mode. */
7517 new = simplify_subreg (GET_MODE (x), r,
7518 inner_mode, SUBREG_BYTE (x));
7522 SUBST (SUBREG_REG (x), r);
7527 /* We don't have to handle SIGN_EXTEND here, because even in the
7528 case of replacing something with a modeless CONST_INT, a
7529 CONST_INT is already (supposed to be) a valid sign extension for
7530 its narrower mode, which implies it's already properly
7531 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7532 story is different. */
7533 else if (code == ZERO_EXTEND)
7535 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7536 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7538 if (XEXP (x, 0) != r)
7540 /* We must simplify the zero_extend here, before we lose
7541 track of the original inner_mode. */
7542 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7547 SUBST (XEXP (x, 0), r);
7553 fmt = GET_RTX_FORMAT (code);
7554 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7557 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7558 else if (fmt[i] == 'E')
7559 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7560 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7567 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7568 assignment as a field assignment. */
7571 rtx_equal_for_field_assignment_p (x, y)
7575 if (x == y || rtx_equal_p (x, y))
7578 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7581 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7582 Note that all SUBREGs of MEM are paradoxical; otherwise they
7583 would have been rewritten. */
7584 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7585 && GET_CODE (SUBREG_REG (y)) == MEM
7586 && rtx_equal_p (SUBREG_REG (y),
7587 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7590 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7591 && GET_CODE (SUBREG_REG (x)) == MEM
7592 && rtx_equal_p (SUBREG_REG (x),
7593 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7596 /* We used to see if get_last_value of X and Y were the same but that's
7597 not correct. In one direction, we'll cause the assignment to have
7598 the wrong destination and in the case, we'll import a register into this
7599 insn that might have already have been dead. So fail if none of the
7600 above cases are true. */
7604 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7605 Return that assignment if so.
7607 We only handle the most common cases. */
7610 make_field_assignment (x)
7613 rtx dest = SET_DEST (x);
7614 rtx src = SET_SRC (x);
7619 unsigned HOST_WIDE_INT len;
7621 enum machine_mode mode;
7623 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7624 a clear of a one-bit field. We will have changed it to
7625 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7628 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7629 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7630 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7631 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7633 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7636 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7640 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7641 && subreg_lowpart_p (XEXP (src, 0))
7642 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7643 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7644 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7645 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7646 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7648 assign = make_extraction (VOIDmode, dest, 0,
7649 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7652 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7656 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7658 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7659 && XEXP (XEXP (src, 0), 0) == const1_rtx
7660 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7662 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7665 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7669 /* The other case we handle is assignments into a constant-position
7670 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7671 a mask that has all one bits except for a group of zero bits and
7672 OTHER is known to have zeros where C1 has ones, this is such an
7673 assignment. Compute the position and length from C1. Shift OTHER
7674 to the appropriate position, force it to the required mode, and
7675 make the extraction. Check for the AND in both operands. */
7677 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7680 rhs = expand_compound_operation (XEXP (src, 0));
7681 lhs = expand_compound_operation (XEXP (src, 1));
7683 if (GET_CODE (rhs) == AND
7684 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7685 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7686 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7687 else if (GET_CODE (lhs) == AND
7688 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7689 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7690 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7694 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7695 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7696 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7697 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7700 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7704 /* The mode to use for the source is the mode of the assignment, or of
7705 what is inside a possible STRICT_LOW_PART. */
7706 mode = (GET_CODE (assign) == STRICT_LOW_PART
7707 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7709 /* Shift OTHER right POS places and make it the source, restricting it
7710 to the proper length and mode. */
7712 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7713 GET_MODE (src), other, pos),
7715 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7716 ? ~(unsigned HOST_WIDE_INT) 0
7717 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7720 return gen_rtx_SET (VOIDmode, assign, src);
7723 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7727 apply_distributive_law (x)
7730 enum rtx_code code = GET_CODE (x);
7731 rtx lhs, rhs, other;
7733 enum rtx_code inner_code;
7735 /* Distributivity is not true for floating point.
7736 It can change the value. So don't do it.
7737 -- rms and moshier@world.std.com. */
7738 if (FLOAT_MODE_P (GET_MODE (x)))
7741 /* The outer operation can only be one of the following: */
7742 if (code != IOR && code != AND && code != XOR
7743 && code != PLUS && code != MINUS)
7746 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7748 /* If either operand is a primitive we can't do anything, so get out
7750 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7751 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7754 lhs = expand_compound_operation (lhs);
7755 rhs = expand_compound_operation (rhs);
7756 inner_code = GET_CODE (lhs);
7757 if (inner_code != GET_CODE (rhs))
7760 /* See if the inner and outer operations distribute. */
7767 /* These all distribute except over PLUS. */
7768 if (code == PLUS || code == MINUS)
7773 if (code != PLUS && code != MINUS)
7778 /* This is also a multiply, so it distributes over everything. */
7782 /* Non-paradoxical SUBREGs distributes over all operations, provided
7783 the inner modes and byte offsets are the same, this is an extraction
7784 of a low-order part, we don't convert an fp operation to int or
7785 vice versa, and we would not be converting a single-word
7786 operation into a multi-word operation. The latter test is not
7787 required, but it prevents generating unneeded multi-word operations.
7788 Some of the previous tests are redundant given the latter test, but
7789 are retained because they are required for correctness.
7791 We produce the result slightly differently in this case. */
7793 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7794 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7795 || ! subreg_lowpart_p (lhs)
7796 || (GET_MODE_CLASS (GET_MODE (lhs))
7797 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7798 || (GET_MODE_SIZE (GET_MODE (lhs))
7799 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7800 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7803 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7804 SUBREG_REG (lhs), SUBREG_REG (rhs));
7805 return gen_lowpart_for_combine (GET_MODE (x), tem);
7811 /* Set LHS and RHS to the inner operands (A and B in the example
7812 above) and set OTHER to the common operand (C in the example).
7813 These is only one way to do this unless the inner operation is
7815 if (GET_RTX_CLASS (inner_code) == 'c'
7816 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7817 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7818 else if (GET_RTX_CLASS (inner_code) == 'c'
7819 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7820 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7821 else if (GET_RTX_CLASS (inner_code) == 'c'
7822 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7823 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7824 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7825 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7829 /* Form the new inner operation, seeing if it simplifies first. */
7830 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7832 /* There is one exception to the general way of distributing:
7833 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7834 if (code == XOR && inner_code == IOR)
7837 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7840 /* We may be able to continuing distributing the result, so call
7841 ourselves recursively on the inner operation before forming the
7842 outer operation, which we return. */
7843 return gen_binary (inner_code, GET_MODE (x),
7844 apply_distributive_law (tem), other);
7847 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7850 Return an equivalent form, if different from X. Otherwise, return X. If
7851 X is zero, we are to always construct the equivalent form. */
7854 simplify_and_const_int (x, mode, varop, constop)
7856 enum machine_mode mode;
7858 unsigned HOST_WIDE_INT constop;
7860 unsigned HOST_WIDE_INT nonzero;
7863 /* Simplify VAROP knowing that we will be only looking at some of the
7866 Note by passing in CONSTOP, we guarantee that the bits not set in
7867 CONSTOP are not significant and will never be examined. We must
7868 ensure that is the case by explicitly masking out those bits
7869 before returning. */
7870 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7872 /* If VAROP is a CLOBBER, we will fail so return it. */
7873 if (GET_CODE (varop) == CLOBBER)
7876 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7877 to VAROP and return the new constant. */
7878 if (GET_CODE (varop) == CONST_INT)
7879 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7881 /* See what bits may be nonzero in VAROP. Unlike the general case of
7882 a call to nonzero_bits, here we don't care about bits outside
7885 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7887 /* Turn off all bits in the constant that are known to already be zero.
7888 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7889 which is tested below. */
7893 /* If we don't have any bits left, return zero. */
7897 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7898 a power of two, we can replace this with an ASHIFT. */
7899 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7900 && (i = exact_log2 (constop)) >= 0)
7901 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7903 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7904 or XOR, then try to apply the distributive law. This may eliminate
7905 operations if either branch can be simplified because of the AND.
7906 It may also make some cases more complex, but those cases probably
7907 won't match a pattern either with or without this. */
7909 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7911 gen_lowpart_for_combine
7913 apply_distributive_law
7914 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7915 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7916 XEXP (varop, 0), constop),
7917 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7918 XEXP (varop, 1), constop))));
7920 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7921 the AND and see if one of the operands simplifies to zero. If so, we
7922 may eliminate it. */
7924 if (GET_CODE (varop) == PLUS
7925 && exact_log2 (constop + 1) >= 0)
7929 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7930 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7931 if (o0 == const0_rtx)
7933 if (o1 == const0_rtx)
7937 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7938 if we already had one (just check for the simplest cases). */
7939 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7940 && GET_MODE (XEXP (x, 0)) == mode
7941 && SUBREG_REG (XEXP (x, 0)) == varop)
7942 varop = XEXP (x, 0);
7944 varop = gen_lowpart_for_combine (mode, varop);
7946 /* If we can't make the SUBREG, try to return what we were given. */
7947 if (GET_CODE (varop) == CLOBBER)
7948 return x ? x : varop;
7950 /* If we are only masking insignificant bits, return VAROP. */
7951 if (constop == nonzero)
7955 /* Otherwise, return an AND. */
7956 constop = trunc_int_for_mode (constop, mode);
7957 /* See how much, if any, of X we can use. */
7958 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7959 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7963 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7964 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7965 SUBST (XEXP (x, 1), GEN_INT (constop));
7967 SUBST (XEXP (x, 0), varop);
7974 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7975 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7976 is less useful. We can't allow both, because that results in exponential
7977 run time recursion. There is a nullstone testcase that triggered
7978 this. This macro avoids accidental uses of num_sign_bit_copies. */
7979 #define num_sign_bit_copies()
7981 /* Given an expression, X, compute which bits in X can be non-zero.
7982 We don't care about bits outside of those defined in MODE.
7984 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7985 a shift, AND, or zero_extract, we can do better. */
7987 static unsigned HOST_WIDE_INT
7988 nonzero_bits (x, mode)
7990 enum machine_mode mode;
7992 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7993 unsigned HOST_WIDE_INT inner_nz;
7995 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7998 /* For floating-point values, assume all bits are needed. */
7999 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8002 /* If X is wider than MODE, use its mode instead. */
8003 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8005 mode = GET_MODE (x);
8006 nonzero = GET_MODE_MASK (mode);
8007 mode_width = GET_MODE_BITSIZE (mode);
8010 if (mode_width > HOST_BITS_PER_WIDE_INT)
8011 /* Our only callers in this case look for single bit values. So
8012 just return the mode mask. Those tests will then be false. */
8015 #ifndef WORD_REGISTER_OPERATIONS
8016 /* If MODE is wider than X, but both are a single word for both the host
8017 and target machines, we can compute this from which bits of the
8018 object might be nonzero in its own mode, taking into account the fact
8019 that on many CISC machines, accessing an object in a wider mode
8020 causes the high-order bits to become undefined. So they are
8021 not known to be zero. */
8023 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8024 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8025 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8026 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8028 nonzero &= nonzero_bits (x, GET_MODE (x));
8029 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8034 code = GET_CODE (x);
8038 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8039 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8040 all the bits above ptr_mode are known to be zero. */
8041 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8043 nonzero &= GET_MODE_MASK (ptr_mode);
8046 /* Include declared information about alignment of pointers. */
8047 /* ??? We don't properly preserve REG_POINTER changes across
8048 pointer-to-integer casts, so we can't trust it except for
8049 things that we know must be pointers. See execute/960116-1.c. */
8050 if ((x == stack_pointer_rtx
8051 || x == frame_pointer_rtx
8052 || x == arg_pointer_rtx)
8053 && REGNO_POINTER_ALIGN (REGNO (x)))
8055 unsigned HOST_WIDE_INT alignment
8056 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8058 #ifdef PUSH_ROUNDING
8059 /* If PUSH_ROUNDING is defined, it is possible for the
8060 stack to be momentarily aligned only to that amount,
8061 so we pick the least alignment. */
8062 if (x == stack_pointer_rtx && PUSH_ARGS)
8063 alignment = MIN (PUSH_ROUNDING (1), alignment);
8066 nonzero &= ~(alignment - 1);
8069 /* If X is a register whose nonzero bits value is current, use it.
8070 Otherwise, if X is a register whose value we can find, use that
8071 value. Otherwise, use the previously-computed global nonzero bits
8072 for this register. */
8074 if (reg_last_set_value[REGNO (x)] != 0
8075 && (reg_last_set_mode[REGNO (x)] == mode
8076 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8077 && GET_MODE_CLASS (mode) == MODE_INT))
8078 && (reg_last_set_label[REGNO (x)] == label_tick
8079 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8080 && REG_N_SETS (REGNO (x)) == 1
8081 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8083 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8084 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8086 tem = get_last_value (x);
8090 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8091 /* If X is narrower than MODE and TEM is a non-negative
8092 constant that would appear negative in the mode of X,
8093 sign-extend it for use in reg_nonzero_bits because some
8094 machines (maybe most) will actually do the sign-extension
8095 and this is the conservative approach.
8097 ??? For 2.5, try to tighten up the MD files in this regard
8098 instead of this kludge. */
8100 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8101 && GET_CODE (tem) == CONST_INT
8103 && 0 != (INTVAL (tem)
8104 & ((HOST_WIDE_INT) 1
8105 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8106 tem = GEN_INT (INTVAL (tem)
8107 | ((HOST_WIDE_INT) (-1)
8108 << GET_MODE_BITSIZE (GET_MODE (x))));
8110 return nonzero_bits (tem, mode) & nonzero;
8112 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8114 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8116 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8117 /* We don't know anything about the upper bits. */
8118 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8119 return nonzero & mask;
8125 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8126 /* If X is negative in MODE, sign-extend the value. */
8127 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8128 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8129 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8135 #ifdef LOAD_EXTEND_OP
8136 /* In many, if not most, RISC machines, reading a byte from memory
8137 zeros the rest of the register. Noticing that fact saves a lot
8138 of extra zero-extends. */
8139 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8140 nonzero &= GET_MODE_MASK (GET_MODE (x));
8145 case UNEQ: case LTGT:
8146 case GT: case GTU: case UNGT:
8147 case LT: case LTU: case UNLT:
8148 case GE: case GEU: case UNGE:
8149 case LE: case LEU: case UNLE:
8150 case UNORDERED: case ORDERED:
8152 /* If this produces an integer result, we know which bits are set.
8153 Code here used to clear bits outside the mode of X, but that is
8156 if (GET_MODE_CLASS (mode) == MODE_INT
8157 && mode_width <= HOST_BITS_PER_WIDE_INT)
8158 nonzero = STORE_FLAG_VALUE;
8163 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8164 and num_sign_bit_copies. */
8165 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8166 == GET_MODE_BITSIZE (GET_MODE (x)))
8170 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8171 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8176 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8177 and num_sign_bit_copies. */
8178 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8179 == GET_MODE_BITSIZE (GET_MODE (x)))
8185 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8189 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8190 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8191 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8195 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8196 Otherwise, show all the bits in the outer mode but not the inner
8198 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8199 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8201 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8203 & (((HOST_WIDE_INT) 1
8204 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8205 inner_nz |= (GET_MODE_MASK (mode)
8206 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8209 nonzero &= inner_nz;
8213 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8214 & nonzero_bits (XEXP (x, 1), mode));
8218 case UMIN: case UMAX: case SMIN: case SMAX:
8220 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8222 /* Don't call nonzero_bits for the second time if it cannot change
8224 if ((nonzero & nonzero0) != nonzero)
8225 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8229 case PLUS: case MINUS:
8231 case DIV: case UDIV:
8232 case MOD: case UMOD:
8233 /* We can apply the rules of arithmetic to compute the number of
8234 high- and low-order zero bits of these operations. We start by
8235 computing the width (position of the highest-order non-zero bit)
8236 and the number of low-order zero bits for each value. */
8238 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8239 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8240 int width0 = floor_log2 (nz0) + 1;
8241 int width1 = floor_log2 (nz1) + 1;
8242 int low0 = floor_log2 (nz0 & -nz0);
8243 int low1 = floor_log2 (nz1 & -nz1);
8244 HOST_WIDE_INT op0_maybe_minusp
8245 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8246 HOST_WIDE_INT op1_maybe_minusp
8247 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8248 unsigned int result_width = mode_width;
8254 result_width = MAX (width0, width1) + 1;
8255 result_low = MIN (low0, low1);
8258 result_low = MIN (low0, low1);
8261 result_width = width0 + width1;
8262 result_low = low0 + low1;
8267 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8268 result_width = width0;
8273 result_width = width0;
8278 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8279 result_width = MIN (width0, width1);
8280 result_low = MIN (low0, low1);
8285 result_width = MIN (width0, width1);
8286 result_low = MIN (low0, low1);
8292 if (result_width < mode_width)
8293 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8296 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8298 #ifdef POINTERS_EXTEND_UNSIGNED
8299 /* If pointers extend unsigned and this is an addition or subtraction
8300 to a pointer in Pmode, all the bits above ptr_mode are known to be
8302 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8303 && (code == PLUS || code == MINUS)
8304 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8305 nonzero &= GET_MODE_MASK (ptr_mode);
8311 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8312 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8313 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8317 /* If this is a SUBREG formed for a promoted variable that has
8318 been zero-extended, we know that at least the high-order bits
8319 are zero, though others might be too. */
8321 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8322 nonzero = (GET_MODE_MASK (GET_MODE (x))
8323 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8325 /* If the inner mode is a single word for both the host and target
8326 machines, we can compute this from which bits of the inner
8327 object might be nonzero. */
8328 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8329 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8330 <= HOST_BITS_PER_WIDE_INT))
8332 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8334 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8335 /* If this is a typical RISC machine, we only have to worry
8336 about the way loads are extended. */
8337 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8339 & (((unsigned HOST_WIDE_INT) 1
8340 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8342 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8345 /* On many CISC machines, accessing an object in a wider mode
8346 causes the high-order bits to become undefined. So they are
8347 not known to be zero. */
8348 if (GET_MODE_SIZE (GET_MODE (x))
8349 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8350 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8351 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8360 /* The nonzero bits are in two classes: any bits within MODE
8361 that aren't in GET_MODE (x) are always significant. The rest of the
8362 nonzero bits are those that are significant in the operand of
8363 the shift when shifted the appropriate number of bits. This
8364 shows that high-order bits are cleared by the right shift and
8365 low-order bits by left shifts. */
8366 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8367 && INTVAL (XEXP (x, 1)) >= 0
8368 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8370 enum machine_mode inner_mode = GET_MODE (x);
8371 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8372 int count = INTVAL (XEXP (x, 1));
8373 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8374 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8375 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8376 unsigned HOST_WIDE_INT outer = 0;
8378 if (mode_width > width)
8379 outer = (op_nonzero & nonzero & ~mode_mask);
8381 if (code == LSHIFTRT)
8383 else if (code == ASHIFTRT)
8387 /* If the sign bit may have been nonzero before the shift, we
8388 need to mark all the places it could have been copied to
8389 by the shift as possibly nonzero. */
8390 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8391 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8393 else if (code == ASHIFT)
8396 inner = ((inner << (count % width)
8397 | (inner >> (width - (count % width)))) & mode_mask);
8399 nonzero &= (outer | inner);
8404 /* This is at most the number of bits in the mode. */
8405 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8409 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8410 | nonzero_bits (XEXP (x, 2), mode));
8420 /* See the macro definition above. */
8421 #undef num_sign_bit_copies
8423 /* Return the number of bits at the high-order end of X that are known to
8424 be equal to the sign bit. X will be used in mode MODE; if MODE is
8425 VOIDmode, X will be used in its own mode. The returned value will always
8426 be between 1 and the number of bits in MODE. */
8429 num_sign_bit_copies (x, mode)
8431 enum machine_mode mode;
8433 enum rtx_code code = GET_CODE (x);
8434 unsigned int bitwidth;
8435 int num0, num1, result;
8436 unsigned HOST_WIDE_INT nonzero;
8439 /* If we weren't given a mode, use the mode of X. If the mode is still
8440 VOIDmode, we don't know anything. Likewise if one of the modes is
8443 if (mode == VOIDmode)
8444 mode = GET_MODE (x);
8446 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8449 bitwidth = GET_MODE_BITSIZE (mode);
8451 /* For a smaller object, just ignore the high bits. */
8452 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8454 num0 = num_sign_bit_copies (x, GET_MODE (x));
8456 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8459 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8461 #ifndef WORD_REGISTER_OPERATIONS
8462 /* If this machine does not do all register operations on the entire
8463 register and MODE is wider than the mode of X, we can say nothing
8464 at all about the high-order bits. */
8467 /* Likewise on machines that do, if the mode of the object is smaller
8468 than a word and loads of that size don't sign extend, we can say
8469 nothing about the high order bits. */
8470 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8471 #ifdef LOAD_EXTEND_OP
8472 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8483 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8484 /* If pointers extend signed and this is a pointer in Pmode, say that
8485 all the bits above ptr_mode are known to be sign bit copies. */
8486 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8488 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8491 if (reg_last_set_value[REGNO (x)] != 0
8492 && reg_last_set_mode[REGNO (x)] == mode
8493 && (reg_last_set_label[REGNO (x)] == label_tick
8494 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8495 && REG_N_SETS (REGNO (x)) == 1
8496 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8498 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8499 return reg_last_set_sign_bit_copies[REGNO (x)];
8501 tem = get_last_value (x);
8503 return num_sign_bit_copies (tem, mode);
8505 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8506 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8507 return reg_sign_bit_copies[REGNO (x)];
8511 #ifdef LOAD_EXTEND_OP
8512 /* Some RISC machines sign-extend all loads of smaller than a word. */
8513 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8514 return MAX (1, ((int) bitwidth
8515 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8520 /* If the constant is negative, take its 1's complement and remask.
8521 Then see how many zero bits we have. */
8522 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8523 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8524 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8525 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8527 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8530 /* If this is a SUBREG for a promoted object that is sign-extended
8531 and we are looking at it in a wider mode, we know that at least the
8532 high-order bits are known to be sign bit copies. */
8534 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8536 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8537 return MAX ((int) bitwidth
8538 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8542 /* For a smaller object, just ignore the high bits. */
8543 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8545 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8546 return MAX (1, (num0
8547 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8551 #ifdef WORD_REGISTER_OPERATIONS
8552 #ifdef LOAD_EXTEND_OP
8553 /* For paradoxical SUBREGs on machines where all register operations
8554 affect the entire register, just look inside. Note that we are
8555 passing MODE to the recursive call, so the number of sign bit copies
8556 will remain relative to that mode, not the inner mode. */
8558 /* This works only if loads sign extend. Otherwise, if we get a
8559 reload for the inner part, it may be loaded from the stack, and
8560 then we lose all sign bit copies that existed before the store
8563 if ((GET_MODE_SIZE (GET_MODE (x))
8564 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8565 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8566 return num_sign_bit_copies (SUBREG_REG (x), mode);
8572 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8573 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8577 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8578 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8581 /* For a smaller object, just ignore the high bits. */
8582 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8583 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8587 return num_sign_bit_copies (XEXP (x, 0), mode);
8589 case ROTATE: case ROTATERT:
8590 /* If we are rotating left by a number of bits less than the number
8591 of sign bit copies, we can just subtract that amount from the
8593 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8594 && INTVAL (XEXP (x, 1)) >= 0
8595 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8597 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8598 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8599 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8604 /* In general, this subtracts one sign bit copy. But if the value
8605 is known to be positive, the number of sign bit copies is the
8606 same as that of the input. Finally, if the input has just one bit
8607 that might be nonzero, all the bits are copies of the sign bit. */
8608 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8609 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8610 return num0 > 1 ? num0 - 1 : 1;
8612 nonzero = nonzero_bits (XEXP (x, 0), mode);
8617 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8622 case IOR: case AND: case XOR:
8623 case SMIN: case SMAX: case UMIN: case UMAX:
8624 /* Logical operations will preserve the number of sign-bit copies.
8625 MIN and MAX operations always return one of the operands. */
8626 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8627 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8628 return MIN (num0, num1);
8630 case PLUS: case MINUS:
8631 /* For addition and subtraction, we can have a 1-bit carry. However,
8632 if we are subtracting 1 from a positive number, there will not
8633 be such a carry. Furthermore, if the positive number is known to
8634 be 0 or 1, we know the result is either -1 or 0. */
8636 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8637 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8639 nonzero = nonzero_bits (XEXP (x, 0), mode);
8640 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8641 return (nonzero == 1 || nonzero == 0 ? bitwidth
8642 : bitwidth - floor_log2 (nonzero) - 1);
8645 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8646 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8647 result = MAX (1, MIN (num0, num1) - 1);
8649 #ifdef POINTERS_EXTEND_UNSIGNED
8650 /* If pointers extend signed and this is an addition or subtraction
8651 to a pointer in Pmode, all the bits above ptr_mode are known to be
8653 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8654 && (code == PLUS || code == MINUS)
8655 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8656 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8657 - GET_MODE_BITSIZE (ptr_mode) + 1),
8663 /* The number of bits of the product is the sum of the number of
8664 bits of both terms. However, unless one of the terms if known
8665 to be positive, we must allow for an additional bit since negating
8666 a negative number can remove one sign bit copy. */
8668 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8669 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8671 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8673 && (bitwidth > HOST_BITS_PER_WIDE_INT
8674 || (((nonzero_bits (XEXP (x, 0), mode)
8675 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8676 && ((nonzero_bits (XEXP (x, 1), mode)
8677 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8680 return MAX (1, result);
8683 /* The result must be <= the first operand. If the first operand
8684 has the high bit set, we know nothing about the number of sign
8686 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8688 else if ((nonzero_bits (XEXP (x, 0), mode)
8689 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8692 return num_sign_bit_copies (XEXP (x, 0), mode);
8695 /* The result must be <= the second operand. */
8696 return num_sign_bit_copies (XEXP (x, 1), mode);
8699 /* Similar to unsigned division, except that we have to worry about
8700 the case where the divisor is negative, in which case we have
8702 result = num_sign_bit_copies (XEXP (x, 0), mode);
8704 && (bitwidth > HOST_BITS_PER_WIDE_INT
8705 || (nonzero_bits (XEXP (x, 1), mode)
8706 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8712 result = num_sign_bit_copies (XEXP (x, 1), mode);
8714 && (bitwidth > HOST_BITS_PER_WIDE_INT
8715 || (nonzero_bits (XEXP (x, 1), mode)
8716 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8722 /* Shifts by a constant add to the number of bits equal to the
8724 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8725 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8726 && INTVAL (XEXP (x, 1)) > 0)
8727 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8732 /* Left shifts destroy copies. */
8733 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8734 || INTVAL (XEXP (x, 1)) < 0
8735 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8738 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8739 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8742 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8743 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8744 return MIN (num0, num1);
8746 case EQ: case NE: case GE: case GT: case LE: case LT:
8747 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8748 case GEU: case GTU: case LEU: case LTU:
8749 case UNORDERED: case ORDERED:
8750 /* If the constant is negative, take its 1's complement and remask.
8751 Then see how many zero bits we have. */
8752 nonzero = STORE_FLAG_VALUE;
8753 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8754 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8755 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8757 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8764 /* If we haven't been able to figure it out by one of the above rules,
8765 see if some of the high-order bits are known to be zero. If so,
8766 count those bits and return one less than that amount. If we can't
8767 safely compute the mask for this mode, always return BITWIDTH. */
8769 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8772 nonzero = nonzero_bits (x, mode);
8773 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8774 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8777 /* Return the number of "extended" bits there are in X, when interpreted
8778 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8779 unsigned quantities, this is the number of high-order zero bits.
8780 For signed quantities, this is the number of copies of the sign bit
8781 minus 1. In both case, this function returns the number of "spare"
8782 bits. For example, if two quantities for which this function returns
8783 at least 1 are added, the addition is known not to overflow.
8785 This function will always return 0 unless called during combine, which
8786 implies that it must be called from a define_split. */
8789 extended_count (x, mode, unsignedp)
8791 enum machine_mode mode;
8794 if (nonzero_sign_valid == 0)
8798 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8799 ? (GET_MODE_BITSIZE (mode) - 1
8800 - floor_log2 (nonzero_bits (x, mode)))
8802 : num_sign_bit_copies (x, mode) - 1);
8805 /* This function is called from `simplify_shift_const' to merge two
8806 outer operations. Specifically, we have already found that we need
8807 to perform operation *POP0 with constant *PCONST0 at the outermost
8808 position. We would now like to also perform OP1 with constant CONST1
8809 (with *POP0 being done last).
8811 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8812 the resulting operation. *PCOMP_P is set to 1 if we would need to
8813 complement the innermost operand, otherwise it is unchanged.
8815 MODE is the mode in which the operation will be done. No bits outside
8816 the width of this mode matter. It is assumed that the width of this mode
8817 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8819 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8820 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8821 result is simply *PCONST0.
8823 If the resulting operation cannot be expressed as one operation, we
8824 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8827 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8828 enum rtx_code *pop0;
8829 HOST_WIDE_INT *pconst0;
8831 HOST_WIDE_INT const1;
8832 enum machine_mode mode;
8835 enum rtx_code op0 = *pop0;
8836 HOST_WIDE_INT const0 = *pconst0;
8838 const0 &= GET_MODE_MASK (mode);
8839 const1 &= GET_MODE_MASK (mode);
8841 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8845 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8848 if (op1 == NIL || op0 == SET)
8851 else if (op0 == NIL)
8852 op0 = op1, const0 = const1;
8854 else if (op0 == op1)
8878 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8879 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8882 /* If the two constants aren't the same, we can't do anything. The
8883 remaining six cases can all be done. */
8884 else if (const0 != const1)
8892 /* (a & b) | b == b */
8894 else /* op1 == XOR */
8895 /* (a ^ b) | b == a | b */
8901 /* (a & b) ^ b == (~a) & b */
8902 op0 = AND, *pcomp_p = 1;
8903 else /* op1 == IOR */
8904 /* (a | b) ^ b == a & ~b */
8905 op0 = AND, *pconst0 = ~const0;
8910 /* (a | b) & b == b */
8912 else /* op1 == XOR */
8913 /* (a ^ b) & b) == (~a) & b */
8920 /* Check for NO-OP cases. */
8921 const0 &= GET_MODE_MASK (mode);
8923 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8925 else if (const0 == 0 && op0 == AND)
8927 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8931 /* ??? Slightly redundant with the above mask, but not entirely.
8932 Moving this above means we'd have to sign-extend the mode mask
8933 for the final test. */
8934 const0 = trunc_int_for_mode (const0, mode);
8942 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8943 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8944 that we started with.
8946 The shift is normally computed in the widest mode we find in VAROP, as
8947 long as it isn't a different number of words than RESULT_MODE. Exceptions
8948 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8951 simplify_shift_const (x, code, result_mode, varop, orig_count)
8954 enum machine_mode result_mode;
8958 enum rtx_code orig_code = code;
8961 enum machine_mode mode = result_mode;
8962 enum machine_mode shift_mode, tmode;
8963 unsigned int mode_words
8964 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8965 /* We form (outer_op (code varop count) (outer_const)). */
8966 enum rtx_code outer_op = NIL;
8967 HOST_WIDE_INT outer_const = 0;
8969 int complement_p = 0;
8972 /* Make sure and truncate the "natural" shift on the way in. We don't
8973 want to do this inside the loop as it makes it more difficult to
8975 #ifdef SHIFT_COUNT_TRUNCATED
8976 if (SHIFT_COUNT_TRUNCATED)
8977 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8980 /* If we were given an invalid count, don't do anything except exactly
8981 what was requested. */
8983 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8988 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8993 /* Unless one of the branches of the `if' in this loop does a `continue',
8994 we will `break' the loop after the `if'. */
8998 /* If we have an operand of (clobber (const_int 0)), just return that
9000 if (GET_CODE (varop) == CLOBBER)
9003 /* If we discovered we had to complement VAROP, leave. Making a NOT
9004 here would cause an infinite loop. */
9008 /* Convert ROTATERT to ROTATE. */
9009 if (code == ROTATERT)
9010 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
9012 /* We need to determine what mode we will do the shift in. If the
9013 shift is a right shift or a ROTATE, we must always do it in the mode
9014 it was originally done in. Otherwise, we can do it in MODE, the
9015 widest mode encountered. */
9017 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9018 ? result_mode : mode);
9020 /* Handle cases where the count is greater than the size of the mode
9021 minus 1. For ASHIFT, use the size minus one as the count (this can
9022 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9023 take the count modulo the size. For other shifts, the result is
9026 Since these shifts are being produced by the compiler by combining
9027 multiple operations, each of which are defined, we know what the
9028 result is supposed to be. */
9030 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
9032 if (code == ASHIFTRT)
9033 count = GET_MODE_BITSIZE (shift_mode) - 1;
9034 else if (code == ROTATE || code == ROTATERT)
9035 count %= GET_MODE_BITSIZE (shift_mode);
9038 /* We can't simply return zero because there may be an
9046 /* An arithmetic right shift of a quantity known to be -1 or 0
9048 if (code == ASHIFTRT
9049 && (num_sign_bit_copies (varop, shift_mode)
9050 == GET_MODE_BITSIZE (shift_mode)))
9056 /* If we are doing an arithmetic right shift and discarding all but
9057 the sign bit copies, this is equivalent to doing a shift by the
9058 bitsize minus one. Convert it into that shift because it will often
9059 allow other simplifications. */
9061 if (code == ASHIFTRT
9062 && (count + num_sign_bit_copies (varop, shift_mode)
9063 >= GET_MODE_BITSIZE (shift_mode)))
9064 count = GET_MODE_BITSIZE (shift_mode) - 1;
9066 /* We simplify the tests below and elsewhere by converting
9067 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9068 `make_compound_operation' will convert it to an ASHIFTRT for
9069 those machines (such as VAX) that don't have an LSHIFTRT. */
9070 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9072 && ((nonzero_bits (varop, shift_mode)
9073 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9077 switch (GET_CODE (varop))
9083 new = expand_compound_operation (varop);
9092 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9093 minus the width of a smaller mode, we can do this with a
9094 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9095 if ((code == ASHIFTRT || code == LSHIFTRT)
9096 && ! mode_dependent_address_p (XEXP (varop, 0))
9097 && ! MEM_VOLATILE_P (varop)
9098 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9099 MODE_INT, 1)) != BLKmode)
9101 new = adjust_address_nv (varop, tmode,
9102 BYTES_BIG_ENDIAN ? 0
9103 : count / BITS_PER_UNIT);
9105 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9106 : ZERO_EXTEND, mode, new);
9113 /* Similar to the case above, except that we can only do this if
9114 the resulting mode is the same as that of the underlying
9115 MEM and adjust the address depending on the *bits* endianness
9116 because of the way that bit-field extract insns are defined. */
9117 if ((code == ASHIFTRT || code == LSHIFTRT)
9118 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9119 MODE_INT, 1)) != BLKmode
9120 && tmode == GET_MODE (XEXP (varop, 0)))
9122 if (BITS_BIG_ENDIAN)
9123 new = XEXP (varop, 0);
9126 new = copy_rtx (XEXP (varop, 0));
9127 SUBST (XEXP (new, 0),
9128 plus_constant (XEXP (new, 0),
9129 count / BITS_PER_UNIT));
9132 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9133 : ZERO_EXTEND, mode, new);
9140 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9141 the same number of words as what we've seen so far. Then store
9142 the widest mode in MODE. */
9143 if (subreg_lowpart_p (varop)
9144 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9145 > GET_MODE_SIZE (GET_MODE (varop)))
9146 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9147 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9150 varop = SUBREG_REG (varop);
9151 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9152 mode = GET_MODE (varop);
9158 /* Some machines use MULT instead of ASHIFT because MULT
9159 is cheaper. But it is still better on those machines to
9160 merge two shifts into one. */
9161 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9162 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9165 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9166 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9172 /* Similar, for when divides are cheaper. */
9173 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9174 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9177 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9178 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9184 /* If we are extracting just the sign bit of an arithmetic
9185 right shift, that shift is not needed. However, the sign
9186 bit of a wider mode may be different from what would be
9187 interpreted as the sign bit in a narrower mode, so, if
9188 the result is narrower, don't discard the shift. */
9189 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9190 && (GET_MODE_BITSIZE (result_mode)
9191 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9193 varop = XEXP (varop, 0);
9197 /* ... fall through ... */
9202 /* Here we have two nested shifts. The result is usually the
9203 AND of a new shift with a mask. We compute the result below. */
9204 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9205 && INTVAL (XEXP (varop, 1)) >= 0
9206 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9207 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9208 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9210 enum rtx_code first_code = GET_CODE (varop);
9211 unsigned int first_count = INTVAL (XEXP (varop, 1));
9212 unsigned HOST_WIDE_INT mask;
9215 /* We have one common special case. We can't do any merging if
9216 the inner code is an ASHIFTRT of a smaller mode. However, if
9217 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9218 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9219 we can convert it to
9220 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9221 This simplifies certain SIGN_EXTEND operations. */
9222 if (code == ASHIFT && first_code == ASHIFTRT
9223 && (GET_MODE_BITSIZE (result_mode)
9224 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9226 /* C3 has the low-order C1 bits zero. */
9228 mask = (GET_MODE_MASK (mode)
9229 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9231 varop = simplify_and_const_int (NULL_RTX, result_mode,
9232 XEXP (varop, 0), mask);
9233 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9235 count = first_count;
9240 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9241 than C1 high-order bits equal to the sign bit, we can convert
9242 this to either an ASHIFT or an ASHIFTRT depending on the
9245 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9247 if (code == ASHIFTRT && first_code == ASHIFT
9248 && GET_MODE (varop) == shift_mode
9249 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9252 varop = XEXP (varop, 0);
9254 signed_count = count - first_count;
9255 if (signed_count < 0)
9256 count = -signed_count, code = ASHIFT;
9258 count = signed_count;
9263 /* There are some cases we can't do. If CODE is ASHIFTRT,
9264 we can only do this if FIRST_CODE is also ASHIFTRT.
9266 We can't do the case when CODE is ROTATE and FIRST_CODE is
9269 If the mode of this shift is not the mode of the outer shift,
9270 we can't do this if either shift is a right shift or ROTATE.
9272 Finally, we can't do any of these if the mode is too wide
9273 unless the codes are the same.
9275 Handle the case where the shift codes are the same
9278 if (code == first_code)
9280 if (GET_MODE (varop) != result_mode
9281 && (code == ASHIFTRT || code == LSHIFTRT
9285 count += first_count;
9286 varop = XEXP (varop, 0);
9290 if (code == ASHIFTRT
9291 || (code == ROTATE && first_code == ASHIFTRT)
9292 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9293 || (GET_MODE (varop) != result_mode
9294 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9295 || first_code == ROTATE
9296 || code == ROTATE)))
9299 /* To compute the mask to apply after the shift, shift the
9300 nonzero bits of the inner shift the same way the
9301 outer shift will. */
9303 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9306 = simplify_binary_operation (code, result_mode, mask_rtx,
9309 /* Give up if we can't compute an outer operation to use. */
9311 || GET_CODE (mask_rtx) != CONST_INT
9312 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9314 result_mode, &complement_p))
9317 /* If the shifts are in the same direction, we add the
9318 counts. Otherwise, we subtract them. */
9319 signed_count = count;
9320 if ((code == ASHIFTRT || code == LSHIFTRT)
9321 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9322 signed_count += first_count;
9324 signed_count -= first_count;
9326 /* If COUNT is positive, the new shift is usually CODE,
9327 except for the two exceptions below, in which case it is
9328 FIRST_CODE. If the count is negative, FIRST_CODE should
9330 if (signed_count > 0
9331 && ((first_code == ROTATE && code == ASHIFT)
9332 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9333 code = first_code, count = signed_count;
9334 else if (signed_count < 0)
9335 code = first_code, count = -signed_count;
9337 count = signed_count;
9339 varop = XEXP (varop, 0);
9343 /* If we have (A << B << C) for any shift, we can convert this to
9344 (A << C << B). This wins if A is a constant. Only try this if
9345 B is not a constant. */
9347 else if (GET_CODE (varop) == code
9348 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9350 = simplify_binary_operation (code, mode,
9354 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9361 /* Make this fit the case below. */
9362 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9363 GEN_INT (GET_MODE_MASK (mode)));
9369 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9370 with C the size of VAROP - 1 and the shift is logical if
9371 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9372 we have an (le X 0) operation. If we have an arithmetic shift
9373 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9374 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9376 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9377 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9378 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9379 && (code == LSHIFTRT || code == ASHIFTRT)
9380 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9381 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9384 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9387 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9388 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9393 /* If we have (shift (logical)), move the logical to the outside
9394 to allow it to possibly combine with another logical and the
9395 shift to combine with another shift. This also canonicalizes to
9396 what a ZERO_EXTRACT looks like. Also, some machines have
9397 (and (shift)) insns. */
9399 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9400 && (new = simplify_binary_operation (code, result_mode,
9402 GEN_INT (count))) != 0
9403 && GET_CODE (new) == CONST_INT
9404 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9405 INTVAL (new), result_mode, &complement_p))
9407 varop = XEXP (varop, 0);
9411 /* If we can't do that, try to simplify the shift in each arm of the
9412 logical expression, make a new logical expression, and apply
9413 the inverse distributive law. */
9415 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9416 XEXP (varop, 0), count);
9417 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9418 XEXP (varop, 1), count);
9420 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9421 varop = apply_distributive_law (varop);
9428 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9429 says that the sign bit can be tested, FOO has mode MODE, C is
9430 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9431 that may be nonzero. */
9432 if (code == LSHIFTRT
9433 && XEXP (varop, 1) == const0_rtx
9434 && GET_MODE (XEXP (varop, 0)) == result_mode
9435 && count == GET_MODE_BITSIZE (result_mode) - 1
9436 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9437 && ((STORE_FLAG_VALUE
9438 & ((HOST_WIDE_INT) 1
9439 < (GET_MODE_BITSIZE (result_mode) - 1))))
9440 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9441 && merge_outer_ops (&outer_op, &outer_const, XOR,
9442 (HOST_WIDE_INT) 1, result_mode,
9445 varop = XEXP (varop, 0);
9452 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9453 than the number of bits in the mode is equivalent to A. */
9454 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9455 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9457 varop = XEXP (varop, 0);
9462 /* NEG commutes with ASHIFT since it is multiplication. Move the
9463 NEG outside to allow shifts to combine. */
9465 && merge_outer_ops (&outer_op, &outer_const, NEG,
9466 (HOST_WIDE_INT) 0, result_mode,
9469 varop = XEXP (varop, 0);
9475 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9476 is one less than the number of bits in the mode is
9477 equivalent to (xor A 1). */
9478 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9479 && XEXP (varop, 1) == constm1_rtx
9480 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9481 && merge_outer_ops (&outer_op, &outer_const, XOR,
9482 (HOST_WIDE_INT) 1, result_mode,
9486 varop = XEXP (varop, 0);
9490 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9491 that might be nonzero in BAR are those being shifted out and those
9492 bits are known zero in FOO, we can replace the PLUS with FOO.
9493 Similarly in the other operand order. This code occurs when
9494 we are computing the size of a variable-size array. */
9496 if ((code == ASHIFTRT || code == LSHIFTRT)
9497 && count < HOST_BITS_PER_WIDE_INT
9498 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9499 && (nonzero_bits (XEXP (varop, 1), result_mode)
9500 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9502 varop = XEXP (varop, 0);
9505 else if ((code == ASHIFTRT || code == LSHIFTRT)
9506 && count < HOST_BITS_PER_WIDE_INT
9507 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9508 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9510 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9511 & nonzero_bits (XEXP (varop, 1),
9514 varop = XEXP (varop, 1);
9518 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9520 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9521 && (new = simplify_binary_operation (ASHIFT, result_mode,
9523 GEN_INT (count))) != 0
9524 && GET_CODE (new) == CONST_INT
9525 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9526 INTVAL (new), result_mode, &complement_p))
9528 varop = XEXP (varop, 0);
9534 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9535 with C the size of VAROP - 1 and the shift is logical if
9536 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9537 we have a (gt X 0) operation. If the shift is arithmetic with
9538 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9539 we have a (neg (gt X 0)) operation. */
9541 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9542 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9543 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9544 && (code == LSHIFTRT || code == ASHIFTRT)
9545 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9546 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9547 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9550 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9553 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9554 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9561 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9562 if the truncate does not affect the value. */
9563 if (code == LSHIFTRT
9564 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9565 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9566 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9567 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9568 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9570 rtx varop_inner = XEXP (varop, 0);
9573 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9574 XEXP (varop_inner, 0),
9576 (count + INTVAL (XEXP (varop_inner, 1))));
9577 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9590 /* We need to determine what mode to do the shift in. If the shift is
9591 a right shift or ROTATE, we must always do it in the mode it was
9592 originally done in. Otherwise, we can do it in MODE, the widest mode
9593 encountered. The code we care about is that of the shift that will
9594 actually be done, not the shift that was originally requested. */
9596 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9597 ? result_mode : mode);
9599 /* We have now finished analyzing the shift. The result should be
9600 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9601 OUTER_OP is non-NIL, it is an operation that needs to be applied
9602 to the result of the shift. OUTER_CONST is the relevant constant,
9603 but we must turn off all bits turned off in the shift.
9605 If we were passed a value for X, see if we can use any pieces of
9606 it. If not, make new rtx. */
9608 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9609 && GET_CODE (XEXP (x, 1)) == CONST_INT
9610 && INTVAL (XEXP (x, 1)) == count)
9611 const_rtx = XEXP (x, 1);
9613 const_rtx = GEN_INT (count);
9615 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9616 && GET_MODE (XEXP (x, 0)) == shift_mode
9617 && SUBREG_REG (XEXP (x, 0)) == varop)
9618 varop = XEXP (x, 0);
9619 else if (GET_MODE (varop) != shift_mode)
9620 varop = gen_lowpart_for_combine (shift_mode, varop);
9622 /* If we can't make the SUBREG, try to return what we were given. */
9623 if (GET_CODE (varop) == CLOBBER)
9624 return x ? x : varop;
9626 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9630 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9632 /* If we have an outer operation and we just made a shift, it is
9633 possible that we could have simplified the shift were it not
9634 for the outer operation. So try to do the simplification
9637 if (outer_op != NIL && GET_CODE (x) == code
9638 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9639 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9640 INTVAL (XEXP (x, 1)));
9642 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9643 turn off all the bits that the shift would have turned off. */
9644 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9645 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9646 GET_MODE_MASK (result_mode) >> orig_count);
9648 /* Do the remainder of the processing in RESULT_MODE. */
9649 x = gen_lowpart_for_combine (result_mode, x);
9651 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9654 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9656 if (outer_op != NIL)
9658 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9659 outer_const = trunc_int_for_mode (outer_const, result_mode);
9661 if (outer_op == AND)
9662 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9663 else if (outer_op == SET)
9664 /* This means that we have determined that the result is
9665 equivalent to a constant. This should be rare. */
9666 x = GEN_INT (outer_const);
9667 else if (GET_RTX_CLASS (outer_op) == '1')
9668 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9670 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9676 /* Like recog, but we receive the address of a pointer to a new pattern.
9677 We try to match the rtx that the pointer points to.
9678 If that fails, we may try to modify or replace the pattern,
9679 storing the replacement into the same pointer object.
9681 Modifications include deletion or addition of CLOBBERs.
9683 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9684 the CLOBBERs are placed.
9686 The value is the final insn code from the pattern ultimately matched,
9690 recog_for_combine (pnewpat, insn, pnotes)
9696 int insn_code_number;
9697 int num_clobbers_to_add = 0;
9702 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9703 we use to indicate that something didn't match. If we find such a
9704 thing, force rejection. */
9705 if (GET_CODE (pat) == PARALLEL)
9706 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9707 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9708 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9711 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9712 instruction for pattern recognition. */
9713 dummy_insn = shallow_copy_rtx (insn);
9714 PATTERN (dummy_insn) = pat;
9715 REG_NOTES (dummy_insn) = 0;
9717 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9719 /* If it isn't, there is the possibility that we previously had an insn
9720 that clobbered some register as a side effect, but the combined
9721 insn doesn't need to do that. So try once more without the clobbers
9722 unless this represents an ASM insn. */
9724 if (insn_code_number < 0 && ! check_asm_operands (pat)
9725 && GET_CODE (pat) == PARALLEL)
9729 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9730 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9733 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9737 SUBST_INT (XVECLEN (pat, 0), pos);
9740 pat = XVECEXP (pat, 0, 0);
9742 PATTERN (dummy_insn) = pat;
9743 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9746 /* Recognize all noop sets, these will be killed by followup pass. */
9747 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9748 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9750 /* If we had any clobbers to add, make a new pattern than contains
9751 them. Then check to make sure that all of them are dead. */
9752 if (num_clobbers_to_add)
9754 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9755 rtvec_alloc (GET_CODE (pat) == PARALLEL
9757 + num_clobbers_to_add)
9758 : num_clobbers_to_add + 1));
9760 if (GET_CODE (pat) == PARALLEL)
9761 for (i = 0; i < XVECLEN (pat, 0); i++)
9762 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9764 XVECEXP (newpat, 0, 0) = pat;
9766 add_clobbers (newpat, insn_code_number);
9768 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9769 i < XVECLEN (newpat, 0); i++)
9771 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9772 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9774 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9775 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9783 return insn_code_number;
9786 /* Like gen_lowpart but for use by combine. In combine it is not possible
9787 to create any new pseudoregs. However, it is safe to create
9788 invalid memory addresses, because combine will try to recognize
9789 them and all they will do is make the combine attempt fail.
9791 If for some reason this cannot do its job, an rtx
9792 (clobber (const_int 0)) is returned.
9793 An insn containing that will not be recognized. */
9798 gen_lowpart_for_combine (mode, x)
9799 enum machine_mode mode;
9804 if (GET_MODE (x) == mode)
9807 /* We can only support MODE being wider than a word if X is a
9808 constant integer or has a mode the same size. */
9810 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9811 && ! ((GET_MODE (x) == VOIDmode
9812 && (GET_CODE (x) == CONST_INT
9813 || GET_CODE (x) == CONST_DOUBLE))
9814 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9815 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9817 /* simplify_gen_subreg does not know how to handle the case where we try
9818 to convert an integer constant to a vector.
9819 ??? We could try to teach it to generate CONST_VECTORs. */
9820 if (GET_MODE (x) == VOIDmode && VECTOR_MODE_P (mode))
9821 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9823 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9824 won't know what to do. So we will strip off the SUBREG here and
9825 process normally. */
9826 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9829 if (GET_MODE (x) == mode)
9833 result = gen_lowpart_common (mode, x);
9834 #ifdef CLASS_CANNOT_CHANGE_MODE
9836 && GET_CODE (result) == SUBREG
9837 && GET_CODE (SUBREG_REG (result)) == REG
9838 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9839 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9840 GET_MODE (SUBREG_REG (result))))
9841 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9847 if (GET_CODE (x) == MEM)
9851 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9853 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9854 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9856 /* If we want to refer to something bigger than the original memref,
9857 generate a perverse subreg instead. That will force a reload
9858 of the original memref X. */
9859 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9860 return gen_rtx_SUBREG (mode, x, 0);
9862 if (WORDS_BIG_ENDIAN)
9863 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9864 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9866 if (BYTES_BIG_ENDIAN)
9868 /* Adjust the address so that the address-after-the-data is
9870 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9871 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9874 return adjust_address_nv (x, mode, offset);
9877 /* If X is a comparison operator, rewrite it in a new mode. This
9878 probably won't match, but may allow further simplifications. */
9879 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9880 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9882 /* If we couldn't simplify X any other way, just enclose it in a
9883 SUBREG. Normally, this SUBREG won't match, but some patterns may
9884 include an explicit SUBREG or we may simplify it further in combine. */
9890 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9891 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9894 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9898 /* These routines make binary and unary operations by first seeing if they
9899 fold; if not, a new expression is allocated. */
9902 gen_binary (code, mode, op0, op1)
9904 enum machine_mode mode;
9910 if (GET_RTX_CLASS (code) == 'c'
9911 && swap_commutative_operands_p (op0, op1))
9912 tem = op0, op0 = op1, op1 = tem;
9914 if (GET_RTX_CLASS (code) == '<')
9916 enum machine_mode op_mode = GET_MODE (op0);
9918 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9919 just (REL_OP X Y). */
9920 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9922 op1 = XEXP (op0, 1);
9923 op0 = XEXP (op0, 0);
9924 op_mode = GET_MODE (op0);
9927 if (op_mode == VOIDmode)
9928 op_mode = GET_MODE (op1);
9929 result = simplify_relational_operation (code, op_mode, op0, op1);
9932 result = simplify_binary_operation (code, mode, op0, op1);
9937 /* Put complex operands first and constants second. */
9938 if (GET_RTX_CLASS (code) == 'c'
9939 && swap_commutative_operands_p (op0, op1))
9940 return gen_rtx_fmt_ee (code, mode, op1, op0);
9942 /* If we are turning off bits already known off in OP0, we need not do
9944 else if (code == AND && GET_CODE (op1) == CONST_INT
9945 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9946 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9949 return gen_rtx_fmt_ee (code, mode, op0, op1);
9952 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9953 comparison code that will be tested.
9955 The result is a possibly different comparison code to use. *POP0 and
9956 *POP1 may be updated.
9958 It is possible that we might detect that a comparison is either always
9959 true or always false. However, we do not perform general constant
9960 folding in combine, so this knowledge isn't useful. Such tautologies
9961 should have been detected earlier. Hence we ignore all such cases. */
9963 static enum rtx_code
9964 simplify_comparison (code, pop0, pop1)
9973 enum machine_mode mode, tmode;
9975 /* Try a few ways of applying the same transformation to both operands. */
9978 #ifndef WORD_REGISTER_OPERATIONS
9979 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9980 so check specially. */
9981 if (code != GTU && code != GEU && code != LTU && code != LEU
9982 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9983 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9984 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9985 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9986 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9987 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9988 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9989 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9990 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9991 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9992 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9993 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9994 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9995 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9996 && (INTVAL (XEXP (op0, 1))
9997 == (GET_MODE_BITSIZE (GET_MODE (op0))
9999 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10001 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10002 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10006 /* If both operands are the same constant shift, see if we can ignore the
10007 shift. We can if the shift is a rotate or if the bits shifted out of
10008 this shift are known to be zero for both inputs and if the type of
10009 comparison is compatible with the shift. */
10010 if (GET_CODE (op0) == GET_CODE (op1)
10011 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10012 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10013 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10014 && (code != GT && code != LT && code != GE && code != LE))
10015 || (GET_CODE (op0) == ASHIFTRT
10016 && (code != GTU && code != LTU
10017 && code != GEU && code != LEU)))
10018 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10019 && INTVAL (XEXP (op0, 1)) >= 0
10020 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10021 && XEXP (op0, 1) == XEXP (op1, 1))
10023 enum machine_mode mode = GET_MODE (op0);
10024 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10025 int shift_count = INTVAL (XEXP (op0, 1));
10027 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10028 mask &= (mask >> shift_count) << shift_count;
10029 else if (GET_CODE (op0) == ASHIFT)
10030 mask = (mask & (mask << shift_count)) >> shift_count;
10032 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10033 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10034 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10039 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10040 SUBREGs are of the same mode, and, in both cases, the AND would
10041 be redundant if the comparison was done in the narrower mode,
10042 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10043 and the operand's possibly nonzero bits are 0xffffff01; in that case
10044 if we only care about QImode, we don't need the AND). This case
10045 occurs if the output mode of an scc insn is not SImode and
10046 STORE_FLAG_VALUE == 1 (e.g., the 386).
10048 Similarly, check for a case where the AND's are ZERO_EXTEND
10049 operations from some narrower mode even though a SUBREG is not
10052 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10053 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10054 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10056 rtx inner_op0 = XEXP (op0, 0);
10057 rtx inner_op1 = XEXP (op1, 0);
10058 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10059 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10062 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10063 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10064 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10065 && (GET_MODE (SUBREG_REG (inner_op0))
10066 == GET_MODE (SUBREG_REG (inner_op1)))
10067 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10068 <= HOST_BITS_PER_WIDE_INT)
10069 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10070 GET_MODE (SUBREG_REG (inner_op0)))))
10071 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10072 GET_MODE (SUBREG_REG (inner_op1))))))
10074 op0 = SUBREG_REG (inner_op0);
10075 op1 = SUBREG_REG (inner_op1);
10077 /* The resulting comparison is always unsigned since we masked
10078 off the original sign bit. */
10079 code = unsigned_condition (code);
10085 for (tmode = GET_CLASS_NARROWEST_MODE
10086 (GET_MODE_CLASS (GET_MODE (op0)));
10087 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10088 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10090 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10091 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10092 code = unsigned_condition (code);
10101 /* If both operands are NOT, we can strip off the outer operation
10102 and adjust the comparison code for swapped operands; similarly for
10103 NEG, except that this must be an equality comparison. */
10104 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10105 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10106 && (code == EQ || code == NE)))
10107 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10113 /* If the first operand is a constant, swap the operands and adjust the
10114 comparison code appropriately, but don't do this if the second operand
10115 is already a constant integer. */
10116 if (swap_commutative_operands_p (op0, op1))
10118 tem = op0, op0 = op1, op1 = tem;
10119 code = swap_condition (code);
10122 /* We now enter a loop during which we will try to simplify the comparison.
10123 For the most part, we only are concerned with comparisons with zero,
10124 but some things may really be comparisons with zero but not start
10125 out looking that way. */
10127 while (GET_CODE (op1) == CONST_INT)
10129 enum machine_mode mode = GET_MODE (op0);
10130 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10131 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10132 int equality_comparison_p;
10133 int sign_bit_comparison_p;
10134 int unsigned_comparison_p;
10135 HOST_WIDE_INT const_op;
10137 /* We only want to handle integral modes. This catches VOIDmode,
10138 CCmode, and the floating-point modes. An exception is that we
10139 can handle VOIDmode if OP0 is a COMPARE or a comparison
10142 if (GET_MODE_CLASS (mode) != MODE_INT
10143 && ! (mode == VOIDmode
10144 && (GET_CODE (op0) == COMPARE
10145 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10148 /* Get the constant we are comparing against and turn off all bits
10149 not on in our mode. */
10150 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10151 op1 = GEN_INT (const_op);
10153 /* If we are comparing against a constant power of two and the value
10154 being compared can only have that single bit nonzero (e.g., it was
10155 `and'ed with that bit), we can replace this with a comparison
10158 && (code == EQ || code == NE || code == GE || code == GEU
10159 || code == LT || code == LTU)
10160 && mode_width <= HOST_BITS_PER_WIDE_INT
10161 && exact_log2 (const_op) >= 0
10162 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10164 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10165 op1 = const0_rtx, const_op = 0;
10168 /* Similarly, if we are comparing a value known to be either -1 or
10169 0 with -1, change it to the opposite comparison against zero. */
10172 && (code == EQ || code == NE || code == GT || code == LE
10173 || code == GEU || code == LTU)
10174 && num_sign_bit_copies (op0, mode) == mode_width)
10176 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10177 op1 = const0_rtx, const_op = 0;
10180 /* Do some canonicalizations based on the comparison code. We prefer
10181 comparisons against zero and then prefer equality comparisons.
10182 If we can reduce the size of a constant, we will do that too. */
10187 /* < C is equivalent to <= (C - 1) */
10191 op1 = GEN_INT (const_op);
10193 /* ... fall through to LE case below. */
10199 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10203 op1 = GEN_INT (const_op);
10207 /* If we are doing a <= 0 comparison on a value known to have
10208 a zero sign bit, we can replace this with == 0. */
10209 else if (const_op == 0
10210 && mode_width <= HOST_BITS_PER_WIDE_INT
10211 && (nonzero_bits (op0, mode)
10212 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10217 /* >= C is equivalent to > (C - 1). */
10221 op1 = GEN_INT (const_op);
10223 /* ... fall through to GT below. */
10229 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10233 op1 = GEN_INT (const_op);
10237 /* If we are doing a > 0 comparison on a value known to have
10238 a zero sign bit, we can replace this with != 0. */
10239 else if (const_op == 0
10240 && mode_width <= HOST_BITS_PER_WIDE_INT
10241 && (nonzero_bits (op0, mode)
10242 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10247 /* < C is equivalent to <= (C - 1). */
10251 op1 = GEN_INT (const_op);
10253 /* ... fall through ... */
10256 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10257 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10258 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10260 const_op = 0, op1 = const0_rtx;
10268 /* unsigned <= 0 is equivalent to == 0 */
10272 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10273 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10274 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10276 const_op = 0, op1 = const0_rtx;
10282 /* >= C is equivalent to < (C - 1). */
10286 op1 = GEN_INT (const_op);
10288 /* ... fall through ... */
10291 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10292 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10293 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10295 const_op = 0, op1 = const0_rtx;
10303 /* unsigned > 0 is equivalent to != 0 */
10307 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10308 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10309 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10311 const_op = 0, op1 = const0_rtx;
10320 /* Compute some predicates to simplify code below. */
10322 equality_comparison_p = (code == EQ || code == NE);
10323 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10324 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10327 /* If this is a sign bit comparison and we can do arithmetic in
10328 MODE, say that we will only be needing the sign bit of OP0. */
10329 if (sign_bit_comparison_p
10330 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10331 op0 = force_to_mode (op0, mode,
10333 << (GET_MODE_BITSIZE (mode) - 1)),
10336 /* Now try cases based on the opcode of OP0. If none of the cases
10337 does a "continue", we exit this loop immediately after the
10340 switch (GET_CODE (op0))
10343 /* If we are extracting a single bit from a variable position in
10344 a constant that has only a single bit set and are comparing it
10345 with zero, we can convert this into an equality comparison
10346 between the position and the location of the single bit. */
10348 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10349 && XEXP (op0, 1) == const1_rtx
10350 && equality_comparison_p && const_op == 0
10351 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10353 if (BITS_BIG_ENDIAN)
10355 enum machine_mode new_mode
10356 = mode_for_extraction (EP_extzv, 1);
10357 if (new_mode == MAX_MACHINE_MODE)
10358 i = BITS_PER_WORD - 1 - i;
10362 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10366 op0 = XEXP (op0, 2);
10370 /* Result is nonzero iff shift count is equal to I. */
10371 code = reverse_condition (code);
10375 /* ... fall through ... */
10378 tem = expand_compound_operation (op0);
10387 /* If testing for equality, we can take the NOT of the constant. */
10388 if (equality_comparison_p
10389 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10391 op0 = XEXP (op0, 0);
10396 /* If just looking at the sign bit, reverse the sense of the
10398 if (sign_bit_comparison_p)
10400 op0 = XEXP (op0, 0);
10401 code = (code == GE ? LT : GE);
10407 /* If testing for equality, we can take the NEG of the constant. */
10408 if (equality_comparison_p
10409 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10411 op0 = XEXP (op0, 0);
10416 /* The remaining cases only apply to comparisons with zero. */
10420 /* When X is ABS or is known positive,
10421 (neg X) is < 0 if and only if X != 0. */
10423 if (sign_bit_comparison_p
10424 && (GET_CODE (XEXP (op0, 0)) == ABS
10425 || (mode_width <= HOST_BITS_PER_WIDE_INT
10426 && (nonzero_bits (XEXP (op0, 0), mode)
10427 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10429 op0 = XEXP (op0, 0);
10430 code = (code == LT ? NE : EQ);
10434 /* If we have NEG of something whose two high-order bits are the
10435 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10436 if (num_sign_bit_copies (op0, mode) >= 2)
10438 op0 = XEXP (op0, 0);
10439 code = swap_condition (code);
10445 /* If we are testing equality and our count is a constant, we
10446 can perform the inverse operation on our RHS. */
10447 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10448 && (tem = simplify_binary_operation (ROTATERT, mode,
10449 op1, XEXP (op0, 1))) != 0)
10451 op0 = XEXP (op0, 0);
10456 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10457 a particular bit. Convert it to an AND of a constant of that
10458 bit. This will be converted into a ZERO_EXTRACT. */
10459 if (const_op == 0 && sign_bit_comparison_p
10460 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10461 && mode_width <= HOST_BITS_PER_WIDE_INT)
10463 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10466 - INTVAL (XEXP (op0, 1)))));
10467 code = (code == LT ? NE : EQ);
10471 /* Fall through. */
10474 /* ABS is ignorable inside an equality comparison with zero. */
10475 if (const_op == 0 && equality_comparison_p)
10477 op0 = XEXP (op0, 0);
10483 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10484 to (compare FOO CONST) if CONST fits in FOO's mode and we
10485 are either testing inequality or have an unsigned comparison
10486 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10487 if (! unsigned_comparison_p
10488 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10489 <= HOST_BITS_PER_WIDE_INT)
10490 && ((unsigned HOST_WIDE_INT) const_op
10491 < (((unsigned HOST_WIDE_INT) 1
10492 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10494 op0 = XEXP (op0, 0);
10500 /* Check for the case where we are comparing A - C1 with C2,
10501 both constants are smaller than 1/2 the maximum positive
10502 value in MODE, and the comparison is equality or unsigned.
10503 In that case, if A is either zero-extended to MODE or has
10504 sufficient sign bits so that the high-order bit in MODE
10505 is a copy of the sign in the inner mode, we can prove that it is
10506 safe to do the operation in the wider mode. This simplifies
10507 many range checks. */
10509 if (mode_width <= HOST_BITS_PER_WIDE_INT
10510 && subreg_lowpart_p (op0)
10511 && GET_CODE (SUBREG_REG (op0)) == PLUS
10512 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10513 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10514 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10515 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10516 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10517 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10518 GET_MODE (SUBREG_REG (op0)))
10519 & ~GET_MODE_MASK (mode))
10520 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10521 GET_MODE (SUBREG_REG (op0)))
10522 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10523 - GET_MODE_BITSIZE (mode)))))
10525 op0 = SUBREG_REG (op0);
10529 /* If the inner mode is narrower and we are extracting the low part,
10530 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10531 if (subreg_lowpart_p (op0)
10532 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10533 /* Fall through */ ;
10537 /* ... fall through ... */
10540 if ((unsigned_comparison_p || equality_comparison_p)
10541 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10542 <= HOST_BITS_PER_WIDE_INT)
10543 && ((unsigned HOST_WIDE_INT) const_op
10544 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10546 op0 = XEXP (op0, 0);
10552 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10553 this for equality comparisons due to pathological cases involving
10555 if (equality_comparison_p
10556 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10557 op1, XEXP (op0, 1))))
10559 op0 = XEXP (op0, 0);
10564 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10565 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10566 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10568 op0 = XEXP (XEXP (op0, 0), 0);
10569 code = (code == LT ? EQ : NE);
10575 /* We used to optimize signed comparisons against zero, but that
10576 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10577 arrive here as equality comparisons, or (GEU, LTU) are
10578 optimized away. No need to special-case them. */
10580 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10581 (eq B (minus A C)), whichever simplifies. We can only do
10582 this for equality comparisons due to pathological cases involving
10584 if (equality_comparison_p
10585 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10586 XEXP (op0, 1), op1)))
10588 op0 = XEXP (op0, 0);
10593 if (equality_comparison_p
10594 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10595 XEXP (op0, 0), op1)))
10597 op0 = XEXP (op0, 1);
10602 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10603 of bits in X minus 1, is one iff X > 0. */
10604 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10605 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10606 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10607 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10609 op0 = XEXP (op0, 1);
10610 code = (code == GE ? LE : GT);
10616 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10617 if C is zero or B is a constant. */
10618 if (equality_comparison_p
10619 && 0 != (tem = simplify_binary_operation (XOR, mode,
10620 XEXP (op0, 1), op1)))
10622 op0 = XEXP (op0, 0);
10629 case UNEQ: case LTGT:
10630 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10631 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10632 case UNORDERED: case ORDERED:
10633 /* We can't do anything if OP0 is a condition code value, rather
10634 than an actual data value. */
10637 || XEXP (op0, 0) == cc0_rtx
10639 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10642 /* Get the two operands being compared. */
10643 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10644 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10646 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10648 /* Check for the cases where we simply want the result of the
10649 earlier test or the opposite of that result. */
10650 if (code == NE || code == EQ
10651 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10652 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10653 && (STORE_FLAG_VALUE
10654 & (((HOST_WIDE_INT) 1
10655 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10656 && (code == LT || code == GE)))
10658 enum rtx_code new_code;
10659 if (code == LT || code == NE)
10660 new_code = GET_CODE (op0);
10662 new_code = combine_reversed_comparison_code (op0);
10664 if (new_code != UNKNOWN)
10675 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10677 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10678 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10679 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10681 op0 = XEXP (op0, 1);
10682 code = (code == GE ? GT : LE);
10688 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10689 will be converted to a ZERO_EXTRACT later. */
10690 if (const_op == 0 && equality_comparison_p
10691 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10692 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10694 op0 = simplify_and_const_int
10695 (op0, mode, gen_rtx_LSHIFTRT (mode,
10697 XEXP (XEXP (op0, 0), 1)),
10698 (HOST_WIDE_INT) 1);
10702 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10703 zero and X is a comparison and C1 and C2 describe only bits set
10704 in STORE_FLAG_VALUE, we can compare with X. */
10705 if (const_op == 0 && equality_comparison_p
10706 && mode_width <= HOST_BITS_PER_WIDE_INT
10707 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10708 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10709 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10710 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10711 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10713 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10714 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10715 if ((~STORE_FLAG_VALUE & mask) == 0
10716 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10717 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10718 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10720 op0 = XEXP (XEXP (op0, 0), 0);
10725 /* If we are doing an equality comparison of an AND of a bit equal
10726 to the sign bit, replace this with a LT or GE comparison of
10727 the underlying value. */
10728 if (equality_comparison_p
10730 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10731 && mode_width <= HOST_BITS_PER_WIDE_INT
10732 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10733 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10735 op0 = XEXP (op0, 0);
10736 code = (code == EQ ? GE : LT);
10740 /* If this AND operation is really a ZERO_EXTEND from a narrower
10741 mode, the constant fits within that mode, and this is either an
10742 equality or unsigned comparison, try to do this comparison in
10743 the narrower mode. */
10744 if ((equality_comparison_p || unsigned_comparison_p)
10745 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10746 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10747 & GET_MODE_MASK (mode))
10749 && const_op >> i == 0
10750 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10752 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10756 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10757 in both M1 and M2 and the SUBREG is either paradoxical or
10758 represents the low part, permute the SUBREG and the AND and
10760 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10762 #ifdef WORD_REGISTER_OPERATIONS
10764 > (GET_MODE_BITSIZE
10765 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10766 && mode_width <= BITS_PER_WORD)
10769 <= (GET_MODE_BITSIZE
10770 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10771 && subreg_lowpart_p (XEXP (op0, 0))))
10772 #ifndef WORD_REGISTER_OPERATIONS
10773 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10774 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10775 As originally written the upper bits have a defined value
10776 due to the AND operation. However, if we commute the AND
10777 inside the SUBREG then they no longer have defined values
10778 and the meaning of the code has been changed. */
10779 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10780 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10782 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10783 && mode_width <= HOST_BITS_PER_WIDE_INT
10784 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10785 <= HOST_BITS_PER_WIDE_INT)
10786 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10787 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10788 & INTVAL (XEXP (op0, 1)))
10789 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10790 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10791 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10795 = gen_lowpart_for_combine
10797 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10798 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10802 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10803 (eq (and (lshiftrt X) 1) 0). */
10804 if (const_op == 0 && equality_comparison_p
10805 && XEXP (op0, 1) == const1_rtx
10806 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10807 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10809 op0 = simplify_and_const_int
10811 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10812 XEXP (XEXP (op0, 0), 1)),
10813 (HOST_WIDE_INT) 1);
10814 code = (code == NE ? EQ : NE);
10820 /* If we have (compare (ashift FOO N) (const_int C)) and
10821 the high order N bits of FOO (N+1 if an inequality comparison)
10822 are known to be zero, we can do this by comparing FOO with C
10823 shifted right N bits so long as the low-order N bits of C are
10825 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10826 && INTVAL (XEXP (op0, 1)) >= 0
10827 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10828 < HOST_BITS_PER_WIDE_INT)
10830 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10831 && mode_width <= HOST_BITS_PER_WIDE_INT
10832 && (nonzero_bits (XEXP (op0, 0), mode)
10833 & ~(mask >> (INTVAL (XEXP (op0, 1))
10834 + ! equality_comparison_p))) == 0)
10836 /* We must perform a logical shift, not an arithmetic one,
10837 as we want the top N bits of C to be zero. */
10838 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10840 temp >>= INTVAL (XEXP (op0, 1));
10841 op1 = gen_int_mode (temp, mode);
10842 op0 = XEXP (op0, 0);
10846 /* If we are doing a sign bit comparison, it means we are testing
10847 a particular bit. Convert it to the appropriate AND. */
10848 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10849 && mode_width <= HOST_BITS_PER_WIDE_INT)
10851 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10854 - INTVAL (XEXP (op0, 1)))));
10855 code = (code == LT ? NE : EQ);
10859 /* If this an equality comparison with zero and we are shifting
10860 the low bit to the sign bit, we can convert this to an AND of the
10862 if (const_op == 0 && equality_comparison_p
10863 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10864 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10866 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10867 (HOST_WIDE_INT) 1);
10873 /* If this is an equality comparison with zero, we can do this
10874 as a logical shift, which might be much simpler. */
10875 if (equality_comparison_p && const_op == 0
10876 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10878 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10880 INTVAL (XEXP (op0, 1)));
10884 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10885 do the comparison in a narrower mode. */
10886 if (! unsigned_comparison_p
10887 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10888 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10889 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10890 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10891 MODE_INT, 1)) != BLKmode
10892 && (((unsigned HOST_WIDE_INT) const_op
10893 + (GET_MODE_MASK (tmode) >> 1) + 1)
10894 <= GET_MODE_MASK (tmode)))
10896 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10900 /* Likewise if OP0 is a PLUS of a sign extension with a
10901 constant, which is usually represented with the PLUS
10902 between the shifts. */
10903 if (! unsigned_comparison_p
10904 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10905 && GET_CODE (XEXP (op0, 0)) == PLUS
10906 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10907 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10908 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10909 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10910 MODE_INT, 1)) != BLKmode
10911 && (((unsigned HOST_WIDE_INT) const_op
10912 + (GET_MODE_MASK (tmode) >> 1) + 1)
10913 <= GET_MODE_MASK (tmode)))
10915 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10916 rtx add_const = XEXP (XEXP (op0, 0), 1);
10917 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10920 op0 = gen_binary (PLUS, tmode,
10921 gen_lowpart_for_combine (tmode, inner),
10926 /* ... fall through ... */
10928 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10929 the low order N bits of FOO are known to be zero, we can do this
10930 by comparing FOO with C shifted left N bits so long as no
10931 overflow occurs. */
10932 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10933 && INTVAL (XEXP (op0, 1)) >= 0
10934 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10935 && mode_width <= HOST_BITS_PER_WIDE_INT
10936 && (nonzero_bits (XEXP (op0, 0), mode)
10937 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10938 && (((unsigned HOST_WIDE_INT) const_op
10939 + (GET_CODE (op0) != LSHIFTRT
10940 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10943 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10945 /* If the shift was logical, then we must make the condition
10947 if (GET_CODE (op0) == LSHIFTRT)
10948 code = unsigned_condition (code);
10950 const_op <<= INTVAL (XEXP (op0, 1));
10951 op1 = GEN_INT (const_op);
10952 op0 = XEXP (op0, 0);
10956 /* If we are using this shift to extract just the sign bit, we
10957 can replace this with an LT or GE comparison. */
10959 && (equality_comparison_p || sign_bit_comparison_p)
10960 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10961 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10963 op0 = XEXP (op0, 0);
10964 code = (code == NE || code == GT ? LT : GE);
10976 /* Now make any compound operations involved in this comparison. Then,
10977 check for an outmost SUBREG on OP0 that is not doing anything or is
10978 paradoxical. The latter transformation must only be performed when
10979 it is known that the "extra" bits will be the same in op0 and op1 or
10980 that they don't matter. There are three cases to consider:
10982 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10983 care bits and we can assume they have any convenient value. So
10984 making the transformation is safe.
10986 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10987 In this case the upper bits of op0 are undefined. We should not make
10988 the simplification in that case as we do not know the contents of
10991 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10992 NIL. In that case we know those bits are zeros or ones. We must
10993 also be sure that they are the same as the upper bits of op1.
10995 We can never remove a SUBREG for a non-equality comparison because
10996 the sign bit is in a different place in the underlying object. */
10998 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10999 op1 = make_compound_operation (op1, SET);
11001 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11002 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11004 && GET_CODE (SUBREG_REG (op0)) == REG
11005 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11006 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11007 && (code == NE || code == EQ))
11009 if (GET_MODE_SIZE (GET_MODE (op0))
11010 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11012 op0 = SUBREG_REG (op0);
11013 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11015 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11016 <= HOST_BITS_PER_WIDE_INT)
11017 && (nonzero_bits (SUBREG_REG (op0),
11018 GET_MODE (SUBREG_REG (op0)))
11019 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11021 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11023 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11024 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11025 op0 = SUBREG_REG (op0), op1 = tem;
11029 /* We now do the opposite procedure: Some machines don't have compare
11030 insns in all modes. If OP0's mode is an integer mode smaller than a
11031 word and we can't do a compare in that mode, see if there is a larger
11032 mode for which we can do the compare. There are a number of cases in
11033 which we can use the wider mode. */
11035 mode = GET_MODE (op0);
11036 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11037 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11038 && ! have_insn_for (COMPARE, mode))
11039 for (tmode = GET_MODE_WIDER_MODE (mode);
11041 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11042 tmode = GET_MODE_WIDER_MODE (tmode))
11043 if (have_insn_for (COMPARE, tmode))
11047 /* If the only nonzero bits in OP0 and OP1 are those in the
11048 narrower mode and this is an equality or unsigned comparison,
11049 we can use the wider mode. Similarly for sign-extended
11050 values, in which case it is true for all comparisons. */
11051 zero_extended = ((code == EQ || code == NE
11052 || code == GEU || code == GTU
11053 || code == LEU || code == LTU)
11054 && (nonzero_bits (op0, tmode)
11055 & ~GET_MODE_MASK (mode)) == 0
11056 && ((GET_CODE (op1) == CONST_INT
11057 || (nonzero_bits (op1, tmode)
11058 & ~GET_MODE_MASK (mode)) == 0)));
11061 || ((num_sign_bit_copies (op0, tmode)
11062 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11063 && (num_sign_bit_copies (op1, tmode)
11064 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11066 /* If OP0 is an AND and we don't have an AND in MODE either,
11067 make a new AND in the proper mode. */
11068 if (GET_CODE (op0) == AND
11069 && !have_insn_for (AND, mode))
11070 op0 = gen_binary (AND, tmode,
11071 gen_lowpart_for_combine (tmode,
11073 gen_lowpart_for_combine (tmode,
11076 op0 = gen_lowpart_for_combine (tmode, op0);
11077 if (zero_extended && GET_CODE (op1) == CONST_INT)
11078 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11079 op1 = gen_lowpart_for_combine (tmode, op1);
11083 /* If this is a test for negative, we can make an explicit
11084 test of the sign bit. */
11086 if (op1 == const0_rtx && (code == LT || code == GE)
11087 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11089 op0 = gen_binary (AND, tmode,
11090 gen_lowpart_for_combine (tmode, op0),
11091 GEN_INT ((HOST_WIDE_INT) 1
11092 << (GET_MODE_BITSIZE (mode) - 1)));
11093 code = (code == LT) ? NE : EQ;
11098 #ifdef CANONICALIZE_COMPARISON
11099 /* If this machine only supports a subset of valid comparisons, see if we
11100 can convert an unsupported one into a supported one. */
11101 CANONICALIZE_COMPARISON (code, op0, op1);
11110 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11111 searching backward. */
11112 static enum rtx_code
11113 combine_reversed_comparison_code (exp)
11116 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11119 if (code1 != UNKNOWN
11120 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11122 /* Otherwise try and find where the condition codes were last set and
11124 x = get_last_value (XEXP (exp, 0));
11125 if (!x || GET_CODE (x) != COMPARE)
11127 return reversed_comparison_code_parts (GET_CODE (exp),
11128 XEXP (x, 0), XEXP (x, 1), NULL);
11130 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11131 Return NULL_RTX in case we fail to do the reversal. */
11133 reversed_comparison (exp, mode, op0, op1)
11135 enum machine_mode mode;
11137 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11138 if (reversed_code == UNKNOWN)
11141 return gen_binary (reversed_code, mode, op0, op1);
11144 /* Utility function for following routine. Called when X is part of a value
11145 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11146 for each register mentioned. Similar to mention_regs in cse.c */
11149 update_table_tick (x)
11152 enum rtx_code code = GET_CODE (x);
11153 const char *fmt = GET_RTX_FORMAT (code);
11158 unsigned int regno = REGNO (x);
11159 unsigned int endregno
11160 = regno + (regno < FIRST_PSEUDO_REGISTER
11161 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11164 for (r = regno; r < endregno; r++)
11165 reg_last_set_table_tick[r] = label_tick;
11170 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11171 /* Note that we can't have an "E" in values stored; see
11172 get_last_value_validate. */
11174 update_table_tick (XEXP (x, i));
11177 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11178 are saying that the register is clobbered and we no longer know its
11179 value. If INSN is zero, don't update reg_last_set; this is only permitted
11180 with VALUE also zero and is used to invalidate the register. */
11183 record_value_for_reg (reg, insn, value)
11188 unsigned int regno = REGNO (reg);
11189 unsigned int endregno
11190 = regno + (regno < FIRST_PSEUDO_REGISTER
11191 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11194 /* If VALUE contains REG and we have a previous value for REG, substitute
11195 the previous value. */
11196 if (value && insn && reg_overlap_mentioned_p (reg, value))
11200 /* Set things up so get_last_value is allowed to see anything set up to
11202 subst_low_cuid = INSN_CUID (insn);
11203 tem = get_last_value (reg);
11205 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11206 it isn't going to be useful and will take a lot of time to process,
11207 so just use the CLOBBER. */
11211 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11212 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11213 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11214 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11215 tem = XEXP (tem, 0);
11217 value = replace_rtx (copy_rtx (value), reg, tem);
11221 /* For each register modified, show we don't know its value, that
11222 we don't know about its bitwise content, that its value has been
11223 updated, and that we don't know the location of the death of the
11225 for (i = regno; i < endregno; i++)
11228 reg_last_set[i] = insn;
11230 reg_last_set_value[i] = 0;
11231 reg_last_set_mode[i] = 0;
11232 reg_last_set_nonzero_bits[i] = 0;
11233 reg_last_set_sign_bit_copies[i] = 0;
11234 reg_last_death[i] = 0;
11237 /* Mark registers that are being referenced in this value. */
11239 update_table_tick (value);
11241 /* Now update the status of each register being set.
11242 If someone is using this register in this block, set this register
11243 to invalid since we will get confused between the two lives in this
11244 basic block. This makes using this register always invalid. In cse, we
11245 scan the table to invalidate all entries using this register, but this
11246 is too much work for us. */
11248 for (i = regno; i < endregno; i++)
11250 reg_last_set_label[i] = label_tick;
11251 if (value && reg_last_set_table_tick[i] == label_tick)
11252 reg_last_set_invalid[i] = 1;
11254 reg_last_set_invalid[i] = 0;
11257 /* The value being assigned might refer to X (like in "x++;"). In that
11258 case, we must replace it with (clobber (const_int 0)) to prevent
11260 if (value && ! get_last_value_validate (&value, insn,
11261 reg_last_set_label[regno], 0))
11263 value = copy_rtx (value);
11264 if (! get_last_value_validate (&value, insn,
11265 reg_last_set_label[regno], 1))
11269 /* For the main register being modified, update the value, the mode, the
11270 nonzero bits, and the number of sign bit copies. */
11272 reg_last_set_value[regno] = value;
11276 enum machine_mode mode = GET_MODE (reg);
11277 subst_low_cuid = INSN_CUID (insn);
11278 reg_last_set_mode[regno] = mode;
11279 if (GET_MODE_CLASS (mode) == MODE_INT
11280 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11281 mode = nonzero_bits_mode;
11282 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11283 reg_last_set_sign_bit_copies[regno]
11284 = num_sign_bit_copies (value, GET_MODE (reg));
11288 /* Called via note_stores from record_dead_and_set_regs to handle one
11289 SET or CLOBBER in an insn. DATA is the instruction in which the
11290 set is occurring. */
11293 record_dead_and_set_regs_1 (dest, setter, data)
11297 rtx record_dead_insn = (rtx) data;
11299 if (GET_CODE (dest) == SUBREG)
11300 dest = SUBREG_REG (dest);
11302 if (GET_CODE (dest) == REG)
11304 /* If we are setting the whole register, we know its value. Otherwise
11305 show that we don't know the value. We can handle SUBREG in
11307 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11308 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11309 else if (GET_CODE (setter) == SET
11310 && GET_CODE (SET_DEST (setter)) == SUBREG
11311 && SUBREG_REG (SET_DEST (setter)) == dest
11312 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11313 && subreg_lowpart_p (SET_DEST (setter)))
11314 record_value_for_reg (dest, record_dead_insn,
11315 gen_lowpart_for_combine (GET_MODE (dest),
11316 SET_SRC (setter)));
11318 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11320 else if (GET_CODE (dest) == MEM
11321 /* Ignore pushes, they clobber nothing. */
11322 && ! push_operand (dest, GET_MODE (dest)))
11323 mem_last_set = INSN_CUID (record_dead_insn);
11326 /* Update the records of when each REG was most recently set or killed
11327 for the things done by INSN. This is the last thing done in processing
11328 INSN in the combiner loop.
11330 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11331 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11332 and also the similar information mem_last_set (which insn most recently
11333 modified memory) and last_call_cuid (which insn was the most recent
11334 subroutine call). */
11337 record_dead_and_set_regs (insn)
11343 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11345 if (REG_NOTE_KIND (link) == REG_DEAD
11346 && GET_CODE (XEXP (link, 0)) == REG)
11348 unsigned int regno = REGNO (XEXP (link, 0));
11349 unsigned int endregno
11350 = regno + (regno < FIRST_PSEUDO_REGISTER
11351 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11354 for (i = regno; i < endregno; i++)
11355 reg_last_death[i] = insn;
11357 else if (REG_NOTE_KIND (link) == REG_INC)
11358 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11361 if (GET_CODE (insn) == CALL_INSN)
11363 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11364 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11366 reg_last_set_value[i] = 0;
11367 reg_last_set_mode[i] = 0;
11368 reg_last_set_nonzero_bits[i] = 0;
11369 reg_last_set_sign_bit_copies[i] = 0;
11370 reg_last_death[i] = 0;
11373 last_call_cuid = mem_last_set = INSN_CUID (insn);
11375 /* Don't bother recording what this insn does. It might set the
11376 return value register, but we can't combine into a call
11377 pattern anyway, so there's no point trying (and it may cause
11378 a crash, if e.g. we wind up asking for last_set_value of a
11379 SUBREG of the return value register). */
11383 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11386 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11387 register present in the SUBREG, so for each such SUBREG go back and
11388 adjust nonzero and sign bit information of the registers that are
11389 known to have some zero/sign bits set.
11391 This is needed because when combine blows the SUBREGs away, the
11392 information on zero/sign bits is lost and further combines can be
11393 missed because of that. */
11396 record_promoted_value (insn, subreg)
11401 unsigned int regno = REGNO (SUBREG_REG (subreg));
11402 enum machine_mode mode = GET_MODE (subreg);
11404 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11407 for (links = LOG_LINKS (insn); links;)
11409 insn = XEXP (links, 0);
11410 set = single_set (insn);
11412 if (! set || GET_CODE (SET_DEST (set)) != REG
11413 || REGNO (SET_DEST (set)) != regno
11414 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11416 links = XEXP (links, 1);
11420 if (reg_last_set[regno] == insn)
11422 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11423 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11426 if (GET_CODE (SET_SRC (set)) == REG)
11428 regno = REGNO (SET_SRC (set));
11429 links = LOG_LINKS (insn);
11436 /* Scan X for promoted SUBREGs. For each one found,
11437 note what it implies to the registers used in it. */
11440 check_promoted_subreg (insn, x)
11444 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11445 && GET_CODE (SUBREG_REG (x)) == REG)
11446 record_promoted_value (insn, x);
11449 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11452 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11456 check_promoted_subreg (insn, XEXP (x, i));
11460 if (XVEC (x, i) != 0)
11461 for (j = 0; j < XVECLEN (x, i); j++)
11462 check_promoted_subreg (insn, XVECEXP (x, i, j));
11468 /* Utility routine for the following function. Verify that all the registers
11469 mentioned in *LOC are valid when *LOC was part of a value set when
11470 label_tick == TICK. Return 0 if some are not.
11472 If REPLACE is non-zero, replace the invalid reference with
11473 (clobber (const_int 0)) and return 1. This replacement is useful because
11474 we often can get useful information about the form of a value (e.g., if
11475 it was produced by a shift that always produces -1 or 0) even though
11476 we don't know exactly what registers it was produced from. */
11479 get_last_value_validate (loc, insn, tick, replace)
11486 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11487 int len = GET_RTX_LENGTH (GET_CODE (x));
11490 if (GET_CODE (x) == REG)
11492 unsigned int regno = REGNO (x);
11493 unsigned int endregno
11494 = regno + (regno < FIRST_PSEUDO_REGISTER
11495 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11498 for (j = regno; j < endregno; j++)
11499 if (reg_last_set_invalid[j]
11500 /* If this is a pseudo-register that was only set once and not
11501 live at the beginning of the function, it is always valid. */
11502 || (! (regno >= FIRST_PSEUDO_REGISTER
11503 && REG_N_SETS (regno) == 1
11504 && (! REGNO_REG_SET_P
11505 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11506 && reg_last_set_label[j] > tick))
11509 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11515 /* If this is a memory reference, make sure that there were
11516 no stores after it that might have clobbered the value. We don't
11517 have alias info, so we assume any store invalidates it. */
11518 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11519 && INSN_CUID (insn) <= mem_last_set)
11522 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11526 for (i = 0; i < len; i++)
11528 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11529 /* Don't bother with these. They shouldn't occur anyway. */
11533 /* If we haven't found a reason for it to be invalid, it is valid. */
11537 /* Get the last value assigned to X, if known. Some registers
11538 in the value may be replaced with (clobber (const_int 0)) if their value
11539 is known longer known reliably. */
11545 unsigned int regno;
11548 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11549 then convert it to the desired mode. If this is a paradoxical SUBREG,
11550 we cannot predict what values the "extra" bits might have. */
11551 if (GET_CODE (x) == SUBREG
11552 && subreg_lowpart_p (x)
11553 && (GET_MODE_SIZE (GET_MODE (x))
11554 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11555 && (value = get_last_value (SUBREG_REG (x))) != 0)
11556 return gen_lowpart_for_combine (GET_MODE (x), value);
11558 if (GET_CODE (x) != REG)
11562 value = reg_last_set_value[regno];
11564 /* If we don't have a value, or if it isn't for this basic block and
11565 it's either a hard register, set more than once, or it's a live
11566 at the beginning of the function, return 0.
11568 Because if it's not live at the beginning of the function then the reg
11569 is always set before being used (is never used without being set).
11570 And, if it's set only once, and it's always set before use, then all
11571 uses must have the same last value, even if it's not from this basic
11575 || (reg_last_set_label[regno] != label_tick
11576 && (regno < FIRST_PSEUDO_REGISTER
11577 || REG_N_SETS (regno) != 1
11578 || (REGNO_REG_SET_P
11579 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11582 /* If the value was set in a later insn than the ones we are processing,
11583 we can't use it even if the register was only set once. */
11584 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11587 /* If the value has all its registers valid, return it. */
11588 if (get_last_value_validate (&value, reg_last_set[regno],
11589 reg_last_set_label[regno], 0))
11592 /* Otherwise, make a copy and replace any invalid register with
11593 (clobber (const_int 0)). If that fails for some reason, return 0. */
11595 value = copy_rtx (value);
11596 if (get_last_value_validate (&value, reg_last_set[regno],
11597 reg_last_set_label[regno], 1))
11603 /* Return nonzero if expression X refers to a REG or to memory
11604 that is set in an instruction more recent than FROM_CUID. */
11607 use_crosses_set_p (x, from_cuid)
11613 enum rtx_code code = GET_CODE (x);
11617 unsigned int regno = REGNO (x);
11618 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11619 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11621 #ifdef PUSH_ROUNDING
11622 /* Don't allow uses of the stack pointer to be moved,
11623 because we don't know whether the move crosses a push insn. */
11624 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11627 for (; regno < endreg; regno++)
11628 if (reg_last_set[regno]
11629 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11634 if (code == MEM && mem_last_set > from_cuid)
11637 fmt = GET_RTX_FORMAT (code);
11639 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11644 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11645 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11648 else if (fmt[i] == 'e'
11649 && use_crosses_set_p (XEXP (x, i), from_cuid))
11655 /* Define three variables used for communication between the following
11658 static unsigned int reg_dead_regno, reg_dead_endregno;
11659 static int reg_dead_flag;
11661 /* Function called via note_stores from reg_dead_at_p.
11663 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11664 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11667 reg_dead_at_p_1 (dest, x, data)
11670 void *data ATTRIBUTE_UNUSED;
11672 unsigned int regno, endregno;
11674 if (GET_CODE (dest) != REG)
11677 regno = REGNO (dest);
11678 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11679 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11681 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11682 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11685 /* Return non-zero if REG is known to be dead at INSN.
11687 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11688 referencing REG, it is dead. If we hit a SET referencing REG, it is
11689 live. Otherwise, see if it is live or dead at the start of the basic
11690 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11691 must be assumed to be always live. */
11694 reg_dead_at_p (reg, insn)
11701 /* Set variables for reg_dead_at_p_1. */
11702 reg_dead_regno = REGNO (reg);
11703 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11704 ? HARD_REGNO_NREGS (reg_dead_regno,
11710 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11711 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11713 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11714 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11718 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11719 beginning of function. */
11720 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11721 insn = prev_nonnote_insn (insn))
11723 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11725 return reg_dead_flag == 1 ? 1 : 0;
11727 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11731 /* Get the basic block that we were in. */
11733 block = ENTRY_BLOCK_PTR->next_bb;
11736 FOR_EACH_BB (block)
11737 if (insn == block->head)
11740 if (block == EXIT_BLOCK_PTR)
11744 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11745 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11751 /* Note hard registers in X that are used. This code is similar to
11752 that in flow.c, but much simpler since we don't care about pseudos. */
11755 mark_used_regs_combine (x)
11758 RTX_CODE code = GET_CODE (x);
11759 unsigned int regno;
11772 case ADDR_DIFF_VEC:
11775 /* CC0 must die in the insn after it is set, so we don't need to take
11776 special note of it here. */
11782 /* If we are clobbering a MEM, mark any hard registers inside the
11783 address as used. */
11784 if (GET_CODE (XEXP (x, 0)) == MEM)
11785 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11790 /* A hard reg in a wide mode may really be multiple registers.
11791 If so, mark all of them just like the first. */
11792 if (regno < FIRST_PSEUDO_REGISTER)
11794 unsigned int endregno, r;
11796 /* None of this applies to the stack, frame or arg pointers */
11797 if (regno == STACK_POINTER_REGNUM
11798 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11799 || regno == HARD_FRAME_POINTER_REGNUM
11801 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11802 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11804 || regno == FRAME_POINTER_REGNUM)
11807 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11808 for (r = regno; r < endregno; r++)
11809 SET_HARD_REG_BIT (newpat_used_regs, r);
11815 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11817 rtx testreg = SET_DEST (x);
11819 while (GET_CODE (testreg) == SUBREG
11820 || GET_CODE (testreg) == ZERO_EXTRACT
11821 || GET_CODE (testreg) == SIGN_EXTRACT
11822 || GET_CODE (testreg) == STRICT_LOW_PART)
11823 testreg = XEXP (testreg, 0);
11825 if (GET_CODE (testreg) == MEM)
11826 mark_used_regs_combine (XEXP (testreg, 0));
11828 mark_used_regs_combine (SET_SRC (x));
11836 /* Recursively scan the operands of this expression. */
11839 const char *fmt = GET_RTX_FORMAT (code);
11841 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11844 mark_used_regs_combine (XEXP (x, i));
11845 else if (fmt[i] == 'E')
11849 for (j = 0; j < XVECLEN (x, i); j++)
11850 mark_used_regs_combine (XVECEXP (x, i, j));
11856 /* Remove register number REGNO from the dead registers list of INSN.
11858 Return the note used to record the death, if there was one. */
11861 remove_death (regno, insn)
11862 unsigned int regno;
11865 rtx note = find_regno_note (insn, REG_DEAD, regno);
11869 REG_N_DEATHS (regno)--;
11870 remove_note (insn, note);
11876 /* For each register (hardware or pseudo) used within expression X, if its
11877 death is in an instruction with cuid between FROM_CUID (inclusive) and
11878 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11879 list headed by PNOTES.
11881 That said, don't move registers killed by maybe_kill_insn.
11883 This is done when X is being merged by combination into TO_INSN. These
11884 notes will then be distributed as needed. */
11887 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11889 rtx maybe_kill_insn;
11896 enum rtx_code code = GET_CODE (x);
11900 unsigned int regno = REGNO (x);
11901 rtx where_dead = reg_last_death[regno];
11902 rtx before_dead, after_dead;
11904 /* Don't move the register if it gets killed in between from and to */
11905 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11906 && ! reg_referenced_p (x, maybe_kill_insn))
11909 /* WHERE_DEAD could be a USE insn made by combine, so first we
11910 make sure that we have insns with valid INSN_CUID values. */
11911 before_dead = where_dead;
11912 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11913 before_dead = PREV_INSN (before_dead);
11915 after_dead = where_dead;
11916 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11917 after_dead = NEXT_INSN (after_dead);
11919 if (before_dead && after_dead
11920 && INSN_CUID (before_dead) >= from_cuid
11921 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11922 || (where_dead != after_dead
11923 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11925 rtx note = remove_death (regno, where_dead);
11927 /* It is possible for the call above to return 0. This can occur
11928 when reg_last_death points to I2 or I1 that we combined with.
11929 In that case make a new note.
11931 We must also check for the case where X is a hard register
11932 and NOTE is a death note for a range of hard registers
11933 including X. In that case, we must put REG_DEAD notes for
11934 the remaining registers in place of NOTE. */
11936 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11937 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11938 > GET_MODE_SIZE (GET_MODE (x))))
11940 unsigned int deadregno = REGNO (XEXP (note, 0));
11941 unsigned int deadend
11942 = (deadregno + HARD_REGNO_NREGS (deadregno,
11943 GET_MODE (XEXP (note, 0))));
11944 unsigned int ourend
11945 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11948 for (i = deadregno; i < deadend; i++)
11949 if (i < regno || i >= ourend)
11950 REG_NOTES (where_dead)
11951 = gen_rtx_EXPR_LIST (REG_DEAD,
11953 REG_NOTES (where_dead));
11956 /* If we didn't find any note, or if we found a REG_DEAD note that
11957 covers only part of the given reg, and we have a multi-reg hard
11958 register, then to be safe we must check for REG_DEAD notes
11959 for each register other than the first. They could have
11960 their own REG_DEAD notes lying around. */
11961 else if ((note == 0
11963 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11964 < GET_MODE_SIZE (GET_MODE (x)))))
11965 && regno < FIRST_PSEUDO_REGISTER
11966 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11968 unsigned int ourend
11969 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11970 unsigned int i, offset;
11974 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11978 for (i = regno + offset; i < ourend; i++)
11979 move_deaths (regno_reg_rtx[i],
11980 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11983 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11985 XEXP (note, 1) = *pnotes;
11989 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11991 REG_N_DEATHS (regno)++;
11997 else if (GET_CODE (x) == SET)
11999 rtx dest = SET_DEST (x);
12001 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12003 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12004 that accesses one word of a multi-word item, some
12005 piece of everything register in the expression is used by
12006 this insn, so remove any old death. */
12007 /* ??? So why do we test for equality of the sizes? */
12009 if (GET_CODE (dest) == ZERO_EXTRACT
12010 || GET_CODE (dest) == STRICT_LOW_PART
12011 || (GET_CODE (dest) == SUBREG
12012 && (((GET_MODE_SIZE (GET_MODE (dest))
12013 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12014 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12015 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12017 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12021 /* If this is some other SUBREG, we know it replaces the entire
12022 value, so use that as the destination. */
12023 if (GET_CODE (dest) == SUBREG)
12024 dest = SUBREG_REG (dest);
12026 /* If this is a MEM, adjust deaths of anything used in the address.
12027 For a REG (the only other possibility), the entire value is
12028 being replaced so the old value is not used in this insn. */
12030 if (GET_CODE (dest) == MEM)
12031 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12036 else if (GET_CODE (x) == CLOBBER)
12039 len = GET_RTX_LENGTH (code);
12040 fmt = GET_RTX_FORMAT (code);
12042 for (i = 0; i < len; i++)
12047 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12048 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12051 else if (fmt[i] == 'e')
12052 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12056 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12057 pattern of an insn. X must be a REG. */
12060 reg_bitfield_target_p (x, body)
12066 if (GET_CODE (body) == SET)
12068 rtx dest = SET_DEST (body);
12070 unsigned int regno, tregno, endregno, endtregno;
12072 if (GET_CODE (dest) == ZERO_EXTRACT)
12073 target = XEXP (dest, 0);
12074 else if (GET_CODE (dest) == STRICT_LOW_PART)
12075 target = SUBREG_REG (XEXP (dest, 0));
12079 if (GET_CODE (target) == SUBREG)
12080 target = SUBREG_REG (target);
12082 if (GET_CODE (target) != REG)
12085 tregno = REGNO (target), regno = REGNO (x);
12086 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12087 return target == x;
12089 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12090 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12092 return endregno > tregno && regno < endtregno;
12095 else if (GET_CODE (body) == PARALLEL)
12096 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12097 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12103 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12104 as appropriate. I3 and I2 are the insns resulting from the combination
12105 insns including FROM (I2 may be zero).
12107 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12108 not need REG_DEAD notes because they are being substituted for. This
12109 saves searching in the most common cases.
12111 Each note in the list is either ignored or placed on some insns, depending
12112 on the type of note. */
12115 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12119 rtx elim_i2, elim_i1;
12121 rtx note, next_note;
12124 for (note = notes; note; note = next_note)
12126 rtx place = 0, place2 = 0;
12128 /* If this NOTE references a pseudo register, ensure it references
12129 the latest copy of that register. */
12130 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12131 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12132 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12134 next_note = XEXP (note, 1);
12135 switch (REG_NOTE_KIND (note))
12139 case REG_EXEC_COUNT:
12140 /* Doesn't matter much where we put this, as long as it's somewhere.
12141 It is preferable to keep these notes on branches, which is most
12142 likely to be i3. */
12146 case REG_VTABLE_REF:
12147 /* ??? Should remain with *a particular* memory load. Given the
12148 nature of vtable data, the last insn seems relatively safe. */
12152 case REG_NON_LOCAL_GOTO:
12153 if (GET_CODE (i3) == JUMP_INSN)
12155 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12161 case REG_EH_REGION:
12162 /* These notes must remain with the call or trapping instruction. */
12163 if (GET_CODE (i3) == CALL_INSN)
12165 else if (i2 && GET_CODE (i2) == CALL_INSN)
12167 else if (flag_non_call_exceptions)
12169 if (may_trap_p (i3))
12171 else if (i2 && may_trap_p (i2))
12173 /* ??? Otherwise assume we've combined things such that we
12174 can now prove that the instructions can't trap. Drop the
12175 note in this case. */
12183 /* These notes must remain with the call. It should not be
12184 possible for both I2 and I3 to be a call. */
12185 if (GET_CODE (i3) == CALL_INSN)
12187 else if (i2 && GET_CODE (i2) == CALL_INSN)
12194 /* Any clobbers for i3 may still exist, and so we must process
12195 REG_UNUSED notes from that insn.
12197 Any clobbers from i2 or i1 can only exist if they were added by
12198 recog_for_combine. In that case, recog_for_combine created the
12199 necessary REG_UNUSED notes. Trying to keep any original
12200 REG_UNUSED notes from these insns can cause incorrect output
12201 if it is for the same register as the original i3 dest.
12202 In that case, we will notice that the register is set in i3,
12203 and then add a REG_UNUSED note for the destination of i3, which
12204 is wrong. However, it is possible to have REG_UNUSED notes from
12205 i2 or i1 for register which were both used and clobbered, so
12206 we keep notes from i2 or i1 if they will turn into REG_DEAD
12209 /* If this register is set or clobbered in I3, put the note there
12210 unless there is one already. */
12211 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12213 if (from_insn != i3)
12216 if (! (GET_CODE (XEXP (note, 0)) == REG
12217 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12218 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12221 /* Otherwise, if this register is used by I3, then this register
12222 now dies here, so we must put a REG_DEAD note here unless there
12224 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12225 && ! (GET_CODE (XEXP (note, 0)) == REG
12226 ? find_regno_note (i3, REG_DEAD,
12227 REGNO (XEXP (note, 0)))
12228 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12230 PUT_REG_NOTE_KIND (note, REG_DEAD);
12238 /* These notes say something about results of an insn. We can
12239 only support them if they used to be on I3 in which case they
12240 remain on I3. Otherwise they are ignored.
12242 If the note refers to an expression that is not a constant, we
12243 must also ignore the note since we cannot tell whether the
12244 equivalence is still true. It might be possible to do
12245 slightly better than this (we only have a problem if I2DEST
12246 or I1DEST is present in the expression), but it doesn't
12247 seem worth the trouble. */
12249 if (from_insn == i3
12250 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12255 case REG_NO_CONFLICT:
12256 /* These notes say something about how a register is used. They must
12257 be present on any use of the register in I2 or I3. */
12258 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12261 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12271 /* This can show up in several ways -- either directly in the
12272 pattern, or hidden off in the constant pool with (or without?)
12273 a REG_EQUAL note. */
12274 /* ??? Ignore the without-reg_equal-note problem for now. */
12275 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12276 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12277 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12278 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12282 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12283 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12284 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12285 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12293 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12294 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12295 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12297 if (JUMP_LABEL (place) != XEXP (note, 0))
12299 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12300 LABEL_NUSES (JUMP_LABEL (place))--;
12303 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12305 if (JUMP_LABEL (place2) != XEXP (note, 0))
12307 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12308 LABEL_NUSES (JUMP_LABEL (place2))--;
12315 /* These notes say something about the value of a register prior
12316 to the execution of an insn. It is too much trouble to see
12317 if the note is still correct in all situations. It is better
12318 to simply delete it. */
12322 /* If the insn previously containing this note still exists,
12323 put it back where it was. Otherwise move it to the previous
12324 insn. Adjust the corresponding REG_LIBCALL note. */
12325 if (GET_CODE (from_insn) != NOTE)
12329 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12330 place = prev_real_insn (from_insn);
12332 XEXP (tem, 0) = place;
12333 /* If we're deleting the last remaining instruction of a
12334 libcall sequence, don't add the notes. */
12335 else if (XEXP (note, 0) == from_insn)
12341 /* This is handled similarly to REG_RETVAL. */
12342 if (GET_CODE (from_insn) != NOTE)
12346 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12347 place = next_real_insn (from_insn);
12349 XEXP (tem, 0) = place;
12350 /* If we're deleting the last remaining instruction of a
12351 libcall sequence, don't add the notes. */
12352 else if (XEXP (note, 0) == from_insn)
12358 /* If the register is used as an input in I3, it dies there.
12359 Similarly for I2, if it is non-zero and adjacent to I3.
12361 If the register is not used as an input in either I3 or I2
12362 and it is not one of the registers we were supposed to eliminate,
12363 there are two possibilities. We might have a non-adjacent I2
12364 or we might have somehow eliminated an additional register
12365 from a computation. For example, we might have had A & B where
12366 we discover that B will always be zero. In this case we will
12367 eliminate the reference to A.
12369 In both cases, we must search to see if we can find a previous
12370 use of A and put the death note there. */
12373 && GET_CODE (from_insn) == CALL_INSN
12374 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12376 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12378 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12379 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12382 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12383 || rtx_equal_p (XEXP (note, 0), elim_i1))
12388 basic_block bb = this_basic_block;
12390 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12392 if (! INSN_P (tem))
12394 if (tem == bb->head)
12399 /* If the register is being set at TEM, see if that is all
12400 TEM is doing. If so, delete TEM. Otherwise, make this
12401 into a REG_UNUSED note instead. */
12402 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12404 rtx set = single_set (tem);
12405 rtx inner_dest = 0;
12407 rtx cc0_setter = NULL_RTX;
12411 for (inner_dest = SET_DEST (set);
12412 (GET_CODE (inner_dest) == STRICT_LOW_PART
12413 || GET_CODE (inner_dest) == SUBREG
12414 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12415 inner_dest = XEXP (inner_dest, 0))
12418 /* Verify that it was the set, and not a clobber that
12419 modified the register.
12421 CC0 targets must be careful to maintain setter/user
12422 pairs. If we cannot delete the setter due to side
12423 effects, mark the user with an UNUSED note instead
12426 if (set != 0 && ! side_effects_p (SET_SRC (set))
12427 && rtx_equal_p (XEXP (note, 0), inner_dest)
12429 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12430 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12431 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12435 /* Move the notes and links of TEM elsewhere.
12436 This might delete other dead insns recursively.
12437 First set the pattern to something that won't use
12440 PATTERN (tem) = pc_rtx;
12442 distribute_notes (REG_NOTES (tem), tem, tem,
12443 NULL_RTX, NULL_RTX, NULL_RTX);
12444 distribute_links (LOG_LINKS (tem));
12446 PUT_CODE (tem, NOTE);
12447 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12448 NOTE_SOURCE_FILE (tem) = 0;
12451 /* Delete the setter too. */
12454 PATTERN (cc0_setter) = pc_rtx;
12456 distribute_notes (REG_NOTES (cc0_setter),
12457 cc0_setter, cc0_setter,
12458 NULL_RTX, NULL_RTX, NULL_RTX);
12459 distribute_links (LOG_LINKS (cc0_setter));
12461 PUT_CODE (cc0_setter, NOTE);
12462 NOTE_LINE_NUMBER (cc0_setter)
12463 = NOTE_INSN_DELETED;
12464 NOTE_SOURCE_FILE (cc0_setter) = 0;
12468 /* If the register is both set and used here, put the
12469 REG_DEAD note here, but place a REG_UNUSED note
12470 here too unless there already is one. */
12471 else if (reg_referenced_p (XEXP (note, 0),
12476 if (! find_regno_note (tem, REG_UNUSED,
12477 REGNO (XEXP (note, 0))))
12479 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12484 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12486 /* If there isn't already a REG_UNUSED note, put one
12488 if (! find_regno_note (tem, REG_UNUSED,
12489 REGNO (XEXP (note, 0))))
12494 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12495 || (GET_CODE (tem) == CALL_INSN
12496 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12500 /* If we are doing a 3->2 combination, and we have a
12501 register which formerly died in i3 and was not used
12502 by i2, which now no longer dies in i3 and is used in
12503 i2 but does not die in i2, and place is between i2
12504 and i3, then we may need to move a link from place to
12506 if (i2 && INSN_UID (place) <= max_uid_cuid
12507 && INSN_CUID (place) > INSN_CUID (i2)
12509 && INSN_CUID (from_insn) > INSN_CUID (i2)
12510 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12512 rtx links = LOG_LINKS (place);
12513 LOG_LINKS (place) = 0;
12514 distribute_links (links);
12519 if (tem == bb->head)
12523 /* We haven't found an insn for the death note and it
12524 is still a REG_DEAD note, but we have hit the beginning
12525 of the block. If the existing life info says the reg
12526 was dead, there's nothing left to do. Otherwise, we'll
12527 need to do a global life update after combine. */
12528 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12529 && REGNO_REG_SET_P (bb->global_live_at_start,
12530 REGNO (XEXP (note, 0))))
12532 SET_BIT (refresh_blocks, this_basic_block->index);
12537 /* If the register is set or already dead at PLACE, we needn't do
12538 anything with this note if it is still a REG_DEAD note.
12539 We can here if it is set at all, not if is it totally replace,
12540 which is what `dead_or_set_p' checks, so also check for it being
12543 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12545 unsigned int regno = REGNO (XEXP (note, 0));
12547 /* Similarly, if the instruction on which we want to place
12548 the note is a noop, we'll need do a global live update
12549 after we remove them in delete_noop_moves. */
12550 if (noop_move_p (place))
12552 SET_BIT (refresh_blocks, this_basic_block->index);
12556 if (dead_or_set_p (place, XEXP (note, 0))
12557 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12559 /* Unless the register previously died in PLACE, clear
12560 reg_last_death. [I no longer understand why this is
12562 if (reg_last_death[regno] != place)
12563 reg_last_death[regno] = 0;
12567 reg_last_death[regno] = place;
12569 /* If this is a death note for a hard reg that is occupying
12570 multiple registers, ensure that we are still using all
12571 parts of the object. If we find a piece of the object
12572 that is unused, we must arrange for an appropriate REG_DEAD
12573 note to be added for it. However, we can't just emit a USE
12574 and tag the note to it, since the register might actually
12575 be dead; so we recourse, and the recursive call then finds
12576 the previous insn that used this register. */
12578 if (place && regno < FIRST_PSEUDO_REGISTER
12579 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12581 unsigned int endregno
12582 = regno + HARD_REGNO_NREGS (regno,
12583 GET_MODE (XEXP (note, 0)));
12587 for (i = regno; i < endregno; i++)
12588 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12589 && ! find_regno_fusage (place, USE, i))
12590 || dead_or_set_regno_p (place, i))
12595 /* Put only REG_DEAD notes for pieces that are
12596 not already dead or set. */
12598 for (i = regno; i < endregno;
12599 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12601 rtx piece = regno_reg_rtx[i];
12602 basic_block bb = this_basic_block;
12604 if (! dead_or_set_p (place, piece)
12605 && ! reg_bitfield_target_p (piece,
12609 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12611 distribute_notes (new_note, place, place,
12612 NULL_RTX, NULL_RTX, NULL_RTX);
12614 else if (! refers_to_regno_p (i, i + 1,
12615 PATTERN (place), 0)
12616 && ! find_regno_fusage (place, USE, i))
12617 for (tem = PREV_INSN (place); ;
12618 tem = PREV_INSN (tem))
12620 if (! INSN_P (tem))
12622 if (tem == bb->head)
12624 SET_BIT (refresh_blocks,
12625 this_basic_block->index);
12631 if (dead_or_set_p (tem, piece)
12632 || reg_bitfield_target_p (piece,
12636 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12651 /* Any other notes should not be present at this point in the
12658 XEXP (note, 1) = REG_NOTES (place);
12659 REG_NOTES (place) = note;
12661 else if ((REG_NOTE_KIND (note) == REG_DEAD
12662 || REG_NOTE_KIND (note) == REG_UNUSED)
12663 && GET_CODE (XEXP (note, 0)) == REG)
12664 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12668 if ((REG_NOTE_KIND (note) == REG_DEAD
12669 || REG_NOTE_KIND (note) == REG_UNUSED)
12670 && GET_CODE (XEXP (note, 0)) == REG)
12671 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12673 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12674 REG_NOTE_KIND (note),
12676 REG_NOTES (place2));
12681 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12682 I3, I2, and I1 to new locations. This is also called in one case to
12683 add a link pointing at I3 when I3's destination is changed. */
12686 distribute_links (links)
12689 rtx link, next_link;
12691 for (link = links; link; link = next_link)
12697 next_link = XEXP (link, 1);
12699 /* If the insn that this link points to is a NOTE or isn't a single
12700 set, ignore it. In the latter case, it isn't clear what we
12701 can do other than ignore the link, since we can't tell which
12702 register it was for. Such links wouldn't be used by combine
12705 It is not possible for the destination of the target of the link to
12706 have been changed by combine. The only potential of this is if we
12707 replace I3, I2, and I1 by I3 and I2. But in that case the
12708 destination of I2 also remains unchanged. */
12710 if (GET_CODE (XEXP (link, 0)) == NOTE
12711 || (set = single_set (XEXP (link, 0))) == 0)
12714 reg = SET_DEST (set);
12715 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12716 || GET_CODE (reg) == SIGN_EXTRACT
12717 || GET_CODE (reg) == STRICT_LOW_PART)
12718 reg = XEXP (reg, 0);
12720 /* A LOG_LINK is defined as being placed on the first insn that uses
12721 a register and points to the insn that sets the register. Start
12722 searching at the next insn after the target of the link and stop
12723 when we reach a set of the register or the end of the basic block.
12725 Note that this correctly handles the link that used to point from
12726 I3 to I2. Also note that not much searching is typically done here
12727 since most links don't point very far away. */
12729 for (insn = NEXT_INSN (XEXP (link, 0));
12730 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12731 || this_basic_block->next_bb->head != insn));
12732 insn = NEXT_INSN (insn))
12733 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12735 if (reg_referenced_p (reg, PATTERN (insn)))
12739 else if (GET_CODE (insn) == CALL_INSN
12740 && find_reg_fusage (insn, USE, reg))
12746 /* If we found a place to put the link, place it there unless there
12747 is already a link to the same insn as LINK at that point. */
12753 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12754 if (XEXP (link2, 0) == XEXP (link, 0))
12759 XEXP (link, 1) = LOG_LINKS (place);
12760 LOG_LINKS (place) = link;
12762 /* Set added_links_insn to the earliest insn we added a
12764 if (added_links_insn == 0
12765 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12766 added_links_insn = place;
12772 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12778 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12779 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12780 insn = NEXT_INSN (insn);
12782 if (INSN_UID (insn) > max_uid_cuid)
12785 return INSN_CUID (insn);
12789 dump_combine_stats (file)
12794 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12795 combine_attempts, combine_merges, combine_extras, combine_successes);
12799 dump_combine_total_stats (file)
12804 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12805 total_attempts, total_merges, total_extras, total_successes);