1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
101 #include "tree-pass.h"
103 #include "valtrack.h"
107 /* Number of attempts to combine instructions in this function. */
109 static int combine_attempts;
111 /* Number of attempts that got as far as substitution in this function. */
113 static int combine_merges;
115 /* Number of instructions combined with added SETs in this function. */
117 static int combine_extras;
119 /* Number of instructions combined in this function. */
121 static int combine_successes;
123 /* Totals over entire compilation. */
125 static int total_attempts, total_merges, total_extras, total_successes;
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
138 static rtx i2mod_old_rhs;
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
142 static rtx i2mod_new_rhs;
144 typedef struct reg_stat_struct {
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
201 int last_set_table_tick;
203 /* Record the value of label_tick when the value for register n is placed in
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
213 unsigned HOST_WIDE_INT last_set_nonzero_bits;
214 char last_set_sign_bit_copies;
215 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
221 char last_set_invalid;
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
233 If an entry is zero, it means that we don't know anything special. */
235 unsigned char sign_bit_copies;
237 unsigned HOST_WIDE_INT nonzero_bits;
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
243 int truncation_label;
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
250 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 static vec<reg_stat_type> reg_stat;
256 /* Record the luid of the last insn that invalidated memory
257 (anything that writes memory, and subroutine calls, but not pushes). */
259 static int mem_last_set;
261 /* Record the luid of the last CALL_INSN
262 so we can tell whether a potential combination crosses any calls. */
264 static int last_call_luid;
266 /* When `subst' is called, this is the insn that is being modified
267 (by combining in a previous insn). The PATTERN of this insn
268 is still the old pattern partially modified and it should not be
269 looked at, but this may be used to examine the successors of the insn
270 to judge whether a simplification is valid. */
272 static rtx subst_insn;
274 /* This is the lowest LUID that `subst' is currently dealing with.
275 get_last_value will not return a value if the register was set at or
276 after this LUID. If not for this mechanism, we could get confused if
277 I2 or I1 in try_combine were an insn that used the old value of a register
278 to obtain a new value. In that case, we might erroneously get the
279 new value of the register when we wanted the old one. */
281 static int subst_low_luid;
283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
284 must consider all these registers to be always live. */
286 static HARD_REG_SET newpat_used_regs;
288 /* This is an insn to which a LOG_LINKS entry has been added. If this
289 insn is the earlier than I2 or I3, combine should rescan starting at
292 static rtx added_links_insn;
294 /* Basic block in which we are performing combines. */
295 static basic_block this_basic_block;
296 static bool optimize_this_for_speed_p;
299 /* Length of the currently allocated uid_insn_cost array. */
301 static int max_uid_known;
303 /* The following array records the insn_rtx_cost for every insn
304 in the instruction stream. */
306 static int *uid_insn_cost;
308 /* The following array records the LOG_LINKS for every insn in the
309 instruction stream as struct insn_link pointers. */
313 struct insn_link *next;
316 static struct insn_link **uid_log_links;
318 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
319 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
321 #define FOR_EACH_LOG_LINK(L, INSN) \
322 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
324 /* Links for LOG_LINKS are allocated from this obstack. */
326 static struct obstack insn_link_obstack;
328 /* Allocate a link. */
330 static inline struct insn_link *
331 alloc_insn_link (rtx insn, struct insn_link *next)
334 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
335 sizeof (struct insn_link));
341 /* Incremented for each basic block. */
343 static int label_tick;
345 /* Reset to label_tick for each extended basic block in scanning order. */
347 static int label_tick_ebb_start;
349 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
350 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
352 static enum machine_mode nonzero_bits_mode;
354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
355 be safely used. It is zero while computing them and after combine has
356 completed. This former test prevents propagating values based on
357 previously set values, which can be incorrect if a variable is modified
360 static int nonzero_sign_valid;
363 /* Record one modification to rtl structure
364 to be undone by storing old_contents into *where. */
366 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
372 union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
373 union { rtx *r; int *i; struct insn_link **l; } where;
376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
377 num_undo says how many are currently recorded.
379 other_insn is nonzero if we have modified some other insn in the process
380 of working on subst_insn. It must be verified too. */
389 static struct undobuf undobuf;
391 /* Number of times the pseudo being substituted for
392 was found and replaced. */
394 static int n_occurrences;
396 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
398 unsigned HOST_WIDE_INT,
399 unsigned HOST_WIDE_INT *);
400 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
402 unsigned int, unsigned int *);
403 static void do_SUBST (rtx *, rtx);
404 static void do_SUBST_INT (int *, int);
405 static void init_reg_last (void);
406 static void setup_incoming_promotions (rtx);
407 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
408 static int cant_combine_insn_p (rtx);
409 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
410 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
411 static int contains_muldiv (rtx);
412 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
413 static void undo_all (void);
414 static void undo_commit (void);
415 static rtx *find_split_point (rtx *, rtx, bool);
416 static rtx subst (rtx, rtx, rtx, int, int, int);
417 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
418 static rtx simplify_if_then_else (rtx);
419 static rtx simplify_set (rtx);
420 static rtx simplify_logical (rtx);
421 static rtx expand_compound_operation (rtx);
422 static const_rtx expand_field_assignment (const_rtx);
423 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
424 rtx, unsigned HOST_WIDE_INT, int, int, int);
425 static rtx extract_left_shift (rtx, int);
426 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
427 unsigned HOST_WIDE_INT *);
428 static rtx canon_reg_for_combine (rtx, rtx);
429 static rtx force_to_mode (rtx, enum machine_mode,
430 unsigned HOST_WIDE_INT, int);
431 static rtx if_then_else_cond (rtx, rtx *, rtx *);
432 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
433 static int rtx_equal_for_field_assignment_p (rtx, rtx);
434 static rtx make_field_assignment (rtx);
435 static rtx apply_distributive_law (rtx);
436 static rtx distribute_and_simplify_rtx (rtx, int);
437 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
438 unsigned HOST_WIDE_INT);
439 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
440 unsigned HOST_WIDE_INT);
441 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
442 HOST_WIDE_INT, enum machine_mode, int *);
443 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
444 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
446 static int recog_for_combine (rtx *, rtx, rtx *);
447 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
448 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
449 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
450 static void update_table_tick (rtx);
451 static void record_value_for_reg (rtx, rtx, rtx);
452 static void check_promoted_subreg (rtx, rtx);
453 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
454 static void record_dead_and_set_regs (rtx);
455 static int get_last_value_validate (rtx *, rtx, int, int);
456 static rtx get_last_value (const_rtx);
457 static int use_crosses_set_p (const_rtx, int);
458 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
459 static int reg_dead_at_p (rtx, rtx);
460 static void move_deaths (rtx, rtx, int, rtx, rtx *);
461 static int reg_bitfield_target_p (rtx, rtx);
462 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
463 static void distribute_links (struct insn_link *);
464 static void mark_used_regs_combine (rtx);
465 static void record_promoted_value (rtx, rtx);
466 static int unmentioned_reg_p_1 (rtx *, void *);
467 static bool unmentioned_reg_p (rtx, rtx);
468 static int record_truncated_value (rtx *, void *);
469 static void record_truncated_values (rtx *, void *);
470 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
471 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
474 /* It is not safe to use ordinary gen_lowpart in combine.
475 See comments in gen_lowpart_for_combine. */
476 #undef RTL_HOOKS_GEN_LOWPART
477 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
479 /* Our implementation of gen_lowpart never emits a new pseudo. */
480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
484 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
492 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
495 /* Convenience wrapper for the canonicalize_comparison target hook.
496 Target hooks cannot use enum rtx_code. */
498 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
499 bool op0_preserve_value)
501 int code_int = (int)*code;
502 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
503 *code = (enum rtx_code)code_int;
506 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
507 PATTERN can not be split. Otherwise, it returns an insn sequence.
508 This is a wrapper around split_insns which ensures that the
509 reg_stat vector is made larger if the splitter creates a new
513 combine_split_insns (rtx pattern, rtx insn)
518 ret = split_insns (pattern, insn);
519 nregs = max_reg_num ();
520 if (nregs > reg_stat.length ())
521 reg_stat.safe_grow_cleared (nregs);
525 /* This is used by find_single_use to locate an rtx in LOC that
526 contains exactly one use of DEST, which is typically either a REG
527 or CC0. It returns a pointer to the innermost rtx expression
528 containing DEST. Appearances of DEST that are being used to
529 totally replace it are not counted. */
532 find_single_use_1 (rtx dest, rtx *loc)
535 enum rtx_code code = GET_CODE (x);
551 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
552 of a REG that occupies all of the REG, the insn uses DEST if
553 it is mentioned in the destination or the source. Otherwise, we
554 need just check the source. */
555 if (GET_CODE (SET_DEST (x)) != CC0
556 && GET_CODE (SET_DEST (x)) != PC
557 && !REG_P (SET_DEST (x))
558 && ! (GET_CODE (SET_DEST (x)) == SUBREG
559 && REG_P (SUBREG_REG (SET_DEST (x)))
560 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
561 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
562 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
563 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
566 return find_single_use_1 (dest, &SET_SRC (x));
570 return find_single_use_1 (dest, &XEXP (x, 0));
576 /* If it wasn't one of the common cases above, check each expression and
577 vector of this code. Look for a unique usage of DEST. */
579 fmt = GET_RTX_FORMAT (code);
580 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
584 if (dest == XEXP (x, i)
585 || (REG_P (dest) && REG_P (XEXP (x, i))
586 && REGNO (dest) == REGNO (XEXP (x, i))))
589 this_result = find_single_use_1 (dest, &XEXP (x, i));
592 result = this_result;
593 else if (this_result)
594 /* Duplicate usage. */
597 else if (fmt[i] == 'E')
601 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
603 if (XVECEXP (x, i, j) == dest
605 && REG_P (XVECEXP (x, i, j))
606 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
609 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
612 result = this_result;
613 else if (this_result)
623 /* See if DEST, produced in INSN, is used only a single time in the
624 sequel. If so, return a pointer to the innermost rtx expression in which
627 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
629 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
630 care about REG_DEAD notes or LOG_LINKS.
632 Otherwise, we find the single use by finding an insn that has a
633 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
634 only referenced once in that insn, we know that it must be the first
635 and last insn referencing DEST. */
638 find_single_use (rtx dest, rtx insn, rtx *ploc)
643 struct insn_link *link;
648 next = NEXT_INSN (insn);
650 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
653 result = find_single_use_1 (dest, &PATTERN (next));
663 bb = BLOCK_FOR_INSN (insn);
664 for (next = NEXT_INSN (insn);
665 next && BLOCK_FOR_INSN (next) == bb;
666 next = NEXT_INSN (next))
667 if (INSN_P (next) && dead_or_set_p (next, dest))
669 FOR_EACH_LOG_LINK (link, next)
670 if (link->insn == insn)
675 result = find_single_use_1 (dest, &PATTERN (next));
685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
686 insn. The substitution can be undone by undo_all. If INTO is already
687 set to NEWVAL, do not record this change. Because computing NEWVAL might
688 also call SUBST, we have to compute it before we put anything into
692 do_SUBST (rtx *into, rtx newval)
697 if (oldval == newval)
700 /* We'd like to catch as many invalid transformations here as
701 possible. Unfortunately, there are way too many mode changes
702 that are perfectly valid, so we'd waste too much effort for
703 little gain doing the checks here. Focus on catching invalid
704 transformations involving integer constants. */
705 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
706 && CONST_INT_P (newval))
708 /* Sanity check that we're replacing oldval with a CONST_INT
709 that is a valid sign-extension for the original mode. */
710 gcc_assert (INTVAL (newval)
711 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
713 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
714 CONST_INT is not valid, because after the replacement, the
715 original mode would be gone. Unfortunately, we can't tell
716 when do_SUBST is called to replace the operand thereof, so we
717 perform this test on oldval instead, checking whether an
718 invalid replacement took place before we got here. */
719 gcc_assert (!(GET_CODE (oldval) == SUBREG
720 && CONST_INT_P (SUBREG_REG (oldval))));
721 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
722 && CONST_INT_P (XEXP (oldval, 0))));
726 buf = undobuf.frees, undobuf.frees = buf->next;
728 buf = XNEW (struct undo);
730 buf->kind = UNDO_RTX;
732 buf->old_contents.r = oldval;
735 buf->next = undobuf.undos, undobuf.undos = buf;
738 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
740 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
741 for the value of a HOST_WIDE_INT value (including CONST_INT) is
745 do_SUBST_INT (int *into, int newval)
750 if (oldval == newval)
754 buf = undobuf.frees, undobuf.frees = buf->next;
756 buf = XNEW (struct undo);
758 buf->kind = UNDO_INT;
760 buf->old_contents.i = oldval;
763 buf->next = undobuf.undos, undobuf.undos = buf;
766 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
768 /* Similar to SUBST, but just substitute the mode. This is used when
769 changing the mode of a pseudo-register, so that any other
770 references to the entry in the regno_reg_rtx array will change as
774 do_SUBST_MODE (rtx *into, enum machine_mode newval)
777 enum machine_mode oldval = GET_MODE (*into);
779 if (oldval == newval)
783 buf = undobuf.frees, undobuf.frees = buf->next;
785 buf = XNEW (struct undo);
787 buf->kind = UNDO_MODE;
789 buf->old_contents.m = oldval;
790 adjust_reg_mode (*into, newval);
792 buf->next = undobuf.undos, undobuf.undos = buf;
795 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
801 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
804 struct insn_link * oldval = *into;
806 if (oldval == newval)
810 buf = undobuf.frees, undobuf.frees = buf->next;
812 buf = XNEW (struct undo);
814 buf->kind = UNDO_LINKS;
816 buf->old_contents.l = oldval;
819 buf->next = undobuf.undos, undobuf.undos = buf;
822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
825 /* Subroutine of try_combine. Determine whether the replacement patterns
826 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
827 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
828 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
829 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
830 of all the instructions can be estimated and the replacements are more
831 expensive than the original sequence. */
834 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
835 rtx newi2pat, rtx newotherpat)
837 int i0_cost, i1_cost, i2_cost, i3_cost;
838 int new_i2_cost, new_i3_cost;
839 int old_cost, new_cost;
841 /* Lookup the original insn_rtx_costs. */
842 i2_cost = INSN_COST (i2);
843 i3_cost = INSN_COST (i3);
847 i1_cost = INSN_COST (i1);
850 i0_cost = INSN_COST (i0);
851 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
852 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
856 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
857 ? i1_cost + i2_cost + i3_cost : 0);
863 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
864 i1_cost = i0_cost = 0;
867 /* Calculate the replacement insn_rtx_costs. */
868 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
871 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
872 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
873 ? new_i2_cost + new_i3_cost : 0;
877 new_cost = new_i3_cost;
881 if (undobuf.other_insn)
883 int old_other_cost, new_other_cost;
885 old_other_cost = INSN_COST (undobuf.other_insn);
886 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
887 if (old_other_cost > 0 && new_other_cost > 0)
889 old_cost += old_other_cost;
890 new_cost += new_other_cost;
896 /* Disallow this combination if both new_cost and old_cost are greater than
897 zero, and new_cost is greater than old cost. */
898 if (old_cost > 0 && new_cost > old_cost)
905 "rejecting combination of insns %d, %d, %d and %d\n",
906 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
908 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
909 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
914 "rejecting combination of insns %d, %d and %d\n",
915 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
916 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
917 i1_cost, i2_cost, i3_cost, old_cost);
922 "rejecting combination of insns %d and %d\n",
923 INSN_UID (i2), INSN_UID (i3));
924 fprintf (dump_file, "original costs %d + %d = %d\n",
925 i2_cost, i3_cost, old_cost);
930 fprintf (dump_file, "replacement costs %d + %d = %d\n",
931 new_i2_cost, new_i3_cost, new_cost);
934 fprintf (dump_file, "replacement cost %d\n", new_cost);
940 /* Update the uid_insn_cost array with the replacement costs. */
941 INSN_COST (i2) = new_i2_cost;
942 INSN_COST (i3) = new_i3_cost;
954 /* Delete any insns that copy a register to itself. */
957 delete_noop_moves (void)
964 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
966 next = NEXT_INSN (insn);
967 if (INSN_P (insn) && noop_move_p (insn))
970 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
972 delete_insn_and_edges (insn);
979 /* Fill in log links field for all insns. */
982 create_log_links (void)
986 df_ref *def_vec, *use_vec;
988 next_use = XCNEWVEC (rtx, max_reg_num ());
990 /* Pass through each block from the end, recording the uses of each
991 register and establishing log links when def is encountered.
992 Note that we do not clear next_use array in order to save time,
993 so we have to test whether the use is in the same basic block as def.
995 There are a few cases below when we do not consider the definition or
996 usage -- these are taken from original flow.c did. Don't ask me why it is
997 done this way; I don't know and if it works, I don't want to know. */
1001 FOR_BB_INSNS_REVERSE (bb, insn)
1003 if (!NONDEBUG_INSN_P (insn))
1006 /* Log links are created only once. */
1007 gcc_assert (!LOG_LINKS (insn));
1009 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1011 df_ref def = *def_vec;
1012 int regno = DF_REF_REGNO (def);
1015 if (!next_use[regno])
1018 /* Do not consider if it is pre/post modification in MEM. */
1019 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1022 /* Do not make the log link for frame pointer. */
1023 if ((regno == FRAME_POINTER_REGNUM
1024 && (! reload_completed || frame_pointer_needed))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026 || (regno == HARD_FRAME_POINTER_REGNUM
1027 && (! reload_completed || frame_pointer_needed))
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1035 use_insn = next_use[regno];
1036 if (BLOCK_FOR_INSN (use_insn) == bb)
1040 We don't build a LOG_LINK for hard registers contained
1041 in ASM_OPERANDs. If these registers get replaced,
1042 we might wind up changing the semantics of the insn,
1043 even if reload can make what appear to be valid
1044 assignments later. */
1045 if (regno >= FIRST_PSEUDO_REGISTER
1046 || asm_noperands (PATTERN (use_insn)) < 0)
1048 /* Don't add duplicate links between instructions. */
1049 struct insn_link *links;
1050 FOR_EACH_LOG_LINK (links, use_insn)
1051 if (insn == links->insn)
1055 LOG_LINKS (use_insn)
1056 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1059 next_use[regno] = NULL_RTX;
1062 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1064 df_ref use = *use_vec;
1065 int regno = DF_REF_REGNO (use);
1067 /* Do not consider the usage of the stack pointer
1068 by function call. */
1069 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1072 next_use[regno] = insn;
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1081 true if we found a LOG_LINK that proves that A feeds B. This only works
1082 if there are no instructions between A and B which could have a link
1083 depending on A, since in that case we would not record a link for B.
1084 We also check the implicit dependency created by a cc0 setter/user
1088 insn_a_feeds_b (rtx a, rtx b)
1090 struct insn_link *links;
1091 FOR_EACH_LOG_LINK (links, b)
1092 if (links->insn == a)
1101 /* Main entry point for combiner. F is the first insn of the function.
1102 NREGS is the first unused pseudo-reg number.
1104 Return nonzero if the combiner has turned an indirect jump
1105 instruction into a direct jump. */
1107 combine_instructions (rtx f, unsigned int nregs)
1113 struct insn_link *links, *nextlinks;
1115 basic_block last_bb;
1117 int new_direct_jump_p = 0;
1119 for (first = f; first && !INSN_P (first); )
1120 first = NEXT_INSN (first);
1124 combine_attempts = 0;
1127 combine_successes = 0;
1129 rtl_hooks = combine_rtl_hooks;
1131 reg_stat.safe_grow_cleared (nregs);
1133 init_recog_no_volatile ();
1135 /* Allocate array for insn info. */
1136 max_uid_known = get_max_uid ();
1137 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1138 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1139 gcc_obstack_init (&insn_link_obstack);
1141 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1143 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1144 problems when, for example, we have j <<= 1 in a loop. */
1146 nonzero_sign_valid = 0;
1147 label_tick = label_tick_ebb_start = 1;
1149 /* Scan all SETs and see if we can deduce anything about what
1150 bits are known to be zero for some registers and how many copies
1151 of the sign bit are known to exist for those registers.
1153 Also set any known values so that we can use it while searching
1154 for what bits are known to be set. */
1156 setup_incoming_promotions (first);
1157 /* Allow the entry block and the first block to fall into the same EBB.
1158 Conceptually the incoming promotions are assigned to the entry block. */
1159 last_bb = ENTRY_BLOCK_PTR;
1161 create_log_links ();
1162 FOR_EACH_BB (this_basic_block)
1164 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1169 if (!single_pred_p (this_basic_block)
1170 || single_pred (this_basic_block) != last_bb)
1171 label_tick_ebb_start = label_tick;
1172 last_bb = this_basic_block;
1174 FOR_BB_INSNS (this_basic_block, insn)
1175 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1181 subst_low_luid = DF_INSN_LUID (insn);
1184 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1186 record_dead_and_set_regs (insn);
1189 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1190 if (REG_NOTE_KIND (links) == REG_INC)
1191 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1195 /* Record the current insn_rtx_cost of this instruction. */
1196 if (NONJUMP_INSN_P (insn))
1197 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1198 optimize_this_for_speed_p);
1200 fprintf(dump_file, "insn_cost %d: %d\n",
1201 INSN_UID (insn), INSN_COST (insn));
1205 nonzero_sign_valid = 1;
1207 /* Now scan all the insns in forward order. */
1208 label_tick = label_tick_ebb_start = 1;
1210 setup_incoming_promotions (first);
1211 last_bb = ENTRY_BLOCK_PTR;
1213 FOR_EACH_BB (this_basic_block)
1215 rtx last_combined_insn = NULL_RTX;
1216 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1221 if (!single_pred_p (this_basic_block)
1222 || single_pred (this_basic_block) != last_bb)
1223 label_tick_ebb_start = label_tick;
1224 last_bb = this_basic_block;
1226 rtl_profile_for_bb (this_basic_block);
1227 for (insn = BB_HEAD (this_basic_block);
1228 insn != NEXT_INSN (BB_END (this_basic_block));
1229 insn = next ? next : NEXT_INSN (insn))
1232 if (NONDEBUG_INSN_P (insn))
1234 while (last_combined_insn
1235 && INSN_DELETED_P (last_combined_insn))
1236 last_combined_insn = PREV_INSN (last_combined_insn);
1237 if (last_combined_insn == NULL_RTX
1238 || BARRIER_P (last_combined_insn)
1239 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1240 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1241 last_combined_insn = insn;
1243 /* See if we know about function return values before this
1244 insn based upon SUBREG flags. */
1245 check_promoted_subreg (insn, PATTERN (insn));
1247 /* See if we can find hardregs and subreg of pseudos in
1248 narrower modes. This could help turning TRUNCATEs
1250 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1252 /* Try this insn with each insn it links back to. */
1254 FOR_EACH_LOG_LINK (links, insn)
1255 if ((next = try_combine (insn, links->insn, NULL_RTX,
1256 NULL_RTX, &new_direct_jump_p,
1257 last_combined_insn)) != 0)
1260 /* Try each sequence of three linked insns ending with this one. */
1262 FOR_EACH_LOG_LINK (links, insn)
1264 rtx link = links->insn;
1266 /* If the linked insn has been replaced by a note, then there
1267 is no point in pursuing this chain any further. */
1271 FOR_EACH_LOG_LINK (nextlinks, link)
1272 if ((next = try_combine (insn, link, nextlinks->insn,
1273 NULL_RTX, &new_direct_jump_p,
1274 last_combined_insn)) != 0)
1279 /* Try to combine a jump insn that uses CC0
1280 with a preceding insn that sets CC0, and maybe with its
1281 logical predecessor as well.
1282 This is how we make decrement-and-branch insns.
1283 We need this special code because data flow connections
1284 via CC0 do not get entered in LOG_LINKS. */
1287 && (prev = prev_nonnote_insn (insn)) != 0
1288 && NONJUMP_INSN_P (prev)
1289 && sets_cc0_p (PATTERN (prev)))
1291 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1293 last_combined_insn)) != 0)
1296 FOR_EACH_LOG_LINK (nextlinks, prev)
1297 if ((next = try_combine (insn, prev, nextlinks->insn,
1298 NULL_RTX, &new_direct_jump_p,
1299 last_combined_insn)) != 0)
1303 /* Do the same for an insn that explicitly references CC0. */
1304 if (NONJUMP_INSN_P (insn)
1305 && (prev = prev_nonnote_insn (insn)) != 0
1306 && NONJUMP_INSN_P (prev)
1307 && sets_cc0_p (PATTERN (prev))
1308 && GET_CODE (PATTERN (insn)) == SET
1309 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1311 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1313 last_combined_insn)) != 0)
1316 FOR_EACH_LOG_LINK (nextlinks, prev)
1317 if ((next = try_combine (insn, prev, nextlinks->insn,
1318 NULL_RTX, &new_direct_jump_p,
1319 last_combined_insn)) != 0)
1323 /* Finally, see if any of the insns that this insn links to
1324 explicitly references CC0. If so, try this insn, that insn,
1325 and its predecessor if it sets CC0. */
1326 FOR_EACH_LOG_LINK (links, insn)
1327 if (NONJUMP_INSN_P (links->insn)
1328 && GET_CODE (PATTERN (links->insn)) == SET
1329 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1330 && (prev = prev_nonnote_insn (links->insn)) != 0
1331 && NONJUMP_INSN_P (prev)
1332 && sets_cc0_p (PATTERN (prev))
1333 && (next = try_combine (insn, links->insn,
1334 prev, NULL_RTX, &new_direct_jump_p,
1335 last_combined_insn)) != 0)
1339 /* Try combining an insn with two different insns whose results it
1341 FOR_EACH_LOG_LINK (links, insn)
1342 for (nextlinks = links->next; nextlinks;
1343 nextlinks = nextlinks->next)
1344 if ((next = try_combine (insn, links->insn,
1345 nextlinks->insn, NULL_RTX,
1347 last_combined_insn)) != 0)
1350 /* Try four-instruction combinations. */
1351 FOR_EACH_LOG_LINK (links, insn)
1353 struct insn_link *next1;
1354 rtx link = links->insn;
1356 /* If the linked insn has been replaced by a note, then there
1357 is no point in pursuing this chain any further. */
1361 FOR_EACH_LOG_LINK (next1, link)
1363 rtx link1 = next1->insn;
1366 /* I0 -> I1 -> I2 -> I3. */
1367 FOR_EACH_LOG_LINK (nextlinks, link1)
1368 if ((next = try_combine (insn, link, link1,
1371 last_combined_insn)) != 0)
1373 /* I0, I1 -> I2, I2 -> I3. */
1374 for (nextlinks = next1->next; nextlinks;
1375 nextlinks = nextlinks->next)
1376 if ((next = try_combine (insn, link, link1,
1379 last_combined_insn)) != 0)
1383 for (next1 = links->next; next1; next1 = next1->next)
1385 rtx link1 = next1->insn;
1388 /* I0 -> I2; I1, I2 -> I3. */
1389 FOR_EACH_LOG_LINK (nextlinks, link)
1390 if ((next = try_combine (insn, link, link1,
1393 last_combined_insn)) != 0)
1395 /* I0 -> I1; I1, I2 -> I3. */
1396 FOR_EACH_LOG_LINK (nextlinks, link1)
1397 if ((next = try_combine (insn, link, link1,
1400 last_combined_insn)) != 0)
1405 /* Try this insn with each REG_EQUAL note it links back to. */
1406 FOR_EACH_LOG_LINK (links, insn)
1409 rtx temp = links->insn;
1410 if ((set = single_set (temp)) != 0
1411 && (note = find_reg_equal_equiv_note (temp)) != 0
1412 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1413 /* Avoid using a register that may already been marked
1414 dead by an earlier instruction. */
1415 && ! unmentioned_reg_p (note, SET_SRC (set))
1416 && (GET_MODE (note) == VOIDmode
1417 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1418 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1420 /* Temporarily replace the set's source with the
1421 contents of the REG_EQUAL note. The insn will
1422 be deleted or recognized by try_combine. */
1423 rtx orig = SET_SRC (set);
1424 SET_SRC (set) = note;
1426 i2mod_old_rhs = copy_rtx (orig);
1427 i2mod_new_rhs = copy_rtx (note);
1428 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1430 last_combined_insn);
1434 SET_SRC (set) = orig;
1439 record_dead_and_set_regs (insn);
1447 default_rtl_profile ();
1449 new_direct_jump_p |= purge_all_dead_edges ();
1450 delete_noop_moves ();
1453 obstack_free (&insn_link_obstack, NULL);
1454 free (uid_log_links);
1455 free (uid_insn_cost);
1456 reg_stat.release ();
1459 struct undo *undo, *next;
1460 for (undo = undobuf.frees; undo; undo = next)
1468 total_attempts += combine_attempts;
1469 total_merges += combine_merges;
1470 total_extras += combine_extras;
1471 total_successes += combine_successes;
1473 nonzero_sign_valid = 0;
1474 rtl_hooks = general_rtl_hooks;
1476 /* Make recognizer allow volatile MEMs again. */
1479 return new_direct_jump_p;
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1485 init_reg_last (void)
1490 FOR_EACH_VEC_ELT (reg_stat, i, p)
1491 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1494 /* Set up any promoted values for incoming argument registers. */
1497 setup_incoming_promotions (rtx first)
1500 bool strictly_local = false;
1502 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1503 arg = DECL_CHAIN (arg))
1505 rtx x, reg = DECL_INCOMING_RTL (arg);
1507 enum machine_mode mode1, mode2, mode3, mode4;
1509 /* Only continue if the incoming argument is in a register. */
1513 /* Determine, if possible, whether all call sites of the current
1514 function lie within the current compilation unit. (This does
1515 take into account the exporting of a function via taking its
1516 address, and so forth.) */
1517 strictly_local = cgraph_local_info (current_function_decl)->local;
1519 /* The mode and signedness of the argument before any promotions happen
1520 (equal to the mode of the pseudo holding it at that stage). */
1521 mode1 = TYPE_MODE (TREE_TYPE (arg));
1522 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1524 /* The mode and signedness of the argument after any source language and
1525 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1526 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1527 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1529 /* The mode and signedness of the argument as it is actually passed,
1530 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1531 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1532 TREE_TYPE (cfun->decl), 0);
1534 /* The mode of the register in which the argument is being passed. */
1535 mode4 = GET_MODE (reg);
1537 /* Eliminate sign extensions in the callee when:
1538 (a) A mode promotion has occurred; */
1541 /* (b) The mode of the register is the same as the mode of
1542 the argument as it is passed; */
1545 /* (c) There's no language level extension; */
1548 /* (c.1) All callers are from the current compilation unit. If that's
1549 the case we don't have to rely on an ABI, we only have to know
1550 what we're generating right now, and we know that we will do the
1551 mode1 to mode2 promotion with the given sign. */
1552 else if (!strictly_local)
1554 /* (c.2) The combination of the two promotions is useful. This is
1555 true when the signs match, or if the first promotion is unsigned.
1556 In the later case, (sign_extend (zero_extend x)) is the same as
1557 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1563 /* Record that the value was promoted from mode1 to mode3,
1564 so that any sign extension at the head of the current
1565 function may be eliminated. */
1566 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1567 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1568 record_value_for_reg (reg, first, x);
1572 /* Called via note_stores. If X is a pseudo that is narrower than
1573 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1575 If we are setting only a portion of X and we can't figure out what
1576 portion, assume all bits will be used since we don't know what will
1579 Similarly, set how many bits of X are known to be copies of the sign bit
1580 at all locations in the function. This is the smallest number implied
1584 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1586 rtx insn = (rtx) data;
1590 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1591 /* If this register is undefined at the start of the file, we can't
1592 say what its contents were. */
1593 && ! REGNO_REG_SET_P
1594 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1595 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1597 reg_stat_type *rsp = ®_stat[REGNO (x)];
1599 if (set == 0 || GET_CODE (set) == CLOBBER)
1601 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1602 rsp->sign_bit_copies = 1;
1606 /* If this register is being initialized using itself, and the
1607 register is uninitialized in this basic block, and there are
1608 no LOG_LINKS which set the register, then part of the
1609 register is uninitialized. In that case we can't assume
1610 anything about the number of nonzero bits.
1612 ??? We could do better if we checked this in
1613 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1614 could avoid making assumptions about the insn which initially
1615 sets the register, while still using the information in other
1616 insns. We would have to be careful to check every insn
1617 involved in the combination. */
1620 && reg_referenced_p (x, PATTERN (insn))
1621 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1624 struct insn_link *link;
1626 FOR_EACH_LOG_LINK (link, insn)
1627 if (dead_or_set_p (link->insn, x))
1631 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1632 rsp->sign_bit_copies = 1;
1637 /* If this is a complex assignment, see if we can convert it into a
1638 simple assignment. */
1639 set = expand_field_assignment (set);
1641 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642 set what we know about X. */
1644 if (SET_DEST (set) == x
1645 || (paradoxical_subreg_p (SET_DEST (set))
1646 && SUBREG_REG (SET_DEST (set)) == x))
1648 rtx src = SET_SRC (set);
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651 /* If X is narrower than a word and SRC is a non-negative
1652 constant that would appear negative in the mode of X,
1653 sign-extend it for use in reg_stat[].nonzero_bits because some
1654 machines (maybe most) will actually do the sign-extension
1655 and this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard
1658 instead of this kludge. */
1660 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1661 && CONST_INT_P (src)
1663 && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1664 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1667 /* Don't call nonzero_bits if it cannot change anything. */
1668 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1669 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1670 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1671 if (rsp->sign_bit_copies == 0
1672 || rsp->sign_bit_copies > num)
1673 rsp->sign_bit_copies = num;
1677 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1678 rsp->sign_bit_copies = 1;
1683 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1684 optionally insns that were previously combined into I3 or that will be
1685 combined into the merger of INSN and I3. The order is PRED, PRED2,
1686 INSN, SUCC, SUCC2, I3.
1688 Return 0 if the combination is not allowed for any reason.
1690 If the combination is allowed, *PDEST will be set to the single
1691 destination of INSN and *PSRC to the single source, and this function
1695 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1696 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1697 rtx *pdest, rtx *psrc)
1706 bool all_adjacent = true;
1707 int (*is_volatile_p) (const_rtx);
1713 if (next_active_insn (succ2) != i3)
1714 all_adjacent = false;
1715 if (next_active_insn (succ) != succ2)
1716 all_adjacent = false;
1718 else if (next_active_insn (succ) != i3)
1719 all_adjacent = false;
1720 if (next_active_insn (insn) != succ)
1721 all_adjacent = false;
1723 else if (next_active_insn (insn) != i3)
1724 all_adjacent = false;
1726 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727 or a PARALLEL consisting of such a SET and CLOBBERs.
1729 If INSN has CLOBBER parallel parts, ignore them for our processing.
1730 By definition, these happen during the execution of the insn. When it
1731 is merged with another insn, all bets are off. If they are, in fact,
1732 needed and aren't also supplied in I3, they may be added by
1733 recog_for_combine. Otherwise, it won't match.
1735 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1738 Get the source and destination of INSN. If more than one, can't
1741 if (GET_CODE (PATTERN (insn)) == SET)
1742 set = PATTERN (insn);
1743 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1744 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1746 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1748 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1750 switch (GET_CODE (elt))
1752 /* This is important to combine floating point insns
1753 for the SH4 port. */
1755 /* Combining an isolated USE doesn't make sense.
1756 We depend here on combinable_i3pat to reject them. */
1757 /* The code below this loop only verifies that the inputs of
1758 the SET in INSN do not change. We call reg_set_between_p
1759 to verify that the REG in the USE does not change between
1761 If the USE in INSN was for a pseudo register, the matching
1762 insn pattern will likely match any register; combining this
1763 with any other USE would only be safe if we knew that the
1764 used registers have identical values, or if there was
1765 something to tell them apart, e.g. different modes. For
1766 now, we forgo such complicated tests and simply disallow
1767 combining of USES of pseudo registers with any other USE. */
1768 if (REG_P (XEXP (elt, 0))
1769 && GET_CODE (PATTERN (i3)) == PARALLEL)
1771 rtx i3pat = PATTERN (i3);
1772 int i = XVECLEN (i3pat, 0) - 1;
1773 unsigned int regno = REGNO (XEXP (elt, 0));
1777 rtx i3elt = XVECEXP (i3pat, 0, i);
1779 if (GET_CODE (i3elt) == USE
1780 && REG_P (XEXP (i3elt, 0))
1781 && (REGNO (XEXP (i3elt, 0)) == regno
1782 ? reg_set_between_p (XEXP (elt, 0),
1783 PREV_INSN (insn), i3)
1784 : regno >= FIRST_PSEUDO_REGISTER))
1791 /* We can ignore CLOBBERs. */
1796 /* Ignore SETs whose result isn't used but not those that
1797 have side-effects. */
1798 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1799 && insn_nothrow_p (insn)
1800 && !side_effects_p (elt))
1803 /* If we have already found a SET, this is a second one and
1804 so we cannot combine with this insn. */
1812 /* Anything else means we can't combine. */
1818 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819 so don't do anything with it. */
1820 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1829 /* The simplification in expand_field_assignment may call back to
1830 get_last_value, so set safe guard here. */
1831 subst_low_luid = DF_INSN_LUID (insn);
1833 set = expand_field_assignment (set);
1834 src = SET_SRC (set), dest = SET_DEST (set);
1836 /* Don't eliminate a store in the stack pointer. */
1837 if (dest == stack_pointer_rtx
1838 /* Don't combine with an insn that sets a register to itself if it has
1839 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1840 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1841 /* Can't merge an ASM_OPERANDS. */
1842 || GET_CODE (src) == ASM_OPERANDS
1843 /* Can't merge a function call. */
1844 || GET_CODE (src) == CALL
1845 /* Don't eliminate a function call argument. */
1847 && (find_reg_fusage (i3, USE, dest)
1849 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1850 && global_regs[REGNO (dest)])))
1851 /* Don't substitute into an incremented register. */
1852 || FIND_REG_INC_NOTE (i3, dest)
1853 || (succ && FIND_REG_INC_NOTE (succ, dest))
1854 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1855 /* Don't substitute into a non-local goto, this confuses CFG. */
1856 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1857 /* Make sure that DEST is not used after SUCC but before I3. */
1860 && (reg_used_between_p (dest, succ2, i3)
1861 || reg_used_between_p (dest, succ, succ2)))
1862 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1863 /* Make sure that the value that is to be substituted for the register
1864 does not use any registers whose values alter in between. However,
1865 If the insns are adjacent, a use can't cross a set even though we
1866 think it might (this can happen for a sequence of insns each setting
1867 the same destination; last_set of that register might point to
1868 a NOTE). If INSN has a REG_EQUIV note, the register is always
1869 equivalent to the memory so the substitution is valid even if there
1870 are intervening stores. Also, don't move a volatile asm or
1871 UNSPEC_VOLATILE across any other insns. */
1874 || ! find_reg_note (insn, REG_EQUIV, src))
1875 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1876 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1877 || GET_CODE (src) == UNSPEC_VOLATILE))
1878 /* Don't combine across a CALL_INSN, because that would possibly
1879 change whether the life span of some REGs crosses calls or not,
1880 and it is a pain to update that information.
1881 Exception: if source is a constant, moving it later can't hurt.
1882 Accept that as a special case. */
1883 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1886 /* DEST must either be a REG or CC0. */
1889 /* If register alignment is being enforced for multi-word items in all
1890 cases except for parameters, it is possible to have a register copy
1891 insn referencing a hard register that is not allowed to contain the
1892 mode being copied and which would not be valid as an operand of most
1893 insns. Eliminate this problem by not combining with such an insn.
1895 Also, on some machines we don't want to extend the life of a hard
1899 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1900 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1901 /* Don't extend the life of a hard register unless it is
1902 user variable (if we have few registers) or it can't
1903 fit into the desired register (meaning something special
1905 Also avoid substituting a return register into I3, because
1906 reload can't handle a conflict with constraints of other
1908 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1909 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1912 else if (GET_CODE (dest) != CC0)
1916 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1917 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1918 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1920 /* Don't substitute for a register intended as a clobberable
1922 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1923 if (rtx_equal_p (reg, dest))
1926 /* If the clobber represents an earlyclobber operand, we must not
1927 substitute an expression containing the clobbered register.
1928 As we do not analyze the constraint strings here, we have to
1929 make the conservative assumption. However, if the register is
1930 a fixed hard reg, the clobber cannot represent any operand;
1931 we leave it up to the machine description to either accept or
1932 reject use-and-clobber patterns. */
1934 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1935 || !fixed_regs[REGNO (reg)])
1936 if (reg_overlap_mentioned_p (reg, src))
1940 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941 or not), reject, unless nothing volatile comes between it and I3 */
1943 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1945 /* Make sure neither succ nor succ2 contains a volatile reference. */
1946 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1948 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1950 /* We'll check insns between INSN and I3 below. */
1953 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954 to be an explicit register variable, and was chosen for a reason. */
1956 if (GET_CODE (src) == ASM_OPERANDS
1957 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1960 /* If INSN contains volatile references (specifically volatile MEMs),
1961 we cannot combine across any other volatile references.
1962 Even if INSN doesn't contain volatile references, any intervening
1963 volatile insn might affect machine state. */
1965 is_volatile_p = volatile_refs_p (PATTERN (insn))
1969 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1970 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1973 /* If INSN contains an autoincrement or autodecrement, make sure that
1974 register is not used between there and I3, and not already used in
1975 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1976 Also insist that I3 not be a jump; if it were one
1977 and the incremented register were spilled, we would lose. */
1980 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1981 if (REG_NOTE_KIND (link) == REG_INC
1983 || reg_used_between_p (XEXP (link, 0), insn, i3)
1984 || (pred != NULL_RTX
1985 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1986 || (pred2 != NULL_RTX
1987 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1988 || (succ != NULL_RTX
1989 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1990 || (succ2 != NULL_RTX
1991 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1992 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1997 /* Don't combine an insn that follows a CC0-setting insn.
1998 An insn that uses CC0 must not be separated from the one that sets it.
1999 We do, however, allow I2 to follow a CC0-setting insn if that insn
2000 is passed as I1; in that case it will be deleted also.
2001 We also allow combining in this case if all the insns are adjacent
2002 because that would leave the two CC0 insns adjacent as well.
2003 It would be more logical to test whether CC0 occurs inside I1 or I2,
2004 but that would be much slower, and this ought to be equivalent. */
2006 p = prev_nonnote_insn (insn);
2007 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2012 /* If we get here, we have passed all the tests and the combination is
2021 /* LOC is the location within I3 that contains its pattern or the component
2022 of a PARALLEL of the pattern. We validate that it is valid for combining.
2024 One problem is if I3 modifies its output, as opposed to replacing it
2025 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026 doing so would produce an insn that is not equivalent to the original insns.
2030 (set (reg:DI 101) (reg:DI 100))
2031 (set (subreg:SI (reg:DI 101) 0) <foo>)
2033 This is NOT equivalent to:
2035 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036 (set (reg:DI 101) (reg:DI 100))])
2038 Not only does this modify 100 (in which case it might still be valid
2039 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2041 We can also run into a problem if I2 sets a register that I1
2042 uses and I1 gets directly substituted into I3 (not via I2). In that
2043 case, we would be getting the wrong value of I2DEST into I3, so we
2044 must reject the combination. This case occurs when I2 and I1 both
2045 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047 of a SET must prevent combination from occurring. The same situation
2048 can occur for I0, in which case I0_NOT_IN_SRC is set.
2050 Before doing the above check, we first try to expand a field assignment
2051 into a set of logical operations.
2053 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054 we place a register that is both set and used within I3. If more than one
2055 such register is detected, we fail.
2057 Return 1 if the combination is valid, zero otherwise. */
2060 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2061 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2065 if (GET_CODE (x) == SET)
2068 rtx dest = SET_DEST (set);
2069 rtx src = SET_SRC (set);
2070 rtx inner_dest = dest;
2073 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2074 || GET_CODE (inner_dest) == SUBREG
2075 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2076 inner_dest = XEXP (inner_dest, 0);
2078 /* Check for the case where I3 modifies its output, as discussed
2079 above. We don't want to prevent pseudos from being combined
2080 into the address of a MEM, so only prevent the combination if
2081 i1 or i2 set the same MEM. */
2082 if ((inner_dest != dest &&
2083 (!MEM_P (inner_dest)
2084 || rtx_equal_p (i2dest, inner_dest)
2085 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2086 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2087 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2088 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2089 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2091 /* This is the same test done in can_combine_p except we can't test
2092 all_adjacent; we don't have to, since this instruction will stay
2093 in place, thus we are not considering increasing the lifetime of
2096 Also, if this insn sets a function argument, combining it with
2097 something that might need a spill could clobber a previous
2098 function argument; the all_adjacent test in can_combine_p also
2099 checks this; here, we do a more specific test for this case. */
2101 || (REG_P (inner_dest)
2102 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2103 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2104 GET_MODE (inner_dest))))
2105 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2106 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2109 /* If DEST is used in I3, it is being killed in this insn, so
2110 record that for later. We have to consider paradoxical
2111 subregs here, since they kill the whole register, but we
2112 ignore partial subregs, STRICT_LOW_PART, etc.
2113 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114 STACK_POINTER_REGNUM, since these are always considered to be
2115 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2117 if (GET_CODE (subdest) == SUBREG
2118 && (GET_MODE_SIZE (GET_MODE (subdest))
2119 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2120 subdest = SUBREG_REG (subdest);
2123 && reg_referenced_p (subdest, PATTERN (i3))
2124 && REGNO (subdest) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129 && (REGNO (subdest) != ARG_POINTER_REGNUM
2130 || ! fixed_regs [REGNO (subdest)])
2132 && REGNO (subdest) != STACK_POINTER_REGNUM)
2134 if (*pi3dest_killed)
2137 *pi3dest_killed = subdest;
2141 else if (GET_CODE (x) == PARALLEL)
2145 for (i = 0; i < XVECLEN (x, 0); i++)
2146 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2147 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155 and division. We don't count multiplications by powers of two here. */
2158 contains_muldiv (rtx x)
2160 switch (GET_CODE (x))
2162 case MOD: case DIV: case UMOD: case UDIV:
2166 return ! (CONST_INT_P (XEXP (x, 1))
2167 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2170 return contains_muldiv (XEXP (x, 0))
2171 || contains_muldiv (XEXP (x, 1));
2174 return contains_muldiv (XEXP (x, 0));
2180 /* Determine whether INSN can be used in a combination. Return nonzero if
2181 not. This is used in try_combine to detect early some cases where we
2182 can't perform combinations. */
2185 cant_combine_insn_p (rtx insn)
2190 /* If this isn't really an insn, we can't do anything.
2191 This can occur when flow deletes an insn that it has merged into an
2192 auto-increment address. */
2193 if (! INSN_P (insn))
2196 /* Never combine loads and stores involving hard regs that are likely
2197 to be spilled. The register allocator can usually handle such
2198 reg-reg moves by tying. If we allow the combiner to make
2199 substitutions of likely-spilled regs, reload might die.
2200 As an exception, we allow combinations involving fixed regs; these are
2201 not available to the register allocator so there's no risk involved. */
2203 set = single_set (insn);
2206 src = SET_SRC (set);
2207 dest = SET_DEST (set);
2208 if (GET_CODE (src) == SUBREG)
2209 src = SUBREG_REG (src);
2210 if (GET_CODE (dest) == SUBREG)
2211 dest = SUBREG_REG (dest);
2212 if (REG_P (src) && REG_P (dest)
2213 && ((HARD_REGISTER_P (src)
2214 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2215 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2216 || (HARD_REGISTER_P (dest)
2217 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2218 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2224 struct likely_spilled_retval_info
2226 unsigned regno, nregs;
2230 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2231 hard registers that are known to be written to / clobbered in full. */
2233 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2235 struct likely_spilled_retval_info *const info =
2236 (struct likely_spilled_retval_info *) data;
2237 unsigned regno, nregs;
2240 if (!REG_P (XEXP (set, 0)))
2243 if (regno >= info->regno + info->nregs)
2245 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2246 if (regno + nregs <= info->regno)
2248 new_mask = (2U << (nregs - 1)) - 1;
2249 if (regno < info->regno)
2250 new_mask >>= info->regno - regno;
2252 new_mask <<= regno - info->regno;
2253 info->mask &= ~new_mask;
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257 it is likely spilled. This can happen when more than one insn is needed
2258 to copy the return value, e.g. when we consider to combine into the
2259 second copy insn for a complex value. */
2262 likely_spilled_retval_p (rtx insn)
2264 rtx use = BB_END (this_basic_block);
2266 unsigned regno, nregs;
2267 /* We assume here that no machine mode needs more than
2268 32 hard registers when the value overlaps with a register
2269 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2271 struct likely_spilled_retval_info info;
2273 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2275 reg = XEXP (PATTERN (use), 0);
2276 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2278 regno = REGNO (reg);
2279 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2282 mask = (2U << (nregs - 1)) - 1;
2284 /* Disregard parts of the return value that are set later. */
2288 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2290 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2293 /* Check if any of the (probably) live return value registers is
2298 if ((mask & 1 << nregs)
2299 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2305 /* Adjust INSN after we made a change to its destination.
2307 Changing the destination can invalidate notes that say something about
2308 the results of the insn and a LOG_LINK pointing to the insn. */
2311 adjust_for_new_dest (rtx insn)
2313 /* For notes, be conservative and simply remove them. */
2314 remove_reg_equal_equiv_notes (insn);
2316 /* The new insn will have a destination that was previously the destination
2317 of an insn just above it. Call distribute_links to make a LOG_LINK from
2318 the next use of that destination. */
2319 distribute_links (alloc_insn_link (insn, NULL));
2321 df_insn_rescan (insn);
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325 ADDED_SETS is nonzero if the original set is still required. */
2327 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2335 /* Allow hard registers if the new mode is legal, and occupies no more
2336 registers than the old mode. */
2337 if (regno < FIRST_PSEUDO_REGISTER)
2338 return (HARD_REGNO_MODE_OK (regno, mode)
2339 && (hard_regno_nregs[regno][GET_MODE (x)]
2340 >= hard_regno_nregs[regno][mode]));
2342 /* Or a pseudo that is only used once. */
2343 return (REG_N_SETS (regno) == 1 && !added_sets
2344 && !REG_USERVAR_P (x));
2348 /* Check whether X, the destination of a set, refers to part of
2349 the register specified by REG. */
2352 reg_subword_p (rtx x, rtx reg)
2354 /* Check that reg is an integer mode register. */
2355 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2358 if (GET_CODE (x) == STRICT_LOW_PART
2359 || GET_CODE (x) == ZERO_EXTRACT)
2362 return GET_CODE (x) == SUBREG
2363 && SUBREG_REG (x) == reg
2364 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368 Note that the INSN should be deleted *after* removing dead edges, so
2369 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370 but not for a (set (pc) (label_ref FOO)). */
2373 update_cfg_for_uncondjump (rtx insn)
2375 basic_block bb = BLOCK_FOR_INSN (insn);
2376 gcc_assert (BB_END (bb) == insn);
2378 purge_dead_edges (bb);
2381 if (EDGE_COUNT (bb->succs) == 1)
2385 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2387 /* Remove barriers from the footer if there are any. */
2388 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2389 if (BARRIER_P (insn))
2391 if (PREV_INSN (insn))
2392 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2394 BB_FOOTER (bb) = NEXT_INSN (insn);
2395 if (NEXT_INSN (insn))
2396 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2398 else if (LABEL_P (insn))
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404 Here I0, I1 and I2 appear earlier than I3.
2405 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2408 If we are combining more than two insns and the resulting insn is not
2409 recognized, try splitting it into two insns. If that happens, I2 and I3
2410 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411 Otherwise, I0, I1 and I2 are pseudo-deleted.
2413 Return 0 if the combination does not work. Then nothing is changed.
2414 If we did the combination, return the insn at which combine should
2417 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418 new direct jump instruction.
2420 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421 been I3 passed to an earlier try_combine within the same basic
2425 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2426 rtx last_combined_insn)
2428 /* New patterns for I3 and I2, respectively. */
2429 rtx newpat, newi2pat = 0;
2430 rtvec newpat_vec_with_clobbers = 0;
2431 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2432 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2434 int added_sets_0, added_sets_1, added_sets_2;
2435 /* Total number of SETs to put into I3. */
2437 /* Nonzero if I2's or I1's body now appears in I3. */
2438 int i2_is_used = 0, i1_is_used = 0;
2439 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2440 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2441 /* Contains I3 if the destination of I3 is used in its source, which means
2442 that the old life of I3 is being killed. If that usage is placed into
2443 I2 and not in I3, a REG_DEAD note must be made. */
2444 rtx i3dest_killed = 0;
2445 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2446 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2447 /* Copy of SET_SRC of I1 and I0, if needed. */
2448 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2449 /* Set if I2DEST was reused as a scratch register. */
2450 bool i2scratch = false;
2451 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2452 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2453 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2454 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2455 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2456 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2457 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2458 /* Notes that must be added to REG_NOTES in I3 and I2. */
2459 rtx new_i3_notes, new_i2_notes;
2460 /* Notes that we substituted I3 into I2 instead of the normal case. */
2461 int i3_subst_into_i2 = 0;
2462 /* Notes that I1, I2 or I3 is a MULT operation. */
2465 int changed_i3_dest = 0;
2469 struct insn_link *link;
2471 rtx new_other_notes;
2474 /* Only try four-insn combinations when there's high likelihood of
2475 success. Look for simple insns, such as loads of constants or
2476 binary operations involving a constant. */
2483 if (!flag_expensive_optimizations)
2486 for (i = 0; i < 4; i++)
2488 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2489 rtx set = single_set (insn);
2493 src = SET_SRC (set);
2494 if (CONSTANT_P (src))
2499 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2501 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2502 || GET_CODE (src) == LSHIFTRT)
2505 if (ngood < 2 && nshift < 2)
2509 /* Exit early if one of the insns involved can't be used for
2511 if (cant_combine_insn_p (i3)
2512 || cant_combine_insn_p (i2)
2513 || (i1 && cant_combine_insn_p (i1))
2514 || (i0 && cant_combine_insn_p (i0))
2515 || likely_spilled_retval_p (i3))
2519 undobuf.other_insn = 0;
2521 /* Reset the hard register usage information. */
2522 CLEAR_HARD_REG_SET (newpat_used_regs);
2524 if (dump_file && (dump_flags & TDF_DETAILS))
2527 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2528 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2530 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2531 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2533 fprintf (dump_file, "\nTrying %d -> %d:\n",
2534 INSN_UID (i2), INSN_UID (i3));
2537 /* If multiple insns feed into one of I2 or I3, they can be in any
2538 order. To simplify the code below, reorder them in sequence. */
2539 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2540 temp = i2, i2 = i0, i0 = temp;
2541 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2542 temp = i1, i1 = i0, i0 = temp;
2543 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2544 temp = i1, i1 = i2, i2 = temp;
2546 added_links_insn = 0;
2548 /* First check for one important special case that the code below will
2549 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2550 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2551 we may be able to replace that destination with the destination of I3.
2552 This occurs in the common code where we compute both a quotient and
2553 remainder into a structure, in which case we want to do the computation
2554 directly into the structure to avoid register-register copies.
2556 Note that this case handles both multiple sets in I2 and also cases
2557 where I2 has a number of CLOBBERs inside the PARALLEL.
2559 We make very conservative checks below and only try to handle the
2560 most common cases of this. For example, we only handle the case
2561 where I2 and I3 are adjacent to avoid making difficult register
2564 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2565 && REG_P (SET_SRC (PATTERN (i3)))
2566 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2567 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2568 && GET_CODE (PATTERN (i2)) == PARALLEL
2569 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2570 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571 below would need to check what is inside (and reg_overlap_mentioned_p
2572 doesn't support those codes anyway). Don't allow those destinations;
2573 the resulting insn isn't likely to be recognized anyway. */
2574 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2575 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2576 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2577 SET_DEST (PATTERN (i3)))
2578 && next_active_insn (i2) == i3)
2580 rtx p2 = PATTERN (i2);
2582 /* Make sure that the destination of I3,
2583 which we are going to substitute into one output of I2,
2584 is not used within another output of I2. We must avoid making this:
2585 (parallel [(set (mem (reg 69)) ...)
2586 (set (reg 69) ...)])
2587 which is not well-defined as to order of actions.
2588 (Besides, reload can't handle output reloads for this.)
2590 The problem can also happen if the dest of I3 is a memory ref,
2591 if another dest in I2 is an indirect memory ref. */
2592 for (i = 0; i < XVECLEN (p2, 0); i++)
2593 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2594 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2595 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2596 SET_DEST (XVECEXP (p2, 0, i))))
2599 if (i == XVECLEN (p2, 0))
2600 for (i = 0; i < XVECLEN (p2, 0); i++)
2601 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2602 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2607 subst_low_luid = DF_INSN_LUID (i2);
2609 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2610 i2src = SET_SRC (XVECEXP (p2, 0, i));
2611 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2612 i2dest_killed = dead_or_set_p (i2, i2dest);
2614 /* Replace the dest in I2 with our dest and make the resulting
2615 insn the new pattern for I3. Then skip to where we validate
2616 the pattern. Everything was set up above. */
2617 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2619 i3_subst_into_i2 = 1;
2620 goto validate_replacement;
2624 /* If I2 is setting a pseudo to a constant and I3 is setting some
2625 sub-part of it to another constant, merge them by making a new
2628 && (temp = single_set (i2)) != 0
2629 && CONST_SCALAR_INT_P (SET_SRC (temp))
2630 && GET_CODE (PATTERN (i3)) == SET
2631 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2632 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2634 rtx dest = SET_DEST (PATTERN (i3));
2638 /* There are not explicit tests to make sure that this is not a
2639 float, but there is code here that would not be correct if it
2641 gcc_assert (GET_MODE_CLASS (GET_MODE (SET_SRC (temp))) != MODE_FLOAT);
2643 if (GET_CODE (dest) == ZERO_EXTRACT)
2645 if (CONST_INT_P (XEXP (dest, 1))
2646 && CONST_INT_P (XEXP (dest, 2)))
2648 width = INTVAL (XEXP (dest, 1));
2649 offset = INTVAL (XEXP (dest, 2));
2650 dest = XEXP (dest, 0);
2651 if (BITS_BIG_ENDIAN)
2652 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2657 if (GET_CODE (dest) == STRICT_LOW_PART)
2658 dest = XEXP (dest, 0);
2659 width = GET_MODE_PRECISION (GET_MODE (dest));
2665 /* If this is the low part, we're done. */
2666 if (subreg_lowpart_p (dest))
2668 /* Handle the case where inner is twice the size of outer. */
2669 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2670 == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2671 offset += GET_MODE_PRECISION (GET_MODE (dest));
2672 /* Otherwise give up for now. */
2678 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2679 <= HOST_BITS_PER_DOUBLE_INT))
2682 rtx inner = SET_SRC (PATTERN (i3));
2683 rtx outer = SET_SRC (temp);
2685 o = rtx_to_double_int (outer);
2686 i = rtx_to_double_int (inner);
2688 m = double_int::mask (width);
2690 m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2691 i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2692 o = o.and_not (m) | i;
2696 subst_low_luid = DF_INSN_LUID (i2);
2697 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2698 i2dest = SET_DEST (temp);
2699 i2dest_killed = dead_or_set_p (i2, i2dest);
2701 /* Replace the source in I2 with the new constant and make the
2702 resulting insn the new pattern for I3. Then skip to where we
2703 validate the pattern. Everything was set up above. */
2704 SUBST (SET_SRC (temp),
2705 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2707 newpat = PATTERN (i2);
2709 /* The dest of I3 has been replaced with the dest of I2. */
2710 changed_i3_dest = 1;
2711 goto validate_replacement;
2716 /* If we have no I1 and I2 looks like:
2717 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2719 make up a dummy I1 that is
2722 (set (reg:CC X) (compare:CC Y (const_int 0)))
2724 (We can ignore any trailing CLOBBERs.)
2726 This undoes a previous combination and allows us to match a branch-and-
2729 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2730 && XVECLEN (PATTERN (i2), 0) >= 2
2731 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2732 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2734 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2735 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2736 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2737 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2738 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2739 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2741 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2742 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2747 /* We make I1 with the same INSN_UID as I2. This gives it
2748 the same DF_INSN_LUID for value tracking. Our fake I1 will
2749 never appear in the insn stream so giving it the same INSN_UID
2750 as I2 will not cause a problem. */
2752 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2753 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2754 INSN_LOCATION (i2), -1, NULL_RTX);
2756 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2757 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2758 SET_DEST (PATTERN (i1)));
2759 SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2764 /* Verify that I2 and I1 are valid for combining. */
2765 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2766 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2768 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2775 /* Record whether I2DEST is used in I2SRC and similarly for the other
2776 cases. Knowing this will help in register status updating below. */
2777 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2778 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2779 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2780 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2781 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2782 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2783 i2dest_killed = dead_or_set_p (i2, i2dest);
2784 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2785 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2787 /* For the earlier insns, determine which of the subsequent ones they
2789 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2790 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2791 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2792 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2793 && reg_overlap_mentioned_p (i0dest, i2src))));
2795 /* Ensure that I3's pattern can be the destination of combines. */
2796 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2797 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2798 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2799 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2806 /* See if any of the insns is a MULT operation. Unless one is, we will
2807 reject a combination that is, since it must be slower. Be conservative
2809 if (GET_CODE (i2src) == MULT
2810 || (i1 != 0 && GET_CODE (i1src) == MULT)
2811 || (i0 != 0 && GET_CODE (i0src) == MULT)
2812 || (GET_CODE (PATTERN (i3)) == SET
2813 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2816 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2817 We used to do this EXCEPT in one case: I3 has a post-inc in an
2818 output operand. However, that exception can give rise to insns like
2820 which is a famous insn on the PDP-11 where the value of r3 used as the
2821 source was model-dependent. Avoid this sort of thing. */
2824 if (!(GET_CODE (PATTERN (i3)) == SET
2825 && REG_P (SET_SRC (PATTERN (i3)))
2826 && MEM_P (SET_DEST (PATTERN (i3)))
2827 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2828 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2829 /* It's not the exception. */
2834 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2835 if (REG_NOTE_KIND (link) == REG_INC
2836 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2838 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2846 /* See if the SETs in I1 or I2 need to be kept around in the merged
2847 instruction: whenever the value set there is still needed past I3.
2848 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2850 For the SET in I1, we have two cases: If I1 and I2 independently
2851 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2852 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2853 in I1 needs to be kept around unless I1DEST dies or is set in either
2854 I2 or I3. The same consideration applies to I0. */
2856 added_sets_2 = !dead_or_set_p (i3, i2dest);
2859 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2860 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2865 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2866 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2867 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2871 /* We are about to copy insns for the case where they need to be kept
2872 around. Check that they can be copied in the merged instruction. */
2874 if (targetm.cannot_copy_insn_p
2875 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2876 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2877 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2883 /* If the set in I2 needs to be kept around, we must make a copy of
2884 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2885 PATTERN (I2), we are only substituting for the original I1DEST, not into
2886 an already-substituted copy. This also prevents making self-referential
2887 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2892 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2893 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2895 i2pat = copy_rtx (PATTERN (i2));
2900 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2901 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2903 i1pat = copy_rtx (PATTERN (i1));
2908 if (GET_CODE (PATTERN (i0)) == PARALLEL)
2909 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2911 i0pat = copy_rtx (PATTERN (i0));
2916 /* Substitute in the latest insn for the regs set by the earlier ones. */
2918 maxreg = max_reg_num ();
2923 /* Many machines that don't use CC0 have insns that can both perform an
2924 arithmetic operation and set the condition code. These operations will
2925 be represented as a PARALLEL with the first element of the vector
2926 being a COMPARE of an arithmetic operation with the constant zero.
2927 The second element of the vector will set some pseudo to the result
2928 of the same arithmetic operation. If we simplify the COMPARE, we won't
2929 match such a pattern and so will generate an extra insn. Here we test
2930 for this case, where both the comparison and the operation result are
2931 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2932 I2SRC. Later we will make the PARALLEL that contains I2. */
2934 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2935 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2936 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2937 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2940 rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2941 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2942 enum machine_mode compare_mode, orig_compare_mode;
2943 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2945 newpat = PATTERN (i3);
2946 newpat_dest = SET_DEST (newpat);
2947 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2949 if (undobuf.other_insn == 0
2950 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2953 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2954 compare_code = simplify_compare_const (compare_code,
2956 target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2959 /* Do the rest only if op1 is const0_rtx, which may be the
2960 result of simplification. */
2961 if (op1 == const0_rtx)
2963 /* If a single use of the CC is found, prepare to modify it
2964 when SELECT_CC_MODE returns a new CC-class mode, or when
2965 the above simplify_compare_const() returned a new comparison
2966 operator. undobuf.other_insn is assigned the CC use insn
2967 when modifying it. */
2970 #ifdef SELECT_CC_MODE
2971 enum machine_mode new_mode
2972 = SELECT_CC_MODE (compare_code, op0, op1);
2973 if (new_mode != orig_compare_mode
2974 && can_change_dest_mode (SET_DEST (newpat),
2975 added_sets_2, new_mode))
2977 unsigned int regno = REGNO (newpat_dest);
2978 compare_mode = new_mode;
2979 if (regno < FIRST_PSEUDO_REGISTER)
2980 newpat_dest = gen_rtx_REG (compare_mode, regno);
2983 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2984 newpat_dest = regno_reg_rtx[regno];
2988 /* Cases for modifying the CC-using comparison. */
2989 if (compare_code != orig_compare_code
2990 /* ??? Do we need to verify the zero rtx? */
2991 && XEXP (*cc_use_loc, 1) == const0_rtx)
2993 /* Replace cc_use_loc with entire new RTX. */
2995 gen_rtx_fmt_ee (compare_code, compare_mode,
2996 newpat_dest, const0_rtx));
2997 undobuf.other_insn = cc_use_insn;
2999 else if (compare_mode != orig_compare_mode)
3001 /* Just replace the CC reg with a new mode. */
3002 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3003 undobuf.other_insn = cc_use_insn;
3007 /* Now we modify the current newpat:
3008 First, SET_DEST(newpat) is updated if the CC mode has been
3009 altered. For targets without SELECT_CC_MODE, this should be
3011 if (compare_mode != orig_compare_mode)
3012 SUBST (SET_DEST (newpat), newpat_dest);
3013 /* This is always done to propagate i2src into newpat. */
3014 SUBST (SET_SRC (newpat),
3015 gen_rtx_COMPARE (compare_mode, op0, op1));
3016 /* Create new version of i2pat if needed; the below PARALLEL
3017 creation needs this to work correctly. */
3018 if (! rtx_equal_p (i2src, op0))
3019 i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3025 if (i2_is_used == 0)
3027 /* It is possible that the source of I2 or I1 may be performing
3028 an unneeded operation, such as a ZERO_EXTEND of something
3029 that is known to have the high part zero. Handle that case
3030 by letting subst look at the inner insns.
3032 Another way to do this would be to have a function that tries
3033 to simplify a single insn instead of merging two or more
3034 insns. We don't do this because of the potential of infinite
3035 loops and because of the potential extra memory required.
3036 However, doing it the way we are is a bit of a kludge and
3037 doesn't catch all cases.
3039 But only do this if -fexpensive-optimizations since it slows
3040 things down and doesn't usually win.
3042 This is not done in the COMPARE case above because the
3043 unmodified I2PAT is used in the PARALLEL and so a pattern
3044 with a modified I2SRC would not match. */
3046 if (flag_expensive_optimizations)
3048 /* Pass pc_rtx so no substitutions are done, just
3052 subst_low_luid = DF_INSN_LUID (i1);
3053 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3056 subst_low_luid = DF_INSN_LUID (i2);
3057 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3060 n_occurrences = 0; /* `subst' counts here */
3061 subst_low_luid = DF_INSN_LUID (i2);
3063 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3064 copy of I2SRC each time we substitute it, in order to avoid creating
3065 self-referential RTL when we will be substituting I1SRC for I1DEST
3066 later. Likewise if I0 feeds into I2, either directly or indirectly
3067 through I1, and I0DEST is in I0SRC. */
3068 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3069 (i1_feeds_i2_n && i1dest_in_i1src)
3070 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3071 && i0dest_in_i0src));
3074 /* Record whether I2's body now appears within I3's body. */
3075 i2_is_used = n_occurrences;
3078 /* If we already got a failure, don't try to do more. Otherwise, try to
3079 substitute I1 if we have it. */
3081 if (i1 && GET_CODE (newpat) != CLOBBER)
3083 /* Check that an autoincrement side-effect on I1 has not been lost.
3084 This happens if I1DEST is mentioned in I2 and dies there, and
3085 has disappeared from the new pattern. */
3086 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3088 && dead_or_set_p (i2, i1dest)
3089 && !reg_overlap_mentioned_p (i1dest, newpat))
3090 /* Before we can do this substitution, we must redo the test done
3091 above (see detailed comments there) that ensures I1DEST isn't
3092 mentioned in any SETs in NEWPAT that are field assignments. */
3093 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3101 subst_low_luid = DF_INSN_LUID (i1);
3103 /* If the following substitution will modify I1SRC, make a copy of it
3104 for the case where it is substituted for I1DEST in I2PAT later. */
3105 if (added_sets_2 && i1_feeds_i2_n)
3106 i1src_copy = copy_rtx (i1src);
3108 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3109 copy of I1SRC each time we substitute it, in order to avoid creating
3110 self-referential RTL when we will be substituting I0SRC for I0DEST
3112 newpat = subst (newpat, i1dest, i1src, 0, 0,
3113 i0_feeds_i1_n && i0dest_in_i0src);
3116 /* Record whether I1's body now appears within I3's body. */
3117 i1_is_used = n_occurrences;
3120 /* Likewise for I0 if we have it. */
3122 if (i0 && GET_CODE (newpat) != CLOBBER)
3124 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3125 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3126 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3127 && !reg_overlap_mentioned_p (i0dest, newpat))
3128 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3135 /* If the following substitution will modify I0SRC, make a copy of it
3136 for the case where it is substituted for I0DEST in I1PAT later. */
3137 if (added_sets_1 && i0_feeds_i1_n)
3138 i0src_copy = copy_rtx (i0src);
3139 /* And a copy for I0DEST in I2PAT substitution. */
3140 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3141 || (i0_feeds_i2_n)))
3142 i0src_copy2 = copy_rtx (i0src);
3145 subst_low_luid = DF_INSN_LUID (i0);
3146 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3150 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3151 to count all the ways that I2SRC and I1SRC can be used. */
3152 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3153 && i2_is_used + added_sets_2 > 1)
3154 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3155 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3157 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3158 && (n_occurrences + added_sets_0
3159 + (added_sets_1 && i0_feeds_i1_n)
3160 + (added_sets_2 && i0_feeds_i2_n)
3162 /* Fail if we tried to make a new register. */
3163 || max_reg_num () != maxreg
3164 /* Fail if we couldn't do something and have a CLOBBER. */
3165 || GET_CODE (newpat) == CLOBBER
3166 /* Fail if this new pattern is a MULT and we didn't have one before
3167 at the outer level. */
3168 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3175 /* If the actions of the earlier insns must be kept
3176 in addition to substituting them into the latest one,
3177 we must make a new PARALLEL for the latest insn
3178 to hold additional the SETs. */
3180 if (added_sets_0 || added_sets_1 || added_sets_2)
3182 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3185 if (GET_CODE (newpat) == PARALLEL)
3187 rtvec old = XVEC (newpat, 0);
3188 total_sets = XVECLEN (newpat, 0) + extra_sets;
3189 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3190 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3191 sizeof (old->elem[0]) * old->num_elem);
3196 total_sets = 1 + extra_sets;
3197 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3198 XVECEXP (newpat, 0, 0) = old;
3202 XVECEXP (newpat, 0, --total_sets) = i0pat;
3208 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3210 XVECEXP (newpat, 0, --total_sets) = t;
3216 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3217 i0_feeds_i1_n && i0dest_in_i0src);
3218 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3219 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3221 XVECEXP (newpat, 0, --total_sets) = t;
3225 validate_replacement:
3227 /* Note which hard regs this insn has as inputs. */
3228 mark_used_regs_combine (newpat);
3230 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3231 consider splitting this pattern, we might need these clobbers. */
3232 if (i1 && GET_CODE (newpat) == PARALLEL
3233 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3235 int len = XVECLEN (newpat, 0);
3237 newpat_vec_with_clobbers = rtvec_alloc (len);
3238 for (i = 0; i < len; i++)
3239 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3242 /* Is the result of combination a valid instruction? */
3243 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3245 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3246 the second SET's destination is a register that is unused and isn't
3247 marked as an instruction that might trap in an EH region. In that case,
3248 we just need the first SET. This can occur when simplifying a divmod
3249 insn. We *must* test for this case here because the code below that
3250 splits two independent SETs doesn't handle this case correctly when it
3251 updates the register status.
3253 It's pointless doing this if we originally had two sets, one from
3254 i3, and one from i2. Combining then splitting the parallel results
3255 in the original i2 again plus an invalid insn (which we delete).
3256 The net effect is only to move instructions around, which makes
3257 debug info less accurate.
3259 Also check the case where the first SET's destination is unused.
3260 That would not cause incorrect code, but does cause an unneeded
3263 if (insn_code_number < 0
3264 && !(added_sets_2 && i1 == 0)
3265 && GET_CODE (newpat) == PARALLEL
3266 && XVECLEN (newpat, 0) == 2
3267 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3268 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3269 && asm_noperands (newpat) < 0)
3271 rtx set0 = XVECEXP (newpat, 0, 0);
3272 rtx set1 = XVECEXP (newpat, 0, 1);
3274 if (((REG_P (SET_DEST (set1))
3275 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3276 || (GET_CODE (SET_DEST (set1)) == SUBREG
3277 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3278 && insn_nothrow_p (i3)
3279 && !side_effects_p (SET_SRC (set1)))
3282 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3285 else if (((REG_P (SET_DEST (set0))
3286 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3287 || (GET_CODE (SET_DEST (set0)) == SUBREG
3288 && find_reg_note (i3, REG_UNUSED,
3289 SUBREG_REG (SET_DEST (set0)))))
3290 && insn_nothrow_p (i3)
3291 && !side_effects_p (SET_SRC (set0)))
3294 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3296 if (insn_code_number >= 0)
3297 changed_i3_dest = 1;
3301 /* If we were combining three insns and the result is a simple SET
3302 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3303 insns. There are two ways to do this. It can be split using a
3304 machine-specific method (like when you have an addition of a large
3305 constant) or by combine in the function find_split_point. */
3307 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3308 && asm_noperands (newpat) < 0)
3310 rtx parallel, m_split, *split;
3312 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3313 use I2DEST as a scratch register will help. In the latter case,
3314 convert I2DEST to the mode of the source of NEWPAT if we can. */
3316 m_split = combine_split_insns (newpat, i3);
3318 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3319 inputs of NEWPAT. */
3321 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3322 possible to try that as a scratch reg. This would require adding
3323 more code to make it work though. */
3325 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3327 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3329 /* First try to split using the original register as a
3330 scratch register. */
3331 parallel = gen_rtx_PARALLEL (VOIDmode,
3332 gen_rtvec (2, newpat,
3333 gen_rtx_CLOBBER (VOIDmode,
3335 m_split = combine_split_insns (parallel, i3);
3337 /* If that didn't work, try changing the mode of I2DEST if
3340 && new_mode != GET_MODE (i2dest)
3341 && new_mode != VOIDmode
3342 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3344 enum machine_mode old_mode = GET_MODE (i2dest);
3347 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3348 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3351 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3352 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3355 parallel = (gen_rtx_PARALLEL
3357 gen_rtvec (2, newpat,
3358 gen_rtx_CLOBBER (VOIDmode,
3360 m_split = combine_split_insns (parallel, i3);
3363 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3367 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3368 buf = undobuf.undos;
3369 undobuf.undos = buf->next;
3370 buf->next = undobuf.frees;
3371 undobuf.frees = buf;
3375 i2scratch = m_split != 0;
3378 /* If recog_for_combine has discarded clobbers, try to use them
3379 again for the split. */
3380 if (m_split == 0 && newpat_vec_with_clobbers)
3382 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3383 m_split = combine_split_insns (parallel, i3);
3386 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3388 m_split = PATTERN (m_split);
3389 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3390 if (insn_code_number >= 0)
3393 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3394 && (next_nonnote_nondebug_insn (i2) == i3
3395 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3398 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3399 newi2pat = PATTERN (m_split);
3401 i3set = single_set (NEXT_INSN (m_split));
3402 i2set = single_set (m_split);
3404 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3406 /* If I2 or I3 has multiple SETs, we won't know how to track
3407 register status, so don't use these insns. If I2's destination
3408 is used between I2 and I3, we also can't use these insns. */
3410 if (i2_code_number >= 0 && i2set && i3set
3411 && (next_nonnote_nondebug_insn (i2) == i3
3412 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3413 insn_code_number = recog_for_combine (&newi3pat, i3,
3415 if (insn_code_number >= 0)
3418 /* It is possible that both insns now set the destination of I3.
3419 If so, we must show an extra use of it. */
3421 if (insn_code_number >= 0)
3423 rtx new_i3_dest = SET_DEST (i3set);
3424 rtx new_i2_dest = SET_DEST (i2set);
3426 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3427 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3428 || GET_CODE (new_i3_dest) == SUBREG)
3429 new_i3_dest = XEXP (new_i3_dest, 0);
3431 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3432 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3433 || GET_CODE (new_i2_dest) == SUBREG)
3434 new_i2_dest = XEXP (new_i2_dest, 0);
3436 if (REG_P (new_i3_dest)
3437 && REG_P (new_i2_dest)
3438 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3439 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3443 /* If we can split it and use I2DEST, go ahead and see if that
3444 helps things be recognized. Verify that none of the registers
3445 are set between I2 and I3. */
3446 if (insn_code_number < 0
3447 && (split = find_split_point (&newpat, i3, false)) != 0
3451 /* We need I2DEST in the proper mode. If it is a hard register
3452 or the only use of a pseudo, we can change its mode.
3453 Make sure we don't change a hard register to have a mode that
3454 isn't valid for it, or change the number of registers. */
3455 && (GET_MODE (*split) == GET_MODE (i2dest)
3456 || GET_MODE (*split) == VOIDmode
3457 || can_change_dest_mode (i2dest, added_sets_2,
3459 && (next_nonnote_nondebug_insn (i2) == i3
3460 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3461 /* We can't overwrite I2DEST if its value is still used by
3463 && ! reg_referenced_p (i2dest, newpat))
3465 rtx newdest = i2dest;
3466 enum rtx_code split_code = GET_CODE (*split);
3467 enum machine_mode split_mode = GET_MODE (*split);
3468 bool subst_done = false;
3469 newi2pat = NULL_RTX;
3473 /* *SPLIT may be part of I2SRC, so make sure we have the
3474 original expression around for later debug processing.
3475 We should not need I2SRC any more in other cases. */
3476 if (MAY_HAVE_DEBUG_INSNS)
3477 i2src = copy_rtx (i2src);
3481 /* Get NEWDEST as a register in the proper mode. We have already
3482 validated that we can do this. */
3483 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3485 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3486 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3489 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3490 newdest = regno_reg_rtx[REGNO (i2dest)];
3494 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3495 an ASHIFT. This can occur if it was inside a PLUS and hence
3496 appeared to be a memory address. This is a kludge. */
3497 if (split_code == MULT
3498 && CONST_INT_P (XEXP (*split, 1))
3499 && INTVAL (XEXP (*split, 1)) > 0
3500 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3502 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3503 XEXP (*split, 0), GEN_INT (i)));
3504 /* Update split_code because we may not have a multiply
3506 split_code = GET_CODE (*split);
3509 #ifdef INSN_SCHEDULING
3510 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3511 be written as a ZERO_EXTEND. */
3512 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3514 #ifdef LOAD_EXTEND_OP
3515 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3516 what it really is. */
3517 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3519 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3520 SUBREG_REG (*split)));
3523 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3524 SUBREG_REG (*split)));
3528 /* Attempt to split binary operators using arithmetic identities. */
3529 if (BINARY_P (SET_SRC (newpat))
3530 && split_mode == GET_MODE (SET_SRC (newpat))
3531 && ! side_effects_p (SET_SRC (newpat)))
3533 rtx setsrc = SET_SRC (newpat);
3534 enum machine_mode mode = GET_MODE (setsrc);
3535 enum rtx_code code = GET_CODE (setsrc);
3536 rtx src_op0 = XEXP (setsrc, 0);
3537 rtx src_op1 = XEXP (setsrc, 1);
3539 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3540 if (rtx_equal_p (src_op0, src_op1))
3542 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3543 SUBST (XEXP (setsrc, 0), newdest);
3544 SUBST (XEXP (setsrc, 1), newdest);
3547 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3548 else if ((code == PLUS || code == MULT)
3549 && GET_CODE (src_op0) == code
3550 && GET_CODE (XEXP (src_op0, 0)) == code
3551 && (INTEGRAL_MODE_P (mode)
3552 || (FLOAT_MODE_P (mode)
3553 && flag_unsafe_math_optimizations)))
3555 rtx p = XEXP (XEXP (src_op0, 0), 0);
3556 rtx q = XEXP (XEXP (src_op0, 0), 1);
3557 rtx r = XEXP (src_op0, 1);
3560 /* Split both "((X op Y) op X) op Y" and
3561 "((X op Y) op Y) op X" as "T op T" where T is
3563 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3564 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3566 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3568 SUBST (XEXP (setsrc, 0), newdest);
3569 SUBST (XEXP (setsrc, 1), newdest);
3572 /* Split "((X op X) op Y) op Y)" as "T op T" where
3574 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3576 rtx tmp = simplify_gen_binary (code, mode, p, r);
3577 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3578 SUBST (XEXP (setsrc, 0), newdest);
3579 SUBST (XEXP (setsrc, 1), newdest);
3587 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3588 SUBST (*split, newdest);
3591 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3593 /* recog_for_combine might have added CLOBBERs to newi2pat.
3594 Make sure NEWPAT does not depend on the clobbered regs. */
3595 if (GET_CODE (newi2pat) == PARALLEL)
3596 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3597 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3599 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3600 if (reg_overlap_mentioned_p (reg, newpat))
3607 /* If the split point was a MULT and we didn't have one before,
3608 don't use one now. */
3609 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3610 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3614 /* Check for a case where we loaded from memory in a narrow mode and
3615 then sign extended it, but we need both registers. In that case,
3616 we have a PARALLEL with both loads from the same memory location.
3617 We can split this into a load from memory followed by a register-register
3618 copy. This saves at least one insn, more if register allocation can
3621 We cannot do this if the destination of the first assignment is a
3622 condition code register or cc0. We eliminate this case by making sure
3623 the SET_DEST and SET_SRC have the same mode.
3625 We cannot do this if the destination of the second assignment is
3626 a register that we have already assumed is zero-extended. Similarly
3627 for a SUBREG of such a register. */
3629 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3630 && GET_CODE (newpat) == PARALLEL
3631 && XVECLEN (newpat, 0) == 2
3632 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3633 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3634 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3635 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3636 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3637 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3638 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3639 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3641 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3642 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3643 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3645 && reg_stat[REGNO (temp)].nonzero_bits != 0
3646 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3647 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3648 && (reg_stat[REGNO (temp)].nonzero_bits
3649 != GET_MODE_MASK (word_mode))))
3650 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3651 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3653 && reg_stat[REGNO (temp)].nonzero_bits != 0
3654 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3655 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3656 && (reg_stat[REGNO (temp)].nonzero_bits
3657 != GET_MODE_MASK (word_mode)))))
3658 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3659 SET_SRC (XVECEXP (newpat, 0, 1)))
3660 && ! find_reg_note (i3, REG_UNUSED,
3661 SET_DEST (XVECEXP (newpat, 0, 0))))
3665 newi2pat = XVECEXP (newpat, 0, 0);
3666 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3667 newpat = XVECEXP (newpat, 0, 1);
3668 SUBST (SET_SRC (newpat),
3669 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3670 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3672 if (i2_code_number >= 0)
3673 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3675 if (insn_code_number >= 0)
3679 /* Similarly, check for a case where we have a PARALLEL of two independent
3680 SETs but we started with three insns. In this case, we can do the sets
3681 as two separate insns. This case occurs when some SET allows two
3682 other insns to combine, but the destination of that SET is still live. */
3684 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3685 && GET_CODE (newpat) == PARALLEL
3686 && XVECLEN (newpat, 0) == 2
3687 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3688 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3689 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3690 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3691 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3692 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3693 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3694 XVECEXP (newpat, 0, 0))
3695 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3696 XVECEXP (newpat, 0, 1))
3697 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3698 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3700 /* Normally, it doesn't matter which of the two is done first,
3701 but the one that references cc0 can't be the second, and
3702 one which uses any regs/memory set in between i2 and i3 can't
3704 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3707 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3711 newi2pat = XVECEXP (newpat, 0, 1);
3712 newpat = XVECEXP (newpat, 0, 0);
3714 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3717 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3721 newi2pat = XVECEXP (newpat, 0, 0);
3722 newpat = XVECEXP (newpat, 0, 1);
3730 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3732 if (i2_code_number >= 0)
3734 /* recog_for_combine might have added CLOBBERs to newi2pat.
3735 Make sure NEWPAT does not depend on the clobbered regs. */
3736 if (GET_CODE (newi2pat) == PARALLEL)
3738 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3739 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3741 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3742 if (reg_overlap_mentioned_p (reg, newpat))
3750 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3754 /* If it still isn't recognized, fail and change things back the way they
3756 if ((insn_code_number < 0
3757 /* Is the result a reasonable ASM_OPERANDS? */
3758 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3764 /* If we had to change another insn, make sure it is valid also. */
3765 if (undobuf.other_insn)
3767 CLEAR_HARD_REG_SET (newpat_used_regs);
3769 other_pat = PATTERN (undobuf.other_insn);
3770 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3773 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3781 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3782 they are adjacent to each other or not. */
3784 rtx p = prev_nonnote_insn (i3);
3785 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3786 && sets_cc0_p (newi2pat))
3794 /* Only allow this combination if insn_rtx_costs reports that the
3795 replacement instructions are cheaper than the originals. */
3796 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3802 if (MAY_HAVE_DEBUG_INSNS)
3806 for (undo = undobuf.undos; undo; undo = undo->next)
3807 if (undo->kind == UNDO_MODE)
3809 rtx reg = *undo->where.r;
3810 enum machine_mode new_mode = GET_MODE (reg);
3811 enum machine_mode old_mode = undo->old_contents.m;
3813 /* Temporarily revert mode back. */
3814 adjust_reg_mode (reg, old_mode);
3816 if (reg == i2dest && i2scratch)
3818 /* If we used i2dest as a scratch register with a
3819 different mode, substitute it for the original
3820 i2src while its original mode is temporarily
3821 restored, and then clear i2scratch so that we don't
3822 do it again later. */
3823 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3826 /* Put back the new mode. */
3827 adjust_reg_mode (reg, new_mode);
3831 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3837 last = last_combined_insn;
3842 last = undobuf.other_insn;
3844 if (DF_INSN_LUID (last)
3845 < DF_INSN_LUID (last_combined_insn))
3846 last = last_combined_insn;
3849 /* We're dealing with a reg that changed mode but not
3850 meaning, so we want to turn it into a subreg for
3851 the new mode. However, because of REG sharing and
3852 because its mode had already changed, we have to do
3853 it in two steps. First, replace any debug uses of
3854 reg, with its original mode temporarily restored,
3855 with this copy we have created; then, replace the
3856 copy with the SUBREG of the original shared reg,
3857 once again changed to the new mode. */
3858 propagate_for_debug (first, last, reg, tempreg,
3860 adjust_reg_mode (reg, new_mode);
3861 propagate_for_debug (first, last, tempreg,
3862 lowpart_subreg (old_mode, reg, new_mode),
3868 /* If we will be able to accept this, we have made a
3869 change to the destination of I3. This requires us to
3870 do a few adjustments. */
3872 if (changed_i3_dest)
3874 PATTERN (i3) = newpat;
3875 adjust_for_new_dest (i3);
3878 /* We now know that we can do this combination. Merge the insns and
3879 update the status of registers and LOG_LINKS. */
3881 if (undobuf.other_insn)
3885 PATTERN (undobuf.other_insn) = other_pat;
3887 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3888 are still valid. Then add any non-duplicate notes added by
3889 recog_for_combine. */
3890 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3892 next = XEXP (note, 1);
3894 if (REG_NOTE_KIND (note) == REG_UNUSED
3895 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3896 remove_note (undobuf.other_insn, note);
3899 distribute_notes (new_other_notes, undobuf.other_insn,
3900 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3907 struct insn_link *link;
3910 /* I3 now uses what used to be its destination and which is now
3911 I2's destination. This requires us to do a few adjustments. */
3912 PATTERN (i3) = newpat;
3913 adjust_for_new_dest (i3);
3915 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3918 However, some later insn might be using I2's dest and have
3919 a LOG_LINK pointing at I3. We must remove this link.
3920 The simplest way to remove the link is to point it at I1,
3921 which we know will be a NOTE. */
3923 /* newi2pat is usually a SET here; however, recog_for_combine might
3924 have added some clobbers. */
3925 if (GET_CODE (newi2pat) == PARALLEL)
3926 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3928 ni2dest = SET_DEST (newi2pat);
3930 for (insn = NEXT_INSN (i3);
3931 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3932 || insn != BB_HEAD (this_basic_block->next_bb));
3933 insn = NEXT_INSN (insn))
3935 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3937 FOR_EACH_LOG_LINK (link, insn)
3938 if (link->insn == i3)
3947 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3948 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3951 /* Compute which registers we expect to eliminate. newi2pat may be setting
3952 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3953 same as i3dest, in which case newi2pat may be setting i1dest. */
3954 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3955 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3958 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3959 || (newi2pat && reg_set_p (i1dest, newi2pat))
3962 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3963 || (newi2pat && reg_set_p (i0dest, newi2pat))
3967 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3969 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3970 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3972 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3974 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3976 /* Ensure that we do not have something that should not be shared but
3977 occurs multiple times in the new insns. Check this by first
3978 resetting all the `used' flags and then copying anything is shared. */
3980 reset_used_flags (i3notes);
3981 reset_used_flags (i2notes);
3982 reset_used_flags (i1notes);
3983 reset_used_flags (i0notes);
3984 reset_used_flags (newpat);
3985 reset_used_flags (newi2pat);
3986 if (undobuf.other_insn)
3987 reset_used_flags (PATTERN (undobuf.other_insn));
3989 i3notes = copy_rtx_if_shared (i3notes);
3990 i2notes = copy_rtx_if_shared (i2notes);
3991 i1notes = copy_rtx_if_shared (i1notes);
3992 i0notes = copy_rtx_if_shared (i0notes);
3993 newpat = copy_rtx_if_shared (newpat);
3994 newi2pat = copy_rtx_if_shared (newi2pat);
3995 if (undobuf.other_insn)
3996 reset_used_flags (PATTERN (undobuf.other_insn));
3998 INSN_CODE (i3) = insn_code_number;
3999 PATTERN (i3) = newpat;
4001 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4003 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4005 reset_used_flags (call_usage);
4006 call_usage = copy_rtx (call_usage);
4010 /* I2SRC must still be meaningful at this point. Some splitting
4011 operations can invalidate I2SRC, but those operations do not
4014 replace_rtx (call_usage, i2dest, i2src);
4018 replace_rtx (call_usage, i1dest, i1src);
4020 replace_rtx (call_usage, i0dest, i0src);
4022 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4025 if (undobuf.other_insn)
4026 INSN_CODE (undobuf.other_insn) = other_code_number;
4028 /* We had one special case above where I2 had more than one set and
4029 we replaced a destination of one of those sets with the destination
4030 of I3. In that case, we have to update LOG_LINKS of insns later
4031 in this basic block. Note that this (expensive) case is rare.
4033 Also, in this case, we must pretend that all REG_NOTEs for I2
4034 actually came from I3, so that REG_UNUSED notes from I2 will be
4035 properly handled. */
4037 if (i3_subst_into_i2)
4039 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4040 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4041 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4042 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4043 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4044 && ! find_reg_note (i2, REG_UNUSED,
4045 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4046 for (temp = NEXT_INSN (i2);
4047 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4048 || BB_HEAD (this_basic_block) != temp);
4049 temp = NEXT_INSN (temp))
4050 if (temp != i3 && INSN_P (temp))
4051 FOR_EACH_LOG_LINK (link, temp)
4052 if (link->insn == i2)
4058 while (XEXP (link, 1))
4059 link = XEXP (link, 1);
4060 XEXP (link, 1) = i2notes;
4067 LOG_LINKS (i3) = NULL;
4069 LOG_LINKS (i2) = NULL;
4074 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4075 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4077 INSN_CODE (i2) = i2_code_number;
4078 PATTERN (i2) = newi2pat;
4082 if (MAY_HAVE_DEBUG_INSNS && i2src)
4083 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4085 SET_INSN_DELETED (i2);
4090 LOG_LINKS (i1) = NULL;
4092 if (MAY_HAVE_DEBUG_INSNS)
4093 propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4095 SET_INSN_DELETED (i1);
4100 LOG_LINKS (i0) = NULL;
4102 if (MAY_HAVE_DEBUG_INSNS)
4103 propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4105 SET_INSN_DELETED (i0);
4108 /* Get death notes for everything that is now used in either I3 or
4109 I2 and used to die in a previous insn. If we built two new
4110 patterns, move from I1 to I2 then I2 to I3 so that we get the
4111 proper movement on registers that I2 modifies. */
4114 from_luid = DF_INSN_LUID (i0);
4116 from_luid = DF_INSN_LUID (i1);
4118 from_luid = DF_INSN_LUID (i2);
4120 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4121 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4123 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4125 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4126 elim_i2, elim_i1, elim_i0);
4128 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4129 elim_i2, elim_i1, elim_i0);
4131 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4132 elim_i2, elim_i1, elim_i0);
4134 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4135 elim_i2, elim_i1, elim_i0);
4137 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4138 elim_i2, elim_i1, elim_i0);
4140 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4141 know these are REG_UNUSED and want them to go to the desired insn,
4142 so we always pass it as i3. */
4144 if (newi2pat && new_i2_notes)
4145 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4149 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4152 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4153 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4154 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4155 in that case, it might delete I2. Similarly for I2 and I1.
4156 Show an additional death due to the REG_DEAD note we make here. If
4157 we discard it in distribute_notes, we will decrement it again. */
4161 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4162 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4164 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4166 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4168 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4169 elim_i2, elim_i1, elim_i0);
4172 if (i2dest_in_i2src)
4174 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4175 if (newi2pat && reg_set_p (i2dest, newi2pat))
4176 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4177 NULL_RTX, NULL_RTX);
4179 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4180 NULL_RTX, NULL_RTX, NULL_RTX);
4183 if (i1dest_in_i1src)
4185 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4186 if (newi2pat && reg_set_p (i1dest, newi2pat))
4187 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4188 NULL_RTX, NULL_RTX);
4190 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4191 NULL_RTX, NULL_RTX, NULL_RTX);
4194 if (i0dest_in_i0src)
4196 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4197 if (newi2pat && reg_set_p (i0dest, newi2pat))
4198 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4199 NULL_RTX, NULL_RTX);
4201 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4202 NULL_RTX, NULL_RTX, NULL_RTX);
4205 distribute_links (i3links);
4206 distribute_links (i2links);
4207 distribute_links (i1links);
4208 distribute_links (i0links);
4212 struct insn_link *link;
4213 rtx i2_insn = 0, i2_val = 0, set;
4215 /* The insn that used to set this register doesn't exist, and
4216 this life of the register may not exist either. See if one of
4217 I3's links points to an insn that sets I2DEST. If it does,
4218 that is now the last known value for I2DEST. If we don't update
4219 this and I2 set the register to a value that depended on its old
4220 contents, we will get confused. If this insn is used, thing
4221 will be set correctly in combine_instructions. */
4222 FOR_EACH_LOG_LINK (link, i3)
4223 if ((set = single_set (link->insn)) != 0
4224 && rtx_equal_p (i2dest, SET_DEST (set)))
4225 i2_insn = link->insn, i2_val = SET_SRC (set);
4227 record_value_for_reg (i2dest, i2_insn, i2_val);
4229 /* If the reg formerly set in I2 died only once and that was in I3,
4230 zero its use count so it won't make `reload' do any work. */
4232 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4233 && ! i2dest_in_i2src)
4234 INC_REG_N_SETS (REGNO (i2dest), -1);
4237 if (i1 && REG_P (i1dest))
4239 struct insn_link *link;
4240 rtx i1_insn = 0, i1_val = 0, set;
4242 FOR_EACH_LOG_LINK (link, i3)
4243 if ((set = single_set (link->insn)) != 0
4244 && rtx_equal_p (i1dest, SET_DEST (set)))
4245 i1_insn = link->insn, i1_val = SET_SRC (set);
4247 record_value_for_reg (i1dest, i1_insn, i1_val);
4249 if (! added_sets_1 && ! i1dest_in_i1src)
4250 INC_REG_N_SETS (REGNO (i1dest), -1);
4253 if (i0 && REG_P (i0dest))
4255 struct insn_link *link;
4256 rtx i0_insn = 0, i0_val = 0, set;
4258 FOR_EACH_LOG_LINK (link, i3)
4259 if ((set = single_set (link->insn)) != 0
4260 && rtx_equal_p (i0dest, SET_DEST (set)))
4261 i0_insn = link->insn, i0_val = SET_SRC (set);
4263 record_value_for_reg (i0dest, i0_insn, i0_val);
4265 if (! added_sets_0 && ! i0dest_in_i0src)
4266 INC_REG_N_SETS (REGNO (i0dest), -1);
4269 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4270 been made to this insn. The order of
4271 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4272 can affect nonzero_bits of newpat */
4274 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4275 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4278 if (undobuf.other_insn != NULL_RTX)
4282 fprintf (dump_file, "modifying other_insn ");
4283 dump_insn_slim (dump_file, undobuf.other_insn);
4285 df_insn_rescan (undobuf.other_insn);
4288 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4292 fprintf (dump_file, "modifying insn i1 ");
4293 dump_insn_slim (dump_file, i0);
4295 df_insn_rescan (i0);
4298 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4302 fprintf (dump_file, "modifying insn i1 ");
4303 dump_insn_slim (dump_file, i1);
4305 df_insn_rescan (i1);
4308 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4312 fprintf (dump_file, "modifying insn i2 ");
4313 dump_insn_slim (dump_file, i2);
4315 df_insn_rescan (i2);
4318 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4322 fprintf (dump_file, "modifying insn i3 ");
4323 dump_insn_slim (dump_file, i3);
4325 df_insn_rescan (i3);
4328 /* Set new_direct_jump_p if a new return or simple jump instruction
4329 has been created. Adjust the CFG accordingly. */
4331 if (returnjump_p (i3) || any_uncondjump_p (i3))
4333 *new_direct_jump_p = 1;
4334 mark_jump_label (PATTERN (i3), i3, 0);
4335 update_cfg_for_uncondjump (i3);
4338 if (undobuf.other_insn != NULL_RTX
4339 && (returnjump_p (undobuf.other_insn)
4340 || any_uncondjump_p (undobuf.other_insn)))
4342 *new_direct_jump_p = 1;
4343 update_cfg_for_uncondjump (undobuf.other_insn);
4346 /* A noop might also need cleaning up of CFG, if it comes from the
4347 simplification of a jump. */
4349 && GET_CODE (newpat) == SET
4350 && SET_SRC (newpat) == pc_rtx
4351 && SET_DEST (newpat) == pc_rtx)
4353 *new_direct_jump_p = 1;
4354 update_cfg_for_uncondjump (i3);
4357 if (undobuf.other_insn != NULL_RTX
4358 && JUMP_P (undobuf.other_insn)
4359 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4360 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4361 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4363 *new_direct_jump_p = 1;
4364 update_cfg_for_uncondjump (undobuf.other_insn);
4367 combine_successes++;
4370 if (added_links_insn
4371 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4372 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4373 return added_links_insn;
4375 return newi2pat ? i2 : i3;
4378 /* Undo all the modifications recorded in undobuf. */
4383 struct undo *undo, *next;
4385 for (undo = undobuf.undos; undo; undo = next)
4391 *undo->where.r = undo->old_contents.r;
4394 *undo->where.i = undo->old_contents.i;
4397 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4400 *undo->where.l = undo->old_contents.l;
4406 undo->next = undobuf.frees;
4407 undobuf.frees = undo;
4413 /* We've committed to accepting the changes we made. Move all
4414 of the undos to the free list. */
4419 struct undo *undo, *next;
4421 for (undo = undobuf.undos; undo; undo = next)
4424 undo->next = undobuf.frees;
4425 undobuf.frees = undo;
4430 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4431 where we have an arithmetic expression and return that point. LOC will
4434 try_combine will call this function to see if an insn can be split into
4438 find_split_point (rtx *loc, rtx insn, bool set_src)
4441 enum rtx_code code = GET_CODE (x);
4443 unsigned HOST_WIDE_INT len = 0;
4444 HOST_WIDE_INT pos = 0;
4446 rtx inner = NULL_RTX;
4448 /* First special-case some codes. */
4452 #ifdef INSN_SCHEDULING
4453 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4455 if (MEM_P (SUBREG_REG (x)))
4458 return find_split_point (&SUBREG_REG (x), insn, false);
4462 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4463 using LO_SUM and HIGH. */
4464 if (GET_CODE (XEXP (x, 0)) == CONST
4465 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4467 enum machine_mode address_mode = get_address_mode (x);
4470 gen_rtx_LO_SUM (address_mode,
4471 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4473 return &XEXP (XEXP (x, 0), 0);
4477 /* If we have a PLUS whose second operand is a constant and the
4478 address is not valid, perhaps will can split it up using
4479 the machine-specific way to split large constants. We use
4480 the first pseudo-reg (one of the virtual regs) as a placeholder;
4481 it will not remain in the result. */
4482 if (GET_CODE (XEXP (x, 0)) == PLUS
4483 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4484 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4485 MEM_ADDR_SPACE (x)))
4487 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4488 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4492 /* This should have produced two insns, each of which sets our
4493 placeholder. If the source of the second is a valid address,
4494 we can make put both sources together and make a split point
4498 && NEXT_INSN (seq) != NULL_RTX
4499 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4500 && NONJUMP_INSN_P (seq)
4501 && GET_CODE (PATTERN (seq)) == SET
4502 && SET_DEST (PATTERN (seq)) == reg
4503 && ! reg_mentioned_p (reg,
4504 SET_SRC (PATTERN (seq)))
4505 && NONJUMP_INSN_P (NEXT_INSN (seq))
4506 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4507 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4508 && memory_address_addr_space_p
4509 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4510 MEM_ADDR_SPACE (x)))
4512 rtx src1 = SET_SRC (PATTERN (seq));
4513 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4515 /* Replace the placeholder in SRC2 with SRC1. If we can
4516 find where in SRC2 it was placed, that can become our
4517 split point and we can replace this address with SRC2.
4518 Just try two obvious places. */
4520 src2 = replace_rtx (src2, reg, src1);
4522 if (XEXP (src2, 0) == src1)
4523 split = &XEXP (src2, 0);
4524 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4525 && XEXP (XEXP (src2, 0), 0) == src1)
4526 split = &XEXP (XEXP (src2, 0), 0);
4530 SUBST (XEXP (x, 0), src2);
4535 /* If that didn't work, perhaps the first operand is complex and
4536 needs to be computed separately, so make a split point there.
4537 This will occur on machines that just support REG + CONST
4538 and have a constant moved through some previous computation. */
4540 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4541 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4542 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4543 return &XEXP (XEXP (x, 0), 0);
4546 /* If we have a PLUS whose first operand is complex, try computing it
4547 separately by making a split there. */
4548 if (GET_CODE (XEXP (x, 0)) == PLUS
4549 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4551 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4552 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4553 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4554 return &XEXP (XEXP (x, 0), 0);
4559 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4560 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4561 we need to put the operand into a register. So split at that
4564 if (SET_DEST (x) == cc0_rtx
4565 && GET_CODE (SET_SRC (x)) != COMPARE
4566 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4567 && !OBJECT_P (SET_SRC (x))
4568 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4569 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4570 return &SET_SRC (x);
4573 /* See if we can split SET_SRC as it stands. */
4574 split = find_split_point (&SET_SRC (x), insn, true);
4575 if (split && split != &SET_SRC (x))
4578 /* See if we can split SET_DEST as it stands. */
4579 split = find_split_point (&SET_DEST (x), insn, false);
4580 if (split && split != &SET_DEST (x))
4583 /* See if this is a bitfield assignment with everything constant. If
4584 so, this is an IOR of an AND, so split it into that. */
4585 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4586 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4587 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4588 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4589 && CONST_INT_P (SET_SRC (x))
4590 && ((INTVAL (XEXP (SET_DEST (x), 1))
4591 + INTVAL (XEXP (SET_DEST (x), 2)))
4592 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4593 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4595 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4596 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4597 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4598 rtx dest = XEXP (SET_DEST (x), 0);
4599 enum machine_mode mode = GET_MODE (dest);
4600 unsigned HOST_WIDE_INT mask
4601 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4604 if (BITS_BIG_ENDIAN)
4605 pos = GET_MODE_PRECISION (mode) - len - pos;
4607 or_mask = gen_int_mode (src << pos, mode);
4610 simplify_gen_binary (IOR, mode, dest, or_mask));
4613 rtx negmask = gen_int_mode (~(mask << pos), mode);
4615 simplify_gen_binary (IOR, mode,
4616 simplify_gen_binary (AND, mode,
4621 SUBST (SET_DEST (x), dest);
4623 split = find_split_point (&SET_SRC (x), insn, true);
4624 if (split && split != &SET_SRC (x))
4628 /* Otherwise, see if this is an operation that we can split into two.
4629 If so, try to split that. */
4630 code = GET_CODE (SET_SRC (x));
4635 /* If we are AND'ing with a large constant that is only a single
4636 bit and the result is only being used in a context where we
4637 need to know if it is zero or nonzero, replace it with a bit
4638 extraction. This will avoid the large constant, which might
4639 have taken more than one insn to make. If the constant were
4640 not a valid argument to the AND but took only one insn to make,
4641 this is no worse, but if it took more than one insn, it will
4644 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4645 && REG_P (XEXP (SET_SRC (x), 0))
4646 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4647 && REG_P (SET_DEST (x))
4648 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4649 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4650 && XEXP (*split, 0) == SET_DEST (x)
4651 && XEXP (*split, 1) == const0_rtx)
4653 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4654 XEXP (SET_SRC (x), 0),
4655 pos, NULL_RTX, 1, 1, 0, 0);
4656 if (extraction != 0)
4658 SUBST (SET_SRC (x), extraction);
4659 return find_split_point (loc, insn, false);
4665 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4666 is known to be on, this can be converted into a NEG of a shift. */
4667 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4668 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4669 && 1 <= (pos = exact_log2
4670 (nonzero_bits (XEXP (SET_SRC (x), 0),
4671 GET_MODE (XEXP (SET_SRC (x), 0))))))
4673 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4677 gen_rtx_LSHIFTRT (mode,
4678 XEXP (SET_SRC (x), 0),
4681 split = find_split_point (&SET_SRC (x), insn, true);
4682 if (split && split != &SET_SRC (x))
4688 inner = XEXP (SET_SRC (x), 0);
4690 /* We can't optimize if either mode is a partial integer
4691 mode as we don't know how many bits are significant
4693 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4694 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4698 len = GET_MODE_PRECISION (GET_MODE (inner));
4704 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4705 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4707 inner = XEXP (SET_SRC (x), 0);
4708 len = INTVAL (XEXP (SET_SRC (x), 1));
4709 pos = INTVAL (XEXP (SET_SRC (x), 2));
4711 if (BITS_BIG_ENDIAN)
4712 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4713 unsignedp = (code == ZERO_EXTRACT);
4722 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4724 enum machine_mode mode = GET_MODE (SET_SRC (x));
4726 /* For unsigned, we have a choice of a shift followed by an
4727 AND or two shifts. Use two shifts for field sizes where the
4728 constant might be too large. We assume here that we can
4729 always at least get 8-bit constants in an AND insn, which is
4730 true for every current RISC. */
4732 if (unsignedp && len <= 8)
4737 (mode, gen_lowpart (mode, inner),
4739 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4742 split = find_split_point (&SET_SRC (x), insn, true);
4743 if (split && split != &SET_SRC (x))
4750 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4751 gen_rtx_ASHIFT (mode,
4752 gen_lowpart (mode, inner),
4753 GEN_INT (GET_MODE_PRECISION (mode)
4755 GEN_INT (GET_MODE_PRECISION (mode) - len)));
4757 split = find_split_point (&SET_SRC (x), insn, true);
4758 if (split && split != &SET_SRC (x))
4763 /* See if this is a simple operation with a constant as the second
4764 operand. It might be that this constant is out of range and hence
4765 could be used as a split point. */
4766 if (BINARY_P (SET_SRC (x))
4767 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4768 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4769 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4770 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4771 return &XEXP (SET_SRC (x), 1);
4773 /* Finally, see if this is a simple operation with its first operand
4774 not in a register. The operation might require this operand in a
4775 register, so return it as a split point. We can always do this
4776 because if the first operand were another operation, we would have
4777 already found it as a split point. */
4778 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4779 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4780 return &XEXP (SET_SRC (x), 0);
4786 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4787 it is better to write this as (not (ior A B)) so we can split it.
4788 Similarly for IOR. */
4789 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4792 gen_rtx_NOT (GET_MODE (x),
4793 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4795 XEXP (XEXP (x, 0), 0),
4796 XEXP (XEXP (x, 1), 0))));
4797 return find_split_point (loc, insn, set_src);
4800 /* Many RISC machines have a large set of logical insns. If the
4801 second operand is a NOT, put it first so we will try to split the
4802 other operand first. */
4803 if (GET_CODE (XEXP (x, 1)) == NOT)
4805 rtx tem = XEXP (x, 0);
4806 SUBST (XEXP (x, 0), XEXP (x, 1));
4807 SUBST (XEXP (x, 1), tem);
4813 /* Canonicalization can produce (minus A (mult B C)), where C is a
4814 constant. It may be better to try splitting (plus (mult B -C) A)
4815 instead if this isn't a multiply by a power of two. */
4816 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4817 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4818 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4820 enum machine_mode mode = GET_MODE (x);
4821 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4822 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4823 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4824 XEXP (XEXP (x, 1), 0),
4825 GEN_INT (other_int)),
4827 return find_split_point (loc, insn, set_src);
4830 /* Split at a multiply-accumulate instruction. However if this is
4831 the SET_SRC, we likely do not have such an instruction and it's
4832 worthless to try this split. */
4833 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4840 /* Otherwise, select our actions depending on our rtx class. */
4841 switch (GET_RTX_CLASS (code))
4843 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4845 split = find_split_point (&XEXP (x, 2), insn, false);
4848 /* ... fall through ... */
4850 case RTX_COMM_ARITH:
4852 case RTX_COMM_COMPARE:
4853 split = find_split_point (&XEXP (x, 1), insn, false);
4856 /* ... fall through ... */
4858 /* Some machines have (and (shift ...) ...) insns. If X is not
4859 an AND, but XEXP (X, 0) is, use it as our split point. */
4860 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4861 return &XEXP (x, 0);
4863 split = find_split_point (&XEXP (x, 0), insn, false);
4869 /* Otherwise, we don't have a split point. */
4874 /* Throughout X, replace FROM with TO, and return the result.
4875 The result is TO if X is FROM;
4876 otherwise the result is X, but its contents may have been modified.
4877 If they were modified, a record was made in undobuf so that
4878 undo_all will (among other things) return X to its original state.
4880 If the number of changes necessary is too much to record to undo,
4881 the excess changes are not made, so the result is invalid.
4882 The changes already made can still be undone.
4883 undobuf.num_undo is incremented for such changes, so by testing that
4884 the caller can tell whether the result is valid.
4886 `n_occurrences' is incremented each time FROM is replaced.
4888 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4890 IN_COND is nonzero if we are at the top level of a condition.
4892 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4893 by copying if `n_occurrences' is nonzero. */
4896 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4898 enum rtx_code code = GET_CODE (x);
4899 enum machine_mode op0_mode = VOIDmode;
4904 /* Two expressions are equal if they are identical copies of a shared
4905 RTX or if they are both registers with the same register number
4908 #define COMBINE_RTX_EQUAL_P(X,Y) \
4910 || (REG_P (X) && REG_P (Y) \
4911 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4913 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4916 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4919 /* If X and FROM are the same register but different modes, they
4920 will not have been seen as equal above. However, the log links code
4921 will make a LOG_LINKS entry for that case. If we do nothing, we
4922 will try to rerecognize our original insn and, when it succeeds,
4923 we will delete the feeding insn, which is incorrect.
4925 So force this insn not to match in this (rare) case. */
4926 if (! in_dest && code == REG && REG_P (from)
4927 && reg_overlap_mentioned_p (x, from))
4928 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4930 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4931 of which may contain things that can be combined. */
4932 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4935 /* It is possible to have a subexpression appear twice in the insn.
4936 Suppose that FROM is a register that appears within TO.
4937 Then, after that subexpression has been scanned once by `subst',
4938 the second time it is scanned, TO may be found. If we were
4939 to scan TO here, we would find FROM within it and create a
4940 self-referent rtl structure which is completely wrong. */
4941 if (COMBINE_RTX_EQUAL_P (x, to))
4944 /* Parallel asm_operands need special attention because all of the
4945 inputs are shared across the arms. Furthermore, unsharing the
4946 rtl results in recognition failures. Failure to handle this case
4947 specially can result in circular rtl.
4949 Solve this by doing a normal pass across the first entry of the
4950 parallel, and only processing the SET_DESTs of the subsequent
4953 if (code == PARALLEL
4954 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4955 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4957 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4959 /* If this substitution failed, this whole thing fails. */
4960 if (GET_CODE (new_rtx) == CLOBBER
4961 && XEXP (new_rtx, 0) == const0_rtx)
4964 SUBST (XVECEXP (x, 0, 0), new_rtx);
4966 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4968 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4971 && GET_CODE (dest) != CC0
4972 && GET_CODE (dest) != PC)
4974 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4976 /* If this substitution failed, this whole thing fails. */
4977 if (GET_CODE (new_rtx) == CLOBBER
4978 && XEXP (new_rtx, 0) == const0_rtx)
4981 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4987 len = GET_RTX_LENGTH (code);
4988 fmt = GET_RTX_FORMAT (code);
4990 /* We don't need to process a SET_DEST that is a register, CC0,
4991 or PC, so set up to skip this common case. All other cases
4992 where we want to suppress replacing something inside a
4993 SET_SRC are handled via the IN_DEST operand. */
4995 && (REG_P (SET_DEST (x))
4996 || GET_CODE (SET_DEST (x)) == CC0
4997 || GET_CODE (SET_DEST (x)) == PC))
5000 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5003 op0_mode = GET_MODE (XEXP (x, 0));
5005 for (i = 0; i < len; i++)
5010 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5012 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5014 new_rtx = (unique_copy && n_occurrences
5015 ? copy_rtx (to) : to);
5020 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5023 /* If this substitution failed, this whole thing
5025 if (GET_CODE (new_rtx) == CLOBBER
5026 && XEXP (new_rtx, 0) == const0_rtx)
5030 SUBST (XVECEXP (x, i, j), new_rtx);
5033 else if (fmt[i] == 'e')
5035 /* If this is a register being set, ignore it. */
5036 new_rtx = XEXP (x, i);
5039 && (((code == SUBREG || code == ZERO_EXTRACT)
5041 || code == STRICT_LOW_PART))
5044 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5046 /* In general, don't install a subreg involving two
5047 modes not tieable. It can worsen register
5048 allocation, and can even make invalid reload
5049 insns, since the reg inside may need to be copied
5050 from in the outside mode, and that may be invalid
5051 if it is an fp reg copied in integer mode.
5053 We allow two exceptions to this: It is valid if
5054 it is inside another SUBREG and the mode of that
5055 SUBREG and the mode of the inside of TO is
5056 tieable and it is valid if X is a SET that copies
5059 if (GET_CODE (to) == SUBREG
5060 && ! MODES_TIEABLE_P (GET_MODE (to),
5061 GET_MODE (SUBREG_REG (to)))
5062 && ! (code == SUBREG
5063 && MODES_TIEABLE_P (GET_MODE (x),
5064 GET_MODE (SUBREG_REG (to))))
5066 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5069 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5071 #ifdef CANNOT_CHANGE_MODE_CLASS
5074 && REGNO (to) < FIRST_PSEUDO_REGISTER
5075 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5078 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5081 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5085 /* If we are in a SET_DEST, suppress most cases unless we
5086 have gone inside a MEM, in which case we want to
5087 simplify the address. We assume here that things that
5088 are actually part of the destination have their inner
5089 parts in the first expression. This is true for SUBREG,
5090 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5091 things aside from REG and MEM that should appear in a
5093 new_rtx = subst (XEXP (x, i), from, to,
5095 && (code == SUBREG || code == STRICT_LOW_PART
5096 || code == ZERO_EXTRACT))
5099 code == IF_THEN_ELSE && i == 0,
5102 /* If we found that we will have to reject this combination,
5103 indicate that by returning the CLOBBER ourselves, rather than
5104 an expression containing it. This will speed things up as
5105 well as prevent accidents where two CLOBBERs are considered
5106 to be equal, thus producing an incorrect simplification. */
5108 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5111 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5113 enum machine_mode mode = GET_MODE (x);
5115 x = simplify_subreg (GET_MODE (x), new_rtx,
5116 GET_MODE (SUBREG_REG (x)),
5119 x = gen_rtx_CLOBBER (mode, const0_rtx);
5121 else if (CONST_INT_P (new_rtx)
5122 && GET_CODE (x) == ZERO_EXTEND)
5124 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5125 new_rtx, GET_MODE (XEXP (x, 0)));
5129 SUBST (XEXP (x, i), new_rtx);
5134 /* Check if we are loading something from the constant pool via float
5135 extension; in this case we would undo compress_float_constant
5136 optimization and degenerate constant load to an immediate value. */
5137 if (GET_CODE (x) == FLOAT_EXTEND
5138 && MEM_P (XEXP (x, 0))
5139 && MEM_READONLY_P (XEXP (x, 0)))
5141 rtx tmp = avoid_constant_pool_reference (x);
5146 /* Try to simplify X. If the simplification changed the code, it is likely
5147 that further simplification will help, so loop, but limit the number
5148 of repetitions that will be performed. */
5150 for (i = 0; i < 4; i++)
5152 /* If X is sufficiently simple, don't bother trying to do anything
5154 if (code != CONST_INT && code != REG && code != CLOBBER)
5155 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5157 if (GET_CODE (x) == code)
5160 code = GET_CODE (x);
5162 /* We no longer know the original mode of operand 0 since we
5163 have changed the form of X) */
5164 op0_mode = VOIDmode;
5170 /* Simplify X, a piece of RTL. We just operate on the expression at the
5171 outer level; call `subst' to simplify recursively. Return the new
5174 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5175 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5179 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5182 enum rtx_code code = GET_CODE (x);
5183 enum machine_mode mode = GET_MODE (x);
5187 /* If this is a commutative operation, put a constant last and a complex
5188 expression first. We don't need to do this for comparisons here. */
5189 if (COMMUTATIVE_ARITH_P (x)
5190 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5193 SUBST (XEXP (x, 0), XEXP (x, 1));
5194 SUBST (XEXP (x, 1), temp);
5197 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5198 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5199 things. Check for cases where both arms are testing the same
5202 Don't do anything if all operands are very simple. */
5205 && ((!OBJECT_P (XEXP (x, 0))
5206 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5207 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5208 || (!OBJECT_P (XEXP (x, 1))
5209 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5210 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5212 && (!OBJECT_P (XEXP (x, 0))
5213 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5214 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5216 rtx cond, true_rtx, false_rtx;
5218 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5220 /* If everything is a comparison, what we have is highly unlikely
5221 to be simpler, so don't use it. */
5222 && ! (COMPARISON_P (x)
5223 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5225 rtx cop1 = const0_rtx;
5226 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5228 if (cond_code == NE && COMPARISON_P (cond))
5231 /* Simplify the alternative arms; this may collapse the true and
5232 false arms to store-flag values. Be careful to use copy_rtx
5233 here since true_rtx or false_rtx might share RTL with x as a
5234 result of the if_then_else_cond call above. */
5235 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5236 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5238 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5239 is unlikely to be simpler. */
5240 if (general_operand (true_rtx, VOIDmode)
5241 && general_operand (false_rtx, VOIDmode))
5243 enum rtx_code reversed;
5245 /* Restarting if we generate a store-flag expression will cause
5246 us to loop. Just drop through in this case. */
5248 /* If the result values are STORE_FLAG_VALUE and zero, we can
5249 just make the comparison operation. */
5250 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5251 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5253 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5254 && ((reversed = reversed_comparison_code_parts
5255 (cond_code, cond, cop1, NULL))
5257 x = simplify_gen_relational (reversed, mode, VOIDmode,
5260 /* Likewise, we can make the negate of a comparison operation
5261 if the result values are - STORE_FLAG_VALUE and zero. */
5262 else if (CONST_INT_P (true_rtx)
5263 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5264 && false_rtx == const0_rtx)
5265 x = simplify_gen_unary (NEG, mode,
5266 simplify_gen_relational (cond_code,
5270 else if (CONST_INT_P (false_rtx)
5271 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5272 && true_rtx == const0_rtx
5273 && ((reversed = reversed_comparison_code_parts
5274 (cond_code, cond, cop1, NULL))
5276 x = simplify_gen_unary (NEG, mode,
5277 simplify_gen_relational (reversed,
5282 return gen_rtx_IF_THEN_ELSE (mode,
5283 simplify_gen_relational (cond_code,
5288 true_rtx, false_rtx);
5290 code = GET_CODE (x);
5291 op0_mode = VOIDmode;
5296 /* Try to fold this expression in case we have constants that weren't
5299 switch (GET_RTX_CLASS (code))
5302 if (op0_mode == VOIDmode)
5303 op0_mode = GET_MODE (XEXP (x, 0));
5304 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5307 case RTX_COMM_COMPARE:
5309 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5310 if (cmp_mode == VOIDmode)
5312 cmp_mode = GET_MODE (XEXP (x, 1));
5313 if (cmp_mode == VOIDmode)
5314 cmp_mode = op0_mode;
5316 temp = simplify_relational_operation (code, mode, cmp_mode,
5317 XEXP (x, 0), XEXP (x, 1));
5320 case RTX_COMM_ARITH:
5322 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5324 case RTX_BITFIELD_OPS:
5326 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5327 XEXP (x, 1), XEXP (x, 2));
5336 code = GET_CODE (temp);
5337 op0_mode = VOIDmode;
5338 mode = GET_MODE (temp);
5341 /* First see if we can apply the inverse distributive law. */
5342 if (code == PLUS || code == MINUS
5343 || code == AND || code == IOR || code == XOR)
5345 x = apply_distributive_law (x);
5346 code = GET_CODE (x);
5347 op0_mode = VOIDmode;
5350 /* If CODE is an associative operation not otherwise handled, see if we
5351 can associate some operands. This can win if they are constants or
5352 if they are logically related (i.e. (a & b) & a). */
5353 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5354 || code == AND || code == IOR || code == XOR
5355 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5356 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5357 || (flag_associative_math && FLOAT_MODE_P (mode))))
5359 if (GET_CODE (XEXP (x, 0)) == code)
5361 rtx other = XEXP (XEXP (x, 0), 0);
5362 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5363 rtx inner_op1 = XEXP (x, 1);
5366 /* Make sure we pass the constant operand if any as the second
5367 one if this is a commutative operation. */
5368 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5370 rtx tem = inner_op0;
5371 inner_op0 = inner_op1;
5374 inner = simplify_binary_operation (code == MINUS ? PLUS
5375 : code == DIV ? MULT
5377 mode, inner_op0, inner_op1);
5379 /* For commutative operations, try the other pair if that one
5381 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5383 other = XEXP (XEXP (x, 0), 1);
5384 inner = simplify_binary_operation (code, mode,
5385 XEXP (XEXP (x, 0), 0),
5390 return simplify_gen_binary (code, mode, other, inner);
5394 /* A little bit of algebraic simplification here. */
5398 /* Ensure that our address has any ASHIFTs converted to MULT in case
5399 address-recognizing predicates are called later. */
5400 temp = make_compound_operation (XEXP (x, 0), MEM);
5401 SUBST (XEXP (x, 0), temp);
5405 if (op0_mode == VOIDmode)
5406 op0_mode = GET_MODE (SUBREG_REG (x));
5408 /* See if this can be moved to simplify_subreg. */
5409 if (CONSTANT_P (SUBREG_REG (x))
5410 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5411 /* Don't call gen_lowpart if the inner mode
5412 is VOIDmode and we cannot simplify it, as SUBREG without
5413 inner mode is invalid. */
5414 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5415 || gen_lowpart_common (mode, SUBREG_REG (x))))
5416 return gen_lowpart (mode, SUBREG_REG (x));
5418 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5422 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5428 /* Don't change the mode of the MEM if that would change the meaning
5430 if (MEM_P (SUBREG_REG (x))
5431 && (MEM_VOLATILE_P (SUBREG_REG (x))
5432 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5433 MEM_ADDR_SPACE (SUBREG_REG (x)))))
5434 return gen_rtx_CLOBBER (mode, const0_rtx);
5436 /* Note that we cannot do any narrowing for non-constants since
5437 we might have been counting on using the fact that some bits were
5438 zero. We now do this in the SET. */
5443 temp = expand_compound_operation (XEXP (x, 0));
5445 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5446 replaced by (lshiftrt X C). This will convert
5447 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5449 if (GET_CODE (temp) == ASHIFTRT
5450 && CONST_INT_P (XEXP (temp, 1))
5451 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5452 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5453 INTVAL (XEXP (temp, 1)));
5455 /* If X has only a single bit that might be nonzero, say, bit I, convert
5456 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5457 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5458 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5459 or a SUBREG of one since we'd be making the expression more
5460 complex if it was just a register. */
5463 && ! (GET_CODE (temp) == SUBREG
5464 && REG_P (SUBREG_REG (temp)))
5465 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5467 rtx temp1 = simplify_shift_const
5468 (NULL_RTX, ASHIFTRT, mode,
5469 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5470 GET_MODE_PRECISION (mode) - 1 - i),
5471 GET_MODE_PRECISION (mode) - 1 - i);
5473 /* If all we did was surround TEMP with the two shifts, we
5474 haven't improved anything, so don't use it. Otherwise,
5475 we are better off with TEMP1. */
5476 if (GET_CODE (temp1) != ASHIFTRT
5477 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5478 || XEXP (XEXP (temp1, 0), 0) != temp)
5484 /* We can't handle truncation to a partial integer mode here
5485 because we don't know the real bitsize of the partial
5487 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5490 if (HWI_COMPUTABLE_MODE_P (mode))
5492 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5493 GET_MODE_MASK (mode), 0));
5495 /* We can truncate a constant value and return it. */
5496 if (CONST_INT_P (XEXP (x, 0)))
5497 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5499 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5500 whose value is a comparison can be replaced with a subreg if
5501 STORE_FLAG_VALUE permits. */
5502 if (HWI_COMPUTABLE_MODE_P (mode)
5503 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5504 && (temp = get_last_value (XEXP (x, 0)))
5505 && COMPARISON_P (temp))
5506 return gen_lowpart (mode, XEXP (x, 0));
5510 /* (const (const X)) can become (const X). Do it this way rather than
5511 returning the inner CONST since CONST can be shared with a
5513 if (GET_CODE (XEXP (x, 0)) == CONST)
5514 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5519 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5520 can add in an offset. find_split_point will split this address up
5521 again if it doesn't match. */
5522 if (GET_CODE (XEXP (x, 0)) == HIGH
5523 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5529 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5530 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5531 bit-field and can be replaced by either a sign_extend or a
5532 sign_extract. The `and' may be a zero_extend and the two
5533 <c>, -<c> constants may be reversed. */
5534 if (GET_CODE (XEXP (x, 0)) == XOR
5535 && CONST_INT_P (XEXP (x, 1))
5536 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5537 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5538 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5539 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5540 && HWI_COMPUTABLE_MODE_P (mode)
5541 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5542 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5543 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5544 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5545 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5546 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5547 == (unsigned int) i + 1))))
5548 return simplify_shift_const
5549 (NULL_RTX, ASHIFTRT, mode,
5550 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5551 XEXP (XEXP (XEXP (x, 0), 0), 0),
5552 GET_MODE_PRECISION (mode) - (i + 1)),
5553 GET_MODE_PRECISION (mode) - (i + 1));
5555 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5556 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5557 the bitsize of the mode - 1. This allows simplification of
5558 "a = (b & 8) == 0;" */
5559 if (XEXP (x, 1) == constm1_rtx
5560 && !REG_P (XEXP (x, 0))
5561 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5562 && REG_P (SUBREG_REG (XEXP (x, 0))))
5563 && nonzero_bits (XEXP (x, 0), mode) == 1)
5564 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5565 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5566 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5567 GET_MODE_PRECISION (mode) - 1),
5568 GET_MODE_PRECISION (mode) - 1);
5570 /* If we are adding two things that have no bits in common, convert
5571 the addition into an IOR. This will often be further simplified,
5572 for example in cases like ((a & 1) + (a & 2)), which can
5575 if (HWI_COMPUTABLE_MODE_P (mode)
5576 && (nonzero_bits (XEXP (x, 0), mode)
5577 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5579 /* Try to simplify the expression further. */
5580 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5581 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5583 /* If we could, great. If not, do not go ahead with the IOR
5584 replacement, since PLUS appears in many special purpose
5585 address arithmetic instructions. */
5586 if (GET_CODE (temp) != CLOBBER
5587 && (GET_CODE (temp) != IOR
5588 || ((XEXP (temp, 0) != XEXP (x, 0)
5589 || XEXP (temp, 1) != XEXP (x, 1))
5590 && (XEXP (temp, 0) != XEXP (x, 1)
5591 || XEXP (temp, 1) != XEXP (x, 0)))))
5597 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5598 (and <foo> (const_int pow2-1)) */
5599 if (GET_CODE (XEXP (x, 1)) == AND
5600 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5601 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5602 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5603 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5604 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5608 /* If we have (mult (plus A B) C), apply the distributive law and then
5609 the inverse distributive law to see if things simplify. This
5610 occurs mostly in addresses, often when unrolling loops. */
5612 if (GET_CODE (XEXP (x, 0)) == PLUS)
5614 rtx result = distribute_and_simplify_rtx (x, 0);
5619 /* Try simplify a*(b/c) as (a*b)/c. */
5620 if (FLOAT_MODE_P (mode) && flag_associative_math
5621 && GET_CODE (XEXP (x, 0)) == DIV)
5623 rtx tem = simplify_binary_operation (MULT, mode,
5624 XEXP (XEXP (x, 0), 0),
5627 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5632 /* If this is a divide by a power of two, treat it as a shift if
5633 its first operand is a shift. */
5634 if (CONST_INT_P (XEXP (x, 1))
5635 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5636 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5637 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5638 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5639 || GET_CODE (XEXP (x, 0)) == ROTATE
5640 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5641 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5645 case GT: case GTU: case GE: case GEU:
5646 case LT: case LTU: case LE: case LEU:
5647 case UNEQ: case LTGT:
5648 case UNGT: case UNGE:
5649 case UNLT: case UNLE:
5650 case UNORDERED: case ORDERED:
5651 /* If the first operand is a condition code, we can't do anything
5653 if (GET_CODE (XEXP (x, 0)) == COMPARE
5654 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5655 && ! CC0_P (XEXP (x, 0))))
5657 rtx op0 = XEXP (x, 0);
5658 rtx op1 = XEXP (x, 1);
5659 enum rtx_code new_code;
5661 if (GET_CODE (op0) == COMPARE)
5662 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5664 /* Simplify our comparison, if possible. */
5665 new_code = simplify_comparison (code, &op0, &op1);
5667 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5668 if only the low-order bit is possibly nonzero in X (such as when
5669 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5670 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5671 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5674 Remove any ZERO_EXTRACT we made when thinking this was a
5675 comparison. It may now be simpler to use, e.g., an AND. If a
5676 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5677 the call to make_compound_operation in the SET case.
5679 Don't apply these optimizations if the caller would
5680 prefer a comparison rather than a value.
5681 E.g., for the condition in an IF_THEN_ELSE most targets need
5682 an explicit comparison. */
5687 else if (STORE_FLAG_VALUE == 1
5688 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5689 && op1 == const0_rtx
5690 && mode == GET_MODE (op0)
5691 && nonzero_bits (op0, mode) == 1)
5692 return gen_lowpart (mode,
5693 expand_compound_operation (op0));
5695 else if (STORE_FLAG_VALUE == 1
5696 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5697 && op1 == const0_rtx
5698 && mode == GET_MODE (op0)
5699 && (num_sign_bit_copies (op0, mode)
5700 == GET_MODE_PRECISION (mode)))
5702 op0 = expand_compound_operation (op0);
5703 return simplify_gen_unary (NEG, mode,
5704 gen_lowpart (mode, op0),
5708 else if (STORE_FLAG_VALUE == 1
5709 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5710 && op1 == const0_rtx
5711 && mode == GET_MODE (op0)
5712 && nonzero_bits (op0, mode) == 1)
5714 op0 = expand_compound_operation (op0);
5715 return simplify_gen_binary (XOR, mode,
5716 gen_lowpart (mode, op0),
5720 else if (STORE_FLAG_VALUE == 1
5721 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5722 && op1 == const0_rtx
5723 && mode == GET_MODE (op0)
5724 && (num_sign_bit_copies (op0, mode)
5725 == GET_MODE_PRECISION (mode)))
5727 op0 = expand_compound_operation (op0);
5728 return plus_constant (mode, gen_lowpart (mode, op0), 1);
5731 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5736 else if (STORE_FLAG_VALUE == -1
5737 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5738 && op1 == const0_rtx
5739 && (num_sign_bit_copies (op0, mode)
5740 == GET_MODE_PRECISION (mode)))
5741 return gen_lowpart (mode,
5742 expand_compound_operation (op0));
5744 else if (STORE_FLAG_VALUE == -1
5745 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5746 && op1 == const0_rtx
5747 && mode == GET_MODE (op0)
5748 && nonzero_bits (op0, mode) == 1)
5750 op0 = expand_compound_operation (op0);
5751 return simplify_gen_unary (NEG, mode,
5752 gen_lowpart (mode, op0),
5756 else if (STORE_FLAG_VALUE == -1
5757 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5758 && op1 == const0_rtx
5759 && mode == GET_MODE (op0)
5760 && (num_sign_bit_copies (op0, mode)
5761 == GET_MODE_PRECISION (mode)))
5763 op0 = expand_compound_operation (op0);
5764 return simplify_gen_unary (NOT, mode,
5765 gen_lowpart (mode, op0),
5769 /* If X is 0/1, (eq X 0) is X-1. */
5770 else if (STORE_FLAG_VALUE == -1
5771 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5772 && op1 == const0_rtx
5773 && mode == GET_MODE (op0)
5774 && nonzero_bits (op0, mode) == 1)
5776 op0 = expand_compound_operation (op0);
5777 return plus_constant (mode, gen_lowpart (mode, op0), -1);
5780 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5781 one bit that might be nonzero, we can convert (ne x 0) to
5782 (ashift x c) where C puts the bit in the sign bit. Remove any
5783 AND with STORE_FLAG_VALUE when we are done, since we are only
5784 going to test the sign bit. */
5785 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5786 && HWI_COMPUTABLE_MODE_P (mode)
5787 && val_signbit_p (mode, STORE_FLAG_VALUE)
5788 && op1 == const0_rtx
5789 && mode == GET_MODE (op0)
5790 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5792 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5793 expand_compound_operation (op0),
5794 GET_MODE_PRECISION (mode) - 1 - i);
5795 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5801 /* If the code changed, return a whole new comparison. */
5802 if (new_code != code)
5803 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5805 /* Otherwise, keep this operation, but maybe change its operands.
5806 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5807 SUBST (XEXP (x, 0), op0);
5808 SUBST (XEXP (x, 1), op1);
5813 return simplify_if_then_else (x);
5819 /* If we are processing SET_DEST, we are done. */
5823 return expand_compound_operation (x);
5826 return simplify_set (x);
5830 return simplify_logical (x);
5837 /* If this is a shift by a constant amount, simplify it. */
5838 if (CONST_INT_P (XEXP (x, 1)))
5839 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5840 INTVAL (XEXP (x, 1)));
5842 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5844 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5845 ((unsigned HOST_WIDE_INT) 1
5846 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5858 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5861 simplify_if_then_else (rtx x)
5863 enum machine_mode mode = GET_MODE (x);
5864 rtx cond = XEXP (x, 0);
5865 rtx true_rtx = XEXP (x, 1);
5866 rtx false_rtx = XEXP (x, 2);
5867 enum rtx_code true_code = GET_CODE (cond);
5868 int comparison_p = COMPARISON_P (cond);
5871 enum rtx_code false_code;
5874 /* Simplify storing of the truth value. */
5875 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5876 return simplify_gen_relational (true_code, mode, VOIDmode,
5877 XEXP (cond, 0), XEXP (cond, 1));
5879 /* Also when the truth value has to be reversed. */
5881 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5882 && (reversed = reversed_comparison (cond, mode)))
5885 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5886 in it is being compared against certain values. Get the true and false
5887 comparisons and see if that says anything about the value of each arm. */
5890 && ((false_code = reversed_comparison_code (cond, NULL))
5892 && REG_P (XEXP (cond, 0)))
5895 rtx from = XEXP (cond, 0);
5896 rtx true_val = XEXP (cond, 1);
5897 rtx false_val = true_val;
5900 /* If FALSE_CODE is EQ, swap the codes and arms. */
5902 if (false_code == EQ)
5904 swapped = 1, true_code = EQ, false_code = NE;
5905 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5908 /* If we are comparing against zero and the expression being tested has
5909 only a single bit that might be nonzero, that is its value when it is
5910 not equal to zero. Similarly if it is known to be -1 or 0. */
5912 if (true_code == EQ && true_val == const0_rtx
5913 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5916 false_val = gen_int_mode (nzb, GET_MODE (from));
5918 else if (true_code == EQ && true_val == const0_rtx
5919 && (num_sign_bit_copies (from, GET_MODE (from))
5920 == GET_MODE_PRECISION (GET_MODE (from))))
5923 false_val = constm1_rtx;
5926 /* Now simplify an arm if we know the value of the register in the
5927 branch and it is used in the arm. Be careful due to the potential
5928 of locally-shared RTL. */
5930 if (reg_mentioned_p (from, true_rtx))
5931 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5933 pc_rtx, pc_rtx, 0, 0, 0);
5934 if (reg_mentioned_p (from, false_rtx))
5935 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5937 pc_rtx, pc_rtx, 0, 0, 0);
5939 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5940 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5942 true_rtx = XEXP (x, 1);
5943 false_rtx = XEXP (x, 2);
5944 true_code = GET_CODE (cond);
5947 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5948 reversed, do so to avoid needing two sets of patterns for
5949 subtract-and-branch insns. Similarly if we have a constant in the true
5950 arm, the false arm is the same as the first operand of the comparison, or
5951 the false arm is more complicated than the true arm. */
5954 && reversed_comparison_code (cond, NULL) != UNKNOWN
5955 && (true_rtx == pc_rtx
5956 || (CONSTANT_P (true_rtx)
5957 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5958 || true_rtx == const0_rtx
5959 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5960 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5961 && !OBJECT_P (false_rtx))
5962 || reg_mentioned_p (true_rtx, false_rtx)
5963 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5965 true_code = reversed_comparison_code (cond, NULL);
5966 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5967 SUBST (XEXP (x, 1), false_rtx);
5968 SUBST (XEXP (x, 2), true_rtx);
5970 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5973 /* It is possible that the conditional has been simplified out. */
5974 true_code = GET_CODE (cond);
5975 comparison_p = COMPARISON_P (cond);
5978 /* If the two arms are identical, we don't need the comparison. */
5980 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5983 /* Convert a == b ? b : a to "a". */
5984 if (true_code == EQ && ! side_effects_p (cond)
5985 && !HONOR_NANS (mode)
5986 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5987 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5989 else if (true_code == NE && ! side_effects_p (cond)
5990 && !HONOR_NANS (mode)
5991 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5992 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5995 /* Look for cases where we have (abs x) or (neg (abs X)). */
5997 if (GET_MODE_CLASS (mode) == MODE_INT
5999 && XEXP (cond, 1) == const0_rtx
6000 && GET_CODE (false_rtx) == NEG
6001 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6002 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6003 && ! side_effects_p (true_rtx))
6008 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6012 simplify_gen_unary (NEG, mode,
6013 simplify_gen_unary (ABS, mode, true_rtx, mode),
6019 /* Look for MIN or MAX. */
6021 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6023 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6024 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6025 && ! side_effects_p (cond))
6030 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6033 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6036 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6039 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6044 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6045 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6046 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6047 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6048 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6049 neither 1 or -1, but it isn't worth checking for. */
6051 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6053 && GET_MODE_CLASS (mode) == MODE_INT
6054 && ! side_effects_p (x))
6056 rtx t = make_compound_operation (true_rtx, SET);
6057 rtx f = make_compound_operation (false_rtx, SET);
6058 rtx cond_op0 = XEXP (cond, 0);
6059 rtx cond_op1 = XEXP (cond, 1);
6060 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6061 enum machine_mode m = mode;
6062 rtx z = 0, c1 = NULL_RTX;
6064 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6065 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6066 || GET_CODE (t) == ASHIFT
6067 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6068 && rtx_equal_p (XEXP (t, 0), f))
6069 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6071 /* If an identity-zero op is commutative, check whether there
6072 would be a match if we swapped the operands. */
6073 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6074 || GET_CODE (t) == XOR)
6075 && rtx_equal_p (XEXP (t, 1), f))
6076 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6077 else if (GET_CODE (t) == SIGN_EXTEND
6078 && (GET_CODE (XEXP (t, 0)) == PLUS
6079 || GET_CODE (XEXP (t, 0)) == MINUS
6080 || GET_CODE (XEXP (t, 0)) == IOR
6081 || GET_CODE (XEXP (t, 0)) == XOR
6082 || GET_CODE (XEXP (t, 0)) == ASHIFT
6083 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6084 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6085 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6086 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6087 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6088 && (num_sign_bit_copies (f, GET_MODE (f))
6090 (GET_MODE_PRECISION (mode)
6091 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6093 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6094 extend_op = SIGN_EXTEND;
6095 m = GET_MODE (XEXP (t, 0));
6097 else if (GET_CODE (t) == SIGN_EXTEND
6098 && (GET_CODE (XEXP (t, 0)) == PLUS
6099 || GET_CODE (XEXP (t, 0)) == IOR
6100 || GET_CODE (XEXP (t, 0)) == XOR)
6101 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6102 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6103 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6104 && (num_sign_bit_copies (f, GET_MODE (f))
6106 (GET_MODE_PRECISION (mode)
6107 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6109 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6110 extend_op = SIGN_EXTEND;
6111 m = GET_MODE (XEXP (t, 0));
6113 else if (GET_CODE (t) == ZERO_EXTEND
6114 && (GET_CODE (XEXP (t, 0)) == PLUS
6115 || GET_CODE (XEXP (t, 0)) == MINUS
6116 || GET_CODE (XEXP (t, 0)) == IOR
6117 || GET_CODE (XEXP (t, 0)) == XOR
6118 || GET_CODE (XEXP (t, 0)) == ASHIFT
6119 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6120 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6121 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6122 && HWI_COMPUTABLE_MODE_P (mode)
6123 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6124 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6125 && ((nonzero_bits (f, GET_MODE (f))
6126 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6129 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6130 extend_op = ZERO_EXTEND;
6131 m = GET_MODE (XEXP (t, 0));
6133 else if (GET_CODE (t) == ZERO_EXTEND
6134 && (GET_CODE (XEXP (t, 0)) == PLUS
6135 || GET_CODE (XEXP (t, 0)) == IOR
6136 || GET_CODE (XEXP (t, 0)) == XOR)
6137 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6138 && HWI_COMPUTABLE_MODE_P (mode)
6139 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6140 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6141 && ((nonzero_bits (f, GET_MODE (f))
6142 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6145 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6146 extend_op = ZERO_EXTEND;
6147 m = GET_MODE (XEXP (t, 0));
6152 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6153 cond_op0, cond_op1),
6154 pc_rtx, pc_rtx, 0, 0, 0);
6155 temp = simplify_gen_binary (MULT, m, temp,
6156 simplify_gen_binary (MULT, m, c1,
6158 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6159 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6161 if (extend_op != UNKNOWN)
6162 temp = simplify_gen_unary (extend_op, mode, temp, m);
6168 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6169 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6170 negation of a single bit, we can convert this operation to a shift. We
6171 can actually do this more generally, but it doesn't seem worth it. */
6173 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6174 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6175 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6176 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6177 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6178 == GET_MODE_PRECISION (mode))
6179 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6181 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6182 gen_lowpart (mode, XEXP (cond, 0)), i);
6184 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6185 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6186 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6187 && GET_MODE (XEXP (cond, 0)) == mode
6188 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6189 == nonzero_bits (XEXP (cond, 0), mode)
6190 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6191 return XEXP (cond, 0);
6196 /* Simplify X, a SET expression. Return the new expression. */
6199 simplify_set (rtx x)
6201 rtx src = SET_SRC (x);
6202 rtx dest = SET_DEST (x);
6203 enum machine_mode mode
6204 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6208 /* (set (pc) (return)) gets written as (return). */
6209 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6212 /* Now that we know for sure which bits of SRC we are using, see if we can
6213 simplify the expression for the object knowing that we only need the
6216 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6218 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6219 SUBST (SET_SRC (x), src);
6222 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6223 the comparison result and try to simplify it unless we already have used
6224 undobuf.other_insn. */
6225 if ((GET_MODE_CLASS (mode) == MODE_CC
6226 || GET_CODE (src) == COMPARE
6228 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6229 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6230 && COMPARISON_P (*cc_use)
6231 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6233 enum rtx_code old_code = GET_CODE (*cc_use);
6234 enum rtx_code new_code;
6236 int other_changed = 0;
6237 rtx inner_compare = NULL_RTX;
6238 enum machine_mode compare_mode = GET_MODE (dest);
6240 if (GET_CODE (src) == COMPARE)
6242 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6243 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6245 inner_compare = op0;
6246 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6250 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6252 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6255 new_code = old_code;
6256 else if (!CONSTANT_P (tmp))
6258 new_code = GET_CODE (tmp);
6259 op0 = XEXP (tmp, 0);
6260 op1 = XEXP (tmp, 1);
6264 rtx pat = PATTERN (other_insn);
6265 undobuf.other_insn = other_insn;
6266 SUBST (*cc_use, tmp);
6268 /* Attempt to simplify CC user. */
6269 if (GET_CODE (pat) == SET)
6271 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6272 if (new_rtx != NULL_RTX)
6273 SUBST (SET_SRC (pat), new_rtx);
6276 /* Convert X into a no-op move. */
6277 SUBST (SET_DEST (x), pc_rtx);
6278 SUBST (SET_SRC (x), pc_rtx);
6282 /* Simplify our comparison, if possible. */
6283 new_code = simplify_comparison (new_code, &op0, &op1);
6285 #ifdef SELECT_CC_MODE
6286 /* If this machine has CC modes other than CCmode, check to see if we
6287 need to use a different CC mode here. */
6288 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6289 compare_mode = GET_MODE (op0);
6290 else if (inner_compare
6291 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6292 && new_code == old_code
6293 && op0 == XEXP (inner_compare, 0)
6294 && op1 == XEXP (inner_compare, 1))
6295 compare_mode = GET_MODE (inner_compare);
6297 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6300 /* If the mode changed, we have to change SET_DEST, the mode in the
6301 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6302 a hard register, just build new versions with the proper mode. If it
6303 is a pseudo, we lose unless it is only time we set the pseudo, in
6304 which case we can safely change its mode. */
6305 if (compare_mode != GET_MODE (dest))
6307 if (can_change_dest_mode (dest, 0, compare_mode))
6309 unsigned int regno = REGNO (dest);
6312 if (regno < FIRST_PSEUDO_REGISTER)
6313 new_dest = gen_rtx_REG (compare_mode, regno);
6316 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6317 new_dest = regno_reg_rtx[regno];
6320 SUBST (SET_DEST (x), new_dest);
6321 SUBST (XEXP (*cc_use, 0), new_dest);
6328 #endif /* SELECT_CC_MODE */
6330 /* If the code changed, we have to build a new comparison in
6331 undobuf.other_insn. */
6332 if (new_code != old_code)
6334 int other_changed_previously = other_changed;
6335 unsigned HOST_WIDE_INT mask;
6336 rtx old_cc_use = *cc_use;
6338 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6342 /* If the only change we made was to change an EQ into an NE or
6343 vice versa, OP0 has only one bit that might be nonzero, and OP1
6344 is zero, check if changing the user of the condition code will
6345 produce a valid insn. If it won't, we can keep the original code
6346 in that insn by surrounding our operation with an XOR. */
6348 if (((old_code == NE && new_code == EQ)
6349 || (old_code == EQ && new_code == NE))
6350 && ! other_changed_previously && op1 == const0_rtx
6351 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6352 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6354 rtx pat = PATTERN (other_insn), note = 0;
6356 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6357 && ! check_asm_operands (pat)))
6359 *cc_use = old_cc_use;
6362 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6363 op0, GEN_INT (mask));
6369 undobuf.other_insn = other_insn;
6371 /* Otherwise, if we didn't previously have a COMPARE in the
6372 correct mode, we need one. */
6373 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6375 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6378 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6380 SUBST (SET_SRC (x), op0);
6383 /* Otherwise, update the COMPARE if needed. */
6384 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6386 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6392 /* Get SET_SRC in a form where we have placed back any
6393 compound expressions. Then do the checks below. */
6394 src = make_compound_operation (src, SET);
6395 SUBST (SET_SRC (x), src);
6398 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6399 and X being a REG or (subreg (reg)), we may be able to convert this to
6400 (set (subreg:m2 x) (op)).
6402 We can always do this if M1 is narrower than M2 because that means that
6403 we only care about the low bits of the result.
6405 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6406 perform a narrower operation than requested since the high-order bits will
6407 be undefined. On machine where it is defined, this transformation is safe
6408 as long as M1 and M2 have the same number of words. */
6410 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6411 && !OBJECT_P (SUBREG_REG (src))
6412 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6414 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6415 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6416 #ifndef WORD_REGISTER_OPERATIONS
6417 && (GET_MODE_SIZE (GET_MODE (src))
6418 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6420 #ifdef CANNOT_CHANGE_MODE_CLASS
6421 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6422 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6423 GET_MODE (SUBREG_REG (src)),
6427 || (GET_CODE (dest) == SUBREG
6428 && REG_P (SUBREG_REG (dest)))))
6430 SUBST (SET_DEST (x),
6431 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6433 SUBST (SET_SRC (x), SUBREG_REG (src));
6435 src = SET_SRC (x), dest = SET_DEST (x);
6439 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6442 && GET_CODE (src) == SUBREG
6443 && subreg_lowpart_p (src)
6444 && (GET_MODE_PRECISION (GET_MODE (src))
6445 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6447 rtx inner = SUBREG_REG (src);
6448 enum machine_mode inner_mode = GET_MODE (inner);
6450 /* Here we make sure that we don't have a sign bit on. */
6451 if (val_signbit_known_clear_p (GET_MODE (src),
6452 nonzero_bits (inner, inner_mode)))
6454 SUBST (SET_SRC (x), inner);
6460 #ifdef LOAD_EXTEND_OP
6461 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6462 would require a paradoxical subreg. Replace the subreg with a
6463 zero_extend to avoid the reload that would otherwise be required. */
6465 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6466 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6467 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6468 && SUBREG_BYTE (src) == 0
6469 && paradoxical_subreg_p (src)
6470 && MEM_P (SUBREG_REG (src)))
6473 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6474 GET_MODE (src), SUBREG_REG (src)));
6480 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6481 are comparing an item known to be 0 or -1 against 0, use a logical
6482 operation instead. Check for one of the arms being an IOR of the other
6483 arm with some value. We compute three terms to be IOR'ed together. In
6484 practice, at most two will be nonzero. Then we do the IOR's. */
6486 if (GET_CODE (dest) != PC
6487 && GET_CODE (src) == IF_THEN_ELSE
6488 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6489 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6490 && XEXP (XEXP (src, 0), 1) == const0_rtx
6491 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6492 #ifdef HAVE_conditional_move
6493 && ! can_conditionally_move_p (GET_MODE (src))
6495 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6496 GET_MODE (XEXP (XEXP (src, 0), 0)))
6497 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6498 && ! side_effects_p (src))
6500 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6501 ? XEXP (src, 1) : XEXP (src, 2));
6502 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6503 ? XEXP (src, 2) : XEXP (src, 1));
6504 rtx term1 = const0_rtx, term2, term3;
6506 if (GET_CODE (true_rtx) == IOR
6507 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6508 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6509 else if (GET_CODE (true_rtx) == IOR
6510 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6511 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6512 else if (GET_CODE (false_rtx) == IOR
6513 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6514 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6515 else if (GET_CODE (false_rtx) == IOR
6516 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6517 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6519 term2 = simplify_gen_binary (AND, GET_MODE (src),
6520 XEXP (XEXP (src, 0), 0), true_rtx);
6521 term3 = simplify_gen_binary (AND, GET_MODE (src),
6522 simplify_gen_unary (NOT, GET_MODE (src),
6523 XEXP (XEXP (src, 0), 0),
6528 simplify_gen_binary (IOR, GET_MODE (src),
6529 simplify_gen_binary (IOR, GET_MODE (src),
6536 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6537 whole thing fail. */
6538 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6540 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6543 /* Convert this into a field assignment operation, if possible. */
6544 return make_field_assignment (x);
6547 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6551 simplify_logical (rtx x)
6553 enum machine_mode mode = GET_MODE (x);
6554 rtx op0 = XEXP (x, 0);
6555 rtx op1 = XEXP (x, 1);
6557 switch (GET_CODE (x))
6560 /* We can call simplify_and_const_int only if we don't lose
6561 any (sign) bits when converting INTVAL (op1) to
6562 "unsigned HOST_WIDE_INT". */
6563 if (CONST_INT_P (op1)
6564 && (HWI_COMPUTABLE_MODE_P (mode)
6565 || INTVAL (op1) > 0))
6567 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6568 if (GET_CODE (x) != AND)
6575 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6576 apply the distributive law and then the inverse distributive
6577 law to see if things simplify. */
6578 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6580 rtx result = distribute_and_simplify_rtx (x, 0);
6584 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6586 rtx result = distribute_and_simplify_rtx (x, 1);
6593 /* If we have (ior (and A B) C), apply the distributive law and then
6594 the inverse distributive law to see if things simplify. */
6596 if (GET_CODE (op0) == AND)
6598 rtx result = distribute_and_simplify_rtx (x, 0);
6603 if (GET_CODE (op1) == AND)
6605 rtx result = distribute_and_simplify_rtx (x, 1);
6618 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6619 operations" because they can be replaced with two more basic operations.
6620 ZERO_EXTEND is also considered "compound" because it can be replaced with
6621 an AND operation, which is simpler, though only one operation.
6623 The function expand_compound_operation is called with an rtx expression
6624 and will convert it to the appropriate shifts and AND operations,
6625 simplifying at each stage.
6627 The function make_compound_operation is called to convert an expression
6628 consisting of shifts and ANDs into the equivalent compound expression.
6629 It is the inverse of this function, loosely speaking. */
6632 expand_compound_operation (rtx x)
6634 unsigned HOST_WIDE_INT pos = 0, len;
6636 unsigned int modewidth;
6639 switch (GET_CODE (x))
6644 /* We can't necessarily use a const_int for a multiword mode;
6645 it depends on implicitly extending the value.
6646 Since we don't know the right way to extend it,
6647 we can't tell whether the implicit way is right.
6649 Even for a mode that is no wider than a const_int,
6650 we can't win, because we need to sign extend one of its bits through
6651 the rest of it, and we don't know which bit. */
6652 if (CONST_INT_P (XEXP (x, 0)))
6655 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6656 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6657 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6658 reloaded. If not for that, MEM's would very rarely be safe.
6660 Reject MODEs bigger than a word, because we might not be able
6661 to reference a two-register group starting with an arbitrary register
6662 (and currently gen_lowpart might crash for a SUBREG). */
6664 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6667 /* Reject MODEs that aren't scalar integers because turning vector
6668 or complex modes into shifts causes problems. */
6670 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6673 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6674 /* If the inner object has VOIDmode (the only way this can happen
6675 is if it is an ASM_OPERANDS), we can't do anything since we don't
6676 know how much masking to do. */
6685 /* ... fall through ... */
6688 /* If the operand is a CLOBBER, just return it. */
6689 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6692 if (!CONST_INT_P (XEXP (x, 1))
6693 || !CONST_INT_P (XEXP (x, 2))
6694 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6697 /* Reject MODEs that aren't scalar integers because turning vector
6698 or complex modes into shifts causes problems. */
6700 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6703 len = INTVAL (XEXP (x, 1));
6704 pos = INTVAL (XEXP (x, 2));
6706 /* This should stay within the object being extracted, fail otherwise. */
6707 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6710 if (BITS_BIG_ENDIAN)
6711 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6718 /* Convert sign extension to zero extension, if we know that the high
6719 bit is not set, as this is easier to optimize. It will be converted
6720 back to cheaper alternative in make_extraction. */
6721 if (GET_CODE (x) == SIGN_EXTEND
6722 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6723 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6724 & ~(((unsigned HOST_WIDE_INT)
6725 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6729 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6730 rtx temp2 = expand_compound_operation (temp);
6732 /* Make sure this is a profitable operation. */
6733 if (set_src_cost (x, optimize_this_for_speed_p)
6734 > set_src_cost (temp2, optimize_this_for_speed_p))
6736 else if (set_src_cost (x, optimize_this_for_speed_p)
6737 > set_src_cost (temp, optimize_this_for_speed_p))
6743 /* We can optimize some special cases of ZERO_EXTEND. */
6744 if (GET_CODE (x) == ZERO_EXTEND)
6746 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6747 know that the last value didn't have any inappropriate bits
6749 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6750 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6751 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6752 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6753 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6754 return XEXP (XEXP (x, 0), 0);
6756 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6757 if (GET_CODE (XEXP (x, 0)) == SUBREG
6758 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6759 && subreg_lowpart_p (XEXP (x, 0))
6760 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6761 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6762 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6763 return SUBREG_REG (XEXP (x, 0));
6765 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6766 is a comparison and STORE_FLAG_VALUE permits. This is like
6767 the first case, but it works even when GET_MODE (x) is larger
6768 than HOST_WIDE_INT. */
6769 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6770 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6771 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6772 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6773 <= HOST_BITS_PER_WIDE_INT)
6774 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6775 return XEXP (XEXP (x, 0), 0);
6777 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6778 if (GET_CODE (XEXP (x, 0)) == SUBREG
6779 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6780 && subreg_lowpart_p (XEXP (x, 0))
6781 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6782 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6783 <= HOST_BITS_PER_WIDE_INT)
6784 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6785 return SUBREG_REG (XEXP (x, 0));
6789 /* If we reach here, we want to return a pair of shifts. The inner
6790 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6791 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6792 logical depending on the value of UNSIGNEDP.
6794 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6795 converted into an AND of a shift.
6797 We must check for the case where the left shift would have a negative
6798 count. This can happen in a case like (x >> 31) & 255 on machines
6799 that can't shift by a constant. On those machines, we would first
6800 combine the shift with the AND to produce a variable-position
6801 extraction. Then the constant of 31 would be substituted in
6802 to produce such a position. */
6804 modewidth = GET_MODE_PRECISION (GET_MODE (x));
6805 if (modewidth >= pos + len)
6807 enum machine_mode mode = GET_MODE (x);
6808 tem = gen_lowpart (mode, XEXP (x, 0));
6809 if (!tem || GET_CODE (tem) == CLOBBER)
6811 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6812 tem, modewidth - pos - len);
6813 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6814 mode, tem, modewidth - len);
6816 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6817 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6818 simplify_shift_const (NULL_RTX, LSHIFTRT,
6821 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6823 /* Any other cases we can't handle. */
6826 /* If we couldn't do this for some reason, return the original
6828 if (GET_CODE (tem) == CLOBBER)
6834 /* X is a SET which contains an assignment of one object into
6835 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6836 or certain SUBREGS). If possible, convert it into a series of
6839 We half-heartedly support variable positions, but do not at all
6840 support variable lengths. */
6843 expand_field_assignment (const_rtx x)
6846 rtx pos; /* Always counts from low bit. */
6848 rtx mask, cleared, masked;
6849 enum machine_mode compute_mode;
6851 /* Loop until we find something we can't simplify. */
6854 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6855 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6857 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6858 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6859 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6861 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6862 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6864 inner = XEXP (SET_DEST (x), 0);
6865 len = INTVAL (XEXP (SET_DEST (x), 1));
6866 pos = XEXP (SET_DEST (x), 2);
6868 /* A constant position should stay within the width of INNER. */
6869 if (CONST_INT_P (pos)
6870 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6873 if (BITS_BIG_ENDIAN)
6875 if (CONST_INT_P (pos))
6876 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6878 else if (GET_CODE (pos) == MINUS
6879 && CONST_INT_P (XEXP (pos, 1))
6880 && (INTVAL (XEXP (pos, 1))
6881 == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6882 /* If position is ADJUST - X, new position is X. */
6883 pos = XEXP (pos, 0);
6885 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6886 GEN_INT (GET_MODE_PRECISION (
6893 /* A SUBREG between two modes that occupy the same numbers of words
6894 can be done by moving the SUBREG to the source. */
6895 else if (GET_CODE (SET_DEST (x)) == SUBREG
6896 /* We need SUBREGs to compute nonzero_bits properly. */
6897 && nonzero_sign_valid
6898 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6899 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6900 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6901 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6903 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6905 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6912 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6913 inner = SUBREG_REG (inner);
6915 compute_mode = GET_MODE (inner);
6917 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6918 if (! SCALAR_INT_MODE_P (compute_mode))
6920 enum machine_mode imode;
6922 /* Don't do anything for vector or complex integral types. */
6923 if (! FLOAT_MODE_P (compute_mode))
6926 /* Try to find an integral mode to pun with. */
6927 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6928 if (imode == BLKmode)
6931 compute_mode = imode;
6932 inner = gen_lowpart (imode, inner);
6935 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6936 if (len >= HOST_BITS_PER_WIDE_INT)
6939 /* Now compute the equivalent expression. Make a copy of INNER
6940 for the SET_DEST in case it is a MEM into which we will substitute;
6941 we don't want shared RTL in that case. */
6942 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6943 cleared = simplify_gen_binary (AND, compute_mode,
6944 simplify_gen_unary (NOT, compute_mode,
6945 simplify_gen_binary (ASHIFT,
6950 masked = simplify_gen_binary (ASHIFT, compute_mode,
6951 simplify_gen_binary (
6953 gen_lowpart (compute_mode, SET_SRC (x)),
6957 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6958 simplify_gen_binary (IOR, compute_mode,
6965 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6966 it is an RTX that represents the (variable) starting position; otherwise,
6967 POS is the (constant) starting bit position. Both are counted from the LSB.
6969 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6971 IN_DEST is nonzero if this is a reference in the destination of a SET.
6972 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6973 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6976 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6977 ZERO_EXTRACT should be built even for bits starting at bit 0.
6979 MODE is the desired mode of the result (if IN_DEST == 0).
6981 The result is an RTX for the extraction or NULL_RTX if the target
6985 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6986 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6987 int in_dest, int in_compare)
6989 /* This mode describes the size of the storage area
6990 to fetch the overall value from. Within that, we
6991 ignore the POS lowest bits, etc. */
6992 enum machine_mode is_mode = GET_MODE (inner);
6993 enum machine_mode inner_mode;
6994 enum machine_mode wanted_inner_mode;
6995 enum machine_mode wanted_inner_reg_mode = word_mode;
6996 enum machine_mode pos_mode = word_mode;
6997 enum machine_mode extraction_mode = word_mode;
6998 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7000 rtx orig_pos_rtx = pos_rtx;
7001 HOST_WIDE_INT orig_pos;
7003 if (pos_rtx && CONST_INT_P (pos_rtx))
7004 pos = INTVAL (pos_rtx), pos_rtx = 0;
7006 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7008 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7009 consider just the QI as the memory to extract from.
7010 The subreg adds or removes high bits; its mode is
7011 irrelevant to the meaning of this extraction,
7012 since POS and LEN count from the lsb. */
7013 if (MEM_P (SUBREG_REG (inner)))
7014 is_mode = GET_MODE (SUBREG_REG (inner));
7015 inner = SUBREG_REG (inner);
7017 else if (GET_CODE (inner) == ASHIFT
7018 && CONST_INT_P (XEXP (inner, 1))
7019 && pos_rtx == 0 && pos == 0
7020 && len > UINTVAL (XEXP (inner, 1)))
7022 /* We're extracting the least significant bits of an rtx
7023 (ashift X (const_int C)), where LEN > C. Extract the
7024 least significant (LEN - C) bits of X, giving an rtx
7025 whose mode is MODE, then shift it left C times. */
7026 new_rtx = make_extraction (mode, XEXP (inner, 0),
7027 0, 0, len - INTVAL (XEXP (inner, 1)),
7028 unsignedp, in_dest, in_compare);
7030 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7032 else if (GET_CODE (inner) == TRUNCATE)
7033 inner = XEXP (inner, 0);
7035 inner_mode = GET_MODE (inner);
7037 /* See if this can be done without an extraction. We never can if the
7038 width of the field is not the same as that of some integer mode. For
7039 registers, we can only avoid the extraction if the position is at the
7040 low-order bit and this is either not in the destination or we have the
7041 appropriate STRICT_LOW_PART operation available.
7043 For MEM, we can avoid an extract if the field starts on an appropriate
7044 boundary and we can change the mode of the memory reference. */
7046 if (tmode != BLKmode
7047 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7049 && (inner_mode == tmode
7051 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7052 || reg_truncated_to_mode (tmode, inner))
7055 && have_insn_for (STRICT_LOW_PART, tmode))))
7056 || (MEM_P (inner) && pos_rtx == 0
7058 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7059 : BITS_PER_UNIT)) == 0
7060 /* We can't do this if we are widening INNER_MODE (it
7061 may not be aligned, for one thing). */
7062 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7063 && (inner_mode == tmode
7064 || (! mode_dependent_address_p (XEXP (inner, 0),
7065 MEM_ADDR_SPACE (inner))
7066 && ! MEM_VOLATILE_P (inner))))))
7068 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7069 field. If the original and current mode are the same, we need not
7070 adjust the offset. Otherwise, we do if bytes big endian.
7072 If INNER is not a MEM, get a piece consisting of just the field
7073 of interest (in this case POS % BITS_PER_WORD must be 0). */
7077 HOST_WIDE_INT offset;
7079 /* POS counts from lsb, but make OFFSET count in memory order. */
7080 if (BYTES_BIG_ENDIAN)
7081 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7083 offset = pos / BITS_PER_UNIT;
7085 new_rtx = adjust_address_nv (inner, tmode, offset);
7087 else if (REG_P (inner))
7089 if (tmode != inner_mode)
7091 /* We can't call gen_lowpart in a DEST since we
7092 always want a SUBREG (see below) and it would sometimes
7093 return a new hard register. */
7096 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7098 if (WORDS_BIG_ENDIAN
7099 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7100 final_word = ((GET_MODE_SIZE (inner_mode)
7101 - GET_MODE_SIZE (tmode))
7102 / UNITS_PER_WORD) - final_word;
7104 final_word *= UNITS_PER_WORD;
7105 if (BYTES_BIG_ENDIAN &&
7106 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7107 final_word += (GET_MODE_SIZE (inner_mode)
7108 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7110 /* Avoid creating invalid subregs, for example when
7111 simplifying (x>>32)&255. */
7112 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7115 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7118 new_rtx = gen_lowpart (tmode, inner);
7124 new_rtx = force_to_mode (inner, tmode,
7125 len >= HOST_BITS_PER_WIDE_INT
7126 ? ~(unsigned HOST_WIDE_INT) 0
7127 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7130 /* If this extraction is going into the destination of a SET,
7131 make a STRICT_LOW_PART unless we made a MEM. */
7134 return (MEM_P (new_rtx) ? new_rtx
7135 : (GET_CODE (new_rtx) != SUBREG
7136 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7137 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7142 if (CONST_SCALAR_INT_P (new_rtx))
7143 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7144 mode, new_rtx, tmode);
7146 /* If we know that no extraneous bits are set, and that the high
7147 bit is not set, convert the extraction to the cheaper of
7148 sign and zero extension, that are equivalent in these cases. */
7149 if (flag_expensive_optimizations
7150 && (HWI_COMPUTABLE_MODE_P (tmode)
7151 && ((nonzero_bits (new_rtx, tmode)
7152 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7155 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7156 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7158 /* Prefer ZERO_EXTENSION, since it gives more information to
7160 if (set_src_cost (temp, optimize_this_for_speed_p)
7161 <= set_src_cost (temp1, optimize_this_for_speed_p))
7166 /* Otherwise, sign- or zero-extend unless we already are in the
7169 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7173 /* Unless this is a COMPARE or we have a funny memory reference,
7174 don't do anything with zero-extending field extracts starting at
7175 the low-order bit since they are simple AND operations. */
7176 if (pos_rtx == 0 && pos == 0 && ! in_dest
7177 && ! in_compare && unsignedp)
7180 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7181 if the position is not a constant and the length is not 1. In all
7182 other cases, we would only be going outside our object in cases when
7183 an original shift would have been undefined. */
7185 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7186 || (pos_rtx != 0 && len != 1)))
7189 enum extraction_pattern pattern = (in_dest ? EP_insv
7190 : unsignedp ? EP_extzv : EP_extv);
7192 /* If INNER is not from memory, we want it to have the mode of a register
7193 extraction pattern's structure operand, or word_mode if there is no
7194 such pattern. The same applies to extraction_mode and pos_mode
7195 and their respective operands.
7197 For memory, assume that the desired extraction_mode and pos_mode
7198 are the same as for a register operation, since at present we don't
7199 have named patterns for aligned memory structures. */
7200 struct extraction_insn insn;
7201 if (get_best_reg_extraction_insn (&insn, pattern,
7202 GET_MODE_BITSIZE (inner_mode), mode))
7204 wanted_inner_reg_mode = insn.struct_mode;
7205 pos_mode = insn.pos_mode;
7206 extraction_mode = insn.field_mode;
7209 /* Never narrow an object, since that might not be safe. */
7211 if (mode != VOIDmode
7212 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7213 extraction_mode = mode;
7216 wanted_inner_mode = wanted_inner_reg_mode;
7219 /* Be careful not to go beyond the extracted object and maintain the
7220 natural alignment of the memory. */
7221 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7222 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7223 > GET_MODE_BITSIZE (wanted_inner_mode))
7225 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7226 gcc_assert (wanted_inner_mode != VOIDmode);
7232 if (BITS_BIG_ENDIAN)
7234 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7235 BITS_BIG_ENDIAN style. If position is constant, compute new
7236 position. Otherwise, build subtraction.
7237 Note that POS is relative to the mode of the original argument.
7238 If it's a MEM we need to recompute POS relative to that.
7239 However, if we're extracting from (or inserting into) a register,
7240 we want to recompute POS relative to wanted_inner_mode. */
7241 int width = (MEM_P (inner)
7242 ? GET_MODE_BITSIZE (is_mode)
7243 : GET_MODE_BITSIZE (wanted_inner_mode));
7246 pos = width - len - pos;
7249 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7250 /* POS may be less than 0 now, but we check for that below.
7251 Note that it can only be less than 0 if !MEM_P (inner). */
7254 /* If INNER has a wider mode, and this is a constant extraction, try to
7255 make it smaller and adjust the byte to point to the byte containing
7257 if (wanted_inner_mode != VOIDmode
7258 && inner_mode != wanted_inner_mode
7260 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7262 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7263 && ! MEM_VOLATILE_P (inner))
7267 /* The computations below will be correct if the machine is big
7268 endian in both bits and bytes or little endian in bits and bytes.
7269 If it is mixed, we must adjust. */
7271 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7272 adjust OFFSET to compensate. */
7273 if (BYTES_BIG_ENDIAN
7274 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7275 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7277 /* We can now move to the desired byte. */
7278 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7279 * GET_MODE_SIZE (wanted_inner_mode);
7280 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7282 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7283 && is_mode != wanted_inner_mode)
7284 offset = (GET_MODE_SIZE (is_mode)
7285 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7287 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7290 /* If INNER is not memory, get it into the proper mode. If we are changing
7291 its mode, POS must be a constant and smaller than the size of the new
7293 else if (!MEM_P (inner))
7295 /* On the LHS, don't create paradoxical subregs implicitely truncating
7296 the register unless TRULY_NOOP_TRUNCATION. */
7298 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7302 if (GET_MODE (inner) != wanted_inner_mode
7304 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7310 inner = force_to_mode (inner, wanted_inner_mode,
7312 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7313 ? ~(unsigned HOST_WIDE_INT) 0
7314 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7319 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7320 have to zero extend. Otherwise, we can just use a SUBREG. */
7322 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7324 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7326 /* If we know that no extraneous bits are set, and that the high
7327 bit is not set, convert extraction to cheaper one - either
7328 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7330 if (flag_expensive_optimizations
7331 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7332 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7333 & ~(((unsigned HOST_WIDE_INT)
7334 GET_MODE_MASK (GET_MODE (pos_rtx)))
7338 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7340 /* Prefer ZERO_EXTENSION, since it gives more information to
7342 if (set_src_cost (temp1, optimize_this_for_speed_p)
7343 < set_src_cost (temp, optimize_this_for_speed_p))
7349 /* Make POS_RTX unless we already have it and it is correct. If we don't
7350 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7352 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7353 pos_rtx = orig_pos_rtx;
7355 else if (pos_rtx == 0)
7356 pos_rtx = GEN_INT (pos);
7358 /* Make the required operation. See if we can use existing rtx. */
7359 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7360 extraction_mode, inner, GEN_INT (len), pos_rtx);
7362 new_rtx = gen_lowpart (mode, new_rtx);
7367 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7368 with any other operations in X. Return X without that shift if so. */
7371 extract_left_shift (rtx x, int count)
7373 enum rtx_code code = GET_CODE (x);
7374 enum machine_mode mode = GET_MODE (x);
7380 /* This is the shift itself. If it is wide enough, we will return
7381 either the value being shifted if the shift count is equal to
7382 COUNT or a shift for the difference. */
7383 if (CONST_INT_P (XEXP (x, 1))
7384 && INTVAL (XEXP (x, 1)) >= count)
7385 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7386 INTVAL (XEXP (x, 1)) - count);
7390 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7391 return simplify_gen_unary (code, mode, tem, mode);
7395 case PLUS: case IOR: case XOR: case AND:
7396 /* If we can safely shift this constant and we find the inner shift,
7397 make a new operation. */
7398 if (CONST_INT_P (XEXP (x, 1))
7399 && (UINTVAL (XEXP (x, 1))
7400 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7401 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7402 return simplify_gen_binary (code, mode, tem,
7403 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7414 /* Look at the expression rooted at X. Look for expressions
7415 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7416 Form these expressions.
7418 Return the new rtx, usually just X.
7420 Also, for machines like the VAX that don't have logical shift insns,
7421 try to convert logical to arithmetic shift operations in cases where
7422 they are equivalent. This undoes the canonicalizations to logical
7423 shifts done elsewhere.
7425 We try, as much as possible, to re-use rtl expressions to save memory.
7427 IN_CODE says what kind of expression we are processing. Normally, it is
7428 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7429 being kludges), it is MEM. When processing the arguments of a comparison
7430 or a COMPARE against zero, it is COMPARE. */
7433 make_compound_operation (rtx x, enum rtx_code in_code)
7435 enum rtx_code code = GET_CODE (x);
7436 enum machine_mode mode = GET_MODE (x);
7437 int mode_width = GET_MODE_PRECISION (mode);
7439 enum rtx_code next_code;
7445 /* Select the code to be used in recursive calls. Once we are inside an
7446 address, we stay there. If we have a comparison, set to COMPARE,
7447 but once inside, go back to our default of SET. */
7449 next_code = (code == MEM ? MEM
7450 : ((code == PLUS || code == MINUS)
7451 && SCALAR_INT_MODE_P (mode)) ? MEM
7452 : ((code == COMPARE || COMPARISON_P (x))
7453 && XEXP (x, 1) == const0_rtx) ? COMPARE
7454 : in_code == COMPARE ? SET : in_code);
7456 /* Process depending on the code of this operation. If NEW is set
7457 nonzero, it will be returned. */
7462 /* Convert shifts by constants into multiplications if inside
7464 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7465 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7466 && INTVAL (XEXP (x, 1)) >= 0
7467 && SCALAR_INT_MODE_P (mode))
7469 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7470 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7472 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7473 if (GET_CODE (new_rtx) == NEG)
7475 new_rtx = XEXP (new_rtx, 0);
7478 multval = trunc_int_for_mode (multval, mode);
7479 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7486 lhs = make_compound_operation (lhs, next_code);
7487 rhs = make_compound_operation (rhs, next_code);
7488 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7489 && SCALAR_INT_MODE_P (mode))
7491 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7493 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7495 else if (GET_CODE (lhs) == MULT
7496 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7498 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7499 simplify_gen_unary (NEG, mode,
7502 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7506 SUBST (XEXP (x, 0), lhs);
7507 SUBST (XEXP (x, 1), rhs);
7510 x = gen_lowpart (mode, new_rtx);
7516 lhs = make_compound_operation (lhs, next_code);
7517 rhs = make_compound_operation (rhs, next_code);
7518 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7519 && SCALAR_INT_MODE_P (mode))
7521 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7523 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7525 else if (GET_CODE (rhs) == MULT
7526 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7528 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7529 simplify_gen_unary (NEG, mode,
7532 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7536 SUBST (XEXP (x, 0), lhs);
7537 SUBST (XEXP (x, 1), rhs);
7540 return gen_lowpart (mode, new_rtx);
7543 /* If the second operand is not a constant, we can't do anything
7545 if (!CONST_INT_P (XEXP (x, 1)))
7548 /* If the constant is a power of two minus one and the first operand
7549 is a logical right shift, make an extraction. */
7550 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7551 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7553 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7554 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7555 0, in_code == COMPARE);
7558 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7559 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7560 && subreg_lowpart_p (XEXP (x, 0))
7561 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7562 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7564 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7566 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7567 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7568 0, in_code == COMPARE);
7570 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7571 else if ((GET_CODE (XEXP (x, 0)) == XOR
7572 || GET_CODE (XEXP (x, 0)) == IOR)
7573 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7574 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7575 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7577 /* Apply the distributive law, and then try to make extractions. */
7578 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7579 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7581 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7583 new_rtx = make_compound_operation (new_rtx, in_code);
7586 /* If we are have (and (rotate X C) M) and C is larger than the number
7587 of bits in M, this is an extraction. */
7589 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7590 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7591 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7592 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7594 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7595 new_rtx = make_extraction (mode, new_rtx,
7596 (GET_MODE_PRECISION (mode)
7597 - INTVAL (XEXP (XEXP (x, 0), 1))),
7598 NULL_RTX, i, 1, 0, in_code == COMPARE);
7601 /* On machines without logical shifts, if the operand of the AND is
7602 a logical shift and our mask turns off all the propagated sign
7603 bits, we can replace the logical shift with an arithmetic shift. */
7604 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7605 && !have_insn_for (LSHIFTRT, mode)
7606 && have_insn_for (ASHIFTRT, mode)
7607 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7608 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7609 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7610 && mode_width <= HOST_BITS_PER_WIDE_INT)
7612 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7614 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7615 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7617 gen_rtx_ASHIFTRT (mode,
7618 make_compound_operation
7619 (XEXP (XEXP (x, 0), 0), next_code),
7620 XEXP (XEXP (x, 0), 1)));
7623 /* If the constant is one less than a power of two, this might be
7624 representable by an extraction even if no shift is present.
7625 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7626 we are in a COMPARE. */
7627 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7628 new_rtx = make_extraction (mode,
7629 make_compound_operation (XEXP (x, 0),
7631 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7633 /* If we are in a comparison and this is an AND with a power of two,
7634 convert this into the appropriate bit extract. */
7635 else if (in_code == COMPARE
7636 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7637 new_rtx = make_extraction (mode,
7638 make_compound_operation (XEXP (x, 0),
7640 i, NULL_RTX, 1, 1, 0, 1);
7645 /* If the sign bit is known to be zero, replace this with an
7646 arithmetic shift. */
7647 if (have_insn_for (ASHIFTRT, mode)
7648 && ! have_insn_for (LSHIFTRT, mode)
7649 && mode_width <= HOST_BITS_PER_WIDE_INT
7650 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7652 new_rtx = gen_rtx_ASHIFTRT (mode,
7653 make_compound_operation (XEXP (x, 0),
7659 /* ... fall through ... */
7665 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7666 this is a SIGN_EXTRACT. */
7667 if (CONST_INT_P (rhs)
7668 && GET_CODE (lhs) == ASHIFT
7669 && CONST_INT_P (XEXP (lhs, 1))
7670 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7671 && INTVAL (XEXP (lhs, 1)) >= 0
7672 && INTVAL (rhs) < mode_width)
7674 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7675 new_rtx = make_extraction (mode, new_rtx,
7676 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7677 NULL_RTX, mode_width - INTVAL (rhs),
7678 code == LSHIFTRT, 0, in_code == COMPARE);
7682 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7683 If so, try to merge the shifts into a SIGN_EXTEND. We could
7684 also do this for some cases of SIGN_EXTRACT, but it doesn't
7685 seem worth the effort; the case checked for occurs on Alpha. */
7688 && ! (GET_CODE (lhs) == SUBREG
7689 && (OBJECT_P (SUBREG_REG (lhs))))
7690 && CONST_INT_P (rhs)
7691 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7692 && INTVAL (rhs) < mode_width
7693 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7694 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7695 0, NULL_RTX, mode_width - INTVAL (rhs),
7696 code == LSHIFTRT, 0, in_code == COMPARE);
7701 /* Call ourselves recursively on the inner expression. If we are
7702 narrowing the object and it has a different RTL code from
7703 what it originally did, do this SUBREG as a force_to_mode. */
7705 rtx inner = SUBREG_REG (x), simplified;
7706 enum rtx_code subreg_code = in_code;
7708 /* If in_code is COMPARE, it isn't always safe to pass it through
7709 to the recursive make_compound_operation call. */
7710 if (subreg_code == COMPARE
7711 && (!subreg_lowpart_p (x)
7712 || GET_CODE (inner) == SUBREG
7713 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7714 is (const_int 0), rather than
7715 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7716 || (GET_CODE (inner) == AND
7717 && CONST_INT_P (XEXP (inner, 1))
7718 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7719 && exact_log2 (UINTVAL (XEXP (inner, 1)))
7720 >= GET_MODE_BITSIZE (mode))))
7723 tem = make_compound_operation (inner, subreg_code);
7726 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7730 if (GET_CODE (tem) != GET_CODE (inner)
7731 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7732 && subreg_lowpart_p (x))
7735 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7737 /* If we have something other than a SUBREG, we might have
7738 done an expansion, so rerun ourselves. */
7739 if (GET_CODE (newer) != SUBREG)
7740 newer = make_compound_operation (newer, in_code);
7742 /* force_to_mode can expand compounds. If it just re-expanded the
7743 compound, use gen_lowpart to convert to the desired mode. */
7744 if (rtx_equal_p (newer, x)
7745 /* Likewise if it re-expanded the compound only partially.
7746 This happens for SUBREG of ZERO_EXTRACT if they extract
7747 the same number of bits. */
7748 || (GET_CODE (newer) == SUBREG
7749 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7750 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7751 && GET_CODE (inner) == AND
7752 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7753 return gen_lowpart (GET_MODE (x), tem);
7769 x = gen_lowpart (mode, new_rtx);
7770 code = GET_CODE (x);
7773 /* Now recursively process each operand of this operation. We need to
7774 handle ZERO_EXTEND specially so that we don't lose track of the
7776 if (GET_CODE (x) == ZERO_EXTEND)
7778 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7779 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7780 new_rtx, GET_MODE (XEXP (x, 0)));
7783 SUBST (XEXP (x, 0), new_rtx);
7787 fmt = GET_RTX_FORMAT (code);
7788 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7791 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7792 SUBST (XEXP (x, i), new_rtx);
7794 else if (fmt[i] == 'E')
7795 for (j = 0; j < XVECLEN (x, i); j++)
7797 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7798 SUBST (XVECEXP (x, i, j), new_rtx);
7802 /* If this is a commutative operation, the changes to the operands
7803 may have made it noncanonical. */
7804 if (COMMUTATIVE_ARITH_P (x)
7805 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7808 SUBST (XEXP (x, 0), XEXP (x, 1));
7809 SUBST (XEXP (x, 1), tem);
7815 /* Given M see if it is a value that would select a field of bits
7816 within an item, but not the entire word. Return -1 if not.
7817 Otherwise, return the starting position of the field, where 0 is the
7820 *PLEN is set to the length of the field. */
7823 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7825 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7826 int pos = m ? ctz_hwi (m) : -1;
7830 /* Now shift off the low-order zero bits and see if we have a
7831 power of two minus 1. */
7832 len = exact_log2 ((m >> pos) + 1);
7841 /* If X refers to a register that equals REG in value, replace these
7842 references with REG. */
7844 canon_reg_for_combine (rtx x, rtx reg)
7851 enum rtx_code code = GET_CODE (x);
7852 switch (GET_RTX_CLASS (code))
7855 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7856 if (op0 != XEXP (x, 0))
7857 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7862 case RTX_COMM_ARITH:
7863 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7864 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7865 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7866 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7870 case RTX_COMM_COMPARE:
7871 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7872 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7873 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7874 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7875 GET_MODE (op0), op0, op1);
7879 case RTX_BITFIELD_OPS:
7880 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7881 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7882 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7883 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7884 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7885 GET_MODE (op0), op0, op1, op2);
7890 if (rtx_equal_p (get_last_value (reg), x)
7891 || rtx_equal_p (reg, get_last_value (x)))
7900 fmt = GET_RTX_FORMAT (code);
7902 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7905 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7906 if (op != XEXP (x, i))
7916 else if (fmt[i] == 'E')
7919 for (j = 0; j < XVECLEN (x, i); j++)
7921 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7922 if (op != XVECEXP (x, i, j))
7929 XVECEXP (x, i, j) = op;
7940 /* Return X converted to MODE. If the value is already truncated to
7941 MODE we can just return a subreg even though in the general case we
7942 would need an explicit truncation. */
7945 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7947 if (!CONST_INT_P (x)
7948 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7949 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7950 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7952 /* Bit-cast X into an integer mode. */
7953 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7954 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7955 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7959 return gen_lowpart (mode, x);
7962 /* See if X can be simplified knowing that we will only refer to it in
7963 MODE and will only refer to those bits that are nonzero in MASK.
7964 If other bits are being computed or if masking operations are done
7965 that select a superset of the bits in MASK, they can sometimes be
7968 Return a possibly simplified expression, but always convert X to
7969 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7971 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7972 are all off in X. This is used when X will be complemented, by either
7973 NOT, NEG, or XOR. */
7976 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7979 enum rtx_code code = GET_CODE (x);
7980 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7981 enum machine_mode op_mode;
7982 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7985 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7986 code below will do the wrong thing since the mode of such an
7987 expression is VOIDmode.
7989 Also do nothing if X is a CLOBBER; this can happen if X was
7990 the return value from a call to gen_lowpart. */
7991 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7994 /* We want to perform the operation is its present mode unless we know
7995 that the operation is valid in MODE, in which case we do the operation
7997 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7998 && have_insn_for (code, mode))
7999 ? mode : GET_MODE (x));
8001 /* It is not valid to do a right-shift in a narrower mode
8002 than the one it came in with. */
8003 if ((code == LSHIFTRT || code == ASHIFTRT)
8004 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8005 op_mode = GET_MODE (x);
8007 /* Truncate MASK to fit OP_MODE. */
8009 mask &= GET_MODE_MASK (op_mode);
8011 /* When we have an arithmetic operation, or a shift whose count we
8012 do not know, we need to assume that all bits up to the highest-order
8013 bit in MASK will be needed. This is how we form such a mask. */
8014 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8015 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8017 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8020 /* Determine what bits of X are guaranteed to be (non)zero. */
8021 nonzero = nonzero_bits (x, mode);
8023 /* If none of the bits in X are needed, return a zero. */
8024 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8027 /* If X is a CONST_INT, return a new one. Do this here since the
8028 test below will fail. */
8029 if (CONST_INT_P (x))
8031 if (SCALAR_INT_MODE_P (mode))
8032 return gen_int_mode (INTVAL (x) & mask, mode);
8035 x = GEN_INT (INTVAL (x) & mask);
8036 return gen_lowpart_common (mode, x);
8040 /* If X is narrower than MODE and we want all the bits in X's mode, just
8041 get X in the proper mode. */
8042 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8043 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8044 return gen_lowpart (mode, x);
8046 /* We can ignore the effect of a SUBREG if it narrows the mode or
8047 if the constant masks to zero all the bits the mode doesn't have. */
8048 if (GET_CODE (x) == SUBREG
8049 && subreg_lowpart_p (x)
8050 && ((GET_MODE_SIZE (GET_MODE (x))
8051 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8053 & GET_MODE_MASK (GET_MODE (x))
8054 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8055 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8057 /* The arithmetic simplifications here only work for scalar integer modes. */
8058 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8059 return gen_lowpart_or_truncate (mode, x);
8064 /* If X is a (clobber (const_int)), return it since we know we are
8065 generating something that won't match. */
8072 x = expand_compound_operation (x);
8073 if (GET_CODE (x) != code)
8074 return force_to_mode (x, mode, mask, next_select);
8078 /* Similarly for a truncate. */
8079 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8082 /* If this is an AND with a constant, convert it into an AND
8083 whose constant is the AND of that constant with MASK. If it
8084 remains an AND of MASK, delete it since it is redundant. */
8086 if (CONST_INT_P (XEXP (x, 1)))
8088 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8089 mask & INTVAL (XEXP (x, 1)));
8091 /* If X is still an AND, see if it is an AND with a mask that
8092 is just some low-order bits. If so, and it is MASK, we don't
8095 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8096 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8100 /* If it remains an AND, try making another AND with the bits
8101 in the mode mask that aren't in MASK turned on. If the
8102 constant in the AND is wide enough, this might make a
8103 cheaper constant. */
8105 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8106 && GET_MODE_MASK (GET_MODE (x)) != mask
8107 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8109 unsigned HOST_WIDE_INT cval
8110 = UINTVAL (XEXP (x, 1))
8111 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8112 int width = GET_MODE_PRECISION (GET_MODE (x));
8115 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8116 number, sign extend it. */
8117 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8118 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8119 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8121 y = simplify_gen_binary (AND, GET_MODE (x),
8122 XEXP (x, 0), GEN_INT (cval));
8123 if (set_src_cost (y, optimize_this_for_speed_p)
8124 < set_src_cost (x, optimize_this_for_speed_p))
8134 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8135 low-order bits (as in an alignment operation) and FOO is already
8136 aligned to that boundary, mask C1 to that boundary as well.
8137 This may eliminate that PLUS and, later, the AND. */
8140 unsigned int width = GET_MODE_PRECISION (mode);
8141 unsigned HOST_WIDE_INT smask = mask;
8143 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8144 number, sign extend it. */
8146 if (width < HOST_BITS_PER_WIDE_INT
8147 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8148 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8150 if (CONST_INT_P (XEXP (x, 1))
8151 && exact_log2 (- smask) >= 0
8152 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8153 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8154 return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8155 (INTVAL (XEXP (x, 1)) & smask)),
8156 mode, smask, next_select);
8159 /* ... fall through ... */
8162 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8163 most significant bit in MASK since carries from those bits will
8164 affect the bits we are interested in. */
8169 /* If X is (minus C Y) where C's least set bit is larger than any bit
8170 in the mask, then we may replace with (neg Y). */
8171 if (CONST_INT_P (XEXP (x, 0))
8172 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8173 & -INTVAL (XEXP (x, 0))))
8176 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8178 return force_to_mode (x, mode, mask, next_select);
8181 /* Similarly, if C contains every bit in the fuller_mask, then we may
8182 replace with (not Y). */
8183 if (CONST_INT_P (XEXP (x, 0))
8184 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8186 x = simplify_gen_unary (NOT, GET_MODE (x),
8187 XEXP (x, 1), GET_MODE (x));
8188 return force_to_mode (x, mode, mask, next_select);
8196 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8197 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8198 operation which may be a bitfield extraction. Ensure that the
8199 constant we form is not wider than the mode of X. */
8201 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8202 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8203 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8204 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8205 && CONST_INT_P (XEXP (x, 1))
8206 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8207 + floor_log2 (INTVAL (XEXP (x, 1))))
8208 < GET_MODE_PRECISION (GET_MODE (x)))
8209 && (UINTVAL (XEXP (x, 1))
8210 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8212 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8213 << INTVAL (XEXP (XEXP (x, 0), 1)));
8214 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8215 XEXP (XEXP (x, 0), 0), temp);
8216 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8217 XEXP (XEXP (x, 0), 1));
8218 return force_to_mode (x, mode, mask, next_select);
8222 /* For most binary operations, just propagate into the operation and
8223 change the mode if we have an operation of that mode. */
8225 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8226 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8228 /* If we ended up truncating both operands, truncate the result of the
8229 operation instead. */
8230 if (GET_CODE (op0) == TRUNCATE
8231 && GET_CODE (op1) == TRUNCATE)
8233 op0 = XEXP (op0, 0);
8234 op1 = XEXP (op1, 0);
8237 op0 = gen_lowpart_or_truncate (op_mode, op0);
8238 op1 = gen_lowpart_or_truncate (op_mode, op1);
8240 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8241 x = simplify_gen_binary (code, op_mode, op0, op1);
8245 /* For left shifts, do the same, but just for the first operand.
8246 However, we cannot do anything with shifts where we cannot
8247 guarantee that the counts are smaller than the size of the mode
8248 because such a count will have a different meaning in a
8251 if (! (CONST_INT_P (XEXP (x, 1))
8252 && INTVAL (XEXP (x, 1)) >= 0
8253 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8254 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8255 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8256 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8259 /* If the shift count is a constant and we can do arithmetic in
8260 the mode of the shift, refine which bits we need. Otherwise, use the
8261 conservative form of the mask. */
8262 if (CONST_INT_P (XEXP (x, 1))
8263 && INTVAL (XEXP (x, 1)) >= 0
8264 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8265 && HWI_COMPUTABLE_MODE_P (op_mode))
8266 mask >>= INTVAL (XEXP (x, 1));
8270 op0 = gen_lowpart_or_truncate (op_mode,
8271 force_to_mode (XEXP (x, 0), op_mode,
8272 mask, next_select));
8274 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8275 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8279 /* Here we can only do something if the shift count is a constant,
8280 this shift constant is valid for the host, and we can do arithmetic
8283 if (CONST_INT_P (XEXP (x, 1))
8284 && INTVAL (XEXP (x, 1)) >= 0
8285 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8286 && HWI_COMPUTABLE_MODE_P (op_mode))
8288 rtx inner = XEXP (x, 0);
8289 unsigned HOST_WIDE_INT inner_mask;
8291 /* Select the mask of the bits we need for the shift operand. */
8292 inner_mask = mask << INTVAL (XEXP (x, 1));
8294 /* We can only change the mode of the shift if we can do arithmetic
8295 in the mode of the shift and INNER_MASK is no wider than the
8296 width of X's mode. */
8297 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8298 op_mode = GET_MODE (x);
8300 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8302 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8303 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8306 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8307 shift and AND produces only copies of the sign bit (C2 is one less
8308 than a power of two), we can do this with just a shift. */
8310 if (GET_CODE (x) == LSHIFTRT
8311 && CONST_INT_P (XEXP (x, 1))
8312 /* The shift puts one of the sign bit copies in the least significant
8314 && ((INTVAL (XEXP (x, 1))
8315 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8316 >= GET_MODE_PRECISION (GET_MODE (x)))
8317 && exact_log2 (mask + 1) >= 0
8318 /* Number of bits left after the shift must be more than the mask
8320 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8321 <= GET_MODE_PRECISION (GET_MODE (x)))
8322 /* Must be more sign bit copies than the mask needs. */
8323 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8324 >= exact_log2 (mask + 1)))
8325 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8326 GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8327 - exact_log2 (mask + 1)));
8332 /* If we are just looking for the sign bit, we don't need this shift at
8333 all, even if it has a variable count. */
8334 if (val_signbit_p (GET_MODE (x), mask))
8335 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8337 /* If this is a shift by a constant, get a mask that contains those bits
8338 that are not copies of the sign bit. We then have two cases: If
8339 MASK only includes those bits, this can be a logical shift, which may
8340 allow simplifications. If MASK is a single-bit field not within
8341 those bits, we are requesting a copy of the sign bit and hence can
8342 shift the sign bit to the appropriate location. */
8344 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8345 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8349 /* If the considered data is wider than HOST_WIDE_INT, we can't
8350 represent a mask for all its bits in a single scalar.
8351 But we only care about the lower bits, so calculate these. */
8353 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8355 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8357 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8358 is the number of bits a full-width mask would have set.
8359 We need only shift if these are fewer than nonzero can
8360 hold. If not, we must keep all bits set in nonzero. */
8362 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8363 < HOST_BITS_PER_WIDE_INT)
8364 nonzero >>= INTVAL (XEXP (x, 1))
8365 + HOST_BITS_PER_WIDE_INT
8366 - GET_MODE_PRECISION (GET_MODE (x)) ;
8370 nonzero = GET_MODE_MASK (GET_MODE (x));
8371 nonzero >>= INTVAL (XEXP (x, 1));
8374 if ((mask & ~nonzero) == 0)
8376 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8377 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8378 if (GET_CODE (x) != ASHIFTRT)
8379 return force_to_mode (x, mode, mask, next_select);
8382 else if ((i = exact_log2 (mask)) >= 0)
8384 x = simplify_shift_const
8385 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8386 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8388 if (GET_CODE (x) != ASHIFTRT)
8389 return force_to_mode (x, mode, mask, next_select);
8393 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8394 even if the shift count isn't a constant. */
8396 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8397 XEXP (x, 0), XEXP (x, 1));
8401 /* If this is a zero- or sign-extension operation that just affects bits
8402 we don't care about, remove it. Be sure the call above returned
8403 something that is still a shift. */
8405 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8406 && CONST_INT_P (XEXP (x, 1))
8407 && INTVAL (XEXP (x, 1)) >= 0
8408 && (INTVAL (XEXP (x, 1))
8409 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8410 && GET_CODE (XEXP (x, 0)) == ASHIFT
8411 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8412 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8419 /* If the shift count is constant and we can do computations
8420 in the mode of X, compute where the bits we care about are.
8421 Otherwise, we can't do anything. Don't change the mode of
8422 the shift or propagate MODE into the shift, though. */
8423 if (CONST_INT_P (XEXP (x, 1))
8424 && INTVAL (XEXP (x, 1)) >= 0)
8426 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8427 GET_MODE (x), GEN_INT (mask),
8429 if (temp && CONST_INT_P (temp))
8431 force_to_mode (XEXP (x, 0), GET_MODE (x),
8432 INTVAL (temp), next_select));
8437 /* If we just want the low-order bit, the NEG isn't needed since it
8438 won't change the low-order bit. */
8440 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8442 /* We need any bits less significant than the most significant bit in
8443 MASK since carries from those bits will affect the bits we are
8449 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8450 same as the XOR case above. Ensure that the constant we form is not
8451 wider than the mode of X. */
8453 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8454 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8455 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8456 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8457 < GET_MODE_PRECISION (GET_MODE (x)))
8458 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8460 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8462 temp = simplify_gen_binary (XOR, GET_MODE (x),
8463 XEXP (XEXP (x, 0), 0), temp);
8464 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8465 temp, XEXP (XEXP (x, 0), 1));
8467 return force_to_mode (x, mode, mask, next_select);
8470 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8471 use the full mask inside the NOT. */
8475 op0 = gen_lowpart_or_truncate (op_mode,
8476 force_to_mode (XEXP (x, 0), mode, mask,
8478 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8479 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8483 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8484 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8485 which is equal to STORE_FLAG_VALUE. */
8486 if ((mask & ~STORE_FLAG_VALUE) == 0
8487 && XEXP (x, 1) == const0_rtx
8488 && GET_MODE (XEXP (x, 0)) == mode
8489 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8490 && (nonzero_bits (XEXP (x, 0), mode)
8491 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8492 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8497 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8498 written in a narrower mode. We play it safe and do not do so. */
8501 gen_lowpart_or_truncate (GET_MODE (x),
8502 force_to_mode (XEXP (x, 1), mode,
8503 mask, next_select)));
8505 gen_lowpart_or_truncate (GET_MODE (x),
8506 force_to_mode (XEXP (x, 2), mode,
8507 mask, next_select)));
8514 /* Ensure we return a value of the proper mode. */
8515 return gen_lowpart_or_truncate (mode, x);
8518 /* Return nonzero if X is an expression that has one of two values depending on
8519 whether some other value is zero or nonzero. In that case, we return the
8520 value that is being tested, *PTRUE is set to the value if the rtx being
8521 returned has a nonzero value, and *PFALSE is set to the other alternative.
8523 If we return zero, we set *PTRUE and *PFALSE to X. */
8526 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8528 enum machine_mode mode = GET_MODE (x);
8529 enum rtx_code code = GET_CODE (x);
8530 rtx cond0, cond1, true0, true1, false0, false1;
8531 unsigned HOST_WIDE_INT nz;
8533 /* If we are comparing a value against zero, we are done. */
8534 if ((code == NE || code == EQ)
8535 && XEXP (x, 1) == const0_rtx)
8537 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8538 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8542 /* If this is a unary operation whose operand has one of two values, apply
8543 our opcode to compute those values. */
8544 else if (UNARY_P (x)
8545 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8547 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8548 *pfalse = simplify_gen_unary (code, mode, false0,
8549 GET_MODE (XEXP (x, 0)));
8553 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8554 make can't possibly match and would suppress other optimizations. */
8555 else if (code == COMPARE)
8558 /* If this is a binary operation, see if either side has only one of two
8559 values. If either one does or if both do and they are conditional on
8560 the same value, compute the new true and false values. */
8561 else if (BINARY_P (x))
8563 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8564 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8566 if ((cond0 != 0 || cond1 != 0)
8567 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8569 /* If if_then_else_cond returned zero, then true/false are the
8570 same rtl. We must copy one of them to prevent invalid rtl
8573 true0 = copy_rtx (true0);
8574 else if (cond1 == 0)
8575 true1 = copy_rtx (true1);
8577 if (COMPARISON_P (x))
8579 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8581 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8586 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8587 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8590 return cond0 ? cond0 : cond1;
8593 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8594 operands is zero when the other is nonzero, and vice-versa,
8595 and STORE_FLAG_VALUE is 1 or -1. */
8597 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8598 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8600 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8602 rtx op0 = XEXP (XEXP (x, 0), 1);
8603 rtx op1 = XEXP (XEXP (x, 1), 1);
8605 cond0 = XEXP (XEXP (x, 0), 0);
8606 cond1 = XEXP (XEXP (x, 1), 0);
8608 if (COMPARISON_P (cond0)
8609 && COMPARISON_P (cond1)
8610 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8611 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8612 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8613 || ((swap_condition (GET_CODE (cond0))
8614 == reversed_comparison_code (cond1, NULL))
8615 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8616 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8617 && ! side_effects_p (x))
8619 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8620 *pfalse = simplify_gen_binary (MULT, mode,
8622 ? simplify_gen_unary (NEG, mode,
8630 /* Similarly for MULT, AND and UMIN, except that for these the result
8632 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8633 && (code == MULT || code == AND || code == UMIN)
8634 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8636 cond0 = XEXP (XEXP (x, 0), 0);
8637 cond1 = XEXP (XEXP (x, 1), 0);
8639 if (COMPARISON_P (cond0)
8640 && COMPARISON_P (cond1)
8641 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8642 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8643 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8644 || ((swap_condition (GET_CODE (cond0))
8645 == reversed_comparison_code (cond1, NULL))
8646 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8647 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8648 && ! side_effects_p (x))
8650 *ptrue = *pfalse = const0_rtx;
8656 else if (code == IF_THEN_ELSE)
8658 /* If we have IF_THEN_ELSE already, extract the condition and
8659 canonicalize it if it is NE or EQ. */
8660 cond0 = XEXP (x, 0);
8661 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8662 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8663 return XEXP (cond0, 0);
8664 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8666 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8667 return XEXP (cond0, 0);
8673 /* If X is a SUBREG, we can narrow both the true and false values
8674 if the inner expression, if there is a condition. */
8675 else if (code == SUBREG
8676 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8679 true0 = simplify_gen_subreg (mode, true0,
8680 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8681 false0 = simplify_gen_subreg (mode, false0,
8682 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8683 if (true0 && false0)
8691 /* If X is a constant, this isn't special and will cause confusions
8692 if we treat it as such. Likewise if it is equivalent to a constant. */
8693 else if (CONSTANT_P (x)
8694 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8697 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8698 will be least confusing to the rest of the compiler. */
8699 else if (mode == BImode)
8701 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8705 /* If X is known to be either 0 or -1, those are the true and
8706 false values when testing X. */
8707 else if (x == constm1_rtx || x == const0_rtx
8708 || (mode != VOIDmode
8709 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8711 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8715 /* Likewise for 0 or a single bit. */
8716 else if (HWI_COMPUTABLE_MODE_P (mode)
8717 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8719 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8723 /* Otherwise fail; show no condition with true and false values the same. */
8724 *ptrue = *pfalse = x;
8728 /* Return the value of expression X given the fact that condition COND
8729 is known to be true when applied to REG as its first operand and VAL
8730 as its second. X is known to not be shared and so can be modified in
8733 We only handle the simplest cases, and specifically those cases that
8734 arise with IF_THEN_ELSE expressions. */
8737 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8739 enum rtx_code code = GET_CODE (x);
8744 if (side_effects_p (x))
8747 /* If either operand of the condition is a floating point value,
8748 then we have to avoid collapsing an EQ comparison. */
8750 && rtx_equal_p (x, reg)
8751 && ! FLOAT_MODE_P (GET_MODE (x))
8752 && ! FLOAT_MODE_P (GET_MODE (val)))
8755 if (cond == UNEQ && rtx_equal_p (x, reg))
8758 /* If X is (abs REG) and we know something about REG's relationship
8759 with zero, we may be able to simplify this. */
8761 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8764 case GE: case GT: case EQ:
8767 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8769 GET_MODE (XEXP (x, 0)));
8774 /* The only other cases we handle are MIN, MAX, and comparisons if the
8775 operands are the same as REG and VAL. */
8777 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8779 if (rtx_equal_p (XEXP (x, 0), val))
8780 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8782 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8784 if (COMPARISON_P (x))
8786 if (comparison_dominates_p (cond, code))
8787 return const_true_rtx;
8789 code = reversed_comparison_code (x, NULL);
8791 && comparison_dominates_p (cond, code))
8796 else if (code == SMAX || code == SMIN
8797 || code == UMIN || code == UMAX)
8799 int unsignedp = (code == UMIN || code == UMAX);
8801 /* Do not reverse the condition when it is NE or EQ.
8802 This is because we cannot conclude anything about
8803 the value of 'SMAX (x, y)' when x is not equal to y,
8804 but we can when x equals y. */
8805 if ((code == SMAX || code == UMAX)
8806 && ! (cond == EQ || cond == NE))
8807 cond = reverse_condition (cond);
8812 return unsignedp ? x : XEXP (x, 1);
8814 return unsignedp ? x : XEXP (x, 0);
8816 return unsignedp ? XEXP (x, 1) : x;
8818 return unsignedp ? XEXP (x, 0) : x;
8825 else if (code == SUBREG)
8827 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8828 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8830 if (SUBREG_REG (x) != r)
8832 /* We must simplify subreg here, before we lose track of the
8833 original inner_mode. */
8834 new_rtx = simplify_subreg (GET_MODE (x), r,
8835 inner_mode, SUBREG_BYTE (x));
8839 SUBST (SUBREG_REG (x), r);
8844 /* We don't have to handle SIGN_EXTEND here, because even in the
8845 case of replacing something with a modeless CONST_INT, a
8846 CONST_INT is already (supposed to be) a valid sign extension for
8847 its narrower mode, which implies it's already properly
8848 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8849 story is different. */
8850 else if (code == ZERO_EXTEND)
8852 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8853 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8855 if (XEXP (x, 0) != r)
8857 /* We must simplify the zero_extend here, before we lose
8858 track of the original inner_mode. */
8859 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8864 SUBST (XEXP (x, 0), r);
8870 fmt = GET_RTX_FORMAT (code);
8871 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8874 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8875 else if (fmt[i] == 'E')
8876 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8877 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8884 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8885 assignment as a field assignment. */
8888 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8890 if (x == y || rtx_equal_p (x, y))
8893 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8896 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8897 Note that all SUBREGs of MEM are paradoxical; otherwise they
8898 would have been rewritten. */
8899 if (MEM_P (x) && GET_CODE (y) == SUBREG
8900 && MEM_P (SUBREG_REG (y))
8901 && rtx_equal_p (SUBREG_REG (y),
8902 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8905 if (MEM_P (y) && GET_CODE (x) == SUBREG
8906 && MEM_P (SUBREG_REG (x))
8907 && rtx_equal_p (SUBREG_REG (x),
8908 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8911 /* We used to see if get_last_value of X and Y were the same but that's
8912 not correct. In one direction, we'll cause the assignment to have
8913 the wrong destination and in the case, we'll import a register into this
8914 insn that might have already have been dead. So fail if none of the
8915 above cases are true. */
8919 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8920 Return that assignment if so.
8922 We only handle the most common cases. */
8925 make_field_assignment (rtx x)
8927 rtx dest = SET_DEST (x);
8928 rtx src = SET_SRC (x);
8933 unsigned HOST_WIDE_INT len;
8935 enum machine_mode mode;
8937 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8938 a clear of a one-bit field. We will have changed it to
8939 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8942 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8943 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8944 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8945 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8947 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8950 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8954 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8955 && subreg_lowpart_p (XEXP (src, 0))
8956 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8957 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8958 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8959 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8960 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8961 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8963 assign = make_extraction (VOIDmode, dest, 0,
8964 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8967 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8971 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8973 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8974 && XEXP (XEXP (src, 0), 0) == const1_rtx
8975 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8977 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8980 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8984 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8985 SRC is an AND with all bits of that field set, then we can discard
8987 if (GET_CODE (dest) == ZERO_EXTRACT
8988 && CONST_INT_P (XEXP (dest, 1))
8989 && GET_CODE (src) == AND
8990 && CONST_INT_P (XEXP (src, 1)))
8992 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8993 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8994 unsigned HOST_WIDE_INT ze_mask;
8996 if (width >= HOST_BITS_PER_WIDE_INT)
8999 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9001 /* Complete overlap. We can remove the source AND. */
9002 if ((and_mask & ze_mask) == ze_mask)
9003 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9005 /* Partial overlap. We can reduce the source AND. */
9006 if ((and_mask & ze_mask) != and_mask)
9008 mode = GET_MODE (src);
9009 src = gen_rtx_AND (mode, XEXP (src, 0),
9010 gen_int_mode (and_mask & ze_mask, mode));
9011 return gen_rtx_SET (VOIDmode, dest, src);
9015 /* The other case we handle is assignments into a constant-position
9016 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9017 a mask that has all one bits except for a group of zero bits and
9018 OTHER is known to have zeros where C1 has ones, this is such an
9019 assignment. Compute the position and length from C1. Shift OTHER
9020 to the appropriate position, force it to the required mode, and
9021 make the extraction. Check for the AND in both operands. */
9023 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9026 rhs = expand_compound_operation (XEXP (src, 0));
9027 lhs = expand_compound_operation (XEXP (src, 1));
9029 if (GET_CODE (rhs) == AND
9030 && CONST_INT_P (XEXP (rhs, 1))
9031 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9032 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9033 else if (GET_CODE (lhs) == AND
9034 && CONST_INT_P (XEXP (lhs, 1))
9035 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9036 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9040 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9041 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9042 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9043 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9046 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9050 /* The mode to use for the source is the mode of the assignment, or of
9051 what is inside a possible STRICT_LOW_PART. */
9052 mode = (GET_CODE (assign) == STRICT_LOW_PART
9053 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9055 /* Shift OTHER right POS places and make it the source, restricting it
9056 to the proper length and mode. */
9058 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9062 src = force_to_mode (src, mode,
9063 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9064 ? ~(unsigned HOST_WIDE_INT) 0
9065 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9068 /* If SRC is masked by an AND that does not make a difference in
9069 the value being stored, strip it. */
9070 if (GET_CODE (assign) == ZERO_EXTRACT
9071 && CONST_INT_P (XEXP (assign, 1))
9072 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9073 && GET_CODE (src) == AND
9074 && CONST_INT_P (XEXP (src, 1))
9075 && UINTVAL (XEXP (src, 1))
9076 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9077 src = XEXP (src, 0);
9079 return gen_rtx_SET (VOIDmode, assign, src);
9082 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9086 apply_distributive_law (rtx x)
9088 enum rtx_code code = GET_CODE (x);
9089 enum rtx_code inner_code;
9090 rtx lhs, rhs, other;
9093 /* Distributivity is not true for floating point as it can change the
9094 value. So we don't do it unless -funsafe-math-optimizations. */
9095 if (FLOAT_MODE_P (GET_MODE (x))
9096 && ! flag_unsafe_math_optimizations)
9099 /* The outer operation can only be one of the following: */
9100 if (code != IOR && code != AND && code != XOR
9101 && code != PLUS && code != MINUS)
9107 /* If either operand is a primitive we can't do anything, so get out
9109 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9112 lhs = expand_compound_operation (lhs);
9113 rhs = expand_compound_operation (rhs);
9114 inner_code = GET_CODE (lhs);
9115 if (inner_code != GET_CODE (rhs))
9118 /* See if the inner and outer operations distribute. */
9125 /* These all distribute except over PLUS. */
9126 if (code == PLUS || code == MINUS)
9131 if (code != PLUS && code != MINUS)
9136 /* This is also a multiply, so it distributes over everything. */
9139 /* This used to handle SUBREG, but this turned out to be counter-
9140 productive, since (subreg (op ...)) usually is not handled by
9141 insn patterns, and this "optimization" therefore transformed
9142 recognizable patterns into unrecognizable ones. Therefore the
9143 SUBREG case was removed from here.
9145 It is possible that distributing SUBREG over arithmetic operations
9146 leads to an intermediate result than can then be optimized further,
9147 e.g. by moving the outer SUBREG to the other side of a SET as done
9148 in simplify_set. This seems to have been the original intent of
9149 handling SUBREGs here.
9151 However, with current GCC this does not appear to actually happen,
9152 at least on major platforms. If some case is found where removing
9153 the SUBREG case here prevents follow-on optimizations, distributing
9154 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9160 /* Set LHS and RHS to the inner operands (A and B in the example
9161 above) and set OTHER to the common operand (C in the example).
9162 There is only one way to do this unless the inner operation is
9164 if (COMMUTATIVE_ARITH_P (lhs)
9165 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9166 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9167 else if (COMMUTATIVE_ARITH_P (lhs)
9168 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9169 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9170 else if (COMMUTATIVE_ARITH_P (lhs)
9171 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9172 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9173 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9174 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9178 /* Form the new inner operation, seeing if it simplifies first. */
9179 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9181 /* There is one exception to the general way of distributing:
9182 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9183 if (code == XOR && inner_code == IOR)
9186 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9189 /* We may be able to continuing distributing the result, so call
9190 ourselves recursively on the inner operation before forming the
9191 outer operation, which we return. */
9192 return simplify_gen_binary (inner_code, GET_MODE (x),
9193 apply_distributive_law (tem), other);
9196 /* See if X is of the form (* (+ A B) C), and if so convert to
9197 (+ (* A C) (* B C)) and try to simplify.
9199 Most of the time, this results in no change. However, if some of
9200 the operands are the same or inverses of each other, simplifications
9203 For example, (and (ior A B) (not B)) can occur as the result of
9204 expanding a bit field assignment. When we apply the distributive
9205 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9206 which then simplifies to (and (A (not B))).
9208 Note that no checks happen on the validity of applying the inverse
9209 distributive law. This is pointless since we can do it in the
9210 few places where this routine is called.
9212 N is the index of the term that is decomposed (the arithmetic operation,
9213 i.e. (+ A B) in the first example above). !N is the index of the term that
9214 is distributed, i.e. of C in the first example above. */
9216 distribute_and_simplify_rtx (rtx x, int n)
9218 enum machine_mode mode;
9219 enum rtx_code outer_code, inner_code;
9220 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9222 /* Distributivity is not true for floating point as it can change the
9223 value. So we don't do it unless -funsafe-math-optimizations. */
9224 if (FLOAT_MODE_P (GET_MODE (x))
9225 && ! flag_unsafe_math_optimizations)
9228 decomposed = XEXP (x, n);
9229 if (!ARITHMETIC_P (decomposed))
9232 mode = GET_MODE (x);
9233 outer_code = GET_CODE (x);
9234 distributed = XEXP (x, !n);
9236 inner_code = GET_CODE (decomposed);
9237 inner_op0 = XEXP (decomposed, 0);
9238 inner_op1 = XEXP (decomposed, 1);
9240 /* Special case (and (xor B C) (not A)), which is equivalent to
9241 (xor (ior A B) (ior A C)) */
9242 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9244 distributed = XEXP (distributed, 0);
9250 /* Distribute the second term. */
9251 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9252 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9256 /* Distribute the first term. */
9257 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9258 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9261 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9263 if (GET_CODE (tmp) != outer_code
9264 && (set_src_cost (tmp, optimize_this_for_speed_p)
9265 < set_src_cost (x, optimize_this_for_speed_p)))
9271 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9272 in MODE. Return an equivalent form, if different from (and VAROP
9273 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9276 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9277 unsigned HOST_WIDE_INT constop)
9279 unsigned HOST_WIDE_INT nonzero;
9280 unsigned HOST_WIDE_INT orig_constop;
9285 orig_constop = constop;
9286 if (GET_CODE (varop) == CLOBBER)
9289 /* Simplify VAROP knowing that we will be only looking at some of the
9292 Note by passing in CONSTOP, we guarantee that the bits not set in
9293 CONSTOP are not significant and will never be examined. We must
9294 ensure that is the case by explicitly masking out those bits
9295 before returning. */
9296 varop = force_to_mode (varop, mode, constop, 0);
9298 /* If VAROP is a CLOBBER, we will fail so return it. */
9299 if (GET_CODE (varop) == CLOBBER)
9302 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9303 to VAROP and return the new constant. */
9304 if (CONST_INT_P (varop))
9305 return gen_int_mode (INTVAL (varop) & constop, mode);
9307 /* See what bits may be nonzero in VAROP. Unlike the general case of
9308 a call to nonzero_bits, here we don't care about bits outside
9311 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9313 /* Turn off all bits in the constant that are known to already be zero.
9314 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9315 which is tested below. */
9319 /* If we don't have any bits left, return zero. */
9323 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9324 a power of two, we can replace this with an ASHIFT. */
9325 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9326 && (i = exact_log2 (constop)) >= 0)
9327 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9329 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9330 or XOR, then try to apply the distributive law. This may eliminate
9331 operations if either branch can be simplified because of the AND.
9332 It may also make some cases more complex, but those cases probably
9333 won't match a pattern either with or without this. */
9335 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9339 apply_distributive_law
9340 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9341 simplify_and_const_int (NULL_RTX,
9345 simplify_and_const_int (NULL_RTX,
9350 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9351 the AND and see if one of the operands simplifies to zero. If so, we
9352 may eliminate it. */
9354 if (GET_CODE (varop) == PLUS
9355 && exact_log2 (constop + 1) >= 0)
9359 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9360 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9361 if (o0 == const0_rtx)
9363 if (o1 == const0_rtx)
9367 /* Make a SUBREG if necessary. If we can't make it, fail. */
9368 varop = gen_lowpart (mode, varop);
9369 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9372 /* If we are only masking insignificant bits, return VAROP. */
9373 if (constop == nonzero)
9376 if (varop == orig_varop && constop == orig_constop)
9379 /* Otherwise, return an AND. */
9380 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9384 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9387 Return an equivalent form, if different from X. Otherwise, return X. If
9388 X is zero, we are to always construct the equivalent form. */
9391 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9392 unsigned HOST_WIDE_INT constop)
9394 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9399 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9400 gen_int_mode (constop, mode));
9401 if (GET_MODE (x) != mode)
9402 x = gen_lowpart (mode, x);
9406 /* Given a REG, X, compute which bits in X can be nonzero.
9407 We don't care about bits outside of those defined in MODE.
9409 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9410 a shift, AND, or zero_extract, we can do better. */
9413 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9414 const_rtx known_x ATTRIBUTE_UNUSED,
9415 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9416 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9417 unsigned HOST_WIDE_INT *nonzero)
9422 /* If X is a register whose nonzero bits value is current, use it.
9423 Otherwise, if X is a register whose value we can find, use that
9424 value. Otherwise, use the previously-computed global nonzero bits
9425 for this register. */
9427 rsp = ®_stat[REGNO (x)];
9428 if (rsp->last_set_value != 0
9429 && (rsp->last_set_mode == mode
9430 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9431 && GET_MODE_CLASS (mode) == MODE_INT))
9432 && ((rsp->last_set_label >= label_tick_ebb_start
9433 && rsp->last_set_label < label_tick)
9434 || (rsp->last_set_label == label_tick
9435 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9436 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9437 && REG_N_SETS (REGNO (x)) == 1
9439 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9441 *nonzero &= rsp->last_set_nonzero_bits;
9445 tem = get_last_value (x);
9449 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9450 /* If X is narrower than MODE and TEM is a non-negative
9451 constant that would appear negative in the mode of X,
9452 sign-extend it for use in reg_nonzero_bits because some
9453 machines (maybe most) will actually do the sign-extension
9454 and this is the conservative approach.
9456 ??? For 2.5, try to tighten up the MD files in this regard
9457 instead of this kludge. */
9459 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9460 && CONST_INT_P (tem)
9462 && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9463 tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9467 else if (nonzero_sign_valid && rsp->nonzero_bits)
9469 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9471 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9472 /* We don't know anything about the upper bits. */
9473 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9480 /* Return the number of bits at the high-order end of X that are known to
9481 be equal to the sign bit. X will be used in mode MODE; if MODE is
9482 VOIDmode, X will be used in its own mode. The returned value will always
9483 be between 1 and the number of bits in MODE. */
9486 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9487 const_rtx known_x ATTRIBUTE_UNUSED,
9488 enum machine_mode known_mode
9490 unsigned int known_ret ATTRIBUTE_UNUSED,
9491 unsigned int *result)
9496 rsp = ®_stat[REGNO (x)];
9497 if (rsp->last_set_value != 0
9498 && rsp->last_set_mode == mode
9499 && ((rsp->last_set_label >= label_tick_ebb_start
9500 && rsp->last_set_label < label_tick)
9501 || (rsp->last_set_label == label_tick
9502 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9503 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9504 && REG_N_SETS (REGNO (x)) == 1
9506 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9508 *result = rsp->last_set_sign_bit_copies;
9512 tem = get_last_value (x);
9516 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9517 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9518 *result = rsp->sign_bit_copies;
9523 /* Return the number of "extended" bits there are in X, when interpreted
9524 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9525 unsigned quantities, this is the number of high-order zero bits.
9526 For signed quantities, this is the number of copies of the sign bit
9527 minus 1. In both case, this function returns the number of "spare"
9528 bits. For example, if two quantities for which this function returns
9529 at least 1 are added, the addition is known not to overflow.
9531 This function will always return 0 unless called during combine, which
9532 implies that it must be called from a define_split. */
9535 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9537 if (nonzero_sign_valid == 0)
9541 ? (HWI_COMPUTABLE_MODE_P (mode)
9542 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9543 - floor_log2 (nonzero_bits (x, mode)))
9545 : num_sign_bit_copies (x, mode) - 1);
9548 /* This function is called from `simplify_shift_const' to merge two
9549 outer operations. Specifically, we have already found that we need
9550 to perform operation *POP0 with constant *PCONST0 at the outermost
9551 position. We would now like to also perform OP1 with constant CONST1
9552 (with *POP0 being done last).
9554 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9555 the resulting operation. *PCOMP_P is set to 1 if we would need to
9556 complement the innermost operand, otherwise it is unchanged.
9558 MODE is the mode in which the operation will be done. No bits outside
9559 the width of this mode matter. It is assumed that the width of this mode
9560 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9562 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9563 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9564 result is simply *PCONST0.
9566 If the resulting operation cannot be expressed as one operation, we
9567 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9570 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9572 enum rtx_code op0 = *pop0;
9573 HOST_WIDE_INT const0 = *pconst0;
9575 const0 &= GET_MODE_MASK (mode);
9576 const1 &= GET_MODE_MASK (mode);
9578 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9582 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9585 if (op1 == UNKNOWN || op0 == SET)
9588 else if (op0 == UNKNOWN)
9589 op0 = op1, const0 = const1;
9591 else if (op0 == op1)
9615 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9616 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9619 /* If the two constants aren't the same, we can't do anything. The
9620 remaining six cases can all be done. */
9621 else if (const0 != const1)
9629 /* (a & b) | b == b */
9631 else /* op1 == XOR */
9632 /* (a ^ b) | b == a | b */
9638 /* (a & b) ^ b == (~a) & b */
9639 op0 = AND, *pcomp_p = 1;
9640 else /* op1 == IOR */
9641 /* (a | b) ^ b == a & ~b */
9642 op0 = AND, const0 = ~const0;
9647 /* (a | b) & b == b */
9649 else /* op1 == XOR */
9650 /* (a ^ b) & b) == (~a) & b */
9657 /* Check for NO-OP cases. */
9658 const0 &= GET_MODE_MASK (mode);
9660 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9662 else if (const0 == 0 && op0 == AND)
9664 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9670 /* ??? Slightly redundant with the above mask, but not entirely.
9671 Moving this above means we'd have to sign-extend the mode mask
9672 for the final test. */
9673 if (op0 != UNKNOWN && op0 != NEG)
9674 *pconst0 = trunc_int_for_mode (const0, mode);
9679 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9680 the shift in. The original shift operation CODE is performed on OP in
9681 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9682 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9683 result of the shift is subject to operation OUTER_CODE with operand
9686 static enum machine_mode
9687 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9688 enum machine_mode orig_mode, enum machine_mode mode,
9689 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9691 if (orig_mode == mode)
9693 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9695 /* In general we can't perform in wider mode for right shift and rotate. */
9699 /* We can still widen if the bits brought in from the left are identical
9700 to the sign bit of ORIG_MODE. */
9701 if (num_sign_bit_copies (op, mode)
9702 > (unsigned) (GET_MODE_PRECISION (mode)
9703 - GET_MODE_PRECISION (orig_mode)))
9708 /* Similarly here but with zero bits. */
9709 if (HWI_COMPUTABLE_MODE_P (mode)
9710 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9713 /* We can also widen if the bits brought in will be masked off. This
9714 operation is performed in ORIG_MODE. */
9715 if (outer_code == AND)
9717 int care_bits = low_bitmask_len (orig_mode, outer_const);
9720 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9736 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9737 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9738 if we cannot simplify it. Otherwise, return a simplified value.
9740 The shift is normally computed in the widest mode we find in VAROP, as
9741 long as it isn't a different number of words than RESULT_MODE. Exceptions
9742 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9745 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9746 rtx varop, int orig_count)
9748 enum rtx_code orig_code = code;
9749 rtx orig_varop = varop;
9751 enum machine_mode mode = result_mode;
9752 enum machine_mode shift_mode, tmode;
9753 unsigned int mode_words
9754 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9755 /* We form (outer_op (code varop count) (outer_const)). */
9756 enum rtx_code outer_op = UNKNOWN;
9757 HOST_WIDE_INT outer_const = 0;
9758 int complement_p = 0;
9761 /* Make sure and truncate the "natural" shift on the way in. We don't
9762 want to do this inside the loop as it makes it more difficult to
9764 if (SHIFT_COUNT_TRUNCATED)
9765 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9767 /* If we were given an invalid count, don't do anything except exactly
9768 what was requested. */
9770 if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9775 /* Unless one of the branches of the `if' in this loop does a `continue',
9776 we will `break' the loop after the `if'. */
9780 /* If we have an operand of (clobber (const_int 0)), fail. */
9781 if (GET_CODE (varop) == CLOBBER)
9784 /* Convert ROTATERT to ROTATE. */
9785 if (code == ROTATERT)
9787 unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9789 if (VECTOR_MODE_P (result_mode))
9790 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9792 count = bitsize - count;
9795 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9796 mode, outer_op, outer_const);
9798 /* Handle cases where the count is greater than the size of the mode
9799 minus 1. For ASHIFT, use the size minus one as the count (this can
9800 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9801 take the count modulo the size. For other shifts, the result is
9804 Since these shifts are being produced by the compiler by combining
9805 multiple operations, each of which are defined, we know what the
9806 result is supposed to be. */
9808 if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9810 if (code == ASHIFTRT)
9811 count = GET_MODE_PRECISION (shift_mode) - 1;
9812 else if (code == ROTATE || code == ROTATERT)
9813 count %= GET_MODE_PRECISION (shift_mode);
9816 /* We can't simply return zero because there may be an
9824 /* If we discovered we had to complement VAROP, leave. Making a NOT
9825 here would cause an infinite loop. */
9829 /* An arithmetic right shift of a quantity known to be -1 or 0
9831 if (code == ASHIFTRT
9832 && (num_sign_bit_copies (varop, shift_mode)
9833 == GET_MODE_PRECISION (shift_mode)))
9839 /* If we are doing an arithmetic right shift and discarding all but
9840 the sign bit copies, this is equivalent to doing a shift by the
9841 bitsize minus one. Convert it into that shift because it will often
9842 allow other simplifications. */
9844 if (code == ASHIFTRT
9845 && (count + num_sign_bit_copies (varop, shift_mode)
9846 >= GET_MODE_PRECISION (shift_mode)))
9847 count = GET_MODE_PRECISION (shift_mode) - 1;
9849 /* We simplify the tests below and elsewhere by converting
9850 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9851 `make_compound_operation' will convert it to an ASHIFTRT for
9852 those machines (such as VAX) that don't have an LSHIFTRT. */
9853 if (code == ASHIFTRT
9854 && val_signbit_known_clear_p (shift_mode,
9855 nonzero_bits (varop, shift_mode)))
9858 if (((code == LSHIFTRT
9859 && HWI_COMPUTABLE_MODE_P (shift_mode)
9860 && !(nonzero_bits (varop, shift_mode) >> count))
9862 && HWI_COMPUTABLE_MODE_P (shift_mode)
9863 && !((nonzero_bits (varop, shift_mode) << count)
9864 & GET_MODE_MASK (shift_mode))))
9865 && !side_effects_p (varop))
9868 switch (GET_CODE (varop))
9874 new_rtx = expand_compound_operation (varop);
9875 if (new_rtx != varop)
9883 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9884 minus the width of a smaller mode, we can do this with a
9885 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9886 if ((code == ASHIFTRT || code == LSHIFTRT)
9887 && ! mode_dependent_address_p (XEXP (varop, 0),
9888 MEM_ADDR_SPACE (varop))
9889 && ! MEM_VOLATILE_P (varop)
9890 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9891 MODE_INT, 1)) != BLKmode)
9893 new_rtx = adjust_address_nv (varop, tmode,
9894 BYTES_BIG_ENDIAN ? 0
9895 : count / BITS_PER_UNIT);
9897 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9898 : ZERO_EXTEND, mode, new_rtx);
9905 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9906 the same number of words as what we've seen so far. Then store
9907 the widest mode in MODE. */
9908 if (subreg_lowpart_p (varop)
9909 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9910 > GET_MODE_SIZE (GET_MODE (varop)))
9911 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9912 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9914 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9915 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9917 varop = SUBREG_REG (varop);
9918 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9919 mode = GET_MODE (varop);
9925 /* Some machines use MULT instead of ASHIFT because MULT
9926 is cheaper. But it is still better on those machines to
9927 merge two shifts into one. */
9928 if (CONST_INT_P (XEXP (varop, 1))
9929 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9932 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9934 GEN_INT (exact_log2 (
9935 UINTVAL (XEXP (varop, 1)))));
9941 /* Similar, for when divides are cheaper. */
9942 if (CONST_INT_P (XEXP (varop, 1))
9943 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9946 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9948 GEN_INT (exact_log2 (
9949 UINTVAL (XEXP (varop, 1)))));
9955 /* If we are extracting just the sign bit of an arithmetic
9956 right shift, that shift is not needed. However, the sign
9957 bit of a wider mode may be different from what would be
9958 interpreted as the sign bit in a narrower mode, so, if
9959 the result is narrower, don't discard the shift. */
9960 if (code == LSHIFTRT
9961 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9962 && (GET_MODE_BITSIZE (result_mode)
9963 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9965 varop = XEXP (varop, 0);
9969 /* ... fall through ... */
9974 /* Here we have two nested shifts. The result is usually the
9975 AND of a new shift with a mask. We compute the result below. */
9976 if (CONST_INT_P (XEXP (varop, 1))
9977 && INTVAL (XEXP (varop, 1)) >= 0
9978 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
9979 && HWI_COMPUTABLE_MODE_P (result_mode)
9980 && HWI_COMPUTABLE_MODE_P (mode)
9981 && !VECTOR_MODE_P (result_mode))
9983 enum rtx_code first_code = GET_CODE (varop);
9984 unsigned int first_count = INTVAL (XEXP (varop, 1));
9985 unsigned HOST_WIDE_INT mask;
9988 /* We have one common special case. We can't do any merging if
9989 the inner code is an ASHIFTRT of a smaller mode. However, if
9990 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9991 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9992 we can convert it to
9993 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
9994 This simplifies certain SIGN_EXTEND operations. */
9995 if (code == ASHIFT && first_code == ASHIFTRT
9996 && count == (GET_MODE_PRECISION (result_mode)
9997 - GET_MODE_PRECISION (GET_MODE (varop))))
9999 /* C3 has the low-order C1 bits zero. */
10001 mask = GET_MODE_MASK (mode)
10002 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10004 varop = simplify_and_const_int (NULL_RTX, result_mode,
10005 XEXP (varop, 0), mask);
10006 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10008 count = first_count;
10013 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10014 than C1 high-order bits equal to the sign bit, we can convert
10015 this to either an ASHIFT or an ASHIFTRT depending on the
10018 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10020 if (code == ASHIFTRT && first_code == ASHIFT
10021 && GET_MODE (varop) == shift_mode
10022 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10025 varop = XEXP (varop, 0);
10026 count -= first_count;
10036 /* There are some cases we can't do. If CODE is ASHIFTRT,
10037 we can only do this if FIRST_CODE is also ASHIFTRT.
10039 We can't do the case when CODE is ROTATE and FIRST_CODE is
10042 If the mode of this shift is not the mode of the outer shift,
10043 we can't do this if either shift is a right shift or ROTATE.
10045 Finally, we can't do any of these if the mode is too wide
10046 unless the codes are the same.
10048 Handle the case where the shift codes are the same
10051 if (code == first_code)
10053 if (GET_MODE (varop) != result_mode
10054 && (code == ASHIFTRT || code == LSHIFTRT
10055 || code == ROTATE))
10058 count += first_count;
10059 varop = XEXP (varop, 0);
10063 if (code == ASHIFTRT
10064 || (code == ROTATE && first_code == ASHIFTRT)
10065 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10066 || (GET_MODE (varop) != result_mode
10067 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10068 || first_code == ROTATE
10069 || code == ROTATE)))
10072 /* To compute the mask to apply after the shift, shift the
10073 nonzero bits of the inner shift the same way the
10074 outer shift will. */
10076 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10079 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10082 /* Give up if we can't compute an outer operation to use. */
10084 || !CONST_INT_P (mask_rtx)
10085 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10087 result_mode, &complement_p))
10090 /* If the shifts are in the same direction, we add the
10091 counts. Otherwise, we subtract them. */
10092 if ((code == ASHIFTRT || code == LSHIFTRT)
10093 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10094 count += first_count;
10096 count -= first_count;
10098 /* If COUNT is positive, the new shift is usually CODE,
10099 except for the two exceptions below, in which case it is
10100 FIRST_CODE. If the count is negative, FIRST_CODE should
10103 && ((first_code == ROTATE && code == ASHIFT)
10104 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10106 else if (count < 0)
10107 code = first_code, count = -count;
10109 varop = XEXP (varop, 0);
10113 /* If we have (A << B << C) for any shift, we can convert this to
10114 (A << C << B). This wins if A is a constant. Only try this if
10115 B is not a constant. */
10117 else if (GET_CODE (varop) == code
10118 && CONST_INT_P (XEXP (varop, 0))
10119 && !CONST_INT_P (XEXP (varop, 1)))
10121 rtx new_rtx = simplify_const_binary_operation (code, mode,
10124 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10131 if (VECTOR_MODE_P (mode))
10134 /* Make this fit the case below. */
10135 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10141 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10142 with C the size of VAROP - 1 and the shift is logical if
10143 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10144 we have an (le X 0) operation. If we have an arithmetic shift
10145 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10146 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10148 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10149 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10150 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10151 && (code == LSHIFTRT || code == ASHIFTRT)
10152 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10153 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10156 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10159 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10160 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10165 /* If we have (shift (logical)), move the logical to the outside
10166 to allow it to possibly combine with another logical and the
10167 shift to combine with another shift. This also canonicalizes to
10168 what a ZERO_EXTRACT looks like. Also, some machines have
10169 (and (shift)) insns. */
10171 if (CONST_INT_P (XEXP (varop, 1))
10172 /* We can't do this if we have (ashiftrt (xor)) and the
10173 constant has its sign bit set in shift_mode. */
10174 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10175 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10177 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10179 GEN_INT (count))) != 0
10180 && CONST_INT_P (new_rtx)
10181 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10182 INTVAL (new_rtx), result_mode, &complement_p))
10184 varop = XEXP (varop, 0);
10188 /* If we can't do that, try to simplify the shift in each arm of the
10189 logical expression, make a new logical expression, and apply
10190 the inverse distributive law. This also can't be done
10191 for some (ashiftrt (xor)). */
10192 if (CONST_INT_P (XEXP (varop, 1))
10193 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10194 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10197 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10198 XEXP (varop, 0), count);
10199 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10200 XEXP (varop, 1), count);
10202 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10204 varop = apply_distributive_law (varop);
10212 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10213 says that the sign bit can be tested, FOO has mode MODE, C is
10214 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10215 that may be nonzero. */
10216 if (code == LSHIFTRT
10217 && XEXP (varop, 1) == const0_rtx
10218 && GET_MODE (XEXP (varop, 0)) == result_mode
10219 && count == (GET_MODE_PRECISION (result_mode) - 1)
10220 && HWI_COMPUTABLE_MODE_P (result_mode)
10221 && STORE_FLAG_VALUE == -1
10222 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10223 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10226 varop = XEXP (varop, 0);
10233 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10234 than the number of bits in the mode is equivalent to A. */
10235 if (code == LSHIFTRT
10236 && count == (GET_MODE_PRECISION (result_mode) - 1)
10237 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10239 varop = XEXP (varop, 0);
10244 /* NEG commutes with ASHIFT since it is multiplication. Move the
10245 NEG outside to allow shifts to combine. */
10247 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10250 varop = XEXP (varop, 0);
10256 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10257 is one less than the number of bits in the mode is
10258 equivalent to (xor A 1). */
10259 if (code == LSHIFTRT
10260 && count == (GET_MODE_PRECISION (result_mode) - 1)
10261 && XEXP (varop, 1) == constm1_rtx
10262 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10263 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10267 varop = XEXP (varop, 0);
10271 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10272 that might be nonzero in BAR are those being shifted out and those
10273 bits are known zero in FOO, we can replace the PLUS with FOO.
10274 Similarly in the other operand order. This code occurs when
10275 we are computing the size of a variable-size array. */
10277 if ((code == ASHIFTRT || code == LSHIFTRT)
10278 && count < HOST_BITS_PER_WIDE_INT
10279 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10280 && (nonzero_bits (XEXP (varop, 1), result_mode)
10281 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10283 varop = XEXP (varop, 0);
10286 else if ((code == ASHIFTRT || code == LSHIFTRT)
10287 && count < HOST_BITS_PER_WIDE_INT
10288 && HWI_COMPUTABLE_MODE_P (result_mode)
10289 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10291 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10292 & nonzero_bits (XEXP (varop, 1),
10295 varop = XEXP (varop, 1);
10299 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10301 && CONST_INT_P (XEXP (varop, 1))
10302 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10304 GEN_INT (count))) != 0
10305 && CONST_INT_P (new_rtx)
10306 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10307 INTVAL (new_rtx), result_mode, &complement_p))
10309 varop = XEXP (varop, 0);
10313 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10314 signbit', and attempt to change the PLUS to an XOR and move it to
10315 the outer operation as is done above in the AND/IOR/XOR case
10316 leg for shift(logical). See details in logical handling above
10317 for reasoning in doing so. */
10318 if (code == LSHIFTRT
10319 && CONST_INT_P (XEXP (varop, 1))
10320 && mode_signbit_p (result_mode, XEXP (varop, 1))
10321 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10323 GEN_INT (count))) != 0
10324 && CONST_INT_P (new_rtx)
10325 && merge_outer_ops (&outer_op, &outer_const, XOR,
10326 INTVAL (new_rtx), result_mode, &complement_p))
10328 varop = XEXP (varop, 0);
10335 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10336 with C the size of VAROP - 1 and the shift is logical if
10337 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10338 we have a (gt X 0) operation. If the shift is arithmetic with
10339 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10340 we have a (neg (gt X 0)) operation. */
10342 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10343 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10344 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10345 && (code == LSHIFTRT || code == ASHIFTRT)
10346 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10347 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10348 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10351 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10354 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10355 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10362 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10363 if the truncate does not affect the value. */
10364 if (code == LSHIFTRT
10365 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10366 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10367 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10368 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10369 - GET_MODE_PRECISION (GET_MODE (varop)))))
10371 rtx varop_inner = XEXP (varop, 0);
10374 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10375 XEXP (varop_inner, 0),
10377 (count + INTVAL (XEXP (varop_inner, 1))));
10378 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10391 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10392 outer_op, outer_const);
10394 /* We have now finished analyzing the shift. The result should be
10395 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10396 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10397 to the result of the shift. OUTER_CONST is the relevant constant,
10398 but we must turn off all bits turned off in the shift. */
10400 if (outer_op == UNKNOWN
10401 && orig_code == code && orig_count == count
10402 && varop == orig_varop
10403 && shift_mode == GET_MODE (varop))
10406 /* Make a SUBREG if necessary. If we can't make it, fail. */
10407 varop = gen_lowpart (shift_mode, varop);
10408 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10411 /* If we have an outer operation and we just made a shift, it is
10412 possible that we could have simplified the shift were it not
10413 for the outer operation. So try to do the simplification
10416 if (outer_op != UNKNOWN)
10417 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10422 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10424 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10425 turn off all the bits that the shift would have turned off. */
10426 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10427 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10428 GET_MODE_MASK (result_mode) >> orig_count);
10430 /* Do the remainder of the processing in RESULT_MODE. */
10431 x = gen_lowpart_or_truncate (result_mode, x);
10433 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10436 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10438 if (outer_op != UNKNOWN)
10440 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10441 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10442 outer_const = trunc_int_for_mode (outer_const, result_mode);
10444 if (outer_op == AND)
10445 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10446 else if (outer_op == SET)
10448 /* This means that we have determined that the result is
10449 equivalent to a constant. This should be rare. */
10450 if (!side_effects_p (x))
10451 x = GEN_INT (outer_const);
10453 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10454 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10456 x = simplify_gen_binary (outer_op, result_mode, x,
10457 GEN_INT (outer_const));
10463 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10464 The result of the shift is RESULT_MODE. If we cannot simplify it,
10465 return X or, if it is NULL, synthesize the expression with
10466 simplify_gen_binary. Otherwise, return a simplified value.
10468 The shift is normally computed in the widest mode we find in VAROP, as
10469 long as it isn't a different number of words than RESULT_MODE. Exceptions
10470 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10473 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10474 rtx varop, int count)
10476 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10481 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10482 if (GET_MODE (x) != result_mode)
10483 x = gen_lowpart (result_mode, x);
10488 /* Like recog, but we receive the address of a pointer to a new pattern.
10489 We try to match the rtx that the pointer points to.
10490 If that fails, we may try to modify or replace the pattern,
10491 storing the replacement into the same pointer object.
10493 Modifications include deletion or addition of CLOBBERs.
10495 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10496 the CLOBBERs are placed.
10498 The value is the final insn code from the pattern ultimately matched,
10502 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10504 rtx pat = *pnewpat;
10505 rtx pat_without_clobbers;
10506 int insn_code_number;
10507 int num_clobbers_to_add = 0;
10509 rtx notes = NULL_RTX;
10510 rtx old_notes, old_pat;
10513 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10514 we use to indicate that something didn't match. If we find such a
10515 thing, force rejection. */
10516 if (GET_CODE (pat) == PARALLEL)
10517 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10518 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10519 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10522 old_pat = PATTERN (insn);
10523 old_notes = REG_NOTES (insn);
10524 PATTERN (insn) = pat;
10525 REG_NOTES (insn) = NULL_RTX;
10527 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10528 if (dump_file && (dump_flags & TDF_DETAILS))
10530 if (insn_code_number < 0)
10531 fputs ("Failed to match this instruction:\n", dump_file);
10533 fputs ("Successfully matched this instruction:\n", dump_file);
10534 print_rtl_single (dump_file, pat);
10537 /* If it isn't, there is the possibility that we previously had an insn
10538 that clobbered some register as a side effect, but the combined
10539 insn doesn't need to do that. So try once more without the clobbers
10540 unless this represents an ASM insn. */
10542 if (insn_code_number < 0 && ! check_asm_operands (pat)
10543 && GET_CODE (pat) == PARALLEL)
10547 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10548 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10551 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10555 SUBST_INT (XVECLEN (pat, 0), pos);
10558 pat = XVECEXP (pat, 0, 0);
10560 PATTERN (insn) = pat;
10561 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10562 if (dump_file && (dump_flags & TDF_DETAILS))
10564 if (insn_code_number < 0)
10565 fputs ("Failed to match this instruction:\n", dump_file);
10567 fputs ("Successfully matched this instruction:\n", dump_file);
10568 print_rtl_single (dump_file, pat);
10572 pat_without_clobbers = pat;
10574 PATTERN (insn) = old_pat;
10575 REG_NOTES (insn) = old_notes;
10577 /* Recognize all noop sets, these will be killed by followup pass. */
10578 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10579 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10581 /* If we had any clobbers to add, make a new pattern than contains
10582 them. Then check to make sure that all of them are dead. */
10583 if (num_clobbers_to_add)
10585 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10586 rtvec_alloc (GET_CODE (pat) == PARALLEL
10587 ? (XVECLEN (pat, 0)
10588 + num_clobbers_to_add)
10589 : num_clobbers_to_add + 1));
10591 if (GET_CODE (pat) == PARALLEL)
10592 for (i = 0; i < XVECLEN (pat, 0); i++)
10593 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10595 XVECEXP (newpat, 0, 0) = pat;
10597 add_clobbers (newpat, insn_code_number);
10599 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10600 i < XVECLEN (newpat, 0); i++)
10602 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10603 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10605 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10607 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10608 notes = alloc_reg_note (REG_UNUSED,
10609 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10615 if (insn_code_number >= 0
10616 && insn_code_number != NOOP_MOVE_INSN_CODE)
10618 old_pat = PATTERN (insn);
10619 old_notes = REG_NOTES (insn);
10620 old_icode = INSN_CODE (insn);
10621 PATTERN (insn) = pat;
10622 REG_NOTES (insn) = notes;
10624 /* Allow targets to reject combined insn. */
10625 if (!targetm.legitimate_combined_insn (insn))
10627 if (dump_file && (dump_flags & TDF_DETAILS))
10628 fputs ("Instruction not appropriate for target.",
10631 /* Callers expect recog_for_combine to strip
10632 clobbers from the pattern on failure. */
10633 pat = pat_without_clobbers;
10636 insn_code_number = -1;
10639 PATTERN (insn) = old_pat;
10640 REG_NOTES (insn) = old_notes;
10641 INSN_CODE (insn) = old_icode;
10647 return insn_code_number;
10650 /* Like gen_lowpart_general but for use by combine. In combine it
10651 is not possible to create any new pseudoregs. However, it is
10652 safe to create invalid memory addresses, because combine will
10653 try to recognize them and all they will do is make the combine
10656 If for some reason this cannot do its job, an rtx
10657 (clobber (const_int 0)) is returned.
10658 An insn containing that will not be recognized. */
10661 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10663 enum machine_mode imode = GET_MODE (x);
10664 unsigned int osize = GET_MODE_SIZE (omode);
10665 unsigned int isize = GET_MODE_SIZE (imode);
10668 if (omode == imode)
10671 /* We can only support MODE being wider than a word if X is a
10672 constant integer or has a mode the same size. */
10673 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10674 && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10677 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10678 won't know what to do. So we will strip off the SUBREG here and
10679 process normally. */
10680 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10682 x = SUBREG_REG (x);
10684 /* For use in case we fall down into the address adjustments
10685 further below, we need to adjust the known mode and size of
10686 x; imode and isize, since we just adjusted x. */
10687 imode = GET_MODE (x);
10689 if (imode == omode)
10692 isize = GET_MODE_SIZE (imode);
10695 result = gen_lowpart_common (omode, x);
10704 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10706 if (MEM_VOLATILE_P (x)
10707 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10710 /* If we want to refer to something bigger than the original memref,
10711 generate a paradoxical subreg instead. That will force a reload
10712 of the original memref X. */
10714 return gen_rtx_SUBREG (omode, x, 0);
10716 if (WORDS_BIG_ENDIAN)
10717 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10719 /* Adjust the address so that the address-after-the-data is
10721 if (BYTES_BIG_ENDIAN)
10722 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10724 return adjust_address_nv (x, omode, offset);
10727 /* If X is a comparison operator, rewrite it in a new mode. This
10728 probably won't match, but may allow further simplifications. */
10729 else if (COMPARISON_P (x))
10730 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10732 /* If we couldn't simplify X any other way, just enclose it in a
10733 SUBREG. Normally, this SUBREG won't match, but some patterns may
10734 include an explicit SUBREG or we may simplify it further in combine. */
10740 offset = subreg_lowpart_offset (omode, imode);
10741 if (imode == VOIDmode)
10743 imode = int_mode_for_mode (omode);
10744 x = gen_lowpart_common (imode, x);
10748 res = simplify_gen_subreg (omode, x, imode, offset);
10754 return gen_rtx_CLOBBER (omode, const0_rtx);
10757 /* Try to simplify a comparison between OP0 and a constant OP1,
10758 where CODE is the comparison code that will be tested, into a
10759 (CODE OP0 const0_rtx) form.
10761 The result is a possibly different comparison code to use.
10762 *POP1 may be updated. */
10764 static enum rtx_code
10765 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10767 enum machine_mode mode = GET_MODE (op0);
10768 unsigned int mode_width = GET_MODE_PRECISION (mode);
10769 HOST_WIDE_INT const_op = INTVAL (*pop1);
10771 /* Get the constant we are comparing against and turn off all bits
10772 not on in our mode. */
10773 if (mode != VOIDmode)
10774 const_op = trunc_int_for_mode (const_op, mode);
10776 /* If we are comparing against a constant power of two and the value
10777 being compared can only have that single bit nonzero (e.g., it was
10778 `and'ed with that bit), we can replace this with a comparison
10781 && (code == EQ || code == NE || code == GE || code == GEU
10782 || code == LT || code == LTU)
10783 && mode_width <= HOST_BITS_PER_WIDE_INT
10784 && exact_log2 (const_op) >= 0
10785 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10787 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10791 /* Similarly, if we are comparing a value known to be either -1 or
10792 0 with -1, change it to the opposite comparison against zero. */
10794 && (code == EQ || code == NE || code == GT || code == LE
10795 || code == GEU || code == LTU)
10796 && num_sign_bit_copies (op0, mode) == mode_width)
10798 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10802 /* Do some canonicalizations based on the comparison code. We prefer
10803 comparisons against zero and then prefer equality comparisons.
10804 If we can reduce the size of a constant, we will do that too. */
10808 /* < C is equivalent to <= (C - 1) */
10813 /* ... fall through to LE case below. */
10819 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10826 /* If we are doing a <= 0 comparison on a value known to have
10827 a zero sign bit, we can replace this with == 0. */
10828 else if (const_op == 0
10829 && mode_width <= HOST_BITS_PER_WIDE_INT
10830 && (nonzero_bits (op0, mode)
10831 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10837 /* >= C is equivalent to > (C - 1). */
10842 /* ... fall through to GT below. */
10848 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10855 /* If we are doing a > 0 comparison on a value known to have
10856 a zero sign bit, we can replace this with != 0. */
10857 else if (const_op == 0
10858 && mode_width <= HOST_BITS_PER_WIDE_INT
10859 && (nonzero_bits (op0, mode)
10860 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10866 /* < C is equivalent to <= (C - 1). */
10871 /* ... fall through ... */
10873 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10874 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10875 && (unsigned HOST_WIDE_INT) const_op
10876 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10886 /* unsigned <= 0 is equivalent to == 0 */
10889 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10890 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10891 && (unsigned HOST_WIDE_INT) const_op
10892 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10900 /* >= C is equivalent to > (C - 1). */
10905 /* ... fall through ... */
10908 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10909 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10910 && (unsigned HOST_WIDE_INT) const_op
10911 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10921 /* unsigned > 0 is equivalent to != 0 */
10924 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10925 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10926 && (unsigned HOST_WIDE_INT) const_op
10927 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10938 *pop1 = GEN_INT (const_op);
10942 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10943 comparison code that will be tested.
10945 The result is a possibly different comparison code to use. *POP0 and
10946 *POP1 may be updated.
10948 It is possible that we might detect that a comparison is either always
10949 true or always false. However, we do not perform general constant
10950 folding in combine, so this knowledge isn't useful. Such tautologies
10951 should have been detected earlier. Hence we ignore all such cases. */
10953 static enum rtx_code
10954 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10960 enum machine_mode mode, tmode;
10962 /* Try a few ways of applying the same transformation to both operands. */
10965 #ifndef WORD_REGISTER_OPERATIONS
10966 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10967 so check specially. */
10968 if (code != GTU && code != GEU && code != LTU && code != LEU
10969 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10970 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10971 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10972 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10973 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10974 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10975 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10976 && CONST_INT_P (XEXP (op0, 1))
10977 && XEXP (op0, 1) == XEXP (op1, 1)
10978 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10979 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10980 && (INTVAL (XEXP (op0, 1))
10981 == (GET_MODE_PRECISION (GET_MODE (op0))
10982 - (GET_MODE_PRECISION
10983 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10985 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10986 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10990 /* If both operands are the same constant shift, see if we can ignore the
10991 shift. We can if the shift is a rotate or if the bits shifted out of
10992 this shift are known to be zero for both inputs and if the type of
10993 comparison is compatible with the shift. */
10994 if (GET_CODE (op0) == GET_CODE (op1)
10995 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
10996 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10997 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10998 && (code != GT && code != LT && code != GE && code != LE))
10999 || (GET_CODE (op0) == ASHIFTRT
11000 && (code != GTU && code != LTU
11001 && code != GEU && code != LEU)))
11002 && CONST_INT_P (XEXP (op0, 1))
11003 && INTVAL (XEXP (op0, 1)) >= 0
11004 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11005 && XEXP (op0, 1) == XEXP (op1, 1))
11007 enum machine_mode mode = GET_MODE (op0);
11008 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11009 int shift_count = INTVAL (XEXP (op0, 1));
11011 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11012 mask &= (mask >> shift_count) << shift_count;
11013 else if (GET_CODE (op0) == ASHIFT)
11014 mask = (mask & (mask << shift_count)) >> shift_count;
11016 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11017 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11018 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11023 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11024 SUBREGs are of the same mode, and, in both cases, the AND would
11025 be redundant if the comparison was done in the narrower mode,
11026 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11027 and the operand's possibly nonzero bits are 0xffffff01; in that case
11028 if we only care about QImode, we don't need the AND). This case
11029 occurs if the output mode of an scc insn is not SImode and
11030 STORE_FLAG_VALUE == 1 (e.g., the 386).
11032 Similarly, check for a case where the AND's are ZERO_EXTEND
11033 operations from some narrower mode even though a SUBREG is not
11036 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11037 && CONST_INT_P (XEXP (op0, 1))
11038 && CONST_INT_P (XEXP (op1, 1)))
11040 rtx inner_op0 = XEXP (op0, 0);
11041 rtx inner_op1 = XEXP (op1, 0);
11042 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11043 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11046 if (paradoxical_subreg_p (inner_op0)
11047 && GET_CODE (inner_op1) == SUBREG
11048 && (GET_MODE (SUBREG_REG (inner_op0))
11049 == GET_MODE (SUBREG_REG (inner_op1)))
11050 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11051 <= HOST_BITS_PER_WIDE_INT)
11052 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11053 GET_MODE (SUBREG_REG (inner_op0)))))
11054 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11055 GET_MODE (SUBREG_REG (inner_op1))))))
11057 op0 = SUBREG_REG (inner_op0);
11058 op1 = SUBREG_REG (inner_op1);
11060 /* The resulting comparison is always unsigned since we masked
11061 off the original sign bit. */
11062 code = unsigned_condition (code);
11068 for (tmode = GET_CLASS_NARROWEST_MODE
11069 (GET_MODE_CLASS (GET_MODE (op0)));
11070 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11071 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11073 op0 = gen_lowpart (tmode, inner_op0);
11074 op1 = gen_lowpart (tmode, inner_op1);
11075 code = unsigned_condition (code);
11084 /* If both operands are NOT, we can strip off the outer operation
11085 and adjust the comparison code for swapped operands; similarly for
11086 NEG, except that this must be an equality comparison. */
11087 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11088 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11089 && (code == EQ || code == NE)))
11090 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11096 /* If the first operand is a constant, swap the operands and adjust the
11097 comparison code appropriately, but don't do this if the second operand
11098 is already a constant integer. */
11099 if (swap_commutative_operands_p (op0, op1))
11101 tem = op0, op0 = op1, op1 = tem;
11102 code = swap_condition (code);
11105 /* We now enter a loop during which we will try to simplify the comparison.
11106 For the most part, we only are concerned with comparisons with zero,
11107 but some things may really be comparisons with zero but not start
11108 out looking that way. */
11110 while (CONST_INT_P (op1))
11112 enum machine_mode mode = GET_MODE (op0);
11113 unsigned int mode_width = GET_MODE_PRECISION (mode);
11114 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11115 int equality_comparison_p;
11116 int sign_bit_comparison_p;
11117 int unsigned_comparison_p;
11118 HOST_WIDE_INT const_op;
11120 /* We only want to handle integral modes. This catches VOIDmode,
11121 CCmode, and the floating-point modes. An exception is that we
11122 can handle VOIDmode if OP0 is a COMPARE or a comparison
11125 if (GET_MODE_CLASS (mode) != MODE_INT
11126 && ! (mode == VOIDmode
11127 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11130 /* Try to simplify the compare to constant, possibly changing the
11131 comparison op, and/or changing op1 to zero. */
11132 code = simplify_compare_const (code, op0, &op1);
11133 const_op = INTVAL (op1);
11135 /* Compute some predicates to simplify code below. */
11137 equality_comparison_p = (code == EQ || code == NE);
11138 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11139 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11142 /* If this is a sign bit comparison and we can do arithmetic in
11143 MODE, say that we will only be needing the sign bit of OP0. */
11144 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11145 op0 = force_to_mode (op0, mode,
11146 (unsigned HOST_WIDE_INT) 1
11147 << (GET_MODE_PRECISION (mode) - 1),
11150 /* Now try cases based on the opcode of OP0. If none of the cases
11151 does a "continue", we exit this loop immediately after the
11154 switch (GET_CODE (op0))
11157 /* If we are extracting a single bit from a variable position in
11158 a constant that has only a single bit set and are comparing it
11159 with zero, we can convert this into an equality comparison
11160 between the position and the location of the single bit. */
11161 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11162 have already reduced the shift count modulo the word size. */
11163 if (!SHIFT_COUNT_TRUNCATED
11164 && CONST_INT_P (XEXP (op0, 0))
11165 && XEXP (op0, 1) == const1_rtx
11166 && equality_comparison_p && const_op == 0
11167 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11169 if (BITS_BIG_ENDIAN)
11170 i = BITS_PER_WORD - 1 - i;
11172 op0 = XEXP (op0, 2);
11176 /* Result is nonzero iff shift count is equal to I. */
11177 code = reverse_condition (code);
11181 /* ... fall through ... */
11184 tem = expand_compound_operation (op0);
11193 /* If testing for equality, we can take the NOT of the constant. */
11194 if (equality_comparison_p
11195 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11197 op0 = XEXP (op0, 0);
11202 /* If just looking at the sign bit, reverse the sense of the
11204 if (sign_bit_comparison_p)
11206 op0 = XEXP (op0, 0);
11207 code = (code == GE ? LT : GE);
11213 /* If testing for equality, we can take the NEG of the constant. */
11214 if (equality_comparison_p
11215 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11217 op0 = XEXP (op0, 0);
11222 /* The remaining cases only apply to comparisons with zero. */
11226 /* When X is ABS or is known positive,
11227 (neg X) is < 0 if and only if X != 0. */
11229 if (sign_bit_comparison_p
11230 && (GET_CODE (XEXP (op0, 0)) == ABS
11231 || (mode_width <= HOST_BITS_PER_WIDE_INT
11232 && (nonzero_bits (XEXP (op0, 0), mode)
11233 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11236 op0 = XEXP (op0, 0);
11237 code = (code == LT ? NE : EQ);
11241 /* If we have NEG of something whose two high-order bits are the
11242 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11243 if (num_sign_bit_copies (op0, mode) >= 2)
11245 op0 = XEXP (op0, 0);
11246 code = swap_condition (code);
11252 /* If we are testing equality and our count is a constant, we
11253 can perform the inverse operation on our RHS. */
11254 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11255 && (tem = simplify_binary_operation (ROTATERT, mode,
11256 op1, XEXP (op0, 1))) != 0)
11258 op0 = XEXP (op0, 0);
11263 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11264 a particular bit. Convert it to an AND of a constant of that
11265 bit. This will be converted into a ZERO_EXTRACT. */
11266 if (const_op == 0 && sign_bit_comparison_p
11267 && CONST_INT_P (XEXP (op0, 1))
11268 && mode_width <= HOST_BITS_PER_WIDE_INT)
11270 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11271 ((unsigned HOST_WIDE_INT) 1
11273 - INTVAL (XEXP (op0, 1)))));
11274 code = (code == LT ? NE : EQ);
11278 /* Fall through. */
11281 /* ABS is ignorable inside an equality comparison with zero. */
11282 if (const_op == 0 && equality_comparison_p)
11284 op0 = XEXP (op0, 0);
11290 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11291 (compare FOO CONST) if CONST fits in FOO's mode and we
11292 are either testing inequality or have an unsigned
11293 comparison with ZERO_EXTEND or a signed comparison with
11294 SIGN_EXTEND. But don't do it if we don't have a compare
11295 insn of the given mode, since we'd have to revert it
11296 later on, and then we wouldn't know whether to sign- or
11298 mode = GET_MODE (XEXP (op0, 0));
11299 if (GET_MODE_CLASS (mode) == MODE_INT
11300 && ! unsigned_comparison_p
11301 && HWI_COMPUTABLE_MODE_P (mode)
11302 && trunc_int_for_mode (const_op, mode) == const_op
11303 && have_insn_for (COMPARE, mode))
11305 op0 = XEXP (op0, 0);
11311 /* Check for the case where we are comparing A - C1 with C2, that is
11313 (subreg:MODE (plus (A) (-C1))) op (C2)
11315 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11316 comparison in the wider mode. One of the following two conditions
11317 must be true in order for this to be valid:
11319 1. The mode extension results in the same bit pattern being added
11320 on both sides and the comparison is equality or unsigned. As
11321 C2 has been truncated to fit in MODE, the pattern can only be
11324 2. The mode extension results in the sign bit being copied on
11327 The difficulty here is that we have predicates for A but not for
11328 (A - C1) so we need to check that C1 is within proper bounds so
11329 as to perturbate A as little as possible. */
11331 if (mode_width <= HOST_BITS_PER_WIDE_INT
11332 && subreg_lowpart_p (op0)
11333 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11334 && GET_CODE (SUBREG_REG (op0)) == PLUS
11335 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11337 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11338 rtx a = XEXP (SUBREG_REG (op0), 0);
11339 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11342 && (unsigned HOST_WIDE_INT) c1
11343 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11344 && (equality_comparison_p || unsigned_comparison_p)
11345 /* (A - C1) zero-extends if it is positive and sign-extends
11346 if it is negative, C2 both zero- and sign-extends. */
11347 && ((0 == (nonzero_bits (a, inner_mode)
11348 & ~GET_MODE_MASK (mode))
11350 /* (A - C1) sign-extends if it is positive and 1-extends
11351 if it is negative, C2 both sign- and 1-extends. */
11352 || (num_sign_bit_copies (a, inner_mode)
11353 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11356 || ((unsigned HOST_WIDE_INT) c1
11357 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11358 /* (A - C1) always sign-extends, like C2. */
11359 && num_sign_bit_copies (a, inner_mode)
11360 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11361 - (mode_width - 1))))
11363 op0 = SUBREG_REG (op0);
11368 /* If the inner mode is narrower and we are extracting the low part,
11369 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11370 if (subreg_lowpart_p (op0)
11371 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11372 /* Fall through */ ;
11376 /* ... fall through ... */
11379 mode = GET_MODE (XEXP (op0, 0));
11380 if (GET_MODE_CLASS (mode) == MODE_INT
11381 && (unsigned_comparison_p || equality_comparison_p)
11382 && HWI_COMPUTABLE_MODE_P (mode)
11383 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11385 && have_insn_for (COMPARE, mode))
11387 op0 = XEXP (op0, 0);
11393 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11394 this for equality comparisons due to pathological cases involving
11396 if (equality_comparison_p
11397 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11398 op1, XEXP (op0, 1))))
11400 op0 = XEXP (op0, 0);
11405 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11406 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11407 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11409 op0 = XEXP (XEXP (op0, 0), 0);
11410 code = (code == LT ? EQ : NE);
11416 /* We used to optimize signed comparisons against zero, but that
11417 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11418 arrive here as equality comparisons, or (GEU, LTU) are
11419 optimized away. No need to special-case them. */
11421 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11422 (eq B (minus A C)), whichever simplifies. We can only do
11423 this for equality comparisons due to pathological cases involving
11425 if (equality_comparison_p
11426 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11427 XEXP (op0, 1), op1)))
11429 op0 = XEXP (op0, 0);
11434 if (equality_comparison_p
11435 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11436 XEXP (op0, 0), op1)))
11438 op0 = XEXP (op0, 1);
11443 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11444 of bits in X minus 1, is one iff X > 0. */
11445 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11446 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11447 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11448 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11450 op0 = XEXP (op0, 1);
11451 code = (code == GE ? LE : GT);
11457 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11458 if C is zero or B is a constant. */
11459 if (equality_comparison_p
11460 && 0 != (tem = simplify_binary_operation (XOR, mode,
11461 XEXP (op0, 1), op1)))
11463 op0 = XEXP (op0, 0);
11470 case UNEQ: case LTGT:
11471 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11472 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11473 case UNORDERED: case ORDERED:
11474 /* We can't do anything if OP0 is a condition code value, rather
11475 than an actual data value. */
11477 || CC0_P (XEXP (op0, 0))
11478 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11481 /* Get the two operands being compared. */
11482 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11483 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11485 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11487 /* Check for the cases where we simply want the result of the
11488 earlier test or the opposite of that result. */
11489 if (code == NE || code == EQ
11490 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11491 && (code == LT || code == GE)))
11493 enum rtx_code new_code;
11494 if (code == LT || code == NE)
11495 new_code = GET_CODE (op0);
11497 new_code = reversed_comparison_code (op0, NULL);
11499 if (new_code != UNKNOWN)
11510 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11512 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11513 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11514 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11516 op0 = XEXP (op0, 1);
11517 code = (code == GE ? GT : LE);
11523 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11524 will be converted to a ZERO_EXTRACT later. */
11525 if (const_op == 0 && equality_comparison_p
11526 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11527 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11529 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11530 XEXP (XEXP (op0, 0), 1));
11531 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11535 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11536 zero and X is a comparison and C1 and C2 describe only bits set
11537 in STORE_FLAG_VALUE, we can compare with X. */
11538 if (const_op == 0 && equality_comparison_p
11539 && mode_width <= HOST_BITS_PER_WIDE_INT
11540 && CONST_INT_P (XEXP (op0, 1))
11541 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11542 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11543 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11544 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11546 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11547 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11548 if ((~STORE_FLAG_VALUE & mask) == 0
11549 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11550 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11551 && COMPARISON_P (tem))))
11553 op0 = XEXP (XEXP (op0, 0), 0);
11558 /* If we are doing an equality comparison of an AND of a bit equal
11559 to the sign bit, replace this with a LT or GE comparison of
11560 the underlying value. */
11561 if (equality_comparison_p
11563 && CONST_INT_P (XEXP (op0, 1))
11564 && mode_width <= HOST_BITS_PER_WIDE_INT
11565 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11566 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11568 op0 = XEXP (op0, 0);
11569 code = (code == EQ ? GE : LT);
11573 /* If this AND operation is really a ZERO_EXTEND from a narrower
11574 mode, the constant fits within that mode, and this is either an
11575 equality or unsigned comparison, try to do this comparison in
11580 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11581 -> (ne:DI (reg:SI 4) (const_int 0))
11583 unless TRULY_NOOP_TRUNCATION allows it or the register is
11584 known to hold a value of the required mode the
11585 transformation is invalid. */
11586 if ((equality_comparison_p || unsigned_comparison_p)
11587 && CONST_INT_P (XEXP (op0, 1))
11588 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11589 & GET_MODE_MASK (mode))
11591 && const_op >> i == 0
11592 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11593 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11594 || (REG_P (XEXP (op0, 0))
11595 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11597 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11601 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11602 fits in both M1 and M2 and the SUBREG is either paradoxical
11603 or represents the low part, permute the SUBREG and the AND
11605 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11607 unsigned HOST_WIDE_INT c1;
11608 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11609 /* Require an integral mode, to avoid creating something like
11611 if (SCALAR_INT_MODE_P (tmode)
11612 /* It is unsafe to commute the AND into the SUBREG if the
11613 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11614 not defined. As originally written the upper bits
11615 have a defined value due to the AND operation.
11616 However, if we commute the AND inside the SUBREG then
11617 they no longer have defined values and the meaning of
11618 the code has been changed. */
11620 #ifdef WORD_REGISTER_OPERATIONS
11621 || (mode_width > GET_MODE_PRECISION (tmode)
11622 && mode_width <= BITS_PER_WORD)
11624 || (mode_width <= GET_MODE_PRECISION (tmode)
11625 && subreg_lowpart_p (XEXP (op0, 0))))
11626 && CONST_INT_P (XEXP (op0, 1))
11627 && mode_width <= HOST_BITS_PER_WIDE_INT
11628 && HWI_COMPUTABLE_MODE_P (tmode)
11629 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11630 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11632 && c1 != GET_MODE_MASK (tmode))
11634 op0 = simplify_gen_binary (AND, tmode,
11635 SUBREG_REG (XEXP (op0, 0)),
11636 gen_int_mode (c1, tmode));
11637 op0 = gen_lowpart (mode, op0);
11642 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11643 if (const_op == 0 && equality_comparison_p
11644 && XEXP (op0, 1) == const1_rtx
11645 && GET_CODE (XEXP (op0, 0)) == NOT)
11647 op0 = simplify_and_const_int (NULL_RTX, mode,
11648 XEXP (XEXP (op0, 0), 0), 1);
11649 code = (code == NE ? EQ : NE);
11653 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11654 (eq (and (lshiftrt X) 1) 0).
11655 Also handle the case where (not X) is expressed using xor. */
11656 if (const_op == 0 && equality_comparison_p
11657 && XEXP (op0, 1) == const1_rtx
11658 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11660 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11661 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11663 if (GET_CODE (shift_op) == NOT
11664 || (GET_CODE (shift_op) == XOR
11665 && CONST_INT_P (XEXP (shift_op, 1))
11666 && CONST_INT_P (shift_count)
11667 && HWI_COMPUTABLE_MODE_P (mode)
11668 && (UINTVAL (XEXP (shift_op, 1))
11669 == (unsigned HOST_WIDE_INT) 1
11670 << INTVAL (shift_count))))
11673 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11674 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11675 code = (code == NE ? EQ : NE);
11682 /* If we have (compare (ashift FOO N) (const_int C)) and
11683 the high order N bits of FOO (N+1 if an inequality comparison)
11684 are known to be zero, we can do this by comparing FOO with C
11685 shifted right N bits so long as the low-order N bits of C are
11687 if (CONST_INT_P (XEXP (op0, 1))
11688 && INTVAL (XEXP (op0, 1)) >= 0
11689 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11690 < HOST_BITS_PER_WIDE_INT)
11691 && (((unsigned HOST_WIDE_INT) const_op
11692 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11694 && mode_width <= HOST_BITS_PER_WIDE_INT
11695 && (nonzero_bits (XEXP (op0, 0), mode)
11696 & ~(mask >> (INTVAL (XEXP (op0, 1))
11697 + ! equality_comparison_p))) == 0)
11699 /* We must perform a logical shift, not an arithmetic one,
11700 as we want the top N bits of C to be zero. */
11701 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11703 temp >>= INTVAL (XEXP (op0, 1));
11704 op1 = gen_int_mode (temp, mode);
11705 op0 = XEXP (op0, 0);
11709 /* If we are doing a sign bit comparison, it means we are testing
11710 a particular bit. Convert it to the appropriate AND. */
11711 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11712 && mode_width <= HOST_BITS_PER_WIDE_INT)
11714 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11715 ((unsigned HOST_WIDE_INT) 1
11717 - INTVAL (XEXP (op0, 1)))));
11718 code = (code == LT ? NE : EQ);
11722 /* If this an equality comparison with zero and we are shifting
11723 the low bit to the sign bit, we can convert this to an AND of the
11725 if (const_op == 0 && equality_comparison_p
11726 && CONST_INT_P (XEXP (op0, 1))
11727 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11729 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11735 /* If this is an equality comparison with zero, we can do this
11736 as a logical shift, which might be much simpler. */
11737 if (equality_comparison_p && const_op == 0
11738 && CONST_INT_P (XEXP (op0, 1)))
11740 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11742 INTVAL (XEXP (op0, 1)));
11746 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11747 do the comparison in a narrower mode. */
11748 if (! unsigned_comparison_p
11749 && CONST_INT_P (XEXP (op0, 1))
11750 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11751 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11752 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11753 MODE_INT, 1)) != BLKmode
11754 && (((unsigned HOST_WIDE_INT) const_op
11755 + (GET_MODE_MASK (tmode) >> 1) + 1)
11756 <= GET_MODE_MASK (tmode)))
11758 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11762 /* Likewise if OP0 is a PLUS of a sign extension with a
11763 constant, which is usually represented with the PLUS
11764 between the shifts. */
11765 if (! unsigned_comparison_p
11766 && CONST_INT_P (XEXP (op0, 1))
11767 && GET_CODE (XEXP (op0, 0)) == PLUS
11768 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11769 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11770 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11771 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11772 MODE_INT, 1)) != BLKmode
11773 && (((unsigned HOST_WIDE_INT) const_op
11774 + (GET_MODE_MASK (tmode) >> 1) + 1)
11775 <= GET_MODE_MASK (tmode)))
11777 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11778 rtx add_const = XEXP (XEXP (op0, 0), 1);
11779 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11780 add_const, XEXP (op0, 1));
11782 op0 = simplify_gen_binary (PLUS, tmode,
11783 gen_lowpart (tmode, inner),
11788 /* ... fall through ... */
11790 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11791 the low order N bits of FOO are known to be zero, we can do this
11792 by comparing FOO with C shifted left N bits so long as no
11793 overflow occurs. Even if the low order N bits of FOO aren't known
11794 to be zero, if the comparison is >= or < we can use the same
11795 optimization and for > or <= by setting all the low
11796 order N bits in the comparison constant. */
11797 if (CONST_INT_P (XEXP (op0, 1))
11798 && INTVAL (XEXP (op0, 1)) > 0
11799 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11800 && mode_width <= HOST_BITS_PER_WIDE_INT
11801 && (((unsigned HOST_WIDE_INT) const_op
11802 + (GET_CODE (op0) != LSHIFTRT
11803 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11806 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11808 unsigned HOST_WIDE_INT low_bits
11809 = (nonzero_bits (XEXP (op0, 0), mode)
11810 & (((unsigned HOST_WIDE_INT) 1
11811 << INTVAL (XEXP (op0, 1))) - 1));
11812 if (low_bits == 0 || !equality_comparison_p)
11814 /* If the shift was logical, then we must make the condition
11816 if (GET_CODE (op0) == LSHIFTRT)
11817 code = unsigned_condition (code);
11819 const_op <<= INTVAL (XEXP (op0, 1));
11821 && (code == GT || code == GTU
11822 || code == LE || code == LEU))
11824 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11825 op1 = GEN_INT (const_op);
11826 op0 = XEXP (op0, 0);
11831 /* If we are using this shift to extract just the sign bit, we
11832 can replace this with an LT or GE comparison. */
11834 && (equality_comparison_p || sign_bit_comparison_p)
11835 && CONST_INT_P (XEXP (op0, 1))
11836 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11838 op0 = XEXP (op0, 0);
11839 code = (code == NE || code == GT ? LT : GE);
11851 /* Now make any compound operations involved in this comparison. Then,
11852 check for an outmost SUBREG on OP0 that is not doing anything or is
11853 paradoxical. The latter transformation must only be performed when
11854 it is known that the "extra" bits will be the same in op0 and op1 or
11855 that they don't matter. There are three cases to consider:
11857 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11858 care bits and we can assume they have any convenient value. So
11859 making the transformation is safe.
11861 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11862 In this case the upper bits of op0 are undefined. We should not make
11863 the simplification in that case as we do not know the contents of
11866 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11867 UNKNOWN. In that case we know those bits are zeros or ones. We must
11868 also be sure that they are the same as the upper bits of op1.
11870 We can never remove a SUBREG for a non-equality comparison because
11871 the sign bit is in a different place in the underlying object. */
11873 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11874 op1 = make_compound_operation (op1, SET);
11876 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11877 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11878 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11879 && (code == NE || code == EQ))
11881 if (paradoxical_subreg_p (op0))
11883 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11885 if (REG_P (SUBREG_REG (op0)))
11887 op0 = SUBREG_REG (op0);
11888 op1 = gen_lowpart (GET_MODE (op0), op1);
11891 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11892 <= HOST_BITS_PER_WIDE_INT)
11893 && (nonzero_bits (SUBREG_REG (op0),
11894 GET_MODE (SUBREG_REG (op0)))
11895 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11897 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11899 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11900 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11901 op0 = SUBREG_REG (op0), op1 = tem;
11905 /* We now do the opposite procedure: Some machines don't have compare
11906 insns in all modes. If OP0's mode is an integer mode smaller than a
11907 word and we can't do a compare in that mode, see if there is a larger
11908 mode for which we can do the compare. There are a number of cases in
11909 which we can use the wider mode. */
11911 mode = GET_MODE (op0);
11912 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11913 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11914 && ! have_insn_for (COMPARE, mode))
11915 for (tmode = GET_MODE_WIDER_MODE (mode);
11916 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11917 tmode = GET_MODE_WIDER_MODE (tmode))
11918 if (have_insn_for (COMPARE, tmode))
11922 /* If this is a test for negative, we can make an explicit
11923 test of the sign bit. Test this first so we can use
11924 a paradoxical subreg to extend OP0. */
11926 if (op1 == const0_rtx && (code == LT || code == GE)
11927 && HWI_COMPUTABLE_MODE_P (mode))
11929 op0 = simplify_gen_binary (AND, tmode,
11930 gen_lowpart (tmode, op0),
11931 GEN_INT ((unsigned HOST_WIDE_INT) 1
11932 << (GET_MODE_BITSIZE (mode)
11934 code = (code == LT) ? NE : EQ;
11938 /* If the only nonzero bits in OP0 and OP1 are those in the
11939 narrower mode and this is an equality or unsigned comparison,
11940 we can use the wider mode. Similarly for sign-extended
11941 values, in which case it is true for all comparisons. */
11942 zero_extended = ((code == EQ || code == NE
11943 || code == GEU || code == GTU
11944 || code == LEU || code == LTU)
11945 && (nonzero_bits (op0, tmode)
11946 & ~GET_MODE_MASK (mode)) == 0
11947 && ((CONST_INT_P (op1)
11948 || (nonzero_bits (op1, tmode)
11949 & ~GET_MODE_MASK (mode)) == 0)));
11952 || ((num_sign_bit_copies (op0, tmode)
11953 > (unsigned int) (GET_MODE_PRECISION (tmode)
11954 - GET_MODE_PRECISION (mode)))
11955 && (num_sign_bit_copies (op1, tmode)
11956 > (unsigned int) (GET_MODE_PRECISION (tmode)
11957 - GET_MODE_PRECISION (mode)))))
11959 /* If OP0 is an AND and we don't have an AND in MODE either,
11960 make a new AND in the proper mode. */
11961 if (GET_CODE (op0) == AND
11962 && !have_insn_for (AND, mode))
11963 op0 = simplify_gen_binary (AND, tmode,
11964 gen_lowpart (tmode,
11966 gen_lowpart (tmode,
11972 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11973 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11977 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11978 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11985 /* If this machine only supports a subset of valid comparisons, see if we
11986 can convert an unsupported one into a supported one. */
11987 target_canonicalize_comparison (&code, &op0, &op1, 0);
11995 /* Utility function for record_value_for_reg. Count number of
12000 enum rtx_code code = GET_CODE (x);
12004 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12005 || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12007 rtx x0 = XEXP (x, 0);
12008 rtx x1 = XEXP (x, 1);
12011 return 1 + 2 * count_rtxs (x0);
12013 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12014 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12015 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12016 return 2 + 2 * count_rtxs (x0)
12017 + count_rtxs (x == XEXP (x1, 0)
12018 ? XEXP (x1, 1) : XEXP (x1, 0));
12020 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12021 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12022 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12023 return 2 + 2 * count_rtxs (x1)
12024 + count_rtxs (x == XEXP (x0, 0)
12025 ? XEXP (x0, 1) : XEXP (x0, 0));
12028 fmt = GET_RTX_FORMAT (code);
12029 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12031 ret += count_rtxs (XEXP (x, i));
12032 else if (fmt[i] == 'E')
12033 for (j = 0; j < XVECLEN (x, i); j++)
12034 ret += count_rtxs (XVECEXP (x, i, j));
12039 /* Utility function for following routine. Called when X is part of a value
12040 being stored into last_set_value. Sets last_set_table_tick
12041 for each register mentioned. Similar to mention_regs in cse.c */
12044 update_table_tick (rtx x)
12046 enum rtx_code code = GET_CODE (x);
12047 const char *fmt = GET_RTX_FORMAT (code);
12052 unsigned int regno = REGNO (x);
12053 unsigned int endregno = END_REGNO (x);
12056 for (r = regno; r < endregno; r++)
12058 reg_stat_type *rsp = ®_stat[r];
12059 rsp->last_set_table_tick = label_tick;
12065 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12068 /* Check for identical subexpressions. If x contains
12069 identical subexpression we only have to traverse one of
12071 if (i == 0 && ARITHMETIC_P (x))
12073 /* Note that at this point x1 has already been
12075 rtx x0 = XEXP (x, 0);
12076 rtx x1 = XEXP (x, 1);
12078 /* If x0 and x1 are identical then there is no need to
12083 /* If x0 is identical to a subexpression of x1 then while
12084 processing x1, x0 has already been processed. Thus we
12085 are done with x. */
12086 if (ARITHMETIC_P (x1)
12087 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12090 /* If x1 is identical to a subexpression of x0 then we
12091 still have to process the rest of x0. */
12092 if (ARITHMETIC_P (x0)
12093 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12095 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12100 update_table_tick (XEXP (x, i));
12102 else if (fmt[i] == 'E')
12103 for (j = 0; j < XVECLEN (x, i); j++)
12104 update_table_tick (XVECEXP (x, i, j));
12107 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12108 are saying that the register is clobbered and we no longer know its
12109 value. If INSN is zero, don't update reg_stat[].last_set; this is
12110 only permitted with VALUE also zero and is used to invalidate the
12114 record_value_for_reg (rtx reg, rtx insn, rtx value)
12116 unsigned int regno = REGNO (reg);
12117 unsigned int endregno = END_REGNO (reg);
12119 reg_stat_type *rsp;
12121 /* If VALUE contains REG and we have a previous value for REG, substitute
12122 the previous value. */
12123 if (value && insn && reg_overlap_mentioned_p (reg, value))
12127 /* Set things up so get_last_value is allowed to see anything set up to
12129 subst_low_luid = DF_INSN_LUID (insn);
12130 tem = get_last_value (reg);
12132 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12133 it isn't going to be useful and will take a lot of time to process,
12134 so just use the CLOBBER. */
12138 if (ARITHMETIC_P (tem)
12139 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12140 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12141 tem = XEXP (tem, 0);
12142 else if (count_occurrences (value, reg, 1) >= 2)
12144 /* If there are two or more occurrences of REG in VALUE,
12145 prevent the value from growing too much. */
12146 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12147 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12150 value = replace_rtx (copy_rtx (value), reg, tem);
12154 /* For each register modified, show we don't know its value, that
12155 we don't know about its bitwise content, that its value has been
12156 updated, and that we don't know the location of the death of the
12158 for (i = regno; i < endregno; i++)
12160 rsp = ®_stat[i];
12163 rsp->last_set = insn;
12165 rsp->last_set_value = 0;
12166 rsp->last_set_mode = VOIDmode;
12167 rsp->last_set_nonzero_bits = 0;
12168 rsp->last_set_sign_bit_copies = 0;
12169 rsp->last_death = 0;
12170 rsp->truncated_to_mode = VOIDmode;
12173 /* Mark registers that are being referenced in this value. */
12175 update_table_tick (value);
12177 /* Now update the status of each register being set.
12178 If someone is using this register in this block, set this register
12179 to invalid since we will get confused between the two lives in this
12180 basic block. This makes using this register always invalid. In cse, we
12181 scan the table to invalidate all entries using this register, but this
12182 is too much work for us. */
12184 for (i = regno; i < endregno; i++)
12186 rsp = ®_stat[i];
12187 rsp->last_set_label = label_tick;
12189 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12190 rsp->last_set_invalid = 1;
12192 rsp->last_set_invalid = 0;
12195 /* The value being assigned might refer to X (like in "x++;"). In that
12196 case, we must replace it with (clobber (const_int 0)) to prevent
12198 rsp = ®_stat[regno];
12199 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12201 value = copy_rtx (value);
12202 if (!get_last_value_validate (&value, insn, label_tick, 1))
12206 /* For the main register being modified, update the value, the mode, the
12207 nonzero bits, and the number of sign bit copies. */
12209 rsp->last_set_value = value;
12213 enum machine_mode mode = GET_MODE (reg);
12214 subst_low_luid = DF_INSN_LUID (insn);
12215 rsp->last_set_mode = mode;
12216 if (GET_MODE_CLASS (mode) == MODE_INT
12217 && HWI_COMPUTABLE_MODE_P (mode))
12218 mode = nonzero_bits_mode;
12219 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12220 rsp->last_set_sign_bit_copies
12221 = num_sign_bit_copies (value, GET_MODE (reg));
12225 /* Called via note_stores from record_dead_and_set_regs to handle one
12226 SET or CLOBBER in an insn. DATA is the instruction in which the
12227 set is occurring. */
12230 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12232 rtx record_dead_insn = (rtx) data;
12234 if (GET_CODE (dest) == SUBREG)
12235 dest = SUBREG_REG (dest);
12237 if (!record_dead_insn)
12240 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12246 /* If we are setting the whole register, we know its value. Otherwise
12247 show that we don't know the value. We can handle SUBREG in
12249 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12250 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12251 else if (GET_CODE (setter) == SET
12252 && GET_CODE (SET_DEST (setter)) == SUBREG
12253 && SUBREG_REG (SET_DEST (setter)) == dest
12254 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12255 && subreg_lowpart_p (SET_DEST (setter)))
12256 record_value_for_reg (dest, record_dead_insn,
12257 gen_lowpart (GET_MODE (dest),
12258 SET_SRC (setter)));
12260 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12262 else if (MEM_P (dest)
12263 /* Ignore pushes, they clobber nothing. */
12264 && ! push_operand (dest, GET_MODE (dest)))
12265 mem_last_set = DF_INSN_LUID (record_dead_insn);
12268 /* Update the records of when each REG was most recently set or killed
12269 for the things done by INSN. This is the last thing done in processing
12270 INSN in the combiner loop.
12272 We update reg_stat[], in particular fields last_set, last_set_value,
12273 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12274 last_death, and also the similar information mem_last_set (which insn
12275 most recently modified memory) and last_call_luid (which insn was the
12276 most recent subroutine call). */
12279 record_dead_and_set_regs (rtx insn)
12284 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12286 if (REG_NOTE_KIND (link) == REG_DEAD
12287 && REG_P (XEXP (link, 0)))
12289 unsigned int regno = REGNO (XEXP (link, 0));
12290 unsigned int endregno = END_REGNO (XEXP (link, 0));
12292 for (i = regno; i < endregno; i++)
12294 reg_stat_type *rsp;
12296 rsp = ®_stat[i];
12297 rsp->last_death = insn;
12300 else if (REG_NOTE_KIND (link) == REG_INC)
12301 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12306 hard_reg_set_iterator hrsi;
12307 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12309 reg_stat_type *rsp;
12311 rsp = ®_stat[i];
12312 rsp->last_set_invalid = 1;
12313 rsp->last_set = insn;
12314 rsp->last_set_value = 0;
12315 rsp->last_set_mode = VOIDmode;
12316 rsp->last_set_nonzero_bits = 0;
12317 rsp->last_set_sign_bit_copies = 0;
12318 rsp->last_death = 0;
12319 rsp->truncated_to_mode = VOIDmode;
12322 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12324 /* We can't combine into a call pattern. Remember, though, that
12325 the return value register is set at this LUID. We could
12326 still replace a register with the return value from the
12327 wrong subroutine call! */
12328 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12331 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12334 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12335 register present in the SUBREG, so for each such SUBREG go back and
12336 adjust nonzero and sign bit information of the registers that are
12337 known to have some zero/sign bits set.
12339 This is needed because when combine blows the SUBREGs away, the
12340 information on zero/sign bits is lost and further combines can be
12341 missed because of that. */
12344 record_promoted_value (rtx insn, rtx subreg)
12346 struct insn_link *links;
12348 unsigned int regno = REGNO (SUBREG_REG (subreg));
12349 enum machine_mode mode = GET_MODE (subreg);
12351 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12354 for (links = LOG_LINKS (insn); links;)
12356 reg_stat_type *rsp;
12358 insn = links->insn;
12359 set = single_set (insn);
12361 if (! set || !REG_P (SET_DEST (set))
12362 || REGNO (SET_DEST (set)) != regno
12363 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12365 links = links->next;
12369 rsp = ®_stat[regno];
12370 if (rsp->last_set == insn)
12372 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12373 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12376 if (REG_P (SET_SRC (set)))
12378 regno = REGNO (SET_SRC (set));
12379 links = LOG_LINKS (insn);
12386 /* Check if X, a register, is known to contain a value already
12387 truncated to MODE. In this case we can use a subreg to refer to
12388 the truncated value even though in the generic case we would need
12389 an explicit truncation. */
12392 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12394 reg_stat_type *rsp = ®_stat[REGNO (x)];
12395 enum machine_mode truncated = rsp->truncated_to_mode;
12398 || rsp->truncation_label < label_tick_ebb_start)
12400 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12402 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12407 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12408 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12409 might be able to turn a truncate into a subreg using this information.
12410 Return -1 if traversing *P is complete or 0 otherwise. */
12413 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12416 enum machine_mode truncated_mode;
12417 reg_stat_type *rsp;
12419 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12421 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12422 truncated_mode = GET_MODE (x);
12424 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12427 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12430 x = SUBREG_REG (x);
12432 /* ??? For hard-regs we now record everything. We might be able to
12433 optimize this using last_set_mode. */
12434 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12435 truncated_mode = GET_MODE (x);
12439 rsp = ®_stat[REGNO (x)];
12440 if (rsp->truncated_to_mode == 0
12441 || rsp->truncation_label < label_tick_ebb_start
12442 || (GET_MODE_SIZE (truncated_mode)
12443 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12445 rsp->truncated_to_mode = truncated_mode;
12446 rsp->truncation_label = label_tick;
12452 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12453 the modes they are used in. This can help truning TRUNCATEs into
12457 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12459 for_each_rtx (x, record_truncated_value, NULL);
12462 /* Scan X for promoted SUBREGs. For each one found,
12463 note what it implies to the registers used in it. */
12466 check_promoted_subreg (rtx insn, rtx x)
12468 if (GET_CODE (x) == SUBREG
12469 && SUBREG_PROMOTED_VAR_P (x)
12470 && REG_P (SUBREG_REG (x)))
12471 record_promoted_value (insn, x);
12474 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12477 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12481 check_promoted_subreg (insn, XEXP (x, i));
12485 if (XVEC (x, i) != 0)
12486 for (j = 0; j < XVECLEN (x, i); j++)
12487 check_promoted_subreg (insn, XVECEXP (x, i, j));
12493 /* Verify that all the registers and memory references mentioned in *LOC are
12494 still valid. *LOC was part of a value set in INSN when label_tick was
12495 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12496 the invalid references with (clobber (const_int 0)) and return 1. This
12497 replacement is useful because we often can get useful information about
12498 the form of a value (e.g., if it was produced by a shift that always
12499 produces -1 or 0) even though we don't know exactly what registers it
12500 was produced from. */
12503 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12506 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12507 int len = GET_RTX_LENGTH (GET_CODE (x));
12512 unsigned int regno = REGNO (x);
12513 unsigned int endregno = END_REGNO (x);
12516 for (j = regno; j < endregno; j++)
12518 reg_stat_type *rsp = ®_stat[j];
12519 if (rsp->last_set_invalid
12520 /* If this is a pseudo-register that was only set once and not
12521 live at the beginning of the function, it is always valid. */
12522 || (! (regno >= FIRST_PSEUDO_REGISTER
12523 && REG_N_SETS (regno) == 1
12524 && (!REGNO_REG_SET_P
12525 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12526 && rsp->last_set_label > tick))
12529 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12536 /* If this is a memory reference, make sure that there were no stores after
12537 it that might have clobbered the value. We don't have alias info, so we
12538 assume any store invalidates it. Moreover, we only have local UIDs, so
12539 we also assume that there were stores in the intervening basic blocks. */
12540 else if (MEM_P (x) && !MEM_READONLY_P (x)
12541 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12544 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12548 for (i = 0; i < len; i++)
12552 /* Check for identical subexpressions. If x contains
12553 identical subexpression we only have to traverse one of
12555 if (i == 1 && ARITHMETIC_P (x))
12557 /* Note that at this point x0 has already been checked
12558 and found valid. */
12559 rtx x0 = XEXP (x, 0);
12560 rtx x1 = XEXP (x, 1);
12562 /* If x0 and x1 are identical then x is also valid. */
12566 /* If x1 is identical to a subexpression of x0 then
12567 while checking x0, x1 has already been checked. Thus
12568 it is valid and so as x. */
12569 if (ARITHMETIC_P (x0)
12570 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12573 /* If x0 is identical to a subexpression of x1 then x is
12574 valid iff the rest of x1 is valid. */
12575 if (ARITHMETIC_P (x1)
12576 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12578 get_last_value_validate (&XEXP (x1,
12579 x0 == XEXP (x1, 0) ? 1 : 0),
12580 insn, tick, replace);
12583 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12587 else if (fmt[i] == 'E')
12588 for (j = 0; j < XVECLEN (x, i); j++)
12589 if (get_last_value_validate (&XVECEXP (x, i, j),
12590 insn, tick, replace) == 0)
12594 /* If we haven't found a reason for it to be invalid, it is valid. */
12598 /* Get the last value assigned to X, if known. Some registers
12599 in the value may be replaced with (clobber (const_int 0)) if their value
12600 is known longer known reliably. */
12603 get_last_value (const_rtx x)
12605 unsigned int regno;
12607 reg_stat_type *rsp;
12609 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12610 then convert it to the desired mode. If this is a paradoxical SUBREG,
12611 we cannot predict what values the "extra" bits might have. */
12612 if (GET_CODE (x) == SUBREG
12613 && subreg_lowpart_p (x)
12614 && !paradoxical_subreg_p (x)
12615 && (value = get_last_value (SUBREG_REG (x))) != 0)
12616 return gen_lowpart (GET_MODE (x), value);
12622 rsp = ®_stat[regno];
12623 value = rsp->last_set_value;
12625 /* If we don't have a value, or if it isn't for this basic block and
12626 it's either a hard register, set more than once, or it's a live
12627 at the beginning of the function, return 0.
12629 Because if it's not live at the beginning of the function then the reg
12630 is always set before being used (is never used without being set).
12631 And, if it's set only once, and it's always set before use, then all
12632 uses must have the same last value, even if it's not from this basic
12636 || (rsp->last_set_label < label_tick_ebb_start
12637 && (regno < FIRST_PSEUDO_REGISTER
12638 || REG_N_SETS (regno) != 1
12640 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12643 /* If the value was set in a later insn than the ones we are processing,
12644 we can't use it even if the register was only set once. */
12645 if (rsp->last_set_label == label_tick
12646 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12649 /* If the value has all its registers valid, return it. */
12650 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12653 /* Otherwise, make a copy and replace any invalid register with
12654 (clobber (const_int 0)). If that fails for some reason, return 0. */
12656 value = copy_rtx (value);
12657 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12663 /* Return nonzero if expression X refers to a REG or to memory
12664 that is set in an instruction more recent than FROM_LUID. */
12667 use_crosses_set_p (const_rtx x, int from_luid)
12671 enum rtx_code code = GET_CODE (x);
12675 unsigned int regno = REGNO (x);
12676 unsigned endreg = END_REGNO (x);
12678 #ifdef PUSH_ROUNDING
12679 /* Don't allow uses of the stack pointer to be moved,
12680 because we don't know whether the move crosses a push insn. */
12681 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12684 for (; regno < endreg; regno++)
12686 reg_stat_type *rsp = ®_stat[regno];
12688 && rsp->last_set_label == label_tick
12689 && DF_INSN_LUID (rsp->last_set) > from_luid)
12695 if (code == MEM && mem_last_set > from_luid)
12698 fmt = GET_RTX_FORMAT (code);
12700 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12705 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12706 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12709 else if (fmt[i] == 'e'
12710 && use_crosses_set_p (XEXP (x, i), from_luid))
12716 /* Define three variables used for communication between the following
12719 static unsigned int reg_dead_regno, reg_dead_endregno;
12720 static int reg_dead_flag;
12722 /* Function called via note_stores from reg_dead_at_p.
12724 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12725 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12728 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12730 unsigned int regno, endregno;
12735 regno = REGNO (dest);
12736 endregno = END_REGNO (dest);
12737 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12738 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12741 /* Return nonzero if REG is known to be dead at INSN.
12743 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12744 referencing REG, it is dead. If we hit a SET referencing REG, it is
12745 live. Otherwise, see if it is live or dead at the start of the basic
12746 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12747 must be assumed to be always live. */
12750 reg_dead_at_p (rtx reg, rtx insn)
12755 /* Set variables for reg_dead_at_p_1. */
12756 reg_dead_regno = REGNO (reg);
12757 reg_dead_endregno = END_REGNO (reg);
12761 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12762 we allow the machine description to decide whether use-and-clobber
12763 patterns are OK. */
12764 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12766 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12767 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12771 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12772 beginning of basic block. */
12773 block = BLOCK_FOR_INSN (insn);
12778 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12780 return reg_dead_flag == 1 ? 1 : 0;
12782 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12786 if (insn == BB_HEAD (block))
12789 insn = PREV_INSN (insn);
12792 /* Look at live-in sets for the basic block that we were in. */
12793 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12794 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12800 /* Note hard registers in X that are used. */
12803 mark_used_regs_combine (rtx x)
12805 RTX_CODE code = GET_CODE (x);
12806 unsigned int regno;
12817 case ADDR_DIFF_VEC:
12820 /* CC0 must die in the insn after it is set, so we don't need to take
12821 special note of it here. */
12827 /* If we are clobbering a MEM, mark any hard registers inside the
12828 address as used. */
12829 if (MEM_P (XEXP (x, 0)))
12830 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12835 /* A hard reg in a wide mode may really be multiple registers.
12836 If so, mark all of them just like the first. */
12837 if (regno < FIRST_PSEUDO_REGISTER)
12839 /* None of this applies to the stack, frame or arg pointers. */
12840 if (regno == STACK_POINTER_REGNUM
12841 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12842 || regno == HARD_FRAME_POINTER_REGNUM
12844 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12845 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12847 || regno == FRAME_POINTER_REGNUM)
12850 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12856 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12858 rtx testreg = SET_DEST (x);
12860 while (GET_CODE (testreg) == SUBREG
12861 || GET_CODE (testreg) == ZERO_EXTRACT
12862 || GET_CODE (testreg) == STRICT_LOW_PART)
12863 testreg = XEXP (testreg, 0);
12865 if (MEM_P (testreg))
12866 mark_used_regs_combine (XEXP (testreg, 0));
12868 mark_used_regs_combine (SET_SRC (x));
12876 /* Recursively scan the operands of this expression. */
12879 const char *fmt = GET_RTX_FORMAT (code);
12881 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12884 mark_used_regs_combine (XEXP (x, i));
12885 else if (fmt[i] == 'E')
12889 for (j = 0; j < XVECLEN (x, i); j++)
12890 mark_used_regs_combine (XVECEXP (x, i, j));
12896 /* Remove register number REGNO from the dead registers list of INSN.
12898 Return the note used to record the death, if there was one. */
12901 remove_death (unsigned int regno, rtx insn)
12903 rtx note = find_regno_note (insn, REG_DEAD, regno);
12906 remove_note (insn, note);
12911 /* For each register (hardware or pseudo) used within expression X, if its
12912 death is in an instruction with luid between FROM_LUID (inclusive) and
12913 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12914 list headed by PNOTES.
12916 That said, don't move registers killed by maybe_kill_insn.
12918 This is done when X is being merged by combination into TO_INSN. These
12919 notes will then be distributed as needed. */
12922 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12927 enum rtx_code code = GET_CODE (x);
12931 unsigned int regno = REGNO (x);
12932 rtx where_dead = reg_stat[regno].last_death;
12934 /* Don't move the register if it gets killed in between from and to. */
12935 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12936 && ! reg_referenced_p (x, maybe_kill_insn))
12940 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12941 && DF_INSN_LUID (where_dead) >= from_luid
12942 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12944 rtx note = remove_death (regno, where_dead);
12946 /* It is possible for the call above to return 0. This can occur
12947 when last_death points to I2 or I1 that we combined with.
12948 In that case make a new note.
12950 We must also check for the case where X is a hard register
12951 and NOTE is a death note for a range of hard registers
12952 including X. In that case, we must put REG_DEAD notes for
12953 the remaining registers in place of NOTE. */
12955 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12956 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12957 > GET_MODE_SIZE (GET_MODE (x))))
12959 unsigned int deadregno = REGNO (XEXP (note, 0));
12960 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12961 unsigned int ourend = END_HARD_REGNO (x);
12964 for (i = deadregno; i < deadend; i++)
12965 if (i < regno || i >= ourend)
12966 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12969 /* If we didn't find any note, or if we found a REG_DEAD note that
12970 covers only part of the given reg, and we have a multi-reg hard
12971 register, then to be safe we must check for REG_DEAD notes
12972 for each register other than the first. They could have
12973 their own REG_DEAD notes lying around. */
12974 else if ((note == 0
12976 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12977 < GET_MODE_SIZE (GET_MODE (x)))))
12978 && regno < FIRST_PSEUDO_REGISTER
12979 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12981 unsigned int ourend = END_HARD_REGNO (x);
12982 unsigned int i, offset;
12986 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12990 for (i = regno + offset; i < ourend; i++)
12991 move_deaths (regno_reg_rtx[i],
12992 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12995 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12997 XEXP (note, 1) = *pnotes;
13001 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13007 else if (GET_CODE (x) == SET)
13009 rtx dest = SET_DEST (x);
13011 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13013 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13014 that accesses one word of a multi-word item, some
13015 piece of everything register in the expression is used by
13016 this insn, so remove any old death. */
13017 /* ??? So why do we test for equality of the sizes? */
13019 if (GET_CODE (dest) == ZERO_EXTRACT
13020 || GET_CODE (dest) == STRICT_LOW_PART
13021 || (GET_CODE (dest) == SUBREG
13022 && (((GET_MODE_SIZE (GET_MODE (dest))
13023 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13024 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13025 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13027 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13031 /* If this is some other SUBREG, we know it replaces the entire
13032 value, so use that as the destination. */
13033 if (GET_CODE (dest) == SUBREG)
13034 dest = SUBREG_REG (dest);
13036 /* If this is a MEM, adjust deaths of anything used in the address.
13037 For a REG (the only other possibility), the entire value is
13038 being replaced so the old value is not used in this insn. */
13041 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13046 else if (GET_CODE (x) == CLOBBER)
13049 len = GET_RTX_LENGTH (code);
13050 fmt = GET_RTX_FORMAT (code);
13052 for (i = 0; i < len; i++)
13057 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13058 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13061 else if (fmt[i] == 'e')
13062 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13066 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13067 pattern of an insn. X must be a REG. */
13070 reg_bitfield_target_p (rtx x, rtx body)
13074 if (GET_CODE (body) == SET)
13076 rtx dest = SET_DEST (body);
13078 unsigned int regno, tregno, endregno, endtregno;
13080 if (GET_CODE (dest) == ZERO_EXTRACT)
13081 target = XEXP (dest, 0);
13082 else if (GET_CODE (dest) == STRICT_LOW_PART)
13083 target = SUBREG_REG (XEXP (dest, 0));
13087 if (GET_CODE (target) == SUBREG)
13088 target = SUBREG_REG (target);
13090 if (!REG_P (target))
13093 tregno = REGNO (target), regno = REGNO (x);
13094 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13095 return target == x;
13097 endtregno = end_hard_regno (GET_MODE (target), tregno);
13098 endregno = end_hard_regno (GET_MODE (x), regno);
13100 return endregno > tregno && regno < endtregno;
13103 else if (GET_CODE (body) == PARALLEL)
13104 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13105 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13111 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13112 as appropriate. I3 and I2 are the insns resulting from the combination
13113 insns including FROM (I2 may be zero).
13115 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13116 not need REG_DEAD notes because they are being substituted for. This
13117 saves searching in the most common cases.
13119 Each note in the list is either ignored or placed on some insns, depending
13120 on the type of note. */
13123 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13124 rtx elim_i1, rtx elim_i0)
13126 rtx note, next_note;
13129 for (note = notes; note; note = next_note)
13131 rtx place = 0, place2 = 0;
13133 next_note = XEXP (note, 1);
13134 switch (REG_NOTE_KIND (note))
13138 /* Doesn't matter much where we put this, as long as it's somewhere.
13139 It is preferable to keep these notes on branches, which is most
13140 likely to be i3. */
13144 case REG_NON_LOCAL_GOTO:
13149 gcc_assert (i2 && JUMP_P (i2));
13154 case REG_EH_REGION:
13155 /* These notes must remain with the call or trapping instruction. */
13158 else if (i2 && CALL_P (i2))
13162 gcc_assert (cfun->can_throw_non_call_exceptions);
13163 if (may_trap_p (i3))
13165 else if (i2 && may_trap_p (i2))
13167 /* ??? Otherwise assume we've combined things such that we
13168 can now prove that the instructions can't trap. Drop the
13169 note in this case. */
13173 case REG_ARGS_SIZE:
13174 /* ??? How to distribute between i3-i1. Assume i3 contains the
13175 entire adjustment. Assert i3 contains at least some adjust. */
13176 if (!noop_move_p (i3))
13178 int old_size, args_size = INTVAL (XEXP (note, 0));
13179 /* fixup_args_size_notes looks at REG_NORETURN note,
13180 so ensure the note is placed there first. */
13184 for (np = &next_note; *np; np = &XEXP (*np, 1))
13185 if (REG_NOTE_KIND (*np) == REG_NORETURN)
13189 XEXP (n, 1) = REG_NOTES (i3);
13190 REG_NOTES (i3) = n;
13194 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13195 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13196 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13197 gcc_assert (old_size != args_size
13199 && !ACCUMULATE_OUTGOING_ARGS
13200 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13207 /* These notes must remain with the call. It should not be
13208 possible for both I2 and I3 to be a call. */
13213 gcc_assert (i2 && CALL_P (i2));
13219 /* Any clobbers for i3 may still exist, and so we must process
13220 REG_UNUSED notes from that insn.
13222 Any clobbers from i2 or i1 can only exist if they were added by
13223 recog_for_combine. In that case, recog_for_combine created the
13224 necessary REG_UNUSED notes. Trying to keep any original
13225 REG_UNUSED notes from these insns can cause incorrect output
13226 if it is for the same register as the original i3 dest.
13227 In that case, we will notice that the register is set in i3,
13228 and then add a REG_UNUSED note for the destination of i3, which
13229 is wrong. However, it is possible to have REG_UNUSED notes from
13230 i2 or i1 for register which were both used and clobbered, so
13231 we keep notes from i2 or i1 if they will turn into REG_DEAD
13234 /* If this register is set or clobbered in I3, put the note there
13235 unless there is one already. */
13236 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13238 if (from_insn != i3)
13241 if (! (REG_P (XEXP (note, 0))
13242 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13243 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13246 /* Otherwise, if this register is used by I3, then this register
13247 now dies here, so we must put a REG_DEAD note here unless there
13249 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13250 && ! (REG_P (XEXP (note, 0))
13251 ? find_regno_note (i3, REG_DEAD,
13252 REGNO (XEXP (note, 0)))
13253 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13255 PUT_REG_NOTE_KIND (note, REG_DEAD);
13263 /* These notes say something about results of an insn. We can
13264 only support them if they used to be on I3 in which case they
13265 remain on I3. Otherwise they are ignored.
13267 If the note refers to an expression that is not a constant, we
13268 must also ignore the note since we cannot tell whether the
13269 equivalence is still true. It might be possible to do
13270 slightly better than this (we only have a problem if I2DEST
13271 or I1DEST is present in the expression), but it doesn't
13272 seem worth the trouble. */
13274 if (from_insn == i3
13275 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13280 /* These notes say something about how a register is used. They must
13281 be present on any use of the register in I2 or I3. */
13282 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13285 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13294 case REG_LABEL_TARGET:
13295 case REG_LABEL_OPERAND:
13296 /* This can show up in several ways -- either directly in the
13297 pattern, or hidden off in the constant pool with (or without?)
13298 a REG_EQUAL note. */
13299 /* ??? Ignore the without-reg_equal-note problem for now. */
13300 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13301 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13302 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13303 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13307 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13308 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13309 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13310 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13318 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13319 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13321 if (place && JUMP_P (place)
13322 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13323 && (JUMP_LABEL (place) == NULL
13324 || JUMP_LABEL (place) == XEXP (note, 0)))
13326 rtx label = JUMP_LABEL (place);
13329 JUMP_LABEL (place) = XEXP (note, 0);
13330 else if (LABEL_P (label))
13331 LABEL_NUSES (label)--;
13334 if (place2 && JUMP_P (place2)
13335 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13336 && (JUMP_LABEL (place2) == NULL
13337 || JUMP_LABEL (place2) == XEXP (note, 0)))
13339 rtx label = JUMP_LABEL (place2);
13342 JUMP_LABEL (place2) = XEXP (note, 0);
13343 else if (LABEL_P (label))
13344 LABEL_NUSES (label)--;
13350 /* This note says something about the value of a register prior
13351 to the execution of an insn. It is too much trouble to see
13352 if the note is still correct in all situations. It is better
13353 to simply delete it. */
13357 /* If we replaced the right hand side of FROM_INSN with a
13358 REG_EQUAL note, the original use of the dying register
13359 will not have been combined into I3 and I2. In such cases,
13360 FROM_INSN is guaranteed to be the first of the combined
13361 instructions, so we simply need to search back before
13362 FROM_INSN for the previous use or set of this register,
13363 then alter the notes there appropriately.
13365 If the register is used as an input in I3, it dies there.
13366 Similarly for I2, if it is nonzero and adjacent to I3.
13368 If the register is not used as an input in either I3 or I2
13369 and it is not one of the registers we were supposed to eliminate,
13370 there are two possibilities. We might have a non-adjacent I2
13371 or we might have somehow eliminated an additional register
13372 from a computation. For example, we might have had A & B where
13373 we discover that B will always be zero. In this case we will
13374 eliminate the reference to A.
13376 In both cases, we must search to see if we can find a previous
13377 use of A and put the death note there. */
13380 && from_insn == i2mod
13381 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13386 && CALL_P (from_insn)
13387 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13389 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13391 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13392 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13394 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13396 && reg_overlap_mentioned_p (XEXP (note, 0),
13398 || rtx_equal_p (XEXP (note, 0), elim_i1)
13399 || rtx_equal_p (XEXP (note, 0), elim_i0))
13406 basic_block bb = this_basic_block;
13408 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13410 if (!NONDEBUG_INSN_P (tem))
13412 if (tem == BB_HEAD (bb))
13417 /* If the register is being set at TEM, see if that is all
13418 TEM is doing. If so, delete TEM. Otherwise, make this
13419 into a REG_UNUSED note instead. Don't delete sets to
13420 global register vars. */
13421 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13422 || !global_regs[REGNO (XEXP (note, 0))])
13423 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13425 rtx set = single_set (tem);
13426 rtx inner_dest = 0;
13428 rtx cc0_setter = NULL_RTX;
13432 for (inner_dest = SET_DEST (set);
13433 (GET_CODE (inner_dest) == STRICT_LOW_PART
13434 || GET_CODE (inner_dest) == SUBREG
13435 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13436 inner_dest = XEXP (inner_dest, 0))
13439 /* Verify that it was the set, and not a clobber that
13440 modified the register.
13442 CC0 targets must be careful to maintain setter/user
13443 pairs. If we cannot delete the setter due to side
13444 effects, mark the user with an UNUSED note instead
13447 if (set != 0 && ! side_effects_p (SET_SRC (set))
13448 && rtx_equal_p (XEXP (note, 0), inner_dest)
13450 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13451 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13452 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13456 /* Move the notes and links of TEM elsewhere.
13457 This might delete other dead insns recursively.
13458 First set the pattern to something that won't use
13460 rtx old_notes = REG_NOTES (tem);
13462 PATTERN (tem) = pc_rtx;
13463 REG_NOTES (tem) = NULL;
13465 distribute_notes (old_notes, tem, tem, NULL_RTX,
13466 NULL_RTX, NULL_RTX, NULL_RTX);
13467 distribute_links (LOG_LINKS (tem));
13469 SET_INSN_DELETED (tem);
13474 /* Delete the setter too. */
13477 PATTERN (cc0_setter) = pc_rtx;
13478 old_notes = REG_NOTES (cc0_setter);
13479 REG_NOTES (cc0_setter) = NULL;
13481 distribute_notes (old_notes, cc0_setter,
13482 cc0_setter, NULL_RTX,
13483 NULL_RTX, NULL_RTX, NULL_RTX);
13484 distribute_links (LOG_LINKS (cc0_setter));
13486 SET_INSN_DELETED (cc0_setter);
13487 if (cc0_setter == i2)
13494 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13496 /* If there isn't already a REG_UNUSED note, put one
13497 here. Do not place a REG_DEAD note, even if
13498 the register is also used here; that would not
13499 match the algorithm used in lifetime analysis
13500 and can cause the consistency check in the
13501 scheduler to fail. */
13502 if (! find_regno_note (tem, REG_UNUSED,
13503 REGNO (XEXP (note, 0))))
13508 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13510 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13514 /* If we are doing a 3->2 combination, and we have a
13515 register which formerly died in i3 and was not used
13516 by i2, which now no longer dies in i3 and is used in
13517 i2 but does not die in i2, and place is between i2
13518 and i3, then we may need to move a link from place to
13520 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13522 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13523 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13525 struct insn_link *links = LOG_LINKS (place);
13526 LOG_LINKS (place) = NULL;
13527 distribute_links (links);
13532 if (tem == BB_HEAD (bb))
13538 /* If the register is set or already dead at PLACE, we needn't do
13539 anything with this note if it is still a REG_DEAD note.
13540 We check here if it is set at all, not if is it totally replaced,
13541 which is what `dead_or_set_p' checks, so also check for it being
13544 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13546 unsigned int regno = REGNO (XEXP (note, 0));
13547 reg_stat_type *rsp = ®_stat[regno];
13549 if (dead_or_set_p (place, XEXP (note, 0))
13550 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13552 /* Unless the register previously died in PLACE, clear
13553 last_death. [I no longer understand why this is
13555 if (rsp->last_death != place)
13556 rsp->last_death = 0;
13560 rsp->last_death = place;
13562 /* If this is a death note for a hard reg that is occupying
13563 multiple registers, ensure that we are still using all
13564 parts of the object. If we find a piece of the object
13565 that is unused, we must arrange for an appropriate REG_DEAD
13566 note to be added for it. However, we can't just emit a USE
13567 and tag the note to it, since the register might actually
13568 be dead; so we recourse, and the recursive call then finds
13569 the previous insn that used this register. */
13571 if (place && regno < FIRST_PSEUDO_REGISTER
13572 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13574 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13578 for (i = regno; i < endregno; i++)
13579 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13580 && ! find_regno_fusage (place, USE, i))
13581 || dead_or_set_regno_p (place, i))
13586 /* Put only REG_DEAD notes for pieces that are
13587 not already dead or set. */
13589 for (i = regno; i < endregno;
13590 i += hard_regno_nregs[i][reg_raw_mode[i]])
13592 rtx piece = regno_reg_rtx[i];
13593 basic_block bb = this_basic_block;
13595 if (! dead_or_set_p (place, piece)
13596 && ! reg_bitfield_target_p (piece,
13599 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13602 distribute_notes (new_note, place, place,
13603 NULL_RTX, NULL_RTX, NULL_RTX,
13606 else if (! refers_to_regno_p (i, i + 1,
13607 PATTERN (place), 0)
13608 && ! find_regno_fusage (place, USE, i))
13609 for (tem = PREV_INSN (place); ;
13610 tem = PREV_INSN (tem))
13612 if (!NONDEBUG_INSN_P (tem))
13614 if (tem == BB_HEAD (bb))
13618 if (dead_or_set_p (tem, piece)
13619 || reg_bitfield_target_p (piece,
13622 add_reg_note (tem, REG_UNUSED, piece);
13636 /* Any other notes should not be present at this point in the
13638 gcc_unreachable ();
13643 XEXP (note, 1) = REG_NOTES (place);
13644 REG_NOTES (place) = note;
13648 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13652 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13653 I3, I2, and I1 to new locations. This is also called to add a link
13654 pointing at I3 when I3's destination is changed. */
13657 distribute_links (struct insn_link *links)
13659 struct insn_link *link, *next_link;
13661 for (link = links; link; link = next_link)
13667 next_link = link->next;
13669 /* If the insn that this link points to is a NOTE or isn't a single
13670 set, ignore it. In the latter case, it isn't clear what we
13671 can do other than ignore the link, since we can't tell which
13672 register it was for. Such links wouldn't be used by combine
13675 It is not possible for the destination of the target of the link to
13676 have been changed by combine. The only potential of this is if we
13677 replace I3, I2, and I1 by I3 and I2. But in that case the
13678 destination of I2 also remains unchanged. */
13680 if (NOTE_P (link->insn)
13681 || (set = single_set (link->insn)) == 0)
13684 reg = SET_DEST (set);
13685 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13686 || GET_CODE (reg) == STRICT_LOW_PART)
13687 reg = XEXP (reg, 0);
13689 /* A LOG_LINK is defined as being placed on the first insn that uses
13690 a register and points to the insn that sets the register. Start
13691 searching at the next insn after the target of the link and stop
13692 when we reach a set of the register or the end of the basic block.
13694 Note that this correctly handles the link that used to point from
13695 I3 to I2. Also note that not much searching is typically done here
13696 since most links don't point very far away. */
13698 for (insn = NEXT_INSN (link->insn);
13699 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13700 || BB_HEAD (this_basic_block->next_bb) != insn));
13701 insn = NEXT_INSN (insn))
13702 if (DEBUG_INSN_P (insn))
13704 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13706 if (reg_referenced_p (reg, PATTERN (insn)))
13710 else if (CALL_P (insn)
13711 && find_reg_fusage (insn, USE, reg))
13716 else if (INSN_P (insn) && reg_set_p (reg, insn))
13719 /* If we found a place to put the link, place it there unless there
13720 is already a link to the same insn as LINK at that point. */
13724 struct insn_link *link2;
13726 FOR_EACH_LOG_LINK (link2, place)
13727 if (link2->insn == link->insn)
13732 link->next = LOG_LINKS (place);
13733 LOG_LINKS (place) = link;
13735 /* Set added_links_insn to the earliest insn we added a
13737 if (added_links_insn == 0
13738 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13739 added_links_insn = place;
13745 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13746 Check whether the expression pointer to by LOC is a register or
13747 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13748 Otherwise return zero. */
13751 unmentioned_reg_p_1 (rtx *loc, void *expr)
13756 && (REG_P (x) || MEM_P (x))
13757 && ! reg_mentioned_p (x, (rtx) expr))
13762 /* Check for any register or memory mentioned in EQUIV that is not
13763 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13764 of EXPR where some registers may have been replaced by constants. */
13767 unmentioned_reg_p (rtx equiv, rtx expr)
13769 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13772 DEBUG_FUNCTION void
13773 dump_combine_stats (FILE *file)
13777 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13778 combine_attempts, combine_merges, combine_extras, combine_successes);
13782 dump_combine_total_stats (FILE *file)
13786 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13787 total_attempts, total_merges, total_extras, total_successes);
13791 gate_handle_combine (void)
13793 return (optimize > 0);
13796 /* Try combining insns through substitution. */
13797 static unsigned int
13798 rest_of_handle_combine (void)
13800 int rebuild_jump_labels_after_combine;
13802 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13803 df_note_add_problem ();
13806 regstat_init_n_sets_and_refs ();
13808 rebuild_jump_labels_after_combine
13809 = combine_instructions (get_insns (), max_reg_num ());
13811 /* Combining insns may have turned an indirect jump into a
13812 direct jump. Rebuild the JUMP_LABEL fields of jumping
13814 if (rebuild_jump_labels_after_combine)
13816 timevar_push (TV_JUMP);
13817 rebuild_jump_labels (get_insns ());
13819 timevar_pop (TV_JUMP);
13822 regstat_free_n_sets_and_refs ();
13826 struct rtl_opt_pass pass_combine =
13830 "combine", /* name */
13831 OPTGROUP_NONE, /* optinfo_flags */
13832 gate_handle_combine, /* gate */
13833 rest_of_handle_combine, /* execute */
13836 0, /* static_pass_number */
13837 TV_COMBINE, /* tv_id */
13838 PROP_cfglayout, /* properties_required */
13839 0, /* properties_provided */
13840 0, /* properties_destroyed */
13841 0, /* todo_flags_start */
13842 TODO_df_finish | TODO_verify_rtl_sharing |
13843 TODO_ggc_collect, /* todo_flags_finish */