1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This module is essentially the "combiner" phase of the U. of Arizona
24 Portable Optimizer, but redone to work on our list-structured
25 representation for RTL instead of their string representation.
27 The LOG_LINKS of each insn identify the most recent assignment
28 to each REG used in the insn. It is a list of previous insns,
29 each of which contains a SET for a REG that is used in this insn
30 and not used or set in between. LOG_LINKs never cross basic blocks.
31 They were set up by the preceding pass (lifetime analysis).
33 We try to combine each pair of insns joined by a logical link.
34 We also try to combine triples of insns A, B and C when
35 C has a link back to B and B has a link back to A.
37 LOG_LINKS does not have links for use of the CC0. They don't
38 need to, because the insn that sets the CC0 is always immediately
39 before the insn that tests it. So we always regard a branch
40 insn as having a logical link to the preceding insn. The same is true
41 for an insn explicitly using CC0.
43 We check (with use_crosses_set_p) to avoid combining in such a way
44 as to move a computation to a place where its value would be different.
46 Combination is done by mathematically substituting the previous
47 insn(s) values for the regs they set into the expressions in
48 the later insns that refer to these regs. If the result is a valid insn
49 for our target machine, according to the machine description,
50 we install it, delete the earlier insns, and update the data flow
51 information (LOG_LINKS and REG_NOTES) for what we did.
53 There are a few exceptions where the dataflow information created by
54 flow.c aren't completely updated:
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_regnotes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
84 #include "hard-reg-set.h"
85 #include "basic-block.h"
86 #include "insn-config.h"
88 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
90 #include "insn-flags.h"
91 #include "insn-codes.h"
92 #include "insn-attr.h"
98 #ifndef ACCUMULATE_OUTGOING_ARGS
99 #define ACCUMULATE_OUTGOING_ARGS 0
102 /* Supply a default definition for PUSH_ARGS. */
105 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
111 /* It is not safe to use ordinary gen_lowpart in combine.
112 Use gen_lowpart_for_combine instead. See comments there. */
113 #define gen_lowpart dont_use_gen_lowpart_you_dummy
115 /* Number of attempts to combine instructions in this function. */
117 static int combine_attempts;
119 /* Number of attempts that got as far as substitution in this function. */
121 static int combine_merges;
123 /* Number of instructions combined with added SETs in this function. */
125 static int combine_extras;
127 /* Number of instructions combined in this function. */
129 static int combine_successes;
131 /* Totals over entire compilation. */
133 static int total_attempts, total_merges, total_extras, total_successes;
135 /* Define a default value for REVERSIBLE_CC_MODE.
136 We can never assume that a condition code mode is safe to reverse unless
137 the md tells us so. */
138 #ifndef REVERSIBLE_CC_MODE
139 #define REVERSIBLE_CC_MODE(MODE) 0
142 /* Vector mapping INSN_UIDs to cuids.
143 The cuids are like uids but increase monotonically always.
144 Combine always uses cuids so that it can compare them.
145 But actually renumbering the uids, which we used to do,
146 proves to be a bad idea because it makes it hard to compare
147 the dumps produced by earlier passes with those from later passes. */
149 static int *uid_cuid;
150 static int max_uid_cuid;
152 /* Get the cuid of an insn. */
154 #define INSN_CUID(INSN) \
155 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
157 /* Maximum register number, which is the size of the tables below. */
159 static unsigned int combine_max_regno;
161 /* Record last point of death of (hard or pseudo) register n. */
163 static rtx *reg_last_death;
165 /* Record last point of modification of (hard or pseudo) register n. */
167 static rtx *reg_last_set;
169 /* Record the cuid of the last insn that invalidated memory
170 (anything that writes memory, and subroutine calls, but not pushes). */
172 static int mem_last_set;
174 /* Record the cuid of the last CALL_INSN
175 so we can tell whether a potential combination crosses any calls. */
177 static int last_call_cuid;
179 /* When `subst' is called, this is the insn that is being modified
180 (by combining in a previous insn). The PATTERN of this insn
181 is still the old pattern partially modified and it should not be
182 looked at, but this may be used to examine the successors of the insn
183 to judge whether a simplification is valid. */
185 static rtx subst_insn;
187 /* This is an insn that belongs before subst_insn, but is not currently
188 on the insn chain. */
190 static rtx subst_prev_insn;
192 /* This is the lowest CUID that `subst' is currently dealing with.
193 get_last_value will not return a value if the register was set at or
194 after this CUID. If not for this mechanism, we could get confused if
195 I2 or I1 in try_combine were an insn that used the old value of a register
196 to obtain a new value. In that case, we might erroneously get the
197 new value of the register when we wanted the old one. */
199 static int subst_low_cuid;
201 /* This contains any hard registers that are used in newpat; reg_dead_at_p
202 must consider all these registers to be always live. */
204 static HARD_REG_SET newpat_used_regs;
206 /* This is an insn to which a LOG_LINKS entry has been added. If this
207 insn is the earlier than I2 or I3, combine should rescan starting at
210 static rtx added_links_insn;
212 /* Basic block number of the block in which we are performing combines. */
213 static int this_basic_block;
215 /* A bitmap indicating which blocks had registers go dead at entry.
216 After combine, we'll need to re-do global life analysis with
217 those blocks as starting points. */
218 static sbitmap refresh_blocks;
219 static int need_refresh;
221 /* The next group of arrays allows the recording of the last value assigned
222 to (hard or pseudo) register n. We use this information to see if a
223 operation being processed is redundant given a prior operation performed
224 on the register. For example, an `and' with a constant is redundant if
225 all the zero bits are already known to be turned off.
227 We use an approach similar to that used by cse, but change it in the
230 (1) We do not want to reinitialize at each label.
231 (2) It is useful, but not critical, to know the actual value assigned
232 to a register. Often just its form is helpful.
234 Therefore, we maintain the following arrays:
236 reg_last_set_value the last value assigned
237 reg_last_set_label records the value of label_tick when the
238 register was assigned
239 reg_last_set_table_tick records the value of label_tick when a
240 value using the register is assigned
241 reg_last_set_invalid set to non-zero when it is not valid
242 to use the value of this register in some
245 To understand the usage of these tables, it is important to understand
246 the distinction between the value in reg_last_set_value being valid
247 and the register being validly contained in some other expression in the
250 Entry I in reg_last_set_value is valid if it is non-zero, and either
251 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
253 Register I may validly appear in any expression returned for the value
254 of another register if reg_n_sets[i] is 1. It may also appear in the
255 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
256 reg_last_set_invalid[j] is zero.
258 If an expression is found in the table containing a register which may
259 not validly appear in an expression, the register is replaced by
260 something that won't match, (clobber (const_int 0)).
262 reg_last_set_invalid[i] is set non-zero when register I is being assigned
263 to and reg_last_set_table_tick[i] == label_tick. */
265 /* Record last value assigned to (hard or pseudo) register n. */
267 static rtx *reg_last_set_value;
269 /* Record the value of label_tick when the value for register n is placed in
270 reg_last_set_value[n]. */
272 static int *reg_last_set_label;
274 /* Record the value of label_tick when an expression involving register n
275 is placed in reg_last_set_value. */
277 static int *reg_last_set_table_tick;
279 /* Set non-zero if references to register n in expressions should not be
282 static char *reg_last_set_invalid;
284 /* Incremented for each label. */
286 static int label_tick;
288 /* Some registers that are set more than once and used in more than one
289 basic block are nevertheless always set in similar ways. For example,
290 a QImode register may be loaded from memory in two places on a machine
291 where byte loads zero extend.
293 We record in the following array what we know about the nonzero
294 bits of a register, specifically which bits are known to be zero.
296 If an entry is zero, it means that we don't know anything special. */
298 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
300 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
301 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero if we know that a register has some leading bits that are always
306 equal to the sign bit. */
308 static unsigned char *reg_sign_bit_copies;
310 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
311 It is zero while computing them and after combine has completed. This
312 former test prevents propagating values based on previously set values,
313 which can be incorrect if a variable is modified in a loop. */
315 static int nonzero_sign_valid;
317 /* These arrays are maintained in parallel with reg_last_set_value
318 and are used to store the mode in which the register was last set,
319 the bits that were known to be zero when it was last set, and the
320 number of sign bits copies it was known to have when it was last set. */
322 static enum machine_mode *reg_last_set_mode;
323 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
324 static char *reg_last_set_sign_bit_copies;
326 /* Record one modification to rtl structure
327 to be undone by storing old_contents into *where.
328 is_int is 1 if the contents are an int. */
334 union {rtx r; int i;} old_contents;
335 union {rtx *r; int *i;} where;
338 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
339 num_undo says how many are currently recorded.
341 storage is nonzero if we must undo the allocation of new storage.
342 The value of storage is what to pass to obfree.
344 other_insn is nonzero if we have modified some other insn in the process
345 of working on subst_insn. It must be verified too.
347 previous_undos is the value of undobuf.undos when we started processing
348 this substitution. This will prevent gen_rtx_combine from re-used a piece
349 from the previous expression. Doing so can produce circular rtl
357 struct undo *previous_undos;
361 static struct undobuf undobuf;
363 /* Number of times the pseudo being substituted for
364 was found and replaced. */
366 static int n_occurrences;
368 static void do_SUBST PARAMS ((rtx *, rtx));
369 static void do_SUBST_INT PARAMS ((int *, int));
370 static void init_reg_last_arrays PARAMS ((void));
371 static void setup_incoming_promotions PARAMS ((void));
372 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
373 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
374 static int sets_function_arg_p PARAMS ((rtx));
375 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
376 static int contains_muldiv PARAMS ((rtx));
377 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
378 static void undo_all PARAMS ((void));
379 static void undo_commit PARAMS ((void));
380 static rtx *find_split_point PARAMS ((rtx *, rtx));
381 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
382 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
383 static rtx simplify_if_then_else PARAMS ((rtx));
384 static rtx simplify_set PARAMS ((rtx));
385 static rtx simplify_logical PARAMS ((rtx, int));
386 static rtx expand_compound_operation PARAMS ((rtx));
387 static rtx expand_field_assignment PARAMS ((rtx));
388 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
389 rtx, unsigned HOST_WIDE_INT, int,
391 static rtx extract_left_shift PARAMS ((rtx, int));
392 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
393 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
394 unsigned HOST_WIDE_INT *));
395 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
396 unsigned HOST_WIDE_INT, rtx, int));
397 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
398 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
399 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
400 static rtx make_field_assignment PARAMS ((rtx));
401 static rtx apply_distributive_law PARAMS ((rtx));
402 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
403 unsigned HOST_WIDE_INT));
404 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
405 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
406 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
407 enum rtx_code, HOST_WIDE_INT,
408 enum machine_mode, int *));
409 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
411 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
412 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
413 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
415 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
417 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
418 enum machine_mode, rtx));
419 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
420 static int reversible_comparison_p PARAMS ((rtx));
421 static void update_table_tick PARAMS ((rtx));
422 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
423 static void check_promoted_subreg PARAMS ((rtx, rtx));
424 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
425 static void record_dead_and_set_regs PARAMS ((rtx));
426 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
427 static rtx get_last_value PARAMS ((rtx));
428 static int use_crosses_set_p PARAMS ((rtx, int));
429 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
430 static int reg_dead_at_p PARAMS ((rtx, rtx));
431 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
432 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
433 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
434 static void distribute_links PARAMS ((rtx));
435 static void mark_used_regs_combine PARAMS ((rtx));
436 static int insn_cuid PARAMS ((rtx));
437 static void record_promoted_value PARAMS ((rtx, rtx));
439 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
440 insn. The substitution can be undone by undo_all. If INTO is already
441 set to NEWVAL, do not record this change. Because computing NEWVAL might
442 also call SUBST, we have to compute it before we put anything into
446 do_SUBST(into, newval)
452 if (oldval == newval)
456 buf = undobuf.frees, undobuf.frees = buf->next;
458 buf = (struct undo *) xmalloc (sizeof (struct undo));
462 buf->old_contents.r = oldval;
465 buf->next = undobuf.undos, undobuf.undos = buf;
468 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
470 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
471 for the value of a HOST_WIDE_INT value (including CONST_INT) is
475 do_SUBST_INT(into, newval)
481 if (oldval == newval)
485 buf = undobuf.frees, undobuf.frees = buf->next;
487 buf = (struct undo *) xmalloc (sizeof (struct undo));
491 buf->old_contents.i = oldval;
494 buf->next = undobuf.undos, undobuf.undos = buf;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return non-zero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (f, nregs)
509 register rtx insn, next;
514 register rtx links, nextlinks;
516 int new_direct_jump_p = 0;
518 combine_attempts = 0;
521 combine_successes = 0;
523 combine_max_regno = nregs;
525 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
526 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
528 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
530 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
533 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
535 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
537 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
538 reg_last_set_nonzero_bits
539 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
540 reg_last_set_sign_bit_copies
541 = (char *) xmalloc (nregs * sizeof (char));
543 init_reg_last_arrays ();
545 init_recog_no_volatile ();
547 /* Compute maximum uid value so uid_cuid can be allocated. */
549 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
550 if (INSN_UID (insn) > i)
553 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
556 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
558 /* Don't use reg_nonzero_bits when computing it. This can cause problems
559 when, for example, we have j <<= 1 in a loop. */
561 nonzero_sign_valid = 0;
563 /* Compute the mapping from uids to cuids.
564 Cuids are numbers assigned to insns, like uids,
565 except that cuids increase monotonically through the code.
567 Scan all SETs and see if we can deduce anything about what
568 bits are known to be zero for some registers and how many copies
569 of the sign bit are known to exist for those registers.
571 Also set any known values so that we can use it while searching
572 for what bits are known to be set. */
576 /* We need to initialize it here, because record_dead_and_set_regs may call
578 subst_prev_insn = NULL_RTX;
580 setup_incoming_promotions ();
582 refresh_blocks = sbitmap_alloc (n_basic_blocks);
583 sbitmap_zero (refresh_blocks);
586 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
588 uid_cuid[INSN_UID (insn)] = ++i;
592 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
594 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
596 record_dead_and_set_regs (insn);
599 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
600 if (REG_NOTE_KIND (links) == REG_INC)
601 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
606 if (GET_CODE (insn) == CODE_LABEL)
610 nonzero_sign_valid = 1;
612 /* Now scan all the insns in forward order. */
614 this_basic_block = -1;
618 init_reg_last_arrays ();
619 setup_incoming_promotions ();
621 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
625 /* If INSN starts a new basic block, update our basic block number. */
626 if (this_basic_block + 1 < n_basic_blocks
627 && BLOCK_HEAD (this_basic_block + 1) == insn)
630 if (GET_CODE (insn) == CODE_LABEL)
633 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
635 /* See if we know about function return values before this
636 insn based upon SUBREG flags. */
637 check_promoted_subreg (insn, PATTERN (insn));
639 /* Try this insn with each insn it links back to. */
641 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
642 if ((next = try_combine (insn, XEXP (links, 0),
643 NULL_RTX, &new_direct_jump_p)) != 0)
646 /* Try each sequence of three linked insns ending with this one. */
648 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
650 rtx link = XEXP (links, 0);
652 /* If the linked insn has been replaced by a note, then there
653 is no point in persuing this chain any further. */
654 if (GET_CODE (link) == NOTE)
657 for (nextlinks = LOG_LINKS (link);
659 nextlinks = XEXP (nextlinks, 1))
660 if ((next = try_combine (insn, XEXP (links, 0),
662 &new_direct_jump_p)) != 0)
667 /* Try to combine a jump insn that uses CC0
668 with a preceding insn that sets CC0, and maybe with its
669 logical predecessor as well.
670 This is how we make decrement-and-branch insns.
671 We need this special code because data flow connections
672 via CC0 do not get entered in LOG_LINKS. */
674 if (GET_CODE (insn) == JUMP_INSN
675 && (prev = prev_nonnote_insn (insn)) != 0
676 && GET_CODE (prev) == INSN
677 && sets_cc0_p (PATTERN (prev)))
679 if ((next = try_combine (insn, prev,
680 NULL_RTX, &new_direct_jump_p)) != 0)
683 for (nextlinks = LOG_LINKS (prev); nextlinks;
684 nextlinks = XEXP (nextlinks, 1))
685 if ((next = try_combine (insn, prev,
687 &new_direct_jump_p)) != 0)
691 /* Do the same for an insn that explicitly references CC0. */
692 if (GET_CODE (insn) == INSN
693 && (prev = prev_nonnote_insn (insn)) != 0
694 && GET_CODE (prev) == INSN
695 && sets_cc0_p (PATTERN (prev))
696 && GET_CODE (PATTERN (insn)) == SET
697 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
699 if ((next = try_combine (insn, prev,
700 NULL_RTX, &new_direct_jump_p)) != 0)
703 for (nextlinks = LOG_LINKS (prev); nextlinks;
704 nextlinks = XEXP (nextlinks, 1))
705 if ((next = try_combine (insn, prev,
707 &new_direct_jump_p)) != 0)
711 /* Finally, see if any of the insns that this insn links to
712 explicitly references CC0. If so, try this insn, that insn,
713 and its predecessor if it sets CC0. */
714 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
715 if (GET_CODE (XEXP (links, 0)) == INSN
716 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
717 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
718 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
719 && GET_CODE (prev) == INSN
720 && sets_cc0_p (PATTERN (prev))
721 && (next = try_combine (insn, XEXP (links, 0),
722 prev, &new_direct_jump_p)) != 0)
726 /* Try combining an insn with two different insns whose results it
728 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
729 for (nextlinks = XEXP (links, 1); nextlinks;
730 nextlinks = XEXP (nextlinks, 1))
731 if ((next = try_combine (insn, XEXP (links, 0),
733 &new_direct_jump_p)) != 0)
736 if (GET_CODE (insn) != NOTE)
737 record_dead_and_set_regs (insn);
746 compute_bb_for_insn (get_max_uid ());
747 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
797 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
798 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
799 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
800 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
801 bzero (reg_last_set_invalid, nregs * sizeof (char));
802 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
803 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
804 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 reg_nonzero_bits[REGNO (x)]
908 |= nonzero_bits (src, nonzero_bits_mode);
909 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
910 if (reg_sign_bit_copies[REGNO (x)] == 0
911 || reg_sign_bit_copies[REGNO (x)] > num)
912 reg_sign_bit_copies[REGNO (x)] = num;
916 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
917 reg_sign_bit_copies[REGNO (x)] = 1;
922 /* See if INSN can be combined into I3. PRED and SUCC are optionally
923 insns that were previously combined into I3 or that will be combined
924 into the merger of INSN and I3.
926 Return 0 if the combination is not allowed for any reason.
928 If the combination is allowed, *PDEST will be set to the single
929 destination of INSN and *PSRC to the single source, and this function
933 can_combine_p (insn, i3, pred, succ, pdest, psrc)
936 rtx pred ATTRIBUTE_UNUSED;
941 rtx set = 0, src, dest;
946 int all_adjacent = (succ ? (next_active_insn (insn) == succ
947 && next_active_insn (succ) == i3)
948 : next_active_insn (insn) == i3);
950 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
951 or a PARALLEL consisting of such a SET and CLOBBERs.
953 If INSN has CLOBBER parallel parts, ignore them for our processing.
954 By definition, these happen during the execution of the insn. When it
955 is merged with another insn, all bets are off. If they are, in fact,
956 needed and aren't also supplied in I3, they may be added by
957 recog_for_combine. Otherwise, it won't match.
959 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
962 Get the source and destination of INSN. If more than one, can't
965 if (GET_CODE (PATTERN (insn)) == SET)
966 set = PATTERN (insn);
967 else if (GET_CODE (PATTERN (insn)) == PARALLEL
968 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
970 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
972 rtx elt = XVECEXP (PATTERN (insn), 0, i);
974 switch (GET_CODE (elt))
976 /* This is important to combine floating point insns
979 /* Combining an isolated USE doesn't make sense.
980 We depend here on combinable_i3_pat to reject them. */
981 /* The code below this loop only verifies that the inputs of
982 the SET in INSN do not change. We call reg_set_between_p
983 to verify that the REG in the USE does not change betweeen
985 If the USE in INSN was for a pseudo register, the matching
986 insn pattern will likely match any register; combining this
987 with any other USE would only be safe if we knew that the
988 used registers have identical values, or if there was
989 something to tell them apart, e.g. different modes. For
990 now, we forgo such compilcated tests and simply disallow
991 combining of USES of pseudo registers with any other USE. */
992 if (GET_CODE (XEXP (elt, 0)) == REG
993 && GET_CODE (PATTERN (i3)) == PARALLEL)
995 rtx i3pat = PATTERN (i3);
996 int i = XVECLEN (i3pat, 0) - 1;
997 unsigned int regno = REGNO (XEXP (elt, 0));
1001 rtx i3elt = XVECEXP (i3pat, 0, i);
1003 if (GET_CODE (i3elt) == USE
1004 && GET_CODE (XEXP (i3elt, 0)) == REG
1005 && (REGNO (XEXP (i3elt, 0)) == regno
1006 ? reg_set_between_p (XEXP (elt, 0),
1007 PREV_INSN (insn), i3)
1008 : regno >= FIRST_PSEUDO_REGISTER))
1015 /* We can ignore CLOBBERs. */
1020 /* Ignore SETs whose result isn't used but not those that
1021 have side-effects. */
1022 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1023 && ! side_effects_p (elt))
1026 /* If we have already found a SET, this is a second one and
1027 so we cannot combine with this insn. */
1035 /* Anything else means we can't combine. */
1041 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1042 so don't do anything with it. */
1043 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1052 set = expand_field_assignment (set);
1053 src = SET_SRC (set), dest = SET_DEST (set);
1055 /* Don't eliminate a store in the stack pointer. */
1056 if (dest == stack_pointer_rtx
1057 /* If we couldn't eliminate a field assignment, we can't combine. */
1058 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1059 /* Don't combine with an insn that sets a register to itself if it has
1060 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1061 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1062 /* Can't merge a function call. */
1063 || GET_CODE (src) == CALL
1064 /* Don't eliminate a function call argument. */
1065 || (GET_CODE (i3) == CALL_INSN
1066 && (find_reg_fusage (i3, USE, dest)
1067 || (GET_CODE (dest) == REG
1068 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1069 && global_regs[REGNO (dest)])))
1070 /* Don't substitute into an incremented register. */
1071 || FIND_REG_INC_NOTE (i3, dest)
1072 || (succ && FIND_REG_INC_NOTE (succ, dest))
1074 /* Don't combine the end of a libcall into anything. */
1075 /* ??? This gives worse code, and appears to be unnecessary, since no
1076 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1077 use REG_RETVAL notes for noconflict blocks, but other code here
1078 makes sure that those insns don't disappear. */
1079 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1081 /* Make sure that DEST is not used after SUCC but before I3. */
1082 || (succ && ! all_adjacent
1083 && reg_used_between_p (dest, succ, i3))
1084 /* Make sure that the value that is to be substituted for the register
1085 does not use any registers whose values alter in between. However,
1086 If the insns are adjacent, a use can't cross a set even though we
1087 think it might (this can happen for a sequence of insns each setting
1088 the same destination; reg_last_set of that register might point to
1089 a NOTE). If INSN has a REG_EQUIV note, the register is always
1090 equivalent to the memory so the substitution is valid even if there
1091 are intervening stores. Also, don't move a volatile asm or
1092 UNSPEC_VOLATILE across any other insns. */
1094 && (((GET_CODE (src) != MEM
1095 || ! find_reg_note (insn, REG_EQUIV, src))
1096 && use_crosses_set_p (src, INSN_CUID (insn)))
1097 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1098 || GET_CODE (src) == UNSPEC_VOLATILE))
1099 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1100 better register allocation by not doing the combine. */
1101 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1102 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1103 /* Don't combine across a CALL_INSN, because that would possibly
1104 change whether the life span of some REGs crosses calls or not,
1105 and it is a pain to update that information.
1106 Exception: if source is a constant, moving it later can't hurt.
1107 Accept that special case, because it helps -fforce-addr a lot. */
1108 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1111 /* DEST must either be a REG or CC0. */
1112 if (GET_CODE (dest) == REG)
1114 /* If register alignment is being enforced for multi-word items in all
1115 cases except for parameters, it is possible to have a register copy
1116 insn referencing a hard register that is not allowed to contain the
1117 mode being copied and which would not be valid as an operand of most
1118 insns. Eliminate this problem by not combining with such an insn.
1120 Also, on some machines we don't want to extend the life of a hard
1123 This is the same test done in can_combine except that we don't test
1124 if SRC is a CALL operation to permit a hard register with
1125 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1128 if (GET_CODE (src) == REG
1129 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1130 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1131 /* Don't extend the life of a hard register unless it is
1132 user variable (if we have few registers) or it can't
1133 fit into the desired register (meaning something special
1135 Also avoid substituting a return register into I3, because
1136 reload can't handle a conflict with constraints of other
1138 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1139 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1140 || (SMALL_REGISTER_CLASSES
1141 && ((! all_adjacent && ! REG_USERVAR_P (src))
1142 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1143 && ! REG_USERVAR_P (src))))))))
1146 else if (GET_CODE (dest) != CC0)
1149 /* Don't substitute for a register intended as a clobberable operand.
1150 Similarly, don't substitute an expression containing a register that
1151 will be clobbered in I3. */
1152 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1153 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1154 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1155 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1157 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1160 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1161 or not), reject, unless nothing volatile comes between it and I3 */
1163 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1165 /* Make sure succ doesn't contain a volatile reference. */
1166 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1169 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1170 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1171 && p != succ && volatile_refs_p (PATTERN (p)))
1175 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1176 to be an explicit register variable, and was chosen for a reason. */
1178 if (GET_CODE (src) == ASM_OPERANDS
1179 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1182 /* If there are any volatile insns between INSN and I3, reject, because
1183 they might affect machine state. */
1185 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1186 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1187 && p != succ && volatile_insn_p (PATTERN (p)))
1190 /* If INSN or I2 contains an autoincrement or autodecrement,
1191 make sure that register is not used between there and I3,
1192 and not already used in I3 either.
1193 Also insist that I3 not be a jump; if it were one
1194 and the incremented register were spilled, we would lose. */
1197 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1198 if (REG_NOTE_KIND (link) == REG_INC
1199 && (GET_CODE (i3) == JUMP_INSN
1200 || reg_used_between_p (XEXP (link, 0), insn, i3)
1201 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1206 /* Don't combine an insn that follows a CC0-setting insn.
1207 An insn that uses CC0 must not be separated from the one that sets it.
1208 We do, however, allow I2 to follow a CC0-setting insn if that insn
1209 is passed as I1; in that case it will be deleted also.
1210 We also allow combining in this case if all the insns are adjacent
1211 because that would leave the two CC0 insns adjacent as well.
1212 It would be more logical to test whether CC0 occurs inside I1 or I2,
1213 but that would be much slower, and this ought to be equivalent. */
1215 p = prev_nonnote_insn (insn);
1216 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1221 /* If we get here, we have passed all the tests and the combination is
1230 /* Check if PAT is an insn - or a part of it - used to set up an
1231 argument for a function in a hard register. */
1234 sets_function_arg_p (pat)
1240 switch (GET_CODE (pat))
1243 return sets_function_arg_p (PATTERN (pat));
1246 for (i = XVECLEN (pat, 0); --i >= 0;)
1247 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1253 inner_dest = SET_DEST (pat);
1254 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1255 || GET_CODE (inner_dest) == SUBREG
1256 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1257 inner_dest = XEXP (inner_dest, 0);
1259 return (GET_CODE (inner_dest) == REG
1260 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1261 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1270 /* LOC is the location within I3 that contains its pattern or the component
1271 of a PARALLEL of the pattern. We validate that it is valid for combining.
1273 One problem is if I3 modifies its output, as opposed to replacing it
1274 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1275 so would produce an insn that is not equivalent to the original insns.
1279 (set (reg:DI 101) (reg:DI 100))
1280 (set (subreg:SI (reg:DI 101) 0) <foo>)
1282 This is NOT equivalent to:
1284 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1285 (set (reg:DI 101) (reg:DI 100))])
1287 Not only does this modify 100 (in which case it might still be valid
1288 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1290 We can also run into a problem if I2 sets a register that I1
1291 uses and I1 gets directly substituted into I3 (not via I2). In that
1292 case, we would be getting the wrong value of I2DEST into I3, so we
1293 must reject the combination. This case occurs when I2 and I1 both
1294 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1295 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1296 of a SET must prevent combination from occurring.
1298 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1299 if the destination of a SET is a hard register that isn't a user
1302 Before doing the above check, we first try to expand a field assignment
1303 into a set of logical operations.
1305 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1306 we place a register that is both set and used within I3. If more than one
1307 such register is detected, we fail.
1309 Return 1 if the combination is valid, zero otherwise. */
1312 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1318 rtx *pi3dest_killed;
1322 if (GET_CODE (x) == SET)
1324 rtx set = expand_field_assignment (x);
1325 rtx dest = SET_DEST (set);
1326 rtx src = SET_SRC (set);
1327 rtx inner_dest = dest;
1330 rtx inner_src = src;
1335 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1336 || GET_CODE (inner_dest) == SUBREG
1337 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1338 inner_dest = XEXP (inner_dest, 0);
1340 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1343 while (GET_CODE (inner_src) == STRICT_LOW_PART
1344 || GET_CODE (inner_src) == SUBREG
1345 || GET_CODE (inner_src) == ZERO_EXTRACT)
1346 inner_src = XEXP (inner_src, 0);
1348 /* If it is better that two different modes keep two different pseudos,
1349 avoid combining them. This avoids producing the following pattern
1351 (set (subreg:SI (reg/v:QI 21) 0)
1352 (lshiftrt:SI (reg/v:SI 20)
1354 If that were made, reload could not handle the pair of
1355 reg 20/21, since it would try to get any GENERAL_REGS
1356 but some of them don't handle QImode. */
1358 if (rtx_equal_p (inner_src, i2dest)
1359 && GET_CODE (inner_dest) == REG
1360 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1364 /* Check for the case where I3 modifies its output, as
1366 if ((inner_dest != dest
1367 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1368 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1370 /* This is the same test done in can_combine_p except that we
1371 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1372 CALL operation. Moreover, we can't test all_adjacent; we don't
1373 have to, since this instruction will stay in place, thus we are
1374 not considering increasing the lifetime of INNER_DEST.
1376 Also, if this insn sets a function argument, combining it with
1377 something that might need a spill could clobber a previous
1378 function argument; the all_adjacent test in can_combine_p also
1379 checks this; here, we do a more specific test for this case. */
1381 || (GET_CODE (inner_dest) == REG
1382 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1383 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1384 GET_MODE (inner_dest))
1385 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1386 && ! REG_USERVAR_P (inner_dest)
1387 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1388 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1390 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1391 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1394 /* If DEST is used in I3, it is being killed in this insn,
1395 so record that for later.
1396 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1397 STACK_POINTER_REGNUM, since these are always considered to be
1398 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1399 if (pi3dest_killed && GET_CODE (dest) == REG
1400 && reg_referenced_p (dest, PATTERN (i3))
1401 && REGNO (dest) != FRAME_POINTER_REGNUM
1402 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1403 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1405 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1406 && (REGNO (dest) != ARG_POINTER_REGNUM
1407 || ! fixed_regs [REGNO (dest)])
1409 && REGNO (dest) != STACK_POINTER_REGNUM)
1411 if (*pi3dest_killed)
1414 *pi3dest_killed = dest;
1418 else if (GET_CODE (x) == PARALLEL)
1422 for (i = 0; i < XVECLEN (x, 0); i++)
1423 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1424 i1_not_in_src, pi3dest_killed))
1431 /* Return 1 if X is an arithmetic expression that contains a multiplication
1432 and division. We don't count multiplications by powers of two here. */
1438 switch (GET_CODE (x))
1440 case MOD: case DIV: case UMOD: case UDIV:
1444 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1445 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1447 switch (GET_RTX_CLASS (GET_CODE (x)))
1449 case 'c': case '<': case '2':
1450 return contains_muldiv (XEXP (x, 0))
1451 || contains_muldiv (XEXP (x, 1));
1454 return contains_muldiv (XEXP (x, 0));
1462 /* Try to combine the insns I1 and I2 into I3.
1463 Here I1 and I2 appear earlier than I3.
1464 I1 can be zero; then we combine just I2 into I3.
1466 It we are combining three insns and the resulting insn is not recognized,
1467 try splitting it into two insns. If that happens, I2 and I3 are retained
1468 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1471 Return 0 if the combination does not work. Then nothing is changed.
1472 If we did the combination, return the insn at which combine should
1475 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1476 new direct jump instruction. */
1479 try_combine (i3, i2, i1, new_direct_jump_p)
1480 register rtx i3, i2, i1;
1481 register int *new_direct_jump_p;
1483 /* New patterns for I3 and I2, respectively. */
1484 rtx newpat, newi2pat = 0;
1485 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1486 int added_sets_1, added_sets_2;
1487 /* Total number of SETs to put into I3. */
1489 /* Nonzero is I2's body now appears in I3. */
1491 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1492 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1493 /* Contains I3 if the destination of I3 is used in its source, which means
1494 that the old life of I3 is being killed. If that usage is placed into
1495 I2 and not in I3, a REG_DEAD note must be made. */
1496 rtx i3dest_killed = 0;
1497 /* SET_DEST and SET_SRC of I2 and I1. */
1498 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1499 /* PATTERN (I2), or a copy of it in certain cases. */
1501 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1502 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1503 int i1_feeds_i3 = 0;
1504 /* Notes that must be added to REG_NOTES in I3 and I2. */
1505 rtx new_i3_notes, new_i2_notes;
1506 /* Notes that we substituted I3 into I2 instead of the normal case. */
1507 int i3_subst_into_i2 = 0;
1508 /* Notes that I1, I2 or I3 is a MULT operation. */
1516 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1517 This can occur when flow deletes an insn that it has merged into an
1518 auto-increment address. We also can't do anything if I3 has a
1519 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1522 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1523 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1524 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1526 /* ??? This gives worse code, and appears to be unnecessary, since no
1527 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1528 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1534 undobuf.other_insn = 0;
1536 /* Save the current high-water-mark so we can free storage if we didn't
1537 accept this combination. */
1538 undobuf.storage = (char *) oballoc (0);
1540 /* Reset the hard register usage information. */
1541 CLEAR_HARD_REG_SET (newpat_used_regs);
1543 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1544 code below, set I1 to be the earlier of the two insns. */
1545 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1546 temp = i1, i1 = i2, i2 = temp;
1548 added_links_insn = 0;
1550 /* First check for one important special-case that the code below will
1551 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1552 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1553 we may be able to replace that destination with the destination of I3.
1554 This occurs in the common code where we compute both a quotient and
1555 remainder into a structure, in which case we want to do the computation
1556 directly into the structure to avoid register-register copies.
1558 We make very conservative checks below and only try to handle the
1559 most common cases of this. For example, we only handle the case
1560 where I2 and I3 are adjacent to avoid making difficult register
1563 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1564 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1565 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1566 && (! SMALL_REGISTER_CLASSES
1567 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1568 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1569 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1570 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1571 && GET_CODE (PATTERN (i2)) == PARALLEL
1572 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1573 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1574 below would need to check what is inside (and reg_overlap_mentioned_p
1575 doesn't support those codes anyway). Don't allow those destinations;
1576 the resulting insn isn't likely to be recognized anyway. */
1577 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1578 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1579 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1580 SET_DEST (PATTERN (i3)))
1581 && next_real_insn (i2) == i3)
1583 rtx p2 = PATTERN (i2);
1585 /* Make sure that the destination of I3,
1586 which we are going to substitute into one output of I2,
1587 is not used within another output of I2. We must avoid making this:
1588 (parallel [(set (mem (reg 69)) ...)
1589 (set (reg 69) ...)])
1590 which is not well-defined as to order of actions.
1591 (Besides, reload can't handle output reloads for this.)
1593 The problem can also happen if the dest of I3 is a memory ref,
1594 if another dest in I2 is an indirect memory ref. */
1595 for (i = 0; i < XVECLEN (p2, 0); i++)
1596 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1597 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1598 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1599 SET_DEST (XVECEXP (p2, 0, i))))
1602 if (i == XVECLEN (p2, 0))
1603 for (i = 0; i < XVECLEN (p2, 0); i++)
1604 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1605 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1606 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1611 subst_low_cuid = INSN_CUID (i2);
1613 added_sets_2 = added_sets_1 = 0;
1614 i2dest = SET_SRC (PATTERN (i3));
1616 /* Replace the dest in I2 with our dest and make the resulting
1617 insn the new pattern for I3. Then skip to where we
1618 validate the pattern. Everything was set up above. */
1619 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1620 SET_DEST (PATTERN (i3)));
1623 i3_subst_into_i2 = 1;
1624 goto validate_replacement;
1628 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1629 one of those words to another constant, merge them by making a new
1632 && (temp = single_set (i2)) != 0
1633 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1634 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1635 && GET_CODE (SET_DEST (temp)) == REG
1636 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1637 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1638 && GET_CODE (PATTERN (i3)) == SET
1639 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1640 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1641 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1642 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1643 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1645 HOST_WIDE_INT lo, hi;
1647 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1648 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1651 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1652 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1655 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1656 lo = INTVAL (SET_SRC (PATTERN (i3)));
1658 hi = INTVAL (SET_SRC (PATTERN (i3)));
1662 subst_low_cuid = INSN_CUID (i2);
1663 added_sets_2 = added_sets_1 = 0;
1664 i2dest = SET_DEST (temp);
1666 SUBST (SET_SRC (temp),
1667 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1669 newpat = PATTERN (i2);
1670 i3_subst_into_i2 = 1;
1671 goto validate_replacement;
1675 /* If we have no I1 and I2 looks like:
1676 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1678 make up a dummy I1 that is
1681 (set (reg:CC X) (compare:CC Y (const_int 0)))
1683 (We can ignore any trailing CLOBBERs.)
1685 This undoes a previous combination and allows us to match a branch-and-
1688 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1689 && XVECLEN (PATTERN (i2), 0) >= 2
1690 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1691 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1693 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1694 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1695 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1696 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1697 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1698 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1700 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1701 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1706 /* We make I1 with the same INSN_UID as I2. This gives it
1707 the same INSN_CUID for value tracking. Our fake I1 will
1708 never appear in the insn stream so giving it the same INSN_UID
1709 as I2 will not cause a problem. */
1711 subst_prev_insn = i1
1712 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1713 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1716 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1717 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1718 SET_DEST (PATTERN (i1)));
1723 /* Verify that I2 and I1 are valid for combining. */
1724 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1725 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1731 /* Record whether I2DEST is used in I2SRC and similarly for the other
1732 cases. Knowing this will help in register status updating below. */
1733 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1734 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1735 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1737 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1739 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1741 /* Ensure that I3's pattern can be the destination of combines. */
1742 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1743 i1 && i2dest_in_i1src && i1_feeds_i3,
1750 /* See if any of the insns is a MULT operation. Unless one is, we will
1751 reject a combination that is, since it must be slower. Be conservative
1753 if (GET_CODE (i2src) == MULT
1754 || (i1 != 0 && GET_CODE (i1src) == MULT)
1755 || (GET_CODE (PATTERN (i3)) == SET
1756 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1759 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1760 We used to do this EXCEPT in one case: I3 has a post-inc in an
1761 output operand. However, that exception can give rise to insns like
1763 which is a famous insn on the PDP-11 where the value of r3 used as the
1764 source was model-dependent. Avoid this sort of thing. */
1767 if (!(GET_CODE (PATTERN (i3)) == SET
1768 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1769 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1770 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1771 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1772 /* It's not the exception. */
1775 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1776 if (REG_NOTE_KIND (link) == REG_INC
1777 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1779 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1786 /* See if the SETs in I1 or I2 need to be kept around in the merged
1787 instruction: whenever the value set there is still needed past I3.
1788 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1790 For the SET in I1, we have two cases: If I1 and I2 independently
1791 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1792 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1793 in I1 needs to be kept around unless I1DEST dies or is set in either
1794 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1795 I1DEST. If so, we know I1 feeds into I2. */
1797 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1800 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1801 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1803 /* If the set in I2 needs to be kept around, we must make a copy of
1804 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1805 PATTERN (I2), we are only substituting for the original I1DEST, not into
1806 an already-substituted copy. This also prevents making self-referential
1807 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1810 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1811 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1815 i2pat = copy_rtx (i2pat);
1819 /* Substitute in the latest insn for the regs set by the earlier ones. */
1821 maxreg = max_reg_num ();
1825 /* It is possible that the source of I2 or I1 may be performing an
1826 unneeded operation, such as a ZERO_EXTEND of something that is known
1827 to have the high part zero. Handle that case by letting subst look at
1828 the innermost one of them.
1830 Another way to do this would be to have a function that tries to
1831 simplify a single insn instead of merging two or more insns. We don't
1832 do this because of the potential of infinite loops and because
1833 of the potential extra memory required. However, doing it the way
1834 we are is a bit of a kludge and doesn't catch all cases.
1836 But only do this if -fexpensive-optimizations since it slows things down
1837 and doesn't usually win. */
1839 if (flag_expensive_optimizations)
1841 /* Pass pc_rtx so no substitutions are done, just simplifications.
1842 The cases that we are interested in here do not involve the few
1843 cases were is_replaced is checked. */
1846 subst_low_cuid = INSN_CUID (i1);
1847 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1851 subst_low_cuid = INSN_CUID (i2);
1852 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1855 undobuf.previous_undos = undobuf.undos;
1859 /* Many machines that don't use CC0 have insns that can both perform an
1860 arithmetic operation and set the condition code. These operations will
1861 be represented as a PARALLEL with the first element of the vector
1862 being a COMPARE of an arithmetic operation with the constant zero.
1863 The second element of the vector will set some pseudo to the result
1864 of the same arithmetic operation. If we simplify the COMPARE, we won't
1865 match such a pattern and so will generate an extra insn. Here we test
1866 for this case, where both the comparison and the operation result are
1867 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1868 I2SRC. Later we will make the PARALLEL that contains I2. */
1870 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1871 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1872 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1873 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1875 #ifdef EXTRA_CC_MODES
1877 enum machine_mode compare_mode;
1880 newpat = PATTERN (i3);
1881 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1885 #ifdef EXTRA_CC_MODES
1886 /* See if a COMPARE with the operand we substituted in should be done
1887 with the mode that is currently being used. If not, do the same
1888 processing we do in `subst' for a SET; namely, if the destination
1889 is used only once, try to replace it with a register of the proper
1890 mode and also replace the COMPARE. */
1891 if (undobuf.other_insn == 0
1892 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1893 &undobuf.other_insn))
1894 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1896 != GET_MODE (SET_DEST (newpat))))
1898 unsigned int regno = REGNO (SET_DEST (newpat));
1899 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1901 if (regno < FIRST_PSEUDO_REGISTER
1902 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1903 && ! REG_USERVAR_P (SET_DEST (newpat))))
1905 if (regno >= FIRST_PSEUDO_REGISTER)
1906 SUBST (regno_reg_rtx[regno], new_dest);
1908 SUBST (SET_DEST (newpat), new_dest);
1909 SUBST (XEXP (*cc_use, 0), new_dest);
1910 SUBST (SET_SRC (newpat),
1911 gen_rtx_combine (COMPARE, compare_mode,
1912 i2src, const0_rtx));
1915 undobuf.other_insn = 0;
1922 n_occurrences = 0; /* `subst' counts here */
1924 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1925 need to make a unique copy of I2SRC each time we substitute it
1926 to avoid self-referential rtl. */
1928 subst_low_cuid = INSN_CUID (i2);
1929 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1930 ! i1_feeds_i3 && i1dest_in_i1src);
1931 undobuf.previous_undos = undobuf.undos;
1933 /* Record whether i2's body now appears within i3's body. */
1934 i2_is_used = n_occurrences;
1937 /* If we already got a failure, don't try to do more. Otherwise,
1938 try to substitute in I1 if we have it. */
1940 if (i1 && GET_CODE (newpat) != CLOBBER)
1942 /* Before we can do this substitution, we must redo the test done
1943 above (see detailed comments there) that ensures that I1DEST
1944 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1946 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1954 subst_low_cuid = INSN_CUID (i1);
1955 newpat = subst (newpat, i1dest, i1src, 0, 0);
1956 undobuf.previous_undos = undobuf.undos;
1959 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1960 to count all the ways that I2SRC and I1SRC can be used. */
1961 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1962 && i2_is_used + added_sets_2 > 1)
1963 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1964 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1966 /* Fail if we tried to make a new register (we used to abort, but there's
1967 really no reason to). */
1968 || max_reg_num () != maxreg
1969 /* Fail if we couldn't do something and have a CLOBBER. */
1970 || GET_CODE (newpat) == CLOBBER
1971 /* Fail if this new pattern is a MULT and we didn't have one before
1972 at the outer level. */
1973 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1980 /* If the actions of the earlier insns must be kept
1981 in addition to substituting them into the latest one,
1982 we must make a new PARALLEL for the latest insn
1983 to hold additional the SETs. */
1985 if (added_sets_1 || added_sets_2)
1989 if (GET_CODE (newpat) == PARALLEL)
1991 rtvec old = XVEC (newpat, 0);
1992 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1993 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1994 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1995 sizeof (old->elem[0]) * old->num_elem);
2000 total_sets = 1 + added_sets_1 + added_sets_2;
2001 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2002 XVECEXP (newpat, 0, 0) = old;
2006 XVECEXP (newpat, 0, --total_sets)
2007 = (GET_CODE (PATTERN (i1)) == PARALLEL
2008 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2012 /* If there is no I1, use I2's body as is. We used to also not do
2013 the subst call below if I2 was substituted into I3,
2014 but that could lose a simplification. */
2016 XVECEXP (newpat, 0, --total_sets) = i2pat;
2018 /* See comment where i2pat is assigned. */
2019 XVECEXP (newpat, 0, --total_sets)
2020 = subst (i2pat, i1dest, i1src, 0, 0);
2024 /* We come here when we are replacing a destination in I2 with the
2025 destination of I3. */
2026 validate_replacement:
2028 /* Note which hard regs this insn has as inputs. */
2029 mark_used_regs_combine (newpat);
2031 /* Is the result of combination a valid instruction? */
2032 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2034 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2035 the second SET's destination is a register that is unused. In that case,
2036 we just need the first SET. This can occur when simplifying a divmod
2037 insn. We *must* test for this case here because the code below that
2038 splits two independent SETs doesn't handle this case correctly when it
2039 updates the register status. Also check the case where the first
2040 SET's destination is unused. That would not cause incorrect code, but
2041 does cause an unneeded insn to remain. */
2043 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2044 && XVECLEN (newpat, 0) == 2
2045 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2046 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2047 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2048 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2049 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2050 && asm_noperands (newpat) < 0)
2052 newpat = XVECEXP (newpat, 0, 0);
2053 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2056 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2057 && XVECLEN (newpat, 0) == 2
2058 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2059 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2060 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2061 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2062 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2063 && asm_noperands (newpat) < 0)
2065 newpat = XVECEXP (newpat, 0, 1);
2066 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2069 /* If we were combining three insns and the result is a simple SET
2070 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2071 insns. There are two ways to do this. It can be split using a
2072 machine-specific method (like when you have an addition of a large
2073 constant) or by combine in the function find_split_point. */
2075 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2076 && asm_noperands (newpat) < 0)
2078 rtx m_split, *split;
2079 rtx ni2dest = i2dest;
2081 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2082 use I2DEST as a scratch register will help. In the latter case,
2083 convert I2DEST to the mode of the source of NEWPAT if we can. */
2085 m_split = split_insns (newpat, i3);
2087 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2088 inputs of NEWPAT. */
2090 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2091 possible to try that as a scratch reg. This would require adding
2092 more code to make it work though. */
2094 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2096 /* If I2DEST is a hard register or the only use of a pseudo,
2097 we can change its mode. */
2098 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2099 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2100 && GET_CODE (i2dest) == REG
2101 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2102 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2103 && ! REG_USERVAR_P (i2dest))))
2104 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2107 m_split = split_insns (gen_rtx_PARALLEL
2109 gen_rtvec (2, newpat,
2110 gen_rtx_CLOBBER (VOIDmode,
2115 if (m_split && GET_CODE (m_split) == SEQUENCE
2116 && XVECLEN (m_split, 0) == 2
2117 && (next_real_insn (i2) == i3
2118 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2122 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2123 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2125 i3set = single_set (XVECEXP (m_split, 0, 1));
2126 i2set = single_set (XVECEXP (m_split, 0, 0));
2128 /* In case we changed the mode of I2DEST, replace it in the
2129 pseudo-register table here. We can't do it above in case this
2130 code doesn't get executed and we do a split the other way. */
2132 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2133 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2135 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2137 /* If I2 or I3 has multiple SETs, we won't know how to track
2138 register status, so don't use these insns. If I2's destination
2139 is used between I2 and I3, we also can't use these insns. */
2141 if (i2_code_number >= 0 && i2set && i3set
2142 && (next_real_insn (i2) == i3
2143 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2144 insn_code_number = recog_for_combine (&newi3pat, i3,
2146 if (insn_code_number >= 0)
2149 /* It is possible that both insns now set the destination of I3.
2150 If so, we must show an extra use of it. */
2152 if (insn_code_number >= 0)
2154 rtx new_i3_dest = SET_DEST (i3set);
2155 rtx new_i2_dest = SET_DEST (i2set);
2157 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2158 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2159 || GET_CODE (new_i3_dest) == SUBREG)
2160 new_i3_dest = XEXP (new_i3_dest, 0);
2162 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2163 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2164 || GET_CODE (new_i2_dest) == SUBREG)
2165 new_i2_dest = XEXP (new_i2_dest, 0);
2167 if (GET_CODE (new_i3_dest) == REG
2168 && GET_CODE (new_i2_dest) == REG
2169 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2170 REG_N_SETS (REGNO (new_i2_dest))++;
2174 /* If we can split it and use I2DEST, go ahead and see if that
2175 helps things be recognized. Verify that none of the registers
2176 are set between I2 and I3. */
2177 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2179 && GET_CODE (i2dest) == REG
2181 /* We need I2DEST in the proper mode. If it is a hard register
2182 or the only use of a pseudo, we can change its mode. */
2183 && (GET_MODE (*split) == GET_MODE (i2dest)
2184 || GET_MODE (*split) == VOIDmode
2185 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2186 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2187 && ! REG_USERVAR_P (i2dest)))
2188 && (next_real_insn (i2) == i3
2189 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2190 /* We can't overwrite I2DEST if its value is still used by
2192 && ! reg_referenced_p (i2dest, newpat))
2194 rtx newdest = i2dest;
2195 enum rtx_code split_code = GET_CODE (*split);
2196 enum machine_mode split_mode = GET_MODE (*split);
2198 /* Get NEWDEST as a register in the proper mode. We have already
2199 validated that we can do this. */
2200 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2202 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2204 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2205 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2208 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2209 an ASHIFT. This can occur if it was inside a PLUS and hence
2210 appeared to be a memory address. This is a kludge. */
2211 if (split_code == MULT
2212 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2213 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2215 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2216 XEXP (*split, 0), GEN_INT (i)));
2217 /* Update split_code because we may not have a multiply
2219 split_code = GET_CODE (*split);
2222 #ifdef INSN_SCHEDULING
2223 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2224 be written as a ZERO_EXTEND. */
2225 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2226 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2230 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2231 SUBST (*split, newdest);
2232 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2234 /* If the split point was a MULT and we didn't have one before,
2235 don't use one now. */
2236 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2237 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2241 /* Check for a case where we loaded from memory in a narrow mode and
2242 then sign extended it, but we need both registers. In that case,
2243 we have a PARALLEL with both loads from the same memory location.
2244 We can split this into a load from memory followed by a register-register
2245 copy. This saves at least one insn, more if register allocation can
2248 We cannot do this if the destination of the second assignment is
2249 a register that we have already assumed is zero-extended. Similarly
2250 for a SUBREG of such a register. */
2252 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2253 && GET_CODE (newpat) == PARALLEL
2254 && XVECLEN (newpat, 0) == 2
2255 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2256 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2257 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2258 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2259 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2260 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2262 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2263 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2264 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2265 (GET_CODE (temp) == REG
2266 && reg_nonzero_bits[REGNO (temp)] != 0
2267 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2268 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2269 && (reg_nonzero_bits[REGNO (temp)]
2270 != GET_MODE_MASK (word_mode))))
2271 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2272 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2273 (GET_CODE (temp) == REG
2274 && reg_nonzero_bits[REGNO (temp)] != 0
2275 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2276 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2277 && (reg_nonzero_bits[REGNO (temp)]
2278 != GET_MODE_MASK (word_mode)))))
2279 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2280 SET_SRC (XVECEXP (newpat, 0, 1)))
2281 && ! find_reg_note (i3, REG_UNUSED,
2282 SET_DEST (XVECEXP (newpat, 0, 0))))
2286 newi2pat = XVECEXP (newpat, 0, 0);
2287 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2288 newpat = XVECEXP (newpat, 0, 1);
2289 SUBST (SET_SRC (newpat),
2290 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2291 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2293 if (i2_code_number >= 0)
2294 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2296 if (insn_code_number >= 0)
2301 /* If we will be able to accept this, we have made a change to the
2302 destination of I3. This can invalidate a LOG_LINKS pointing
2303 to I3. No other part of combine.c makes such a transformation.
2305 The new I3 will have a destination that was previously the
2306 destination of I1 or I2 and which was used in i2 or I3. Call
2307 distribute_links to make a LOG_LINK from the next use of
2308 that destination. */
2310 PATTERN (i3) = newpat;
2311 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2313 /* I3 now uses what used to be its destination and which is
2314 now I2's destination. That means we need a LOG_LINK from
2315 I3 to I2. But we used to have one, so we still will.
2317 However, some later insn might be using I2's dest and have
2318 a LOG_LINK pointing at I3. We must remove this link.
2319 The simplest way to remove the link is to point it at I1,
2320 which we know will be a NOTE. */
2322 for (insn = NEXT_INSN (i3);
2323 insn && (this_basic_block == n_basic_blocks - 1
2324 || insn != BLOCK_HEAD (this_basic_block + 1));
2325 insn = NEXT_INSN (insn))
2327 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2328 && reg_referenced_p (ni2dest, PATTERN (insn)))
2330 for (link = LOG_LINKS (insn); link;
2331 link = XEXP (link, 1))
2332 if (XEXP (link, 0) == i3)
2333 XEXP (link, 0) = i1;
2341 /* Similarly, check for a case where we have a PARALLEL of two independent
2342 SETs but we started with three insns. In this case, we can do the sets
2343 as two separate insns. This case occurs when some SET allows two
2344 other insns to combine, but the destination of that SET is still live. */
2346 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2347 && GET_CODE (newpat) == PARALLEL
2348 && XVECLEN (newpat, 0) == 2
2349 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2350 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2351 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2352 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2353 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2354 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2355 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2357 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2358 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2359 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2360 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2361 XVECEXP (newpat, 0, 0))
2362 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2363 XVECEXP (newpat, 0, 1))
2364 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2365 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2367 /* Normally, it doesn't matter which of the two is done first,
2368 but it does if one references cc0. In that case, it has to
2371 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2373 newi2pat = XVECEXP (newpat, 0, 0);
2374 newpat = XVECEXP (newpat, 0, 1);
2379 newi2pat = XVECEXP (newpat, 0, 1);
2380 newpat = XVECEXP (newpat, 0, 0);
2383 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2385 if (i2_code_number >= 0)
2386 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2389 /* If it still isn't recognized, fail and change things back the way they
2391 if ((insn_code_number < 0
2392 /* Is the result a reasonable ASM_OPERANDS? */
2393 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2399 /* If we had to change another insn, make sure it is valid also. */
2400 if (undobuf.other_insn)
2402 rtx other_pat = PATTERN (undobuf.other_insn);
2403 rtx new_other_notes;
2406 CLEAR_HARD_REG_SET (newpat_used_regs);
2408 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2411 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2417 PATTERN (undobuf.other_insn) = other_pat;
2419 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2420 are still valid. Then add any non-duplicate notes added by
2421 recog_for_combine. */
2422 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2424 next = XEXP (note, 1);
2426 if (REG_NOTE_KIND (note) == REG_UNUSED
2427 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2429 if (GET_CODE (XEXP (note, 0)) == REG)
2430 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2432 remove_note (undobuf.other_insn, note);
2436 for (note = new_other_notes; note; note = XEXP (note, 1))
2437 if (GET_CODE (XEXP (note, 0)) == REG)
2438 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2440 distribute_notes (new_other_notes, undobuf.other_insn,
2441 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2444 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2445 they are adjacent to each other or not. */
2447 rtx p = prev_nonnote_insn (i3);
2448 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat && sets_cc0_p (newi2pat))
2456 /* We now know that we can do this combination. Merge the insns and
2457 update the status of registers and LOG_LINKS. */
2460 rtx i3notes, i2notes, i1notes = 0;
2461 rtx i3links, i2links, i1links = 0;
2464 /* Compute which registers we expect to eliminate. newi2pat may be setting
2465 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2466 same as i3dest, in which case newi2pat may be setting i1dest. */
2467 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2468 || i2dest_in_i2src || i2dest_in_i1src
2470 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2471 || (newi2pat && reg_set_p (i1dest, newi2pat))
2474 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2476 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2477 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2479 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2481 /* Ensure that we do not have something that should not be shared but
2482 occurs multiple times in the new insns. Check this by first
2483 resetting all the `used' flags and then copying anything is shared. */
2485 reset_used_flags (i3notes);
2486 reset_used_flags (i2notes);
2487 reset_used_flags (i1notes);
2488 reset_used_flags (newpat);
2489 reset_used_flags (newi2pat);
2490 if (undobuf.other_insn)
2491 reset_used_flags (PATTERN (undobuf.other_insn));
2493 i3notes = copy_rtx_if_shared (i3notes);
2494 i2notes = copy_rtx_if_shared (i2notes);
2495 i1notes = copy_rtx_if_shared (i1notes);
2496 newpat = copy_rtx_if_shared (newpat);
2497 newi2pat = copy_rtx_if_shared (newi2pat);
2498 if (undobuf.other_insn)
2499 reset_used_flags (PATTERN (undobuf.other_insn));
2501 INSN_CODE (i3) = insn_code_number;
2502 PATTERN (i3) = newpat;
2503 if (undobuf.other_insn)
2504 INSN_CODE (undobuf.other_insn) = other_code_number;
2506 /* We had one special case above where I2 had more than one set and
2507 we replaced a destination of one of those sets with the destination
2508 of I3. In that case, we have to update LOG_LINKS of insns later
2509 in this basic block. Note that this (expensive) case is rare.
2511 Also, in this case, we must pretend that all REG_NOTEs for I2
2512 actually came from I3, so that REG_UNUSED notes from I2 will be
2513 properly handled. */
2515 if (i3_subst_into_i2 && GET_CODE (PATTERN (i2)) == PARALLEL)
2517 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2519 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2520 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2521 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2522 && ! find_reg_note (i2, REG_UNUSED,
2523 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2524 for (temp = NEXT_INSN (i2);
2525 temp && (this_basic_block == n_basic_blocks - 1
2526 || BLOCK_HEAD (this_basic_block) != temp);
2527 temp = NEXT_INSN (temp))
2528 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2529 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2530 if (XEXP (link, 0) == i2)
2531 XEXP (link, 0) = i3;
2537 while (XEXP (link, 1))
2538 link = XEXP (link, 1);
2539 XEXP (link, 1) = i2notes;
2553 INSN_CODE (i2) = i2_code_number;
2554 PATTERN (i2) = newi2pat;
2558 PUT_CODE (i2, NOTE);
2559 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2560 NOTE_SOURCE_FILE (i2) = 0;
2567 PUT_CODE (i1, NOTE);
2568 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2569 NOTE_SOURCE_FILE (i1) = 0;
2572 /* Get death notes for everything that is now used in either I3 or
2573 I2 and used to die in a previous insn. If we built two new
2574 patterns, move from I1 to I2 then I2 to I3 so that we get the
2575 proper movement on registers that I2 modifies. */
2579 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2580 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2583 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2586 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2588 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2591 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2594 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2597 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2600 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2601 know these are REG_UNUSED and want them to go to the desired insn,
2602 so we always pass it as i3. We have not counted the notes in
2603 reg_n_deaths yet, so we need to do so now. */
2605 if (newi2pat && new_i2_notes)
2607 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2608 if (GET_CODE (XEXP (temp, 0)) == REG)
2609 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2611 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2616 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2617 if (GET_CODE (XEXP (temp, 0)) == REG)
2618 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2620 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2623 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2624 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2625 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2626 in that case, it might delete I2. Similarly for I2 and I1.
2627 Show an additional death due to the REG_DEAD note we make here. If
2628 we discard it in distribute_notes, we will decrement it again. */
2632 if (GET_CODE (i3dest_killed) == REG)
2633 REG_N_DEATHS (REGNO (i3dest_killed))++;
2635 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2636 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2638 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2640 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2642 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2646 if (i2dest_in_i2src)
2648 if (GET_CODE (i2dest) == REG)
2649 REG_N_DEATHS (REGNO (i2dest))++;
2651 if (newi2pat && reg_set_p (i2dest, newi2pat))
2652 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2653 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2655 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2656 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2657 NULL_RTX, NULL_RTX);
2660 if (i1dest_in_i1src)
2662 if (GET_CODE (i1dest) == REG)
2663 REG_N_DEATHS (REGNO (i1dest))++;
2665 if (newi2pat && reg_set_p (i1dest, newi2pat))
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2667 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2670 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2671 NULL_RTX, NULL_RTX);
2674 distribute_links (i3links);
2675 distribute_links (i2links);
2676 distribute_links (i1links);
2678 if (GET_CODE (i2dest) == REG)
2681 rtx i2_insn = 0, i2_val = 0, set;
2683 /* The insn that used to set this register doesn't exist, and
2684 this life of the register may not exist either. See if one of
2685 I3's links points to an insn that sets I2DEST. If it does,
2686 that is now the last known value for I2DEST. If we don't update
2687 this and I2 set the register to a value that depended on its old
2688 contents, we will get confused. If this insn is used, thing
2689 will be set correctly in combine_instructions. */
2691 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2692 if ((set = single_set (XEXP (link, 0))) != 0
2693 && rtx_equal_p (i2dest, SET_DEST (set)))
2694 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2696 record_value_for_reg (i2dest, i2_insn, i2_val);
2698 /* If the reg formerly set in I2 died only once and that was in I3,
2699 zero its use count so it won't make `reload' do any work. */
2701 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2702 && ! i2dest_in_i2src)
2704 regno = REGNO (i2dest);
2705 REG_N_SETS (regno)--;
2709 if (i1 && GET_CODE (i1dest) == REG)
2712 rtx i1_insn = 0, i1_val = 0, set;
2714 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2715 if ((set = single_set (XEXP (link, 0))) != 0
2716 && rtx_equal_p (i1dest, SET_DEST (set)))
2717 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2719 record_value_for_reg (i1dest, i1_insn, i1_val);
2721 regno = REGNO (i1dest);
2722 if (! added_sets_1 && ! i1dest_in_i1src)
2723 REG_N_SETS (regno)--;
2726 /* Update reg_nonzero_bits et al for any changes that may have been made
2727 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2728 important. Because newi2pat can affect nonzero_bits of newpat */
2730 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2731 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2733 /* Set new_direct_jump_p if a new return or simple jump instruction
2736 If I3 is now an unconditional jump, ensure that it has a
2737 BARRIER following it since it may have initially been a
2738 conditional jump. It may also be the last nonnote insn. */
2740 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2742 *new_direct_jump_p = 1;
2744 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2745 || GET_CODE (temp) != BARRIER)
2746 emit_barrier_after (i3);
2750 combine_successes++;
2753 /* Clear this here, so that subsequent get_last_value calls are not
2755 subst_prev_insn = NULL_RTX;
2757 if (added_links_insn
2758 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2759 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2760 return added_links_insn;
2762 return newi2pat ? i2 : i3;
2765 /* Undo all the modifications recorded in undobuf. */
2770 struct undo *undo, *next;
2772 for (undo = undobuf.undos; undo; undo = next)
2776 *undo->where.i = undo->old_contents.i;
2778 *undo->where.r = undo->old_contents.r;
2780 undo->next = undobuf.frees;
2781 undobuf.frees = undo;
2784 obfree (undobuf.storage);
2785 undobuf.undos = undobuf.previous_undos = 0;
2787 /* Clear this here, so that subsequent get_last_value calls are not
2789 subst_prev_insn = NULL_RTX;
2792 /* We've committed to accepting the changes we made. Move all
2793 of the undos to the free list. */
2798 struct undo *undo, *next;
2800 for (undo = undobuf.undos; undo; undo = next)
2803 undo->next = undobuf.frees;
2804 undobuf.frees = undo;
2806 undobuf.undos = undobuf.previous_undos = 0;
2810 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2811 where we have an arithmetic expression and return that point. LOC will
2814 try_combine will call this function to see if an insn can be split into
2818 find_split_point (loc, insn)
2823 enum rtx_code code = GET_CODE (x);
2825 unsigned HOST_WIDE_INT len = 0;
2826 HOST_WIDE_INT pos = 0;
2828 rtx inner = NULL_RTX;
2830 /* First special-case some codes. */
2834 #ifdef INSN_SCHEDULING
2835 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2837 if (GET_CODE (SUBREG_REG (x)) == MEM)
2840 return find_split_point (&SUBREG_REG (x), insn);
2844 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2845 using LO_SUM and HIGH. */
2846 if (GET_CODE (XEXP (x, 0)) == CONST
2847 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2850 gen_rtx_combine (LO_SUM, Pmode,
2851 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2853 return &XEXP (XEXP (x, 0), 0);
2857 /* If we have a PLUS whose second operand is a constant and the
2858 address is not valid, perhaps will can split it up using
2859 the machine-specific way to split large constants. We use
2860 the first pseudo-reg (one of the virtual regs) as a placeholder;
2861 it will not remain in the result. */
2862 if (GET_CODE (XEXP (x, 0)) == PLUS
2863 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2864 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2866 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2867 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2870 /* This should have produced two insns, each of which sets our
2871 placeholder. If the source of the second is a valid address,
2872 we can make put both sources together and make a split point
2875 if (seq && XVECLEN (seq, 0) == 2
2876 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2877 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2878 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2879 && ! reg_mentioned_p (reg,
2880 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2881 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2882 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2883 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2884 && memory_address_p (GET_MODE (x),
2885 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2887 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2888 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2890 /* Replace the placeholder in SRC2 with SRC1. If we can
2891 find where in SRC2 it was placed, that can become our
2892 split point and we can replace this address with SRC2.
2893 Just try two obvious places. */
2895 src2 = replace_rtx (src2, reg, src1);
2897 if (XEXP (src2, 0) == src1)
2898 split = &XEXP (src2, 0);
2899 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2900 && XEXP (XEXP (src2, 0), 0) == src1)
2901 split = &XEXP (XEXP (src2, 0), 0);
2905 SUBST (XEXP (x, 0), src2);
2910 /* If that didn't work, perhaps the first operand is complex and
2911 needs to be computed separately, so make a split point there.
2912 This will occur on machines that just support REG + CONST
2913 and have a constant moved through some previous computation. */
2915 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2916 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2917 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2919 return &XEXP (XEXP (x, 0), 0);
2925 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2926 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2927 we need to put the operand into a register. So split at that
2930 if (SET_DEST (x) == cc0_rtx
2931 && GET_CODE (SET_SRC (x)) != COMPARE
2932 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2933 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2934 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2935 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2936 return &SET_SRC (x);
2939 /* See if we can split SET_SRC as it stands. */
2940 split = find_split_point (&SET_SRC (x), insn);
2941 if (split && split != &SET_SRC (x))
2944 /* See if we can split SET_DEST as it stands. */
2945 split = find_split_point (&SET_DEST (x), insn);
2946 if (split && split != &SET_DEST (x))
2949 /* See if this is a bitfield assignment with everything constant. If
2950 so, this is an IOR of an AND, so split it into that. */
2951 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2952 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2953 <= HOST_BITS_PER_WIDE_INT)
2954 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2955 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2956 && GET_CODE (SET_SRC (x)) == CONST_INT
2957 && ((INTVAL (XEXP (SET_DEST (x), 1))
2958 + INTVAL (XEXP (SET_DEST (x), 2)))
2959 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2960 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2962 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2963 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2964 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2965 rtx dest = XEXP (SET_DEST (x), 0);
2966 enum machine_mode mode = GET_MODE (dest);
2967 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2969 if (BITS_BIG_ENDIAN)
2970 pos = GET_MODE_BITSIZE (mode) - len - pos;
2974 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2977 gen_binary (IOR, mode,
2978 gen_binary (AND, mode, dest,
2979 GEN_INT (~ (mask << pos)
2980 & GET_MODE_MASK (mode))),
2981 GEN_INT (src << pos)));
2983 SUBST (SET_DEST (x), dest);
2985 split = find_split_point (&SET_SRC (x), insn);
2986 if (split && split != &SET_SRC (x))
2990 /* Otherwise, see if this is an operation that we can split into two.
2991 If so, try to split that. */
2992 code = GET_CODE (SET_SRC (x));
2997 /* If we are AND'ing with a large constant that is only a single
2998 bit and the result is only being used in a context where we
2999 need to know if it is zero or non-zero, replace it with a bit
3000 extraction. This will avoid the large constant, which might
3001 have taken more than one insn to make. If the constant were
3002 not a valid argument to the AND but took only one insn to make,
3003 this is no worse, but if it took more than one insn, it will
3006 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3007 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3008 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3009 && GET_CODE (SET_DEST (x)) == REG
3010 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3011 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3012 && XEXP (*split, 0) == SET_DEST (x)
3013 && XEXP (*split, 1) == const0_rtx)
3015 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3016 XEXP (SET_SRC (x), 0),
3017 pos, NULL_RTX, 1, 1, 0, 0);
3018 if (extraction != 0)
3020 SUBST (SET_SRC (x), extraction);
3021 return find_split_point (loc, insn);
3027 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3028 is known to be on, this can be converted into a NEG of a shift. */
3029 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3030 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3031 && 1 <= (pos = exact_log2
3032 (nonzero_bits (XEXP (SET_SRC (x), 0),
3033 GET_MODE (XEXP (SET_SRC (x), 0))))))
3035 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3038 gen_rtx_combine (NEG, mode,
3039 gen_rtx_combine (LSHIFTRT, mode,
3040 XEXP (SET_SRC (x), 0),
3043 split = find_split_point (&SET_SRC (x), insn);
3044 if (split && split != &SET_SRC (x))
3050 inner = XEXP (SET_SRC (x), 0);
3052 /* We can't optimize if either mode is a partial integer
3053 mode as we don't know how many bits are significant
3055 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3056 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3060 len = GET_MODE_BITSIZE (GET_MODE (inner));
3066 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3067 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3069 inner = XEXP (SET_SRC (x), 0);
3070 len = INTVAL (XEXP (SET_SRC (x), 1));
3071 pos = INTVAL (XEXP (SET_SRC (x), 2));
3073 if (BITS_BIG_ENDIAN)
3074 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3075 unsignedp = (code == ZERO_EXTRACT);
3083 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3085 enum machine_mode mode = GET_MODE (SET_SRC (x));
3087 /* For unsigned, we have a choice of a shift followed by an
3088 AND or two shifts. Use two shifts for field sizes where the
3089 constant might be too large. We assume here that we can
3090 always at least get 8-bit constants in an AND insn, which is
3091 true for every current RISC. */
3093 if (unsignedp && len <= 8)
3098 gen_rtx_combine (LSHIFTRT, mode,
3099 gen_lowpart_for_combine (mode, inner),
3101 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3103 split = find_split_point (&SET_SRC (x), insn);
3104 if (split && split != &SET_SRC (x))
3111 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3112 gen_rtx_combine (ASHIFT, mode,
3113 gen_lowpart_for_combine (mode, inner),
3114 GEN_INT (GET_MODE_BITSIZE (mode)
3116 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3118 split = find_split_point (&SET_SRC (x), insn);
3119 if (split && split != &SET_SRC (x))
3124 /* See if this is a simple operation with a constant as the second
3125 operand. It might be that this constant is out of range and hence
3126 could be used as a split point. */
3127 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3128 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3129 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3130 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3131 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3132 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3133 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3135 return &XEXP (SET_SRC (x), 1);
3137 /* Finally, see if this is a simple operation with its first operand
3138 not in a register. The operation might require this operand in a
3139 register, so return it as a split point. We can always do this
3140 because if the first operand were another operation, we would have
3141 already found it as a split point. */
3142 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3143 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3144 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3145 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3146 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3147 return &XEXP (SET_SRC (x), 0);
3153 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3154 it is better to write this as (not (ior A B)) so we can split it.
3155 Similarly for IOR. */
3156 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3159 gen_rtx_combine (NOT, GET_MODE (x),
3160 gen_rtx_combine (code == IOR ? AND : IOR,
3162 XEXP (XEXP (x, 0), 0),
3163 XEXP (XEXP (x, 1), 0))));
3164 return find_split_point (loc, insn);
3167 /* Many RISC machines have a large set of logical insns. If the
3168 second operand is a NOT, put it first so we will try to split the
3169 other operand first. */
3170 if (GET_CODE (XEXP (x, 1)) == NOT)
3172 rtx tem = XEXP (x, 0);
3173 SUBST (XEXP (x, 0), XEXP (x, 1));
3174 SUBST (XEXP (x, 1), tem);
3182 /* Otherwise, select our actions depending on our rtx class. */
3183 switch (GET_RTX_CLASS (code))
3185 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3187 split = find_split_point (&XEXP (x, 2), insn);
3190 /* ... fall through ... */
3194 split = find_split_point (&XEXP (x, 1), insn);
3197 /* ... fall through ... */
3199 /* Some machines have (and (shift ...) ...) insns. If X is not
3200 an AND, but XEXP (X, 0) is, use it as our split point. */
3201 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3202 return &XEXP (x, 0);
3204 split = find_split_point (&XEXP (x, 0), insn);
3210 /* Otherwise, we don't have a split point. */
3214 /* Throughout X, replace FROM with TO, and return the result.
3215 The result is TO if X is FROM;
3216 otherwise the result is X, but its contents may have been modified.
3217 If they were modified, a record was made in undobuf so that
3218 undo_all will (among other things) return X to its original state.
3220 If the number of changes necessary is too much to record to undo,
3221 the excess changes are not made, so the result is invalid.
3222 The changes already made can still be undone.
3223 undobuf.num_undo is incremented for such changes, so by testing that
3224 the caller can tell whether the result is valid.
3226 `n_occurrences' is incremented each time FROM is replaced.
3228 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3230 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3231 by copying if `n_occurrences' is non-zero. */
3234 subst (x, from, to, in_dest, unique_copy)
3235 register rtx x, from, to;
3239 register enum rtx_code code = GET_CODE (x);
3240 enum machine_mode op0_mode = VOIDmode;
3241 register const char *fmt;
3242 register int len, i;
3245 /* Two expressions are equal if they are identical copies of a shared
3246 RTX or if they are both registers with the same register number
3249 #define COMBINE_RTX_EQUAL_P(X,Y) \
3251 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3252 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3254 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3257 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3260 /* If X and FROM are the same register but different modes, they will
3261 not have been seen as equal above. However, flow.c will make a
3262 LOG_LINKS entry for that case. If we do nothing, we will try to
3263 rerecognize our original insn and, when it succeeds, we will
3264 delete the feeding insn, which is incorrect.
3266 So force this insn not to match in this (rare) case. */
3267 if (! in_dest && code == REG && GET_CODE (from) == REG
3268 && REGNO (x) == REGNO (from))
3269 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3271 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3272 of which may contain things that can be combined. */
3273 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3276 /* It is possible to have a subexpression appear twice in the insn.
3277 Suppose that FROM is a register that appears within TO.
3278 Then, after that subexpression has been scanned once by `subst',
3279 the second time it is scanned, TO may be found. If we were
3280 to scan TO here, we would find FROM within it and create a
3281 self-referent rtl structure which is completely wrong. */
3282 if (COMBINE_RTX_EQUAL_P (x, to))
3285 /* Parallel asm_operands need special attention because all of the
3286 inputs are shared across the arms. Furthermore, unsharing the
3287 rtl results in recognition failures. Failure to handle this case
3288 specially can result in circular rtl.
3290 Solve this by doing a normal pass across the first entry of the
3291 parallel, and only processing the SET_DESTs of the subsequent
3294 if (code == PARALLEL
3295 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3296 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3298 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3300 /* If this substitution failed, this whole thing fails. */
3301 if (GET_CODE (new) == CLOBBER
3302 && XEXP (new, 0) == const0_rtx)
3305 SUBST (XVECEXP (x, 0, 0), new);
3307 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3309 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3311 if (GET_CODE (dest) != REG
3312 && GET_CODE (dest) != CC0
3313 && GET_CODE (dest) != PC)
3315 new = subst (dest, from, to, 0, unique_copy);
3317 /* If this substitution failed, this whole thing fails. */
3318 if (GET_CODE (new) == CLOBBER
3319 && XEXP (new, 0) == const0_rtx)
3322 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3328 len = GET_RTX_LENGTH (code);
3329 fmt = GET_RTX_FORMAT (code);
3331 /* We don't need to process a SET_DEST that is a register, CC0,
3332 or PC, so set up to skip this common case. All other cases
3333 where we want to suppress replacing something inside a
3334 SET_SRC are handled via the IN_DEST operand. */
3336 && (GET_CODE (SET_DEST (x)) == REG
3337 || GET_CODE (SET_DEST (x)) == CC0
3338 || GET_CODE (SET_DEST (x)) == PC))
3341 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3344 op0_mode = GET_MODE (XEXP (x, 0));
3346 for (i = 0; i < len; i++)
3351 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3353 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3355 new = (unique_copy && n_occurrences
3356 ? copy_rtx (to) : to);
3361 new = subst (XVECEXP (x, i, j), from, to, 0,
3364 /* If this substitution failed, this whole thing
3366 if (GET_CODE (new) == CLOBBER
3367 && XEXP (new, 0) == const0_rtx)
3371 SUBST (XVECEXP (x, i, j), new);
3374 else if (fmt[i] == 'e')
3376 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3378 /* In general, don't install a subreg involving two
3379 modes not tieable. It can worsen register
3380 allocation, and can even make invalid reload
3381 insns, since the reg inside may need to be copied
3382 from in the outside mode, and that may be invalid
3383 if it is an fp reg copied in integer mode.
3385 We allow two exceptions to this: It is valid if
3386 it is inside another SUBREG and the mode of that
3387 SUBREG and the mode of the inside of TO is
3388 tieable and it is valid if X is a SET that copies
3391 if (GET_CODE (to) == SUBREG
3392 && ! MODES_TIEABLE_P (GET_MODE (to),
3393 GET_MODE (SUBREG_REG (to)))
3394 && ! (code == SUBREG
3395 && MODES_TIEABLE_P (GET_MODE (x),
3396 GET_MODE (SUBREG_REG (to))))
3398 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3401 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3403 #ifdef CLASS_CANNOT_CHANGE_SIZE
3405 && GET_CODE (to) == REG
3406 && REGNO (to) < FIRST_PSEUDO_REGISTER
3407 && (TEST_HARD_REG_BIT
3408 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
3410 && (GET_MODE_BITSIZE (GET_MODE (to))
3411 != GET_MODE_BITSIZE (GET_MODE (x))))
3412 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3415 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3419 /* If we are in a SET_DEST, suppress most cases unless we
3420 have gone inside a MEM, in which case we want to
3421 simplify the address. We assume here that things that
3422 are actually part of the destination have their inner
3423 parts in the first expression. This is true for SUBREG,
3424 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3425 things aside from REG and MEM that should appear in a
3427 new = subst (XEXP (x, i), from, to,
3429 && (code == SUBREG || code == STRICT_LOW_PART
3430 || code == ZERO_EXTRACT))
3432 && i == 0), unique_copy);
3434 /* If we found that we will have to reject this combination,
3435 indicate that by returning the CLOBBER ourselves, rather than
3436 an expression containing it. This will speed things up as
3437 well as prevent accidents where two CLOBBERs are considered
3438 to be equal, thus producing an incorrect simplification. */
3440 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3443 SUBST (XEXP (x, i), new);
3448 /* Try to simplify X. If the simplification changed the code, it is likely
3449 that further simplification will help, so loop, but limit the number
3450 of repetitions that will be performed. */
3452 for (i = 0; i < 4; i++)
3454 /* If X is sufficiently simple, don't bother trying to do anything
3456 if (code != CONST_INT && code != REG && code != CLOBBER)
3457 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3459 if (GET_CODE (x) == code)
3462 code = GET_CODE (x);
3464 /* We no longer know the original mode of operand 0 since we
3465 have changed the form of X) */
3466 op0_mode = VOIDmode;
3472 /* Simplify X, a piece of RTL. We just operate on the expression at the
3473 outer level; call `subst' to simplify recursively. Return the new
3476 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3477 will be the iteration even if an expression with a code different from
3478 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3481 combine_simplify_rtx (x, op0_mode, last, in_dest)
3483 enum machine_mode op0_mode;
3487 enum rtx_code code = GET_CODE (x);
3488 enum machine_mode mode = GET_MODE (x);
3492 /* If this is a commutative operation, put a constant last and a complex
3493 expression first. We don't need to do this for comparisons here. */
3494 if (GET_RTX_CLASS (code) == 'c'
3495 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3496 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3497 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3498 || (GET_CODE (XEXP (x, 0)) == SUBREG
3499 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3500 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3503 SUBST (XEXP (x, 0), XEXP (x, 1));
3504 SUBST (XEXP (x, 1), temp);
3507 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3508 sign extension of a PLUS with a constant, reverse the order of the sign
3509 extension and the addition. Note that this not the same as the original
3510 code, but overflow is undefined for signed values. Also note that the
3511 PLUS will have been partially moved "inside" the sign-extension, so that
3512 the first operand of X will really look like:
3513 (ashiftrt (plus (ashift A C4) C5) C4).
3515 (plus (ashiftrt (ashift A C4) C2) C4)
3516 and replace the first operand of X with that expression. Later parts
3517 of this function may simplify the expression further.
3519 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3520 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3521 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3523 We do this to simplify address expressions. */
3525 if ((code == PLUS || code == MINUS || code == MULT)
3526 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3527 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3528 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3529 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3530 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3531 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3532 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3533 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3534 XEXP (XEXP (XEXP (x, 0), 0), 1),
3535 XEXP (XEXP (x, 0), 1))) != 0)
3538 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3539 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3540 INTVAL (XEXP (XEXP (x, 0), 1)));
3542 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3543 INTVAL (XEXP (XEXP (x, 0), 1)));
3545 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3548 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3549 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3550 things. Check for cases where both arms are testing the same
3553 Don't do anything if all operands are very simple. */
3555 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3556 || GET_RTX_CLASS (code) == '<')
3557 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3558 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3559 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3561 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3562 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3563 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3565 || (GET_RTX_CLASS (code) == '1'
3566 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3567 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3568 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3571 rtx cond, true, false;
3573 cond = if_then_else_cond (x, &true, &false);
3575 /* If everything is a comparison, what we have is highly unlikely
3576 to be simpler, so don't use it. */
3577 && ! (GET_RTX_CLASS (code) == '<'
3578 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3579 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3581 rtx cop1 = const0_rtx;
3582 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3584 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3587 /* Simplify the alternative arms; this may collapse the true and
3588 false arms to store-flag values. */
3589 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3590 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3592 /* If true and false are not general_operands, an if_then_else
3593 is unlikely to be simpler. */
3594 if (general_operand (true, VOIDmode)
3595 && general_operand (false, VOIDmode))
3597 /* Restarting if we generate a store-flag expression will cause
3598 us to loop. Just drop through in this case. */
3600 /* If the result values are STORE_FLAG_VALUE and zero, we can
3601 just make the comparison operation. */
3602 if (true == const_true_rtx && false == const0_rtx)
3603 x = gen_binary (cond_code, mode, cond, cop1);
3604 else if (true == const0_rtx && false == const_true_rtx)
3605 x = gen_binary (reverse_condition (cond_code),
3608 /* Likewise, we can make the negate of a comparison operation
3609 if the result values are - STORE_FLAG_VALUE and zero. */
3610 else if (GET_CODE (true) == CONST_INT
3611 && INTVAL (true) == - STORE_FLAG_VALUE
3612 && false == const0_rtx)
3613 x = gen_unary (NEG, mode, mode,
3614 gen_binary (cond_code, mode, cond, cop1));
3615 else if (GET_CODE (false) == CONST_INT
3616 && INTVAL (false) == - STORE_FLAG_VALUE
3617 && true == const0_rtx)
3618 x = gen_unary (NEG, mode, mode,
3619 gen_binary (reverse_condition (cond_code),
3622 return gen_rtx_IF_THEN_ELSE (mode,
3623 gen_binary (cond_code, VOIDmode,
3627 code = GET_CODE (x);
3628 op0_mode = VOIDmode;
3633 /* Try to fold this expression in case we have constants that weren't
3636 switch (GET_RTX_CLASS (code))
3639 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3642 temp = simplify_relational_operation (code, op0_mode,
3643 XEXP (x, 0), XEXP (x, 1));
3644 #ifdef FLOAT_STORE_FLAG_VALUE
3645 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3647 if (temp == const0_rtx)
3648 temp = CONST0_RTX (mode);
3650 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3656 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3660 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3661 XEXP (x, 1), XEXP (x, 2));
3666 x = temp, code = GET_CODE (temp);
3668 /* First see if we can apply the inverse distributive law. */
3669 if (code == PLUS || code == MINUS
3670 || code == AND || code == IOR || code == XOR)
3672 x = apply_distributive_law (x);
3673 code = GET_CODE (x);
3676 /* If CODE is an associative operation not otherwise handled, see if we
3677 can associate some operands. This can win if they are constants or
3678 if they are logically related (i.e. (a & b) & a. */
3679 if ((code == PLUS || code == MINUS
3680 || code == MULT || code == AND || code == IOR || code == XOR
3681 || code == DIV || code == UDIV
3682 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3683 && INTEGRAL_MODE_P (mode))
3685 if (GET_CODE (XEXP (x, 0)) == code)
3687 rtx other = XEXP (XEXP (x, 0), 0);
3688 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3689 rtx inner_op1 = XEXP (x, 1);
3692 /* Make sure we pass the constant operand if any as the second
3693 one if this is a commutative operation. */
3694 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3696 rtx tem = inner_op0;
3697 inner_op0 = inner_op1;
3700 inner = simplify_binary_operation (code == MINUS ? PLUS
3701 : code == DIV ? MULT
3702 : code == UDIV ? MULT
3704 mode, inner_op0, inner_op1);
3706 /* For commutative operations, try the other pair if that one
3708 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3710 other = XEXP (XEXP (x, 0), 1);
3711 inner = simplify_binary_operation (code, mode,
3712 XEXP (XEXP (x, 0), 0),
3717 return gen_binary (code, mode, other, inner);
3721 /* A little bit of algebraic simplification here. */
3725 /* Ensure that our address has any ASHIFTs converted to MULT in case
3726 address-recognizing predicates are called later. */
3727 temp = make_compound_operation (XEXP (x, 0), MEM);
3728 SUBST (XEXP (x, 0), temp);
3732 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3733 is paradoxical. If we can't do that safely, then it becomes
3734 something nonsensical so that this combination won't take place. */
3736 if (GET_CODE (SUBREG_REG (x)) == MEM
3737 && (GET_MODE_SIZE (mode)
3738 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3740 rtx inner = SUBREG_REG (x);
3741 int endian_offset = 0;
3742 /* Don't change the mode of the MEM
3743 if that would change the meaning of the address. */
3744 if (MEM_VOLATILE_P (SUBREG_REG (x))
3745 || mode_dependent_address_p (XEXP (inner, 0)))
3746 return gen_rtx_CLOBBER (mode, const0_rtx);
3748 if (BYTES_BIG_ENDIAN)
3750 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3751 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3752 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3753 endian_offset -= (UNITS_PER_WORD
3754 - GET_MODE_SIZE (GET_MODE (inner)));
3756 /* Note if the plus_constant doesn't make a valid address
3757 then this combination won't be accepted. */
3758 x = gen_rtx_MEM (mode,
3759 plus_constant (XEXP (inner, 0),
3760 (SUBREG_WORD (x) * UNITS_PER_WORD
3762 MEM_COPY_ATTRIBUTES (x, inner);
3766 /* If we are in a SET_DEST, these other cases can't apply. */
3770 /* Changing mode twice with SUBREG => just change it once,
3771 or not at all if changing back to starting mode. */
3772 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3774 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3775 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3776 return SUBREG_REG (SUBREG_REG (x));
3778 SUBST_INT (SUBREG_WORD (x),
3779 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3780 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3783 /* SUBREG of a hard register => just change the register number
3784 and/or mode. If the hard register is not valid in that mode,
3785 suppress this combination. If the hard register is the stack,
3786 frame, or argument pointer, leave this as a SUBREG. */
3788 if (GET_CODE (SUBREG_REG (x)) == REG
3789 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3790 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3791 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3792 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3794 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3795 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3797 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3799 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3801 return gen_rtx_REG (mode,
3802 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3804 return gen_rtx_CLOBBER (mode, const0_rtx);
3807 /* For a constant, try to pick up the part we want. Handle a full
3808 word and low-order part. Only do this if we are narrowing
3809 the constant; if it is being widened, we have no idea what
3810 the extra bits will have been set to. */
3812 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3813 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3814 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3815 && GET_MODE_CLASS (mode) == MODE_INT)
3817 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3823 /* If we want a subreg of a constant, at offset 0,
3824 take the low bits. On a little-endian machine, that's
3825 always valid. On a big-endian machine, it's valid
3826 only if the constant's mode fits in one word. Note that we
3827 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3828 if (CONSTANT_P (SUBREG_REG (x))
3829 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3830 || ! WORDS_BIG_ENDIAN)
3831 ? SUBREG_WORD (x) == 0
3833 == ((GET_MODE_SIZE (op0_mode)
3834 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3836 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3837 && (! WORDS_BIG_ENDIAN
3838 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3839 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3841 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3842 since we are saying that the high bits don't matter. */
3843 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3844 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3846 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3847 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3848 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3849 return SUBREG_REG (x);
3852 /* Note that we cannot do any narrowing for non-constants since
3853 we might have been counting on using the fact that some bits were
3854 zero. We now do this in the SET. */
3859 /* (not (plus X -1)) can become (neg X). */
3860 if (GET_CODE (XEXP (x, 0)) == PLUS
3861 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3862 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3864 /* Similarly, (not (neg X)) is (plus X -1). */
3865 if (GET_CODE (XEXP (x, 0)) == NEG)
3866 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3869 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3870 if (GET_CODE (XEXP (x, 0)) == XOR
3871 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3872 && (temp = simplify_unary_operation (NOT, mode,
3873 XEXP (XEXP (x, 0), 1),
3875 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3877 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3878 other than 1, but that is not valid. We could do a similar
3879 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3880 but this doesn't seem common enough to bother with. */
3881 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3882 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3883 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3884 XEXP (XEXP (x, 0), 1));
3886 if (GET_CODE (XEXP (x, 0)) == SUBREG
3887 && subreg_lowpart_p (XEXP (x, 0))
3888 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3889 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3890 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3891 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3893 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3895 x = gen_rtx_ROTATE (inner_mode,
3896 gen_unary (NOT, inner_mode, inner_mode,
3898 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3899 return gen_lowpart_for_combine (mode, x);
3902 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3903 reversing the comparison code if valid. */
3904 if (STORE_FLAG_VALUE == -1
3905 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3906 && reversible_comparison_p (XEXP (x, 0)))
3907 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3908 mode, XEXP (XEXP (x, 0), 0),
3909 XEXP (XEXP (x, 0), 1));
3911 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3912 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3913 perform the above simplification. */
3915 if (STORE_FLAG_VALUE == -1
3916 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3917 && XEXP (x, 1) == const1_rtx
3918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3919 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3920 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3922 /* Apply De Morgan's laws to reduce number of patterns for machines
3923 with negating logical insns (and-not, nand, etc.). If result has
3924 only one NOT, put it first, since that is how the patterns are
3927 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3929 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3931 if (GET_CODE (in1) == NOT)
3932 in1 = XEXP (in1, 0);
3934 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3936 if (GET_CODE (in2) == NOT)
3937 in2 = XEXP (in2, 0);
3938 else if (GET_CODE (in2) == CONST_INT
3939 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3940 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3942 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3944 if (GET_CODE (in2) == NOT)
3947 in2 = in1; in1 = tem;
3950 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3956 /* (neg (plus X 1)) can become (not X). */
3957 if (GET_CODE (XEXP (x, 0)) == PLUS
3958 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3959 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3961 /* Similarly, (neg (not X)) is (plus X 1). */
3962 if (GET_CODE (XEXP (x, 0)) == NOT)
3963 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3965 /* (neg (minus X Y)) can become (minus Y X). */
3966 if (GET_CODE (XEXP (x, 0)) == MINUS
3967 && (! FLOAT_MODE_P (mode)
3968 /* x-y != -(y-x) with IEEE floating point. */
3969 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3971 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3972 XEXP (XEXP (x, 0), 0));
3974 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3975 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3976 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3977 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3979 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3980 if we can then eliminate the NEG (e.g.,
3981 if the operand is a constant). */
3983 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3985 temp = simplify_unary_operation (NEG, mode,
3986 XEXP (XEXP (x, 0), 0), mode);
3989 SUBST (XEXP (XEXP (x, 0), 0), temp);
3994 temp = expand_compound_operation (XEXP (x, 0));
3996 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3997 replaced by (lshiftrt X C). This will convert
3998 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4000 if (GET_CODE (temp) == ASHIFTRT
4001 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4002 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4003 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4004 INTVAL (XEXP (temp, 1)));
4006 /* If X has only a single bit that might be nonzero, say, bit I, convert
4007 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4008 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4009 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4010 or a SUBREG of one since we'd be making the expression more
4011 complex if it was just a register. */
4013 if (GET_CODE (temp) != REG
4014 && ! (GET_CODE (temp) == SUBREG
4015 && GET_CODE (SUBREG_REG (temp)) == REG)
4016 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4018 rtx temp1 = simplify_shift_const
4019 (NULL_RTX, ASHIFTRT, mode,
4020 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4021 GET_MODE_BITSIZE (mode) - 1 - i),
4022 GET_MODE_BITSIZE (mode) - 1 - i);
4024 /* If all we did was surround TEMP with the two shifts, we
4025 haven't improved anything, so don't use it. Otherwise,
4026 we are better off with TEMP1. */
4027 if (GET_CODE (temp1) != ASHIFTRT
4028 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4029 || XEXP (XEXP (temp1, 0), 0) != temp)
4035 /* We can't handle truncation to a partial integer mode here
4036 because we don't know the real bitsize of the partial
4038 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4041 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4042 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4043 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4045 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4046 GET_MODE_MASK (mode), NULL_RTX, 0));
4048 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4049 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4050 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4051 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4052 return XEXP (XEXP (x, 0), 0);
4054 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4055 (OP:SI foo:SI) if OP is NEG or ABS. */
4056 if ((GET_CODE (XEXP (x, 0)) == ABS
4057 || GET_CODE (XEXP (x, 0)) == NEG)
4058 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4059 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4060 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4061 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4062 XEXP (XEXP (XEXP (x, 0), 0), 0));
4064 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4066 if (GET_CODE (XEXP (x, 0)) == SUBREG
4067 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4068 && subreg_lowpart_p (XEXP (x, 0)))
4069 return SUBREG_REG (XEXP (x, 0));
4071 /* If we know that the value is already truncated, we can
4072 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4073 is nonzero for the corresponding modes. But don't do this
4074 for an (LSHIFTRT (MULT ...)) since this will cause problems
4075 with the umulXi3_highpart patterns. */
4076 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4077 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4078 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4079 >= GET_MODE_BITSIZE (mode) + 1
4080 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4081 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4082 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4084 /* A truncate of a comparison can be replaced with a subreg if
4085 STORE_FLAG_VALUE permits. This is like the previous test,
4086 but it works even if the comparison is done in a mode larger
4087 than HOST_BITS_PER_WIDE_INT. */
4088 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4089 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4090 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
4091 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4093 /* Similarly, a truncate of a register whose value is a
4094 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4096 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4097 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
4098 && (temp = get_last_value (XEXP (x, 0)))
4099 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4100 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4104 case FLOAT_TRUNCATE:
4105 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4106 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4107 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4108 return XEXP (XEXP (x, 0), 0);
4110 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4111 (OP:SF foo:SF) if OP is NEG or ABS. */
4112 if ((GET_CODE (XEXP (x, 0)) == ABS
4113 || GET_CODE (XEXP (x, 0)) == NEG)
4114 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4115 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4116 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4117 XEXP (XEXP (XEXP (x, 0), 0), 0));
4119 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4120 is (float_truncate:SF x). */
4121 if (GET_CODE (XEXP (x, 0)) == SUBREG
4122 && subreg_lowpart_p (XEXP (x, 0))
4123 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4124 return SUBREG_REG (XEXP (x, 0));
4129 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4130 using cc0, in which case we want to leave it as a COMPARE
4131 so we can distinguish it from a register-register-copy. */
4132 if (XEXP (x, 1) == const0_rtx)
4135 /* In IEEE floating point, x-0 is not the same as x. */
4136 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4137 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4139 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4145 /* (const (const X)) can become (const X). Do it this way rather than
4146 returning the inner CONST since CONST can be shared with a
4148 if (GET_CODE (XEXP (x, 0)) == CONST)
4149 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4154 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4155 can add in an offset. find_split_point will split this address up
4156 again if it doesn't match. */
4157 if (GET_CODE (XEXP (x, 0)) == HIGH
4158 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4164 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4165 outermost. That's because that's the way indexed addresses are
4166 supposed to appear. This code used to check many more cases, but
4167 they are now checked elsewhere. */
4168 if (GET_CODE (XEXP (x, 0)) == PLUS
4169 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4170 return gen_binary (PLUS, mode,
4171 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4173 XEXP (XEXP (x, 0), 1));
4175 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4176 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4177 bit-field and can be replaced by either a sign_extend or a
4178 sign_extract. The `and' may be a zero_extend and the two
4179 <c>, -<c> constants may be reversed. */
4180 if (GET_CODE (XEXP (x, 0)) == XOR
4181 && GET_CODE (XEXP (x, 1)) == CONST_INT
4182 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4183 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
4184 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4185 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4186 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4187 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4188 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4189 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4190 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4191 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4192 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4193 == (unsigned int) i + 1))))
4194 return simplify_shift_const
4195 (NULL_RTX, ASHIFTRT, mode,
4196 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4197 XEXP (XEXP (XEXP (x, 0), 0), 0),
4198 GET_MODE_BITSIZE (mode) - (i + 1)),
4199 GET_MODE_BITSIZE (mode) - (i + 1));
4201 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4202 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4203 is 1. This produces better code than the alternative immediately
4205 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4206 && reversible_comparison_p (XEXP (x, 0))
4207 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4208 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4210 gen_unary (NEG, mode, mode,
4211 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4212 mode, XEXP (XEXP (x, 0), 0),
4213 XEXP (XEXP (x, 0), 1)));
4215 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4216 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4217 the bitsize of the mode - 1. This allows simplification of
4218 "a = (b & 8) == 0;" */
4219 if (XEXP (x, 1) == constm1_rtx
4220 && GET_CODE (XEXP (x, 0)) != REG
4221 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4222 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4223 && nonzero_bits (XEXP (x, 0), mode) == 1)
4224 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4225 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4226 gen_rtx_combine (XOR, mode,
4227 XEXP (x, 0), const1_rtx),
4228 GET_MODE_BITSIZE (mode) - 1),
4229 GET_MODE_BITSIZE (mode) - 1);
4231 /* If we are adding two things that have no bits in common, convert
4232 the addition into an IOR. This will often be further simplified,
4233 for example in cases like ((a & 1) + (a & 2)), which can
4236 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4237 && (nonzero_bits (XEXP (x, 0), mode)
4238 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4240 /* Try to simplify the expression further. */
4241 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4242 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4244 /* If we could, great. If not, do not go ahead with the IOR
4245 replacement, since PLUS appears in many special purpose
4246 address arithmetic instructions. */
4247 if (GET_CODE (temp) != CLOBBER && temp != tor)
4253 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4254 by reversing the comparison code if valid. */
4255 if (STORE_FLAG_VALUE == 1
4256 && XEXP (x, 0) == const1_rtx
4257 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4258 && reversible_comparison_p (XEXP (x, 1)))
4259 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4260 mode, XEXP (XEXP (x, 1), 0),
4261 XEXP (XEXP (x, 1), 1));
4263 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4264 (and <foo> (const_int pow2-1)) */
4265 if (GET_CODE (XEXP (x, 1)) == AND
4266 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4267 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4268 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4269 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4270 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4272 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4274 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4275 return gen_binary (MINUS, mode,
4276 gen_binary (MINUS, mode, XEXP (x, 0),
4277 XEXP (XEXP (x, 1), 0)),
4278 XEXP (XEXP (x, 1), 1));
4282 /* If we have (mult (plus A B) C), apply the distributive law and then
4283 the inverse distributive law to see if things simplify. This
4284 occurs mostly in addresses, often when unrolling loops. */
4286 if (GET_CODE (XEXP (x, 0)) == PLUS)
4288 x = apply_distributive_law
4289 (gen_binary (PLUS, mode,
4290 gen_binary (MULT, mode,
4291 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4292 gen_binary (MULT, mode,
4293 XEXP (XEXP (x, 0), 1),
4294 copy_rtx (XEXP (x, 1)))));
4296 if (GET_CODE (x) != MULT)
4302 /* If this is a divide by a power of two, treat it as a shift if
4303 its first operand is a shift. */
4304 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4305 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4306 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4307 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4308 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4309 || GET_CODE (XEXP (x, 0)) == ROTATE
4310 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4311 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4315 case GT: case GTU: case GE: case GEU:
4316 case LT: case LTU: case LE: case LEU:
4317 /* If the first operand is a condition code, we can't do anything
4319 if (GET_CODE (XEXP (x, 0)) == COMPARE
4320 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4322 && XEXP (x, 0) != cc0_rtx
4326 rtx op0 = XEXP (x, 0);
4327 rtx op1 = XEXP (x, 1);
4328 enum rtx_code new_code;
4330 if (GET_CODE (op0) == COMPARE)
4331 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4333 /* Simplify our comparison, if possible. */
4334 new_code = simplify_comparison (code, &op0, &op1);
4336 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4337 if only the low-order bit is possibly nonzero in X (such as when
4338 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4339 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4340 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4343 Remove any ZERO_EXTRACT we made when thinking this was a
4344 comparison. It may now be simpler to use, e.g., an AND. If a
4345 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4346 the call to make_compound_operation in the SET case. */
4348 if (STORE_FLAG_VALUE == 1
4349 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4350 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4351 return gen_lowpart_for_combine (mode,
4352 expand_compound_operation (op0));
4354 else if (STORE_FLAG_VALUE == 1
4355 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4356 && op1 == const0_rtx
4357 && (num_sign_bit_copies (op0, mode)
4358 == GET_MODE_BITSIZE (mode)))
4360 op0 = expand_compound_operation (op0);
4361 return gen_unary (NEG, mode, mode,
4362 gen_lowpart_for_combine (mode, op0));
4365 else if (STORE_FLAG_VALUE == 1
4366 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4367 && op1 == const0_rtx
4368 && nonzero_bits (op0, mode) == 1)
4370 op0 = expand_compound_operation (op0);
4371 return gen_binary (XOR, mode,
4372 gen_lowpart_for_combine (mode, op0),
4376 else if (STORE_FLAG_VALUE == 1
4377 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4378 && op1 == const0_rtx
4379 && (num_sign_bit_copies (op0, mode)
4380 == GET_MODE_BITSIZE (mode)))
4382 op0 = expand_compound_operation (op0);
4383 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4386 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4388 if (STORE_FLAG_VALUE == -1
4389 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4390 && op1 == const0_rtx
4391 && (num_sign_bit_copies (op0, mode)
4392 == GET_MODE_BITSIZE (mode)))
4393 return gen_lowpart_for_combine (mode,
4394 expand_compound_operation (op0));
4396 else if (STORE_FLAG_VALUE == -1
4397 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4398 && op1 == const0_rtx
4399 && nonzero_bits (op0, mode) == 1)
4401 op0 = expand_compound_operation (op0);
4402 return gen_unary (NEG, mode, mode,
4403 gen_lowpart_for_combine (mode, op0));
4406 else if (STORE_FLAG_VALUE == -1
4407 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4408 && op1 == const0_rtx
4409 && (num_sign_bit_copies (op0, mode)
4410 == GET_MODE_BITSIZE (mode)))
4412 op0 = expand_compound_operation (op0);
4413 return gen_unary (NOT, mode, mode,
4414 gen_lowpart_for_combine (mode, op0));
4417 /* If X is 0/1, (eq X 0) is X-1. */
4418 else if (STORE_FLAG_VALUE == -1
4419 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4420 && op1 == const0_rtx
4421 && nonzero_bits (op0, mode) == 1)
4423 op0 = expand_compound_operation (op0);
4424 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4427 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4428 one bit that might be nonzero, we can convert (ne x 0) to
4429 (ashift x c) where C puts the bit in the sign bit. Remove any
4430 AND with STORE_FLAG_VALUE when we are done, since we are only
4431 going to test the sign bit. */
4432 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4433 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4434 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4435 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4436 && op1 == const0_rtx
4437 && mode == GET_MODE (op0)
4438 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4440 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4441 expand_compound_operation (op0),
4442 GET_MODE_BITSIZE (mode) - 1 - i);
4443 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4449 /* If the code changed, return a whole new comparison. */
4450 if (new_code != code)
4451 return gen_rtx_combine (new_code, mode, op0, op1);
4453 /* Otherwise, keep this operation, but maybe change its operands.
4454 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4455 SUBST (XEXP (x, 0), op0);
4456 SUBST (XEXP (x, 1), op1);
4461 return simplify_if_then_else (x);
4467 /* If we are processing SET_DEST, we are done. */
4471 return expand_compound_operation (x);
4474 return simplify_set (x);
4479 return simplify_logical (x, last);
4482 /* (abs (neg <foo>)) -> (abs <foo>) */
4483 if (GET_CODE (XEXP (x, 0)) == NEG)
4484 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4486 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4488 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4491 /* If operand is something known to be positive, ignore the ABS. */
4492 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4493 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4494 <= HOST_BITS_PER_WIDE_INT)
4495 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4496 & ((HOST_WIDE_INT) 1
4497 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4502 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4503 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4504 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4509 /* (ffs (*_extend <X>)) = (ffs <X>) */
4510 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4511 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4512 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4516 /* (float (sign_extend <X>)) = (float <X>). */
4517 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4518 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4526 /* If this is a shift by a constant amount, simplify it. */
4527 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4528 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4529 INTVAL (XEXP (x, 1)));
4531 #ifdef SHIFT_COUNT_TRUNCATED
4532 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4534 force_to_mode (XEXP (x, 1), GET_MODE (x),
4536 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4550 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4553 simplify_if_then_else (x)
4556 enum machine_mode mode = GET_MODE (x);
4557 rtx cond = XEXP (x, 0);
4558 rtx true = XEXP (x, 1);
4559 rtx false = XEXP (x, 2);
4560 enum rtx_code true_code = GET_CODE (cond);
4561 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4565 /* Simplify storing of the truth value. */
4566 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4567 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4569 /* Also when the truth value has to be reversed. */
4570 if (comparison_p && reversible_comparison_p (cond)
4571 && true == const0_rtx && false == const_true_rtx)
4572 return gen_binary (reverse_condition (true_code),
4573 mode, XEXP (cond, 0), XEXP (cond, 1));
4575 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4576 in it is being compared against certain values. Get the true and false
4577 comparisons and see if that says anything about the value of each arm. */
4579 if (comparison_p && reversible_comparison_p (cond)
4580 && GET_CODE (XEXP (cond, 0)) == REG)
4583 rtx from = XEXP (cond, 0);
4584 enum rtx_code false_code = reverse_condition (true_code);
4585 rtx true_val = XEXP (cond, 1);
4586 rtx false_val = true_val;
4589 /* If FALSE_CODE is EQ, swap the codes and arms. */
4591 if (false_code == EQ)
4593 swapped = 1, true_code = EQ, false_code = NE;
4594 temp = true, true = false, false = temp;
4597 /* If we are comparing against zero and the expression being tested has
4598 only a single bit that might be nonzero, that is its value when it is
4599 not equal to zero. Similarly if it is known to be -1 or 0. */
4601 if (true_code == EQ && true_val == const0_rtx
4602 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4603 false_code = EQ, false_val = GEN_INT (nzb);
4604 else if (true_code == EQ && true_val == const0_rtx
4605 && (num_sign_bit_copies (from, GET_MODE (from))
4606 == GET_MODE_BITSIZE (GET_MODE (from))))
4607 false_code = EQ, false_val = constm1_rtx;
4609 /* Now simplify an arm if we know the value of the register in the
4610 branch and it is used in the arm. Be careful due to the potential
4611 of locally-shared RTL. */
4613 if (reg_mentioned_p (from, true))
4614 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4615 pc_rtx, pc_rtx, 0, 0);
4616 if (reg_mentioned_p (from, false))
4617 false = subst (known_cond (copy_rtx (false), false_code,
4619 pc_rtx, pc_rtx, 0, 0);
4621 SUBST (XEXP (x, 1), swapped ? false : true);
4622 SUBST (XEXP (x, 2), swapped ? true : false);
4624 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4627 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4628 reversed, do so to avoid needing two sets of patterns for
4629 subtract-and-branch insns. Similarly if we have a constant in the true
4630 arm, the false arm is the same as the first operand of the comparison, or
4631 the false arm is more complicated than the true arm. */
4633 if (comparison_p && reversible_comparison_p (cond)
4635 || (CONSTANT_P (true)
4636 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4637 || true == const0_rtx
4638 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4639 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4640 || (GET_CODE (true) == SUBREG
4641 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4642 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4643 || reg_mentioned_p (true, false)
4644 || rtx_equal_p (false, XEXP (cond, 0))))
4646 true_code = reverse_condition (true_code);
4648 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4651 SUBST (XEXP (x, 1), false);
4652 SUBST (XEXP (x, 2), true);
4654 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4656 /* It is possible that the conditional has been simplified out. */
4657 true_code = GET_CODE (cond);
4658 comparison_p = GET_RTX_CLASS (true_code) == '<';
4661 /* If the two arms are identical, we don't need the comparison. */
4663 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4666 /* Convert a == b ? b : a to "a". */
4667 if (true_code == EQ && ! side_effects_p (cond)
4668 && rtx_equal_p (XEXP (cond, 0), false)
4669 && rtx_equal_p (XEXP (cond, 1), true))
4671 else if (true_code == NE && ! side_effects_p (cond)
4672 && rtx_equal_p (XEXP (cond, 0), true)
4673 && rtx_equal_p (XEXP (cond, 1), false))
4676 /* Look for cases where we have (abs x) or (neg (abs X)). */
4678 if (GET_MODE_CLASS (mode) == MODE_INT
4679 && GET_CODE (false) == NEG
4680 && rtx_equal_p (true, XEXP (false, 0))
4682 && rtx_equal_p (true, XEXP (cond, 0))
4683 && ! side_effects_p (true))
4688 return gen_unary (ABS, mode, mode, true);
4691 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4696 /* Look for MIN or MAX. */
4698 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4700 && rtx_equal_p (XEXP (cond, 0), true)
4701 && rtx_equal_p (XEXP (cond, 1), false)
4702 && ! side_effects_p (cond))
4707 return gen_binary (SMAX, mode, true, false);
4710 return gen_binary (SMIN, mode, true, false);
4713 return gen_binary (UMAX, mode, true, false);
4716 return gen_binary (UMIN, mode, true, false);
4721 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4722 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4723 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4724 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4725 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4726 neither 1 or -1, but it isn't worth checking for. */
4728 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4729 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4731 rtx t = make_compound_operation (true, SET);
4732 rtx f = make_compound_operation (false, SET);
4733 rtx cond_op0 = XEXP (cond, 0);
4734 rtx cond_op1 = XEXP (cond, 1);
4735 enum rtx_code op = NIL, extend_op = NIL;
4736 enum machine_mode m = mode;
4737 rtx z = 0, c1 = NULL_RTX;
4739 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4740 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4741 || GET_CODE (t) == ASHIFT
4742 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4743 && rtx_equal_p (XEXP (t, 0), f))
4744 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4746 /* If an identity-zero op is commutative, check whether there
4747 would be a match if we swapped the operands. */
4748 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4749 || GET_CODE (t) == XOR)
4750 && rtx_equal_p (XEXP (t, 1), f))
4751 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4752 else if (GET_CODE (t) == SIGN_EXTEND
4753 && (GET_CODE (XEXP (t, 0)) == PLUS
4754 || GET_CODE (XEXP (t, 0)) == MINUS
4755 || GET_CODE (XEXP (t, 0)) == IOR
4756 || GET_CODE (XEXP (t, 0)) == XOR
4757 || GET_CODE (XEXP (t, 0)) == ASHIFT
4758 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4759 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4760 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4761 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4762 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4763 && (num_sign_bit_copies (f, GET_MODE (f))
4764 > (GET_MODE_BITSIZE (mode)
4765 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4767 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4768 extend_op = SIGN_EXTEND;
4769 m = GET_MODE (XEXP (t, 0));
4771 else if (GET_CODE (t) == SIGN_EXTEND
4772 && (GET_CODE (XEXP (t, 0)) == PLUS
4773 || GET_CODE (XEXP (t, 0)) == IOR
4774 || GET_CODE (XEXP (t, 0)) == XOR)
4775 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4776 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4777 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4778 && (num_sign_bit_copies (f, GET_MODE (f))
4779 > (GET_MODE_BITSIZE (mode)
4780 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4782 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4783 extend_op = SIGN_EXTEND;
4784 m = GET_MODE (XEXP (t, 0));
4786 else if (GET_CODE (t) == ZERO_EXTEND
4787 && (GET_CODE (XEXP (t, 0)) == PLUS
4788 || GET_CODE (XEXP (t, 0)) == MINUS
4789 || GET_CODE (XEXP (t, 0)) == IOR
4790 || GET_CODE (XEXP (t, 0)) == XOR
4791 || GET_CODE (XEXP (t, 0)) == ASHIFT
4792 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4793 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4794 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4795 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4796 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4797 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4798 && ((nonzero_bits (f, GET_MODE (f))
4799 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4802 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4803 extend_op = ZERO_EXTEND;
4804 m = GET_MODE (XEXP (t, 0));
4806 else if (GET_CODE (t) == ZERO_EXTEND
4807 && (GET_CODE (XEXP (t, 0)) == PLUS
4808 || GET_CODE (XEXP (t, 0)) == IOR
4809 || GET_CODE (XEXP (t, 0)) == XOR)
4810 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4811 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4812 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4813 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4814 && ((nonzero_bits (f, GET_MODE (f))
4815 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4818 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4819 extend_op = ZERO_EXTEND;
4820 m = GET_MODE (XEXP (t, 0));
4825 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4826 pc_rtx, pc_rtx, 0, 0);
4827 temp = gen_binary (MULT, m, temp,
4828 gen_binary (MULT, m, c1, const_true_rtx));
4829 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4830 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4832 if (extend_op != NIL)
4833 temp = gen_unary (extend_op, mode, m, temp);
4839 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4840 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4841 negation of a single bit, we can convert this operation to a shift. We
4842 can actually do this more generally, but it doesn't seem worth it. */
4844 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4845 && false == const0_rtx && GET_CODE (true) == CONST_INT
4846 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4847 && (i = exact_log2 (INTVAL (true))) >= 0)
4848 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4849 == GET_MODE_BITSIZE (mode))
4850 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4852 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4853 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4858 /* Simplify X, a SET expression. Return the new expression. */
4864 rtx src = SET_SRC (x);
4865 rtx dest = SET_DEST (x);
4866 enum machine_mode mode
4867 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4871 /* (set (pc) (return)) gets written as (return). */
4872 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4875 /* Now that we know for sure which bits of SRC we are using, see if we can
4876 simplify the expression for the object knowing that we only need the
4879 if (GET_MODE_CLASS (mode) == MODE_INT)
4881 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4882 SUBST (SET_SRC (x), src);
4885 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4886 the comparison result and try to simplify it unless we already have used
4887 undobuf.other_insn. */
4888 if ((GET_CODE (src) == COMPARE
4893 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4894 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4895 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4896 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4898 enum rtx_code old_code = GET_CODE (*cc_use);
4899 enum rtx_code new_code;
4901 int other_changed = 0;
4902 enum machine_mode compare_mode = GET_MODE (dest);
4904 if (GET_CODE (src) == COMPARE)
4905 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4907 op0 = src, op1 = const0_rtx;
4909 /* Simplify our comparison, if possible. */
4910 new_code = simplify_comparison (old_code, &op0, &op1);
4912 #ifdef EXTRA_CC_MODES
4913 /* If this machine has CC modes other than CCmode, check to see if we
4914 need to use a different CC mode here. */
4915 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4916 #endif /* EXTRA_CC_MODES */
4918 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4919 /* If the mode changed, we have to change SET_DEST, the mode in the
4920 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4921 a hard register, just build new versions with the proper mode. If it
4922 is a pseudo, we lose unless it is only time we set the pseudo, in
4923 which case we can safely change its mode. */
4924 if (compare_mode != GET_MODE (dest))
4926 unsigned int regno = REGNO (dest);
4927 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4929 if (regno < FIRST_PSEUDO_REGISTER
4930 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4932 if (regno >= FIRST_PSEUDO_REGISTER)
4933 SUBST (regno_reg_rtx[regno], new_dest);
4935 SUBST (SET_DEST (x), new_dest);
4936 SUBST (XEXP (*cc_use, 0), new_dest);
4944 /* If the code changed, we have to build a new comparison in
4945 undobuf.other_insn. */
4946 if (new_code != old_code)
4948 unsigned HOST_WIDE_INT mask;
4950 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4953 /* If the only change we made was to change an EQ into an NE or
4954 vice versa, OP0 has only one bit that might be nonzero, and OP1
4955 is zero, check if changing the user of the condition code will
4956 produce a valid insn. If it won't, we can keep the original code
4957 in that insn by surrounding our operation with an XOR. */
4959 if (((old_code == NE && new_code == EQ)
4960 || (old_code == EQ && new_code == NE))
4961 && ! other_changed && op1 == const0_rtx
4962 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4963 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4965 rtx pat = PATTERN (other_insn), note = 0;
4967 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4968 && ! check_asm_operands (pat)))
4970 PUT_CODE (*cc_use, old_code);
4973 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4981 undobuf.other_insn = other_insn;
4984 /* If we are now comparing against zero, change our source if
4985 needed. If we do not use cc0, we always have a COMPARE. */
4986 if (op1 == const0_rtx && dest == cc0_rtx)
4988 SUBST (SET_SRC (x), op0);
4994 /* Otherwise, if we didn't previously have a COMPARE in the
4995 correct mode, we need one. */
4996 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4999 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
5004 /* Otherwise, update the COMPARE if needed. */
5005 SUBST (XEXP (src, 0), op0);
5006 SUBST (XEXP (src, 1), op1);
5011 /* Get SET_SRC in a form where we have placed back any
5012 compound expressions. Then do the checks below. */
5013 src = make_compound_operation (src, SET);
5014 SUBST (SET_SRC (x), src);
5017 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5018 and X being a REG or (subreg (reg)), we may be able to convert this to
5019 (set (subreg:m2 x) (op)).
5021 We can always do this if M1 is narrower than M2 because that means that
5022 we only care about the low bits of the result.
5024 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5025 perform a narrower operation than requested since the high-order bits will
5026 be undefined. On machine where it is defined, this transformation is safe
5027 as long as M1 and M2 have the same number of words. */
5029 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5030 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5031 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5033 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5034 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5035 #ifndef WORD_REGISTER_OPERATIONS
5036 && (GET_MODE_SIZE (GET_MODE (src))
5037 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5039 #ifdef CLASS_CANNOT_CHANGE_SIZE
5040 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5041 && (TEST_HARD_REG_BIT
5042 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
5044 && (GET_MODE_SIZE (GET_MODE (src))
5045 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
5047 && (GET_CODE (dest) == REG
5048 || (GET_CODE (dest) == SUBREG
5049 && GET_CODE (SUBREG_REG (dest)) == REG)))
5051 SUBST (SET_DEST (x),
5052 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5054 SUBST (SET_SRC (x), SUBREG_REG (src));
5056 src = SET_SRC (x), dest = SET_DEST (x);
5059 #ifdef LOAD_EXTEND_OP
5060 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5061 would require a paradoxical subreg. Replace the subreg with a
5062 zero_extend to avoid the reload that would otherwise be required. */
5064 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5065 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5066 && SUBREG_WORD (src) == 0
5067 && (GET_MODE_SIZE (GET_MODE (src))
5068 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5069 && GET_CODE (SUBREG_REG (src)) == MEM)
5072 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5073 GET_MODE (src), XEXP (src, 0)));
5079 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5080 are comparing an item known to be 0 or -1 against 0, use a logical
5081 operation instead. Check for one of the arms being an IOR of the other
5082 arm with some value. We compute three terms to be IOR'ed together. In
5083 practice, at most two will be nonzero. Then we do the IOR's. */
5085 if (GET_CODE (dest) != PC
5086 && GET_CODE (src) == IF_THEN_ELSE
5087 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5088 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5089 && XEXP (XEXP (src, 0), 1) == const0_rtx
5090 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5091 #ifdef HAVE_conditional_move
5092 && ! can_conditionally_move_p (GET_MODE (src))
5094 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5095 GET_MODE (XEXP (XEXP (src, 0), 0)))
5096 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5097 && ! side_effects_p (src))
5099 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5100 ? XEXP (src, 1) : XEXP (src, 2));
5101 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5102 ? XEXP (src, 2) : XEXP (src, 1));
5103 rtx term1 = const0_rtx, term2, term3;
5105 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5106 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5107 else if (GET_CODE (true) == IOR
5108 && rtx_equal_p (XEXP (true, 1), false))
5109 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5110 else if (GET_CODE (false) == IOR
5111 && rtx_equal_p (XEXP (false, 0), true))
5112 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5113 else if (GET_CODE (false) == IOR
5114 && rtx_equal_p (XEXP (false, 1), true))
5115 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5117 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5118 term3 = gen_binary (AND, GET_MODE (src),
5119 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5120 XEXP (XEXP (src, 0), 0)),
5124 gen_binary (IOR, GET_MODE (src),
5125 gen_binary (IOR, GET_MODE (src), term1, term2),
5131 #ifdef HAVE_conditional_arithmetic
5132 /* If we have conditional arithmetic and the operand of a SET is
5133 a conditional expression, replace this with an IF_THEN_ELSE.
5134 We can either have a conditional expression or a MULT of that expression
5136 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5137 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5138 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5139 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5140 || (GET_CODE (XEXP (src, 0)) == MULT
5141 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5142 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5144 rtx cond = XEXP (src, 0);
5145 rtx true_val = const1_rtx;
5146 rtx false_arm, true_arm;
5148 if (GET_CODE (cond) == MULT)
5150 true_val = XEXP (cond, 1);
5151 cond = XEXP (cond, 0);
5154 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5156 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5157 GET_MODE (XEXP (src, 0)), true_val);
5158 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5159 GET_MODE (XEXP (src, 0)), const0_rtx);
5163 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5164 true_val, XEXP (src, 1));
5165 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5166 const0_rtx, XEXP (src, 1));
5169 /* Canonicalize if true_arm is the simpler one. */
5170 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5171 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5172 && reversible_comparison_p (cond))
5174 rtx temp = true_arm;
5176 true_arm = false_arm;
5179 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5180 GET_MODE (cond), XEXP (cond, 0),
5184 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5185 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5188 true_arm, false_arm);
5189 SUBST (SET_SRC (x), src);
5193 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5194 whole thing fail. */
5195 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5197 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5200 /* Convert this into a field assignment operation, if possible. */
5201 return make_field_assignment (x);
5204 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5205 result. LAST is nonzero if this is the last retry. */
5208 simplify_logical (x, last)
5212 enum machine_mode mode = GET_MODE (x);
5213 rtx op0 = XEXP (x, 0);
5214 rtx op1 = XEXP (x, 1);
5216 switch (GET_CODE (x))
5219 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5220 insn (and may simplify more). */
5221 if (GET_CODE (op0) == XOR
5222 && rtx_equal_p (XEXP (op0, 0), op1)
5223 && ! side_effects_p (op1))
5224 x = gen_binary (AND, mode,
5225 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5227 if (GET_CODE (op0) == XOR
5228 && rtx_equal_p (XEXP (op0, 1), op1)
5229 && ! side_effects_p (op1))
5230 x = gen_binary (AND, mode,
5231 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5233 /* Similarly for (~ (A ^ B)) & A. */
5234 if (GET_CODE (op0) == NOT
5235 && GET_CODE (XEXP (op0, 0)) == XOR
5236 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5237 && ! side_effects_p (op1))
5238 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5240 if (GET_CODE (op0) == NOT
5241 && GET_CODE (XEXP (op0, 0)) == XOR
5242 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5243 && ! side_effects_p (op1))
5244 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5246 /* We can call simplify_and_const_int only if we don't lose
5247 any (sign) bits when converting INTVAL (op1) to
5248 "unsigned HOST_WIDE_INT". */
5249 if (GET_CODE (op1) == CONST_INT
5250 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5251 || INTVAL (op1) > 0))
5253 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5255 /* If we have (ior (and (X C1) C2)) and the next restart would be
5256 the last, simplify this by making C1 as small as possible
5259 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5260 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5261 && GET_CODE (op1) == CONST_INT)
5262 return gen_binary (IOR, mode,
5263 gen_binary (AND, mode, XEXP (op0, 0),
5264 GEN_INT (INTVAL (XEXP (op0, 1))
5265 & ~ INTVAL (op1))), op1);
5267 if (GET_CODE (x) != AND)
5270 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5271 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5272 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5275 /* Convert (A | B) & A to A. */
5276 if (GET_CODE (op0) == IOR
5277 && (rtx_equal_p (XEXP (op0, 0), op1)
5278 || rtx_equal_p (XEXP (op0, 1), op1))
5279 && ! side_effects_p (XEXP (op0, 0))
5280 && ! side_effects_p (XEXP (op0, 1)))
5283 /* In the following group of tests (and those in case IOR below),
5284 we start with some combination of logical operations and apply
5285 the distributive law followed by the inverse distributive law.
5286 Most of the time, this results in no change. However, if some of
5287 the operands are the same or inverses of each other, simplifications
5290 For example, (and (ior A B) (not B)) can occur as the result of
5291 expanding a bit field assignment. When we apply the distributive
5292 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5293 which then simplifies to (and (A (not B))).
5295 If we have (and (ior A B) C), apply the distributive law and then
5296 the inverse distributive law to see if things simplify. */
5298 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5300 x = apply_distributive_law
5301 (gen_binary (GET_CODE (op0), mode,
5302 gen_binary (AND, mode, XEXP (op0, 0), op1),
5303 gen_binary (AND, mode, XEXP (op0, 1),
5305 if (GET_CODE (x) != AND)
5309 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5310 return apply_distributive_law
5311 (gen_binary (GET_CODE (op1), mode,
5312 gen_binary (AND, mode, XEXP (op1, 0), op0),
5313 gen_binary (AND, mode, XEXP (op1, 1),
5316 /* Similarly, taking advantage of the fact that
5317 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5319 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5320 return apply_distributive_law
5321 (gen_binary (XOR, mode,
5322 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5323 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5326 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5327 return apply_distributive_law
5328 (gen_binary (XOR, mode,
5329 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5330 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5334 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5335 if (GET_CODE (op1) == CONST_INT
5336 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5337 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5340 /* Convert (A & B) | A to A. */
5341 if (GET_CODE (op0) == AND
5342 && (rtx_equal_p (XEXP (op0, 0), op1)
5343 || rtx_equal_p (XEXP (op0, 1), op1))
5344 && ! side_effects_p (XEXP (op0, 0))
5345 && ! side_effects_p (XEXP (op0, 1)))
5348 /* If we have (ior (and A B) C), apply the distributive law and then
5349 the inverse distributive law to see if things simplify. */
5351 if (GET_CODE (op0) == AND)
5353 x = apply_distributive_law
5354 (gen_binary (AND, mode,
5355 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5356 gen_binary (IOR, mode, XEXP (op0, 1),
5359 if (GET_CODE (x) != IOR)
5363 if (GET_CODE (op1) == AND)
5365 x = apply_distributive_law
5366 (gen_binary (AND, mode,
5367 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5368 gen_binary (IOR, mode, XEXP (op1, 1),
5371 if (GET_CODE (x) != IOR)
5375 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5376 mode size to (rotate A CX). */
5378 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5379 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5380 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5381 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5382 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5383 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5384 == GET_MODE_BITSIZE (mode)))
5385 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5386 (GET_CODE (op0) == ASHIFT
5387 ? XEXP (op0, 1) : XEXP (op1, 1)));
5389 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5390 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5391 does not affect any of the bits in OP1, it can really be done
5392 as a PLUS and we can associate. We do this by seeing if OP1
5393 can be safely shifted left C bits. */
5394 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5395 && GET_CODE (XEXP (op0, 0)) == PLUS
5396 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5397 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5398 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5400 int count = INTVAL (XEXP (op0, 1));
5401 HOST_WIDE_INT mask = INTVAL (op1) << count;
5403 if (mask >> count == INTVAL (op1)
5404 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5406 SUBST (XEXP (XEXP (op0, 0), 1),
5407 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5414 /* If we are XORing two things that have no bits in common,
5415 convert them into an IOR. This helps to detect rotation encoded
5416 using those methods and possibly other simplifications. */
5418 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5419 && (nonzero_bits (op0, mode)
5420 & nonzero_bits (op1, mode)) == 0)
5421 return (gen_binary (IOR, mode, op0, op1));
5423 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5424 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5427 int num_negated = 0;
5429 if (GET_CODE (op0) == NOT)
5430 num_negated++, op0 = XEXP (op0, 0);
5431 if (GET_CODE (op1) == NOT)
5432 num_negated++, op1 = XEXP (op1, 0);
5434 if (num_negated == 2)
5436 SUBST (XEXP (x, 0), op0);
5437 SUBST (XEXP (x, 1), op1);
5439 else if (num_negated == 1)
5440 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5443 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5444 correspond to a machine insn or result in further simplifications
5445 if B is a constant. */
5447 if (GET_CODE (op0) == AND
5448 && rtx_equal_p (XEXP (op0, 1), op1)
5449 && ! side_effects_p (op1))
5450 return gen_binary (AND, mode,
5451 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5454 else if (GET_CODE (op0) == AND
5455 && rtx_equal_p (XEXP (op0, 0), op1)
5456 && ! side_effects_p (op1))
5457 return gen_binary (AND, mode,
5458 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5461 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5462 comparison if STORE_FLAG_VALUE is 1. */
5463 if (STORE_FLAG_VALUE == 1
5464 && op1 == const1_rtx
5465 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5466 && reversible_comparison_p (op0))
5467 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5468 mode, XEXP (op0, 0), XEXP (op0, 1));
5470 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5471 is (lt foo (const_int 0)), so we can perform the above
5472 simplification if STORE_FLAG_VALUE is 1. */
5474 if (STORE_FLAG_VALUE == 1
5475 && op1 == const1_rtx
5476 && GET_CODE (op0) == LSHIFTRT
5477 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5478 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5479 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5481 /* (xor (comparison foo bar) (const_int sign-bit))
5482 when STORE_FLAG_VALUE is the sign bit. */
5483 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5484 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5485 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5486 && op1 == const_true_rtx
5487 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5488 && reversible_comparison_p (op0))
5489 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5490 mode, XEXP (op0, 0), XEXP (op0, 1));
5501 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5502 operations" because they can be replaced with two more basic operations.
5503 ZERO_EXTEND is also considered "compound" because it can be replaced with
5504 an AND operation, which is simpler, though only one operation.
5506 The function expand_compound_operation is called with an rtx expression
5507 and will convert it to the appropriate shifts and AND operations,
5508 simplifying at each stage.
5510 The function make_compound_operation is called to convert an expression
5511 consisting of shifts and ANDs into the equivalent compound expression.
5512 It is the inverse of this function, loosely speaking. */
5515 expand_compound_operation (x)
5518 unsigned HOST_WIDE_INT pos = 0, len;
5520 unsigned int modewidth;
5523 switch (GET_CODE (x))
5528 /* We can't necessarily use a const_int for a multiword mode;
5529 it depends on implicitly extending the value.
5530 Since we don't know the right way to extend it,
5531 we can't tell whether the implicit way is right.
5533 Even for a mode that is no wider than a const_int,
5534 we can't win, because we need to sign extend one of its bits through
5535 the rest of it, and we don't know which bit. */
5536 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5539 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5540 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5541 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5542 reloaded. If not for that, MEM's would very rarely be safe.
5544 Reject MODEs bigger than a word, because we might not be able
5545 to reference a two-register group starting with an arbitrary register
5546 (and currently gen_lowpart might crash for a SUBREG). */
5548 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5551 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5552 /* If the inner object has VOIDmode (the only way this can happen
5553 is if it is a ASM_OPERANDS), we can't do anything since we don't
5554 know how much masking to do. */
5563 /* If the operand is a CLOBBER, just return it. */
5564 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5567 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5568 || GET_CODE (XEXP (x, 2)) != CONST_INT
5569 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5572 len = INTVAL (XEXP (x, 1));
5573 pos = INTVAL (XEXP (x, 2));
5575 /* If this goes outside the object being extracted, replace the object
5576 with a (use (mem ...)) construct that only combine understands
5577 and is used only for this purpose. */
5578 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5579 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5581 if (BITS_BIG_ENDIAN)
5582 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5589 /* Convert sign extension to zero extension, if we know that the high
5590 bit is not set, as this is easier to optimize. It will be converted
5591 back to cheaper alternative in make_extraction. */
5592 if (GET_CODE (x) == SIGN_EXTEND
5593 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5594 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5595 & ~ (((unsigned HOST_WIDE_INT)
5596 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5600 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5601 return expand_compound_operation (temp);
5604 /* We can optimize some special cases of ZERO_EXTEND. */
5605 if (GET_CODE (x) == ZERO_EXTEND)
5607 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5608 know that the last value didn't have any inappropriate bits
5610 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5611 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5612 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5613 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5614 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5615 return XEXP (XEXP (x, 0), 0);
5617 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5618 if (GET_CODE (XEXP (x, 0)) == SUBREG
5619 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5620 && subreg_lowpart_p (XEXP (x, 0))
5621 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5622 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5623 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5624 return SUBREG_REG (XEXP (x, 0));
5626 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5627 is a comparison and STORE_FLAG_VALUE permits. This is like
5628 the first case, but it works even when GET_MODE (x) is larger
5629 than HOST_WIDE_INT. */
5630 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5631 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5632 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5633 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5634 <= HOST_BITS_PER_WIDE_INT)
5635 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5636 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5637 return XEXP (XEXP (x, 0), 0);
5639 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5640 if (GET_CODE (XEXP (x, 0)) == SUBREG
5641 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5642 && subreg_lowpart_p (XEXP (x, 0))
5643 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5644 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5645 <= HOST_BITS_PER_WIDE_INT)
5646 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5647 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5648 return SUBREG_REG (XEXP (x, 0));
5652 /* If we reach here, we want to return a pair of shifts. The inner
5653 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5654 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5655 logical depending on the value of UNSIGNEDP.
5657 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5658 converted into an AND of a shift.
5660 We must check for the case where the left shift would have a negative
5661 count. This can happen in a case like (x >> 31) & 255 on machines
5662 that can't shift by a constant. On those machines, we would first
5663 combine the shift with the AND to produce a variable-position
5664 extraction. Then the constant of 31 would be substituted in to produce
5665 a such a position. */
5667 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5668 if (modewidth + len >= pos)
5669 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5671 simplify_shift_const (NULL_RTX, ASHIFT,
5674 modewidth - pos - len),
5677 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5678 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5679 simplify_shift_const (NULL_RTX, LSHIFTRT,
5682 ((HOST_WIDE_INT) 1 << len) - 1);
5684 /* Any other cases we can't handle. */
5688 /* If we couldn't do this for some reason, return the original
5690 if (GET_CODE (tem) == CLOBBER)
5696 /* X is a SET which contains an assignment of one object into
5697 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5698 or certain SUBREGS). If possible, convert it into a series of
5701 We half-heartedly support variable positions, but do not at all
5702 support variable lengths. */
5705 expand_field_assignment (x)
5709 rtx pos; /* Always counts from low bit. */
5712 enum machine_mode compute_mode;
5714 /* Loop until we find something we can't simplify. */
5717 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5718 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5720 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5721 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5722 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5724 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5725 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5727 inner = XEXP (SET_DEST (x), 0);
5728 len = INTVAL (XEXP (SET_DEST (x), 1));
5729 pos = XEXP (SET_DEST (x), 2);
5731 /* If the position is constant and spans the width of INNER,
5732 surround INNER with a USE to indicate this. */
5733 if (GET_CODE (pos) == CONST_INT
5734 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5735 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5737 if (BITS_BIG_ENDIAN)
5739 if (GET_CODE (pos) == CONST_INT)
5740 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5742 else if (GET_CODE (pos) == MINUS
5743 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5744 && (INTVAL (XEXP (pos, 1))
5745 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5746 /* If position is ADJUST - X, new position is X. */
5747 pos = XEXP (pos, 0);
5749 pos = gen_binary (MINUS, GET_MODE (pos),
5750 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5756 /* A SUBREG between two modes that occupy the same numbers of words
5757 can be done by moving the SUBREG to the source. */
5758 else if (GET_CODE (SET_DEST (x)) == SUBREG
5759 /* We need SUBREGs to compute nonzero_bits properly. */
5760 && nonzero_sign_valid
5761 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5762 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5763 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5764 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5766 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5767 gen_lowpart_for_combine
5768 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5775 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5776 inner = SUBREG_REG (inner);
5778 compute_mode = GET_MODE (inner);
5780 /* Don't attempt bitwise arithmetic on non-integral modes. */
5781 if (! INTEGRAL_MODE_P (compute_mode))
5783 enum machine_mode imode;
5785 /* Something is probably seriously wrong if this matches. */
5786 if (! FLOAT_MODE_P (compute_mode))
5789 /* Try to find an integral mode to pun with. */
5790 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5791 if (imode == BLKmode)
5794 compute_mode = imode;
5795 inner = gen_lowpart_for_combine (imode, inner);
5798 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5799 if (len < HOST_BITS_PER_WIDE_INT)
5800 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5804 /* Now compute the equivalent expression. Make a copy of INNER
5805 for the SET_DEST in case it is a MEM into which we will substitute;
5806 we don't want shared RTL in that case. */
5808 (VOIDmode, copy_rtx (inner),
5809 gen_binary (IOR, compute_mode,
5810 gen_binary (AND, compute_mode,
5811 gen_unary (NOT, compute_mode,
5817 gen_binary (ASHIFT, compute_mode,
5818 gen_binary (AND, compute_mode,
5819 gen_lowpart_for_combine
5820 (compute_mode, SET_SRC (x)),
5828 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5829 it is an RTX that represents a variable starting position; otherwise,
5830 POS is the (constant) starting bit position (counted from the LSB).
5832 INNER may be a USE. This will occur when we started with a bitfield
5833 that went outside the boundary of the object in memory, which is
5834 allowed on most machines. To isolate this case, we produce a USE
5835 whose mode is wide enough and surround the MEM with it. The only
5836 code that understands the USE is this routine. If it is not removed,
5837 it will cause the resulting insn not to match.
5839 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5842 IN_DEST is non-zero if this is a reference in the destination of a
5843 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5844 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5847 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5848 ZERO_EXTRACT should be built even for bits starting at bit 0.
5850 MODE is the desired mode of the result (if IN_DEST == 0).
5852 The result is an RTX for the extraction or NULL_RTX if the target
5856 make_extraction (mode, inner, pos, pos_rtx, len,
5857 unsignedp, in_dest, in_compare)
5858 enum machine_mode mode;
5862 unsigned HOST_WIDE_INT len;
5864 int in_dest, in_compare;
5866 /* This mode describes the size of the storage area
5867 to fetch the overall value from. Within that, we
5868 ignore the POS lowest bits, etc. */
5869 enum machine_mode is_mode = GET_MODE (inner);
5870 enum machine_mode inner_mode;
5871 enum machine_mode wanted_inner_mode = byte_mode;
5872 enum machine_mode wanted_inner_reg_mode = word_mode;
5873 enum machine_mode pos_mode = word_mode;
5874 enum machine_mode extraction_mode = word_mode;
5875 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5878 rtx orig_pos_rtx = pos_rtx;
5879 HOST_WIDE_INT orig_pos;
5881 /* Get some information about INNER and get the innermost object. */
5882 if (GET_CODE (inner) == USE)
5883 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5884 /* We don't need to adjust the position because we set up the USE
5885 to pretend that it was a full-word object. */
5886 spans_byte = 1, inner = XEXP (inner, 0);
5887 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5889 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5890 consider just the QI as the memory to extract from.
5891 The subreg adds or removes high bits; its mode is
5892 irrelevant to the meaning of this extraction,
5893 since POS and LEN count from the lsb. */
5894 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5895 is_mode = GET_MODE (SUBREG_REG (inner));
5896 inner = SUBREG_REG (inner);
5899 inner_mode = GET_MODE (inner);
5901 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5902 pos = INTVAL (pos_rtx), pos_rtx = 0;
5904 /* See if this can be done without an extraction. We never can if the
5905 width of the field is not the same as that of some integer mode. For
5906 registers, we can only avoid the extraction if the position is at the
5907 low-order bit and this is either not in the destination or we have the
5908 appropriate STRICT_LOW_PART operation available.
5910 For MEM, we can avoid an extract if the field starts on an appropriate
5911 boundary and we can change the mode of the memory reference. However,
5912 we cannot directly access the MEM if we have a USE and the underlying
5913 MEM is not TMODE. This combination means that MEM was being used in a
5914 context where bits outside its mode were being referenced; that is only
5915 valid in bit-field insns. */
5917 if (tmode != BLKmode
5918 && ! (spans_byte && inner_mode != tmode)
5919 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5920 && GET_CODE (inner) != MEM
5922 || (GET_CODE (inner) == REG
5923 && (movstrict_optab->handlers[(int) tmode].insn_code
5924 != CODE_FOR_nothing))))
5925 || (GET_CODE (inner) == MEM && pos_rtx == 0
5927 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5928 : BITS_PER_UNIT)) == 0
5929 /* We can't do this if we are widening INNER_MODE (it
5930 may not be aligned, for one thing). */
5931 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5932 && (inner_mode == tmode
5933 || (! mode_dependent_address_p (XEXP (inner, 0))
5934 && ! MEM_VOLATILE_P (inner))))))
5936 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5937 field. If the original and current mode are the same, we need not
5938 adjust the offset. Otherwise, we do if bytes big endian.
5940 If INNER is not a MEM, get a piece consisting of just the field
5941 of interest (in this case POS % BITS_PER_WORD must be 0). */
5943 if (GET_CODE (inner) == MEM)
5946 /* POS counts from lsb, but make OFFSET count in memory order. */
5947 if (BYTES_BIG_ENDIAN)
5948 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5950 offset = pos / BITS_PER_UNIT;
5952 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5953 MEM_COPY_ATTRIBUTES (new, inner);
5955 else if (GET_CODE (inner) == REG)
5957 /* We can't call gen_lowpart_for_combine here since we always want
5958 a SUBREG and it would sometimes return a new hard register. */
5959 if (tmode != inner_mode)
5960 new = gen_rtx_SUBREG (tmode, inner,
5962 && (GET_MODE_SIZE (inner_mode)
5964 ? (((GET_MODE_SIZE (inner_mode)
5965 - GET_MODE_SIZE (tmode))
5967 - pos / BITS_PER_WORD)
5968 : pos / BITS_PER_WORD));
5973 new = force_to_mode (inner, tmode,
5974 len >= HOST_BITS_PER_WIDE_INT
5975 ? GET_MODE_MASK (tmode)
5976 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5979 /* If this extraction is going into the destination of a SET,
5980 make a STRICT_LOW_PART unless we made a MEM. */
5983 return (GET_CODE (new) == MEM ? new
5984 : (GET_CODE (new) != SUBREG
5985 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5986 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5991 /* If we know that no extraneous bits are set, and that the high
5992 bit is not set, convert the extraction to the cheaper of
5993 sign and zero extension, that are equivalent in these cases. */
5994 if (flag_expensive_optimizations
5995 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5996 && ((nonzero_bits (new, tmode)
5997 & ~ (((unsigned HOST_WIDE_INT)
5998 GET_MODE_MASK (tmode))
6002 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6003 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6005 /* Prefer ZERO_EXTENSION, since it gives more information to
6007 if (rtx_cost (temp, SET) < rtx_cost (temp1, SET))
6012 /* Otherwise, sign- or zero-extend unless we already are in the
6015 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6019 /* Unless this is a COMPARE or we have a funny memory reference,
6020 don't do anything with zero-extending field extracts starting at
6021 the low-order bit since they are simple AND operations. */
6022 if (pos_rtx == 0 && pos == 0 && ! in_dest
6023 && ! in_compare && ! spans_byte && unsignedp)
6026 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6027 we would be spanning bytes or if the position is not a constant and the
6028 length is not 1. In all other cases, we would only be going outside
6029 our object in cases when an original shift would have been
6031 if (! spans_byte && GET_CODE (inner) == MEM
6032 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6033 || (pos_rtx != 0 && len != 1)))
6036 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6037 and the mode for the result. */
6041 wanted_inner_reg_mode
6042 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6043 if (wanted_inner_reg_mode == VOIDmode)
6044 wanted_inner_reg_mode = word_mode;
6046 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6047 if (pos_mode == VOIDmode)
6048 pos_mode = word_mode;
6050 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6051 if (extraction_mode == VOIDmode)
6052 extraction_mode = word_mode;
6057 if (! in_dest && unsignedp)
6059 wanted_inner_reg_mode
6060 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6061 if (wanted_inner_reg_mode == VOIDmode)
6062 wanted_inner_reg_mode = word_mode;
6064 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6065 if (pos_mode == VOIDmode)
6066 pos_mode = word_mode;
6068 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6069 if (extraction_mode == VOIDmode)
6070 extraction_mode = word_mode;
6075 if (! in_dest && ! unsignedp)
6077 wanted_inner_reg_mode
6078 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6079 if (wanted_inner_reg_mode == VOIDmode)
6080 wanted_inner_reg_mode = word_mode;
6082 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6083 if (pos_mode == VOIDmode)
6084 pos_mode = word_mode;
6086 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6087 if (extraction_mode == VOIDmode)
6088 extraction_mode = word_mode;
6092 /* Never narrow an object, since that might not be safe. */
6094 if (mode != VOIDmode
6095 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6096 extraction_mode = mode;
6098 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6099 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6100 pos_mode = GET_MODE (pos_rtx);
6102 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6103 if we have to change the mode of memory and cannot, the desired mode is
6105 if (GET_CODE (inner) != MEM)
6106 wanted_inner_mode = wanted_inner_reg_mode;
6107 else if (inner_mode != wanted_inner_mode
6108 && (mode_dependent_address_p (XEXP (inner, 0))
6109 || MEM_VOLATILE_P (inner)))
6110 wanted_inner_mode = extraction_mode;
6114 if (BITS_BIG_ENDIAN)
6116 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6117 BITS_BIG_ENDIAN style. If position is constant, compute new
6118 position. Otherwise, build subtraction.
6119 Note that POS is relative to the mode of the original argument.
6120 If it's a MEM we need to recompute POS relative to that.
6121 However, if we're extracting from (or inserting into) a register,
6122 we want to recompute POS relative to wanted_inner_mode. */
6123 int width = (GET_CODE (inner) == MEM
6124 ? GET_MODE_BITSIZE (is_mode)
6125 : GET_MODE_BITSIZE (wanted_inner_mode));
6128 pos = width - len - pos;
6131 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6132 GEN_INT (width - len), pos_rtx);
6133 /* POS may be less than 0 now, but we check for that below.
6134 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6137 /* If INNER has a wider mode, make it smaller. If this is a constant
6138 extract, try to adjust the byte to point to the byte containing
6140 if (wanted_inner_mode != VOIDmode
6141 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6142 && ((GET_CODE (inner) == MEM
6143 && (inner_mode == wanted_inner_mode
6144 || (! mode_dependent_address_p (XEXP (inner, 0))
6145 && ! MEM_VOLATILE_P (inner))))))
6149 /* The computations below will be correct if the machine is big
6150 endian in both bits and bytes or little endian in bits and bytes.
6151 If it is mixed, we must adjust. */
6153 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6154 adjust OFFSET to compensate. */
6155 if (BYTES_BIG_ENDIAN
6157 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6158 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6160 /* If this is a constant position, we can move to the desired byte. */
6163 offset += pos / BITS_PER_UNIT;
6164 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6167 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6169 && is_mode != wanted_inner_mode)
6170 offset = (GET_MODE_SIZE (is_mode)
6171 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6173 if (offset != 0 || inner_mode != wanted_inner_mode)
6175 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6176 plus_constant (XEXP (inner, 0), offset));
6178 MEM_COPY_ATTRIBUTES (newmem, inner);
6183 /* If INNER is not memory, we can always get it into the proper mode. If we
6184 are changing its mode, POS must be a constant and smaller than the size
6186 else if (GET_CODE (inner) != MEM)
6188 if (GET_MODE (inner) != wanted_inner_mode
6190 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6193 inner = force_to_mode (inner, wanted_inner_mode,
6195 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6196 ? GET_MODE_MASK (wanted_inner_mode)
6197 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6202 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6203 have to zero extend. Otherwise, we can just use a SUBREG. */
6205 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6207 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6209 /* If we know that no extraneous bits are set, and that the high
6210 bit is not set, convert extraction to cheaper one - eighter
6211 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6213 if (flag_expensive_optimizations
6214 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6215 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6216 & ~ (((unsigned HOST_WIDE_INT)
6217 GET_MODE_MASK (GET_MODE (pos_rtx)))
6221 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6223 /* Preffer ZERO_EXTENSION, since it gives more information to
6225 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6230 else if (pos_rtx != 0
6231 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6232 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6234 /* Make POS_RTX unless we already have it and it is correct. If we don't
6235 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6237 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6238 pos_rtx = orig_pos_rtx;
6240 else if (pos_rtx == 0)
6241 pos_rtx = GEN_INT (pos);
6243 /* Make the required operation. See if we can use existing rtx. */
6244 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6245 extraction_mode, inner, GEN_INT (len), pos_rtx);
6247 new = gen_lowpart_for_combine (mode, new);
6252 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6253 with any other operations in X. Return X without that shift if so. */
6256 extract_left_shift (x, count)
6260 enum rtx_code code = GET_CODE (x);
6261 enum machine_mode mode = GET_MODE (x);
6267 /* This is the shift itself. If it is wide enough, we will return
6268 either the value being shifted if the shift count is equal to
6269 COUNT or a shift for the difference. */
6270 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6271 && INTVAL (XEXP (x, 1)) >= count)
6272 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6273 INTVAL (XEXP (x, 1)) - count);
6277 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6278 return gen_unary (code, mode, mode, tem);
6282 case PLUS: case IOR: case XOR: case AND:
6283 /* If we can safely shift this constant and we find the inner shift,
6284 make a new operation. */
6285 if (GET_CODE (XEXP (x,1)) == CONST_INT
6286 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6287 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6288 return gen_binary (code, mode, tem,
6289 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6300 /* Look at the expression rooted at X. Look for expressions
6301 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6302 Form these expressions.
6304 Return the new rtx, usually just X.
6306 Also, for machines like the Vax that don't have logical shift insns,
6307 try to convert logical to arithmetic shift operations in cases where
6308 they are equivalent. This undoes the canonicalizations to logical
6309 shifts done elsewhere.
6311 We try, as much as possible, to re-use rtl expressions to save memory.
6313 IN_CODE says what kind of expression we are processing. Normally, it is
6314 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6315 being kludges), it is MEM. When processing the arguments of a comparison
6316 or a COMPARE against zero, it is COMPARE. */
6319 make_compound_operation (x, in_code)
6321 enum rtx_code in_code;
6323 enum rtx_code code = GET_CODE (x);
6324 enum machine_mode mode = GET_MODE (x);
6325 int mode_width = GET_MODE_BITSIZE (mode);
6327 enum rtx_code next_code;
6333 /* Select the code to be used in recursive calls. Once we are inside an
6334 address, we stay there. If we have a comparison, set to COMPARE,
6335 but once inside, go back to our default of SET. */
6337 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6338 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6339 && XEXP (x, 1) == const0_rtx) ? COMPARE
6340 : in_code == COMPARE ? SET : in_code);
6342 /* Process depending on the code of this operation. If NEW is set
6343 non-zero, it will be returned. */
6348 /* Convert shifts by constants into multiplications if inside
6350 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6351 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6352 && INTVAL (XEXP (x, 1)) >= 0)
6354 new = make_compound_operation (XEXP (x, 0), next_code);
6355 new = gen_rtx_combine (MULT, mode, new,
6356 GEN_INT ((HOST_WIDE_INT) 1
6357 << INTVAL (XEXP (x, 1))));
6362 /* If the second operand is not a constant, we can't do anything
6364 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6367 /* If the constant is a power of two minus one and the first operand
6368 is a logical right shift, make an extraction. */
6369 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6370 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6372 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6373 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6374 0, in_code == COMPARE);
6377 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6378 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6379 && subreg_lowpart_p (XEXP (x, 0))
6380 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6381 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6383 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6385 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6386 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6387 0, in_code == COMPARE);
6389 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6390 else if ((GET_CODE (XEXP (x, 0)) == XOR
6391 || GET_CODE (XEXP (x, 0)) == IOR)
6392 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6393 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6394 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6396 /* Apply the distributive law, and then try to make extractions. */
6397 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6398 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6400 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6402 new = make_compound_operation (new, in_code);
6405 /* If we are have (and (rotate X C) M) and C is larger than the number
6406 of bits in M, this is an extraction. */
6408 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6409 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6410 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6411 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6413 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6414 new = make_extraction (mode, new,
6415 (GET_MODE_BITSIZE (mode)
6416 - INTVAL (XEXP (XEXP (x, 0), 1))),
6417 NULL_RTX, i, 1, 0, in_code == COMPARE);
6420 /* On machines without logical shifts, if the operand of the AND is
6421 a logical shift and our mask turns off all the propagated sign
6422 bits, we can replace the logical shift with an arithmetic shift. */
6423 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6424 && (lshr_optab->handlers[(int) mode].insn_code
6425 == CODE_FOR_nothing)
6426 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6427 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6428 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6429 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6430 && mode_width <= HOST_BITS_PER_WIDE_INT)
6432 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6434 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6435 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6437 gen_rtx_combine (ASHIFTRT, mode,
6438 make_compound_operation (XEXP (XEXP (x, 0), 0),
6440 XEXP (XEXP (x, 0), 1)));
6443 /* If the constant is one less than a power of two, this might be
6444 representable by an extraction even if no shift is present.
6445 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6446 we are in a COMPARE. */
6447 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6448 new = make_extraction (mode,
6449 make_compound_operation (XEXP (x, 0),
6451 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6453 /* If we are in a comparison and this is an AND with a power of two,
6454 convert this into the appropriate bit extract. */
6455 else if (in_code == COMPARE
6456 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6457 new = make_extraction (mode,
6458 make_compound_operation (XEXP (x, 0),
6460 i, NULL_RTX, 1, 1, 0, 1);
6465 /* If the sign bit is known to be zero, replace this with an
6466 arithmetic shift. */
6467 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6468 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6469 && mode_width <= HOST_BITS_PER_WIDE_INT
6470 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6472 new = gen_rtx_combine (ASHIFTRT, mode,
6473 make_compound_operation (XEXP (x, 0),
6479 /* ... fall through ... */
6485 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6486 this is a SIGN_EXTRACT. */
6487 if (GET_CODE (rhs) == CONST_INT
6488 && GET_CODE (lhs) == ASHIFT
6489 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6490 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6492 new = make_compound_operation (XEXP (lhs, 0), next_code);
6493 new = make_extraction (mode, new,
6494 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6495 NULL_RTX, mode_width - INTVAL (rhs),
6496 code == LSHIFTRT, 0, in_code == COMPARE);
6499 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6500 If so, try to merge the shifts into a SIGN_EXTEND. We could
6501 also do this for some cases of SIGN_EXTRACT, but it doesn't
6502 seem worth the effort; the case checked for occurs on Alpha. */
6504 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6505 && ! (GET_CODE (lhs) == SUBREG
6506 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6507 && GET_CODE (rhs) == CONST_INT
6508 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6509 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6510 new = make_extraction (mode, make_compound_operation (new, next_code),
6511 0, NULL_RTX, mode_width - INTVAL (rhs),
6512 code == LSHIFTRT, 0, in_code == COMPARE);
6517 /* Call ourselves recursively on the inner expression. If we are
6518 narrowing the object and it has a different RTL code from
6519 what it originally did, do this SUBREG as a force_to_mode. */
6521 tem = make_compound_operation (SUBREG_REG (x), in_code);
6522 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6523 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6524 && subreg_lowpart_p (x))
6526 rtx newer = force_to_mode (tem, mode,
6527 GET_MODE_MASK (mode), NULL_RTX, 0);
6529 /* If we have something other than a SUBREG, we might have
6530 done an expansion, so rerun outselves. */
6531 if (GET_CODE (newer) != SUBREG)
6532 newer = make_compound_operation (newer, in_code);
6537 /* If this is a paradoxical subreg, and the new code is a sign or
6538 zero extension, omit the subreg and widen the extension. If it
6539 is a regular subreg, we can still get rid of the subreg by not
6540 widening so much, or in fact removing the extension entirely. */
6541 if ((GET_CODE (tem) == SIGN_EXTEND
6542 || GET_CODE (tem) == ZERO_EXTEND)
6543 && subreg_lowpart_p (x))
6545 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6546 || (GET_MODE_SIZE (mode) >
6547 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6548 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6550 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6561 x = gen_lowpart_for_combine (mode, new);
6562 code = GET_CODE (x);
6565 /* Now recursively process each operand of this operation. */
6566 fmt = GET_RTX_FORMAT (code);
6567 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6570 new = make_compound_operation (XEXP (x, i), next_code);
6571 SUBST (XEXP (x, i), new);
6577 /* Given M see if it is a value that would select a field of bits
6578 within an item, but not the entire word. Return -1 if not.
6579 Otherwise, return the starting position of the field, where 0 is the
6582 *PLEN is set to the length of the field. */
6585 get_pos_from_mask (m, plen)
6586 unsigned HOST_WIDE_INT m;
6587 unsigned HOST_WIDE_INT *plen;
6589 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6590 int pos = exact_log2 (m & - m);
6596 /* Now shift off the low-order zero bits and see if we have a power of
6598 len = exact_log2 ((m >> pos) + 1);
6607 /* See if X can be simplified knowing that we will only refer to it in
6608 MODE and will only refer to those bits that are nonzero in MASK.
6609 If other bits are being computed or if masking operations are done
6610 that select a superset of the bits in MASK, they can sometimes be
6613 Return a possibly simplified expression, but always convert X to
6614 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6616 Also, if REG is non-zero and X is a register equal in value to REG,
6619 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6620 are all off in X. This is used when X will be complemented, by either
6621 NOT, NEG, or XOR. */
6624 force_to_mode (x, mode, mask, reg, just_select)
6626 enum machine_mode mode;
6627 unsigned HOST_WIDE_INT mask;
6631 enum rtx_code code = GET_CODE (x);
6632 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6633 enum machine_mode op_mode;
6634 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6637 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6638 code below will do the wrong thing since the mode of such an
6639 expression is VOIDmode.
6641 Also do nothing if X is a CLOBBER; this can happen if X was
6642 the return value from a call to gen_lowpart_for_combine. */
6643 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6646 /* We want to perform the operation is its present mode unless we know
6647 that the operation is valid in MODE, in which case we do the operation
6649 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6650 && code_to_optab[(int) code] != 0
6651 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6652 != CODE_FOR_nothing))
6653 ? mode : GET_MODE (x));
6655 /* It is not valid to do a right-shift in a narrower mode
6656 than the one it came in with. */
6657 if ((code == LSHIFTRT || code == ASHIFTRT)
6658 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6659 op_mode = GET_MODE (x);
6661 /* Truncate MASK to fit OP_MODE. */
6663 mask &= GET_MODE_MASK (op_mode);
6665 /* When we have an arithmetic operation, or a shift whose count we
6666 do not know, we need to assume that all bit the up to the highest-order
6667 bit in MASK will be needed. This is how we form such a mask. */
6669 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6670 ? GET_MODE_MASK (op_mode)
6671 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6674 fuller_mask = ~ (HOST_WIDE_INT) 0;
6676 /* Determine what bits of X are guaranteed to be (non)zero. */
6677 nonzero = nonzero_bits (x, mode);
6679 /* If none of the bits in X are needed, return a zero. */
6680 if (! just_select && (nonzero & mask) == 0)
6683 /* If X is a CONST_INT, return a new one. Do this here since the
6684 test below will fail. */
6685 if (GET_CODE (x) == CONST_INT)
6687 HOST_WIDE_INT cval = INTVAL (x) & mask;
6688 int width = GET_MODE_BITSIZE (mode);
6690 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6691 number, sign extend it. */
6692 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6693 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6694 cval |= (HOST_WIDE_INT) -1 << width;
6696 return GEN_INT (cval);
6699 /* If X is narrower than MODE and we want all the bits in X's mode, just
6700 get X in the proper mode. */
6701 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6702 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6703 return gen_lowpart_for_combine (mode, x);
6705 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6706 MASK are already known to be zero in X, we need not do anything. */
6707 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6713 /* If X is a (clobber (const_int)), return it since we know we are
6714 generating something that won't match. */
6718 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6719 spanned the boundary of the MEM. If we are now masking so it is
6720 within that boundary, we don't need the USE any more. */
6721 if (! BITS_BIG_ENDIAN
6722 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6723 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6730 x = expand_compound_operation (x);
6731 if (GET_CODE (x) != code)
6732 return force_to_mode (x, mode, mask, reg, next_select);
6736 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6737 || rtx_equal_p (reg, get_last_value (x))))
6742 if (subreg_lowpart_p (x)
6743 /* We can ignore the effect of this SUBREG if it narrows the mode or
6744 if the constant masks to zero all the bits the mode doesn't
6746 && ((GET_MODE_SIZE (GET_MODE (x))
6747 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6749 & GET_MODE_MASK (GET_MODE (x))
6750 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6751 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6755 /* If this is an AND with a constant, convert it into an AND
6756 whose constant is the AND of that constant with MASK. If it
6757 remains an AND of MASK, delete it since it is redundant. */
6759 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6761 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6762 mask & INTVAL (XEXP (x, 1)));
6764 /* If X is still an AND, see if it is an AND with a mask that
6765 is just some low-order bits. If so, and it is MASK, we don't
6768 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6769 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6772 /* If it remains an AND, try making another AND with the bits
6773 in the mode mask that aren't in MASK turned on. If the
6774 constant in the AND is wide enough, this might make a
6775 cheaper constant. */
6777 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6778 && GET_MODE_MASK (GET_MODE (x)) != mask
6779 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6781 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6782 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6783 int width = GET_MODE_BITSIZE (GET_MODE (x));
6786 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6787 number, sign extend it. */
6788 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6789 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6790 cval |= (HOST_WIDE_INT) -1 << width;
6792 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6793 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6803 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6804 low-order bits (as in an alignment operation) and FOO is already
6805 aligned to that boundary, mask C1 to that boundary as well.
6806 This may eliminate that PLUS and, later, the AND. */
6809 unsigned int width = GET_MODE_BITSIZE (mode);
6810 unsigned HOST_WIDE_INT smask = mask;
6812 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6813 number, sign extend it. */
6815 if (width < HOST_BITS_PER_WIDE_INT
6816 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6817 smask |= (HOST_WIDE_INT) -1 << width;
6819 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6820 && exact_log2 (- smask) >= 0)
6824 && (XEXP (x, 0) == stack_pointer_rtx
6825 || XEXP (x, 0) == frame_pointer_rtx))
6827 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6828 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6830 sp_mask &= ~ (sp_alignment - 1);
6831 if ((sp_mask & ~ smask) == 0
6832 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6833 return force_to_mode (plus_constant (XEXP (x, 0),
6834 ((INTVAL (XEXP (x, 1)) -
6835 STACK_BIAS) & smask)
6837 mode, smask, reg, next_select);
6840 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6841 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6842 return force_to_mode (plus_constant (XEXP (x, 0),
6843 (INTVAL (XEXP (x, 1))
6845 mode, smask, reg, next_select);
6849 /* ... fall through ... */
6852 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6853 most significant bit in MASK since carries from those bits will
6854 affect the bits we are interested in. */
6859 /* If X is (minus C Y) where C's least set bit is larger than any bit
6860 in the mask, then we may replace with (neg Y). */
6861 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6862 && (INTVAL (XEXP (x, 0)) & -INTVAL (XEXP (x, 0))) > mask)
6864 x = gen_unary (NEG, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6865 return force_to_mode (x, mode, mask, reg, next_select);
6868 /* Similarly, if C contains every bit in the mask, then we may
6869 replace with (not Y). */
6870 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6871 && (INTVAL (XEXP (x, 0)) | mask) == INTVAL (XEXP (x, 0)))
6873 x = gen_unary (NOT, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6874 return force_to_mode (x, mode, mask, reg, next_select);
6882 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6883 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6884 operation which may be a bitfield extraction. Ensure that the
6885 constant we form is not wider than the mode of X. */
6887 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6888 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6889 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6890 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6891 && GET_CODE (XEXP (x, 1)) == CONST_INT
6892 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6893 + floor_log2 (INTVAL (XEXP (x, 1))))
6894 < GET_MODE_BITSIZE (GET_MODE (x)))
6895 && (INTVAL (XEXP (x, 1))
6896 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6898 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6899 << INTVAL (XEXP (XEXP (x, 0), 1)));
6900 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6901 XEXP (XEXP (x, 0), 0), temp);
6902 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6903 XEXP (XEXP (x, 0), 1));
6904 return force_to_mode (x, mode, mask, reg, next_select);
6908 /* For most binary operations, just propagate into the operation and
6909 change the mode if we have an operation of that mode. */
6911 op0 = gen_lowpart_for_combine (op_mode,
6912 force_to_mode (XEXP (x, 0), mode, mask,
6914 op1 = gen_lowpart_for_combine (op_mode,
6915 force_to_mode (XEXP (x, 1), mode, mask,
6918 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6919 MASK since OP1 might have been sign-extended but we never want
6920 to turn on extra bits, since combine might have previously relied
6921 on them being off. */
6922 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6923 && (INTVAL (op1) & mask) != 0)
6924 op1 = GEN_INT (INTVAL (op1) & mask);
6926 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6927 x = gen_binary (code, op_mode, op0, op1);
6931 /* For left shifts, do the same, but just for the first operand.
6932 However, we cannot do anything with shifts where we cannot
6933 guarantee that the counts are smaller than the size of the mode
6934 because such a count will have a different meaning in a
6937 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6938 && INTVAL (XEXP (x, 1)) >= 0
6939 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6940 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6941 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6942 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6945 /* If the shift count is a constant and we can do arithmetic in
6946 the mode of the shift, refine which bits we need. Otherwise, use the
6947 conservative form of the mask. */
6948 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6949 && INTVAL (XEXP (x, 1)) >= 0
6950 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6951 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6952 mask >>= INTVAL (XEXP (x, 1));
6956 op0 = gen_lowpart_for_combine (op_mode,
6957 force_to_mode (XEXP (x, 0), op_mode,
6958 mask, reg, next_select));
6960 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6961 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6965 /* Here we can only do something if the shift count is a constant,
6966 this shift constant is valid for the host, and we can do arithmetic
6969 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6970 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6971 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6973 rtx inner = XEXP (x, 0);
6974 unsigned HOST_WIDE_INT inner_mask;
6976 /* Select the mask of the bits we need for the shift operand. */
6977 inner_mask = mask << INTVAL (XEXP (x, 1));
6979 /* We can only change the mode of the shift if we can do arithmetic
6980 in the mode of the shift and INNER_MASK is no wider than the
6981 width of OP_MODE. */
6982 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6983 || (inner_mask & ~ GET_MODE_MASK (op_mode)) != 0)
6984 op_mode = GET_MODE (x);
6986 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6988 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6989 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6992 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6993 shift and AND produces only copies of the sign bit (C2 is one less
6994 than a power of two), we can do this with just a shift. */
6996 if (GET_CODE (x) == LSHIFTRT
6997 && GET_CODE (XEXP (x, 1)) == CONST_INT
6998 /* The shift puts one of the sign bit copies in the least significant
7000 && ((INTVAL (XEXP (x, 1))
7001 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7002 >= GET_MODE_BITSIZE (GET_MODE (x)))
7003 && exact_log2 (mask + 1) >= 0
7004 /* Number of bits left after the shift must be more than the mask
7006 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7007 <= GET_MODE_BITSIZE (GET_MODE (x)))
7008 /* Must be more sign bit copies than the mask needs. */
7009 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7010 >= exact_log2 (mask + 1)))
7011 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7012 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7013 - exact_log2 (mask + 1)));
7018 /* If we are just looking for the sign bit, we don't need this shift at
7019 all, even if it has a variable count. */
7020 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7021 && (mask == ((unsigned HOST_WIDE_INT) 1
7022 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7023 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7025 /* If this is a shift by a constant, get a mask that contains those bits
7026 that are not copies of the sign bit. We then have two cases: If
7027 MASK only includes those bits, this can be a logical shift, which may
7028 allow simplifications. If MASK is a single-bit field not within
7029 those bits, we are requesting a copy of the sign bit and hence can
7030 shift the sign bit to the appropriate location. */
7032 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7033 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7037 /* If the considered data is wider then HOST_WIDE_INT, we can't
7038 represent a mask for all its bits in a single scalar.
7039 But we only care about the lower bits, so calculate these. */
7041 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7043 nonzero = ~ (HOST_WIDE_INT) 0;
7045 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7046 is the number of bits a full-width mask would have set.
7047 We need only shift if these are fewer than nonzero can
7048 hold. If not, we must keep all bits set in nonzero. */
7050 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7051 < HOST_BITS_PER_WIDE_INT)
7052 nonzero >>= INTVAL (XEXP (x, 1))
7053 + HOST_BITS_PER_WIDE_INT
7054 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7058 nonzero = GET_MODE_MASK (GET_MODE (x));
7059 nonzero >>= INTVAL (XEXP (x, 1));
7062 if ((mask & ~ nonzero) == 0
7063 || (i = exact_log2 (mask)) >= 0)
7065 x = simplify_shift_const
7066 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7067 i < 0 ? INTVAL (XEXP (x, 1))
7068 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7070 if (GET_CODE (x) != ASHIFTRT)
7071 return force_to_mode (x, mode, mask, reg, next_select);
7075 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7076 even if the shift count isn't a constant. */
7078 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7082 /* If this is a zero- or sign-extension operation that just affects bits
7083 we don't care about, remove it. Be sure the call above returned
7084 something that is still a shift. */
7086 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7087 && GET_CODE (XEXP (x, 1)) == CONST_INT
7088 && INTVAL (XEXP (x, 1)) >= 0
7089 && (INTVAL (XEXP (x, 1))
7090 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7091 && GET_CODE (XEXP (x, 0)) == ASHIFT
7092 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7093 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7094 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7101 /* If the shift count is constant and we can do computations
7102 in the mode of X, compute where the bits we care about are.
7103 Otherwise, we can't do anything. Don't change the mode of
7104 the shift or propagate MODE into the shift, though. */
7105 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7106 && INTVAL (XEXP (x, 1)) >= 0)
7108 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7109 GET_MODE (x), GEN_INT (mask),
7111 if (temp && GET_CODE(temp) == CONST_INT)
7113 force_to_mode (XEXP (x, 0), GET_MODE (x),
7114 INTVAL (temp), reg, next_select));
7119 /* If we just want the low-order bit, the NEG isn't needed since it
7120 won't change the low-order bit. */
7122 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7124 /* We need any bits less significant than the most significant bit in
7125 MASK since carries from those bits will affect the bits we are
7131 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7132 same as the XOR case above. Ensure that the constant we form is not
7133 wider than the mode of X. */
7135 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7136 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7137 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7138 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7139 < GET_MODE_BITSIZE (GET_MODE (x)))
7140 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7142 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7143 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7144 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7146 return force_to_mode (x, mode, mask, reg, next_select);
7149 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7150 use the full mask inside the NOT. */
7154 op0 = gen_lowpart_for_combine (op_mode,
7155 force_to_mode (XEXP (x, 0), mode, mask,
7157 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7158 x = gen_unary (code, op_mode, op_mode, op0);
7162 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7163 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7164 which is equal to STORE_FLAG_VALUE. */
7165 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7166 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7167 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7168 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7173 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7174 written in a narrower mode. We play it safe and do not do so. */
7177 gen_lowpart_for_combine (GET_MODE (x),
7178 force_to_mode (XEXP (x, 1), mode,
7179 mask, reg, next_select)));
7181 gen_lowpart_for_combine (GET_MODE (x),
7182 force_to_mode (XEXP (x, 2), mode,
7183 mask, reg,next_select)));
7190 /* Ensure we return a value of the proper mode. */
7191 return gen_lowpart_for_combine (mode, x);
7194 /* Return nonzero if X is an expression that has one of two values depending on
7195 whether some other value is zero or nonzero. In that case, we return the
7196 value that is being tested, *PTRUE is set to the value if the rtx being
7197 returned has a nonzero value, and *PFALSE is set to the other alternative.
7199 If we return zero, we set *PTRUE and *PFALSE to X. */
7202 if_then_else_cond (x, ptrue, pfalse)
7204 rtx *ptrue, *pfalse;
7206 enum machine_mode mode = GET_MODE (x);
7207 enum rtx_code code = GET_CODE (x);
7208 unsigned int size = GET_MODE_BITSIZE (mode);
7209 rtx cond0, cond1, true0, true1, false0, false1;
7210 unsigned HOST_WIDE_INT nz;
7212 /* If we are comparing a value against zero, we are done. */
7213 if ((code == NE || code == EQ)
7214 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7216 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7217 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7221 /* If this is a unary operation whose operand has one of two values, apply
7222 our opcode to compute those values. */
7223 else if (GET_RTX_CLASS (code) == '1'
7224 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7226 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7227 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7231 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7232 make can't possibly match and would suppress other optimizations. */
7233 else if (code == COMPARE)
7236 /* If this is a binary operation, see if either side has only one of two
7237 values. If either one does or if both do and they are conditional on
7238 the same value, compute the new true and false values. */
7239 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7240 || GET_RTX_CLASS (code) == '<')
7242 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7243 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7245 if ((cond0 != 0 || cond1 != 0)
7246 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7248 /* If if_then_else_cond returned zero, then true/false are the
7249 same rtl. We must copy one of them to prevent invalid rtl
7252 true0 = copy_rtx (true0);
7253 else if (cond1 == 0)
7254 true1 = copy_rtx (true1);
7256 *ptrue = gen_binary (code, mode, true0, true1);
7257 *pfalse = gen_binary (code, mode, false0, false1);
7258 return cond0 ? cond0 : cond1;
7261 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7262 operands is zero when the other is non-zero, and vice-versa,
7263 and STORE_FLAG_VALUE is 1 or -1. */
7265 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7266 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7268 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7270 rtx op0 = XEXP (XEXP (x, 0), 1);
7271 rtx op1 = XEXP (XEXP (x, 1), 1);
7273 cond0 = XEXP (XEXP (x, 0), 0);
7274 cond1 = XEXP (XEXP (x, 1), 0);
7276 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7277 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7278 && reversible_comparison_p (cond1)
7279 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7280 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7281 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7282 || ((swap_condition (GET_CODE (cond0))
7283 == reverse_condition (GET_CODE (cond1)))
7284 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7285 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7286 && ! side_effects_p (x))
7288 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7289 *pfalse = gen_binary (MULT, mode,
7291 ? gen_unary (NEG, mode, mode, op1) : op1),
7297 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7299 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7300 && (code == MULT || code == AND || code == UMIN)
7301 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7303 cond0 = XEXP (XEXP (x, 0), 0);
7304 cond1 = XEXP (XEXP (x, 1), 0);
7306 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7307 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7308 && reversible_comparison_p (cond1)
7309 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7310 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7311 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7312 || ((swap_condition (GET_CODE (cond0))
7313 == reverse_condition (GET_CODE (cond1)))
7314 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7315 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7316 && ! side_effects_p (x))
7318 *ptrue = *pfalse = const0_rtx;
7324 else if (code == IF_THEN_ELSE)
7326 /* If we have IF_THEN_ELSE already, extract the condition and
7327 canonicalize it if it is NE or EQ. */
7328 cond0 = XEXP (x, 0);
7329 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7330 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7331 return XEXP (cond0, 0);
7332 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7334 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7335 return XEXP (cond0, 0);
7341 /* If X is a normal SUBREG with both inner and outer modes integral,
7342 we can narrow both the true and false values of the inner expression,
7343 if there is a condition. */
7344 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7345 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7346 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7347 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7350 if ((GET_CODE (SUBREG_REG (x)) == REG
7351 || GET_CODE (SUBREG_REG (x)) == MEM
7352 || CONSTANT_P (SUBREG_REG (x)))
7353 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7354 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7356 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7357 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7359 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7361 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7366 /* If X is a constant, this isn't special and will cause confusions
7367 if we treat it as such. Likewise if it is equivalent to a constant. */
7368 else if (CONSTANT_P (x)
7369 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7372 /* If X is known to be either 0 or -1, those are the true and
7373 false values when testing X. */
7374 else if (num_sign_bit_copies (x, mode) == size)
7376 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7380 /* Likewise for 0 or a single bit. */
7381 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7383 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7387 /* Otherwise fail; show no condition with true and false values the same. */
7388 *ptrue = *pfalse = x;
7392 /* Return the value of expression X given the fact that condition COND
7393 is known to be true when applied to REG as its first operand and VAL
7394 as its second. X is known to not be shared and so can be modified in
7397 We only handle the simplest cases, and specifically those cases that
7398 arise with IF_THEN_ELSE expressions. */
7401 known_cond (x, cond, reg, val)
7406 enum rtx_code code = GET_CODE (x);
7411 if (side_effects_p (x))
7414 if (cond == EQ && rtx_equal_p (x, reg))
7417 /* If X is (abs REG) and we know something about REG's relationship
7418 with zero, we may be able to simplify this. */
7420 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7423 case GE: case GT: case EQ:
7426 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7432 /* The only other cases we handle are MIN, MAX, and comparisons if the
7433 operands are the same as REG and VAL. */
7435 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7437 if (rtx_equal_p (XEXP (x, 0), val))
7438 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7440 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7442 if (GET_RTX_CLASS (code) == '<')
7444 if (comparison_dominates_p (cond, code))
7445 return const_true_rtx;
7447 code = reverse_condition (code);
7449 && comparison_dominates_p (cond, code))
7454 else if (code == SMAX || code == SMIN
7455 || code == UMIN || code == UMAX)
7457 int unsignedp = (code == UMIN || code == UMAX);
7459 if (code == SMAX || code == UMAX)
7460 cond = reverse_condition (cond);
7465 return unsignedp ? x : XEXP (x, 1);
7467 return unsignedp ? x : XEXP (x, 0);
7469 return unsignedp ? XEXP (x, 1) : x;
7471 return unsignedp ? XEXP (x, 0) : x;
7479 fmt = GET_RTX_FORMAT (code);
7480 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7483 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7484 else if (fmt[i] == 'E')
7485 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7486 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7493 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7494 assignment as a field assignment. */
7497 rtx_equal_for_field_assignment_p (x, y)
7501 if (x == y || rtx_equal_p (x, y))
7504 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7507 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7508 Note that all SUBREGs of MEM are paradoxical; otherwise they
7509 would have been rewritten. */
7510 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7511 && GET_CODE (SUBREG_REG (y)) == MEM
7512 && rtx_equal_p (SUBREG_REG (y),
7513 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7516 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7517 && GET_CODE (SUBREG_REG (x)) == MEM
7518 && rtx_equal_p (SUBREG_REG (x),
7519 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7522 /* We used to see if get_last_value of X and Y were the same but that's
7523 not correct. In one direction, we'll cause the assignment to have
7524 the wrong destination and in the case, we'll import a register into this
7525 insn that might have already have been dead. So fail if none of the
7526 above cases are true. */
7530 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7531 Return that assignment if so.
7533 We only handle the most common cases. */
7536 make_field_assignment (x)
7539 rtx dest = SET_DEST (x);
7540 rtx src = SET_SRC (x);
7545 unsigned HOST_WIDE_INT len;
7547 enum machine_mode mode;
7549 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7550 a clear of a one-bit field. We will have changed it to
7551 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7554 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7555 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7556 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7557 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7559 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7562 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7566 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7567 && subreg_lowpart_p (XEXP (src, 0))
7568 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7569 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7570 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7571 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7572 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7574 assign = make_extraction (VOIDmode, dest, 0,
7575 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7578 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7582 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7584 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7585 && XEXP (XEXP (src, 0), 0) == const1_rtx
7586 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7588 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7591 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7595 /* The other case we handle is assignments into a constant-position
7596 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7597 a mask that has all one bits except for a group of zero bits and
7598 OTHER is known to have zeros where C1 has ones, this is such an
7599 assignment. Compute the position and length from C1. Shift OTHER
7600 to the appropriate position, force it to the required mode, and
7601 make the extraction. Check for the AND in both operands. */
7603 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7606 rhs = expand_compound_operation (XEXP (src, 0));
7607 lhs = expand_compound_operation (XEXP (src, 1));
7609 if (GET_CODE (rhs) == AND
7610 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7611 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7612 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7613 else if (GET_CODE (lhs) == AND
7614 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7615 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7616 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7620 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7621 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7622 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7623 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7626 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7630 /* The mode to use for the source is the mode of the assignment, or of
7631 what is inside a possible STRICT_LOW_PART. */
7632 mode = (GET_CODE (assign) == STRICT_LOW_PART
7633 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7635 /* Shift OTHER right POS places and make it the source, restricting it
7636 to the proper length and mode. */
7638 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7639 GET_MODE (src), other, pos),
7641 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7642 ? GET_MODE_MASK (mode)
7643 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7646 return gen_rtx_combine (SET, VOIDmode, assign, src);
7649 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7653 apply_distributive_law (x)
7656 enum rtx_code code = GET_CODE (x);
7657 rtx lhs, rhs, other;
7659 enum rtx_code inner_code;
7661 /* Distributivity is not true for floating point.
7662 It can change the value. So don't do it.
7663 -- rms and moshier@world.std.com. */
7664 if (FLOAT_MODE_P (GET_MODE (x)))
7667 /* The outer operation can only be one of the following: */
7668 if (code != IOR && code != AND && code != XOR
7669 && code != PLUS && code != MINUS)
7672 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7674 /* If either operand is a primitive we can't do anything, so get out
7676 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7677 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7680 lhs = expand_compound_operation (lhs);
7681 rhs = expand_compound_operation (rhs);
7682 inner_code = GET_CODE (lhs);
7683 if (inner_code != GET_CODE (rhs))
7686 /* See if the inner and outer operations distribute. */
7693 /* These all distribute except over PLUS. */
7694 if (code == PLUS || code == MINUS)
7699 if (code != PLUS && code != MINUS)
7704 /* This is also a multiply, so it distributes over everything. */
7708 /* Non-paradoxical SUBREGs distributes over all operations, provided
7709 the inner modes and word numbers are the same, this is an extraction
7710 of a low-order part, we don't convert an fp operation to int or
7711 vice versa, and we would not be converting a single-word
7712 operation into a multi-word operation. The latter test is not
7713 required, but it prevents generating unneeded multi-word operations.
7714 Some of the previous tests are redundant given the latter test, but
7715 are retained because they are required for correctness.
7717 We produce the result slightly differently in this case. */
7719 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7720 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7721 || ! subreg_lowpart_p (lhs)
7722 || (GET_MODE_CLASS (GET_MODE (lhs))
7723 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7724 || (GET_MODE_SIZE (GET_MODE (lhs))
7725 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7726 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7729 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7730 SUBREG_REG (lhs), SUBREG_REG (rhs));
7731 return gen_lowpart_for_combine (GET_MODE (x), tem);
7737 /* Set LHS and RHS to the inner operands (A and B in the example
7738 above) and set OTHER to the common operand (C in the example).
7739 These is only one way to do this unless the inner operation is
7741 if (GET_RTX_CLASS (inner_code) == 'c'
7742 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7743 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7744 else if (GET_RTX_CLASS (inner_code) == 'c'
7745 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7746 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7747 else if (GET_RTX_CLASS (inner_code) == 'c'
7748 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7749 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7750 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7751 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7755 /* Form the new inner operation, seeing if it simplifies first. */
7756 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7758 /* There is one exception to the general way of distributing:
7759 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7760 if (code == XOR && inner_code == IOR)
7763 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7766 /* We may be able to continuing distributing the result, so call
7767 ourselves recursively on the inner operation before forming the
7768 outer operation, which we return. */
7769 return gen_binary (inner_code, GET_MODE (x),
7770 apply_distributive_law (tem), other);
7773 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7776 Return an equivalent form, if different from X. Otherwise, return X. If
7777 X is zero, we are to always construct the equivalent form. */
7780 simplify_and_const_int (x, mode, varop, constop)
7782 enum machine_mode mode;
7784 unsigned HOST_WIDE_INT constop;
7786 unsigned HOST_WIDE_INT nonzero;
7789 /* Simplify VAROP knowing that we will be only looking at some of the
7791 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7793 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7794 CONST_INT, we are done. */
7795 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7798 /* See what bits may be nonzero in VAROP. Unlike the general case of
7799 a call to nonzero_bits, here we don't care about bits outside
7802 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7803 nonzero = trunc_int_for_mode (nonzero, mode);
7805 /* Turn off all bits in the constant that are known to already be zero.
7806 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7807 which is tested below. */
7811 /* If we don't have any bits left, return zero. */
7815 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7816 a power of two, we can replace this with a ASHIFT. */
7817 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7818 && (i = exact_log2 (constop)) >= 0)
7819 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7821 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7822 or XOR, then try to apply the distributive law. This may eliminate
7823 operations if either branch can be simplified because of the AND.
7824 It may also make some cases more complex, but those cases probably
7825 won't match a pattern either with or without this. */
7827 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7829 gen_lowpart_for_combine
7831 apply_distributive_law
7832 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7833 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7834 XEXP (varop, 0), constop),
7835 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7836 XEXP (varop, 1), constop))));
7838 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7839 if we already had one (just check for the simplest cases). */
7840 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7841 && GET_MODE (XEXP (x, 0)) == mode
7842 && SUBREG_REG (XEXP (x, 0)) == varop)
7843 varop = XEXP (x, 0);
7845 varop = gen_lowpart_for_combine (mode, varop);
7847 /* If we can't make the SUBREG, try to return what we were given. */
7848 if (GET_CODE (varop) == CLOBBER)
7849 return x ? x : varop;
7851 /* If we are only masking insignificant bits, return VAROP. */
7852 if (constop == nonzero)
7855 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7856 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7857 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7861 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7862 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7863 SUBST (XEXP (x, 1), GEN_INT (constop));
7865 SUBST (XEXP (x, 0), varop);
7871 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7872 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7873 is less useful. We can't allow both, because that results in exponential
7874 run time recursion. There is a nullstone testcase that triggered
7875 this. This macro avoids accidental uses of num_sign_bit_copies. */
7876 #define num_sign_bit_copies()
7878 /* Given an expression, X, compute which bits in X can be non-zero.
7879 We don't care about bits outside of those defined in MODE.
7881 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7882 a shift, AND, or zero_extract, we can do better. */
7884 static unsigned HOST_WIDE_INT
7885 nonzero_bits (x, mode)
7887 enum machine_mode mode;
7889 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7890 unsigned HOST_WIDE_INT inner_nz;
7892 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7895 /* For floating-point values, assume all bits are needed. */
7896 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7899 /* If X is wider than MODE, use its mode instead. */
7900 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7902 mode = GET_MODE (x);
7903 nonzero = GET_MODE_MASK (mode);
7904 mode_width = GET_MODE_BITSIZE (mode);
7907 if (mode_width > HOST_BITS_PER_WIDE_INT)
7908 /* Our only callers in this case look for single bit values. So
7909 just return the mode mask. Those tests will then be false. */
7912 #ifndef WORD_REGISTER_OPERATIONS
7913 /* If MODE is wider than X, but both are a single word for both the host
7914 and target machines, we can compute this from which bits of the
7915 object might be nonzero in its own mode, taking into account the fact
7916 that on many CISC machines, accessing an object in a wider mode
7917 causes the high-order bits to become undefined. So they are
7918 not known to be zero. */
7920 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7921 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7922 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7923 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7925 nonzero &= nonzero_bits (x, GET_MODE (x));
7926 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7931 code = GET_CODE (x);
7935 #ifdef POINTERS_EXTEND_UNSIGNED
7936 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7937 all the bits above ptr_mode are known to be zero. */
7938 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7939 && REGNO_POINTER_FLAG (REGNO (x)))
7940 nonzero &= GET_MODE_MASK (ptr_mode);
7943 #ifdef STACK_BOUNDARY
7944 /* If this is the stack pointer, we may know something about its
7945 alignment. If PUSH_ROUNDING is defined, it is possible for the
7946 stack to be momentarily aligned only to that amount, so we pick
7947 the least alignment. */
7949 /* We can't check for arg_pointer_rtx here, because it is not
7950 guaranteed to have as much alignment as the stack pointer.
7951 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7952 alignment but the argument pointer has only 64 bit alignment. */
7954 if ((x == frame_pointer_rtx
7955 || x == stack_pointer_rtx
7956 || x == hard_frame_pointer_rtx
7957 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7958 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7964 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7966 #ifdef PUSH_ROUNDING
7967 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
7968 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7971 /* We must return here, otherwise we may get a worse result from
7972 one of the choices below. There is nothing useful below as
7973 far as the stack pointer is concerned. */
7974 return nonzero &= ~ (sp_alignment - 1);
7978 /* If X is a register whose nonzero bits value is current, use it.
7979 Otherwise, if X is a register whose value we can find, use that
7980 value. Otherwise, use the previously-computed global nonzero bits
7981 for this register. */
7983 if (reg_last_set_value[REGNO (x)] != 0
7984 && reg_last_set_mode[REGNO (x)] == mode
7985 && (reg_last_set_label[REGNO (x)] == label_tick
7986 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7987 && REG_N_SETS (REGNO (x)) == 1
7988 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7990 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7991 return reg_last_set_nonzero_bits[REGNO (x)];
7993 tem = get_last_value (x);
7997 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7998 /* If X is narrower than MODE and TEM is a non-negative
7999 constant that would appear negative in the mode of X,
8000 sign-extend it for use in reg_nonzero_bits because some
8001 machines (maybe most) will actually do the sign-extension
8002 and this is the conservative approach.
8004 ??? For 2.5, try to tighten up the MD files in this regard
8005 instead of this kludge. */
8007 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8008 && GET_CODE (tem) == CONST_INT
8010 && 0 != (INTVAL (tem)
8011 & ((HOST_WIDE_INT) 1
8012 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8013 tem = GEN_INT (INTVAL (tem)
8014 | ((HOST_WIDE_INT) (-1)
8015 << GET_MODE_BITSIZE (GET_MODE (x))));
8017 return nonzero_bits (tem, mode);
8019 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8020 return reg_nonzero_bits[REGNO (x)] & nonzero;
8025 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8026 /* If X is negative in MODE, sign-extend the value. */
8027 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8028 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8029 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8035 #ifdef LOAD_EXTEND_OP
8036 /* In many, if not most, RISC machines, reading a byte from memory
8037 zeros the rest of the register. Noticing that fact saves a lot
8038 of extra zero-extends. */
8039 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8040 nonzero &= GET_MODE_MASK (GET_MODE (x));
8050 /* If this produces an integer result, we know which bits are set.
8051 Code here used to clear bits outside the mode of X, but that is
8054 if (GET_MODE_CLASS (mode) == MODE_INT
8055 && mode_width <= HOST_BITS_PER_WIDE_INT)
8056 nonzero = STORE_FLAG_VALUE;
8061 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8062 and num_sign_bit_copies. */
8063 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8064 == GET_MODE_BITSIZE (GET_MODE (x)))
8068 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8069 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
8074 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8075 and num_sign_bit_copies. */
8076 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8077 == GET_MODE_BITSIZE (GET_MODE (x)))
8083 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8087 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8088 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8089 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8093 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8094 Otherwise, show all the bits in the outer mode but not the inner
8096 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8097 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8099 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8101 & (((HOST_WIDE_INT) 1
8102 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8103 inner_nz |= (GET_MODE_MASK (mode)
8104 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8107 nonzero &= inner_nz;
8111 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8112 & nonzero_bits (XEXP (x, 1), mode));
8116 case UMIN: case UMAX: case SMIN: case SMAX:
8117 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8118 | nonzero_bits (XEXP (x, 1), mode));
8121 case PLUS: case MINUS:
8123 case DIV: case UDIV:
8124 case MOD: case UMOD:
8125 /* We can apply the rules of arithmetic to compute the number of
8126 high- and low-order zero bits of these operations. We start by
8127 computing the width (position of the highest-order non-zero bit)
8128 and the number of low-order zero bits for each value. */
8130 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8131 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8132 int width0 = floor_log2 (nz0) + 1;
8133 int width1 = floor_log2 (nz1) + 1;
8134 int low0 = floor_log2 (nz0 & -nz0);
8135 int low1 = floor_log2 (nz1 & -nz1);
8136 HOST_WIDE_INT op0_maybe_minusp
8137 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8138 HOST_WIDE_INT op1_maybe_minusp
8139 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8140 unsigned int result_width = mode_width;
8148 && (XEXP (x, 0) == stack_pointer_rtx
8149 || XEXP (x, 0) == frame_pointer_rtx)
8150 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8152 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8154 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
8155 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8156 width0 = floor_log2 (nz0) + 1;
8157 width1 = floor_log2 (nz1) + 1;
8158 low0 = floor_log2 (nz0 & -nz0);
8159 low1 = floor_log2 (nz1 & -nz1);
8162 result_width = MAX (width0, width1) + 1;
8163 result_low = MIN (low0, low1);
8166 result_low = MIN (low0, low1);
8169 result_width = width0 + width1;
8170 result_low = low0 + low1;
8173 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8174 result_width = width0;
8177 result_width = width0;
8180 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8181 result_width = MIN (width0, width1);
8182 result_low = MIN (low0, low1);
8185 result_width = MIN (width0, width1);
8186 result_low = MIN (low0, low1);
8192 if (result_width < mode_width)
8193 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8196 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
8201 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8202 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8203 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8207 /* If this is a SUBREG formed for a promoted variable that has
8208 been zero-extended, we know that at least the high-order bits
8209 are zero, though others might be too. */
8211 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8212 nonzero = (GET_MODE_MASK (GET_MODE (x))
8213 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8215 /* If the inner mode is a single word for both the host and target
8216 machines, we can compute this from which bits of the inner
8217 object might be nonzero. */
8218 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8219 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8220 <= HOST_BITS_PER_WIDE_INT))
8222 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8224 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8225 /* If this is a typical RISC machine, we only have to worry
8226 about the way loads are extended. */
8227 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8229 & (((unsigned HOST_WIDE_INT) 1
8230 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8232 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8235 /* On many CISC machines, accessing an object in a wider mode
8236 causes the high-order bits to become undefined. So they are
8237 not known to be zero. */
8238 if (GET_MODE_SIZE (GET_MODE (x))
8239 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8240 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8241 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8250 /* The nonzero bits are in two classes: any bits within MODE
8251 that aren't in GET_MODE (x) are always significant. The rest of the
8252 nonzero bits are those that are significant in the operand of
8253 the shift when shifted the appropriate number of bits. This
8254 shows that high-order bits are cleared by the right shift and
8255 low-order bits by left shifts. */
8256 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8257 && INTVAL (XEXP (x, 1)) >= 0
8258 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8260 enum machine_mode inner_mode = GET_MODE (x);
8261 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8262 int count = INTVAL (XEXP (x, 1));
8263 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8264 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8265 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8266 unsigned HOST_WIDE_INT outer = 0;
8268 if (mode_width > width)
8269 outer = (op_nonzero & nonzero & ~ mode_mask);
8271 if (code == LSHIFTRT)
8273 else if (code == ASHIFTRT)
8277 /* If the sign bit may have been nonzero before the shift, we
8278 need to mark all the places it could have been copied to
8279 by the shift as possibly nonzero. */
8280 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8281 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8283 else if (code == ASHIFT)
8286 inner = ((inner << (count % width)
8287 | (inner >> (width - (count % width)))) & mode_mask);
8289 nonzero &= (outer | inner);
8294 /* This is at most the number of bits in the mode. */
8295 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8299 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8300 | nonzero_bits (XEXP (x, 2), mode));
8310 /* See the macro definition above. */
8311 #undef num_sign_bit_copies
8313 /* Return the number of bits at the high-order end of X that are known to
8314 be equal to the sign bit. X will be used in mode MODE; if MODE is
8315 VOIDmode, X will be used in its own mode. The returned value will always
8316 be between 1 and the number of bits in MODE. */
8319 num_sign_bit_copies (x, mode)
8321 enum machine_mode mode;
8323 enum rtx_code code = GET_CODE (x);
8324 unsigned int bitwidth;
8325 int num0, num1, result;
8326 unsigned HOST_WIDE_INT nonzero;
8329 /* If we weren't given a mode, use the mode of X. If the mode is still
8330 VOIDmode, we don't know anything. Likewise if one of the modes is
8333 if (mode == VOIDmode)
8334 mode = GET_MODE (x);
8336 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8339 bitwidth = GET_MODE_BITSIZE (mode);
8341 /* For a smaller object, just ignore the high bits. */
8342 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8344 num0 = num_sign_bit_copies (x, GET_MODE (x));
8346 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8349 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8351 #ifndef WORD_REGISTER_OPERATIONS
8352 /* If this machine does not do all register operations on the entire
8353 register and MODE is wider than the mode of X, we can say nothing
8354 at all about the high-order bits. */
8357 /* Likewise on machines that do, if the mode of the object is smaller
8358 than a word and loads of that size don't sign extend, we can say
8359 nothing about the high order bits. */
8360 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8361 #ifdef LOAD_EXTEND_OP
8362 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8373 #ifdef POINTERS_EXTEND_UNSIGNED
8374 /* If pointers extend signed and this is a pointer in Pmode, say that
8375 all the bits above ptr_mode are known to be sign bit copies. */
8376 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8377 && REGNO_POINTER_FLAG (REGNO (x)))
8378 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8381 if (reg_last_set_value[REGNO (x)] != 0
8382 && reg_last_set_mode[REGNO (x)] == mode
8383 && (reg_last_set_label[REGNO (x)] == label_tick
8384 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8385 && REG_N_SETS (REGNO (x)) == 1
8386 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8388 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8389 return reg_last_set_sign_bit_copies[REGNO (x)];
8391 tem = get_last_value (x);
8393 return num_sign_bit_copies (tem, mode);
8395 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8396 return reg_sign_bit_copies[REGNO (x)];
8400 #ifdef LOAD_EXTEND_OP
8401 /* Some RISC machines sign-extend all loads of smaller than a word. */
8402 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8403 return MAX (1, ((int) bitwidth
8404 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8409 /* If the constant is negative, take its 1's complement and remask.
8410 Then see how many zero bits we have. */
8411 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8412 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8413 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8414 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8416 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8419 /* If this is a SUBREG for a promoted object that is sign-extended
8420 and we are looking at it in a wider mode, we know that at least the
8421 high-order bits are known to be sign bit copies. */
8423 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8425 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8426 return MAX ((int) bitwidth
8427 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8431 /* For a smaller object, just ignore the high bits. */
8432 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8434 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8435 return MAX (1, (num0
8436 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8440 #ifdef WORD_REGISTER_OPERATIONS
8441 #ifdef LOAD_EXTEND_OP
8442 /* For paradoxical SUBREGs on machines where all register operations
8443 affect the entire register, just look inside. Note that we are
8444 passing MODE to the recursive call, so the number of sign bit copies
8445 will remain relative to that mode, not the inner mode. */
8447 /* This works only if loads sign extend. Otherwise, if we get a
8448 reload for the inner part, it may be loaded from the stack, and
8449 then we lose all sign bit copies that existed before the store
8452 if ((GET_MODE_SIZE (GET_MODE (x))
8453 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8454 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8455 return num_sign_bit_copies (SUBREG_REG (x), mode);
8461 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8462 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8466 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8467 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8470 /* For a smaller object, just ignore the high bits. */
8471 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8472 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8476 return num_sign_bit_copies (XEXP (x, 0), mode);
8478 case ROTATE: case ROTATERT:
8479 /* If we are rotating left by a number of bits less than the number
8480 of sign bit copies, we can just subtract that amount from the
8482 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8483 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8485 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8486 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8487 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8492 /* In general, this subtracts one sign bit copy. But if the value
8493 is known to be positive, the number of sign bit copies is the
8494 same as that of the input. Finally, if the input has just one bit
8495 that might be nonzero, all the bits are copies of the sign bit. */
8496 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8497 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8498 return num0 > 1 ? num0 - 1 : 1;
8500 nonzero = nonzero_bits (XEXP (x, 0), mode);
8505 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8510 case IOR: case AND: case XOR:
8511 case SMIN: case SMAX: case UMIN: case UMAX:
8512 /* Logical operations will preserve the number of sign-bit copies.
8513 MIN and MAX operations always return one of the operands. */
8514 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8515 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8516 return MIN (num0, num1);
8518 case PLUS: case MINUS:
8519 /* For addition and subtraction, we can have a 1-bit carry. However,
8520 if we are subtracting 1 from a positive number, there will not
8521 be such a carry. Furthermore, if the positive number is known to
8522 be 0 or 1, we know the result is either -1 or 0. */
8524 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8525 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8527 nonzero = nonzero_bits (XEXP (x, 0), mode);
8528 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8529 return (nonzero == 1 || nonzero == 0 ? bitwidth
8530 : bitwidth - floor_log2 (nonzero) - 1);
8533 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8534 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8535 return MAX (1, MIN (num0, num1) - 1);
8538 /* The number of bits of the product is the sum of the number of
8539 bits of both terms. However, unless one of the terms if known
8540 to be positive, we must allow for an additional bit since negating
8541 a negative number can remove one sign bit copy. */
8543 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8544 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8546 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8548 && (bitwidth > HOST_BITS_PER_WIDE_INT
8549 || (((nonzero_bits (XEXP (x, 0), mode)
8550 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8551 && ((nonzero_bits (XEXP (x, 1), mode)
8552 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8555 return MAX (1, result);
8558 /* The result must be <= the first operand. If the first operand
8559 has the high bit set, we know nothing about the number of sign
8561 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8563 else if ((nonzero_bits (XEXP (x, 0), mode)
8564 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8567 return num_sign_bit_copies (XEXP (x, 0), mode);
8570 /* The result must be <= the scond operand. */
8571 return num_sign_bit_copies (XEXP (x, 1), mode);
8574 /* Similar to unsigned division, except that we have to worry about
8575 the case where the divisor is negative, in which case we have
8577 result = num_sign_bit_copies (XEXP (x, 0), mode);
8579 && (bitwidth > HOST_BITS_PER_WIDE_INT
8580 || (nonzero_bits (XEXP (x, 1), mode)
8581 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8587 result = num_sign_bit_copies (XEXP (x, 1), mode);
8589 && (bitwidth > HOST_BITS_PER_WIDE_INT
8590 || (nonzero_bits (XEXP (x, 1), mode)
8591 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8597 /* Shifts by a constant add to the number of bits equal to the
8599 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8600 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8601 && INTVAL (XEXP (x, 1)) > 0)
8602 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8607 /* Left shifts destroy copies. */
8608 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8609 || INTVAL (XEXP (x, 1)) < 0
8610 || INTVAL (XEXP (x, 1)) >= bitwidth)
8613 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8614 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8617 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8618 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8619 return MIN (num0, num1);
8621 case EQ: case NE: case GE: case GT: case LE: case LT:
8622 case GEU: case GTU: case LEU: case LTU:
8623 if (STORE_FLAG_VALUE == -1)
8631 /* If we haven't been able to figure it out by one of the above rules,
8632 see if some of the high-order bits are known to be zero. If so,
8633 count those bits and return one less than that amount. If we can't
8634 safely compute the mask for this mode, always return BITWIDTH. */
8636 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8639 nonzero = nonzero_bits (x, mode);
8640 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8641 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8644 /* Return the number of "extended" bits there are in X, when interpreted
8645 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8646 unsigned quantities, this is the number of high-order zero bits.
8647 For signed quantities, this is the number of copies of the sign bit
8648 minus 1. In both case, this function returns the number of "spare"
8649 bits. For example, if two quantities for which this function returns
8650 at least 1 are added, the addition is known not to overflow.
8652 This function will always return 0 unless called during combine, which
8653 implies that it must be called from a define_split. */
8656 extended_count (x, mode, unsignedp)
8658 enum machine_mode mode;
8661 if (nonzero_sign_valid == 0)
8665 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8666 ? (GET_MODE_BITSIZE (mode) - 1
8667 - floor_log2 (nonzero_bits (x, mode)))
8669 : num_sign_bit_copies (x, mode) - 1);
8672 /* This function is called from `simplify_shift_const' to merge two
8673 outer operations. Specifically, we have already found that we need
8674 to perform operation *POP0 with constant *PCONST0 at the outermost
8675 position. We would now like to also perform OP1 with constant CONST1
8676 (with *POP0 being done last).
8678 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8679 the resulting operation. *PCOMP_P is set to 1 if we would need to
8680 complement the innermost operand, otherwise it is unchanged.
8682 MODE is the mode in which the operation will be done. No bits outside
8683 the width of this mode matter. It is assumed that the width of this mode
8684 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8686 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8687 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8688 result is simply *PCONST0.
8690 If the resulting operation cannot be expressed as one operation, we
8691 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8694 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8695 enum rtx_code *pop0;
8696 HOST_WIDE_INT *pconst0;
8698 HOST_WIDE_INT const1;
8699 enum machine_mode mode;
8702 enum rtx_code op0 = *pop0;
8703 HOST_WIDE_INT const0 = *pconst0;
8705 const0 &= GET_MODE_MASK (mode);
8706 const1 &= GET_MODE_MASK (mode);
8708 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8712 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8715 if (op1 == NIL || op0 == SET)
8718 else if (op0 == NIL)
8719 op0 = op1, const0 = const1;
8721 else if (op0 == op1)
8745 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8746 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8749 /* If the two constants aren't the same, we can't do anything. The
8750 remaining six cases can all be done. */
8751 else if (const0 != const1)
8759 /* (a & b) | b == b */
8761 else /* op1 == XOR */
8762 /* (a ^ b) | b == a | b */
8768 /* (a & b) ^ b == (~a) & b */
8769 op0 = AND, *pcomp_p = 1;
8770 else /* op1 == IOR */
8771 /* (a | b) ^ b == a & ~b */
8772 op0 = AND, *pconst0 = ~ const0;
8777 /* (a | b) & b == b */
8779 else /* op1 == XOR */
8780 /* (a ^ b) & b) == (~a) & b */
8787 /* Check for NO-OP cases. */
8788 const0 &= GET_MODE_MASK (mode);
8790 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8792 else if (const0 == 0 && op0 == AND)
8794 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8798 /* ??? Slightly redundant with the above mask, but not entirely.
8799 Moving this above means we'd have to sign-extend the mode mask
8800 for the final test. */
8801 const0 = trunc_int_for_mode (const0, mode);
8809 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8810 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8811 that we started with.
8813 The shift is normally computed in the widest mode we find in VAROP, as
8814 long as it isn't a different number of words than RESULT_MODE. Exceptions
8815 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8818 simplify_shift_const (x, code, result_mode, varop, input_count)
8821 enum machine_mode result_mode;
8825 enum rtx_code orig_code = code;
8826 int orig_count = input_count;
8829 enum machine_mode mode = result_mode;
8830 enum machine_mode shift_mode, tmode;
8831 unsigned int mode_words
8832 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8833 /* We form (outer_op (code varop count) (outer_const)). */
8834 enum rtx_code outer_op = NIL;
8835 HOST_WIDE_INT outer_const = 0;
8837 int complement_p = 0;
8840 /* If we were given an invalid count, don't do anything except exactly
8841 what was requested. */
8843 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8848 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8851 count = input_count;
8853 /* Unless one of the branches of the `if' in this loop does a `continue',
8854 we will `break' the loop after the `if'. */
8858 /* If we have an operand of (clobber (const_int 0)), just return that
8860 if (GET_CODE (varop) == CLOBBER)
8863 /* If we discovered we had to complement VAROP, leave. Making a NOT
8864 here would cause an infinite loop. */
8868 /* Convert ROTATERT to ROTATE. */
8869 if (code == ROTATERT)
8870 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8872 /* We need to determine what mode we will do the shift in. If the
8873 shift is a right shift or a ROTATE, we must always do it in the mode
8874 it was originally done in. Otherwise, we can do it in MODE, the
8875 widest mode encountered. */
8877 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8878 ? result_mode : mode);
8880 /* Handle cases where the count is greater than the size of the mode
8881 minus 1. For ASHIFT, use the size minus one as the count (this can
8882 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8883 take the count modulo the size. For other shifts, the result is
8886 Since these shifts are being produced by the compiler by combining
8887 multiple operations, each of which are defined, we know what the
8888 result is supposed to be. */
8890 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8892 if (code == ASHIFTRT)
8893 count = GET_MODE_BITSIZE (shift_mode) - 1;
8894 else if (code == ROTATE || code == ROTATERT)
8895 count %= GET_MODE_BITSIZE (shift_mode);
8898 /* We can't simply return zero because there may be an
8906 /* An arithmetic right shift of a quantity known to be -1 or 0
8908 if (code == ASHIFTRT
8909 && (num_sign_bit_copies (varop, shift_mode)
8910 == GET_MODE_BITSIZE (shift_mode)))
8916 /* If we are doing an arithmetic right shift and discarding all but
8917 the sign bit copies, this is equivalent to doing a shift by the
8918 bitsize minus one. Convert it into that shift because it will often
8919 allow other simplifications. */
8921 if (code == ASHIFTRT
8922 && (count + num_sign_bit_copies (varop, shift_mode)
8923 >= GET_MODE_BITSIZE (shift_mode)))
8924 count = GET_MODE_BITSIZE (shift_mode) - 1;
8926 /* We simplify the tests below and elsewhere by converting
8927 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8928 `make_compound_operation' will convert it to a ASHIFTRT for
8929 those machines (such as Vax) that don't have a LSHIFTRT. */
8930 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8932 && ((nonzero_bits (varop, shift_mode)
8933 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8937 switch (GET_CODE (varop))
8943 new = expand_compound_operation (varop);
8952 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8953 minus the width of a smaller mode, we can do this with a
8954 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8955 if ((code == ASHIFTRT || code == LSHIFTRT)
8956 && ! mode_dependent_address_p (XEXP (varop, 0))
8957 && ! MEM_VOLATILE_P (varop)
8958 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8959 MODE_INT, 1)) != BLKmode)
8961 if (BYTES_BIG_ENDIAN)
8962 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8964 new = gen_rtx_MEM (tmode,
8965 plus_constant (XEXP (varop, 0),
8966 count / BITS_PER_UNIT));
8968 MEM_COPY_ATTRIBUTES (new, varop);
8969 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8970 : ZERO_EXTEND, mode, new);
8977 /* Similar to the case above, except that we can only do this if
8978 the resulting mode is the same as that of the underlying
8979 MEM and adjust the address depending on the *bits* endianness
8980 because of the way that bit-field extract insns are defined. */
8981 if ((code == ASHIFTRT || code == LSHIFTRT)
8982 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8983 MODE_INT, 1)) != BLKmode
8984 && tmode == GET_MODE (XEXP (varop, 0)))
8986 if (BITS_BIG_ENDIAN)
8987 new = XEXP (varop, 0);
8990 new = copy_rtx (XEXP (varop, 0));
8991 SUBST (XEXP (new, 0),
8992 plus_constant (XEXP (new, 0),
8993 count / BITS_PER_UNIT));
8996 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8997 : ZERO_EXTEND, mode, new);
9004 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9005 the same number of words as what we've seen so far. Then store
9006 the widest mode in MODE. */
9007 if (subreg_lowpart_p (varop)
9008 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9009 > GET_MODE_SIZE (GET_MODE (varop)))
9010 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9011 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9014 varop = SUBREG_REG (varop);
9015 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9016 mode = GET_MODE (varop);
9022 /* Some machines use MULT instead of ASHIFT because MULT
9023 is cheaper. But it is still better on those machines to
9024 merge two shifts into one. */
9025 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9026 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9029 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9030 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9036 /* Similar, for when divides are cheaper. */
9037 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9038 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9041 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9042 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9048 /* If we are extracting just the sign bit of an arithmetic right
9049 shift, that shift is not needed. */
9050 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
9052 varop = XEXP (varop, 0);
9056 /* ... fall through ... */
9061 /* Here we have two nested shifts. The result is usually the
9062 AND of a new shift with a mask. We compute the result below. */
9063 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9064 && INTVAL (XEXP (varop, 1)) >= 0
9065 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9066 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9067 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9069 enum rtx_code first_code = GET_CODE (varop);
9070 unsigned int first_count = INTVAL (XEXP (varop, 1));
9071 unsigned HOST_WIDE_INT mask;
9074 /* We have one common special case. We can't do any merging if
9075 the inner code is an ASHIFTRT of a smaller mode. However, if
9076 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9077 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9078 we can convert it to
9079 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9080 This simplifies certain SIGN_EXTEND operations. */
9081 if (code == ASHIFT && first_code == ASHIFTRT
9082 && (GET_MODE_BITSIZE (result_mode)
9083 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9085 /* C3 has the low-order C1 bits zero. */
9087 mask = (GET_MODE_MASK (mode)
9088 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
9090 varop = simplify_and_const_int (NULL_RTX, result_mode,
9091 XEXP (varop, 0), mask);
9092 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9094 count = first_count;
9099 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9100 than C1 high-order bits equal to the sign bit, we can convert
9101 this to either an ASHIFT or a ASHIFTRT depending on the
9104 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9106 if (code == ASHIFTRT && first_code == ASHIFT
9107 && GET_MODE (varop) == shift_mode
9108 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9111 varop = XEXP (varop, 0);
9113 signed_count = count - first_count;
9114 if (signed_count < 0)
9115 count = - signed_count, code = ASHIFT;
9117 count = signed_count;
9122 /* There are some cases we can't do. If CODE is ASHIFTRT,
9123 we can only do this if FIRST_CODE is also ASHIFTRT.
9125 We can't do the case when CODE is ROTATE and FIRST_CODE is
9128 If the mode of this shift is not the mode of the outer shift,
9129 we can't do this if either shift is a right shift or ROTATE.
9131 Finally, we can't do any of these if the mode is too wide
9132 unless the codes are the same.
9134 Handle the case where the shift codes are the same
9137 if (code == first_code)
9139 if (GET_MODE (varop) != result_mode
9140 && (code == ASHIFTRT || code == LSHIFTRT
9144 count += first_count;
9145 varop = XEXP (varop, 0);
9149 if (code == ASHIFTRT
9150 || (code == ROTATE && first_code == ASHIFTRT)
9151 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9152 || (GET_MODE (varop) != result_mode
9153 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9154 || first_code == ROTATE
9155 || code == ROTATE)))
9158 /* To compute the mask to apply after the shift, shift the
9159 nonzero bits of the inner shift the same way the
9160 outer shift will. */
9162 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9165 = simplify_binary_operation (code, result_mode, mask_rtx,
9168 /* Give up if we can't compute an outer operation to use. */
9170 || GET_CODE (mask_rtx) != CONST_INT
9171 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9173 result_mode, &complement_p))
9176 /* If the shifts are in the same direction, we add the
9177 counts. Otherwise, we subtract them. */
9178 signed_count = count;
9179 if ((code == ASHIFTRT || code == LSHIFTRT)
9180 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9181 signed_count += first_count;
9183 signed_count -= first_count;
9185 /* If COUNT is positive, the new shift is usually CODE,
9186 except for the two exceptions below, in which case it is
9187 FIRST_CODE. If the count is negative, FIRST_CODE should
9189 if (signed_count > 0
9190 && ((first_code == ROTATE && code == ASHIFT)
9191 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9192 code = first_code, count = signed_count;
9193 else if (signed_count < 0)
9194 code = first_code, count = - signed_count;
9196 count = signed_count;
9198 varop = XEXP (varop, 0);
9202 /* If we have (A << B << C) for any shift, we can convert this to
9203 (A << C << B). This wins if A is a constant. Only try this if
9204 B is not a constant. */
9206 else if (GET_CODE (varop) == code
9207 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9209 = simplify_binary_operation (code, mode,
9213 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9220 /* Make this fit the case below. */
9221 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9222 GEN_INT (GET_MODE_MASK (mode)));
9228 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9229 with C the size of VAROP - 1 and the shift is logical if
9230 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9231 we have an (le X 0) operation. If we have an arithmetic shift
9232 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9233 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9235 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9236 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9237 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9238 && (code == LSHIFTRT || code == ASHIFTRT)
9239 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9240 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9243 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9246 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9247 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9252 /* If we have (shift (logical)), move the logical to the outside
9253 to allow it to possibly combine with another logical and the
9254 shift to combine with another shift. This also canonicalizes to
9255 what a ZERO_EXTRACT looks like. Also, some machines have
9256 (and (shift)) insns. */
9258 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9259 && (new = simplify_binary_operation (code, result_mode,
9261 GEN_INT (count))) != 0
9262 && GET_CODE(new) == CONST_INT
9263 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9264 INTVAL (new), result_mode, &complement_p))
9266 varop = XEXP (varop, 0);
9270 /* If we can't do that, try to simplify the shift in each arm of the
9271 logical expression, make a new logical expression, and apply
9272 the inverse distributive law. */
9274 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9275 XEXP (varop, 0), count);
9276 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9277 XEXP (varop, 1), count);
9279 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9280 varop = apply_distributive_law (varop);
9287 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9288 says that the sign bit can be tested, FOO has mode MODE, C is
9289 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9290 that may be nonzero. */
9291 if (code == LSHIFTRT
9292 && XEXP (varop, 1) == const0_rtx
9293 && GET_MODE (XEXP (varop, 0)) == result_mode
9294 && count == GET_MODE_BITSIZE (result_mode) - 1
9295 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9296 && ((STORE_FLAG_VALUE
9297 & ((HOST_WIDE_INT) 1
9298 < (GET_MODE_BITSIZE (result_mode) - 1))))
9299 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9300 && merge_outer_ops (&outer_op, &outer_const, XOR,
9301 (HOST_WIDE_INT) 1, result_mode,
9304 varop = XEXP (varop, 0);
9311 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9312 than the number of bits in the mode is equivalent to A. */
9313 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9314 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9316 varop = XEXP (varop, 0);
9321 /* NEG commutes with ASHIFT since it is multiplication. Move the
9322 NEG outside to allow shifts to combine. */
9324 && merge_outer_ops (&outer_op, &outer_const, NEG,
9325 (HOST_WIDE_INT) 0, result_mode,
9328 varop = XEXP (varop, 0);
9334 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9335 is one less than the number of bits in the mode is
9336 equivalent to (xor A 1). */
9337 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9338 && XEXP (varop, 1) == constm1_rtx
9339 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9340 && merge_outer_ops (&outer_op, &outer_const, XOR,
9341 (HOST_WIDE_INT) 1, result_mode,
9345 varop = XEXP (varop, 0);
9349 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9350 that might be nonzero in BAR are those being shifted out and those
9351 bits are known zero in FOO, we can replace the PLUS with FOO.
9352 Similarly in the other operand order. This code occurs when
9353 we are computing the size of a variable-size array. */
9355 if ((code == ASHIFTRT || code == LSHIFTRT)
9356 && count < HOST_BITS_PER_WIDE_INT
9357 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9358 && (nonzero_bits (XEXP (varop, 1), result_mode)
9359 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9361 varop = XEXP (varop, 0);
9364 else if ((code == ASHIFTRT || code == LSHIFTRT)
9365 && count < HOST_BITS_PER_WIDE_INT
9366 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9367 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9369 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9370 & nonzero_bits (XEXP (varop, 1),
9373 varop = XEXP (varop, 1);
9377 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9379 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9380 && (new = simplify_binary_operation (ASHIFT, result_mode,
9382 GEN_INT (count))) != 0
9383 && GET_CODE (new) == CONST_INT
9384 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9385 INTVAL (new), result_mode, &complement_p))
9387 varop = XEXP (varop, 0);
9393 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9394 with C the size of VAROP - 1 and the shift is logical if
9395 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9396 we have a (gt X 0) operation. If the shift is arithmetic with
9397 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9398 we have a (neg (gt X 0)) operation. */
9400 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9401 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9402 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9403 && (code == LSHIFTRT || code == ASHIFTRT)
9404 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9405 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9406 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9409 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9412 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9413 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9420 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9421 if the truncate does not affect the value. */
9422 if (code == LSHIFTRT
9423 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9424 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9425 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9426 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9427 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9429 rtx varop_inner = XEXP (varop, 0);
9432 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9433 XEXP (varop_inner, 0),
9435 + INTVAL (XEXP (varop_inner, 1))));
9436 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9450 /* We need to determine what mode to do the shift in. If the shift is
9451 a right shift or ROTATE, we must always do it in the mode it was
9452 originally done in. Otherwise, we can do it in MODE, the widest mode
9453 encountered. The code we care about is that of the shift that will
9454 actually be done, not the shift that was originally requested. */
9456 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9457 ? result_mode : mode);
9459 /* We have now finished analyzing the shift. The result should be
9460 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9461 OUTER_OP is non-NIL, it is an operation that needs to be applied
9462 to the result of the shift. OUTER_CONST is the relevant constant,
9463 but we must turn off all bits turned off in the shift.
9465 If we were passed a value for X, see if we can use any pieces of
9466 it. If not, make new rtx. */
9468 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9469 && GET_CODE (XEXP (x, 1)) == CONST_INT
9470 && INTVAL (XEXP (x, 1)) == count)
9471 const_rtx = XEXP (x, 1);
9473 const_rtx = GEN_INT (count);
9475 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9476 && GET_MODE (XEXP (x, 0)) == shift_mode
9477 && SUBREG_REG (XEXP (x, 0)) == varop)
9478 varop = XEXP (x, 0);
9479 else if (GET_MODE (varop) != shift_mode)
9480 varop = gen_lowpart_for_combine (shift_mode, varop);
9482 /* If we can't make the SUBREG, try to return what we were given. */
9483 if (GET_CODE (varop) == CLOBBER)
9484 return x ? x : varop;
9486 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9491 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9492 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9494 SUBST (XEXP (x, 0), varop);
9495 SUBST (XEXP (x, 1), const_rtx);
9498 /* If we have an outer operation and we just made a shift, it is
9499 possible that we could have simplified the shift were it not
9500 for the outer operation. So try to do the simplification
9503 if (outer_op != NIL && GET_CODE (x) == code
9504 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9505 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9506 INTVAL (XEXP (x, 1)));
9508 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9509 turn off all the bits that the shift would have turned off. */
9510 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9511 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9512 GET_MODE_MASK (result_mode) >> orig_count);
9514 /* Do the remainder of the processing in RESULT_MODE. */
9515 x = gen_lowpart_for_combine (result_mode, x);
9517 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9520 x = gen_unary (NOT, result_mode, result_mode, x);
9522 if (outer_op != NIL)
9524 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9525 outer_const = trunc_int_for_mode (outer_const, result_mode);
9527 if (outer_op == AND)
9528 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9529 else if (outer_op == SET)
9530 /* This means that we have determined that the result is
9531 equivalent to a constant. This should be rare. */
9532 x = GEN_INT (outer_const);
9533 else if (GET_RTX_CLASS (outer_op) == '1')
9534 x = gen_unary (outer_op, result_mode, result_mode, x);
9536 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9542 /* Like recog, but we receive the address of a pointer to a new pattern.
9543 We try to match the rtx that the pointer points to.
9544 If that fails, we may try to modify or replace the pattern,
9545 storing the replacement into the same pointer object.
9547 Modifications include deletion or addition of CLOBBERs.
9549 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9550 the CLOBBERs are placed.
9552 The value is the final insn code from the pattern ultimately matched,
9556 recog_for_combine (pnewpat, insn, pnotes)
9561 register rtx pat = *pnewpat;
9562 int insn_code_number;
9563 int num_clobbers_to_add = 0;
9567 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9568 we use to indicate that something didn't match. If we find such a
9569 thing, force rejection. */
9570 if (GET_CODE (pat) == PARALLEL)
9571 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9572 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9573 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9576 /* Is the result of combination a valid instruction? */
9577 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9579 /* If it isn't, there is the possibility that we previously had an insn
9580 that clobbered some register as a side effect, but the combined
9581 insn doesn't need to do that. So try once more without the clobbers
9582 unless this represents an ASM insn. */
9584 if (insn_code_number < 0 && ! check_asm_operands (pat)
9585 && GET_CODE (pat) == PARALLEL)
9589 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9590 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9593 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9597 SUBST_INT (XVECLEN (pat, 0), pos);
9600 pat = XVECEXP (pat, 0, 0);
9602 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9605 /* If we had any clobbers to add, make a new pattern than contains
9606 them. Then check to make sure that all of them are dead. */
9607 if (num_clobbers_to_add)
9609 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9610 gen_rtvec (GET_CODE (pat) == PARALLEL
9612 + num_clobbers_to_add)
9613 : num_clobbers_to_add + 1));
9615 if (GET_CODE (pat) == PARALLEL)
9616 for (i = 0; i < XVECLEN (pat, 0); i++)
9617 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9619 XVECEXP (newpat, 0, 0) = pat;
9621 add_clobbers (newpat, insn_code_number);
9623 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9624 i < XVECLEN (newpat, 0); i++)
9626 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9627 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9629 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9630 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9638 return insn_code_number;
9641 /* Like gen_lowpart but for use by combine. In combine it is not possible
9642 to create any new pseudoregs. However, it is safe to create
9643 invalid memory addresses, because combine will try to recognize
9644 them and all they will do is make the combine attempt fail.
9646 If for some reason this cannot do its job, an rtx
9647 (clobber (const_int 0)) is returned.
9648 An insn containing that will not be recognized. */
9653 gen_lowpart_for_combine (mode, x)
9654 enum machine_mode mode;
9659 if (GET_MODE (x) == mode)
9662 /* We can only support MODE being wider than a word if X is a
9663 constant integer or has a mode the same size. */
9665 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9666 && ! ((GET_MODE (x) == VOIDmode
9667 && (GET_CODE (x) == CONST_INT
9668 || GET_CODE (x) == CONST_DOUBLE))
9669 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9670 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9672 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9673 won't know what to do. So we will strip off the SUBREG here and
9674 process normally. */
9675 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9678 if (GET_MODE (x) == mode)
9682 result = gen_lowpart_common (mode, x);
9684 && GET_CODE (result) == SUBREG
9685 && GET_CODE (SUBREG_REG (result)) == REG
9686 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9687 && (GET_MODE_SIZE (GET_MODE (result))
9688 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9689 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9694 if (GET_CODE (x) == MEM)
9696 register int offset = 0;
9699 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9701 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9702 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9704 /* If we want to refer to something bigger than the original memref,
9705 generate a perverse subreg instead. That will force a reload
9706 of the original memref X. */
9707 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9708 return gen_rtx_SUBREG (mode, x, 0);
9710 if (WORDS_BIG_ENDIAN)
9711 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9712 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9714 if (BYTES_BIG_ENDIAN)
9716 /* Adjust the address so that the address-after-the-data is
9718 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9719 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9721 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9722 MEM_COPY_ATTRIBUTES (new, x);
9726 /* If X is a comparison operator, rewrite it in a new mode. This
9727 probably won't match, but may allow further simplifications. */
9728 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9729 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9731 /* If we couldn't simplify X any other way, just enclose it in a
9732 SUBREG. Normally, this SUBREG won't match, but some patterns may
9733 include an explicit SUBREG or we may simplify it further in combine. */
9738 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9739 word = ((GET_MODE_SIZE (GET_MODE (x))
9740 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9742 return gen_rtx_SUBREG (mode, x, word);
9746 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9747 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9749 If the identical expression was previously in the insn (in the undobuf),
9750 it will be returned. Only if it is not found will a new expression
9755 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9757 #ifndef ANSI_PROTOTYPES
9759 enum machine_mode mode;
9771 #ifndef ANSI_PROTOTYPES
9772 code = va_arg (p, enum rtx_code);
9773 mode = va_arg (p, enum machine_mode);
9776 n_args = GET_RTX_LENGTH (code);
9777 fmt = GET_RTX_FORMAT (code);
9779 if (n_args == 0 || n_args > 3)
9782 /* Get each arg and verify that it is supposed to be an expression. */
9783 for (j = 0; j < n_args; j++)
9788 args[j] = va_arg (p, rtx);
9793 /* See if this is in undobuf. Be sure we don't use objects that came
9794 from another insn; this could produce circular rtl structures. */
9796 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9798 && GET_CODE (undo->old_contents.r) == code
9799 && GET_MODE (undo->old_contents.r) == mode)
9801 for (j = 0; j < n_args; j++)
9802 if (XEXP (undo->old_contents.r, j) != args[j])
9806 return undo->old_contents.r;
9809 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9810 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9811 rt = rtx_alloc (code);
9812 PUT_MODE (rt, mode);
9813 XEXP (rt, 0) = args[0];
9816 XEXP (rt, 1) = args[1];
9818 XEXP (rt, 2) = args[2];
9823 /* These routines make binary and unary operations by first seeing if they
9824 fold; if not, a new expression is allocated. */
9827 gen_binary (code, mode, op0, op1)
9829 enum machine_mode mode;
9835 if (GET_RTX_CLASS (code) == 'c'
9836 && (GET_CODE (op0) == CONST_INT
9837 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9838 tem = op0, op0 = op1, op1 = tem;
9840 if (GET_RTX_CLASS (code) == '<')
9842 enum machine_mode op_mode = GET_MODE (op0);
9844 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9845 just (REL_OP X Y). */
9846 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9848 op1 = XEXP (op0, 1);
9849 op0 = XEXP (op0, 0);
9850 op_mode = GET_MODE (op0);
9853 if (op_mode == VOIDmode)
9854 op_mode = GET_MODE (op1);
9855 result = simplify_relational_operation (code, op_mode, op0, op1);
9858 result = simplify_binary_operation (code, mode, op0, op1);
9863 /* Put complex operands first and constants second. */
9864 if (GET_RTX_CLASS (code) == 'c'
9865 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9866 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9867 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9868 || (GET_CODE (op0) == SUBREG
9869 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9870 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9871 return gen_rtx_combine (code, mode, op1, op0);
9873 /* If we are turning off bits already known off in OP0, we need not do
9875 else if (code == AND && GET_CODE (op1) == CONST_INT
9876 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9877 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9880 return gen_rtx_combine (code, mode, op0, op1);
9884 gen_unary (code, mode, op0_mode, op0)
9886 enum machine_mode mode, op0_mode;
9889 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9894 return gen_rtx_combine (code, mode, op0);
9897 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9898 comparison code that will be tested.
9900 The result is a possibly different comparison code to use. *POP0 and
9901 *POP1 may be updated.
9903 It is possible that we might detect that a comparison is either always
9904 true or always false. However, we do not perform general constant
9905 folding in combine, so this knowledge isn't useful. Such tautologies
9906 should have been detected earlier. Hence we ignore all such cases. */
9908 static enum rtx_code
9909 simplify_comparison (code, pop0, pop1)
9918 enum machine_mode mode, tmode;
9920 /* Try a few ways of applying the same transformation to both operands. */
9923 #ifndef WORD_REGISTER_OPERATIONS
9924 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9925 so check specially. */
9926 if (code != GTU && code != GEU && code != LTU && code != LEU
9927 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9928 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9929 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9930 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9931 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9932 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9933 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9934 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9935 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9936 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9937 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9938 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9939 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9940 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9941 && (INTVAL (XEXP (op0, 1))
9942 == (GET_MODE_BITSIZE (GET_MODE (op0))
9944 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9946 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9947 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9951 /* If both operands are the same constant shift, see if we can ignore the
9952 shift. We can if the shift is a rotate or if the bits shifted out of
9953 this shift are known to be zero for both inputs and if the type of
9954 comparison is compatible with the shift. */
9955 if (GET_CODE (op0) == GET_CODE (op1)
9956 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9957 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9958 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9959 && (code != GT && code != LT && code != GE && code != LE))
9960 || (GET_CODE (op0) == ASHIFTRT
9961 && (code != GTU && code != LTU
9962 && code != GEU && code != GEU)))
9963 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9964 && INTVAL (XEXP (op0, 1)) >= 0
9965 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9966 && XEXP (op0, 1) == XEXP (op1, 1))
9968 enum machine_mode mode = GET_MODE (op0);
9969 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9970 int shift_count = INTVAL (XEXP (op0, 1));
9972 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9973 mask &= (mask >> shift_count) << shift_count;
9974 else if (GET_CODE (op0) == ASHIFT)
9975 mask = (mask & (mask << shift_count)) >> shift_count;
9977 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9978 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9979 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9984 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9985 SUBREGs are of the same mode, and, in both cases, the AND would
9986 be redundant if the comparison was done in the narrower mode,
9987 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9988 and the operand's possibly nonzero bits are 0xffffff01; in that case
9989 if we only care about QImode, we don't need the AND). This case
9990 occurs if the output mode of an scc insn is not SImode and
9991 STORE_FLAG_VALUE == 1 (e.g., the 386).
9993 Similarly, check for a case where the AND's are ZERO_EXTEND
9994 operations from some narrower mode even though a SUBREG is not
9997 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9998 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9999 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10001 rtx inner_op0 = XEXP (op0, 0);
10002 rtx inner_op1 = XEXP (op1, 0);
10003 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10004 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10007 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10008 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10009 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10010 && (GET_MODE (SUBREG_REG (inner_op0))
10011 == GET_MODE (SUBREG_REG (inner_op1)))
10012 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10013 <= HOST_BITS_PER_WIDE_INT)
10014 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10015 GET_MODE (SUBREG_REG (inner_op0)))))
10016 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10017 GET_MODE (SUBREG_REG (inner_op1))))))
10019 op0 = SUBREG_REG (inner_op0);
10020 op1 = SUBREG_REG (inner_op1);
10022 /* The resulting comparison is always unsigned since we masked
10023 off the original sign bit. */
10024 code = unsigned_condition (code);
10030 for (tmode = GET_CLASS_NARROWEST_MODE
10031 (GET_MODE_CLASS (GET_MODE (op0)));
10032 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10033 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10035 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10036 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10037 code = unsigned_condition (code);
10046 /* If both operands are NOT, we can strip off the outer operation
10047 and adjust the comparison code for swapped operands; similarly for
10048 NEG, except that this must be an equality comparison. */
10049 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10050 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10051 && (code == EQ || code == NE)))
10052 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10058 /* If the first operand is a constant, swap the operands and adjust the
10059 comparison code appropriately, but don't do this if the second operand
10060 is already a constant integer. */
10061 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10063 tem = op0, op0 = op1, op1 = tem;
10064 code = swap_condition (code);
10067 /* We now enter a loop during which we will try to simplify the comparison.
10068 For the most part, we only are concerned with comparisons with zero,
10069 but some things may really be comparisons with zero but not start
10070 out looking that way. */
10072 while (GET_CODE (op1) == CONST_INT)
10074 enum machine_mode mode = GET_MODE (op0);
10075 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10076 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10077 int equality_comparison_p;
10078 int sign_bit_comparison_p;
10079 int unsigned_comparison_p;
10080 HOST_WIDE_INT const_op;
10082 /* We only want to handle integral modes. This catches VOIDmode,
10083 CCmode, and the floating-point modes. An exception is that we
10084 can handle VOIDmode if OP0 is a COMPARE or a comparison
10087 if (GET_MODE_CLASS (mode) != MODE_INT
10088 && ! (mode == VOIDmode
10089 && (GET_CODE (op0) == COMPARE
10090 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10093 /* Get the constant we are comparing against and turn off all bits
10094 not on in our mode. */
10095 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10097 /* If we are comparing against a constant power of two and the value
10098 being compared can only have that single bit nonzero (e.g., it was
10099 `and'ed with that bit), we can replace this with a comparison
10102 && (code == EQ || code == NE || code == GE || code == GEU
10103 || code == LT || code == LTU)
10104 && mode_width <= HOST_BITS_PER_WIDE_INT
10105 && exact_log2 (const_op) >= 0
10106 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10108 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10109 op1 = const0_rtx, const_op = 0;
10112 /* Similarly, if we are comparing a value known to be either -1 or
10113 0 with -1, change it to the opposite comparison against zero. */
10116 && (code == EQ || code == NE || code == GT || code == LE
10117 || code == GEU || code == LTU)
10118 && num_sign_bit_copies (op0, mode) == mode_width)
10120 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10121 op1 = const0_rtx, const_op = 0;
10124 /* Do some canonicalizations based on the comparison code. We prefer
10125 comparisons against zero and then prefer equality comparisons.
10126 If we can reduce the size of a constant, we will do that too. */
10131 /* < C is equivalent to <= (C - 1) */
10135 op1 = GEN_INT (const_op);
10137 /* ... fall through to LE case below. */
10143 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10147 op1 = GEN_INT (const_op);
10151 /* If we are doing a <= 0 comparison on a value known to have
10152 a zero sign bit, we can replace this with == 0. */
10153 else if (const_op == 0
10154 && mode_width <= HOST_BITS_PER_WIDE_INT
10155 && (nonzero_bits (op0, mode)
10156 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10161 /* >= C is equivalent to > (C - 1). */
10165 op1 = GEN_INT (const_op);
10167 /* ... fall through to GT below. */
10173 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
10177 op1 = GEN_INT (const_op);
10181 /* If we are doing a > 0 comparison on a value known to have
10182 a zero sign bit, we can replace this with != 0. */
10183 else if (const_op == 0
10184 && mode_width <= HOST_BITS_PER_WIDE_INT
10185 && (nonzero_bits (op0, mode)
10186 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10191 /* < C is equivalent to <= (C - 1). */
10195 op1 = GEN_INT (const_op);
10197 /* ... fall through ... */
10200 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10201 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10202 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10204 const_op = 0, op1 = const0_rtx;
10212 /* unsigned <= 0 is equivalent to == 0 */
10216 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10217 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10218 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10220 const_op = 0, op1 = const0_rtx;
10226 /* >= C is equivalent to < (C - 1). */
10230 op1 = GEN_INT (const_op);
10232 /* ... fall through ... */
10235 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10236 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10237 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10239 const_op = 0, op1 = const0_rtx;
10247 /* unsigned > 0 is equivalent to != 0 */
10251 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10252 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10253 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10255 const_op = 0, op1 = const0_rtx;
10264 /* Compute some predicates to simplify code below. */
10266 equality_comparison_p = (code == EQ || code == NE);
10267 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10268 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10271 /* If this is a sign bit comparison and we can do arithmetic in
10272 MODE, say that we will only be needing the sign bit of OP0. */
10273 if (sign_bit_comparison_p
10274 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10275 op0 = force_to_mode (op0, mode,
10277 << (GET_MODE_BITSIZE (mode) - 1)),
10280 /* Now try cases based on the opcode of OP0. If none of the cases
10281 does a "continue", we exit this loop immediately after the
10284 switch (GET_CODE (op0))
10287 /* If we are extracting a single bit from a variable position in
10288 a constant that has only a single bit set and are comparing it
10289 with zero, we can convert this into an equality comparison
10290 between the position and the location of the single bit. */
10292 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10293 && XEXP (op0, 1) == const1_rtx
10294 && equality_comparison_p && const_op == 0
10295 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10297 if (BITS_BIG_ENDIAN)
10300 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10301 if (mode == VOIDmode)
10303 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10305 i = BITS_PER_WORD - 1 - i;
10309 op0 = XEXP (op0, 2);
10313 /* Result is nonzero iff shift count is equal to I. */
10314 code = reverse_condition (code);
10318 /* ... fall through ... */
10321 tem = expand_compound_operation (op0);
10330 /* If testing for equality, we can take the NOT of the constant. */
10331 if (equality_comparison_p
10332 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10334 op0 = XEXP (op0, 0);
10339 /* If just looking at the sign bit, reverse the sense of the
10341 if (sign_bit_comparison_p)
10343 op0 = XEXP (op0, 0);
10344 code = (code == GE ? LT : GE);
10350 /* If testing for equality, we can take the NEG of the constant. */
10351 if (equality_comparison_p
10352 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10354 op0 = XEXP (op0, 0);
10359 /* The remaining cases only apply to comparisons with zero. */
10363 /* When X is ABS or is known positive,
10364 (neg X) is < 0 if and only if X != 0. */
10366 if (sign_bit_comparison_p
10367 && (GET_CODE (XEXP (op0, 0)) == ABS
10368 || (mode_width <= HOST_BITS_PER_WIDE_INT
10369 && (nonzero_bits (XEXP (op0, 0), mode)
10370 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10372 op0 = XEXP (op0, 0);
10373 code = (code == LT ? NE : EQ);
10377 /* If we have NEG of something whose two high-order bits are the
10378 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10379 if (num_sign_bit_copies (op0, mode) >= 2)
10381 op0 = XEXP (op0, 0);
10382 code = swap_condition (code);
10388 /* If we are testing equality and our count is a constant, we
10389 can perform the inverse operation on our RHS. */
10390 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10391 && (tem = simplify_binary_operation (ROTATERT, mode,
10392 op1, XEXP (op0, 1))) != 0)
10394 op0 = XEXP (op0, 0);
10399 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10400 a particular bit. Convert it to an AND of a constant of that
10401 bit. This will be converted into a ZERO_EXTRACT. */
10402 if (const_op == 0 && sign_bit_comparison_p
10403 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10404 && mode_width <= HOST_BITS_PER_WIDE_INT)
10406 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10409 - INTVAL (XEXP (op0, 1)))));
10410 code = (code == LT ? NE : EQ);
10414 /* ... fall through ... */
10417 /* ABS is ignorable inside an equality comparison with zero. */
10418 if (const_op == 0 && equality_comparison_p)
10420 op0 = XEXP (op0, 0);
10427 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10428 to (compare FOO CONST) if CONST fits in FOO's mode and we
10429 are either testing inequality or have an unsigned comparison
10430 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10431 if (! unsigned_comparison_p
10432 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10433 <= HOST_BITS_PER_WIDE_INT)
10434 && ((unsigned HOST_WIDE_INT) const_op
10435 < (((unsigned HOST_WIDE_INT) 1
10436 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10438 op0 = XEXP (op0, 0);
10444 /* Check for the case where we are comparing A - C1 with C2,
10445 both constants are smaller than 1/2 the maximum positive
10446 value in MODE, and the comparison is equality or unsigned.
10447 In that case, if A is either zero-extended to MODE or has
10448 sufficient sign bits so that the high-order bit in MODE
10449 is a copy of the sign in the inner mode, we can prove that it is
10450 safe to do the operation in the wider mode. This simplifies
10451 many range checks. */
10453 if (mode_width <= HOST_BITS_PER_WIDE_INT
10454 && subreg_lowpart_p (op0)
10455 && GET_CODE (SUBREG_REG (op0)) == PLUS
10456 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10457 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10458 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10459 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10460 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10461 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10462 GET_MODE (SUBREG_REG (op0)))
10463 & ~ GET_MODE_MASK (mode))
10464 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10465 GET_MODE (SUBREG_REG (op0)))
10466 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10467 - GET_MODE_BITSIZE (mode)))))
10469 op0 = SUBREG_REG (op0);
10473 /* If the inner mode is narrower and we are extracting the low part,
10474 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10475 if (subreg_lowpart_p (op0)
10476 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10477 /* Fall through */ ;
10481 /* ... fall through ... */
10484 if ((unsigned_comparison_p || equality_comparison_p)
10485 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10486 <= HOST_BITS_PER_WIDE_INT)
10487 && ((unsigned HOST_WIDE_INT) const_op
10488 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10490 op0 = XEXP (op0, 0);
10496 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10497 this for equality comparisons due to pathological cases involving
10499 if (equality_comparison_p
10500 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10501 op1, XEXP (op0, 1))))
10503 op0 = XEXP (op0, 0);
10508 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10509 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10510 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10512 op0 = XEXP (XEXP (op0, 0), 0);
10513 code = (code == LT ? EQ : NE);
10519 /* We used to optimize signed comparisons against zero, but that
10520 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10521 arrive here as equality comparisons, or (GEU, LTU) are
10522 optimized away. No need to special-case them. */
10524 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10525 (eq B (minus A C)), whichever simplifies. We can only do
10526 this for equality comparisons due to pathological cases involving
10528 if (equality_comparison_p
10529 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10530 XEXP (op0, 1), op1)))
10532 op0 = XEXP (op0, 0);
10537 if (equality_comparison_p
10538 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10539 XEXP (op0, 0), op1)))
10541 op0 = XEXP (op0, 1);
10546 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10547 of bits in X minus 1, is one iff X > 0. */
10548 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10549 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10550 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10551 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10553 op0 = XEXP (op0, 1);
10554 code = (code == GE ? LE : GT);
10560 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10561 if C is zero or B is a constant. */
10562 if (equality_comparison_p
10563 && 0 != (tem = simplify_binary_operation (XOR, mode,
10564 XEXP (op0, 1), op1)))
10566 op0 = XEXP (op0, 0);
10573 case LT: case LTU: case LE: case LEU:
10574 case GT: case GTU: case GE: case GEU:
10575 /* We can't do anything if OP0 is a condition code value, rather
10576 than an actual data value. */
10579 || XEXP (op0, 0) == cc0_rtx
10581 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10584 /* Get the two operands being compared. */
10585 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10586 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10588 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10590 /* Check for the cases where we simply want the result of the
10591 earlier test or the opposite of that result. */
10593 || (code == EQ && reversible_comparison_p (op0))
10594 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10595 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10596 && (STORE_FLAG_VALUE
10597 & (((HOST_WIDE_INT) 1
10598 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10600 || (code == GE && reversible_comparison_p (op0)))))
10602 code = (code == LT || code == NE
10603 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10604 op0 = tem, op1 = tem1;
10610 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10612 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10613 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10614 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10616 op0 = XEXP (op0, 1);
10617 code = (code == GE ? GT : LE);
10623 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10624 will be converted to a ZERO_EXTRACT later. */
10625 if (const_op == 0 && equality_comparison_p
10626 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10627 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10629 op0 = simplify_and_const_int
10630 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10632 XEXP (XEXP (op0, 0), 1)),
10633 (HOST_WIDE_INT) 1);
10637 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10638 zero and X is a comparison and C1 and C2 describe only bits set
10639 in STORE_FLAG_VALUE, we can compare with X. */
10640 if (const_op == 0 && equality_comparison_p
10641 && mode_width <= HOST_BITS_PER_WIDE_INT
10642 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10643 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10644 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10645 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10646 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10648 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10649 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10650 if ((~ STORE_FLAG_VALUE & mask) == 0
10651 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10652 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10653 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10655 op0 = XEXP (XEXP (op0, 0), 0);
10660 /* If we are doing an equality comparison of an AND of a bit equal
10661 to the sign bit, replace this with a LT or GE comparison of
10662 the underlying value. */
10663 if (equality_comparison_p
10665 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10666 && mode_width <= HOST_BITS_PER_WIDE_INT
10667 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10668 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10670 op0 = XEXP (op0, 0);
10671 code = (code == EQ ? GE : LT);
10675 /* If this AND operation is really a ZERO_EXTEND from a narrower
10676 mode, the constant fits within that mode, and this is either an
10677 equality or unsigned comparison, try to do this comparison in
10678 the narrower mode. */
10679 if ((equality_comparison_p || unsigned_comparison_p)
10680 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10681 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10682 & GET_MODE_MASK (mode))
10684 && const_op >> i == 0
10685 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10687 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10691 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10692 in both M1 and M2 and the SUBREG is either paradoxical or
10693 represents the low part, permute the SUBREG and the AND and
10695 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10697 #ifdef WORD_REGISTER_OPERATIONS
10699 > (GET_MODE_BITSIZE
10700 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10701 && mode_width <= BITS_PER_WORD)
10704 <= (GET_MODE_BITSIZE
10705 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10706 && subreg_lowpart_p (XEXP (op0, 0))))
10707 #ifndef WORD_REGISTER_OPERATIONS
10708 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10709 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10710 As originally written the upper bits have a defined value
10711 due to the AND operation. However, if we commute the AND
10712 inside the SUBREG then they no longer have defined values
10713 and the meaning of the code has been changed. */
10714 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10715 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10717 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10718 && mode_width <= HOST_BITS_PER_WIDE_INT
10719 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10720 <= HOST_BITS_PER_WIDE_INT)
10721 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10722 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10723 & INTVAL (XEXP (op0, 1)))
10724 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10725 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10726 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10730 = gen_lowpart_for_combine
10732 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10733 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10740 /* If we have (compare (ashift FOO N) (const_int C)) and
10741 the high order N bits of FOO (N+1 if an inequality comparison)
10742 are known to be zero, we can do this by comparing FOO with C
10743 shifted right N bits so long as the low-order N bits of C are
10745 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10746 && INTVAL (XEXP (op0, 1)) >= 0
10747 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10748 < HOST_BITS_PER_WIDE_INT)
10750 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10751 && mode_width <= HOST_BITS_PER_WIDE_INT
10752 && (nonzero_bits (XEXP (op0, 0), mode)
10753 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10754 + ! equality_comparison_p))) == 0)
10756 /* We must perform a logical shift, not an arithmetic one,
10757 as we want the top N bits of C to be zero. */
10758 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10760 temp >>= INTVAL (XEXP (op0, 1));
10761 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10762 op0 = XEXP (op0, 0);
10766 /* If we are doing a sign bit comparison, it means we are testing
10767 a particular bit. Convert it to the appropriate AND. */
10768 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10769 && mode_width <= HOST_BITS_PER_WIDE_INT)
10771 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10774 - INTVAL (XEXP (op0, 1)))));
10775 code = (code == LT ? NE : EQ);
10779 /* If this an equality comparison with zero and we are shifting
10780 the low bit to the sign bit, we can convert this to an AND of the
10782 if (const_op == 0 && equality_comparison_p
10783 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10784 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10786 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10787 (HOST_WIDE_INT) 1);
10793 /* If this is an equality comparison with zero, we can do this
10794 as a logical shift, which might be much simpler. */
10795 if (equality_comparison_p && const_op == 0
10796 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10798 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10800 INTVAL (XEXP (op0, 1)));
10804 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10805 do the comparison in a narrower mode. */
10806 if (! unsigned_comparison_p
10807 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10808 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10809 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10810 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10811 MODE_INT, 1)) != BLKmode
10812 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10813 || ((unsigned HOST_WIDE_INT) - const_op
10814 <= GET_MODE_MASK (tmode))))
10816 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10820 /* Likewise if OP0 is a PLUS of a sign extension with a
10821 constant, which is usually represented with the PLUS
10822 between the shifts. */
10823 if (! unsigned_comparison_p
10824 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10825 && GET_CODE (XEXP (op0, 0)) == PLUS
10826 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10827 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10828 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10829 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10830 MODE_INT, 1)) != BLKmode
10831 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10832 || ((unsigned HOST_WIDE_INT) - const_op
10833 <= GET_MODE_MASK (tmode))))
10835 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10836 rtx add_const = XEXP (XEXP (op0, 0), 1);
10837 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10840 op0 = gen_binary (PLUS, tmode,
10841 gen_lowpart_for_combine (tmode, inner),
10846 /* ... fall through ... */
10848 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10849 the low order N bits of FOO are known to be zero, we can do this
10850 by comparing FOO with C shifted left N bits so long as no
10851 overflow occurs. */
10852 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10853 && INTVAL (XEXP (op0, 1)) >= 0
10854 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10855 && mode_width <= HOST_BITS_PER_WIDE_INT
10856 && (nonzero_bits (XEXP (op0, 0), mode)
10857 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10859 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10862 const_op <<= INTVAL (XEXP (op0, 1));
10863 op1 = GEN_INT (const_op);
10864 op0 = XEXP (op0, 0);
10868 /* If we are using this shift to extract just the sign bit, we
10869 can replace this with an LT or GE comparison. */
10871 && (equality_comparison_p || sign_bit_comparison_p)
10872 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10873 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10875 op0 = XEXP (op0, 0);
10876 code = (code == NE || code == GT ? LT : GE);
10888 /* Now make any compound operations involved in this comparison. Then,
10889 check for an outmost SUBREG on OP0 that is not doing anything or is
10890 paradoxical. The latter case can only occur when it is known that the
10891 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10892 We can never remove a SUBREG for a non-equality comparison because the
10893 sign bit is in a different place in the underlying object. */
10895 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10896 op1 = make_compound_operation (op1, SET);
10898 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10899 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10900 && (code == NE || code == EQ)
10901 && ((GET_MODE_SIZE (GET_MODE (op0))
10902 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10904 op0 = SUBREG_REG (op0);
10905 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10908 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10909 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10910 && (code == NE || code == EQ)
10911 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10912 <= HOST_BITS_PER_WIDE_INT)
10913 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10914 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10915 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10917 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10918 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10919 op0 = SUBREG_REG (op0), op1 = tem;
10921 /* We now do the opposite procedure: Some machines don't have compare
10922 insns in all modes. If OP0's mode is an integer mode smaller than a
10923 word and we can't do a compare in that mode, see if there is a larger
10924 mode for which we can do the compare. There are a number of cases in
10925 which we can use the wider mode. */
10927 mode = GET_MODE (op0);
10928 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10929 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10930 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10931 for (tmode = GET_MODE_WIDER_MODE (mode);
10933 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10934 tmode = GET_MODE_WIDER_MODE (tmode))
10935 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10937 /* If the only nonzero bits in OP0 and OP1 are those in the
10938 narrower mode and this is an equality or unsigned comparison,
10939 we can use the wider mode. Similarly for sign-extended
10940 values, in which case it is true for all comparisons. */
10941 if (((code == EQ || code == NE
10942 || code == GEU || code == GTU || code == LEU || code == LTU)
10943 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10944 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10945 || ((num_sign_bit_copies (op0, tmode)
10946 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10947 && (num_sign_bit_copies (op1, tmode)
10948 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10950 /* If OP0 is an AND and we don't have an AND in MODE either,
10951 make a new AND in the proper mode. */
10952 if (GET_CODE (op0) == AND
10953 && (add_optab->handlers[(int) mode].insn_code
10954 == CODE_FOR_nothing))
10955 op0 = gen_binary (AND, tmode,
10956 gen_lowpart_for_combine (tmode,
10958 gen_lowpart_for_combine (tmode,
10961 op0 = gen_lowpart_for_combine (tmode, op0);
10962 op1 = gen_lowpart_for_combine (tmode, op1);
10966 /* If this is a test for negative, we can make an explicit
10967 test of the sign bit. */
10969 if (op1 == const0_rtx && (code == LT || code == GE)
10970 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10972 op0 = gen_binary (AND, tmode,
10973 gen_lowpart_for_combine (tmode, op0),
10974 GEN_INT ((HOST_WIDE_INT) 1
10975 << (GET_MODE_BITSIZE (mode) - 1)));
10976 code = (code == LT) ? NE : EQ;
10981 #ifdef CANONICALIZE_COMPARISON
10982 /* If this machine only supports a subset of valid comparisons, see if we
10983 can convert an unsupported one into a supported one. */
10984 CANONICALIZE_COMPARISON (code, op0, op1);
10993 /* Return 1 if we know that X, a comparison operation, is not operating
10994 on a floating-point value or is EQ or NE, meaning that we can safely
10998 reversible_comparison_p (x)
11001 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
11003 || GET_CODE (x) == NE || GET_CODE (x) == EQ
11004 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
11007 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
11010 case MODE_PARTIAL_INT:
11011 case MODE_COMPLEX_INT:
11015 /* If the mode of the condition codes tells us that this is safe,
11016 we need look no further. */
11017 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
11020 /* Otherwise try and find where the condition codes were last set and
11022 x = get_last_value (XEXP (x, 0));
11023 return (x && GET_CODE (x) == COMPARE
11024 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
11031 /* Utility function for following routine. Called when X is part of a value
11032 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11033 for each register mentioned. Similar to mention_regs in cse.c */
11036 update_table_tick (x)
11039 register enum rtx_code code = GET_CODE (x);
11040 register const char *fmt = GET_RTX_FORMAT (code);
11045 unsigned int regno = REGNO (x);
11046 unsigned int endregno
11047 = regno + (regno < FIRST_PSEUDO_REGISTER
11048 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11051 for (r = regno; r < endregno; r++)
11052 reg_last_set_table_tick[r] = label_tick;
11057 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11058 /* Note that we can't have an "E" in values stored; see
11059 get_last_value_validate. */
11061 update_table_tick (XEXP (x, i));
11064 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11065 are saying that the register is clobbered and we no longer know its
11066 value. If INSN is zero, don't update reg_last_set; this is only permitted
11067 with VALUE also zero and is used to invalidate the register. */
11070 record_value_for_reg (reg, insn, value)
11075 unsigned int regno = REGNO (reg);
11076 unsigned int endregno
11077 = regno + (regno < FIRST_PSEUDO_REGISTER
11078 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11081 /* If VALUE contains REG and we have a previous value for REG, substitute
11082 the previous value. */
11083 if (value && insn && reg_overlap_mentioned_p (reg, value))
11087 /* Set things up so get_last_value is allowed to see anything set up to
11089 subst_low_cuid = INSN_CUID (insn);
11090 tem = get_last_value (reg);
11092 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11093 it isn't going to be useful and will take a lot of time to process,
11094 so just use the CLOBBER. */
11098 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11099 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11100 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11101 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11102 tem = XEXP (tem, 0);
11104 value = replace_rtx (copy_rtx (value), reg, tem);
11108 /* For each register modified, show we don't know its value, that
11109 we don't know about its bitwise content, that its value has been
11110 updated, and that we don't know the location of the death of the
11112 for (i = regno; i < endregno; i++)
11115 reg_last_set[i] = insn;
11117 reg_last_set_value[i] = 0;
11118 reg_last_set_mode[i] = 0;
11119 reg_last_set_nonzero_bits[i] = 0;
11120 reg_last_set_sign_bit_copies[i] = 0;
11121 reg_last_death[i] = 0;
11124 /* Mark registers that are being referenced in this value. */
11126 update_table_tick (value);
11128 /* Now update the status of each register being set.
11129 If someone is using this register in this block, set this register
11130 to invalid since we will get confused between the two lives in this
11131 basic block. This makes using this register always invalid. In cse, we
11132 scan the table to invalidate all entries using this register, but this
11133 is too much work for us. */
11135 for (i = regno; i < endregno; i++)
11137 reg_last_set_label[i] = label_tick;
11138 if (value && reg_last_set_table_tick[i] == label_tick)
11139 reg_last_set_invalid[i] = 1;
11141 reg_last_set_invalid[i] = 0;
11144 /* The value being assigned might refer to X (like in "x++;"). In that
11145 case, we must replace it with (clobber (const_int 0)) to prevent
11147 if (value && ! get_last_value_validate (&value, insn,
11148 reg_last_set_label[regno], 0))
11150 value = copy_rtx (value);
11151 if (! get_last_value_validate (&value, insn,
11152 reg_last_set_label[regno], 1))
11156 /* For the main register being modified, update the value, the mode, the
11157 nonzero bits, and the number of sign bit copies. */
11159 reg_last_set_value[regno] = value;
11163 subst_low_cuid = INSN_CUID (insn);
11164 reg_last_set_mode[regno] = GET_MODE (reg);
11165 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11166 reg_last_set_sign_bit_copies[regno]
11167 = num_sign_bit_copies (value, GET_MODE (reg));
11171 /* Called via note_stores from record_dead_and_set_regs to handle one
11172 SET or CLOBBER in an insn. DATA is the instruction in which the
11173 set is occurring. */
11176 record_dead_and_set_regs_1 (dest, setter, data)
11180 rtx record_dead_insn = (rtx) data;
11182 if (GET_CODE (dest) == SUBREG)
11183 dest = SUBREG_REG (dest);
11185 if (GET_CODE (dest) == REG)
11187 /* If we are setting the whole register, we know its value. Otherwise
11188 show that we don't know the value. We can handle SUBREG in
11190 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11191 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11192 else if (GET_CODE (setter) == SET
11193 && GET_CODE (SET_DEST (setter)) == SUBREG
11194 && SUBREG_REG (SET_DEST (setter)) == dest
11195 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11196 && subreg_lowpart_p (SET_DEST (setter)))
11197 record_value_for_reg (dest, record_dead_insn,
11198 gen_lowpart_for_combine (GET_MODE (dest),
11199 SET_SRC (setter)));
11201 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11203 else if (GET_CODE (dest) == MEM
11204 /* Ignore pushes, they clobber nothing. */
11205 && ! push_operand (dest, GET_MODE (dest)))
11206 mem_last_set = INSN_CUID (record_dead_insn);
11209 /* Update the records of when each REG was most recently set or killed
11210 for the things done by INSN. This is the last thing done in processing
11211 INSN in the combiner loop.
11213 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11214 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11215 and also the similar information mem_last_set (which insn most recently
11216 modified memory) and last_call_cuid (which insn was the most recent
11217 subroutine call). */
11220 record_dead_and_set_regs (insn)
11226 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11228 if (REG_NOTE_KIND (link) == REG_DEAD
11229 && GET_CODE (XEXP (link, 0)) == REG)
11231 unsigned int regno = REGNO (XEXP (link, 0));
11232 unsigned int endregno
11233 = regno + (regno < FIRST_PSEUDO_REGISTER
11234 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11237 for (i = regno; i < endregno; i++)
11238 reg_last_death[i] = insn;
11240 else if (REG_NOTE_KIND (link) == REG_INC)
11241 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11244 if (GET_CODE (insn) == CALL_INSN)
11246 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11247 if (call_used_regs[i])
11249 reg_last_set_value[i] = 0;
11250 reg_last_set_mode[i] = 0;
11251 reg_last_set_nonzero_bits[i] = 0;
11252 reg_last_set_sign_bit_copies[i] = 0;
11253 reg_last_death[i] = 0;
11256 last_call_cuid = mem_last_set = INSN_CUID (insn);
11259 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11262 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11263 register present in the SUBREG, so for each such SUBREG go back and
11264 adjust nonzero and sign bit information of the registers that are
11265 known to have some zero/sign bits set.
11267 This is needed because when combine blows the SUBREGs away, the
11268 information on zero/sign bits is lost and further combines can be
11269 missed because of that. */
11272 record_promoted_value (insn, subreg)
11277 unsigned int regno = REGNO (SUBREG_REG (subreg));
11278 enum machine_mode mode = GET_MODE (subreg);
11280 if (GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT)
11283 for (links = LOG_LINKS (insn); links; )
11285 insn = XEXP (links, 0);
11286 set = single_set (insn);
11288 if (! set || GET_CODE (SET_DEST (set)) != REG
11289 || REGNO (SET_DEST (set)) != regno
11290 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11292 links = XEXP (links, 1);
11296 if (reg_last_set [regno] == insn)
11298 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11299 reg_last_set_nonzero_bits [regno] &= GET_MODE_MASK (mode);
11302 if (GET_CODE (SET_SRC (set)) == REG)
11304 regno = REGNO (SET_SRC (set));
11305 links = LOG_LINKS (insn);
11312 /* Scan X for promoted SUBREGs. For each one found,
11313 note what it implies to the registers used in it. */
11316 check_promoted_subreg (insn, x)
11320 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11321 && GET_CODE (SUBREG_REG (x)) == REG)
11322 record_promoted_value (insn, x);
11325 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11328 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11329 switch (format [i])
11332 check_promoted_subreg (insn, XEXP (x, i));
11336 if (XVEC (x, i) != 0)
11337 for (j = 0; j < XVECLEN (x, i); j++)
11338 check_promoted_subreg (insn, XVECEXP (x, i, j));
11344 /* Utility routine for the following function. Verify that all the registers
11345 mentioned in *LOC are valid when *LOC was part of a value set when
11346 label_tick == TICK. Return 0 if some are not.
11348 If REPLACE is non-zero, replace the invalid reference with
11349 (clobber (const_int 0)) and return 1. This replacement is useful because
11350 we often can get useful information about the form of a value (e.g., if
11351 it was produced by a shift that always produces -1 or 0) even though
11352 we don't know exactly what registers it was produced from. */
11355 get_last_value_validate (loc, insn, tick, replace)
11362 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11363 int len = GET_RTX_LENGTH (GET_CODE (x));
11366 if (GET_CODE (x) == REG)
11368 unsigned int regno = REGNO (x);
11369 unsigned int endregno
11370 = regno + (regno < FIRST_PSEUDO_REGISTER
11371 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11374 for (j = regno; j < endregno; j++)
11375 if (reg_last_set_invalid[j]
11376 /* If this is a pseudo-register that was only set once and not
11377 live at the beginning of the function, it is always valid. */
11378 || (! (regno >= FIRST_PSEUDO_REGISTER
11379 && REG_N_SETS (regno) == 1
11380 && (! REGNO_REG_SET_P
11381 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11382 && reg_last_set_label[j] > tick))
11385 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11391 /* If this is a memory reference, make sure that there were
11392 no stores after it that might have clobbered the value. We don't
11393 have alias info, so we assume any store invalidates it. */
11394 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11395 && INSN_CUID (insn) <= mem_last_set)
11398 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11402 for (i = 0; i < len; i++)
11404 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11405 /* Don't bother with these. They shouldn't occur anyway. */
11409 /* If we haven't found a reason for it to be invalid, it is valid. */
11413 /* Get the last value assigned to X, if known. Some registers
11414 in the value may be replaced with (clobber (const_int 0)) if their value
11415 is known longer known reliably. */
11421 unsigned int regno;
11424 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11425 then convert it to the desired mode. If this is a paradoxical SUBREG,
11426 we cannot predict what values the "extra" bits might have. */
11427 if (GET_CODE (x) == SUBREG
11428 && subreg_lowpart_p (x)
11429 && (GET_MODE_SIZE (GET_MODE (x))
11430 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11431 && (value = get_last_value (SUBREG_REG (x))) != 0)
11432 return gen_lowpart_for_combine (GET_MODE (x), value);
11434 if (GET_CODE (x) != REG)
11438 value = reg_last_set_value[regno];
11440 /* If we don't have a value, or if it isn't for this basic block and
11441 it's either a hard register, set more than once, or it's a live
11442 at the beginning of the function, return 0.
11444 Because if it's not live at the beginnning of the function then the reg
11445 is always set before being used (is never used without being set).
11446 And, if it's set only once, and it's always set before use, then all
11447 uses must have the same last value, even if it's not from this basic
11451 || (reg_last_set_label[regno] != label_tick
11452 && (regno < FIRST_PSEUDO_REGISTER
11453 || REG_N_SETS (regno) != 1
11454 || (REGNO_REG_SET_P
11455 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11458 /* If the value was set in a later insn than the ones we are processing,
11459 we can't use it even if the register was only set once. */
11460 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11463 /* If the value has all its registers valid, return it. */
11464 if (get_last_value_validate (&value, reg_last_set[regno],
11465 reg_last_set_label[regno], 0))
11468 /* Otherwise, make a copy and replace any invalid register with
11469 (clobber (const_int 0)). If that fails for some reason, return 0. */
11471 value = copy_rtx (value);
11472 if (get_last_value_validate (&value, reg_last_set[regno],
11473 reg_last_set_label[regno], 1))
11479 /* Return nonzero if expression X refers to a REG or to memory
11480 that is set in an instruction more recent than FROM_CUID. */
11483 use_crosses_set_p (x, from_cuid)
11487 register const char *fmt;
11489 register enum rtx_code code = GET_CODE (x);
11493 unsigned int regno = REGNO (x);
11494 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11495 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11497 #ifdef PUSH_ROUNDING
11498 /* Don't allow uses of the stack pointer to be moved,
11499 because we don't know whether the move crosses a push insn. */
11500 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11503 for (; regno < endreg; regno++)
11504 if (reg_last_set[regno]
11505 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11510 if (code == MEM && mem_last_set > from_cuid)
11513 fmt = GET_RTX_FORMAT (code);
11515 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11520 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11521 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11524 else if (fmt[i] == 'e'
11525 && use_crosses_set_p (XEXP (x, i), from_cuid))
11531 /* Define three variables used for communication between the following
11534 static unsigned int reg_dead_regno, reg_dead_endregno;
11535 static int reg_dead_flag;
11537 /* Function called via note_stores from reg_dead_at_p.
11539 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11540 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11543 reg_dead_at_p_1 (dest, x, data)
11546 void *data ATTRIBUTE_UNUSED;
11548 unsigned int regno, endregno;
11550 if (GET_CODE (dest) != REG)
11553 regno = REGNO (dest);
11554 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11555 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11557 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11558 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11561 /* Return non-zero if REG is known to be dead at INSN.
11563 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11564 referencing REG, it is dead. If we hit a SET referencing REG, it is
11565 live. Otherwise, see if it is live or dead at the start of the basic
11566 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11567 must be assumed to be always live. */
11570 reg_dead_at_p (reg, insn)
11577 /* Set variables for reg_dead_at_p_1. */
11578 reg_dead_regno = REGNO (reg);
11579 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11580 ? HARD_REGNO_NREGS (reg_dead_regno,
11586 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11587 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11589 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11590 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11594 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11595 beginning of function. */
11596 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11597 insn = prev_nonnote_insn (insn))
11599 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11601 return reg_dead_flag == 1 ? 1 : 0;
11603 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11607 /* Get the basic block number that we were in. */
11612 for (block = 0; block < n_basic_blocks; block++)
11613 if (insn == BLOCK_HEAD (block))
11616 if (block == n_basic_blocks)
11620 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11621 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11627 /* Note hard registers in X that are used. This code is similar to
11628 that in flow.c, but much simpler since we don't care about pseudos. */
11631 mark_used_regs_combine (x)
11634 RTX_CODE code = GET_CODE (x);
11635 unsigned int regno;
11647 case ADDR_DIFF_VEC:
11650 /* CC0 must die in the insn after it is set, so we don't need to take
11651 special note of it here. */
11657 /* If we are clobbering a MEM, mark any hard registers inside the
11658 address as used. */
11659 if (GET_CODE (XEXP (x, 0)) == MEM)
11660 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11665 /* A hard reg in a wide mode may really be multiple registers.
11666 If so, mark all of them just like the first. */
11667 if (regno < FIRST_PSEUDO_REGISTER)
11669 unsigned int endregno, r;
11671 /* None of this applies to the stack, frame or arg pointers */
11672 if (regno == STACK_POINTER_REGNUM
11673 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11674 || regno == HARD_FRAME_POINTER_REGNUM
11676 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11677 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11679 || regno == FRAME_POINTER_REGNUM)
11682 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11683 for (r = regno; r < endregno; r++)
11684 SET_HARD_REG_BIT (newpat_used_regs, r);
11690 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11692 register rtx testreg = SET_DEST (x);
11694 while (GET_CODE (testreg) == SUBREG
11695 || GET_CODE (testreg) == ZERO_EXTRACT
11696 || GET_CODE (testreg) == SIGN_EXTRACT
11697 || GET_CODE (testreg) == STRICT_LOW_PART)
11698 testreg = XEXP (testreg, 0);
11700 if (GET_CODE (testreg) == MEM)
11701 mark_used_regs_combine (XEXP (testreg, 0));
11703 mark_used_regs_combine (SET_SRC (x));
11711 /* Recursively scan the operands of this expression. */
11714 register const char *fmt = GET_RTX_FORMAT (code);
11716 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11719 mark_used_regs_combine (XEXP (x, i));
11720 else if (fmt[i] == 'E')
11724 for (j = 0; j < XVECLEN (x, i); j++)
11725 mark_used_regs_combine (XVECEXP (x, i, j));
11732 /* Remove register number REGNO from the dead registers list of INSN.
11734 Return the note used to record the death, if there was one. */
11737 remove_death (regno, insn)
11738 unsigned int regno;
11741 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11745 REG_N_DEATHS (regno)--;
11746 remove_note (insn, note);
11752 /* For each register (hardware or pseudo) used within expression X, if its
11753 death is in an instruction with cuid between FROM_CUID (inclusive) and
11754 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11755 list headed by PNOTES.
11757 That said, don't move registers killed by maybe_kill_insn.
11759 This is done when X is being merged by combination into TO_INSN. These
11760 notes will then be distributed as needed. */
11763 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11765 rtx maybe_kill_insn;
11770 register const char *fmt;
11771 register int len, i;
11772 register enum rtx_code code = GET_CODE (x);
11776 unsigned int regno = REGNO (x);
11777 register rtx where_dead = reg_last_death[regno];
11778 register rtx before_dead, after_dead;
11780 /* Don't move the register if it gets killed in between from and to */
11781 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11782 && ! reg_referenced_p (x, maybe_kill_insn))
11785 /* WHERE_DEAD could be a USE insn made by combine, so first we
11786 make sure that we have insns with valid INSN_CUID values. */
11787 before_dead = where_dead;
11788 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11789 before_dead = PREV_INSN (before_dead);
11791 after_dead = where_dead;
11792 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11793 after_dead = NEXT_INSN (after_dead);
11795 if (before_dead && after_dead
11796 && INSN_CUID (before_dead) >= from_cuid
11797 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11798 || (where_dead != after_dead
11799 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11801 rtx note = remove_death (regno, where_dead);
11803 /* It is possible for the call above to return 0. This can occur
11804 when reg_last_death points to I2 or I1 that we combined with.
11805 In that case make a new note.
11807 We must also check for the case where X is a hard register
11808 and NOTE is a death note for a range of hard registers
11809 including X. In that case, we must put REG_DEAD notes for
11810 the remaining registers in place of NOTE. */
11812 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11813 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11814 > GET_MODE_SIZE (GET_MODE (x))))
11816 unsigned int deadregno = REGNO (XEXP (note, 0));
11817 unsigned int deadend
11818 = (deadregno + HARD_REGNO_NREGS (deadregno,
11819 GET_MODE (XEXP (note, 0))));
11820 unsigned int ourend
11821 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11824 for (i = deadregno; i < deadend; i++)
11825 if (i < regno || i >= ourend)
11826 REG_NOTES (where_dead)
11827 = gen_rtx_EXPR_LIST (REG_DEAD,
11828 gen_rtx_REG (reg_raw_mode[i], i),
11829 REG_NOTES (where_dead));
11832 /* If we didn't find any note, or if we found a REG_DEAD note that
11833 covers only part of the given reg, and we have a multi-reg hard
11834 register, then to be safe we must check for REG_DEAD notes
11835 for each register other than the first. They could have
11836 their own REG_DEAD notes lying around. */
11837 else if ((note == 0
11839 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11840 < GET_MODE_SIZE (GET_MODE (x)))))
11841 && regno < FIRST_PSEUDO_REGISTER
11842 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11844 unsigned int ourend
11845 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11846 unsigned int i, offset;
11850 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11854 for (i = regno + offset; i < ourend; i++)
11855 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11856 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11859 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11861 XEXP (note, 1) = *pnotes;
11865 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11867 REG_N_DEATHS (regno)++;
11873 else if (GET_CODE (x) == SET)
11875 rtx dest = SET_DEST (x);
11877 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11879 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11880 that accesses one word of a multi-word item, some
11881 piece of everything register in the expression is used by
11882 this insn, so remove any old death. */
11884 if (GET_CODE (dest) == ZERO_EXTRACT
11885 || GET_CODE (dest) == STRICT_LOW_PART
11886 || (GET_CODE (dest) == SUBREG
11887 && (((GET_MODE_SIZE (GET_MODE (dest))
11888 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11889 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11890 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11892 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11896 /* If this is some other SUBREG, we know it replaces the entire
11897 value, so use that as the destination. */
11898 if (GET_CODE (dest) == SUBREG)
11899 dest = SUBREG_REG (dest);
11901 /* If this is a MEM, adjust deaths of anything used in the address.
11902 For a REG (the only other possibility), the entire value is
11903 being replaced so the old value is not used in this insn. */
11905 if (GET_CODE (dest) == MEM)
11906 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11911 else if (GET_CODE (x) == CLOBBER)
11914 len = GET_RTX_LENGTH (code);
11915 fmt = GET_RTX_FORMAT (code);
11917 for (i = 0; i < len; i++)
11922 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11923 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11926 else if (fmt[i] == 'e')
11927 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11931 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11932 pattern of an insn. X must be a REG. */
11935 reg_bitfield_target_p (x, body)
11941 if (GET_CODE (body) == SET)
11943 rtx dest = SET_DEST (body);
11945 unsigned int regno, tregno, endregno, endtregno;
11947 if (GET_CODE (dest) == ZERO_EXTRACT)
11948 target = XEXP (dest, 0);
11949 else if (GET_CODE (dest) == STRICT_LOW_PART)
11950 target = SUBREG_REG (XEXP (dest, 0));
11954 if (GET_CODE (target) == SUBREG)
11955 target = SUBREG_REG (target);
11957 if (GET_CODE (target) != REG)
11960 tregno = REGNO (target), regno = REGNO (x);
11961 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11962 return target == x;
11964 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11965 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11967 return endregno > tregno && regno < endtregno;
11970 else if (GET_CODE (body) == PARALLEL)
11971 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11972 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11978 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11979 as appropriate. I3 and I2 are the insns resulting from the combination
11980 insns including FROM (I2 may be zero).
11982 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11983 not need REG_DEAD notes because they are being substituted for. This
11984 saves searching in the most common cases.
11986 Each note in the list is either ignored or placed on some insns, depending
11987 on the type of note. */
11990 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11994 rtx elim_i2, elim_i1;
11996 rtx note, next_note;
11999 for (note = notes; note; note = next_note)
12001 rtx place = 0, place2 = 0;
12003 /* If this NOTE references a pseudo register, ensure it references
12004 the latest copy of that register. */
12005 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12006 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12007 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12009 next_note = XEXP (note, 1);
12010 switch (REG_NOTE_KIND (note))
12013 case REG_EXEC_COUNT:
12014 /* Doesn't matter much where we put this, as long as it's somewhere.
12015 It is preferable to keep these notes on branches, which is most
12016 likely to be i3. */
12020 case REG_EH_REGION:
12021 case REG_EH_RETHROW:
12022 /* These notes must remain with the call. It should not be
12023 possible for both I2 and I3 to be a call. */
12024 if (GET_CODE (i3) == CALL_INSN)
12026 else if (i2 && GET_CODE (i2) == CALL_INSN)
12033 /* Any clobbers for i3 may still exist, and so we must process
12034 REG_UNUSED notes from that insn.
12036 Any clobbers from i2 or i1 can only exist if they were added by
12037 recog_for_combine. In that case, recog_for_combine created the
12038 necessary REG_UNUSED notes. Trying to keep any original
12039 REG_UNUSED notes from these insns can cause incorrect output
12040 if it is for the same register as the original i3 dest.
12041 In that case, we will notice that the register is set in i3,
12042 and then add a REG_UNUSED note for the destination of i3, which
12043 is wrong. However, it is possible to have REG_UNUSED notes from
12044 i2 or i1 for register which were both used and clobbered, so
12045 we keep notes from i2 or i1 if they will turn into REG_DEAD
12048 /* If this register is set or clobbered in I3, put the note there
12049 unless there is one already. */
12050 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12052 if (from_insn != i3)
12055 if (! (GET_CODE (XEXP (note, 0)) == REG
12056 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12057 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12060 /* Otherwise, if this register is used by I3, then this register
12061 now dies here, so we must put a REG_DEAD note here unless there
12063 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12064 && ! (GET_CODE (XEXP (note, 0)) == REG
12065 ? find_regno_note (i3, REG_DEAD,
12066 REGNO (XEXP (note, 0)))
12067 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12069 PUT_REG_NOTE_KIND (note, REG_DEAD);
12078 /* These notes say something about results of an insn. We can
12079 only support them if they used to be on I3 in which case they
12080 remain on I3. Otherwise they are ignored.
12082 If the note refers to an expression that is not a constant, we
12083 must also ignore the note since we cannot tell whether the
12084 equivalence is still true. It might be possible to do
12085 slightly better than this (we only have a problem if I2DEST
12086 or I1DEST is present in the expression), but it doesn't
12087 seem worth the trouble. */
12089 if (from_insn == i3
12090 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12095 case REG_NO_CONFLICT:
12096 /* These notes say something about how a register is used. They must
12097 be present on any use of the register in I2 or I3. */
12098 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12101 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12111 /* This can show up in several ways -- either directly in the
12112 pattern, or hidden off in the constant pool with (or without?)
12113 a REG_EQUAL note. */
12114 /* ??? Ignore the without-reg_equal-note problem for now. */
12115 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12116 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12117 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12118 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12122 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12123 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12124 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12125 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12135 /* It is too much trouble to try to see if this note is still
12136 correct in all situations. It is better to simply delete it. */
12140 /* If the insn previously containing this note still exists,
12141 put it back where it was. Otherwise move it to the previous
12142 insn. Adjust the corresponding REG_LIBCALL note. */
12143 if (GET_CODE (from_insn) != NOTE)
12147 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12148 place = prev_real_insn (from_insn);
12150 XEXP (tem, 0) = place;
12155 /* This is handled similarly to REG_RETVAL. */
12156 if (GET_CODE (from_insn) != NOTE)
12160 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12161 place = next_real_insn (from_insn);
12163 XEXP (tem, 0) = place;
12168 /* If the register is used as an input in I3, it dies there.
12169 Similarly for I2, if it is non-zero and adjacent to I3.
12171 If the register is not used as an input in either I3 or I2
12172 and it is not one of the registers we were supposed to eliminate,
12173 there are two possibilities. We might have a non-adjacent I2
12174 or we might have somehow eliminated an additional register
12175 from a computation. For example, we might have had A & B where
12176 we discover that B will always be zero. In this case we will
12177 eliminate the reference to A.
12179 In both cases, we must search to see if we can find a previous
12180 use of A and put the death note there. */
12183 && GET_CODE (from_insn) == CALL_INSN
12184 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12186 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12188 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12189 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12192 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12197 basic_block bb = BASIC_BLOCK (this_basic_block);
12199 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12201 if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
12203 if (tem == bb->head)
12208 /* If the register is being set at TEM, see if that is all
12209 TEM is doing. If so, delete TEM. Otherwise, make this
12210 into a REG_UNUSED note instead. */
12211 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12213 rtx set = single_set (tem);
12214 rtx inner_dest = 0;
12216 rtx cc0_setter = NULL_RTX;
12220 for (inner_dest = SET_DEST (set);
12221 GET_CODE (inner_dest) == STRICT_LOW_PART
12222 || GET_CODE (inner_dest) == SUBREG
12223 || GET_CODE (inner_dest) == ZERO_EXTRACT;
12224 inner_dest = XEXP (inner_dest, 0))
12227 /* Verify that it was the set, and not a clobber that
12228 modified the register.
12230 CC0 targets must be careful to maintain setter/user
12231 pairs. If we cannot delete the setter due to side
12232 effects, mark the user with an UNUSED note instead
12235 if (set != 0 && ! side_effects_p (SET_SRC (set))
12236 && rtx_equal_p (XEXP (note, 0), inner_dest)
12238 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12239 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12240 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12244 /* Move the notes and links of TEM elsewhere.
12245 This might delete other dead insns recursively.
12246 First set the pattern to something that won't use
12249 PATTERN (tem) = pc_rtx;
12251 distribute_notes (REG_NOTES (tem), tem, tem,
12252 NULL_RTX, NULL_RTX, NULL_RTX);
12253 distribute_links (LOG_LINKS (tem));
12255 PUT_CODE (tem, NOTE);
12256 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12257 NOTE_SOURCE_FILE (tem) = 0;
12260 /* Delete the setter too. */
12263 PATTERN (cc0_setter) = pc_rtx;
12265 distribute_notes (REG_NOTES (cc0_setter),
12266 cc0_setter, cc0_setter,
12267 NULL_RTX, NULL_RTX, NULL_RTX);
12268 distribute_links (LOG_LINKS (cc0_setter));
12270 PUT_CODE (cc0_setter, NOTE);
12271 NOTE_LINE_NUMBER (cc0_setter)
12272 = NOTE_INSN_DELETED;
12273 NOTE_SOURCE_FILE (cc0_setter) = 0;
12277 /* If the register is both set and used here, put the
12278 REG_DEAD note here, but place a REG_UNUSED note
12279 here too unless there already is one. */
12280 else if (reg_referenced_p (XEXP (note, 0),
12285 if (! find_regno_note (tem, REG_UNUSED,
12286 REGNO (XEXP (note, 0))))
12288 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12293 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12295 /* If there isn't already a REG_UNUSED note, put one
12297 if (! find_regno_note (tem, REG_UNUSED,
12298 REGNO (XEXP (note, 0))))
12303 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12304 || (GET_CODE (tem) == CALL_INSN
12305 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12309 /* If we are doing a 3->2 combination, and we have a
12310 register which formerly died in i3 and was not used
12311 by i2, which now no longer dies in i3 and is used in
12312 i2 but does not die in i2, and place is between i2
12313 and i3, then we may need to move a link from place to
12315 if (i2 && INSN_UID (place) <= max_uid_cuid
12316 && INSN_CUID (place) > INSN_CUID (i2)
12317 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
12318 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12320 rtx links = LOG_LINKS (place);
12321 LOG_LINKS (place) = 0;
12322 distribute_links (links);
12327 if (tem == bb->head)
12331 /* We haven't found an insn for the death note and it
12332 is still a REG_DEAD note, but we have hit the beginning
12333 of the block. If the existing life info says the reg
12334 was dead, there's nothing left to do. Otherwise, we'll
12335 need to do a global life update after combine. */
12336 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12337 && REGNO_REG_SET_P (bb->global_live_at_start,
12338 REGNO (XEXP (note, 0))))
12340 SET_BIT (refresh_blocks, this_basic_block);
12345 /* If the register is set or already dead at PLACE, we needn't do
12346 anything with this note if it is still a REG_DEAD note.
12347 We can here if it is set at all, not if is it totally replace,
12348 which is what `dead_or_set_p' checks, so also check for it being
12351 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12353 unsigned int regno = REGNO (XEXP (note, 0));
12355 if (dead_or_set_p (place, XEXP (note, 0))
12356 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12358 /* Unless the register previously died in PLACE, clear
12359 reg_last_death. [I no longer understand why this is
12361 if (reg_last_death[regno] != place)
12362 reg_last_death[regno] = 0;
12366 reg_last_death[regno] = place;
12368 /* If this is a death note for a hard reg that is occupying
12369 multiple registers, ensure that we are still using all
12370 parts of the object. If we find a piece of the object
12371 that is unused, we must add a USE for that piece before
12372 PLACE and put the appropriate REG_DEAD note on it.
12374 An alternative would be to put a REG_UNUSED for the pieces
12375 on the insn that set the register, but that can't be done if
12376 it is not in the same block. It is simpler, though less
12377 efficient, to add the USE insns. */
12379 if (place && regno < FIRST_PSEUDO_REGISTER
12380 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12382 unsigned int endregno
12383 = regno + HARD_REGNO_NREGS (regno,
12384 GET_MODE (XEXP (note, 0)));
12388 for (i = regno; i < endregno; i++)
12389 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12390 && ! find_regno_fusage (place, USE, i))
12392 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12395 /* See if we already placed a USE note for this
12396 register in front of PLACE. */
12398 GET_CODE (PREV_INSN (p)) == INSN
12399 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12401 if (rtx_equal_p (piece,
12402 XEXP (PATTERN (PREV_INSN (p)), 0)))
12411 = emit_insn_before (gen_rtx_USE (VOIDmode,
12414 REG_NOTES (use_insn)
12415 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12416 REG_NOTES (use_insn));
12422 /* Check for the case where the register dying partially
12423 overlaps the register set by this insn. */
12425 for (i = regno; i < endregno; i++)
12426 if (dead_or_set_regno_p (place, i))
12434 /* Put only REG_DEAD notes for pieces that are
12435 still used and that are not already dead or set. */
12437 for (i = regno; i < endregno; i++)
12439 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12441 if ((reg_referenced_p (piece, PATTERN (place))
12442 || (GET_CODE (place) == CALL_INSN
12443 && find_reg_fusage (place, USE, piece)))
12444 && ! dead_or_set_p (place, piece)
12445 && ! reg_bitfield_target_p (piece,
12448 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12449 REG_NOTES (place));
12459 /* Any other notes should not be present at this point in the
12466 XEXP (note, 1) = REG_NOTES (place);
12467 REG_NOTES (place) = note;
12469 else if ((REG_NOTE_KIND (note) == REG_DEAD
12470 || REG_NOTE_KIND (note) == REG_UNUSED)
12471 && GET_CODE (XEXP (note, 0)) == REG)
12472 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12476 if ((REG_NOTE_KIND (note) == REG_DEAD
12477 || REG_NOTE_KIND (note) == REG_UNUSED)
12478 && GET_CODE (XEXP (note, 0)) == REG)
12479 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12481 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12482 REG_NOTE_KIND (note),
12484 REG_NOTES (place2));
12489 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12490 I3, I2, and I1 to new locations. This is also called in one case to
12491 add a link pointing at I3 when I3's destination is changed. */
12494 distribute_links (links)
12497 rtx link, next_link;
12499 for (link = links; link; link = next_link)
12505 next_link = XEXP (link, 1);
12507 /* If the insn that this link points to is a NOTE or isn't a single
12508 set, ignore it. In the latter case, it isn't clear what we
12509 can do other than ignore the link, since we can't tell which
12510 register it was for. Such links wouldn't be used by combine
12513 It is not possible for the destination of the target of the link to
12514 have been changed by combine. The only potential of this is if we
12515 replace I3, I2, and I1 by I3 and I2. But in that case the
12516 destination of I2 also remains unchanged. */
12518 if (GET_CODE (XEXP (link, 0)) == NOTE
12519 || (set = single_set (XEXP (link, 0))) == 0)
12522 reg = SET_DEST (set);
12523 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12524 || GET_CODE (reg) == SIGN_EXTRACT
12525 || GET_CODE (reg) == STRICT_LOW_PART)
12526 reg = XEXP (reg, 0);
12528 /* A LOG_LINK is defined as being placed on the first insn that uses
12529 a register and points to the insn that sets the register. Start
12530 searching at the next insn after the target of the link and stop
12531 when we reach a set of the register or the end of the basic block.
12533 Note that this correctly handles the link that used to point from
12534 I3 to I2. Also note that not much searching is typically done here
12535 since most links don't point very far away. */
12537 for (insn = NEXT_INSN (XEXP (link, 0));
12538 (insn && (this_basic_block == n_basic_blocks - 1
12539 || BLOCK_HEAD (this_basic_block + 1) != insn));
12540 insn = NEXT_INSN (insn))
12541 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12542 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12544 if (reg_referenced_p (reg, PATTERN (insn)))
12548 else if (GET_CODE (insn) == CALL_INSN
12549 && find_reg_fusage (insn, USE, reg))
12555 /* If we found a place to put the link, place it there unless there
12556 is already a link to the same insn as LINK at that point. */
12562 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12563 if (XEXP (link2, 0) == XEXP (link, 0))
12568 XEXP (link, 1) = LOG_LINKS (place);
12569 LOG_LINKS (place) = link;
12571 /* Set added_links_insn to the earliest insn we added a
12573 if (added_links_insn == 0
12574 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12575 added_links_insn = place;
12581 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12587 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12588 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12589 insn = NEXT_INSN (insn);
12591 if (INSN_UID (insn) > max_uid_cuid)
12594 return INSN_CUID (insn);
12598 dump_combine_stats (file)
12603 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12604 combine_attempts, combine_merges, combine_extras, combine_successes);
12608 dump_combine_total_stats (file)
12613 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12614 total_attempts, total_merges, total_extras, total_successes);