1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
924 if (!NONDEBUG_INSN_P (insn))
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1014 /* Main entry point for combiner. F is the first insn of the function.
1015 NREGS is the first unused pseudo-reg number.
1017 Return nonzero if the combiner has turned an indirect jump
1018 instruction into a direct jump. */
1020 combine_instructions (rtx f, unsigned int nregs)
1026 rtx links, nextlinks;
1028 basic_block last_bb;
1030 int new_direct_jump_p = 0;
1032 for (first = f; first && !INSN_P (first); )
1033 first = NEXT_INSN (first);
1037 combine_attempts = 0;
1040 combine_successes = 0;
1042 rtl_hooks = combine_rtl_hooks;
1044 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1046 init_recog_no_volatile ();
1048 /* Allocate array for insn info. */
1049 max_uid_known = get_max_uid ();
1050 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1051 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1053 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1058 nonzero_sign_valid = 0;
1059 label_tick = label_tick_ebb_start = 1;
1061 /* Scan all SETs and see if we can deduce anything about what
1062 bits are known to be zero for some registers and how many copies
1063 of the sign bit are known to exist for those registers.
1065 Also set any known values so that we can use it while searching
1066 for what bits are known to be set. */
1068 setup_incoming_promotions (first);
1069 /* Allow the entry block and the first block to fall into the same EBB.
1070 Conceptually the incoming promotions are assigned to the entry block. */
1071 last_bb = ENTRY_BLOCK_PTR;
1073 create_log_links ();
1074 FOR_EACH_BB (this_basic_block)
1076 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1081 if (!single_pred_p (this_basic_block)
1082 || single_pred (this_basic_block) != last_bb)
1083 label_tick_ebb_start = label_tick;
1084 last_bb = this_basic_block;
1086 FOR_BB_INSNS (this_basic_block, insn)
1087 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1089 subst_low_luid = DF_INSN_LUID (insn);
1092 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1094 record_dead_and_set_regs (insn);
1097 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1098 if (REG_NOTE_KIND (links) == REG_INC)
1099 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1103 /* Record the current insn_rtx_cost of this instruction. */
1104 if (NONJUMP_INSN_P (insn))
1105 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1106 optimize_this_for_speed_p);
1108 fprintf(dump_file, "insn_cost %d: %d\n",
1109 INSN_UID (insn), INSN_COST (insn));
1113 nonzero_sign_valid = 1;
1115 /* Now scan all the insns in forward order. */
1116 label_tick = label_tick_ebb_start = 1;
1118 setup_incoming_promotions (first);
1119 last_bb = ENTRY_BLOCK_PTR;
1121 FOR_EACH_BB (this_basic_block)
1123 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1128 if (!single_pred_p (this_basic_block)
1129 || single_pred (this_basic_block) != last_bb)
1130 label_tick_ebb_start = label_tick;
1131 last_bb = this_basic_block;
1133 rtl_profile_for_bb (this_basic_block);
1134 for (insn = BB_HEAD (this_basic_block);
1135 insn != NEXT_INSN (BB_END (this_basic_block));
1136 insn = next ? next : NEXT_INSN (insn))
1139 if (NONDEBUG_INSN_P (insn))
1141 /* See if we know about function return values before this
1142 insn based upon SUBREG flags. */
1143 check_promoted_subreg (insn, PATTERN (insn));
1145 /* See if we can find hardregs and subreg of pseudos in
1146 narrower modes. This could help turning TRUNCATEs
1148 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1150 /* Try this insn with each insn it links back to. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1153 if ((next = try_combine (insn, XEXP (links, 0),
1154 NULL_RTX, &new_direct_jump_p)) != 0)
1157 /* Try each sequence of three linked insns ending with this one. */
1159 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1161 rtx link = XEXP (links, 0);
1163 /* If the linked insn has been replaced by a note, then there
1164 is no point in pursuing this chain any further. */
1168 for (nextlinks = LOG_LINKS (link);
1170 nextlinks = XEXP (nextlinks, 1))
1171 if ((next = try_combine (insn, link,
1172 XEXP (nextlinks, 0),
1173 &new_direct_jump_p)) != 0)
1178 /* Try to combine a jump insn that uses CC0
1179 with a preceding insn that sets CC0, and maybe with its
1180 logical predecessor as well.
1181 This is how we make decrement-and-branch insns.
1182 We need this special code because data flow connections
1183 via CC0 do not get entered in LOG_LINKS. */
1186 && (prev = prev_nonnote_insn (insn)) != 0
1187 && NONJUMP_INSN_P (prev)
1188 && sets_cc0_p (PATTERN (prev)))
1190 if ((next = try_combine (insn, prev,
1191 NULL_RTX, &new_direct_jump_p)) != 0)
1194 for (nextlinks = LOG_LINKS (prev); nextlinks;
1195 nextlinks = XEXP (nextlinks, 1))
1196 if ((next = try_combine (insn, prev,
1197 XEXP (nextlinks, 0),
1198 &new_direct_jump_p)) != 0)
1202 /* Do the same for an insn that explicitly references CC0. */
1203 if (NONJUMP_INSN_P (insn)
1204 && (prev = prev_nonnote_insn (insn)) != 0
1205 && NONJUMP_INSN_P (prev)
1206 && sets_cc0_p (PATTERN (prev))
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1210 if ((next = try_combine (insn, prev,
1211 NULL_RTX, &new_direct_jump_p)) != 0)
1214 for (nextlinks = LOG_LINKS (prev); nextlinks;
1215 nextlinks = XEXP (nextlinks, 1))
1216 if ((next = try_combine (insn, prev,
1217 XEXP (nextlinks, 0),
1218 &new_direct_jump_p)) != 0)
1222 /* Finally, see if any of the insns that this insn links to
1223 explicitly references CC0. If so, try this insn, that insn,
1224 and its predecessor if it sets CC0. */
1225 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1226 if (NONJUMP_INSN_P (XEXP (links, 0))
1227 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1228 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1229 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1230 && NONJUMP_INSN_P (prev)
1231 && sets_cc0_p (PATTERN (prev))
1232 && (next = try_combine (insn, XEXP (links, 0),
1233 prev, &new_direct_jump_p)) != 0)
1237 /* Try combining an insn with two different insns whose results it
1239 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1240 for (nextlinks = XEXP (links, 1); nextlinks;
1241 nextlinks = XEXP (nextlinks, 1))
1242 if ((next = try_combine (insn, XEXP (links, 0),
1243 XEXP (nextlinks, 0),
1244 &new_direct_jump_p)) != 0)
1247 /* Try this insn with each REG_EQUAL note it links back to. */
1248 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1251 rtx temp = XEXP (links, 0);
1252 if ((set = single_set (temp)) != 0
1253 && (note = find_reg_equal_equiv_note (temp)) != 0
1254 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1255 /* Avoid using a register that may already been marked
1256 dead by an earlier instruction. */
1257 && ! unmentioned_reg_p (note, SET_SRC (set))
1258 && (GET_MODE (note) == VOIDmode
1259 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1260 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1262 /* Temporarily replace the set's source with the
1263 contents of the REG_EQUAL note. The insn will
1264 be deleted or recognized by try_combine. */
1265 rtx orig = SET_SRC (set);
1266 SET_SRC (set) = note;
1268 i2mod_old_rhs = copy_rtx (orig);
1269 i2mod_new_rhs = copy_rtx (note);
1270 next = try_combine (insn, i2mod, NULL_RTX,
1271 &new_direct_jump_p);
1275 SET_SRC (set) = orig;
1280 record_dead_and_set_regs (insn);
1288 default_rtl_profile ();
1291 new_direct_jump_p |= purge_all_dead_edges ();
1292 delete_noop_moves ();
1295 free (uid_log_links);
1296 free (uid_insn_cost);
1297 VEC_free (reg_stat_type, heap, reg_stat);
1300 struct undo *undo, *next;
1301 for (undo = undobuf.frees; undo; undo = next)
1309 total_attempts += combine_attempts;
1310 total_merges += combine_merges;
1311 total_extras += combine_extras;
1312 total_successes += combine_successes;
1314 nonzero_sign_valid = 0;
1315 rtl_hooks = general_rtl_hooks;
1317 /* Make recognizer allow volatile MEMs again. */
1320 return new_direct_jump_p;
1323 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1326 init_reg_last (void)
1331 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1332 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1335 /* Set up any promoted values for incoming argument registers. */
1338 setup_incoming_promotions (rtx first)
1341 bool strictly_local = false;
1343 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1344 arg = TREE_CHAIN (arg))
1346 rtx reg = DECL_INCOMING_RTL (arg);
1348 enum machine_mode mode1, mode2, mode3, mode4;
1350 /* Only continue if the incoming argument is in a register. */
1354 /* Determine, if possible, whether all call sites of the current
1355 function lie within the current compilation unit. (This does
1356 take into account the exporting of a function via taking its
1357 address, and so forth.) */
1358 strictly_local = cgraph_local_info (current_function_decl)->local;
1360 /* The mode and signedness of the argument before any promotions happen
1361 (equal to the mode of the pseudo holding it at that stage). */
1362 mode1 = TYPE_MODE (TREE_TYPE (arg));
1363 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1365 /* The mode and signedness of the argument after any source language and
1366 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1367 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1368 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1370 /* The mode and signedness of the argument as it is actually passed,
1371 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1372 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1373 TREE_TYPE (cfun->decl), 0);
1375 /* The mode of the register in which the argument is being passed. */
1376 mode4 = GET_MODE (reg);
1378 /* Eliminate sign extensions in the callee when possible. Only
1380 (a) a mode promotion has occurred;
1381 (b) the mode of the register is the same as the mode of
1382 the argument as it is passed; and
1383 (c) the signedness does not change across any of the promotions; and
1384 (d) when no language-level promotions (which we cannot guarantee
1385 will have been done by an external caller) are necessary,
1386 unless we know that this function is only ever called from
1387 the current compilation unit -- all of whose call sites will
1388 do the mode1 --> mode2 promotion. */
1392 && (mode1 == mode2 || strictly_local))
1394 /* Record that the value was promoted from mode1 to mode3,
1395 so that any sign extension at the head of the current
1396 function may be eliminated. */
1398 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1399 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1400 record_value_for_reg (reg, first, x);
1405 /* Called via note_stores. If X is a pseudo that is narrower than
1406 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1408 If we are setting only a portion of X and we can't figure out what
1409 portion, assume all bits will be used since we don't know what will
1412 Similarly, set how many bits of X are known to be copies of the sign bit
1413 at all locations in the function. This is the smallest number implied
1417 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1419 rtx insn = (rtx) data;
1423 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1424 /* If this register is undefined at the start of the file, we can't
1425 say what its contents were. */
1426 && ! REGNO_REG_SET_P
1427 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1428 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1430 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1432 if (set == 0 || GET_CODE (set) == CLOBBER)
1434 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1435 rsp->sign_bit_copies = 1;
1439 /* If this register is being initialized using itself, and the
1440 register is uninitialized in this basic block, and there are
1441 no LOG_LINKS which set the register, then part of the
1442 register is uninitialized. In that case we can't assume
1443 anything about the number of nonzero bits.
1445 ??? We could do better if we checked this in
1446 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1447 could avoid making assumptions about the insn which initially
1448 sets the register, while still using the information in other
1449 insns. We would have to be careful to check every insn
1450 involved in the combination. */
1453 && reg_referenced_p (x, PATTERN (insn))
1454 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1459 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1461 if (dead_or_set_p (XEXP (link, 0), x))
1466 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1467 rsp->sign_bit_copies = 1;
1472 /* If this is a complex assignment, see if we can convert it into a
1473 simple assignment. */
1474 set = expand_field_assignment (set);
1476 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1477 set what we know about X. */
1479 if (SET_DEST (set) == x
1480 || (GET_CODE (SET_DEST (set)) == SUBREG
1481 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1482 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1483 && SUBREG_REG (SET_DEST (set)) == x))
1485 rtx src = SET_SRC (set);
1487 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1488 /* If X is narrower than a word and SRC is a non-negative
1489 constant that would appear negative in the mode of X,
1490 sign-extend it for use in reg_stat[].nonzero_bits because some
1491 machines (maybe most) will actually do the sign-extension
1492 and this is the conservative approach.
1494 ??? For 2.5, try to tighten up the MD files in this regard
1495 instead of this kludge. */
1497 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1498 && CONST_INT_P (src)
1500 && 0 != (INTVAL (src)
1501 & ((HOST_WIDE_INT) 1
1502 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1503 src = GEN_INT (INTVAL (src)
1504 | ((HOST_WIDE_INT) (-1)
1505 << GET_MODE_BITSIZE (GET_MODE (x))));
1508 /* Don't call nonzero_bits if it cannot change anything. */
1509 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1510 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1511 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1512 if (rsp->sign_bit_copies == 0
1513 || rsp->sign_bit_copies > num)
1514 rsp->sign_bit_copies = num;
1518 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1519 rsp->sign_bit_copies = 1;
1524 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1525 insns that were previously combined into I3 or that will be combined
1526 into the merger of INSN and I3.
1528 Return 0 if the combination is not allowed for any reason.
1530 If the combination is allowed, *PDEST will be set to the single
1531 destination of INSN and *PSRC to the single source, and this function
1535 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1536 rtx *pdest, rtx *psrc)
1545 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1546 && next_active_insn (succ) == i3)
1547 : next_active_insn (insn) == i3);
1549 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1550 or a PARALLEL consisting of such a SET and CLOBBERs.
1552 If INSN has CLOBBER parallel parts, ignore them for our processing.
1553 By definition, these happen during the execution of the insn. When it
1554 is merged with another insn, all bets are off. If they are, in fact,
1555 needed and aren't also supplied in I3, they may be added by
1556 recog_for_combine. Otherwise, it won't match.
1558 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1561 Get the source and destination of INSN. If more than one, can't
1564 if (GET_CODE (PATTERN (insn)) == SET)
1565 set = PATTERN (insn);
1566 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1567 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1569 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1571 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1573 switch (GET_CODE (elt))
1575 /* This is important to combine floating point insns
1576 for the SH4 port. */
1578 /* Combining an isolated USE doesn't make sense.
1579 We depend here on combinable_i3pat to reject them. */
1580 /* The code below this loop only verifies that the inputs of
1581 the SET in INSN do not change. We call reg_set_between_p
1582 to verify that the REG in the USE does not change between
1584 If the USE in INSN was for a pseudo register, the matching
1585 insn pattern will likely match any register; combining this
1586 with any other USE would only be safe if we knew that the
1587 used registers have identical values, or if there was
1588 something to tell them apart, e.g. different modes. For
1589 now, we forgo such complicated tests and simply disallow
1590 combining of USES of pseudo registers with any other USE. */
1591 if (REG_P (XEXP (elt, 0))
1592 && GET_CODE (PATTERN (i3)) == PARALLEL)
1594 rtx i3pat = PATTERN (i3);
1595 int i = XVECLEN (i3pat, 0) - 1;
1596 unsigned int regno = REGNO (XEXP (elt, 0));
1600 rtx i3elt = XVECEXP (i3pat, 0, i);
1602 if (GET_CODE (i3elt) == USE
1603 && REG_P (XEXP (i3elt, 0))
1604 && (REGNO (XEXP (i3elt, 0)) == regno
1605 ? reg_set_between_p (XEXP (elt, 0),
1606 PREV_INSN (insn), i3)
1607 : regno >= FIRST_PSEUDO_REGISTER))
1614 /* We can ignore CLOBBERs. */
1619 /* Ignore SETs whose result isn't used but not those that
1620 have side-effects. */
1621 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1622 && insn_nothrow_p (insn)
1623 && !side_effects_p (elt))
1626 /* If we have already found a SET, this is a second one and
1627 so we cannot combine with this insn. */
1635 /* Anything else means we can't combine. */
1641 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1642 so don't do anything with it. */
1643 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1652 set = expand_field_assignment (set);
1653 src = SET_SRC (set), dest = SET_DEST (set);
1655 /* Don't eliminate a store in the stack pointer. */
1656 if (dest == stack_pointer_rtx
1657 /* Don't combine with an insn that sets a register to itself if it has
1658 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1659 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1660 /* Can't merge an ASM_OPERANDS. */
1661 || GET_CODE (src) == ASM_OPERANDS
1662 /* Can't merge a function call. */
1663 || GET_CODE (src) == CALL
1664 /* Don't eliminate a function call argument. */
1666 && (find_reg_fusage (i3, USE, dest)
1668 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1669 && global_regs[REGNO (dest)])))
1670 /* Don't substitute into an incremented register. */
1671 || FIND_REG_INC_NOTE (i3, dest)
1672 || (succ && FIND_REG_INC_NOTE (succ, dest))
1673 /* Don't substitute into a non-local goto, this confuses CFG. */
1674 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1675 /* Make sure that DEST is not used after SUCC but before I3. */
1676 || (succ && ! all_adjacent
1677 && reg_used_between_p (dest, succ, i3))
1678 /* Make sure that the value that is to be substituted for the register
1679 does not use any registers whose values alter in between. However,
1680 If the insns are adjacent, a use can't cross a set even though we
1681 think it might (this can happen for a sequence of insns each setting
1682 the same destination; last_set of that register might point to
1683 a NOTE). If INSN has a REG_EQUIV note, the register is always
1684 equivalent to the memory so the substitution is valid even if there
1685 are intervening stores. Also, don't move a volatile asm or
1686 UNSPEC_VOLATILE across any other insns. */
1689 || ! find_reg_note (insn, REG_EQUIV, src))
1690 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1691 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1692 || GET_CODE (src) == UNSPEC_VOLATILE))
1693 /* Don't combine across a CALL_INSN, because that would possibly
1694 change whether the life span of some REGs crosses calls or not,
1695 and it is a pain to update that information.
1696 Exception: if source is a constant, moving it later can't hurt.
1697 Accept that as a special case. */
1698 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1701 /* DEST must either be a REG or CC0. */
1704 /* If register alignment is being enforced for multi-word items in all
1705 cases except for parameters, it is possible to have a register copy
1706 insn referencing a hard register that is not allowed to contain the
1707 mode being copied and which would not be valid as an operand of most
1708 insns. Eliminate this problem by not combining with such an insn.
1710 Also, on some machines we don't want to extend the life of a hard
1714 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1715 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1716 /* Don't extend the life of a hard register unless it is
1717 user variable (if we have few registers) or it can't
1718 fit into the desired register (meaning something special
1720 Also avoid substituting a return register into I3, because
1721 reload can't handle a conflict with constraints of other
1723 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1724 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1727 else if (GET_CODE (dest) != CC0)
1731 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1732 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1733 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1735 /* Don't substitute for a register intended as a clobberable
1737 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1738 if (rtx_equal_p (reg, dest))
1741 /* If the clobber represents an earlyclobber operand, we must not
1742 substitute an expression containing the clobbered register.
1743 As we do not analyze the constraint strings here, we have to
1744 make the conservative assumption. However, if the register is
1745 a fixed hard reg, the clobber cannot represent any operand;
1746 we leave it up to the machine description to either accept or
1747 reject use-and-clobber patterns. */
1749 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1750 || !fixed_regs[REGNO (reg)])
1751 if (reg_overlap_mentioned_p (reg, src))
1755 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1756 or not), reject, unless nothing volatile comes between it and I3 */
1758 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1760 /* Make sure succ doesn't contain a volatile reference. */
1761 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1764 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1765 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1769 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1770 to be an explicit register variable, and was chosen for a reason. */
1772 if (GET_CODE (src) == ASM_OPERANDS
1773 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1776 /* If there are any volatile insns between INSN and I3, reject, because
1777 they might affect machine state. */
1779 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1780 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1783 /* If INSN contains an autoincrement or autodecrement, make sure that
1784 register is not used between there and I3, and not already used in
1785 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1786 Also insist that I3 not be a jump; if it were one
1787 and the incremented register were spilled, we would lose. */
1790 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1791 if (REG_NOTE_KIND (link) == REG_INC
1793 || reg_used_between_p (XEXP (link, 0), insn, i3)
1794 || (pred != NULL_RTX
1795 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1796 || (succ != NULL_RTX
1797 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1798 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1803 /* Don't combine an insn that follows a CC0-setting insn.
1804 An insn that uses CC0 must not be separated from the one that sets it.
1805 We do, however, allow I2 to follow a CC0-setting insn if that insn
1806 is passed as I1; in that case it will be deleted also.
1807 We also allow combining in this case if all the insns are adjacent
1808 because that would leave the two CC0 insns adjacent as well.
1809 It would be more logical to test whether CC0 occurs inside I1 or I2,
1810 but that would be much slower, and this ought to be equivalent. */
1812 p = prev_nonnote_insn (insn);
1813 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1818 /* If we get here, we have passed all the tests and the combination is
1827 /* LOC is the location within I3 that contains its pattern or the component
1828 of a PARALLEL of the pattern. We validate that it is valid for combining.
1830 One problem is if I3 modifies its output, as opposed to replacing it
1831 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1832 so would produce an insn that is not equivalent to the original insns.
1836 (set (reg:DI 101) (reg:DI 100))
1837 (set (subreg:SI (reg:DI 101) 0) <foo>)
1839 This is NOT equivalent to:
1841 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1842 (set (reg:DI 101) (reg:DI 100))])
1844 Not only does this modify 100 (in which case it might still be valid
1845 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1847 We can also run into a problem if I2 sets a register that I1
1848 uses and I1 gets directly substituted into I3 (not via I2). In that
1849 case, we would be getting the wrong value of I2DEST into I3, so we
1850 must reject the combination. This case occurs when I2 and I1 both
1851 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1852 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1853 of a SET must prevent combination from occurring.
1855 Before doing the above check, we first try to expand a field assignment
1856 into a set of logical operations.
1858 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1859 we place a register that is both set and used within I3. If more than one
1860 such register is detected, we fail.
1862 Return 1 if the combination is valid, zero otherwise. */
1865 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1866 int i1_not_in_src, rtx *pi3dest_killed)
1870 if (GET_CODE (x) == SET)
1873 rtx dest = SET_DEST (set);
1874 rtx src = SET_SRC (set);
1875 rtx inner_dest = dest;
1878 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1879 || GET_CODE (inner_dest) == SUBREG
1880 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1881 inner_dest = XEXP (inner_dest, 0);
1883 /* Check for the case where I3 modifies its output, as discussed
1884 above. We don't want to prevent pseudos from being combined
1885 into the address of a MEM, so only prevent the combination if
1886 i1 or i2 set the same MEM. */
1887 if ((inner_dest != dest &&
1888 (!MEM_P (inner_dest)
1889 || rtx_equal_p (i2dest, inner_dest)
1890 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1891 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1892 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1894 /* This is the same test done in can_combine_p except we can't test
1895 all_adjacent; we don't have to, since this instruction will stay
1896 in place, thus we are not considering increasing the lifetime of
1899 Also, if this insn sets a function argument, combining it with
1900 something that might need a spill could clobber a previous
1901 function argument; the all_adjacent test in can_combine_p also
1902 checks this; here, we do a more specific test for this case. */
1904 || (REG_P (inner_dest)
1905 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1906 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1907 GET_MODE (inner_dest))))
1908 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1911 /* If DEST is used in I3, it is being killed in this insn, so
1912 record that for later. We have to consider paradoxical
1913 subregs here, since they kill the whole register, but we
1914 ignore partial subregs, STRICT_LOW_PART, etc.
1915 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1916 STACK_POINTER_REGNUM, since these are always considered to be
1917 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1919 if (GET_CODE (subdest) == SUBREG
1920 && (GET_MODE_SIZE (GET_MODE (subdest))
1921 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1922 subdest = SUBREG_REG (subdest);
1925 && reg_referenced_p (subdest, PATTERN (i3))
1926 && REGNO (subdest) != FRAME_POINTER_REGNUM
1927 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1928 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1930 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1931 && (REGNO (subdest) != ARG_POINTER_REGNUM
1932 || ! fixed_regs [REGNO (subdest)])
1934 && REGNO (subdest) != STACK_POINTER_REGNUM)
1936 if (*pi3dest_killed)
1939 *pi3dest_killed = subdest;
1943 else if (GET_CODE (x) == PARALLEL)
1947 for (i = 0; i < XVECLEN (x, 0); i++)
1948 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1949 i1_not_in_src, pi3dest_killed))
1956 /* Return 1 if X is an arithmetic expression that contains a multiplication
1957 and division. We don't count multiplications by powers of two here. */
1960 contains_muldiv (rtx x)
1962 switch (GET_CODE (x))
1964 case MOD: case DIV: case UMOD: case UDIV:
1968 return ! (CONST_INT_P (XEXP (x, 1))
1969 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1972 return contains_muldiv (XEXP (x, 0))
1973 || contains_muldiv (XEXP (x, 1));
1976 return contains_muldiv (XEXP (x, 0));
1982 /* Determine whether INSN can be used in a combination. Return nonzero if
1983 not. This is used in try_combine to detect early some cases where we
1984 can't perform combinations. */
1987 cant_combine_insn_p (rtx insn)
1992 /* If this isn't really an insn, we can't do anything.
1993 This can occur when flow deletes an insn that it has merged into an
1994 auto-increment address. */
1995 if (! INSN_P (insn))
1998 /* Never combine loads and stores involving hard regs that are likely
1999 to be spilled. The register allocator can usually handle such
2000 reg-reg moves by tying. If we allow the combiner to make
2001 substitutions of likely-spilled regs, reload might die.
2002 As an exception, we allow combinations involving fixed regs; these are
2003 not available to the register allocator so there's no risk involved. */
2005 set = single_set (insn);
2008 src = SET_SRC (set);
2009 dest = SET_DEST (set);
2010 if (GET_CODE (src) == SUBREG)
2011 src = SUBREG_REG (src);
2012 if (GET_CODE (dest) == SUBREG)
2013 dest = SUBREG_REG (dest);
2014 if (REG_P (src) && REG_P (dest)
2015 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2016 && ! fixed_regs[REGNO (src)]
2017 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2018 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2019 && ! fixed_regs[REGNO (dest)]
2020 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2026 struct likely_spilled_retval_info
2028 unsigned regno, nregs;
2032 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2033 hard registers that are known to be written to / clobbered in full. */
2035 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2037 struct likely_spilled_retval_info *const info =
2038 (struct likely_spilled_retval_info *) data;
2039 unsigned regno, nregs;
2042 if (!REG_P (XEXP (set, 0)))
2045 if (regno >= info->regno + info->nregs)
2047 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2048 if (regno + nregs <= info->regno)
2050 new_mask = (2U << (nregs - 1)) - 1;
2051 if (regno < info->regno)
2052 new_mask >>= info->regno - regno;
2054 new_mask <<= regno - info->regno;
2055 info->mask &= ~new_mask;
2058 /* Return nonzero iff part of the return value is live during INSN, and
2059 it is likely spilled. This can happen when more than one insn is needed
2060 to copy the return value, e.g. when we consider to combine into the
2061 second copy insn for a complex value. */
2064 likely_spilled_retval_p (rtx insn)
2066 rtx use = BB_END (this_basic_block);
2068 unsigned regno, nregs;
2069 /* We assume here that no machine mode needs more than
2070 32 hard registers when the value overlaps with a register
2071 for which FUNCTION_VALUE_REGNO_P is true. */
2073 struct likely_spilled_retval_info info;
2075 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2077 reg = XEXP (PATTERN (use), 0);
2078 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2080 regno = REGNO (reg);
2081 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2084 mask = (2U << (nregs - 1)) - 1;
2086 /* Disregard parts of the return value that are set later. */
2090 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2092 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2095 /* Check if any of the (probably) live return value registers is
2100 if ((mask & 1 << nregs)
2101 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2107 /* Adjust INSN after we made a change to its destination.
2109 Changing the destination can invalidate notes that say something about
2110 the results of the insn and a LOG_LINK pointing to the insn. */
2113 adjust_for_new_dest (rtx insn)
2115 /* For notes, be conservative and simply remove them. */
2116 remove_reg_equal_equiv_notes (insn);
2118 /* The new insn will have a destination that was previously the destination
2119 of an insn just above it. Call distribute_links to make a LOG_LINK from
2120 the next use of that destination. */
2121 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2123 df_insn_rescan (insn);
2126 /* Return TRUE if combine can reuse reg X in mode MODE.
2127 ADDED_SETS is nonzero if the original set is still required. */
2129 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2137 /* Allow hard registers if the new mode is legal, and occupies no more
2138 registers than the old mode. */
2139 if (regno < FIRST_PSEUDO_REGISTER)
2140 return (HARD_REGNO_MODE_OK (regno, mode)
2141 && (hard_regno_nregs[regno][GET_MODE (x)]
2142 >= hard_regno_nregs[regno][mode]));
2144 /* Or a pseudo that is only used once. */
2145 return (REG_N_SETS (regno) == 1 && !added_sets
2146 && !REG_USERVAR_P (x));
2150 /* Check whether X, the destination of a set, refers to part of
2151 the register specified by REG. */
2154 reg_subword_p (rtx x, rtx reg)
2156 /* Check that reg is an integer mode register. */
2157 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2160 if (GET_CODE (x) == STRICT_LOW_PART
2161 || GET_CODE (x) == ZERO_EXTRACT)
2164 return GET_CODE (x) == SUBREG
2165 && SUBREG_REG (x) == reg
2166 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2170 /* Replace auto-increment addressing modes with explicit operations to
2171 access the same addresses without modifying the corresponding
2172 registers. If AFTER holds, SRC is meant to be reused after the
2173 side effect, otherwise it is to be reused before that. */
2176 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2179 const RTX_CODE code = GET_CODE (x);
2195 /* SCRATCH must be shared because they represent distinct values. */
2198 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2203 if (shared_const_p (x))
2208 mem_mode = GET_MODE (x);
2215 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2216 if (after == (code == PRE_INC || code == PRE_DEC))
2217 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2219 x = gen_rtx_PLUS (GET_MODE (x),
2220 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2221 GEN_INT ((code == PRE_INC || code == POST_INC)
2222 ? GET_MODE_SIZE (mem_mode)
2223 : -GET_MODE_SIZE (mem_mode)));
2228 if (after == (code == PRE_MODIFY))
2232 return cleanup_auto_inc_dec (x, after, mem_mode);
2238 /* Copy the various flags, fields, and other information. We assume
2239 that all fields need copying, and then clear the fields that should
2240 not be copied. That is the sensible default behavior, and forces
2241 us to explicitly document why we are *not* copying a flag. */
2242 x = shallow_copy_rtx (x);
2244 /* We do not copy the USED flag, which is used as a mark bit during
2245 walks over the RTL. */
2246 RTX_FLAG (x, used) = 0;
2248 /* We do not copy FRAME_RELATED for INSNs. */
2250 RTX_FLAG (x, frame_related) = 0;
2252 fmt = GET_RTX_FORMAT (code);
2253 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2255 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2256 else if (fmt[i] == 'E' || fmt[i] == 'V')
2259 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2260 for (j = 0; j < XVECLEN (x, i); j++)
2262 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2268 /* Auxiliary data structure for propagate_for_debug_stmt. */
2270 struct rtx_subst_pair
2277 /* DATA points to an rtx_subst_pair. Return the value that should be
2281 propagate_for_debug_subst (rtx from ATTRIBUTE_UNUSED, void *data)
2283 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2285 if (!pair->adjusted)
2287 pair->adjusted = true;
2288 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2291 return copy_rtx (pair->to);
2295 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2296 and LAST. If MOVE holds, debug insns must also be moved past
2300 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2302 rtx next, move_pos = move ? last : NULL_RTX, loc;
2305 struct rtx_subst_pair p;
2311 next = NEXT_INSN (insn);
2312 while (next != last)
2315 next = NEXT_INSN (insn);
2316 if (DEBUG_INSN_P (insn))
2319 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2320 dest, propagate_for_debug_subst, &p);
2322 loc = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), dest, src);
2324 if (loc == INSN_VAR_LOCATION_LOC (insn))
2326 INSN_VAR_LOCATION_LOC (insn) = loc;
2330 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2331 move_pos = emit_debug_insn_after (insn, move_pos);
2334 df_insn_rescan (insn);
2339 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2340 Note that the INSN should be deleted *after* removing dead edges, so
2341 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2342 but not for a (set (pc) (label_ref FOO)). */
2345 update_cfg_for_uncondjump (rtx insn)
2347 basic_block bb = BLOCK_FOR_INSN (insn);
2348 bool at_end = (BB_END (bb) == insn);
2351 purge_dead_edges (bb);
2354 if (at_end && EDGE_COUNT (bb->succs) == 1)
2355 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2359 /* Try to combine the insns I1 and I2 into I3.
2360 Here I1 and I2 appear earlier than I3.
2361 I1 can be zero; then we combine just I2 into I3.
2363 If we are combining three insns and the resulting insn is not recognized,
2364 try splitting it into two insns. If that happens, I2 and I3 are retained
2365 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2368 Return 0 if the combination does not work. Then nothing is changed.
2369 If we did the combination, return the insn at which combine should
2372 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2373 new direct jump instruction. */
2376 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2378 /* New patterns for I3 and I2, respectively. */
2379 rtx newpat, newi2pat = 0;
2380 rtvec newpat_vec_with_clobbers = 0;
2381 int substed_i2 = 0, substed_i1 = 0;
2382 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2383 int added_sets_1, added_sets_2;
2384 /* Total number of SETs to put into I3. */
2386 /* Nonzero if I2's body now appears in I3. */
2388 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2389 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2390 /* Contains I3 if the destination of I3 is used in its source, which means
2391 that the old life of I3 is being killed. If that usage is placed into
2392 I2 and not in I3, a REG_DEAD note must be made. */
2393 rtx i3dest_killed = 0;
2394 /* SET_DEST and SET_SRC of I2 and I1. */
2395 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2396 /* Set if I2DEST was reused as a scratch register. */
2397 bool i2scratch = false;
2398 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2399 rtx i1pat = 0, i2pat = 0;
2400 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2401 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2402 int i2dest_killed = 0, i1dest_killed = 0;
2403 int i1_feeds_i3 = 0;
2404 /* Notes that must be added to REG_NOTES in I3 and I2. */
2405 rtx new_i3_notes, new_i2_notes;
2406 /* Notes that we substituted I3 into I2 instead of the normal case. */
2407 int i3_subst_into_i2 = 0;
2408 /* Notes that I1, I2 or I3 is a MULT operation. */
2411 int changed_i3_dest = 0;
2417 rtx new_other_notes;
2420 /* Exit early if one of the insns involved can't be used for
2422 if (cant_combine_insn_p (i3)
2423 || cant_combine_insn_p (i2)
2424 || (i1 && cant_combine_insn_p (i1))
2425 || likely_spilled_retval_p (i3))
2429 undobuf.other_insn = 0;
2431 /* Reset the hard register usage information. */
2432 CLEAR_HARD_REG_SET (newpat_used_regs);
2434 if (dump_file && (dump_flags & TDF_DETAILS))
2437 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2438 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2440 fprintf (dump_file, "\nTrying %d -> %d:\n",
2441 INSN_UID (i2), INSN_UID (i3));
2444 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2445 code below, set I1 to be the earlier of the two insns. */
2446 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2447 temp = i1, i1 = i2, i2 = temp;
2449 added_links_insn = 0;
2451 /* First check for one important special-case that the code below will
2452 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2453 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2454 we may be able to replace that destination with the destination of I3.
2455 This occurs in the common code where we compute both a quotient and
2456 remainder into a structure, in which case we want to do the computation
2457 directly into the structure to avoid register-register copies.
2459 Note that this case handles both multiple sets in I2 and also
2460 cases where I2 has a number of CLOBBER or PARALLELs.
2462 We make very conservative checks below and only try to handle the
2463 most common cases of this. For example, we only handle the case
2464 where I2 and I3 are adjacent to avoid making difficult register
2467 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2468 && REG_P (SET_SRC (PATTERN (i3)))
2469 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2470 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2471 && GET_CODE (PATTERN (i2)) == PARALLEL
2472 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2473 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2474 below would need to check what is inside (and reg_overlap_mentioned_p
2475 doesn't support those codes anyway). Don't allow those destinations;
2476 the resulting insn isn't likely to be recognized anyway. */
2477 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2478 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2479 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2480 SET_DEST (PATTERN (i3)))
2481 && next_active_insn (i2) == i3)
2483 rtx p2 = PATTERN (i2);
2485 /* Make sure that the destination of I3,
2486 which we are going to substitute into one output of I2,
2487 is not used within another output of I2. We must avoid making this:
2488 (parallel [(set (mem (reg 69)) ...)
2489 (set (reg 69) ...)])
2490 which is not well-defined as to order of actions.
2491 (Besides, reload can't handle output reloads for this.)
2493 The problem can also happen if the dest of I3 is a memory ref,
2494 if another dest in I2 is an indirect memory ref. */
2495 for (i = 0; i < XVECLEN (p2, 0); i++)
2496 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2497 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2498 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2499 SET_DEST (XVECEXP (p2, 0, i))))
2502 if (i == XVECLEN (p2, 0))
2503 for (i = 0; i < XVECLEN (p2, 0); i++)
2504 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2505 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2506 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2511 subst_low_luid = DF_INSN_LUID (i2);
2513 added_sets_2 = added_sets_1 = 0;
2514 i2src = SET_DEST (PATTERN (i3));
2515 i2dest = SET_SRC (PATTERN (i3));
2516 i2dest_killed = dead_or_set_p (i2, i2dest);
2518 /* Replace the dest in I2 with our dest and make the resulting
2519 insn the new pattern for I3. Then skip to where we
2520 validate the pattern. Everything was set up above. */
2521 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2522 SET_DEST (PATTERN (i3)));
2525 i3_subst_into_i2 = 1;
2526 goto validate_replacement;
2530 /* If I2 is setting a pseudo to a constant and I3 is setting some
2531 sub-part of it to another constant, merge them by making a new
2534 && (temp = single_set (i2)) != 0
2535 && (CONST_INT_P (SET_SRC (temp))
2536 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2537 && GET_CODE (PATTERN (i3)) == SET
2538 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2539 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2540 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2542 rtx dest = SET_DEST (PATTERN (i3));
2546 if (GET_CODE (dest) == ZERO_EXTRACT)
2548 if (CONST_INT_P (XEXP (dest, 1))
2549 && CONST_INT_P (XEXP (dest, 2)))
2551 width = INTVAL (XEXP (dest, 1));
2552 offset = INTVAL (XEXP (dest, 2));
2553 dest = XEXP (dest, 0);
2554 if (BITS_BIG_ENDIAN)
2555 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2560 if (GET_CODE (dest) == STRICT_LOW_PART)
2561 dest = XEXP (dest, 0);
2562 width = GET_MODE_BITSIZE (GET_MODE (dest));
2568 /* If this is the low part, we're done. */
2569 if (subreg_lowpart_p (dest))
2571 /* Handle the case where inner is twice the size of outer. */
2572 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2573 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2574 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2575 /* Otherwise give up for now. */
2581 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2582 <= HOST_BITS_PER_WIDE_INT * 2))
2584 HOST_WIDE_INT mhi, ohi, ihi;
2585 HOST_WIDE_INT mlo, olo, ilo;
2586 rtx inner = SET_SRC (PATTERN (i3));
2587 rtx outer = SET_SRC (temp);
2589 if (CONST_INT_P (outer))
2591 olo = INTVAL (outer);
2592 ohi = olo < 0 ? -1 : 0;
2596 olo = CONST_DOUBLE_LOW (outer);
2597 ohi = CONST_DOUBLE_HIGH (outer);
2600 if (CONST_INT_P (inner))
2602 ilo = INTVAL (inner);
2603 ihi = ilo < 0 ? -1 : 0;
2607 ilo = CONST_DOUBLE_LOW (inner);
2608 ihi = CONST_DOUBLE_HIGH (inner);
2611 if (width < HOST_BITS_PER_WIDE_INT)
2613 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2616 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2618 mhi = ((unsigned HOST_WIDE_INT) 1
2619 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2631 if (offset >= HOST_BITS_PER_WIDE_INT)
2633 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2635 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2638 else if (offset > 0)
2640 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2641 >> (HOST_BITS_PER_WIDE_INT - offset));
2642 mlo = mlo << offset;
2643 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2644 >> (HOST_BITS_PER_WIDE_INT - offset));
2645 ilo = ilo << offset;
2648 olo = (olo & ~mlo) | ilo;
2649 ohi = (ohi & ~mhi) | ihi;
2653 subst_low_luid = DF_INSN_LUID (i2);
2654 added_sets_2 = added_sets_1 = 0;
2655 i2dest = SET_DEST (temp);
2656 i2dest_killed = dead_or_set_p (i2, i2dest);
2658 SUBST (SET_SRC (temp),
2659 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2661 newpat = PATTERN (i2);
2662 goto validate_replacement;
2667 /* If we have no I1 and I2 looks like:
2668 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2670 make up a dummy I1 that is
2673 (set (reg:CC X) (compare:CC Y (const_int 0)))
2675 (We can ignore any trailing CLOBBERs.)
2677 This undoes a previous combination and allows us to match a branch-and-
2680 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2681 && XVECLEN (PATTERN (i2), 0) >= 2
2682 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2683 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2685 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2686 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2687 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2688 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2689 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2690 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2692 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2693 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2698 /* We make I1 with the same INSN_UID as I2. This gives it
2699 the same DF_INSN_LUID for value tracking. Our fake I1 will
2700 never appear in the insn stream so giving it the same INSN_UID
2701 as I2 will not cause a problem. */
2703 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2704 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2705 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2707 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2708 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2709 SET_DEST (PATTERN (i1)));
2714 /* Verify that I2 and I1 are valid for combining. */
2715 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2716 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2722 /* Record whether I2DEST is used in I2SRC and similarly for the other
2723 cases. Knowing this will help in register status updating below. */
2724 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2725 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2726 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2727 i2dest_killed = dead_or_set_p (i2, i2dest);
2728 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2730 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2732 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2734 /* Ensure that I3's pattern can be the destination of combines. */
2735 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2736 i1 && i2dest_in_i1src && i1_feeds_i3,
2743 /* See if any of the insns is a MULT operation. Unless one is, we will
2744 reject a combination that is, since it must be slower. Be conservative
2746 if (GET_CODE (i2src) == MULT
2747 || (i1 != 0 && GET_CODE (i1src) == MULT)
2748 || (GET_CODE (PATTERN (i3)) == SET
2749 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2752 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2753 We used to do this EXCEPT in one case: I3 has a post-inc in an
2754 output operand. However, that exception can give rise to insns like
2756 which is a famous insn on the PDP-11 where the value of r3 used as the
2757 source was model-dependent. Avoid this sort of thing. */
2760 if (!(GET_CODE (PATTERN (i3)) == SET
2761 && REG_P (SET_SRC (PATTERN (i3)))
2762 && MEM_P (SET_DEST (PATTERN (i3)))
2763 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2764 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2765 /* It's not the exception. */
2768 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2769 if (REG_NOTE_KIND (link) == REG_INC
2770 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2772 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2779 /* See if the SETs in I1 or I2 need to be kept around in the merged
2780 instruction: whenever the value set there is still needed past I3.
2781 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2783 For the SET in I1, we have two cases: If I1 and I2 independently
2784 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2785 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2786 in I1 needs to be kept around unless I1DEST dies or is set in either
2787 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2788 I1DEST. If so, we know I1 feeds into I2. */
2790 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2793 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2794 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2796 /* If the set in I2 needs to be kept around, we must make a copy of
2797 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2798 PATTERN (I2), we are only substituting for the original I1DEST, not into
2799 an already-substituted copy. This also prevents making self-referential
2800 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2805 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2806 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2808 i2pat = copy_rtx (PATTERN (i2));
2813 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2814 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2816 i1pat = copy_rtx (PATTERN (i1));
2821 /* Substitute in the latest insn for the regs set by the earlier ones. */
2823 maxreg = max_reg_num ();
2828 /* Many machines that don't use CC0 have insns that can both perform an
2829 arithmetic operation and set the condition code. These operations will
2830 be represented as a PARALLEL with the first element of the vector
2831 being a COMPARE of an arithmetic operation with the constant zero.
2832 The second element of the vector will set some pseudo to the result
2833 of the same arithmetic operation. If we simplify the COMPARE, we won't
2834 match such a pattern and so will generate an extra insn. Here we test
2835 for this case, where both the comparison and the operation result are
2836 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2837 I2SRC. Later we will make the PARALLEL that contains I2. */
2839 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2840 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2841 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2842 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2844 #ifdef SELECT_CC_MODE
2846 enum machine_mode compare_mode;
2849 newpat = PATTERN (i3);
2850 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2854 #ifdef SELECT_CC_MODE
2855 /* See if a COMPARE with the operand we substituted in should be done
2856 with the mode that is currently being used. If not, do the same
2857 processing we do in `subst' for a SET; namely, if the destination
2858 is used only once, try to replace it with a register of the proper
2859 mode and also replace the COMPARE. */
2860 if (undobuf.other_insn == 0
2861 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2862 &undobuf.other_insn))
2863 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2865 != GET_MODE (SET_DEST (newpat))))
2867 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2870 unsigned int regno = REGNO (SET_DEST (newpat));
2873 if (regno < FIRST_PSEUDO_REGISTER)
2874 new_dest = gen_rtx_REG (compare_mode, regno);
2877 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2878 new_dest = regno_reg_rtx[regno];
2881 SUBST (SET_DEST (newpat), new_dest);
2882 SUBST (XEXP (*cc_use, 0), new_dest);
2883 SUBST (SET_SRC (newpat),
2884 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2887 undobuf.other_insn = 0;
2894 /* It is possible that the source of I2 or I1 may be performing
2895 an unneeded operation, such as a ZERO_EXTEND of something
2896 that is known to have the high part zero. Handle that case
2897 by letting subst look at the innermost one of them.
2899 Another way to do this would be to have a function that tries
2900 to simplify a single insn instead of merging two or more
2901 insns. We don't do this because of the potential of infinite
2902 loops and because of the potential extra memory required.
2903 However, doing it the way we are is a bit of a kludge and
2904 doesn't catch all cases.
2906 But only do this if -fexpensive-optimizations since it slows
2907 things down and doesn't usually win.
2909 This is not done in the COMPARE case above because the
2910 unmodified I2PAT is used in the PARALLEL and so a pattern
2911 with a modified I2SRC would not match. */
2913 if (flag_expensive_optimizations)
2915 /* Pass pc_rtx so no substitutions are done, just
2919 subst_low_luid = DF_INSN_LUID (i1);
2920 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2924 subst_low_luid = DF_INSN_LUID (i2);
2925 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2929 n_occurrences = 0; /* `subst' counts here */
2931 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2932 need to make a unique copy of I2SRC each time we substitute it
2933 to avoid self-referential rtl. */
2935 subst_low_luid = DF_INSN_LUID (i2);
2936 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2937 ! i1_feeds_i3 && i1dest_in_i1src);
2940 /* Record whether i2's body now appears within i3's body. */
2941 i2_is_used = n_occurrences;
2944 /* If we already got a failure, don't try to do more. Otherwise,
2945 try to substitute in I1 if we have it. */
2947 if (i1 && GET_CODE (newpat) != CLOBBER)
2949 /* Check that an autoincrement side-effect on I1 has not been lost.
2950 This happens if I1DEST is mentioned in I2 and dies there, and
2951 has disappeared from the new pattern. */
2952 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2954 && dead_or_set_p (i2, i1dest)
2955 && !reg_overlap_mentioned_p (i1dest, newpat))
2956 /* Before we can do this substitution, we must redo the test done
2957 above (see detailed comments there) that ensures that I1DEST
2958 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2959 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2966 subst_low_luid = DF_INSN_LUID (i1);
2967 newpat = subst (newpat, i1dest, i1src, 0, 0);
2971 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2972 to count all the ways that I2SRC and I1SRC can be used. */
2973 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2974 && i2_is_used + added_sets_2 > 1)
2975 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2976 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2978 /* Fail if we tried to make a new register. */
2979 || max_reg_num () != maxreg
2980 /* Fail if we couldn't do something and have a CLOBBER. */
2981 || GET_CODE (newpat) == CLOBBER
2982 /* Fail if this new pattern is a MULT and we didn't have one before
2983 at the outer level. */
2984 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2991 /* If the actions of the earlier insns must be kept
2992 in addition to substituting them into the latest one,
2993 we must make a new PARALLEL for the latest insn
2994 to hold additional the SETs. */
2996 if (added_sets_1 || added_sets_2)
3000 if (GET_CODE (newpat) == PARALLEL)
3002 rtvec old = XVEC (newpat, 0);
3003 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
3004 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3005 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3006 sizeof (old->elem[0]) * old->num_elem);
3011 total_sets = 1 + added_sets_1 + added_sets_2;
3012 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3013 XVECEXP (newpat, 0, 0) = old;
3017 XVECEXP (newpat, 0, --total_sets) = i1pat;
3021 /* If there is no I1, use I2's body as is. We used to also not do
3022 the subst call below if I2 was substituted into I3,
3023 but that could lose a simplification. */
3025 XVECEXP (newpat, 0, --total_sets) = i2pat;
3027 /* See comment where i2pat is assigned. */
3028 XVECEXP (newpat, 0, --total_sets)
3029 = subst (i2pat, i1dest, i1src, 0, 0);
3033 /* We come here when we are replacing a destination in I2 with the
3034 destination of I3. */
3035 validate_replacement:
3037 /* Note which hard regs this insn has as inputs. */
3038 mark_used_regs_combine (newpat);
3040 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3041 consider splitting this pattern, we might need these clobbers. */
3042 if (i1 && GET_CODE (newpat) == PARALLEL
3043 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3045 int len = XVECLEN (newpat, 0);
3047 newpat_vec_with_clobbers = rtvec_alloc (len);
3048 for (i = 0; i < len; i++)
3049 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3052 /* Is the result of combination a valid instruction? */
3053 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3055 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3056 the second SET's destination is a register that is unused and isn't
3057 marked as an instruction that might trap in an EH region. In that case,
3058 we just need the first SET. This can occur when simplifying a divmod
3059 insn. We *must* test for this case here because the code below that
3060 splits two independent SETs doesn't handle this case correctly when it
3061 updates the register status.
3063 It's pointless doing this if we originally had two sets, one from
3064 i3, and one from i2. Combining then splitting the parallel results
3065 in the original i2 again plus an invalid insn (which we delete).
3066 The net effect is only to move instructions around, which makes
3067 debug info less accurate.
3069 Also check the case where the first SET's destination is unused.
3070 That would not cause incorrect code, but does cause an unneeded
3073 if (insn_code_number < 0
3074 && !(added_sets_2 && i1 == 0)
3075 && GET_CODE (newpat) == PARALLEL
3076 && XVECLEN (newpat, 0) == 2
3077 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3078 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3079 && asm_noperands (newpat) < 0)
3081 rtx set0 = XVECEXP (newpat, 0, 0);
3082 rtx set1 = XVECEXP (newpat, 0, 1);
3084 if (((REG_P (SET_DEST (set1))
3085 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3086 || (GET_CODE (SET_DEST (set1)) == SUBREG
3087 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3088 && insn_nothrow_p (i3)
3089 && !side_effects_p (SET_SRC (set1)))
3092 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3095 else if (((REG_P (SET_DEST (set0))
3096 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3097 || (GET_CODE (SET_DEST (set0)) == SUBREG
3098 && find_reg_note (i3, REG_UNUSED,
3099 SUBREG_REG (SET_DEST (set0)))))
3100 && insn_nothrow_p (i3)
3101 && !side_effects_p (SET_SRC (set0)))
3104 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3106 if (insn_code_number >= 0)
3107 changed_i3_dest = 1;
3111 /* If we were combining three insns and the result is a simple SET
3112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3113 insns. There are two ways to do this. It can be split using a
3114 machine-specific method (like when you have an addition of a large
3115 constant) or by combine in the function find_split_point. */
3117 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3118 && asm_noperands (newpat) < 0)
3120 rtx parallel, m_split, *split;
3122 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3123 use I2DEST as a scratch register will help. In the latter case,
3124 convert I2DEST to the mode of the source of NEWPAT if we can. */
3126 m_split = combine_split_insns (newpat, i3);
3128 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3129 inputs of NEWPAT. */
3131 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3132 possible to try that as a scratch reg. This would require adding
3133 more code to make it work though. */
3135 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3137 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3139 /* First try to split using the original register as a
3140 scratch register. */
3141 parallel = gen_rtx_PARALLEL (VOIDmode,
3142 gen_rtvec (2, newpat,
3143 gen_rtx_CLOBBER (VOIDmode,
3145 m_split = combine_split_insns (parallel, i3);
3147 /* If that didn't work, try changing the mode of I2DEST if
3150 && new_mode != GET_MODE (i2dest)
3151 && new_mode != VOIDmode
3152 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3154 enum machine_mode old_mode = GET_MODE (i2dest);
3157 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3158 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3161 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3162 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3165 parallel = (gen_rtx_PARALLEL
3167 gen_rtvec (2, newpat,
3168 gen_rtx_CLOBBER (VOIDmode,
3170 m_split = combine_split_insns (parallel, i3);
3173 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3177 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3178 buf = undobuf.undos;
3179 undobuf.undos = buf->next;
3180 buf->next = undobuf.frees;
3181 undobuf.frees = buf;
3185 i2scratch = m_split != 0;
3188 /* If recog_for_combine has discarded clobbers, try to use them
3189 again for the split. */
3190 if (m_split == 0 && newpat_vec_with_clobbers)
3192 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3193 m_split = combine_split_insns (parallel, i3);
3196 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3198 m_split = PATTERN (m_split);
3199 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3200 if (insn_code_number >= 0)
3203 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3204 && (next_real_insn (i2) == i3
3205 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3208 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3209 newi2pat = PATTERN (m_split);
3211 i3set = single_set (NEXT_INSN (m_split));
3212 i2set = single_set (m_split);
3214 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3216 /* If I2 or I3 has multiple SETs, we won't know how to track
3217 register status, so don't use these insns. If I2's destination
3218 is used between I2 and I3, we also can't use these insns. */
3220 if (i2_code_number >= 0 && i2set && i3set
3221 && (next_real_insn (i2) == i3
3222 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3223 insn_code_number = recog_for_combine (&newi3pat, i3,
3225 if (insn_code_number >= 0)
3228 /* It is possible that both insns now set the destination of I3.
3229 If so, we must show an extra use of it. */
3231 if (insn_code_number >= 0)
3233 rtx new_i3_dest = SET_DEST (i3set);
3234 rtx new_i2_dest = SET_DEST (i2set);
3236 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3237 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3238 || GET_CODE (new_i3_dest) == SUBREG)
3239 new_i3_dest = XEXP (new_i3_dest, 0);
3241 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3242 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3243 || GET_CODE (new_i2_dest) == SUBREG)
3244 new_i2_dest = XEXP (new_i2_dest, 0);
3246 if (REG_P (new_i3_dest)
3247 && REG_P (new_i2_dest)
3248 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3249 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3253 /* If we can split it and use I2DEST, go ahead and see if that
3254 helps things be recognized. Verify that none of the registers
3255 are set between I2 and I3. */
3256 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3260 /* We need I2DEST in the proper mode. If it is a hard register
3261 or the only use of a pseudo, we can change its mode.
3262 Make sure we don't change a hard register to have a mode that
3263 isn't valid for it, or change the number of registers. */
3264 && (GET_MODE (*split) == GET_MODE (i2dest)
3265 || GET_MODE (*split) == VOIDmode
3266 || can_change_dest_mode (i2dest, added_sets_2,
3268 && (next_real_insn (i2) == i3
3269 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3270 /* We can't overwrite I2DEST if its value is still used by
3272 && ! reg_referenced_p (i2dest, newpat))
3274 rtx newdest = i2dest;
3275 enum rtx_code split_code = GET_CODE (*split);
3276 enum machine_mode split_mode = GET_MODE (*split);
3277 bool subst_done = false;
3278 newi2pat = NULL_RTX;
3282 /* Get NEWDEST as a register in the proper mode. We have already
3283 validated that we can do this. */
3284 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3286 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3287 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3290 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3291 newdest = regno_reg_rtx[REGNO (i2dest)];
3295 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3296 an ASHIFT. This can occur if it was inside a PLUS and hence
3297 appeared to be a memory address. This is a kludge. */
3298 if (split_code == MULT
3299 && CONST_INT_P (XEXP (*split, 1))
3300 && INTVAL (XEXP (*split, 1)) > 0
3301 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3303 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3304 XEXP (*split, 0), GEN_INT (i)));
3305 /* Update split_code because we may not have a multiply
3307 split_code = GET_CODE (*split);
3310 #ifdef INSN_SCHEDULING
3311 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3312 be written as a ZERO_EXTEND. */
3313 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3315 #ifdef LOAD_EXTEND_OP
3316 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3317 what it really is. */
3318 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3320 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3321 SUBREG_REG (*split)));
3324 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3325 SUBREG_REG (*split)));
3329 /* Attempt to split binary operators using arithmetic identities. */
3330 if (BINARY_P (SET_SRC (newpat))
3331 && split_mode == GET_MODE (SET_SRC (newpat))
3332 && ! side_effects_p (SET_SRC (newpat)))
3334 rtx setsrc = SET_SRC (newpat);
3335 enum machine_mode mode = GET_MODE (setsrc);
3336 enum rtx_code code = GET_CODE (setsrc);
3337 rtx src_op0 = XEXP (setsrc, 0);
3338 rtx src_op1 = XEXP (setsrc, 1);
3340 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3341 if (rtx_equal_p (src_op0, src_op1))
3343 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3344 SUBST (XEXP (setsrc, 0), newdest);
3345 SUBST (XEXP (setsrc, 1), newdest);
3348 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3349 else if ((code == PLUS || code == MULT)
3350 && GET_CODE (src_op0) == code
3351 && GET_CODE (XEXP (src_op0, 0)) == code
3352 && (INTEGRAL_MODE_P (mode)
3353 || (FLOAT_MODE_P (mode)
3354 && flag_unsafe_math_optimizations)))
3356 rtx p = XEXP (XEXP (src_op0, 0), 0);
3357 rtx q = XEXP (XEXP (src_op0, 0), 1);
3358 rtx r = XEXP (src_op0, 1);
3361 /* Split both "((X op Y) op X) op Y" and
3362 "((X op Y) op Y) op X" as "T op T" where T is
3364 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3365 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3367 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3369 SUBST (XEXP (setsrc, 0), newdest);
3370 SUBST (XEXP (setsrc, 1), newdest);
3373 /* Split "((X op X) op Y) op Y)" as "T op T" where
3375 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3377 rtx tmp = simplify_gen_binary (code, mode, p, r);
3378 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3379 SUBST (XEXP (setsrc, 0), newdest);
3380 SUBST (XEXP (setsrc, 1), newdest);
3388 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3389 SUBST (*split, newdest);
3392 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3394 /* recog_for_combine might have added CLOBBERs to newi2pat.
3395 Make sure NEWPAT does not depend on the clobbered regs. */
3396 if (GET_CODE (newi2pat) == PARALLEL)
3397 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3398 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3400 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3401 if (reg_overlap_mentioned_p (reg, newpat))
3408 /* If the split point was a MULT and we didn't have one before,
3409 don't use one now. */
3410 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3411 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3415 /* Check for a case where we loaded from memory in a narrow mode and
3416 then sign extended it, but we need both registers. In that case,
3417 we have a PARALLEL with both loads from the same memory location.
3418 We can split this into a load from memory followed by a register-register
3419 copy. This saves at least one insn, more if register allocation can
3422 We cannot do this if the destination of the first assignment is a
3423 condition code register or cc0. We eliminate this case by making sure
3424 the SET_DEST and SET_SRC have the same mode.
3426 We cannot do this if the destination of the second assignment is
3427 a register that we have already assumed is zero-extended. Similarly
3428 for a SUBREG of such a register. */
3430 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3431 && GET_CODE (newpat) == PARALLEL
3432 && XVECLEN (newpat, 0) == 2
3433 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3434 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3435 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3436 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3437 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3438 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3439 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3440 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3442 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3443 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3444 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3446 && VEC_index (reg_stat_type, reg_stat,
3447 REGNO (temp))->nonzero_bits != 0
3448 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3449 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3450 && (VEC_index (reg_stat_type, reg_stat,
3451 REGNO (temp))->nonzero_bits
3452 != GET_MODE_MASK (word_mode))))
3453 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3454 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3456 && VEC_index (reg_stat_type, reg_stat,
3457 REGNO (temp))->nonzero_bits != 0
3458 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3459 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3460 && (VEC_index (reg_stat_type, reg_stat,
3461 REGNO (temp))->nonzero_bits
3462 != GET_MODE_MASK (word_mode)))))
3463 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3464 SET_SRC (XVECEXP (newpat, 0, 1)))
3465 && ! find_reg_note (i3, REG_UNUSED,
3466 SET_DEST (XVECEXP (newpat, 0, 0))))
3470 newi2pat = XVECEXP (newpat, 0, 0);
3471 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3472 newpat = XVECEXP (newpat, 0, 1);
3473 SUBST (SET_SRC (newpat),
3474 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3475 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3477 if (i2_code_number >= 0)
3478 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3480 if (insn_code_number >= 0)
3484 /* Similarly, check for a case where we have a PARALLEL of two independent
3485 SETs but we started with three insns. In this case, we can do the sets
3486 as two separate insns. This case occurs when some SET allows two
3487 other insns to combine, but the destination of that SET is still live. */
3489 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3490 && GET_CODE (newpat) == PARALLEL
3491 && XVECLEN (newpat, 0) == 2
3492 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3493 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3494 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3495 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3496 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3497 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3498 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3500 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3501 XVECEXP (newpat, 0, 0))
3502 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3503 XVECEXP (newpat, 0, 1))
3504 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3505 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3507 /* We cannot split the parallel into two sets if both sets
3509 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3510 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3514 /* Normally, it doesn't matter which of the two is done first,
3515 but it does if one references cc0. In that case, it has to
3518 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3520 newi2pat = XVECEXP (newpat, 0, 0);
3521 newpat = XVECEXP (newpat, 0, 1);
3526 newi2pat = XVECEXP (newpat, 0, 1);
3527 newpat = XVECEXP (newpat, 0, 0);
3530 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3532 if (i2_code_number >= 0)
3533 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3536 /* If it still isn't recognized, fail and change things back the way they
3538 if ((insn_code_number < 0
3539 /* Is the result a reasonable ASM_OPERANDS? */
3540 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3546 /* If we had to change another insn, make sure it is valid also. */
3547 if (undobuf.other_insn)
3549 CLEAR_HARD_REG_SET (newpat_used_regs);
3551 other_pat = PATTERN (undobuf.other_insn);
3552 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3555 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3563 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3564 they are adjacent to each other or not. */
3566 rtx p = prev_nonnote_insn (i3);
3567 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3568 && sets_cc0_p (newi2pat))
3576 /* Only allow this combination if insn_rtx_costs reports that the
3577 replacement instructions are cheaper than the originals. */
3578 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3584 if (MAY_HAVE_DEBUG_INSNS)
3588 for (undo = undobuf.undos; undo; undo = undo->next)
3589 if (undo->kind == UNDO_MODE)
3591 rtx reg = *undo->where.r;
3592 enum machine_mode new_mode = GET_MODE (reg);
3593 enum machine_mode old_mode = undo->old_contents.m;
3595 /* Temporarily revert mode back. */
3596 adjust_reg_mode (reg, old_mode);
3598 if (reg == i2dest && i2scratch)
3600 /* If we used i2dest as a scratch register with a
3601 different mode, substitute it for the original
3602 i2src while its original mode is temporarily
3603 restored, and then clear i2scratch so that we don't
3604 do it again later. */
3605 propagate_for_debug (i2, i3, reg, i2src, false);
3607 /* Put back the new mode. */
3608 adjust_reg_mode (reg, new_mode);
3612 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3623 last = undobuf.other_insn;
3627 /* We're dealing with a reg that changed mode but not
3628 meaning, so we want to turn it into a subreg for
3629 the new mode. However, because of REG sharing and
3630 because its mode had already changed, we have to do
3631 it in two steps. First, replace any debug uses of
3632 reg, with its original mode temporarily restored,
3633 with this copy we have created; then, replace the
3634 copy with the SUBREG of the original shared reg,
3635 once again changed to the new mode. */
3636 propagate_for_debug (first, last, reg, tempreg, false);
3637 adjust_reg_mode (reg, new_mode);
3638 propagate_for_debug (first, last, tempreg,
3639 lowpart_subreg (old_mode, reg, new_mode),
3645 /* If we will be able to accept this, we have made a
3646 change to the destination of I3. This requires us to
3647 do a few adjustments. */
3649 if (changed_i3_dest)
3651 PATTERN (i3) = newpat;
3652 adjust_for_new_dest (i3);
3655 /* We now know that we can do this combination. Merge the insns and
3656 update the status of registers and LOG_LINKS. */
3658 if (undobuf.other_insn)
3662 PATTERN (undobuf.other_insn) = other_pat;
3664 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3665 are still valid. Then add any non-duplicate notes added by
3666 recog_for_combine. */
3667 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3669 next = XEXP (note, 1);
3671 if (REG_NOTE_KIND (note) == REG_UNUSED
3672 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3673 remove_note (undobuf.other_insn, note);
3676 distribute_notes (new_other_notes, undobuf.other_insn,
3677 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3686 /* I3 now uses what used to be its destination and which is now
3687 I2's destination. This requires us to do a few adjustments. */
3688 PATTERN (i3) = newpat;
3689 adjust_for_new_dest (i3);
3691 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3694 However, some later insn might be using I2's dest and have
3695 a LOG_LINK pointing at I3. We must remove this link.
3696 The simplest way to remove the link is to point it at I1,
3697 which we know will be a NOTE. */
3699 /* newi2pat is usually a SET here; however, recog_for_combine might
3700 have added some clobbers. */
3701 if (GET_CODE (newi2pat) == PARALLEL)
3702 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3704 ni2dest = SET_DEST (newi2pat);
3706 for (insn = NEXT_INSN (i3);
3707 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3708 || insn != BB_HEAD (this_basic_block->next_bb));
3709 insn = NEXT_INSN (insn))
3711 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3713 for (link = LOG_LINKS (insn); link;
3714 link = XEXP (link, 1))
3715 if (XEXP (link, 0) == i3)
3716 XEXP (link, 0) = i1;
3724 rtx i3notes, i2notes, i1notes = 0;
3725 rtx i3links, i2links, i1links = 0;
3728 /* Compute which registers we expect to eliminate. newi2pat may be setting
3729 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3730 same as i3dest, in which case newi2pat may be setting i1dest. */
3731 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3732 || i2dest_in_i2src || i2dest_in_i1src
3735 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3736 || (newi2pat && reg_set_p (i1dest, newi2pat))
3740 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3742 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3743 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3745 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3747 /* Ensure that we do not have something that should not be shared but
3748 occurs multiple times in the new insns. Check this by first
3749 resetting all the `used' flags and then copying anything is shared. */
3751 reset_used_flags (i3notes);
3752 reset_used_flags (i2notes);
3753 reset_used_flags (i1notes);
3754 reset_used_flags (newpat);
3755 reset_used_flags (newi2pat);
3756 if (undobuf.other_insn)
3757 reset_used_flags (PATTERN (undobuf.other_insn));
3759 i3notes = copy_rtx_if_shared (i3notes);
3760 i2notes = copy_rtx_if_shared (i2notes);
3761 i1notes = copy_rtx_if_shared (i1notes);
3762 newpat = copy_rtx_if_shared (newpat);
3763 newi2pat = copy_rtx_if_shared (newi2pat);
3764 if (undobuf.other_insn)
3765 reset_used_flags (PATTERN (undobuf.other_insn));
3767 INSN_CODE (i3) = insn_code_number;
3768 PATTERN (i3) = newpat;
3770 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3772 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3774 reset_used_flags (call_usage);
3775 call_usage = copy_rtx (call_usage);
3778 replace_rtx (call_usage, i2dest, i2src);
3781 replace_rtx (call_usage, i1dest, i1src);
3783 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3786 if (undobuf.other_insn)
3787 INSN_CODE (undobuf.other_insn) = other_code_number;
3789 /* We had one special case above where I2 had more than one set and
3790 we replaced a destination of one of those sets with the destination
3791 of I3. In that case, we have to update LOG_LINKS of insns later
3792 in this basic block. Note that this (expensive) case is rare.
3794 Also, in this case, we must pretend that all REG_NOTEs for I2
3795 actually came from I3, so that REG_UNUSED notes from I2 will be
3796 properly handled. */
3798 if (i3_subst_into_i2)
3800 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3801 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3802 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3803 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3804 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3805 && ! find_reg_note (i2, REG_UNUSED,
3806 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3807 for (temp = NEXT_INSN (i2);
3808 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3809 || BB_HEAD (this_basic_block) != temp);
3810 temp = NEXT_INSN (temp))
3811 if (temp != i3 && INSN_P (temp))
3812 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3813 if (XEXP (link, 0) == i2)
3814 XEXP (link, 0) = i3;
3819 while (XEXP (link, 1))
3820 link = XEXP (link, 1);
3821 XEXP (link, 1) = i2notes;
3835 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3836 propagate_for_debug (i2, i3, i2dest, i2src, false);
3837 INSN_CODE (i2) = i2_code_number;
3838 PATTERN (i2) = newi2pat;
3842 if (MAY_HAVE_DEBUG_INSNS && i2src)
3843 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3844 SET_INSN_DELETED (i2);
3851 if (MAY_HAVE_DEBUG_INSNS)
3852 propagate_for_debug (i1, i3, i1dest, i1src, false);
3853 SET_INSN_DELETED (i1);
3856 /* Get death notes for everything that is now used in either I3 or
3857 I2 and used to die in a previous insn. If we built two new
3858 patterns, move from I1 to I2 then I2 to I3 so that we get the
3859 proper movement on registers that I2 modifies. */
3863 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3864 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3867 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3870 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3872 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3875 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3878 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3881 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3884 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3885 know these are REG_UNUSED and want them to go to the desired insn,
3886 so we always pass it as i3. */
3888 if (newi2pat && new_i2_notes)
3889 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3892 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3894 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3895 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3896 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3897 in that case, it might delete I2. Similarly for I2 and I1.
3898 Show an additional death due to the REG_DEAD note we make here. If
3899 we discard it in distribute_notes, we will decrement it again. */
3903 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3904 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3906 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3908 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3910 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3914 if (i2dest_in_i2src)
3916 if (newi2pat && reg_set_p (i2dest, newi2pat))
3917 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3918 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3920 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3921 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3922 NULL_RTX, NULL_RTX);
3925 if (i1dest_in_i1src)
3927 if (newi2pat && reg_set_p (i1dest, newi2pat))
3928 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3929 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3931 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3932 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3933 NULL_RTX, NULL_RTX);
3936 distribute_links (i3links);
3937 distribute_links (i2links);
3938 distribute_links (i1links);
3943 rtx i2_insn = 0, i2_val = 0, set;
3945 /* The insn that used to set this register doesn't exist, and
3946 this life of the register may not exist either. See if one of
3947 I3's links points to an insn that sets I2DEST. If it does,
3948 that is now the last known value for I2DEST. If we don't update
3949 this and I2 set the register to a value that depended on its old
3950 contents, we will get confused. If this insn is used, thing
3951 will be set correctly in combine_instructions. */
3953 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3954 if ((set = single_set (XEXP (link, 0))) != 0
3955 && rtx_equal_p (i2dest, SET_DEST (set)))
3956 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3958 record_value_for_reg (i2dest, i2_insn, i2_val);
3960 /* If the reg formerly set in I2 died only once and that was in I3,
3961 zero its use count so it won't make `reload' do any work. */
3963 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3964 && ! i2dest_in_i2src)
3966 regno = REGNO (i2dest);
3967 INC_REG_N_SETS (regno, -1);
3971 if (i1 && REG_P (i1dest))
3974 rtx i1_insn = 0, i1_val = 0, set;
3976 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3977 if ((set = single_set (XEXP (link, 0))) != 0
3978 && rtx_equal_p (i1dest, SET_DEST (set)))
3979 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3981 record_value_for_reg (i1dest, i1_insn, i1_val);
3983 regno = REGNO (i1dest);
3984 if (! added_sets_1 && ! i1dest_in_i1src)
3985 INC_REG_N_SETS (regno, -1);
3988 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3989 been made to this insn. The order of
3990 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3991 can affect nonzero_bits of newpat */
3993 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3994 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3997 if (undobuf.other_insn != NULL_RTX)
4001 fprintf (dump_file, "modifying other_insn ");
4002 dump_insn_slim (dump_file, undobuf.other_insn);
4004 df_insn_rescan (undobuf.other_insn);
4007 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4011 fprintf (dump_file, "modifying insn i1 ");
4012 dump_insn_slim (dump_file, i1);
4014 df_insn_rescan (i1);
4017 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4021 fprintf (dump_file, "modifying insn i2 ");
4022 dump_insn_slim (dump_file, i2);
4024 df_insn_rescan (i2);
4027 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4031 fprintf (dump_file, "modifying insn i3 ");
4032 dump_insn_slim (dump_file, i3);
4034 df_insn_rescan (i3);
4037 /* Set new_direct_jump_p if a new return or simple jump instruction
4038 has been created. Adjust the CFG accordingly. */
4040 if (returnjump_p (i3) || any_uncondjump_p (i3))
4042 *new_direct_jump_p = 1;
4043 mark_jump_label (PATTERN (i3), i3, 0);
4044 update_cfg_for_uncondjump (i3);
4047 if (undobuf.other_insn != NULL_RTX
4048 && (returnjump_p (undobuf.other_insn)
4049 || any_uncondjump_p (undobuf.other_insn)))
4051 *new_direct_jump_p = 1;
4052 update_cfg_for_uncondjump (undobuf.other_insn);
4055 /* A noop might also need cleaning up of CFG, if it comes from the
4056 simplification of a jump. */
4057 if (GET_CODE (newpat) == SET
4058 && SET_SRC (newpat) == pc_rtx
4059 && SET_DEST (newpat) == pc_rtx)
4061 *new_direct_jump_p = 1;
4062 update_cfg_for_uncondjump (i3);
4065 combine_successes++;
4068 if (added_links_insn
4069 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4070 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4071 return added_links_insn;
4073 return newi2pat ? i2 : i3;
4076 /* Undo all the modifications recorded in undobuf. */
4081 struct undo *undo, *next;
4083 for (undo = undobuf.undos; undo; undo = next)
4089 *undo->where.r = undo->old_contents.r;
4092 *undo->where.i = undo->old_contents.i;
4095 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4101 undo->next = undobuf.frees;
4102 undobuf.frees = undo;
4108 /* We've committed to accepting the changes we made. Move all
4109 of the undos to the free list. */
4114 struct undo *undo, *next;
4116 for (undo = undobuf.undos; undo; undo = next)
4119 undo->next = undobuf.frees;
4120 undobuf.frees = undo;
4125 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4126 where we have an arithmetic expression and return that point. LOC will
4129 try_combine will call this function to see if an insn can be split into
4133 find_split_point (rtx *loc, rtx insn)
4136 enum rtx_code code = GET_CODE (x);
4138 unsigned HOST_WIDE_INT len = 0;
4139 HOST_WIDE_INT pos = 0;
4141 rtx inner = NULL_RTX;
4143 /* First special-case some codes. */
4147 #ifdef INSN_SCHEDULING
4148 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4150 if (MEM_P (SUBREG_REG (x)))
4153 return find_split_point (&SUBREG_REG (x), insn);
4157 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4158 using LO_SUM and HIGH. */
4159 if (GET_CODE (XEXP (x, 0)) == CONST
4160 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4163 gen_rtx_LO_SUM (Pmode,
4164 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
4166 return &XEXP (XEXP (x, 0), 0);
4170 /* If we have a PLUS whose second operand is a constant and the
4171 address is not valid, perhaps will can split it up using
4172 the machine-specific way to split large constants. We use
4173 the first pseudo-reg (one of the virtual regs) as a placeholder;
4174 it will not remain in the result. */
4175 if (GET_CODE (XEXP (x, 0)) == PLUS
4176 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4177 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4178 MEM_ADDR_SPACE (x)))
4180 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4181 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4185 /* This should have produced two insns, each of which sets our
4186 placeholder. If the source of the second is a valid address,
4187 we can make put both sources together and make a split point
4191 && NEXT_INSN (seq) != NULL_RTX
4192 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4193 && NONJUMP_INSN_P (seq)
4194 && GET_CODE (PATTERN (seq)) == SET
4195 && SET_DEST (PATTERN (seq)) == reg
4196 && ! reg_mentioned_p (reg,
4197 SET_SRC (PATTERN (seq)))
4198 && NONJUMP_INSN_P (NEXT_INSN (seq))
4199 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4200 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4201 && memory_address_addr_space_p
4202 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4203 MEM_ADDR_SPACE (x)))
4205 rtx src1 = SET_SRC (PATTERN (seq));
4206 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4208 /* Replace the placeholder in SRC2 with SRC1. If we can
4209 find where in SRC2 it was placed, that can become our
4210 split point and we can replace this address with SRC2.
4211 Just try two obvious places. */
4213 src2 = replace_rtx (src2, reg, src1);
4215 if (XEXP (src2, 0) == src1)
4216 split = &XEXP (src2, 0);
4217 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4218 && XEXP (XEXP (src2, 0), 0) == src1)
4219 split = &XEXP (XEXP (src2, 0), 0);
4223 SUBST (XEXP (x, 0), src2);
4228 /* If that didn't work, perhaps the first operand is complex and
4229 needs to be computed separately, so make a split point there.
4230 This will occur on machines that just support REG + CONST
4231 and have a constant moved through some previous computation. */
4233 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4234 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4235 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4236 return &XEXP (XEXP (x, 0), 0);
4239 /* If we have a PLUS whose first operand is complex, try computing it
4240 separately by making a split there. */
4241 if (GET_CODE (XEXP (x, 0)) == PLUS
4242 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4244 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4245 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4246 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4247 return &XEXP (XEXP (x, 0), 0);
4252 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4253 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4254 we need to put the operand into a register. So split at that
4257 if (SET_DEST (x) == cc0_rtx
4258 && GET_CODE (SET_SRC (x)) != COMPARE
4259 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4260 && !OBJECT_P (SET_SRC (x))
4261 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4262 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4263 return &SET_SRC (x);
4266 /* See if we can split SET_SRC as it stands. */
4267 split = find_split_point (&SET_SRC (x), insn);
4268 if (split && split != &SET_SRC (x))
4271 /* See if we can split SET_DEST as it stands. */
4272 split = find_split_point (&SET_DEST (x), insn);
4273 if (split && split != &SET_DEST (x))
4276 /* See if this is a bitfield assignment with everything constant. If
4277 so, this is an IOR of an AND, so split it into that. */
4278 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4279 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4280 <= HOST_BITS_PER_WIDE_INT)
4281 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4282 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4283 && CONST_INT_P (SET_SRC (x))
4284 && ((INTVAL (XEXP (SET_DEST (x), 1))
4285 + INTVAL (XEXP (SET_DEST (x), 2)))
4286 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4287 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4289 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4290 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4291 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4292 rtx dest = XEXP (SET_DEST (x), 0);
4293 enum machine_mode mode = GET_MODE (dest);
4294 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4297 if (BITS_BIG_ENDIAN)
4298 pos = GET_MODE_BITSIZE (mode) - len - pos;
4300 or_mask = gen_int_mode (src << pos, mode);
4303 simplify_gen_binary (IOR, mode, dest, or_mask));
4306 rtx negmask = gen_int_mode (~(mask << pos), mode);
4308 simplify_gen_binary (IOR, mode,
4309 simplify_gen_binary (AND, mode,
4314 SUBST (SET_DEST (x), dest);
4316 split = find_split_point (&SET_SRC (x), insn);
4317 if (split && split != &SET_SRC (x))
4321 /* Otherwise, see if this is an operation that we can split into two.
4322 If so, try to split that. */
4323 code = GET_CODE (SET_SRC (x));
4328 /* If we are AND'ing with a large constant that is only a single
4329 bit and the result is only being used in a context where we
4330 need to know if it is zero or nonzero, replace it with a bit
4331 extraction. This will avoid the large constant, which might
4332 have taken more than one insn to make. If the constant were
4333 not a valid argument to the AND but took only one insn to make,
4334 this is no worse, but if it took more than one insn, it will
4337 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4338 && REG_P (XEXP (SET_SRC (x), 0))
4339 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4340 && REG_P (SET_DEST (x))
4341 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4342 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4343 && XEXP (*split, 0) == SET_DEST (x)
4344 && XEXP (*split, 1) == const0_rtx)
4346 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4347 XEXP (SET_SRC (x), 0),
4348 pos, NULL_RTX, 1, 1, 0, 0);
4349 if (extraction != 0)
4351 SUBST (SET_SRC (x), extraction);
4352 return find_split_point (loc, insn);
4358 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4359 is known to be on, this can be converted into a NEG of a shift. */
4360 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4361 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4362 && 1 <= (pos = exact_log2
4363 (nonzero_bits (XEXP (SET_SRC (x), 0),
4364 GET_MODE (XEXP (SET_SRC (x), 0))))))
4366 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4370 gen_rtx_LSHIFTRT (mode,
4371 XEXP (SET_SRC (x), 0),
4374 split = find_split_point (&SET_SRC (x), insn);
4375 if (split && split != &SET_SRC (x))
4381 inner = XEXP (SET_SRC (x), 0);
4383 /* We can't optimize if either mode is a partial integer
4384 mode as we don't know how many bits are significant
4386 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4387 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4391 len = GET_MODE_BITSIZE (GET_MODE (inner));
4397 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4398 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4400 inner = XEXP (SET_SRC (x), 0);
4401 len = INTVAL (XEXP (SET_SRC (x), 1));
4402 pos = INTVAL (XEXP (SET_SRC (x), 2));
4404 if (BITS_BIG_ENDIAN)
4405 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4406 unsignedp = (code == ZERO_EXTRACT);
4414 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4416 enum machine_mode mode = GET_MODE (SET_SRC (x));
4418 /* For unsigned, we have a choice of a shift followed by an
4419 AND or two shifts. Use two shifts for field sizes where the
4420 constant might be too large. We assume here that we can
4421 always at least get 8-bit constants in an AND insn, which is
4422 true for every current RISC. */
4424 if (unsignedp && len <= 8)
4429 (mode, gen_lowpart (mode, inner),
4431 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4433 split = find_split_point (&SET_SRC (x), insn);
4434 if (split && split != &SET_SRC (x))
4441 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4442 gen_rtx_ASHIFT (mode,
4443 gen_lowpart (mode, inner),
4444 GEN_INT (GET_MODE_BITSIZE (mode)
4446 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4448 split = find_split_point (&SET_SRC (x), insn);
4449 if (split && split != &SET_SRC (x))
4454 /* See if this is a simple operation with a constant as the second
4455 operand. It might be that this constant is out of range and hence
4456 could be used as a split point. */
4457 if (BINARY_P (SET_SRC (x))
4458 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4459 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4460 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4461 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4462 return &XEXP (SET_SRC (x), 1);
4464 /* Finally, see if this is a simple operation with its first operand
4465 not in a register. The operation might require this operand in a
4466 register, so return it as a split point. We can always do this
4467 because if the first operand were another operation, we would have
4468 already found it as a split point. */
4469 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4470 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4471 return &XEXP (SET_SRC (x), 0);
4477 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4478 it is better to write this as (not (ior A B)) so we can split it.
4479 Similarly for IOR. */
4480 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4483 gen_rtx_NOT (GET_MODE (x),
4484 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4486 XEXP (XEXP (x, 0), 0),
4487 XEXP (XEXP (x, 1), 0))));
4488 return find_split_point (loc, insn);
4491 /* Many RISC machines have a large set of logical insns. If the
4492 second operand is a NOT, put it first so we will try to split the
4493 other operand first. */
4494 if (GET_CODE (XEXP (x, 1)) == NOT)
4496 rtx tem = XEXP (x, 0);
4497 SUBST (XEXP (x, 0), XEXP (x, 1));
4498 SUBST (XEXP (x, 1), tem);
4506 /* Otherwise, select our actions depending on our rtx class. */
4507 switch (GET_RTX_CLASS (code))
4509 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4511 split = find_split_point (&XEXP (x, 2), insn);
4514 /* ... fall through ... */
4516 case RTX_COMM_ARITH:
4518 case RTX_COMM_COMPARE:
4519 split = find_split_point (&XEXP (x, 1), insn);
4522 /* ... fall through ... */
4524 /* Some machines have (and (shift ...) ...) insns. If X is not
4525 an AND, but XEXP (X, 0) is, use it as our split point. */
4526 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4527 return &XEXP (x, 0);
4529 split = find_split_point (&XEXP (x, 0), insn);
4535 /* Otherwise, we don't have a split point. */
4540 /* Throughout X, replace FROM with TO, and return the result.
4541 The result is TO if X is FROM;
4542 otherwise the result is X, but its contents may have been modified.
4543 If they were modified, a record was made in undobuf so that
4544 undo_all will (among other things) return X to its original state.
4546 If the number of changes necessary is too much to record to undo,
4547 the excess changes are not made, so the result is invalid.
4548 The changes already made can still be undone.
4549 undobuf.num_undo is incremented for such changes, so by testing that
4550 the caller can tell whether the result is valid.
4552 `n_occurrences' is incremented each time FROM is replaced.
4554 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4556 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4557 by copying if `n_occurrences' is nonzero. */
4560 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4562 enum rtx_code code = GET_CODE (x);
4563 enum machine_mode op0_mode = VOIDmode;
4568 /* Two expressions are equal if they are identical copies of a shared
4569 RTX or if they are both registers with the same register number
4572 #define COMBINE_RTX_EQUAL_P(X,Y) \
4574 || (REG_P (X) && REG_P (Y) \
4575 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4577 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4580 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4583 /* If X and FROM are the same register but different modes, they
4584 will not have been seen as equal above. However, the log links code
4585 will make a LOG_LINKS entry for that case. If we do nothing, we
4586 will try to rerecognize our original insn and, when it succeeds,
4587 we will delete the feeding insn, which is incorrect.
4589 So force this insn not to match in this (rare) case. */
4590 if (! in_dest && code == REG && REG_P (from)
4591 && reg_overlap_mentioned_p (x, from))
4592 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4594 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4595 of which may contain things that can be combined. */
4596 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4599 /* It is possible to have a subexpression appear twice in the insn.
4600 Suppose that FROM is a register that appears within TO.
4601 Then, after that subexpression has been scanned once by `subst',
4602 the second time it is scanned, TO may be found. If we were
4603 to scan TO here, we would find FROM within it and create a
4604 self-referent rtl structure which is completely wrong. */
4605 if (COMBINE_RTX_EQUAL_P (x, to))
4608 /* Parallel asm_operands need special attention because all of the
4609 inputs are shared across the arms. Furthermore, unsharing the
4610 rtl results in recognition failures. Failure to handle this case
4611 specially can result in circular rtl.
4613 Solve this by doing a normal pass across the first entry of the
4614 parallel, and only processing the SET_DESTs of the subsequent
4617 if (code == PARALLEL
4618 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4619 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4621 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4623 /* If this substitution failed, this whole thing fails. */
4624 if (GET_CODE (new_rtx) == CLOBBER
4625 && XEXP (new_rtx, 0) == const0_rtx)
4628 SUBST (XVECEXP (x, 0, 0), new_rtx);
4630 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4632 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4635 && GET_CODE (dest) != CC0
4636 && GET_CODE (dest) != PC)
4638 new_rtx = subst (dest, from, to, 0, unique_copy);
4640 /* If this substitution failed, this whole thing fails. */
4641 if (GET_CODE (new_rtx) == CLOBBER
4642 && XEXP (new_rtx, 0) == const0_rtx)
4645 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4651 len = GET_RTX_LENGTH (code);
4652 fmt = GET_RTX_FORMAT (code);
4654 /* We don't need to process a SET_DEST that is a register, CC0,
4655 or PC, so set up to skip this common case. All other cases
4656 where we want to suppress replacing something inside a
4657 SET_SRC are handled via the IN_DEST operand. */
4659 && (REG_P (SET_DEST (x))
4660 || GET_CODE (SET_DEST (x)) == CC0
4661 || GET_CODE (SET_DEST (x)) == PC))
4664 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4667 op0_mode = GET_MODE (XEXP (x, 0));
4669 for (i = 0; i < len; i++)
4674 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4676 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4678 new_rtx = (unique_copy && n_occurrences
4679 ? copy_rtx (to) : to);
4684 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4687 /* If this substitution failed, this whole thing
4689 if (GET_CODE (new_rtx) == CLOBBER
4690 && XEXP (new_rtx, 0) == const0_rtx)
4694 SUBST (XVECEXP (x, i, j), new_rtx);
4697 else if (fmt[i] == 'e')
4699 /* If this is a register being set, ignore it. */
4700 new_rtx = XEXP (x, i);
4703 && (((code == SUBREG || code == ZERO_EXTRACT)
4705 || code == STRICT_LOW_PART))
4708 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4710 /* In general, don't install a subreg involving two
4711 modes not tieable. It can worsen register
4712 allocation, and can even make invalid reload
4713 insns, since the reg inside may need to be copied
4714 from in the outside mode, and that may be invalid
4715 if it is an fp reg copied in integer mode.
4717 We allow two exceptions to this: It is valid if
4718 it is inside another SUBREG and the mode of that
4719 SUBREG and the mode of the inside of TO is
4720 tieable and it is valid if X is a SET that copies
4723 if (GET_CODE (to) == SUBREG
4724 && ! MODES_TIEABLE_P (GET_MODE (to),
4725 GET_MODE (SUBREG_REG (to)))
4726 && ! (code == SUBREG
4727 && MODES_TIEABLE_P (GET_MODE (x),
4728 GET_MODE (SUBREG_REG (to))))
4730 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4733 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4735 #ifdef CANNOT_CHANGE_MODE_CLASS
4738 && REGNO (to) < FIRST_PSEUDO_REGISTER
4739 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4742 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4745 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4749 /* If we are in a SET_DEST, suppress most cases unless we
4750 have gone inside a MEM, in which case we want to
4751 simplify the address. We assume here that things that
4752 are actually part of the destination have their inner
4753 parts in the first expression. This is true for SUBREG,
4754 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4755 things aside from REG and MEM that should appear in a
4757 new_rtx = subst (XEXP (x, i), from, to,
4759 && (code == SUBREG || code == STRICT_LOW_PART
4760 || code == ZERO_EXTRACT))
4762 && i == 0), unique_copy);
4764 /* If we found that we will have to reject this combination,
4765 indicate that by returning the CLOBBER ourselves, rather than
4766 an expression containing it. This will speed things up as
4767 well as prevent accidents where two CLOBBERs are considered
4768 to be equal, thus producing an incorrect simplification. */
4770 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4773 if (GET_CODE (x) == SUBREG
4774 && (CONST_INT_P (new_rtx)
4775 || GET_CODE (new_rtx) == CONST_DOUBLE))
4777 enum machine_mode mode = GET_MODE (x);
4779 x = simplify_subreg (GET_MODE (x), new_rtx,
4780 GET_MODE (SUBREG_REG (x)),
4783 x = gen_rtx_CLOBBER (mode, const0_rtx);
4785 else if (CONST_INT_P (new_rtx)
4786 && GET_CODE (x) == ZERO_EXTEND)
4788 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4789 new_rtx, GET_MODE (XEXP (x, 0)));
4793 SUBST (XEXP (x, i), new_rtx);
4798 /* Check if we are loading something from the constant pool via float
4799 extension; in this case we would undo compress_float_constant
4800 optimization and degenerate constant load to an immediate value. */
4801 if (GET_CODE (x) == FLOAT_EXTEND
4802 && MEM_P (XEXP (x, 0))
4803 && MEM_READONLY_P (XEXP (x, 0)))
4805 rtx tmp = avoid_constant_pool_reference (x);
4810 /* Try to simplify X. If the simplification changed the code, it is likely
4811 that further simplification will help, so loop, but limit the number
4812 of repetitions that will be performed. */
4814 for (i = 0; i < 4; i++)
4816 /* If X is sufficiently simple, don't bother trying to do anything
4818 if (code != CONST_INT && code != REG && code != CLOBBER)
4819 x = combine_simplify_rtx (x, op0_mode, in_dest);
4821 if (GET_CODE (x) == code)
4824 code = GET_CODE (x);
4826 /* We no longer know the original mode of operand 0 since we
4827 have changed the form of X) */
4828 op0_mode = VOIDmode;
4834 /* Simplify X, a piece of RTL. We just operate on the expression at the
4835 outer level; call `subst' to simplify recursively. Return the new
4838 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4839 if we are inside a SET_DEST. */
4842 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4844 enum rtx_code code = GET_CODE (x);
4845 enum machine_mode mode = GET_MODE (x);
4849 /* If this is a commutative operation, put a constant last and a complex
4850 expression first. We don't need to do this for comparisons here. */
4851 if (COMMUTATIVE_ARITH_P (x)
4852 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4855 SUBST (XEXP (x, 0), XEXP (x, 1));
4856 SUBST (XEXP (x, 1), temp);
4859 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4860 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4861 things. Check for cases where both arms are testing the same
4864 Don't do anything if all operands are very simple. */
4867 && ((!OBJECT_P (XEXP (x, 0))
4868 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4869 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4870 || (!OBJECT_P (XEXP (x, 1))
4871 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4872 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4874 && (!OBJECT_P (XEXP (x, 0))
4875 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4876 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4878 rtx cond, true_rtx, false_rtx;
4880 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4882 /* If everything is a comparison, what we have is highly unlikely
4883 to be simpler, so don't use it. */
4884 && ! (COMPARISON_P (x)
4885 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4887 rtx cop1 = const0_rtx;
4888 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4890 if (cond_code == NE && COMPARISON_P (cond))
4893 /* Simplify the alternative arms; this may collapse the true and
4894 false arms to store-flag values. Be careful to use copy_rtx
4895 here since true_rtx or false_rtx might share RTL with x as a
4896 result of the if_then_else_cond call above. */
4897 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4898 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4900 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4901 is unlikely to be simpler. */
4902 if (general_operand (true_rtx, VOIDmode)
4903 && general_operand (false_rtx, VOIDmode))
4905 enum rtx_code reversed;
4907 /* Restarting if we generate a store-flag expression will cause
4908 us to loop. Just drop through in this case. */
4910 /* If the result values are STORE_FLAG_VALUE and zero, we can
4911 just make the comparison operation. */
4912 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4913 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4915 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4916 && ((reversed = reversed_comparison_code_parts
4917 (cond_code, cond, cop1, NULL))
4919 x = simplify_gen_relational (reversed, mode, VOIDmode,
4922 /* Likewise, we can make the negate of a comparison operation
4923 if the result values are - STORE_FLAG_VALUE and zero. */
4924 else if (CONST_INT_P (true_rtx)
4925 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4926 && false_rtx == const0_rtx)
4927 x = simplify_gen_unary (NEG, mode,
4928 simplify_gen_relational (cond_code,
4932 else if (CONST_INT_P (false_rtx)
4933 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4934 && true_rtx == const0_rtx
4935 && ((reversed = reversed_comparison_code_parts
4936 (cond_code, cond, cop1, NULL))
4938 x = simplify_gen_unary (NEG, mode,
4939 simplify_gen_relational (reversed,
4944 return gen_rtx_IF_THEN_ELSE (mode,
4945 simplify_gen_relational (cond_code,
4950 true_rtx, false_rtx);
4952 code = GET_CODE (x);
4953 op0_mode = VOIDmode;
4958 /* Try to fold this expression in case we have constants that weren't
4961 switch (GET_RTX_CLASS (code))
4964 if (op0_mode == VOIDmode)
4965 op0_mode = GET_MODE (XEXP (x, 0));
4966 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4969 case RTX_COMM_COMPARE:
4971 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4972 if (cmp_mode == VOIDmode)
4974 cmp_mode = GET_MODE (XEXP (x, 1));
4975 if (cmp_mode == VOIDmode)
4976 cmp_mode = op0_mode;
4978 temp = simplify_relational_operation (code, mode, cmp_mode,
4979 XEXP (x, 0), XEXP (x, 1));
4982 case RTX_COMM_ARITH:
4984 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4986 case RTX_BITFIELD_OPS:
4988 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4989 XEXP (x, 1), XEXP (x, 2));
4998 code = GET_CODE (temp);
4999 op0_mode = VOIDmode;
5000 mode = GET_MODE (temp);
5003 /* First see if we can apply the inverse distributive law. */
5004 if (code == PLUS || code == MINUS
5005 || code == AND || code == IOR || code == XOR)
5007 x = apply_distributive_law (x);
5008 code = GET_CODE (x);
5009 op0_mode = VOIDmode;
5012 /* If CODE is an associative operation not otherwise handled, see if we
5013 can associate some operands. This can win if they are constants or
5014 if they are logically related (i.e. (a & b) & a). */
5015 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5016 || code == AND || code == IOR || code == XOR
5017 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5018 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5019 || (flag_associative_math && FLOAT_MODE_P (mode))))
5021 if (GET_CODE (XEXP (x, 0)) == code)
5023 rtx other = XEXP (XEXP (x, 0), 0);
5024 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5025 rtx inner_op1 = XEXP (x, 1);
5028 /* Make sure we pass the constant operand if any as the second
5029 one if this is a commutative operation. */
5030 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5032 rtx tem = inner_op0;
5033 inner_op0 = inner_op1;
5036 inner = simplify_binary_operation (code == MINUS ? PLUS
5037 : code == DIV ? MULT
5039 mode, inner_op0, inner_op1);
5041 /* For commutative operations, try the other pair if that one
5043 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5045 other = XEXP (XEXP (x, 0), 1);
5046 inner = simplify_binary_operation (code, mode,
5047 XEXP (XEXP (x, 0), 0),
5052 return simplify_gen_binary (code, mode, other, inner);
5056 /* A little bit of algebraic simplification here. */
5060 /* Ensure that our address has any ASHIFTs converted to MULT in case
5061 address-recognizing predicates are called later. */
5062 temp = make_compound_operation (XEXP (x, 0), MEM);
5063 SUBST (XEXP (x, 0), temp);
5067 if (op0_mode == VOIDmode)
5068 op0_mode = GET_MODE (SUBREG_REG (x));
5070 /* See if this can be moved to simplify_subreg. */
5071 if (CONSTANT_P (SUBREG_REG (x))
5072 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5073 /* Don't call gen_lowpart if the inner mode
5074 is VOIDmode and we cannot simplify it, as SUBREG without
5075 inner mode is invalid. */
5076 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5077 || gen_lowpart_common (mode, SUBREG_REG (x))))
5078 return gen_lowpart (mode, SUBREG_REG (x));
5080 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5084 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5090 /* Don't change the mode of the MEM if that would change the meaning
5092 if (MEM_P (SUBREG_REG (x))
5093 && (MEM_VOLATILE_P (SUBREG_REG (x))
5094 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5095 return gen_rtx_CLOBBER (mode, const0_rtx);
5097 /* Note that we cannot do any narrowing for non-constants since
5098 we might have been counting on using the fact that some bits were
5099 zero. We now do this in the SET. */
5104 temp = expand_compound_operation (XEXP (x, 0));
5106 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5107 replaced by (lshiftrt X C). This will convert
5108 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5110 if (GET_CODE (temp) == ASHIFTRT
5111 && CONST_INT_P (XEXP (temp, 1))
5112 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5113 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5114 INTVAL (XEXP (temp, 1)));
5116 /* If X has only a single bit that might be nonzero, say, bit I, convert
5117 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5118 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5119 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5120 or a SUBREG of one since we'd be making the expression more
5121 complex if it was just a register. */
5124 && ! (GET_CODE (temp) == SUBREG
5125 && REG_P (SUBREG_REG (temp)))
5126 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5128 rtx temp1 = simplify_shift_const
5129 (NULL_RTX, ASHIFTRT, mode,
5130 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5131 GET_MODE_BITSIZE (mode) - 1 - i),
5132 GET_MODE_BITSIZE (mode) - 1 - i);
5134 /* If all we did was surround TEMP with the two shifts, we
5135 haven't improved anything, so don't use it. Otherwise,
5136 we are better off with TEMP1. */
5137 if (GET_CODE (temp1) != ASHIFTRT
5138 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5139 || XEXP (XEXP (temp1, 0), 0) != temp)
5145 /* We can't handle truncation to a partial integer mode here
5146 because we don't know the real bitsize of the partial
5148 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5151 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5153 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5154 GET_MODE_MASK (mode), 0));
5156 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5157 whose value is a comparison can be replaced with a subreg if
5158 STORE_FLAG_VALUE permits. */
5159 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5160 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5161 && (temp = get_last_value (XEXP (x, 0)))
5162 && COMPARISON_P (temp))
5163 return gen_lowpart (mode, XEXP (x, 0));
5167 /* (const (const X)) can become (const X). Do it this way rather than
5168 returning the inner CONST since CONST can be shared with a
5170 if (GET_CODE (XEXP (x, 0)) == CONST)
5171 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5176 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5177 can add in an offset. find_split_point will split this address up
5178 again if it doesn't match. */
5179 if (GET_CODE (XEXP (x, 0)) == HIGH
5180 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5186 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5187 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5188 bit-field and can be replaced by either a sign_extend or a
5189 sign_extract. The `and' may be a zero_extend and the two
5190 <c>, -<c> constants may be reversed. */
5191 if (GET_CODE (XEXP (x, 0)) == XOR
5192 && CONST_INT_P (XEXP (x, 1))
5193 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5194 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5195 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5196 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5197 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5198 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5199 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5200 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5201 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5202 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5203 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5204 == (unsigned int) i + 1))))
5205 return simplify_shift_const
5206 (NULL_RTX, ASHIFTRT, mode,
5207 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5208 XEXP (XEXP (XEXP (x, 0), 0), 0),
5209 GET_MODE_BITSIZE (mode) - (i + 1)),
5210 GET_MODE_BITSIZE (mode) - (i + 1));
5212 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5213 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5214 the bitsize of the mode - 1. This allows simplification of
5215 "a = (b & 8) == 0;" */
5216 if (XEXP (x, 1) == constm1_rtx
5217 && !REG_P (XEXP (x, 0))
5218 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5219 && REG_P (SUBREG_REG (XEXP (x, 0))))
5220 && nonzero_bits (XEXP (x, 0), mode) == 1)
5221 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5222 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5223 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5224 GET_MODE_BITSIZE (mode) - 1),
5225 GET_MODE_BITSIZE (mode) - 1);
5227 /* If we are adding two things that have no bits in common, convert
5228 the addition into an IOR. This will often be further simplified,
5229 for example in cases like ((a & 1) + (a & 2)), which can
5232 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5233 && (nonzero_bits (XEXP (x, 0), mode)
5234 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5236 /* Try to simplify the expression further. */
5237 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5238 temp = combine_simplify_rtx (tor, mode, in_dest);
5240 /* If we could, great. If not, do not go ahead with the IOR
5241 replacement, since PLUS appears in many special purpose
5242 address arithmetic instructions. */
5243 if (GET_CODE (temp) != CLOBBER && temp != tor)
5249 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5250 (and <foo> (const_int pow2-1)) */
5251 if (GET_CODE (XEXP (x, 1)) == AND
5252 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5253 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5254 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5255 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5256 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5260 /* If we have (mult (plus A B) C), apply the distributive law and then
5261 the inverse distributive law to see if things simplify. This
5262 occurs mostly in addresses, often when unrolling loops. */
5264 if (GET_CODE (XEXP (x, 0)) == PLUS)
5266 rtx result = distribute_and_simplify_rtx (x, 0);
5271 /* Try simplify a*(b/c) as (a*b)/c. */
5272 if (FLOAT_MODE_P (mode) && flag_associative_math
5273 && GET_CODE (XEXP (x, 0)) == DIV)
5275 rtx tem = simplify_binary_operation (MULT, mode,
5276 XEXP (XEXP (x, 0), 0),
5279 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5284 /* If this is a divide by a power of two, treat it as a shift if
5285 its first operand is a shift. */
5286 if (CONST_INT_P (XEXP (x, 1))
5287 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5288 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5289 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5290 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5291 || GET_CODE (XEXP (x, 0)) == ROTATE
5292 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5293 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5297 case GT: case GTU: case GE: case GEU:
5298 case LT: case LTU: case LE: case LEU:
5299 case UNEQ: case LTGT:
5300 case UNGT: case UNGE:
5301 case UNLT: case UNLE:
5302 case UNORDERED: case ORDERED:
5303 /* If the first operand is a condition code, we can't do anything
5305 if (GET_CODE (XEXP (x, 0)) == COMPARE
5306 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5307 && ! CC0_P (XEXP (x, 0))))
5309 rtx op0 = XEXP (x, 0);
5310 rtx op1 = XEXP (x, 1);
5311 enum rtx_code new_code;
5313 if (GET_CODE (op0) == COMPARE)
5314 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5316 /* Simplify our comparison, if possible. */
5317 new_code = simplify_comparison (code, &op0, &op1);
5319 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5320 if only the low-order bit is possibly nonzero in X (such as when
5321 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5322 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5323 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5326 Remove any ZERO_EXTRACT we made when thinking this was a
5327 comparison. It may now be simpler to use, e.g., an AND. If a
5328 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5329 the call to make_compound_operation in the SET case. */
5331 if (STORE_FLAG_VALUE == 1
5332 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5333 && op1 == const0_rtx
5334 && mode == GET_MODE (op0)
5335 && nonzero_bits (op0, mode) == 1)
5336 return gen_lowpart (mode,
5337 expand_compound_operation (op0));
5339 else if (STORE_FLAG_VALUE == 1
5340 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5341 && op1 == const0_rtx
5342 && mode == GET_MODE (op0)
5343 && (num_sign_bit_copies (op0, mode)
5344 == GET_MODE_BITSIZE (mode)))
5346 op0 = expand_compound_operation (op0);
5347 return simplify_gen_unary (NEG, mode,
5348 gen_lowpart (mode, op0),
5352 else if (STORE_FLAG_VALUE == 1
5353 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5354 && op1 == const0_rtx
5355 && mode == GET_MODE (op0)
5356 && nonzero_bits (op0, mode) == 1)
5358 op0 = expand_compound_operation (op0);
5359 return simplify_gen_binary (XOR, mode,
5360 gen_lowpart (mode, op0),
5364 else if (STORE_FLAG_VALUE == 1
5365 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5366 && op1 == const0_rtx
5367 && mode == GET_MODE (op0)
5368 && (num_sign_bit_copies (op0, mode)
5369 == GET_MODE_BITSIZE (mode)))
5371 op0 = expand_compound_operation (op0);
5372 return plus_constant (gen_lowpart (mode, op0), 1);
5375 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5377 if (STORE_FLAG_VALUE == -1
5378 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5379 && op1 == const0_rtx
5380 && (num_sign_bit_copies (op0, mode)
5381 == GET_MODE_BITSIZE (mode)))
5382 return gen_lowpart (mode,
5383 expand_compound_operation (op0));
5385 else if (STORE_FLAG_VALUE == -1
5386 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5387 && op1 == const0_rtx
5388 && mode == GET_MODE (op0)
5389 && nonzero_bits (op0, mode) == 1)
5391 op0 = expand_compound_operation (op0);
5392 return simplify_gen_unary (NEG, mode,
5393 gen_lowpart (mode, op0),
5397 else if (STORE_FLAG_VALUE == -1
5398 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5399 && op1 == const0_rtx
5400 && mode == GET_MODE (op0)
5401 && (num_sign_bit_copies (op0, mode)
5402 == GET_MODE_BITSIZE (mode)))
5404 op0 = expand_compound_operation (op0);
5405 return simplify_gen_unary (NOT, mode,
5406 gen_lowpart (mode, op0),
5410 /* If X is 0/1, (eq X 0) is X-1. */
5411 else if (STORE_FLAG_VALUE == -1
5412 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5413 && op1 == const0_rtx
5414 && mode == GET_MODE (op0)
5415 && nonzero_bits (op0, mode) == 1)
5417 op0 = expand_compound_operation (op0);
5418 return plus_constant (gen_lowpart (mode, op0), -1);
5421 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5422 one bit that might be nonzero, we can convert (ne x 0) to
5423 (ashift x c) where C puts the bit in the sign bit. Remove any
5424 AND with STORE_FLAG_VALUE when we are done, since we are only
5425 going to test the sign bit. */
5426 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5427 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5428 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5429 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5430 && op1 == const0_rtx
5431 && mode == GET_MODE (op0)
5432 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5434 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5435 expand_compound_operation (op0),
5436 GET_MODE_BITSIZE (mode) - 1 - i);
5437 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5443 /* If the code changed, return a whole new comparison. */
5444 if (new_code != code)
5445 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5447 /* Otherwise, keep this operation, but maybe change its operands.
5448 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5449 SUBST (XEXP (x, 0), op0);
5450 SUBST (XEXP (x, 1), op1);
5455 return simplify_if_then_else (x);
5461 /* If we are processing SET_DEST, we are done. */
5465 return expand_compound_operation (x);
5468 return simplify_set (x);
5472 return simplify_logical (x);
5479 /* If this is a shift by a constant amount, simplify it. */
5480 if (CONST_INT_P (XEXP (x, 1)))
5481 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5482 INTVAL (XEXP (x, 1)));
5484 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5486 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5488 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5500 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5503 simplify_if_then_else (rtx x)
5505 enum machine_mode mode = GET_MODE (x);
5506 rtx cond = XEXP (x, 0);
5507 rtx true_rtx = XEXP (x, 1);
5508 rtx false_rtx = XEXP (x, 2);
5509 enum rtx_code true_code = GET_CODE (cond);
5510 int comparison_p = COMPARISON_P (cond);
5513 enum rtx_code false_code;
5516 /* Simplify storing of the truth value. */
5517 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5518 return simplify_gen_relational (true_code, mode, VOIDmode,
5519 XEXP (cond, 0), XEXP (cond, 1));
5521 /* Also when the truth value has to be reversed. */
5523 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5524 && (reversed = reversed_comparison (cond, mode)))
5527 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5528 in it is being compared against certain values. Get the true and false
5529 comparisons and see if that says anything about the value of each arm. */
5532 && ((false_code = reversed_comparison_code (cond, NULL))
5534 && REG_P (XEXP (cond, 0)))
5537 rtx from = XEXP (cond, 0);
5538 rtx true_val = XEXP (cond, 1);
5539 rtx false_val = true_val;
5542 /* If FALSE_CODE is EQ, swap the codes and arms. */
5544 if (false_code == EQ)
5546 swapped = 1, true_code = EQ, false_code = NE;
5547 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5550 /* If we are comparing against zero and the expression being tested has
5551 only a single bit that might be nonzero, that is its value when it is
5552 not equal to zero. Similarly if it is known to be -1 or 0. */
5554 if (true_code == EQ && true_val == const0_rtx
5555 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5558 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5560 else if (true_code == EQ && true_val == const0_rtx
5561 && (num_sign_bit_copies (from, GET_MODE (from))
5562 == GET_MODE_BITSIZE (GET_MODE (from))))
5565 false_val = constm1_rtx;
5568 /* Now simplify an arm if we know the value of the register in the
5569 branch and it is used in the arm. Be careful due to the potential
5570 of locally-shared RTL. */
5572 if (reg_mentioned_p (from, true_rtx))
5573 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5575 pc_rtx, pc_rtx, 0, 0);
5576 if (reg_mentioned_p (from, false_rtx))
5577 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5579 pc_rtx, pc_rtx, 0, 0);
5581 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5582 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5584 true_rtx = XEXP (x, 1);
5585 false_rtx = XEXP (x, 2);
5586 true_code = GET_CODE (cond);
5589 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5590 reversed, do so to avoid needing two sets of patterns for
5591 subtract-and-branch insns. Similarly if we have a constant in the true
5592 arm, the false arm is the same as the first operand of the comparison, or
5593 the false arm is more complicated than the true arm. */
5596 && reversed_comparison_code (cond, NULL) != UNKNOWN
5597 && (true_rtx == pc_rtx
5598 || (CONSTANT_P (true_rtx)
5599 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5600 || true_rtx == const0_rtx
5601 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5602 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5603 && !OBJECT_P (false_rtx))
5604 || reg_mentioned_p (true_rtx, false_rtx)
5605 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5607 true_code = reversed_comparison_code (cond, NULL);
5608 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5609 SUBST (XEXP (x, 1), false_rtx);
5610 SUBST (XEXP (x, 2), true_rtx);
5612 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5615 /* It is possible that the conditional has been simplified out. */
5616 true_code = GET_CODE (cond);
5617 comparison_p = COMPARISON_P (cond);
5620 /* If the two arms are identical, we don't need the comparison. */
5622 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5625 /* Convert a == b ? b : a to "a". */
5626 if (true_code == EQ && ! side_effects_p (cond)
5627 && !HONOR_NANS (mode)
5628 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5629 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5631 else if (true_code == NE && ! side_effects_p (cond)
5632 && !HONOR_NANS (mode)
5633 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5634 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5637 /* Look for cases where we have (abs x) or (neg (abs X)). */
5639 if (GET_MODE_CLASS (mode) == MODE_INT
5641 && XEXP (cond, 1) == const0_rtx
5642 && GET_CODE (false_rtx) == NEG
5643 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5644 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5645 && ! side_effects_p (true_rtx))
5650 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5654 simplify_gen_unary (NEG, mode,
5655 simplify_gen_unary (ABS, mode, true_rtx, mode),
5661 /* Look for MIN or MAX. */
5663 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5665 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5666 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5667 && ! side_effects_p (cond))
5672 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5675 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5678 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5681 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5686 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5687 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5688 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5689 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5690 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5691 neither 1 or -1, but it isn't worth checking for. */
5693 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5695 && GET_MODE_CLASS (mode) == MODE_INT
5696 && ! side_effects_p (x))
5698 rtx t = make_compound_operation (true_rtx, SET);
5699 rtx f = make_compound_operation (false_rtx, SET);
5700 rtx cond_op0 = XEXP (cond, 0);
5701 rtx cond_op1 = XEXP (cond, 1);
5702 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5703 enum machine_mode m = mode;
5704 rtx z = 0, c1 = NULL_RTX;
5706 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5707 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5708 || GET_CODE (t) == ASHIFT
5709 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5710 && rtx_equal_p (XEXP (t, 0), f))
5711 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5713 /* If an identity-zero op is commutative, check whether there
5714 would be a match if we swapped the operands. */
5715 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5716 || GET_CODE (t) == XOR)
5717 && rtx_equal_p (XEXP (t, 1), f))
5718 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5719 else if (GET_CODE (t) == SIGN_EXTEND
5720 && (GET_CODE (XEXP (t, 0)) == PLUS
5721 || GET_CODE (XEXP (t, 0)) == MINUS
5722 || GET_CODE (XEXP (t, 0)) == IOR
5723 || GET_CODE (XEXP (t, 0)) == XOR
5724 || GET_CODE (XEXP (t, 0)) == ASHIFT
5725 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5726 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5727 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5728 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5729 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5730 && (num_sign_bit_copies (f, GET_MODE (f))
5732 (GET_MODE_BITSIZE (mode)
5733 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5735 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5736 extend_op = SIGN_EXTEND;
5737 m = GET_MODE (XEXP (t, 0));
5739 else if (GET_CODE (t) == SIGN_EXTEND
5740 && (GET_CODE (XEXP (t, 0)) == PLUS
5741 || GET_CODE (XEXP (t, 0)) == IOR
5742 || GET_CODE (XEXP (t, 0)) == XOR)
5743 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5744 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5745 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5746 && (num_sign_bit_copies (f, GET_MODE (f))
5748 (GET_MODE_BITSIZE (mode)
5749 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5751 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5752 extend_op = SIGN_EXTEND;
5753 m = GET_MODE (XEXP (t, 0));
5755 else if (GET_CODE (t) == ZERO_EXTEND
5756 && (GET_CODE (XEXP (t, 0)) == PLUS
5757 || GET_CODE (XEXP (t, 0)) == MINUS
5758 || GET_CODE (XEXP (t, 0)) == IOR
5759 || GET_CODE (XEXP (t, 0)) == XOR
5760 || GET_CODE (XEXP (t, 0)) == ASHIFT
5761 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5762 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5763 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5764 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5765 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5766 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5767 && ((nonzero_bits (f, GET_MODE (f))
5768 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5771 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5772 extend_op = ZERO_EXTEND;
5773 m = GET_MODE (XEXP (t, 0));
5775 else if (GET_CODE (t) == ZERO_EXTEND
5776 && (GET_CODE (XEXP (t, 0)) == PLUS
5777 || GET_CODE (XEXP (t, 0)) == IOR
5778 || GET_CODE (XEXP (t, 0)) == XOR)
5779 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5780 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5781 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5782 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5783 && ((nonzero_bits (f, GET_MODE (f))
5784 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5787 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5788 extend_op = ZERO_EXTEND;
5789 m = GET_MODE (XEXP (t, 0));
5794 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5795 cond_op0, cond_op1),
5796 pc_rtx, pc_rtx, 0, 0);
5797 temp = simplify_gen_binary (MULT, m, temp,
5798 simplify_gen_binary (MULT, m, c1,
5800 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5801 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5803 if (extend_op != UNKNOWN)
5804 temp = simplify_gen_unary (extend_op, mode, temp, m);
5810 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5811 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5812 negation of a single bit, we can convert this operation to a shift. We
5813 can actually do this more generally, but it doesn't seem worth it. */
5815 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5816 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5817 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5818 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5819 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5820 == GET_MODE_BITSIZE (mode))
5821 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5823 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5824 gen_lowpart (mode, XEXP (cond, 0)), i);
5826 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5827 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5828 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5829 && GET_MODE (XEXP (cond, 0)) == mode
5830 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5831 == nonzero_bits (XEXP (cond, 0), mode)
5832 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5833 return XEXP (cond, 0);
5838 /* Simplify X, a SET expression. Return the new expression. */
5841 simplify_set (rtx x)
5843 rtx src = SET_SRC (x);
5844 rtx dest = SET_DEST (x);
5845 enum machine_mode mode
5846 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5850 /* (set (pc) (return)) gets written as (return). */
5851 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5854 /* Now that we know for sure which bits of SRC we are using, see if we can
5855 simplify the expression for the object knowing that we only need the
5858 if (GET_MODE_CLASS (mode) == MODE_INT
5859 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5861 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5862 SUBST (SET_SRC (x), src);
5865 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5866 the comparison result and try to simplify it unless we already have used
5867 undobuf.other_insn. */
5868 if ((GET_MODE_CLASS (mode) == MODE_CC
5869 || GET_CODE (src) == COMPARE
5871 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5872 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5873 && COMPARISON_P (*cc_use)
5874 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5876 enum rtx_code old_code = GET_CODE (*cc_use);
5877 enum rtx_code new_code;
5879 int other_changed = 0;
5880 enum machine_mode compare_mode = GET_MODE (dest);
5882 if (GET_CODE (src) == COMPARE)
5883 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5885 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5887 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5890 new_code = old_code;
5891 else if (!CONSTANT_P (tmp))
5893 new_code = GET_CODE (tmp);
5894 op0 = XEXP (tmp, 0);
5895 op1 = XEXP (tmp, 1);
5899 rtx pat = PATTERN (other_insn);
5900 undobuf.other_insn = other_insn;
5901 SUBST (*cc_use, tmp);
5903 /* Attempt to simplify CC user. */
5904 if (GET_CODE (pat) == SET)
5906 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5907 if (new_rtx != NULL_RTX)
5908 SUBST (SET_SRC (pat), new_rtx);
5911 /* Convert X into a no-op move. */
5912 SUBST (SET_DEST (x), pc_rtx);
5913 SUBST (SET_SRC (x), pc_rtx);
5917 /* Simplify our comparison, if possible. */
5918 new_code = simplify_comparison (new_code, &op0, &op1);
5920 #ifdef SELECT_CC_MODE
5921 /* If this machine has CC modes other than CCmode, check to see if we
5922 need to use a different CC mode here. */
5923 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5924 compare_mode = GET_MODE (op0);
5926 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5929 /* If the mode changed, we have to change SET_DEST, the mode in the
5930 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5931 a hard register, just build new versions with the proper mode. If it
5932 is a pseudo, we lose unless it is only time we set the pseudo, in
5933 which case we can safely change its mode. */
5934 if (compare_mode != GET_MODE (dest))
5936 if (can_change_dest_mode (dest, 0, compare_mode))
5938 unsigned int regno = REGNO (dest);
5941 if (regno < FIRST_PSEUDO_REGISTER)
5942 new_dest = gen_rtx_REG (compare_mode, regno);
5945 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5946 new_dest = regno_reg_rtx[regno];
5949 SUBST (SET_DEST (x), new_dest);
5950 SUBST (XEXP (*cc_use, 0), new_dest);
5957 #endif /* SELECT_CC_MODE */
5959 /* If the code changed, we have to build a new comparison in
5960 undobuf.other_insn. */
5961 if (new_code != old_code)
5963 int other_changed_previously = other_changed;
5964 unsigned HOST_WIDE_INT mask;
5965 rtx old_cc_use = *cc_use;
5967 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5971 /* If the only change we made was to change an EQ into an NE or
5972 vice versa, OP0 has only one bit that might be nonzero, and OP1
5973 is zero, check if changing the user of the condition code will
5974 produce a valid insn. If it won't, we can keep the original code
5975 in that insn by surrounding our operation with an XOR. */
5977 if (((old_code == NE && new_code == EQ)
5978 || (old_code == EQ && new_code == NE))
5979 && ! other_changed_previously && op1 == const0_rtx
5980 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5981 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5983 rtx pat = PATTERN (other_insn), note = 0;
5985 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5986 && ! check_asm_operands (pat)))
5988 *cc_use = old_cc_use;
5991 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5992 op0, GEN_INT (mask));
5998 undobuf.other_insn = other_insn;
6000 /* Otherwise, if we didn't previously have a COMPARE in the
6001 correct mode, we need one. */
6002 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6004 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6007 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6009 SUBST (SET_SRC (x), op0);
6012 /* Otherwise, update the COMPARE if needed. */
6013 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6015 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6021 /* Get SET_SRC in a form where we have placed back any
6022 compound expressions. Then do the checks below. */
6023 src = make_compound_operation (src, SET);
6024 SUBST (SET_SRC (x), src);
6027 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6028 and X being a REG or (subreg (reg)), we may be able to convert this to
6029 (set (subreg:m2 x) (op)).
6031 We can always do this if M1 is narrower than M2 because that means that
6032 we only care about the low bits of the result.
6034 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6035 perform a narrower operation than requested since the high-order bits will
6036 be undefined. On machine where it is defined, this transformation is safe
6037 as long as M1 and M2 have the same number of words. */
6039 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6040 && !OBJECT_P (SUBREG_REG (src))
6041 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6043 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6044 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6045 #ifndef WORD_REGISTER_OPERATIONS
6046 && (GET_MODE_SIZE (GET_MODE (src))
6047 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6049 #ifdef CANNOT_CHANGE_MODE_CLASS
6050 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6051 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6052 GET_MODE (SUBREG_REG (src)),
6056 || (GET_CODE (dest) == SUBREG
6057 && REG_P (SUBREG_REG (dest)))))
6059 SUBST (SET_DEST (x),
6060 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6062 SUBST (SET_SRC (x), SUBREG_REG (src));
6064 src = SET_SRC (x), dest = SET_DEST (x);
6068 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6071 && GET_CODE (src) == SUBREG
6072 && subreg_lowpart_p (src)
6073 && (GET_MODE_BITSIZE (GET_MODE (src))
6074 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6076 rtx inner = SUBREG_REG (src);
6077 enum machine_mode inner_mode = GET_MODE (inner);
6079 /* Here we make sure that we don't have a sign bit on. */
6080 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6081 && (nonzero_bits (inner, inner_mode)
6082 < ((unsigned HOST_WIDE_INT) 1
6083 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6085 SUBST (SET_SRC (x), inner);
6091 #ifdef LOAD_EXTEND_OP
6092 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6093 would require a paradoxical subreg. Replace the subreg with a
6094 zero_extend to avoid the reload that would otherwise be required. */
6096 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6097 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6098 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6099 && SUBREG_BYTE (src) == 0
6100 && (GET_MODE_SIZE (GET_MODE (src))
6101 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6102 && MEM_P (SUBREG_REG (src)))
6105 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6106 GET_MODE (src), SUBREG_REG (src)));
6112 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6113 are comparing an item known to be 0 or -1 against 0, use a logical
6114 operation instead. Check for one of the arms being an IOR of the other
6115 arm with some value. We compute three terms to be IOR'ed together. In
6116 practice, at most two will be nonzero. Then we do the IOR's. */
6118 if (GET_CODE (dest) != PC
6119 && GET_CODE (src) == IF_THEN_ELSE
6120 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6121 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6122 && XEXP (XEXP (src, 0), 1) == const0_rtx
6123 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6124 #ifdef HAVE_conditional_move
6125 && ! can_conditionally_move_p (GET_MODE (src))
6127 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6128 GET_MODE (XEXP (XEXP (src, 0), 0)))
6129 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6130 && ! side_effects_p (src))
6132 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6133 ? XEXP (src, 1) : XEXP (src, 2));
6134 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6135 ? XEXP (src, 2) : XEXP (src, 1));
6136 rtx term1 = const0_rtx, term2, term3;
6138 if (GET_CODE (true_rtx) == IOR
6139 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6140 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6141 else if (GET_CODE (true_rtx) == IOR
6142 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6143 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6144 else if (GET_CODE (false_rtx) == IOR
6145 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6146 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6147 else if (GET_CODE (false_rtx) == IOR
6148 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6149 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6151 term2 = simplify_gen_binary (AND, GET_MODE (src),
6152 XEXP (XEXP (src, 0), 0), true_rtx);
6153 term3 = simplify_gen_binary (AND, GET_MODE (src),
6154 simplify_gen_unary (NOT, GET_MODE (src),
6155 XEXP (XEXP (src, 0), 0),
6160 simplify_gen_binary (IOR, GET_MODE (src),
6161 simplify_gen_binary (IOR, GET_MODE (src),
6168 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6169 whole thing fail. */
6170 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6172 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6175 /* Convert this into a field assignment operation, if possible. */
6176 return make_field_assignment (x);
6179 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6183 simplify_logical (rtx x)
6185 enum machine_mode mode = GET_MODE (x);
6186 rtx op0 = XEXP (x, 0);
6187 rtx op1 = XEXP (x, 1);
6189 switch (GET_CODE (x))
6192 /* We can call simplify_and_const_int only if we don't lose
6193 any (sign) bits when converting INTVAL (op1) to
6194 "unsigned HOST_WIDE_INT". */
6195 if (CONST_INT_P (op1)
6196 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6197 || INTVAL (op1) > 0))
6199 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6200 if (GET_CODE (x) != AND)
6207 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6208 apply the distributive law and then the inverse distributive
6209 law to see if things simplify. */
6210 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6212 rtx result = distribute_and_simplify_rtx (x, 0);
6216 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6218 rtx result = distribute_and_simplify_rtx (x, 1);
6225 /* If we have (ior (and A B) C), apply the distributive law and then
6226 the inverse distributive law to see if things simplify. */
6228 if (GET_CODE (op0) == AND)
6230 rtx result = distribute_and_simplify_rtx (x, 0);
6235 if (GET_CODE (op1) == AND)
6237 rtx result = distribute_and_simplify_rtx (x, 1);
6250 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6251 operations" because they can be replaced with two more basic operations.
6252 ZERO_EXTEND is also considered "compound" because it can be replaced with
6253 an AND operation, which is simpler, though only one operation.
6255 The function expand_compound_operation is called with an rtx expression
6256 and will convert it to the appropriate shifts and AND operations,
6257 simplifying at each stage.
6259 The function make_compound_operation is called to convert an expression
6260 consisting of shifts and ANDs into the equivalent compound expression.
6261 It is the inverse of this function, loosely speaking. */
6264 expand_compound_operation (rtx x)
6266 unsigned HOST_WIDE_INT pos = 0, len;
6268 unsigned int modewidth;
6271 switch (GET_CODE (x))
6276 /* We can't necessarily use a const_int for a multiword mode;
6277 it depends on implicitly extending the value.
6278 Since we don't know the right way to extend it,
6279 we can't tell whether the implicit way is right.
6281 Even for a mode that is no wider than a const_int,
6282 we can't win, because we need to sign extend one of its bits through
6283 the rest of it, and we don't know which bit. */
6284 if (CONST_INT_P (XEXP (x, 0)))
6287 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6288 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6289 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6290 reloaded. If not for that, MEM's would very rarely be safe.
6292 Reject MODEs bigger than a word, because we might not be able
6293 to reference a two-register group starting with an arbitrary register
6294 (and currently gen_lowpart might crash for a SUBREG). */
6296 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6299 /* Reject MODEs that aren't scalar integers because turning vector
6300 or complex modes into shifts causes problems. */
6302 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6305 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6306 /* If the inner object has VOIDmode (the only way this can happen
6307 is if it is an ASM_OPERANDS), we can't do anything since we don't
6308 know how much masking to do. */
6317 /* ... fall through ... */
6320 /* If the operand is a CLOBBER, just return it. */
6321 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6324 if (!CONST_INT_P (XEXP (x, 1))
6325 || !CONST_INT_P (XEXP (x, 2))
6326 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6329 /* Reject MODEs that aren't scalar integers because turning vector
6330 or complex modes into shifts causes problems. */
6332 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6335 len = INTVAL (XEXP (x, 1));
6336 pos = INTVAL (XEXP (x, 2));
6338 /* This should stay within the object being extracted, fail otherwise. */
6339 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6342 if (BITS_BIG_ENDIAN)
6343 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6350 /* Convert sign extension to zero extension, if we know that the high
6351 bit is not set, as this is easier to optimize. It will be converted
6352 back to cheaper alternative in make_extraction. */
6353 if (GET_CODE (x) == SIGN_EXTEND
6354 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6355 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6356 & ~(((unsigned HOST_WIDE_INT)
6357 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6361 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6362 rtx temp2 = expand_compound_operation (temp);
6364 /* Make sure this is a profitable operation. */
6365 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6366 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6368 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6369 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6375 /* We can optimize some special cases of ZERO_EXTEND. */
6376 if (GET_CODE (x) == ZERO_EXTEND)
6378 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6379 know that the last value didn't have any inappropriate bits
6381 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6382 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6383 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6384 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6385 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6386 return XEXP (XEXP (x, 0), 0);
6388 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6389 if (GET_CODE (XEXP (x, 0)) == SUBREG
6390 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6391 && subreg_lowpart_p (XEXP (x, 0))
6392 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6393 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6394 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6395 return SUBREG_REG (XEXP (x, 0));
6397 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6398 is a comparison and STORE_FLAG_VALUE permits. This is like
6399 the first case, but it works even when GET_MODE (x) is larger
6400 than HOST_WIDE_INT. */
6401 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6402 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6403 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6404 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6405 <= HOST_BITS_PER_WIDE_INT)
6406 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6407 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6408 return XEXP (XEXP (x, 0), 0);
6410 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6411 if (GET_CODE (XEXP (x, 0)) == SUBREG
6412 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6413 && subreg_lowpart_p (XEXP (x, 0))
6414 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6415 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6416 <= HOST_BITS_PER_WIDE_INT)
6417 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6418 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6419 return SUBREG_REG (XEXP (x, 0));
6423 /* If we reach here, we want to return a pair of shifts. The inner
6424 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6425 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6426 logical depending on the value of UNSIGNEDP.
6428 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6429 converted into an AND of a shift.
6431 We must check for the case where the left shift would have a negative
6432 count. This can happen in a case like (x >> 31) & 255 on machines
6433 that can't shift by a constant. On those machines, we would first
6434 combine the shift with the AND to produce a variable-position
6435 extraction. Then the constant of 31 would be substituted in to produce
6436 a such a position. */
6438 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6439 if (modewidth + len >= pos)
6441 enum machine_mode mode = GET_MODE (x);
6442 tem = gen_lowpart (mode, XEXP (x, 0));
6443 if (!tem || GET_CODE (tem) == CLOBBER)
6445 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6446 tem, modewidth - pos - len);
6447 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6448 mode, tem, modewidth - len);
6450 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6451 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6452 simplify_shift_const (NULL_RTX, LSHIFTRT,
6455 ((HOST_WIDE_INT) 1 << len) - 1);
6457 /* Any other cases we can't handle. */
6460 /* If we couldn't do this for some reason, return the original
6462 if (GET_CODE (tem) == CLOBBER)
6468 /* X is a SET which contains an assignment of one object into
6469 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6470 or certain SUBREGS). If possible, convert it into a series of
6473 We half-heartedly support variable positions, but do not at all
6474 support variable lengths. */
6477 expand_field_assignment (const_rtx x)
6480 rtx pos; /* Always counts from low bit. */
6482 rtx mask, cleared, masked;
6483 enum machine_mode compute_mode;
6485 /* Loop until we find something we can't simplify. */
6488 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6489 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6491 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6492 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6493 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6495 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6496 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6498 inner = XEXP (SET_DEST (x), 0);
6499 len = INTVAL (XEXP (SET_DEST (x), 1));
6500 pos = XEXP (SET_DEST (x), 2);
6502 /* A constant position should stay within the width of INNER. */
6503 if (CONST_INT_P (pos)
6504 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6507 if (BITS_BIG_ENDIAN)
6509 if (CONST_INT_P (pos))
6510 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6512 else if (GET_CODE (pos) == MINUS
6513 && CONST_INT_P (XEXP (pos, 1))
6514 && (INTVAL (XEXP (pos, 1))
6515 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6516 /* If position is ADJUST - X, new position is X. */
6517 pos = XEXP (pos, 0);
6519 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6520 GEN_INT (GET_MODE_BITSIZE (
6527 /* A SUBREG between two modes that occupy the same numbers of words
6528 can be done by moving the SUBREG to the source. */
6529 else if (GET_CODE (SET_DEST (x)) == SUBREG
6530 /* We need SUBREGs to compute nonzero_bits properly. */
6531 && nonzero_sign_valid
6532 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6534 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6535 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6537 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6539 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6546 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6547 inner = SUBREG_REG (inner);
6549 compute_mode = GET_MODE (inner);
6551 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6552 if (! SCALAR_INT_MODE_P (compute_mode))
6554 enum machine_mode imode;
6556 /* Don't do anything for vector or complex integral types. */
6557 if (! FLOAT_MODE_P (compute_mode))
6560 /* Try to find an integral mode to pun with. */
6561 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6562 if (imode == BLKmode)
6565 compute_mode = imode;
6566 inner = gen_lowpart (imode, inner);
6569 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6570 if (len >= HOST_BITS_PER_WIDE_INT)
6573 /* Now compute the equivalent expression. Make a copy of INNER
6574 for the SET_DEST in case it is a MEM into which we will substitute;
6575 we don't want shared RTL in that case. */
6576 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6577 cleared = simplify_gen_binary (AND, compute_mode,
6578 simplify_gen_unary (NOT, compute_mode,
6579 simplify_gen_binary (ASHIFT,
6584 masked = simplify_gen_binary (ASHIFT, compute_mode,
6585 simplify_gen_binary (
6587 gen_lowpart (compute_mode, SET_SRC (x)),
6591 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6592 simplify_gen_binary (IOR, compute_mode,
6599 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6600 it is an RTX that represents a variable starting position; otherwise,
6601 POS is the (constant) starting bit position (counted from the LSB).
6603 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6606 IN_DEST is nonzero if this is a reference in the destination of a
6607 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6608 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6611 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6612 ZERO_EXTRACT should be built even for bits starting at bit 0.
6614 MODE is the desired mode of the result (if IN_DEST == 0).
6616 The result is an RTX for the extraction or NULL_RTX if the target
6620 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6621 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6622 int in_dest, int in_compare)
6624 /* This mode describes the size of the storage area
6625 to fetch the overall value from. Within that, we
6626 ignore the POS lowest bits, etc. */
6627 enum machine_mode is_mode = GET_MODE (inner);
6628 enum machine_mode inner_mode;
6629 enum machine_mode wanted_inner_mode;
6630 enum machine_mode wanted_inner_reg_mode = word_mode;
6631 enum machine_mode pos_mode = word_mode;
6632 enum machine_mode extraction_mode = word_mode;
6633 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6635 rtx orig_pos_rtx = pos_rtx;
6636 HOST_WIDE_INT orig_pos;
6638 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6640 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6641 consider just the QI as the memory to extract from.
6642 The subreg adds or removes high bits; its mode is
6643 irrelevant to the meaning of this extraction,
6644 since POS and LEN count from the lsb. */
6645 if (MEM_P (SUBREG_REG (inner)))
6646 is_mode = GET_MODE (SUBREG_REG (inner));
6647 inner = SUBREG_REG (inner);
6649 else if (GET_CODE (inner) == ASHIFT
6650 && CONST_INT_P (XEXP (inner, 1))
6651 && pos_rtx == 0 && pos == 0
6652 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6654 /* We're extracting the least significant bits of an rtx
6655 (ashift X (const_int C)), where LEN > C. Extract the
6656 least significant (LEN - C) bits of X, giving an rtx
6657 whose mode is MODE, then shift it left C times. */
6658 new_rtx = make_extraction (mode, XEXP (inner, 0),
6659 0, 0, len - INTVAL (XEXP (inner, 1)),
6660 unsignedp, in_dest, in_compare);
6662 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6665 inner_mode = GET_MODE (inner);
6667 if (pos_rtx && CONST_INT_P (pos_rtx))
6668 pos = INTVAL (pos_rtx), pos_rtx = 0;
6670 /* See if this can be done without an extraction. We never can if the
6671 width of the field is not the same as that of some integer mode. For
6672 registers, we can only avoid the extraction if the position is at the
6673 low-order bit and this is either not in the destination or we have the
6674 appropriate STRICT_LOW_PART operation available.
6676 For MEM, we can avoid an extract if the field starts on an appropriate
6677 boundary and we can change the mode of the memory reference. */
6679 if (tmode != BLKmode
6680 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6682 && (inner_mode == tmode
6684 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6685 GET_MODE_BITSIZE (inner_mode))
6686 || reg_truncated_to_mode (tmode, inner))
6689 && have_insn_for (STRICT_LOW_PART, tmode))))
6690 || (MEM_P (inner) && pos_rtx == 0
6692 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6693 : BITS_PER_UNIT)) == 0
6694 /* We can't do this if we are widening INNER_MODE (it
6695 may not be aligned, for one thing). */
6696 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6697 && (inner_mode == tmode
6698 || (! mode_dependent_address_p (XEXP (inner, 0))
6699 && ! MEM_VOLATILE_P (inner))))))
6701 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6702 field. If the original and current mode are the same, we need not
6703 adjust the offset. Otherwise, we do if bytes big endian.
6705 If INNER is not a MEM, get a piece consisting of just the field
6706 of interest (in this case POS % BITS_PER_WORD must be 0). */
6710 HOST_WIDE_INT offset;
6712 /* POS counts from lsb, but make OFFSET count in memory order. */
6713 if (BYTES_BIG_ENDIAN)
6714 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6716 offset = pos / BITS_PER_UNIT;
6718 new_rtx = adjust_address_nv (inner, tmode, offset);
6720 else if (REG_P (inner))
6722 if (tmode != inner_mode)
6724 /* We can't call gen_lowpart in a DEST since we
6725 always want a SUBREG (see below) and it would sometimes
6726 return a new hard register. */
6729 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6731 if (WORDS_BIG_ENDIAN
6732 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6733 final_word = ((GET_MODE_SIZE (inner_mode)
6734 - GET_MODE_SIZE (tmode))
6735 / UNITS_PER_WORD) - final_word;
6737 final_word *= UNITS_PER_WORD;
6738 if (BYTES_BIG_ENDIAN &&
6739 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6740 final_word += (GET_MODE_SIZE (inner_mode)
6741 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6743 /* Avoid creating invalid subregs, for example when
6744 simplifying (x>>32)&255. */
6745 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6748 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6751 new_rtx = gen_lowpart (tmode, inner);
6757 new_rtx = force_to_mode (inner, tmode,
6758 len >= HOST_BITS_PER_WIDE_INT
6759 ? ~(unsigned HOST_WIDE_INT) 0
6760 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6763 /* If this extraction is going into the destination of a SET,
6764 make a STRICT_LOW_PART unless we made a MEM. */
6767 return (MEM_P (new_rtx) ? new_rtx
6768 : (GET_CODE (new_rtx) != SUBREG
6769 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6770 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6775 if (CONST_INT_P (new_rtx))
6776 return gen_int_mode (INTVAL (new_rtx), mode);
6778 /* If we know that no extraneous bits are set, and that the high
6779 bit is not set, convert the extraction to the cheaper of
6780 sign and zero extension, that are equivalent in these cases. */
6781 if (flag_expensive_optimizations
6782 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6783 && ((nonzero_bits (new_rtx, tmode)
6784 & ~(((unsigned HOST_WIDE_INT)
6785 GET_MODE_MASK (tmode))
6789 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6790 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6792 /* Prefer ZERO_EXTENSION, since it gives more information to
6794 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6795 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6800 /* Otherwise, sign- or zero-extend unless we already are in the
6803 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6807 /* Unless this is a COMPARE or we have a funny memory reference,
6808 don't do anything with zero-extending field extracts starting at
6809 the low-order bit since they are simple AND operations. */
6810 if (pos_rtx == 0 && pos == 0 && ! in_dest
6811 && ! in_compare && unsignedp)
6814 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6815 if the position is not a constant and the length is not 1. In all
6816 other cases, we would only be going outside our object in cases when
6817 an original shift would have been undefined. */
6819 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6820 || (pos_rtx != 0 && len != 1)))
6823 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6824 and the mode for the result. */
6825 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6827 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6828 pos_mode = mode_for_extraction (EP_insv, 2);
6829 extraction_mode = mode_for_extraction (EP_insv, 3);
6832 if (! in_dest && unsignedp
6833 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6835 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6836 pos_mode = mode_for_extraction (EP_extzv, 3);
6837 extraction_mode = mode_for_extraction (EP_extzv, 0);
6840 if (! in_dest && ! unsignedp
6841 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6843 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6844 pos_mode = mode_for_extraction (EP_extv, 3);
6845 extraction_mode = mode_for_extraction (EP_extv, 0);
6848 /* Never narrow an object, since that might not be safe. */
6850 if (mode != VOIDmode
6851 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6852 extraction_mode = mode;
6854 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6855 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6856 pos_mode = GET_MODE (pos_rtx);
6858 /* If this is not from memory, the desired mode is the preferred mode
6859 for an extraction pattern's first input operand, or word_mode if there
6862 wanted_inner_mode = wanted_inner_reg_mode;
6865 /* Be careful not to go beyond the extracted object and maintain the
6866 natural alignment of the memory. */
6867 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6868 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6869 > GET_MODE_BITSIZE (wanted_inner_mode))
6871 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6872 gcc_assert (wanted_inner_mode != VOIDmode);
6875 /* If we have to change the mode of memory and cannot, the desired mode
6876 is EXTRACTION_MODE. */
6877 if (inner_mode != wanted_inner_mode
6878 && (mode_dependent_address_p (XEXP (inner, 0))
6879 || MEM_VOLATILE_P (inner)
6881 wanted_inner_mode = extraction_mode;
6886 if (BITS_BIG_ENDIAN)
6888 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6889 BITS_BIG_ENDIAN style. If position is constant, compute new
6890 position. Otherwise, build subtraction.
6891 Note that POS is relative to the mode of the original argument.
6892 If it's a MEM we need to recompute POS relative to that.
6893 However, if we're extracting from (or inserting into) a register,
6894 we want to recompute POS relative to wanted_inner_mode. */
6895 int width = (MEM_P (inner)
6896 ? GET_MODE_BITSIZE (is_mode)
6897 : GET_MODE_BITSIZE (wanted_inner_mode));
6900 pos = width - len - pos;
6903 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6904 /* POS may be less than 0 now, but we check for that below.
6905 Note that it can only be less than 0 if !MEM_P (inner). */
6908 /* If INNER has a wider mode, and this is a constant extraction, try to
6909 make it smaller and adjust the byte to point to the byte containing
6911 if (wanted_inner_mode != VOIDmode
6912 && inner_mode != wanted_inner_mode
6914 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6916 && ! mode_dependent_address_p (XEXP (inner, 0))
6917 && ! MEM_VOLATILE_P (inner))
6921 /* The computations below will be correct if the machine is big
6922 endian in both bits and bytes or little endian in bits and bytes.
6923 If it is mixed, we must adjust. */
6925 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6926 adjust OFFSET to compensate. */
6927 if (BYTES_BIG_ENDIAN
6928 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6929 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6931 /* We can now move to the desired byte. */
6932 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6933 * GET_MODE_SIZE (wanted_inner_mode);
6934 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6936 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6937 && is_mode != wanted_inner_mode)
6938 offset = (GET_MODE_SIZE (is_mode)
6939 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6941 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6944 /* If INNER is not memory, get it into the proper mode. If we are changing
6945 its mode, POS must be a constant and smaller than the size of the new
6947 else if (!MEM_P (inner))
6949 /* On the LHS, don't create paradoxical subregs implicitely truncating
6950 the register unless TRULY_NOOP_TRUNCATION. */
6952 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6953 GET_MODE_BITSIZE (wanted_inner_mode)))
6956 if (GET_MODE (inner) != wanted_inner_mode
6958 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6964 inner = force_to_mode (inner, wanted_inner_mode,
6966 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6967 ? ~(unsigned HOST_WIDE_INT) 0
6968 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6973 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6974 have to zero extend. Otherwise, we can just use a SUBREG. */
6976 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6978 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6980 /* If we know that no extraneous bits are set, and that the high
6981 bit is not set, convert extraction to cheaper one - either
6982 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6984 if (flag_expensive_optimizations
6985 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6986 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6987 & ~(((unsigned HOST_WIDE_INT)
6988 GET_MODE_MASK (GET_MODE (pos_rtx)))
6992 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6994 /* Prefer ZERO_EXTENSION, since it gives more information to
6996 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6997 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7002 else if (pos_rtx != 0
7003 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7004 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7006 /* Make POS_RTX unless we already have it and it is correct. If we don't
7007 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7009 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7010 pos_rtx = orig_pos_rtx;
7012 else if (pos_rtx == 0)
7013 pos_rtx = GEN_INT (pos);
7015 /* Make the required operation. See if we can use existing rtx. */
7016 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7017 extraction_mode, inner, GEN_INT (len), pos_rtx);
7019 new_rtx = gen_lowpart (mode, new_rtx);
7024 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7025 with any other operations in X. Return X without that shift if so. */
7028 extract_left_shift (rtx x, int count)
7030 enum rtx_code code = GET_CODE (x);
7031 enum machine_mode mode = GET_MODE (x);
7037 /* This is the shift itself. If it is wide enough, we will return
7038 either the value being shifted if the shift count is equal to
7039 COUNT or a shift for the difference. */
7040 if (CONST_INT_P (XEXP (x, 1))
7041 && INTVAL (XEXP (x, 1)) >= count)
7042 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7043 INTVAL (XEXP (x, 1)) - count);
7047 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7048 return simplify_gen_unary (code, mode, tem, mode);
7052 case PLUS: case IOR: case XOR: case AND:
7053 /* If we can safely shift this constant and we find the inner shift,
7054 make a new operation. */
7055 if (CONST_INT_P (XEXP (x, 1))
7056 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7057 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7058 return simplify_gen_binary (code, mode, tem,
7059 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7070 /* Look at the expression rooted at X. Look for expressions
7071 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7072 Form these expressions.
7074 Return the new rtx, usually just X.
7076 Also, for machines like the VAX that don't have logical shift insns,
7077 try to convert logical to arithmetic shift operations in cases where
7078 they are equivalent. This undoes the canonicalizations to logical
7079 shifts done elsewhere.
7081 We try, as much as possible, to re-use rtl expressions to save memory.
7083 IN_CODE says what kind of expression we are processing. Normally, it is
7084 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7085 being kludges), it is MEM. When processing the arguments of a comparison
7086 or a COMPARE against zero, it is COMPARE. */
7089 make_compound_operation (rtx x, enum rtx_code in_code)
7091 enum rtx_code code = GET_CODE (x);
7092 enum machine_mode mode = GET_MODE (x);
7093 int mode_width = GET_MODE_BITSIZE (mode);
7095 enum rtx_code next_code;
7101 /* Select the code to be used in recursive calls. Once we are inside an
7102 address, we stay there. If we have a comparison, set to COMPARE,
7103 but once inside, go back to our default of SET. */
7105 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7106 : ((code == COMPARE || COMPARISON_P (x))
7107 && XEXP (x, 1) == const0_rtx) ? COMPARE
7108 : in_code == COMPARE ? SET : in_code);
7110 /* Process depending on the code of this operation. If NEW is set
7111 nonzero, it will be returned. */
7116 /* Convert shifts by constants into multiplications if inside
7118 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7119 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7120 && INTVAL (XEXP (x, 1)) >= 0)
7122 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7123 new_rtx = gen_rtx_MULT (mode, new_rtx,
7124 GEN_INT ((HOST_WIDE_INT) 1
7125 << INTVAL (XEXP (x, 1))));
7130 /* If the second operand is not a constant, we can't do anything
7132 if (!CONST_INT_P (XEXP (x, 1)))
7135 /* If the constant is a power of two minus one and the first operand
7136 is a logical right shift, make an extraction. */
7137 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7138 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7140 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7141 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7142 0, in_code == COMPARE);
7145 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7146 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7147 && subreg_lowpart_p (XEXP (x, 0))
7148 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7149 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7151 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7153 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7154 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7155 0, in_code == COMPARE);
7157 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7158 else if ((GET_CODE (XEXP (x, 0)) == XOR
7159 || GET_CODE (XEXP (x, 0)) == IOR)
7160 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7161 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7162 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7164 /* Apply the distributive law, and then try to make extractions. */
7165 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7166 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7168 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7170 new_rtx = make_compound_operation (new_rtx, in_code);
7173 /* If we are have (and (rotate X C) M) and C is larger than the number
7174 of bits in M, this is an extraction. */
7176 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7177 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7178 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7179 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7181 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7182 new_rtx = make_extraction (mode, new_rtx,
7183 (GET_MODE_BITSIZE (mode)
7184 - INTVAL (XEXP (XEXP (x, 0), 1))),
7185 NULL_RTX, i, 1, 0, in_code == COMPARE);
7188 /* On machines without logical shifts, if the operand of the AND is
7189 a logical shift and our mask turns off all the propagated sign
7190 bits, we can replace the logical shift with an arithmetic shift. */
7191 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7192 && !have_insn_for (LSHIFTRT, mode)
7193 && have_insn_for (ASHIFTRT, mode)
7194 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7195 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7196 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7197 && mode_width <= HOST_BITS_PER_WIDE_INT)
7199 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7201 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7202 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7204 gen_rtx_ASHIFTRT (mode,
7205 make_compound_operation
7206 (XEXP (XEXP (x, 0), 0), next_code),
7207 XEXP (XEXP (x, 0), 1)));
7210 /* If the constant is one less than a power of two, this might be
7211 representable by an extraction even if no shift is present.
7212 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7213 we are in a COMPARE. */
7214 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7215 new_rtx = make_extraction (mode,
7216 make_compound_operation (XEXP (x, 0),
7218 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7220 /* If we are in a comparison and this is an AND with a power of two,
7221 convert this into the appropriate bit extract. */
7222 else if (in_code == COMPARE
7223 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7224 new_rtx = make_extraction (mode,
7225 make_compound_operation (XEXP (x, 0),
7227 i, NULL_RTX, 1, 1, 0, 1);
7232 /* If the sign bit is known to be zero, replace this with an
7233 arithmetic shift. */
7234 if (have_insn_for (ASHIFTRT, mode)
7235 && ! have_insn_for (LSHIFTRT, mode)
7236 && mode_width <= HOST_BITS_PER_WIDE_INT
7237 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7239 new_rtx = gen_rtx_ASHIFTRT (mode,
7240 make_compound_operation (XEXP (x, 0),
7246 /* ... fall through ... */
7252 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7253 this is a SIGN_EXTRACT. */
7254 if (CONST_INT_P (rhs)
7255 && GET_CODE (lhs) == ASHIFT
7256 && CONST_INT_P (XEXP (lhs, 1))
7257 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7258 && INTVAL (rhs) < mode_width)
7260 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7261 new_rtx = make_extraction (mode, new_rtx,
7262 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7263 NULL_RTX, mode_width - INTVAL (rhs),
7264 code == LSHIFTRT, 0, in_code == COMPARE);
7268 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7269 If so, try to merge the shifts into a SIGN_EXTEND. We could
7270 also do this for some cases of SIGN_EXTRACT, but it doesn't
7271 seem worth the effort; the case checked for occurs on Alpha. */
7274 && ! (GET_CODE (lhs) == SUBREG
7275 && (OBJECT_P (SUBREG_REG (lhs))))
7276 && CONST_INT_P (rhs)
7277 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7278 && INTVAL (rhs) < mode_width
7279 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7280 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7281 0, NULL_RTX, mode_width - INTVAL (rhs),
7282 code == LSHIFTRT, 0, in_code == COMPARE);
7287 /* Call ourselves recursively on the inner expression. If we are
7288 narrowing the object and it has a different RTL code from
7289 what it originally did, do this SUBREG as a force_to_mode. */
7291 tem = make_compound_operation (SUBREG_REG (x), in_code);
7295 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7301 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7302 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7303 && subreg_lowpart_p (x))
7305 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7308 /* If we have something other than a SUBREG, we might have
7309 done an expansion, so rerun ourselves. */
7310 if (GET_CODE (newer) != SUBREG)
7311 newer = make_compound_operation (newer, in_code);
7313 /* force_to_mode can expand compounds. If it just re-expanded the
7314 compound use gen_lowpart instead to convert to the desired
7316 if (rtx_equal_p (newer, x))
7317 return gen_lowpart (GET_MODE (x), tem);
7333 x = gen_lowpart (mode, new_rtx);
7334 code = GET_CODE (x);
7337 /* Now recursively process each operand of this operation. */
7338 fmt = GET_RTX_FORMAT (code);
7339 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7342 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7343 SUBST (XEXP (x, i), new_rtx);
7345 else if (fmt[i] == 'E')
7346 for (j = 0; j < XVECLEN (x, i); j++)
7348 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7349 SUBST (XVECEXP (x, i, j), new_rtx);
7352 /* If this is a commutative operation, the changes to the operands
7353 may have made it noncanonical. */
7354 if (COMMUTATIVE_ARITH_P (x)
7355 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7358 SUBST (XEXP (x, 0), XEXP (x, 1));
7359 SUBST (XEXP (x, 1), tem);
7365 /* Given M see if it is a value that would select a field of bits
7366 within an item, but not the entire word. Return -1 if not.
7367 Otherwise, return the starting position of the field, where 0 is the
7370 *PLEN is set to the length of the field. */
7373 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7375 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7376 int pos = exact_log2 (m & -m);
7380 /* Now shift off the low-order zero bits and see if we have a
7381 power of two minus 1. */
7382 len = exact_log2 ((m >> pos) + 1);
7391 /* If X refers to a register that equals REG in value, replace these
7392 references with REG. */
7394 canon_reg_for_combine (rtx x, rtx reg)
7401 enum rtx_code code = GET_CODE (x);
7402 switch (GET_RTX_CLASS (code))
7405 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7406 if (op0 != XEXP (x, 0))
7407 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7412 case RTX_COMM_ARITH:
7413 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7414 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7415 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7416 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7420 case RTX_COMM_COMPARE:
7421 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7422 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7423 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7424 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7425 GET_MODE (op0), op0, op1);
7429 case RTX_BITFIELD_OPS:
7430 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7431 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7432 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7433 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7434 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7435 GET_MODE (op0), op0, op1, op2);
7440 if (rtx_equal_p (get_last_value (reg), x)
7441 || rtx_equal_p (reg, get_last_value (x)))
7450 fmt = GET_RTX_FORMAT (code);
7452 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7455 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7456 if (op != XEXP (x, i))
7466 else if (fmt[i] == 'E')
7469 for (j = 0; j < XVECLEN (x, i); j++)
7471 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7472 if (op != XVECEXP (x, i, j))
7479 XVECEXP (x, i, j) = op;
7490 /* Return X converted to MODE. If the value is already truncated to
7491 MODE we can just return a subreg even though in the general case we
7492 would need an explicit truncation. */
7495 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7497 if (!CONST_INT_P (x)
7498 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7499 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7500 GET_MODE_BITSIZE (GET_MODE (x)))
7501 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7503 /* Bit-cast X into an integer mode. */
7504 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7505 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7506 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7510 return gen_lowpart (mode, x);
7513 /* See if X can be simplified knowing that we will only refer to it in
7514 MODE and will only refer to those bits that are nonzero in MASK.
7515 If other bits are being computed or if masking operations are done
7516 that select a superset of the bits in MASK, they can sometimes be
7519 Return a possibly simplified expression, but always convert X to
7520 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7522 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7523 are all off in X. This is used when X will be complemented, by either
7524 NOT, NEG, or XOR. */
7527 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7530 enum rtx_code code = GET_CODE (x);
7531 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7532 enum machine_mode op_mode;
7533 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7536 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7537 code below will do the wrong thing since the mode of such an
7538 expression is VOIDmode.
7540 Also do nothing if X is a CLOBBER; this can happen if X was
7541 the return value from a call to gen_lowpart. */
7542 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7545 /* We want to perform the operation is its present mode unless we know
7546 that the operation is valid in MODE, in which case we do the operation
7548 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7549 && have_insn_for (code, mode))
7550 ? mode : GET_MODE (x));
7552 /* It is not valid to do a right-shift in a narrower mode
7553 than the one it came in with. */
7554 if ((code == LSHIFTRT || code == ASHIFTRT)
7555 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7556 op_mode = GET_MODE (x);
7558 /* Truncate MASK to fit OP_MODE. */
7560 mask &= GET_MODE_MASK (op_mode);
7562 /* When we have an arithmetic operation, or a shift whose count we
7563 do not know, we need to assume that all bits up to the highest-order
7564 bit in MASK will be needed. This is how we form such a mask. */
7565 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7566 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7568 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7571 /* Determine what bits of X are guaranteed to be (non)zero. */
7572 nonzero = nonzero_bits (x, mode);
7574 /* If none of the bits in X are needed, return a zero. */
7575 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7578 /* If X is a CONST_INT, return a new one. Do this here since the
7579 test below will fail. */
7580 if (CONST_INT_P (x))
7582 if (SCALAR_INT_MODE_P (mode))
7583 return gen_int_mode (INTVAL (x) & mask, mode);
7586 x = GEN_INT (INTVAL (x) & mask);
7587 return gen_lowpart_common (mode, x);
7591 /* If X is narrower than MODE and we want all the bits in X's mode, just
7592 get X in the proper mode. */
7593 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7594 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7595 return gen_lowpart (mode, x);
7597 /* We can ignore the effect of a SUBREG if it narrows the mode or
7598 if the constant masks to zero all the bits the mode doesn't have. */
7599 if (GET_CODE (x) == SUBREG
7600 && subreg_lowpart_p (x)
7601 && ((GET_MODE_SIZE (GET_MODE (x))
7602 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7604 & GET_MODE_MASK (GET_MODE (x))
7605 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7606 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7608 /* The arithmetic simplifications here only work for scalar integer modes. */
7609 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7610 return gen_lowpart_or_truncate (mode, x);
7615 /* If X is a (clobber (const_int)), return it since we know we are
7616 generating something that won't match. */
7623 x = expand_compound_operation (x);
7624 if (GET_CODE (x) != code)
7625 return force_to_mode (x, mode, mask, next_select);
7629 /* Similarly for a truncate. */
7630 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7633 /* If this is an AND with a constant, convert it into an AND
7634 whose constant is the AND of that constant with MASK. If it
7635 remains an AND of MASK, delete it since it is redundant. */
7637 if (CONST_INT_P (XEXP (x, 1)))
7639 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7640 mask & INTVAL (XEXP (x, 1)));
7642 /* If X is still an AND, see if it is an AND with a mask that
7643 is just some low-order bits. If so, and it is MASK, we don't
7646 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7647 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7651 /* If it remains an AND, try making another AND with the bits
7652 in the mode mask that aren't in MASK turned on. If the
7653 constant in the AND is wide enough, this might make a
7654 cheaper constant. */
7656 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7657 && GET_MODE_MASK (GET_MODE (x)) != mask
7658 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7660 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7661 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7662 int width = GET_MODE_BITSIZE (GET_MODE (x));
7665 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7666 number, sign extend it. */
7667 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7668 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7669 cval |= (HOST_WIDE_INT) -1 << width;
7671 y = simplify_gen_binary (AND, GET_MODE (x),
7672 XEXP (x, 0), GEN_INT (cval));
7673 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7674 < rtx_cost (x, SET, optimize_this_for_speed_p))
7684 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7685 low-order bits (as in an alignment operation) and FOO is already
7686 aligned to that boundary, mask C1 to that boundary as well.
7687 This may eliminate that PLUS and, later, the AND. */
7690 unsigned int width = GET_MODE_BITSIZE (mode);
7691 unsigned HOST_WIDE_INT smask = mask;
7693 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7694 number, sign extend it. */
7696 if (width < HOST_BITS_PER_WIDE_INT
7697 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7698 smask |= (HOST_WIDE_INT) -1 << width;
7700 if (CONST_INT_P (XEXP (x, 1))
7701 && exact_log2 (- smask) >= 0
7702 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7703 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7704 return force_to_mode (plus_constant (XEXP (x, 0),
7705 (INTVAL (XEXP (x, 1)) & smask)),
7706 mode, smask, next_select);
7709 /* ... fall through ... */
7712 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7713 most significant bit in MASK since carries from those bits will
7714 affect the bits we are interested in. */
7719 /* If X is (minus C Y) where C's least set bit is larger than any bit
7720 in the mask, then we may replace with (neg Y). */
7721 if (CONST_INT_P (XEXP (x, 0))
7722 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7723 & -INTVAL (XEXP (x, 0))))
7726 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7728 return force_to_mode (x, mode, mask, next_select);
7731 /* Similarly, if C contains every bit in the fuller_mask, then we may
7732 replace with (not Y). */
7733 if (CONST_INT_P (XEXP (x, 0))
7734 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7735 == INTVAL (XEXP (x, 0))))
7737 x = simplify_gen_unary (NOT, GET_MODE (x),
7738 XEXP (x, 1), GET_MODE (x));
7739 return force_to_mode (x, mode, mask, next_select);
7747 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7748 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7749 operation which may be a bitfield extraction. Ensure that the
7750 constant we form is not wider than the mode of X. */
7752 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7753 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7754 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7755 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7756 && CONST_INT_P (XEXP (x, 1))
7757 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7758 + floor_log2 (INTVAL (XEXP (x, 1))))
7759 < GET_MODE_BITSIZE (GET_MODE (x)))
7760 && (INTVAL (XEXP (x, 1))
7761 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7763 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7764 << INTVAL (XEXP (XEXP (x, 0), 1)));
7765 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7766 XEXP (XEXP (x, 0), 0), temp);
7767 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7768 XEXP (XEXP (x, 0), 1));
7769 return force_to_mode (x, mode, mask, next_select);
7773 /* For most binary operations, just propagate into the operation and
7774 change the mode if we have an operation of that mode. */
7776 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7777 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7779 /* If we ended up truncating both operands, truncate the result of the
7780 operation instead. */
7781 if (GET_CODE (op0) == TRUNCATE
7782 && GET_CODE (op1) == TRUNCATE)
7784 op0 = XEXP (op0, 0);
7785 op1 = XEXP (op1, 0);
7788 op0 = gen_lowpart_or_truncate (op_mode, op0);
7789 op1 = gen_lowpart_or_truncate (op_mode, op1);
7791 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7792 x = simplify_gen_binary (code, op_mode, op0, op1);
7796 /* For left shifts, do the same, but just for the first operand.
7797 However, we cannot do anything with shifts where we cannot
7798 guarantee that the counts are smaller than the size of the mode
7799 because such a count will have a different meaning in a
7802 if (! (CONST_INT_P (XEXP (x, 1))
7803 && INTVAL (XEXP (x, 1)) >= 0
7804 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7805 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7806 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7807 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7810 /* If the shift count is a constant and we can do arithmetic in
7811 the mode of the shift, refine which bits we need. Otherwise, use the
7812 conservative form of the mask. */
7813 if (CONST_INT_P (XEXP (x, 1))
7814 && INTVAL (XEXP (x, 1)) >= 0
7815 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7816 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7817 mask >>= INTVAL (XEXP (x, 1));
7821 op0 = gen_lowpart_or_truncate (op_mode,
7822 force_to_mode (XEXP (x, 0), op_mode,
7823 mask, next_select));
7825 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7826 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7830 /* Here we can only do something if the shift count is a constant,
7831 this shift constant is valid for the host, and we can do arithmetic
7834 if (CONST_INT_P (XEXP (x, 1))
7835 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7836 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7838 rtx inner = XEXP (x, 0);
7839 unsigned HOST_WIDE_INT inner_mask;
7841 /* Select the mask of the bits we need for the shift operand. */
7842 inner_mask = mask << INTVAL (XEXP (x, 1));
7844 /* We can only change the mode of the shift if we can do arithmetic
7845 in the mode of the shift and INNER_MASK is no wider than the
7846 width of X's mode. */
7847 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7848 op_mode = GET_MODE (x);
7850 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7852 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7853 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7856 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7857 shift and AND produces only copies of the sign bit (C2 is one less
7858 than a power of two), we can do this with just a shift. */
7860 if (GET_CODE (x) == LSHIFTRT
7861 && CONST_INT_P (XEXP (x, 1))
7862 /* The shift puts one of the sign bit copies in the least significant
7864 && ((INTVAL (XEXP (x, 1))
7865 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7866 >= GET_MODE_BITSIZE (GET_MODE (x)))
7867 && exact_log2 (mask + 1) >= 0
7868 /* Number of bits left after the shift must be more than the mask
7870 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7871 <= GET_MODE_BITSIZE (GET_MODE (x)))
7872 /* Must be more sign bit copies than the mask needs. */
7873 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7874 >= exact_log2 (mask + 1)))
7875 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7876 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7877 - exact_log2 (mask + 1)));
7882 /* If we are just looking for the sign bit, we don't need this shift at
7883 all, even if it has a variable count. */
7884 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7885 && (mask == ((unsigned HOST_WIDE_INT) 1
7886 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7887 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7889 /* If this is a shift by a constant, get a mask that contains those bits
7890 that are not copies of the sign bit. We then have two cases: If
7891 MASK only includes those bits, this can be a logical shift, which may
7892 allow simplifications. If MASK is a single-bit field not within
7893 those bits, we are requesting a copy of the sign bit and hence can
7894 shift the sign bit to the appropriate location. */
7896 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7897 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7901 /* If the considered data is wider than HOST_WIDE_INT, we can't
7902 represent a mask for all its bits in a single scalar.
7903 But we only care about the lower bits, so calculate these. */
7905 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7907 nonzero = ~(HOST_WIDE_INT) 0;
7909 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7910 is the number of bits a full-width mask would have set.
7911 We need only shift if these are fewer than nonzero can
7912 hold. If not, we must keep all bits set in nonzero. */
7914 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7915 < HOST_BITS_PER_WIDE_INT)
7916 nonzero >>= INTVAL (XEXP (x, 1))
7917 + HOST_BITS_PER_WIDE_INT
7918 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7922 nonzero = GET_MODE_MASK (GET_MODE (x));
7923 nonzero >>= INTVAL (XEXP (x, 1));
7926 if ((mask & ~nonzero) == 0)
7928 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7929 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7930 if (GET_CODE (x) != ASHIFTRT)
7931 return force_to_mode (x, mode, mask, next_select);
7934 else if ((i = exact_log2 (mask)) >= 0)
7936 x = simplify_shift_const
7937 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7938 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7940 if (GET_CODE (x) != ASHIFTRT)
7941 return force_to_mode (x, mode, mask, next_select);
7945 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7946 even if the shift count isn't a constant. */
7948 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7949 XEXP (x, 0), XEXP (x, 1));
7953 /* If this is a zero- or sign-extension operation that just affects bits
7954 we don't care about, remove it. Be sure the call above returned
7955 something that is still a shift. */
7957 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7958 && CONST_INT_P (XEXP (x, 1))
7959 && INTVAL (XEXP (x, 1)) >= 0
7960 && (INTVAL (XEXP (x, 1))
7961 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7962 && GET_CODE (XEXP (x, 0)) == ASHIFT
7963 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7964 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7971 /* If the shift count is constant and we can do computations
7972 in the mode of X, compute where the bits we care about are.
7973 Otherwise, we can't do anything. Don't change the mode of
7974 the shift or propagate MODE into the shift, though. */
7975 if (CONST_INT_P (XEXP (x, 1))
7976 && INTVAL (XEXP (x, 1)) >= 0)
7978 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7979 GET_MODE (x), GEN_INT (mask),
7981 if (temp && CONST_INT_P (temp))
7983 force_to_mode (XEXP (x, 0), GET_MODE (x),
7984 INTVAL (temp), next_select));
7989 /* If we just want the low-order bit, the NEG isn't needed since it
7990 won't change the low-order bit. */
7992 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7994 /* We need any bits less significant than the most significant bit in
7995 MASK since carries from those bits will affect the bits we are
8001 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8002 same as the XOR case above. Ensure that the constant we form is not
8003 wider than the mode of X. */
8005 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8006 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8007 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8008 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8009 < GET_MODE_BITSIZE (GET_MODE (x)))
8010 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8012 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8014 temp = simplify_gen_binary (XOR, GET_MODE (x),
8015 XEXP (XEXP (x, 0), 0), temp);
8016 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8017 temp, XEXP (XEXP (x, 0), 1));
8019 return force_to_mode (x, mode, mask, next_select);
8022 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8023 use the full mask inside the NOT. */
8027 op0 = gen_lowpart_or_truncate (op_mode,
8028 force_to_mode (XEXP (x, 0), mode, mask,
8030 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8031 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8035 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8036 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8037 which is equal to STORE_FLAG_VALUE. */
8038 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8039 && GET_MODE (XEXP (x, 0)) == mode
8040 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8041 && (nonzero_bits (XEXP (x, 0), mode)
8042 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8043 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8048 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8049 written in a narrower mode. We play it safe and do not do so. */
8052 gen_lowpart_or_truncate (GET_MODE (x),
8053 force_to_mode (XEXP (x, 1), mode,
8054 mask, next_select)));
8056 gen_lowpart_or_truncate (GET_MODE (x),
8057 force_to_mode (XEXP (x, 2), mode,
8058 mask, next_select)));
8065 /* Ensure we return a value of the proper mode. */
8066 return gen_lowpart_or_truncate (mode, x);
8069 /* Return nonzero if X is an expression that has one of two values depending on
8070 whether some other value is zero or nonzero. In that case, we return the
8071 value that is being tested, *PTRUE is set to the value if the rtx being
8072 returned has a nonzero value, and *PFALSE is set to the other alternative.
8074 If we return zero, we set *PTRUE and *PFALSE to X. */
8077 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8079 enum machine_mode mode = GET_MODE (x);
8080 enum rtx_code code = GET_CODE (x);
8081 rtx cond0, cond1, true0, true1, false0, false1;
8082 unsigned HOST_WIDE_INT nz;
8084 /* If we are comparing a value against zero, we are done. */
8085 if ((code == NE || code == EQ)
8086 && XEXP (x, 1) == const0_rtx)
8088 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8089 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8093 /* If this is a unary operation whose operand has one of two values, apply
8094 our opcode to compute those values. */
8095 else if (UNARY_P (x)
8096 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8098 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8099 *pfalse = simplify_gen_unary (code, mode, false0,
8100 GET_MODE (XEXP (x, 0)));
8104 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8105 make can't possibly match and would suppress other optimizations. */
8106 else if (code == COMPARE)
8109 /* If this is a binary operation, see if either side has only one of two
8110 values. If either one does or if both do and they are conditional on
8111 the same value, compute the new true and false values. */
8112 else if (BINARY_P (x))
8114 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8115 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8117 if ((cond0 != 0 || cond1 != 0)
8118 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8120 /* If if_then_else_cond returned zero, then true/false are the
8121 same rtl. We must copy one of them to prevent invalid rtl
8124 true0 = copy_rtx (true0);
8125 else if (cond1 == 0)
8126 true1 = copy_rtx (true1);
8128 if (COMPARISON_P (x))
8130 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8132 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8137 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8138 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8141 return cond0 ? cond0 : cond1;
8144 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8145 operands is zero when the other is nonzero, and vice-versa,
8146 and STORE_FLAG_VALUE is 1 or -1. */
8148 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8149 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8151 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8153 rtx op0 = XEXP (XEXP (x, 0), 1);
8154 rtx op1 = XEXP (XEXP (x, 1), 1);
8156 cond0 = XEXP (XEXP (x, 0), 0);
8157 cond1 = XEXP (XEXP (x, 1), 0);
8159 if (COMPARISON_P (cond0)
8160 && COMPARISON_P (cond1)
8161 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8162 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8163 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8164 || ((swap_condition (GET_CODE (cond0))
8165 == reversed_comparison_code (cond1, NULL))
8166 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8167 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8168 && ! side_effects_p (x))
8170 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8171 *pfalse = simplify_gen_binary (MULT, mode,
8173 ? simplify_gen_unary (NEG, mode,
8181 /* Similarly for MULT, AND and UMIN, except that for these the result
8183 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8184 && (code == MULT || code == AND || code == UMIN)
8185 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8187 cond0 = XEXP (XEXP (x, 0), 0);
8188 cond1 = XEXP (XEXP (x, 1), 0);
8190 if (COMPARISON_P (cond0)
8191 && COMPARISON_P (cond1)
8192 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8193 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8194 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8195 || ((swap_condition (GET_CODE (cond0))
8196 == reversed_comparison_code (cond1, NULL))
8197 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8198 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8199 && ! side_effects_p (x))
8201 *ptrue = *pfalse = const0_rtx;
8207 else if (code == IF_THEN_ELSE)
8209 /* If we have IF_THEN_ELSE already, extract the condition and
8210 canonicalize it if it is NE or EQ. */
8211 cond0 = XEXP (x, 0);
8212 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8213 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8214 return XEXP (cond0, 0);
8215 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8217 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8218 return XEXP (cond0, 0);
8224 /* If X is a SUBREG, we can narrow both the true and false values
8225 if the inner expression, if there is a condition. */
8226 else if (code == SUBREG
8227 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8230 true0 = simplify_gen_subreg (mode, true0,
8231 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8232 false0 = simplify_gen_subreg (mode, false0,
8233 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8234 if (true0 && false0)
8242 /* If X is a constant, this isn't special and will cause confusions
8243 if we treat it as such. Likewise if it is equivalent to a constant. */
8244 else if (CONSTANT_P (x)
8245 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8248 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8249 will be least confusing to the rest of the compiler. */
8250 else if (mode == BImode)
8252 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8256 /* If X is known to be either 0 or -1, those are the true and
8257 false values when testing X. */
8258 else if (x == constm1_rtx || x == const0_rtx
8259 || (mode != VOIDmode
8260 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8262 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8266 /* Likewise for 0 or a single bit. */
8267 else if (SCALAR_INT_MODE_P (mode)
8268 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8269 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8271 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8275 /* Otherwise fail; show no condition with true and false values the same. */
8276 *ptrue = *pfalse = x;
8280 /* Return the value of expression X given the fact that condition COND
8281 is known to be true when applied to REG as its first operand and VAL
8282 as its second. X is known to not be shared and so can be modified in
8285 We only handle the simplest cases, and specifically those cases that
8286 arise with IF_THEN_ELSE expressions. */
8289 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8291 enum rtx_code code = GET_CODE (x);
8296 if (side_effects_p (x))
8299 /* If either operand of the condition is a floating point value,
8300 then we have to avoid collapsing an EQ comparison. */
8302 && rtx_equal_p (x, reg)
8303 && ! FLOAT_MODE_P (GET_MODE (x))
8304 && ! FLOAT_MODE_P (GET_MODE (val)))
8307 if (cond == UNEQ && rtx_equal_p (x, reg))
8310 /* If X is (abs REG) and we know something about REG's relationship
8311 with zero, we may be able to simplify this. */
8313 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8316 case GE: case GT: case EQ:
8319 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8321 GET_MODE (XEXP (x, 0)));
8326 /* The only other cases we handle are MIN, MAX, and comparisons if the
8327 operands are the same as REG and VAL. */
8329 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8331 if (rtx_equal_p (XEXP (x, 0), val))
8332 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8334 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8336 if (COMPARISON_P (x))
8338 if (comparison_dominates_p (cond, code))
8339 return const_true_rtx;
8341 code = reversed_comparison_code (x, NULL);
8343 && comparison_dominates_p (cond, code))
8348 else if (code == SMAX || code == SMIN
8349 || code == UMIN || code == UMAX)
8351 int unsignedp = (code == UMIN || code == UMAX);
8353 /* Do not reverse the condition when it is NE or EQ.
8354 This is because we cannot conclude anything about
8355 the value of 'SMAX (x, y)' when x is not equal to y,
8356 but we can when x equals y. */
8357 if ((code == SMAX || code == UMAX)
8358 && ! (cond == EQ || cond == NE))
8359 cond = reverse_condition (cond);
8364 return unsignedp ? x : XEXP (x, 1);
8366 return unsignedp ? x : XEXP (x, 0);
8368 return unsignedp ? XEXP (x, 1) : x;
8370 return unsignedp ? XEXP (x, 0) : x;
8377 else if (code == SUBREG)
8379 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8380 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8382 if (SUBREG_REG (x) != r)
8384 /* We must simplify subreg here, before we lose track of the
8385 original inner_mode. */
8386 new_rtx = simplify_subreg (GET_MODE (x), r,
8387 inner_mode, SUBREG_BYTE (x));
8391 SUBST (SUBREG_REG (x), r);
8396 /* We don't have to handle SIGN_EXTEND here, because even in the
8397 case of replacing something with a modeless CONST_INT, a
8398 CONST_INT is already (supposed to be) a valid sign extension for
8399 its narrower mode, which implies it's already properly
8400 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8401 story is different. */
8402 else if (code == ZERO_EXTEND)
8404 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8405 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8407 if (XEXP (x, 0) != r)
8409 /* We must simplify the zero_extend here, before we lose
8410 track of the original inner_mode. */
8411 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8416 SUBST (XEXP (x, 0), r);
8422 fmt = GET_RTX_FORMAT (code);
8423 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8426 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8427 else if (fmt[i] == 'E')
8428 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8429 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8436 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8437 assignment as a field assignment. */
8440 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8442 if (x == y || rtx_equal_p (x, y))
8445 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8448 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8449 Note that all SUBREGs of MEM are paradoxical; otherwise they
8450 would have been rewritten. */
8451 if (MEM_P (x) && GET_CODE (y) == SUBREG
8452 && MEM_P (SUBREG_REG (y))
8453 && rtx_equal_p (SUBREG_REG (y),
8454 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8457 if (MEM_P (y) && GET_CODE (x) == SUBREG
8458 && MEM_P (SUBREG_REG (x))
8459 && rtx_equal_p (SUBREG_REG (x),
8460 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8463 /* We used to see if get_last_value of X and Y were the same but that's
8464 not correct. In one direction, we'll cause the assignment to have
8465 the wrong destination and in the case, we'll import a register into this
8466 insn that might have already have been dead. So fail if none of the
8467 above cases are true. */
8471 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8472 Return that assignment if so.
8474 We only handle the most common cases. */
8477 make_field_assignment (rtx x)
8479 rtx dest = SET_DEST (x);
8480 rtx src = SET_SRC (x);
8485 unsigned HOST_WIDE_INT len;
8487 enum machine_mode mode;
8489 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8490 a clear of a one-bit field. We will have changed it to
8491 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8494 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8495 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8496 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8497 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8499 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8502 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8506 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8507 && subreg_lowpart_p (XEXP (src, 0))
8508 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8509 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8510 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8511 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8512 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8513 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8515 assign = make_extraction (VOIDmode, dest, 0,
8516 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8519 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8523 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8525 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8526 && XEXP (XEXP (src, 0), 0) == const1_rtx
8527 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8529 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8532 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8536 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8537 SRC is an AND with all bits of that field set, then we can discard
8539 if (GET_CODE (dest) == ZERO_EXTRACT
8540 && CONST_INT_P (XEXP (dest, 1))
8541 && GET_CODE (src) == AND
8542 && CONST_INT_P (XEXP (src, 1)))
8544 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8545 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8546 unsigned HOST_WIDE_INT ze_mask;
8548 if (width >= HOST_BITS_PER_WIDE_INT)
8551 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8553 /* Complete overlap. We can remove the source AND. */
8554 if ((and_mask & ze_mask) == ze_mask)
8555 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8557 /* Partial overlap. We can reduce the source AND. */
8558 if ((and_mask & ze_mask) != and_mask)
8560 mode = GET_MODE (src);
8561 src = gen_rtx_AND (mode, XEXP (src, 0),
8562 gen_int_mode (and_mask & ze_mask, mode));
8563 return gen_rtx_SET (VOIDmode, dest, src);
8567 /* The other case we handle is assignments into a constant-position
8568 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8569 a mask that has all one bits except for a group of zero bits and
8570 OTHER is known to have zeros where C1 has ones, this is such an
8571 assignment. Compute the position and length from C1. Shift OTHER
8572 to the appropriate position, force it to the required mode, and
8573 make the extraction. Check for the AND in both operands. */
8575 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8578 rhs = expand_compound_operation (XEXP (src, 0));
8579 lhs = expand_compound_operation (XEXP (src, 1));
8581 if (GET_CODE (rhs) == AND
8582 && CONST_INT_P (XEXP (rhs, 1))
8583 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8584 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8585 else if (GET_CODE (lhs) == AND
8586 && CONST_INT_P (XEXP (lhs, 1))
8587 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8588 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8592 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8593 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8594 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8595 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8598 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8602 /* The mode to use for the source is the mode of the assignment, or of
8603 what is inside a possible STRICT_LOW_PART. */
8604 mode = (GET_CODE (assign) == STRICT_LOW_PART
8605 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8607 /* Shift OTHER right POS places and make it the source, restricting it
8608 to the proper length and mode. */
8610 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8614 src = force_to_mode (src, mode,
8615 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8616 ? ~(unsigned HOST_WIDE_INT) 0
8617 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8620 /* If SRC is masked by an AND that does not make a difference in
8621 the value being stored, strip it. */
8622 if (GET_CODE (assign) == ZERO_EXTRACT
8623 && CONST_INT_P (XEXP (assign, 1))
8624 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8625 && GET_CODE (src) == AND
8626 && CONST_INT_P (XEXP (src, 1))
8627 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8628 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8629 src = XEXP (src, 0);
8631 return gen_rtx_SET (VOIDmode, assign, src);
8634 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8638 apply_distributive_law (rtx x)
8640 enum rtx_code code = GET_CODE (x);
8641 enum rtx_code inner_code;
8642 rtx lhs, rhs, other;
8645 /* Distributivity is not true for floating point as it can change the
8646 value. So we don't do it unless -funsafe-math-optimizations. */
8647 if (FLOAT_MODE_P (GET_MODE (x))
8648 && ! flag_unsafe_math_optimizations)
8651 /* The outer operation can only be one of the following: */
8652 if (code != IOR && code != AND && code != XOR
8653 && code != PLUS && code != MINUS)
8659 /* If either operand is a primitive we can't do anything, so get out
8661 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8664 lhs = expand_compound_operation (lhs);
8665 rhs = expand_compound_operation (rhs);
8666 inner_code = GET_CODE (lhs);
8667 if (inner_code != GET_CODE (rhs))
8670 /* See if the inner and outer operations distribute. */
8677 /* These all distribute except over PLUS. */
8678 if (code == PLUS || code == MINUS)
8683 if (code != PLUS && code != MINUS)
8688 /* This is also a multiply, so it distributes over everything. */
8692 /* Non-paradoxical SUBREGs distributes over all operations,
8693 provided the inner modes and byte offsets are the same, this
8694 is an extraction of a low-order part, we don't convert an fp
8695 operation to int or vice versa, this is not a vector mode,
8696 and we would not be converting a single-word operation into a
8697 multi-word operation. The latter test is not required, but
8698 it prevents generating unneeded multi-word operations. Some
8699 of the previous tests are redundant given the latter test,
8700 but are retained because they are required for correctness.
8702 We produce the result slightly differently in this case. */
8704 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8705 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8706 || ! subreg_lowpart_p (lhs)
8707 || (GET_MODE_CLASS (GET_MODE (lhs))
8708 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8709 || (GET_MODE_SIZE (GET_MODE (lhs))
8710 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8711 || VECTOR_MODE_P (GET_MODE (lhs))
8712 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8713 /* Result might need to be truncated. Don't change mode if
8714 explicit truncation is needed. */
8715 || !TRULY_NOOP_TRUNCATION
8716 (GET_MODE_BITSIZE (GET_MODE (x)),
8717 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8720 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8721 SUBREG_REG (lhs), SUBREG_REG (rhs));
8722 return gen_lowpart (GET_MODE (x), tem);
8728 /* Set LHS and RHS to the inner operands (A and B in the example
8729 above) and set OTHER to the common operand (C in the example).
8730 There is only one way to do this unless the inner operation is
8732 if (COMMUTATIVE_ARITH_P (lhs)
8733 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8734 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8735 else if (COMMUTATIVE_ARITH_P (lhs)
8736 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8737 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8738 else if (COMMUTATIVE_ARITH_P (lhs)
8739 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8740 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8741 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8742 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8746 /* Form the new inner operation, seeing if it simplifies first. */
8747 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8749 /* There is one exception to the general way of distributing:
8750 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8751 if (code == XOR && inner_code == IOR)
8754 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8757 /* We may be able to continuing distributing the result, so call
8758 ourselves recursively on the inner operation before forming the
8759 outer operation, which we return. */
8760 return simplify_gen_binary (inner_code, GET_MODE (x),
8761 apply_distributive_law (tem), other);
8764 /* See if X is of the form (* (+ A B) C), and if so convert to
8765 (+ (* A C) (* B C)) and try to simplify.
8767 Most of the time, this results in no change. However, if some of
8768 the operands are the same or inverses of each other, simplifications
8771 For example, (and (ior A B) (not B)) can occur as the result of
8772 expanding a bit field assignment. When we apply the distributive
8773 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8774 which then simplifies to (and (A (not B))).
8776 Note that no checks happen on the validity of applying the inverse
8777 distributive law. This is pointless since we can do it in the
8778 few places where this routine is called.
8780 N is the index of the term that is decomposed (the arithmetic operation,
8781 i.e. (+ A B) in the first example above). !N is the index of the term that
8782 is distributed, i.e. of C in the first example above. */
8784 distribute_and_simplify_rtx (rtx x, int n)
8786 enum machine_mode mode;
8787 enum rtx_code outer_code, inner_code;
8788 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8790 /* Distributivity is not true for floating point as it can change the
8791 value. So we don't do it unless -funsafe-math-optimizations. */
8792 if (FLOAT_MODE_P (GET_MODE (x))
8793 && ! flag_unsafe_math_optimizations)
8796 decomposed = XEXP (x, n);
8797 if (!ARITHMETIC_P (decomposed))
8800 mode = GET_MODE (x);
8801 outer_code = GET_CODE (x);
8802 distributed = XEXP (x, !n);
8804 inner_code = GET_CODE (decomposed);
8805 inner_op0 = XEXP (decomposed, 0);
8806 inner_op1 = XEXP (decomposed, 1);
8808 /* Special case (and (xor B C) (not A)), which is equivalent to
8809 (xor (ior A B) (ior A C)) */
8810 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8812 distributed = XEXP (distributed, 0);
8818 /* Distribute the second term. */
8819 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8820 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8824 /* Distribute the first term. */
8825 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8826 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8829 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8831 if (GET_CODE (tmp) != outer_code
8832 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8833 < rtx_cost (x, SET, optimize_this_for_speed_p))
8839 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8840 in MODE. Return an equivalent form, if different from (and VAROP
8841 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8844 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8845 unsigned HOST_WIDE_INT constop)
8847 unsigned HOST_WIDE_INT nonzero;
8848 unsigned HOST_WIDE_INT orig_constop;
8853 orig_constop = constop;
8854 if (GET_CODE (varop) == CLOBBER)
8857 /* Simplify VAROP knowing that we will be only looking at some of the
8860 Note by passing in CONSTOP, we guarantee that the bits not set in
8861 CONSTOP are not significant and will never be examined. We must
8862 ensure that is the case by explicitly masking out those bits
8863 before returning. */
8864 varop = force_to_mode (varop, mode, constop, 0);
8866 /* If VAROP is a CLOBBER, we will fail so return it. */
8867 if (GET_CODE (varop) == CLOBBER)
8870 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8871 to VAROP and return the new constant. */
8872 if (CONST_INT_P (varop))
8873 return gen_int_mode (INTVAL (varop) & constop, mode);
8875 /* See what bits may be nonzero in VAROP. Unlike the general case of
8876 a call to nonzero_bits, here we don't care about bits outside
8879 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8881 /* Turn off all bits in the constant that are known to already be zero.
8882 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8883 which is tested below. */
8887 /* If we don't have any bits left, return zero. */
8891 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8892 a power of two, we can replace this with an ASHIFT. */
8893 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8894 && (i = exact_log2 (constop)) >= 0)
8895 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8897 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8898 or XOR, then try to apply the distributive law. This may eliminate
8899 operations if either branch can be simplified because of the AND.
8900 It may also make some cases more complex, but those cases probably
8901 won't match a pattern either with or without this. */
8903 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8907 apply_distributive_law
8908 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8909 simplify_and_const_int (NULL_RTX,
8913 simplify_and_const_int (NULL_RTX,
8918 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8919 the AND and see if one of the operands simplifies to zero. If so, we
8920 may eliminate it. */
8922 if (GET_CODE (varop) == PLUS
8923 && exact_log2 (constop + 1) >= 0)
8927 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8928 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8929 if (o0 == const0_rtx)
8931 if (o1 == const0_rtx)
8935 /* Make a SUBREG if necessary. If we can't make it, fail. */
8936 varop = gen_lowpart (mode, varop);
8937 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8940 /* If we are only masking insignificant bits, return VAROP. */
8941 if (constop == nonzero)
8944 if (varop == orig_varop && constop == orig_constop)
8947 /* Otherwise, return an AND. */
8948 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8952 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8955 Return an equivalent form, if different from X. Otherwise, return X. If
8956 X is zero, we are to always construct the equivalent form. */
8959 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8960 unsigned HOST_WIDE_INT constop)
8962 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8967 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8968 gen_int_mode (constop, mode));
8969 if (GET_MODE (x) != mode)
8970 x = gen_lowpart (mode, x);
8974 /* Given a REG, X, compute which bits in X can be nonzero.
8975 We don't care about bits outside of those defined in MODE.
8977 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8978 a shift, AND, or zero_extract, we can do better. */
8981 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8982 const_rtx known_x ATTRIBUTE_UNUSED,
8983 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8984 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8985 unsigned HOST_WIDE_INT *nonzero)
8990 /* If X is a register whose nonzero bits value is current, use it.
8991 Otherwise, if X is a register whose value we can find, use that
8992 value. Otherwise, use the previously-computed global nonzero bits
8993 for this register. */
8995 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8996 if (rsp->last_set_value != 0
8997 && (rsp->last_set_mode == mode
8998 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8999 && GET_MODE_CLASS (mode) == MODE_INT))
9000 && ((rsp->last_set_label >= label_tick_ebb_start
9001 && rsp->last_set_label < label_tick)
9002 || (rsp->last_set_label == label_tick
9003 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9004 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9005 && REG_N_SETS (REGNO (x)) == 1
9007 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9009 *nonzero &= rsp->last_set_nonzero_bits;
9013 tem = get_last_value (x);
9017 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9018 /* If X is narrower than MODE and TEM is a non-negative
9019 constant that would appear negative in the mode of X,
9020 sign-extend it for use in reg_nonzero_bits because some
9021 machines (maybe most) will actually do the sign-extension
9022 and this is the conservative approach.
9024 ??? For 2.5, try to tighten up the MD files in this regard
9025 instead of this kludge. */
9027 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9028 && CONST_INT_P (tem)
9030 && 0 != (INTVAL (tem)
9031 & ((HOST_WIDE_INT) 1
9032 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9033 tem = GEN_INT (INTVAL (tem)
9034 | ((HOST_WIDE_INT) (-1)
9035 << GET_MODE_BITSIZE (GET_MODE (x))));
9039 else if (nonzero_sign_valid && rsp->nonzero_bits)
9041 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9043 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9044 /* We don't know anything about the upper bits. */
9045 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9052 /* Return the number of bits at the high-order end of X that are known to
9053 be equal to the sign bit. X will be used in mode MODE; if MODE is
9054 VOIDmode, X will be used in its own mode. The returned value will always
9055 be between 1 and the number of bits in MODE. */
9058 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9059 const_rtx known_x ATTRIBUTE_UNUSED,
9060 enum machine_mode known_mode
9062 unsigned int known_ret ATTRIBUTE_UNUSED,
9063 unsigned int *result)
9068 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9069 if (rsp->last_set_value != 0
9070 && rsp->last_set_mode == mode
9071 && ((rsp->last_set_label >= label_tick_ebb_start
9072 && rsp->last_set_label < label_tick)
9073 || (rsp->last_set_label == label_tick
9074 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9075 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9076 && REG_N_SETS (REGNO (x)) == 1
9078 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9080 *result = rsp->last_set_sign_bit_copies;
9084 tem = get_last_value (x);
9088 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9089 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9090 *result = rsp->sign_bit_copies;
9095 /* Return the number of "extended" bits there are in X, when interpreted
9096 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9097 unsigned quantities, this is the number of high-order zero bits.
9098 For signed quantities, this is the number of copies of the sign bit
9099 minus 1. In both case, this function returns the number of "spare"
9100 bits. For example, if two quantities for which this function returns
9101 at least 1 are added, the addition is known not to overflow.
9103 This function will always return 0 unless called during combine, which
9104 implies that it must be called from a define_split. */
9107 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9109 if (nonzero_sign_valid == 0)
9113 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9114 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9115 - floor_log2 (nonzero_bits (x, mode)))
9117 : num_sign_bit_copies (x, mode) - 1);
9120 /* This function is called from `simplify_shift_const' to merge two
9121 outer operations. Specifically, we have already found that we need
9122 to perform operation *POP0 with constant *PCONST0 at the outermost
9123 position. We would now like to also perform OP1 with constant CONST1
9124 (with *POP0 being done last).
9126 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9127 the resulting operation. *PCOMP_P is set to 1 if we would need to
9128 complement the innermost operand, otherwise it is unchanged.
9130 MODE is the mode in which the operation will be done. No bits outside
9131 the width of this mode matter. It is assumed that the width of this mode
9132 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9134 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9135 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9136 result is simply *PCONST0.
9138 If the resulting operation cannot be expressed as one operation, we
9139 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9142 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9144 enum rtx_code op0 = *pop0;
9145 HOST_WIDE_INT const0 = *pconst0;
9147 const0 &= GET_MODE_MASK (mode);
9148 const1 &= GET_MODE_MASK (mode);
9150 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9154 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9157 if (op1 == UNKNOWN || op0 == SET)
9160 else if (op0 == UNKNOWN)
9161 op0 = op1, const0 = const1;
9163 else if (op0 == op1)
9187 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9188 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9191 /* If the two constants aren't the same, we can't do anything. The
9192 remaining six cases can all be done. */
9193 else if (const0 != const1)
9201 /* (a & b) | b == b */
9203 else /* op1 == XOR */
9204 /* (a ^ b) | b == a | b */
9210 /* (a & b) ^ b == (~a) & b */
9211 op0 = AND, *pcomp_p = 1;
9212 else /* op1 == IOR */
9213 /* (a | b) ^ b == a & ~b */
9214 op0 = AND, const0 = ~const0;
9219 /* (a | b) & b == b */
9221 else /* op1 == XOR */
9222 /* (a ^ b) & b) == (~a) & b */
9229 /* Check for NO-OP cases. */
9230 const0 &= GET_MODE_MASK (mode);
9232 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9234 else if (const0 == 0 && op0 == AND)
9236 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9242 /* ??? Slightly redundant with the above mask, but not entirely.
9243 Moving this above means we'd have to sign-extend the mode mask
9244 for the final test. */
9245 if (op0 != UNKNOWN && op0 != NEG)
9246 *pconst0 = trunc_int_for_mode (const0, mode);
9251 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9252 the shift in. The original shift operation CODE is performed on OP in
9253 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9254 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9255 result of the shift is subject to operation OUTER_CODE with operand
9258 static enum machine_mode
9259 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9260 enum machine_mode orig_mode, enum machine_mode mode,
9261 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9263 if (orig_mode == mode)
9265 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9267 /* In general we can't perform in wider mode for right shift and rotate. */
9271 /* We can still widen if the bits brought in from the left are identical
9272 to the sign bit of ORIG_MODE. */
9273 if (num_sign_bit_copies (op, mode)
9274 > (unsigned) (GET_MODE_BITSIZE (mode)
9275 - GET_MODE_BITSIZE (orig_mode)))
9280 /* Similarly here but with zero bits. */
9281 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9282 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9285 /* We can also widen if the bits brought in will be masked off. This
9286 operation is performed in ORIG_MODE. */
9287 if (outer_code == AND)
9289 int care_bits = low_bitmask_len (orig_mode, outer_const);
9292 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9308 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9309 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9310 simplify it. Otherwise, return a simplified value.
9312 The shift is normally computed in the widest mode we find in VAROP, as
9313 long as it isn't a different number of words than RESULT_MODE. Exceptions
9314 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9317 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9318 rtx varop, int orig_count)
9320 enum rtx_code orig_code = code;
9321 rtx orig_varop = varop;
9323 enum machine_mode mode = result_mode;
9324 enum machine_mode shift_mode, tmode;
9325 unsigned int mode_words
9326 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9327 /* We form (outer_op (code varop count) (outer_const)). */
9328 enum rtx_code outer_op = UNKNOWN;
9329 HOST_WIDE_INT outer_const = 0;
9330 int complement_p = 0;
9333 /* Make sure and truncate the "natural" shift on the way in. We don't
9334 want to do this inside the loop as it makes it more difficult to
9336 if (SHIFT_COUNT_TRUNCATED)
9337 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9339 /* If we were given an invalid count, don't do anything except exactly
9340 what was requested. */
9342 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9347 /* Unless one of the branches of the `if' in this loop does a `continue',
9348 we will `break' the loop after the `if'. */
9352 /* If we have an operand of (clobber (const_int 0)), fail. */
9353 if (GET_CODE (varop) == CLOBBER)
9356 /* Convert ROTATERT to ROTATE. */
9357 if (code == ROTATERT)
9359 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9361 if (VECTOR_MODE_P (result_mode))
9362 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9364 count = bitsize - count;
9367 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9368 mode, outer_op, outer_const);
9370 /* Handle cases where the count is greater than the size of the mode
9371 minus 1. For ASHIFT, use the size minus one as the count (this can
9372 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9373 take the count modulo the size. For other shifts, the result is
9376 Since these shifts are being produced by the compiler by combining
9377 multiple operations, each of which are defined, we know what the
9378 result is supposed to be. */
9380 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9382 if (code == ASHIFTRT)
9383 count = GET_MODE_BITSIZE (shift_mode) - 1;
9384 else if (code == ROTATE || code == ROTATERT)
9385 count %= GET_MODE_BITSIZE (shift_mode);
9388 /* We can't simply return zero because there may be an
9396 /* If we discovered we had to complement VAROP, leave. Making a NOT
9397 here would cause an infinite loop. */
9401 /* An arithmetic right shift of a quantity known to be -1 or 0
9403 if (code == ASHIFTRT
9404 && (num_sign_bit_copies (varop, shift_mode)
9405 == GET_MODE_BITSIZE (shift_mode)))
9411 /* If we are doing an arithmetic right shift and discarding all but
9412 the sign bit copies, this is equivalent to doing a shift by the
9413 bitsize minus one. Convert it into that shift because it will often
9414 allow other simplifications. */
9416 if (code == ASHIFTRT
9417 && (count + num_sign_bit_copies (varop, shift_mode)
9418 >= GET_MODE_BITSIZE (shift_mode)))
9419 count = GET_MODE_BITSIZE (shift_mode) - 1;
9421 /* We simplify the tests below and elsewhere by converting
9422 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9423 `make_compound_operation' will convert it to an ASHIFTRT for
9424 those machines (such as VAX) that don't have an LSHIFTRT. */
9425 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9427 && ((nonzero_bits (varop, shift_mode)
9428 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9432 if (((code == LSHIFTRT
9433 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9434 && !(nonzero_bits (varop, shift_mode) >> count))
9436 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9437 && !((nonzero_bits (varop, shift_mode) << count)
9438 & GET_MODE_MASK (shift_mode))))
9439 && !side_effects_p (varop))
9442 switch (GET_CODE (varop))
9448 new_rtx = expand_compound_operation (varop);
9449 if (new_rtx != varop)
9457 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9458 minus the width of a smaller mode, we can do this with a
9459 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9460 if ((code == ASHIFTRT || code == LSHIFTRT)
9461 && ! mode_dependent_address_p (XEXP (varop, 0))
9462 && ! MEM_VOLATILE_P (varop)
9463 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9464 MODE_INT, 1)) != BLKmode)
9466 new_rtx = adjust_address_nv (varop, tmode,
9467 BYTES_BIG_ENDIAN ? 0
9468 : count / BITS_PER_UNIT);
9470 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9471 : ZERO_EXTEND, mode, new_rtx);
9478 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9479 the same number of words as what we've seen so far. Then store
9480 the widest mode in MODE. */
9481 if (subreg_lowpart_p (varop)
9482 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9483 > GET_MODE_SIZE (GET_MODE (varop)))
9484 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9485 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9488 varop = SUBREG_REG (varop);
9489 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9490 mode = GET_MODE (varop);
9496 /* Some machines use MULT instead of ASHIFT because MULT
9497 is cheaper. But it is still better on those machines to
9498 merge two shifts into one. */
9499 if (CONST_INT_P (XEXP (varop, 1))
9500 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9503 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9505 GEN_INT (exact_log2 (
9506 INTVAL (XEXP (varop, 1)))));
9512 /* Similar, for when divides are cheaper. */
9513 if (CONST_INT_P (XEXP (varop, 1))
9514 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9517 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9519 GEN_INT (exact_log2 (
9520 INTVAL (XEXP (varop, 1)))));
9526 /* If we are extracting just the sign bit of an arithmetic
9527 right shift, that shift is not needed. However, the sign
9528 bit of a wider mode may be different from what would be
9529 interpreted as the sign bit in a narrower mode, so, if
9530 the result is narrower, don't discard the shift. */
9531 if (code == LSHIFTRT
9532 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9533 && (GET_MODE_BITSIZE (result_mode)
9534 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9536 varop = XEXP (varop, 0);
9540 /* ... fall through ... */
9545 /* Here we have two nested shifts. The result is usually the
9546 AND of a new shift with a mask. We compute the result below. */
9547 if (CONST_INT_P (XEXP (varop, 1))
9548 && INTVAL (XEXP (varop, 1)) >= 0
9549 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9550 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9551 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9552 && !VECTOR_MODE_P (result_mode))
9554 enum rtx_code first_code = GET_CODE (varop);
9555 unsigned int first_count = INTVAL (XEXP (varop, 1));
9556 unsigned HOST_WIDE_INT mask;
9559 /* We have one common special case. We can't do any merging if
9560 the inner code is an ASHIFTRT of a smaller mode. However, if
9561 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9562 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9563 we can convert it to
9564 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9565 This simplifies certain SIGN_EXTEND operations. */
9566 if (code == ASHIFT && first_code == ASHIFTRT
9567 && count == (GET_MODE_BITSIZE (result_mode)
9568 - GET_MODE_BITSIZE (GET_MODE (varop))))
9570 /* C3 has the low-order C1 bits zero. */
9572 mask = (GET_MODE_MASK (mode)
9573 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9575 varop = simplify_and_const_int (NULL_RTX, result_mode,
9576 XEXP (varop, 0), mask);
9577 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9579 count = first_count;
9584 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9585 than C1 high-order bits equal to the sign bit, we can convert
9586 this to either an ASHIFT or an ASHIFTRT depending on the
9589 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9591 if (code == ASHIFTRT && first_code == ASHIFT
9592 && GET_MODE (varop) == shift_mode
9593 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9596 varop = XEXP (varop, 0);
9597 count -= first_count;
9607 /* There are some cases we can't do. If CODE is ASHIFTRT,
9608 we can only do this if FIRST_CODE is also ASHIFTRT.
9610 We can't do the case when CODE is ROTATE and FIRST_CODE is
9613 If the mode of this shift is not the mode of the outer shift,
9614 we can't do this if either shift is a right shift or ROTATE.
9616 Finally, we can't do any of these if the mode is too wide
9617 unless the codes are the same.
9619 Handle the case where the shift codes are the same
9622 if (code == first_code)
9624 if (GET_MODE (varop) != result_mode
9625 && (code == ASHIFTRT || code == LSHIFTRT
9629 count += first_count;
9630 varop = XEXP (varop, 0);
9634 if (code == ASHIFTRT
9635 || (code == ROTATE && first_code == ASHIFTRT)
9636 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9637 || (GET_MODE (varop) != result_mode
9638 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9639 || first_code == ROTATE
9640 || code == ROTATE)))
9643 /* To compute the mask to apply after the shift, shift the
9644 nonzero bits of the inner shift the same way the
9645 outer shift will. */
9647 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9650 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9653 /* Give up if we can't compute an outer operation to use. */
9655 || !CONST_INT_P (mask_rtx)
9656 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9658 result_mode, &complement_p))
9661 /* If the shifts are in the same direction, we add the
9662 counts. Otherwise, we subtract them. */
9663 if ((code == ASHIFTRT || code == LSHIFTRT)
9664 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9665 count += first_count;
9667 count -= first_count;
9669 /* If COUNT is positive, the new shift is usually CODE,
9670 except for the two exceptions below, in which case it is
9671 FIRST_CODE. If the count is negative, FIRST_CODE should
9674 && ((first_code == ROTATE && code == ASHIFT)
9675 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9678 code = first_code, count = -count;
9680 varop = XEXP (varop, 0);
9684 /* If we have (A << B << C) for any shift, we can convert this to
9685 (A << C << B). This wins if A is a constant. Only try this if
9686 B is not a constant. */
9688 else if (GET_CODE (varop) == code
9689 && CONST_INT_P (XEXP (varop, 0))
9690 && !CONST_INT_P (XEXP (varop, 1)))
9692 rtx new_rtx = simplify_const_binary_operation (code, mode,
9695 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9702 if (VECTOR_MODE_P (mode))
9705 /* Make this fit the case below. */
9706 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9707 GEN_INT (GET_MODE_MASK (mode)));
9713 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9714 with C the size of VAROP - 1 and the shift is logical if
9715 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9716 we have an (le X 0) operation. If we have an arithmetic shift
9717 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9718 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9720 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9721 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9722 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9723 && (code == LSHIFTRT || code == ASHIFTRT)
9724 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9725 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9728 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9731 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9732 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9737 /* If we have (shift (logical)), move the logical to the outside
9738 to allow it to possibly combine with another logical and the
9739 shift to combine with another shift. This also canonicalizes to
9740 what a ZERO_EXTRACT looks like. Also, some machines have
9741 (and (shift)) insns. */
9743 if (CONST_INT_P (XEXP (varop, 1))
9744 /* We can't do this if we have (ashiftrt (xor)) and the
9745 constant has its sign bit set in shift_mode. */
9746 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9747 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9749 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9751 GEN_INT (count))) != 0
9752 && CONST_INT_P (new_rtx)
9753 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9754 INTVAL (new_rtx), result_mode, &complement_p))
9756 varop = XEXP (varop, 0);
9760 /* If we can't do that, try to simplify the shift in each arm of the
9761 logical expression, make a new logical expression, and apply
9762 the inverse distributive law. This also can't be done
9763 for some (ashiftrt (xor)). */
9764 if (CONST_INT_P (XEXP (varop, 1))
9765 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9766 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9769 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9770 XEXP (varop, 0), count);
9771 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9772 XEXP (varop, 1), count);
9774 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9776 varop = apply_distributive_law (varop);
9784 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9785 says that the sign bit can be tested, FOO has mode MODE, C is
9786 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9787 that may be nonzero. */
9788 if (code == LSHIFTRT
9789 && XEXP (varop, 1) == const0_rtx
9790 && GET_MODE (XEXP (varop, 0)) == result_mode
9791 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9792 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9793 && STORE_FLAG_VALUE == -1
9794 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9795 && merge_outer_ops (&outer_op, &outer_const, XOR,
9796 (HOST_WIDE_INT) 1, result_mode,
9799 varop = XEXP (varop, 0);
9806 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9807 than the number of bits in the mode is equivalent to A. */
9808 if (code == LSHIFTRT
9809 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9810 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9812 varop = XEXP (varop, 0);
9817 /* NEG commutes with ASHIFT since it is multiplication. Move the
9818 NEG outside to allow shifts to combine. */
9820 && merge_outer_ops (&outer_op, &outer_const, NEG,
9821 (HOST_WIDE_INT) 0, result_mode,
9824 varop = XEXP (varop, 0);
9830 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9831 is one less than the number of bits in the mode is
9832 equivalent to (xor A 1). */
9833 if (code == LSHIFTRT
9834 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9835 && XEXP (varop, 1) == constm1_rtx
9836 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9837 && merge_outer_ops (&outer_op, &outer_const, XOR,
9838 (HOST_WIDE_INT) 1, result_mode,
9842 varop = XEXP (varop, 0);
9846 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9847 that might be nonzero in BAR are those being shifted out and those
9848 bits are known zero in FOO, we can replace the PLUS with FOO.
9849 Similarly in the other operand order. This code occurs when
9850 we are computing the size of a variable-size array. */
9852 if ((code == ASHIFTRT || code == LSHIFTRT)
9853 && count < HOST_BITS_PER_WIDE_INT
9854 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9855 && (nonzero_bits (XEXP (varop, 1), result_mode)
9856 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9858 varop = XEXP (varop, 0);
9861 else if ((code == ASHIFTRT || code == LSHIFTRT)
9862 && count < HOST_BITS_PER_WIDE_INT
9863 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9864 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9866 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9867 & nonzero_bits (XEXP (varop, 1),
9870 varop = XEXP (varop, 1);
9874 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9876 && CONST_INT_P (XEXP (varop, 1))
9877 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9879 GEN_INT (count))) != 0
9880 && CONST_INT_P (new_rtx)
9881 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9882 INTVAL (new_rtx), result_mode, &complement_p))
9884 varop = XEXP (varop, 0);
9888 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9889 signbit', and attempt to change the PLUS to an XOR and move it to
9890 the outer operation as is done above in the AND/IOR/XOR case
9891 leg for shift(logical). See details in logical handling above
9892 for reasoning in doing so. */
9893 if (code == LSHIFTRT
9894 && CONST_INT_P (XEXP (varop, 1))
9895 && mode_signbit_p (result_mode, XEXP (varop, 1))
9896 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9898 GEN_INT (count))) != 0
9899 && CONST_INT_P (new_rtx)
9900 && merge_outer_ops (&outer_op, &outer_const, XOR,
9901 INTVAL (new_rtx), result_mode, &complement_p))
9903 varop = XEXP (varop, 0);
9910 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9911 with C the size of VAROP - 1 and the shift is logical if
9912 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9913 we have a (gt X 0) operation. If the shift is arithmetic with
9914 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9915 we have a (neg (gt X 0)) operation. */
9917 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9918 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9919 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9920 && (code == LSHIFTRT || code == ASHIFTRT)
9921 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9922 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9923 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9926 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9929 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9930 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9937 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9938 if the truncate does not affect the value. */
9939 if (code == LSHIFTRT
9940 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9941 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9942 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9943 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9944 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9946 rtx varop_inner = XEXP (varop, 0);
9949 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9950 XEXP (varop_inner, 0),
9952 (count + INTVAL (XEXP (varop_inner, 1))));
9953 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9966 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9967 outer_op, outer_const);
9969 /* We have now finished analyzing the shift. The result should be
9970 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9971 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9972 to the result of the shift. OUTER_CONST is the relevant constant,
9973 but we must turn off all bits turned off in the shift. */
9975 if (outer_op == UNKNOWN
9976 && orig_code == code && orig_count == count
9977 && varop == orig_varop
9978 && shift_mode == GET_MODE (varop))
9981 /* Make a SUBREG if necessary. If we can't make it, fail. */
9982 varop = gen_lowpart (shift_mode, varop);
9983 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9986 /* If we have an outer operation and we just made a shift, it is
9987 possible that we could have simplified the shift were it not
9988 for the outer operation. So try to do the simplification
9991 if (outer_op != UNKNOWN)
9992 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9997 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9999 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10000 turn off all the bits that the shift would have turned off. */
10001 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10002 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10003 GET_MODE_MASK (result_mode) >> orig_count);
10005 /* Do the remainder of the processing in RESULT_MODE. */
10006 x = gen_lowpart_or_truncate (result_mode, x);
10008 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10011 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10013 if (outer_op != UNKNOWN)
10015 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10016 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10017 outer_const = trunc_int_for_mode (outer_const, result_mode);
10019 if (outer_op == AND)
10020 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10021 else if (outer_op == SET)
10023 /* This means that we have determined that the result is
10024 equivalent to a constant. This should be rare. */
10025 if (!side_effects_p (x))
10026 x = GEN_INT (outer_const);
10028 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10029 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10031 x = simplify_gen_binary (outer_op, result_mode, x,
10032 GEN_INT (outer_const));
10038 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10039 The result of the shift is RESULT_MODE. If we cannot simplify it,
10040 return X or, if it is NULL, synthesize the expression with
10041 simplify_gen_binary. Otherwise, return a simplified value.
10043 The shift is normally computed in the widest mode we find in VAROP, as
10044 long as it isn't a different number of words than RESULT_MODE. Exceptions
10045 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10048 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10049 rtx varop, int count)
10051 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10056 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10057 if (GET_MODE (x) != result_mode)
10058 x = gen_lowpart (result_mode, x);
10063 /* Like recog, but we receive the address of a pointer to a new pattern.
10064 We try to match the rtx that the pointer points to.
10065 If that fails, we may try to modify or replace the pattern,
10066 storing the replacement into the same pointer object.
10068 Modifications include deletion or addition of CLOBBERs.
10070 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10071 the CLOBBERs are placed.
10073 The value is the final insn code from the pattern ultimately matched,
10077 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10079 rtx pat = *pnewpat;
10080 int insn_code_number;
10081 int num_clobbers_to_add = 0;
10084 rtx old_notes, old_pat;
10086 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10087 we use to indicate that something didn't match. If we find such a
10088 thing, force rejection. */
10089 if (GET_CODE (pat) == PARALLEL)
10090 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10091 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10092 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10095 old_pat = PATTERN (insn);
10096 old_notes = REG_NOTES (insn);
10097 PATTERN (insn) = pat;
10098 REG_NOTES (insn) = 0;
10100 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10101 if (dump_file && (dump_flags & TDF_DETAILS))
10103 if (insn_code_number < 0)
10104 fputs ("Failed to match this instruction:\n", dump_file);
10106 fputs ("Successfully matched this instruction:\n", dump_file);
10107 print_rtl_single (dump_file, pat);
10110 /* If it isn't, there is the possibility that we previously had an insn
10111 that clobbered some register as a side effect, but the combined
10112 insn doesn't need to do that. So try once more without the clobbers
10113 unless this represents an ASM insn. */
10115 if (insn_code_number < 0 && ! check_asm_operands (pat)
10116 && GET_CODE (pat) == PARALLEL)
10120 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10121 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10124 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10128 SUBST_INT (XVECLEN (pat, 0), pos);
10131 pat = XVECEXP (pat, 0, 0);
10133 PATTERN (insn) = pat;
10134 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10135 if (dump_file && (dump_flags & TDF_DETAILS))
10137 if (insn_code_number < 0)
10138 fputs ("Failed to match this instruction:\n", dump_file);
10140 fputs ("Successfully matched this instruction:\n", dump_file);
10141 print_rtl_single (dump_file, pat);
10144 PATTERN (insn) = old_pat;
10145 REG_NOTES (insn) = old_notes;
10147 /* Recognize all noop sets, these will be killed by followup pass. */
10148 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10149 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10151 /* If we had any clobbers to add, make a new pattern than contains
10152 them. Then check to make sure that all of them are dead. */
10153 if (num_clobbers_to_add)
10155 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10156 rtvec_alloc (GET_CODE (pat) == PARALLEL
10157 ? (XVECLEN (pat, 0)
10158 + num_clobbers_to_add)
10159 : num_clobbers_to_add + 1));
10161 if (GET_CODE (pat) == PARALLEL)
10162 for (i = 0; i < XVECLEN (pat, 0); i++)
10163 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10165 XVECEXP (newpat, 0, 0) = pat;
10167 add_clobbers (newpat, insn_code_number);
10169 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10170 i < XVECLEN (newpat, 0); i++)
10172 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10173 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10175 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10177 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10178 notes = alloc_reg_note (REG_UNUSED,
10179 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10188 return insn_code_number;
10191 /* Like gen_lowpart_general but for use by combine. In combine it
10192 is not possible to create any new pseudoregs. However, it is
10193 safe to create invalid memory addresses, because combine will
10194 try to recognize them and all they will do is make the combine
10197 If for some reason this cannot do its job, an rtx
10198 (clobber (const_int 0)) is returned.
10199 An insn containing that will not be recognized. */
10202 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10204 enum machine_mode imode = GET_MODE (x);
10205 unsigned int osize = GET_MODE_SIZE (omode);
10206 unsigned int isize = GET_MODE_SIZE (imode);
10209 if (omode == imode)
10212 /* Return identity if this is a CONST or symbolic reference. */
10214 && (GET_CODE (x) == CONST
10215 || GET_CODE (x) == SYMBOL_REF
10216 || GET_CODE (x) == LABEL_REF))
10219 /* We can only support MODE being wider than a word if X is a
10220 constant integer or has a mode the same size. */
10221 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10222 && ! ((imode == VOIDmode
10223 && (CONST_INT_P (x)
10224 || GET_CODE (x) == CONST_DOUBLE))
10225 || isize == osize))
10228 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10229 won't know what to do. So we will strip off the SUBREG here and
10230 process normally. */
10231 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10233 x = SUBREG_REG (x);
10235 /* For use in case we fall down into the address adjustments
10236 further below, we need to adjust the known mode and size of
10237 x; imode and isize, since we just adjusted x. */
10238 imode = GET_MODE (x);
10240 if (imode == omode)
10243 isize = GET_MODE_SIZE (imode);
10246 result = gen_lowpart_common (omode, x);
10255 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10257 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10260 /* If we want to refer to something bigger than the original memref,
10261 generate a paradoxical subreg instead. That will force a reload
10262 of the original memref X. */
10264 return gen_rtx_SUBREG (omode, x, 0);
10266 if (WORDS_BIG_ENDIAN)
10267 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10269 /* Adjust the address so that the address-after-the-data is
10271 if (BYTES_BIG_ENDIAN)
10272 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10274 return adjust_address_nv (x, omode, offset);
10277 /* If X is a comparison operator, rewrite it in a new mode. This
10278 probably won't match, but may allow further simplifications. */
10279 else if (COMPARISON_P (x))
10280 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10282 /* If we couldn't simplify X any other way, just enclose it in a
10283 SUBREG. Normally, this SUBREG won't match, but some patterns may
10284 include an explicit SUBREG or we may simplify it further in combine. */
10290 offset = subreg_lowpart_offset (omode, imode);
10291 if (imode == VOIDmode)
10293 imode = int_mode_for_mode (omode);
10294 x = gen_lowpart_common (imode, x);
10298 res = simplify_gen_subreg (omode, x, imode, offset);
10304 return gen_rtx_CLOBBER (omode, const0_rtx);
10307 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10308 comparison code that will be tested.
10310 The result is a possibly different comparison code to use. *POP0 and
10311 *POP1 may be updated.
10313 It is possible that we might detect that a comparison is either always
10314 true or always false. However, we do not perform general constant
10315 folding in combine, so this knowledge isn't useful. Such tautologies
10316 should have been detected earlier. Hence we ignore all such cases. */
10318 static enum rtx_code
10319 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10325 enum machine_mode mode, tmode;
10327 /* Try a few ways of applying the same transformation to both operands. */
10330 #ifndef WORD_REGISTER_OPERATIONS
10331 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10332 so check specially. */
10333 if (code != GTU && code != GEU && code != LTU && code != LEU
10334 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10335 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10336 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10337 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10338 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10339 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10340 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10341 && CONST_INT_P (XEXP (op0, 1))
10342 && XEXP (op0, 1) == XEXP (op1, 1)
10343 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10344 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10345 && (INTVAL (XEXP (op0, 1))
10346 == (GET_MODE_BITSIZE (GET_MODE (op0))
10347 - (GET_MODE_BITSIZE
10348 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10350 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10351 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10355 /* If both operands are the same constant shift, see if we can ignore the
10356 shift. We can if the shift is a rotate or if the bits shifted out of
10357 this shift are known to be zero for both inputs and if the type of
10358 comparison is compatible with the shift. */
10359 if (GET_CODE (op0) == GET_CODE (op1)
10360 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10361 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10362 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10363 && (code != GT && code != LT && code != GE && code != LE))
10364 || (GET_CODE (op0) == ASHIFTRT
10365 && (code != GTU && code != LTU
10366 && code != GEU && code != LEU)))
10367 && CONST_INT_P (XEXP (op0, 1))
10368 && INTVAL (XEXP (op0, 1)) >= 0
10369 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10370 && XEXP (op0, 1) == XEXP (op1, 1))
10372 enum machine_mode mode = GET_MODE (op0);
10373 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10374 int shift_count = INTVAL (XEXP (op0, 1));
10376 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10377 mask &= (mask >> shift_count) << shift_count;
10378 else if (GET_CODE (op0) == ASHIFT)
10379 mask = (mask & (mask << shift_count)) >> shift_count;
10381 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10382 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10383 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10388 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10389 SUBREGs are of the same mode, and, in both cases, the AND would
10390 be redundant if the comparison was done in the narrower mode,
10391 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10392 and the operand's possibly nonzero bits are 0xffffff01; in that case
10393 if we only care about QImode, we don't need the AND). This case
10394 occurs if the output mode of an scc insn is not SImode and
10395 STORE_FLAG_VALUE == 1 (e.g., the 386).
10397 Similarly, check for a case where the AND's are ZERO_EXTEND
10398 operations from some narrower mode even though a SUBREG is not
10401 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10402 && CONST_INT_P (XEXP (op0, 1))
10403 && CONST_INT_P (XEXP (op1, 1)))
10405 rtx inner_op0 = XEXP (op0, 0);
10406 rtx inner_op1 = XEXP (op1, 0);
10407 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10408 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10411 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10412 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10413 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10414 && (GET_MODE (SUBREG_REG (inner_op0))
10415 == GET_MODE (SUBREG_REG (inner_op1)))
10416 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10417 <= HOST_BITS_PER_WIDE_INT)
10418 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10419 GET_MODE (SUBREG_REG (inner_op0)))))
10420 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10421 GET_MODE (SUBREG_REG (inner_op1))))))
10423 op0 = SUBREG_REG (inner_op0);
10424 op1 = SUBREG_REG (inner_op1);
10426 /* The resulting comparison is always unsigned since we masked
10427 off the original sign bit. */
10428 code = unsigned_condition (code);
10434 for (tmode = GET_CLASS_NARROWEST_MODE
10435 (GET_MODE_CLASS (GET_MODE (op0)));
10436 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10437 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10439 op0 = gen_lowpart (tmode, inner_op0);
10440 op1 = gen_lowpart (tmode, inner_op1);
10441 code = unsigned_condition (code);
10450 /* If both operands are NOT, we can strip off the outer operation
10451 and adjust the comparison code for swapped operands; similarly for
10452 NEG, except that this must be an equality comparison. */
10453 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10454 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10455 && (code == EQ || code == NE)))
10456 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10462 /* If the first operand is a constant, swap the operands and adjust the
10463 comparison code appropriately, but don't do this if the second operand
10464 is already a constant integer. */
10465 if (swap_commutative_operands_p (op0, op1))
10467 tem = op0, op0 = op1, op1 = tem;
10468 code = swap_condition (code);
10471 /* We now enter a loop during which we will try to simplify the comparison.
10472 For the most part, we only are concerned with comparisons with zero,
10473 but some things may really be comparisons with zero but not start
10474 out looking that way. */
10476 while (CONST_INT_P (op1))
10478 enum machine_mode mode = GET_MODE (op0);
10479 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10480 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10481 int equality_comparison_p;
10482 int sign_bit_comparison_p;
10483 int unsigned_comparison_p;
10484 HOST_WIDE_INT const_op;
10486 /* We only want to handle integral modes. This catches VOIDmode,
10487 CCmode, and the floating-point modes. An exception is that we
10488 can handle VOIDmode if OP0 is a COMPARE or a comparison
10491 if (GET_MODE_CLASS (mode) != MODE_INT
10492 && ! (mode == VOIDmode
10493 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10496 /* Get the constant we are comparing against and turn off all bits
10497 not on in our mode. */
10498 const_op = INTVAL (op1);
10499 if (mode != VOIDmode)
10500 const_op = trunc_int_for_mode (const_op, mode);
10501 op1 = GEN_INT (const_op);
10503 /* If we are comparing against a constant power of two and the value
10504 being compared can only have that single bit nonzero (e.g., it was
10505 `and'ed with that bit), we can replace this with a comparison
10508 && (code == EQ || code == NE || code == GE || code == GEU
10509 || code == LT || code == LTU)
10510 && mode_width <= HOST_BITS_PER_WIDE_INT
10511 && exact_log2 (const_op) >= 0
10512 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10514 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10515 op1 = const0_rtx, const_op = 0;
10518 /* Similarly, if we are comparing a value known to be either -1 or
10519 0 with -1, change it to the opposite comparison against zero. */
10522 && (code == EQ || code == NE || code == GT || code == LE
10523 || code == GEU || code == LTU)
10524 && num_sign_bit_copies (op0, mode) == mode_width)
10526 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10527 op1 = const0_rtx, const_op = 0;
10530 /* Do some canonicalizations based on the comparison code. We prefer
10531 comparisons against zero and then prefer equality comparisons.
10532 If we can reduce the size of a constant, we will do that too. */
10537 /* < C is equivalent to <= (C - 1) */
10541 op1 = GEN_INT (const_op);
10543 /* ... fall through to LE case below. */
10549 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10553 op1 = GEN_INT (const_op);
10557 /* If we are doing a <= 0 comparison on a value known to have
10558 a zero sign bit, we can replace this with == 0. */
10559 else if (const_op == 0
10560 && mode_width <= HOST_BITS_PER_WIDE_INT
10561 && (nonzero_bits (op0, mode)
10562 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10567 /* >= C is equivalent to > (C - 1). */
10571 op1 = GEN_INT (const_op);
10573 /* ... fall through to GT below. */
10579 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10583 op1 = GEN_INT (const_op);
10587 /* If we are doing a > 0 comparison on a value known to have
10588 a zero sign bit, we can replace this with != 0. */
10589 else if (const_op == 0
10590 && mode_width <= HOST_BITS_PER_WIDE_INT
10591 && (nonzero_bits (op0, mode)
10592 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10597 /* < C is equivalent to <= (C - 1). */
10601 op1 = GEN_INT (const_op);
10603 /* ... fall through ... */
10606 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10607 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10608 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10610 const_op = 0, op1 = const0_rtx;
10618 /* unsigned <= 0 is equivalent to == 0 */
10622 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10623 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10624 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10626 const_op = 0, op1 = const0_rtx;
10632 /* >= C is equivalent to > (C - 1). */
10636 op1 = GEN_INT (const_op);
10638 /* ... fall through ... */
10641 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10642 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10643 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10645 const_op = 0, op1 = const0_rtx;
10653 /* unsigned > 0 is equivalent to != 0 */
10657 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10658 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10659 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10661 const_op = 0, op1 = const0_rtx;
10670 /* Compute some predicates to simplify code below. */
10672 equality_comparison_p = (code == EQ || code == NE);
10673 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10674 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10677 /* If this is a sign bit comparison and we can do arithmetic in
10678 MODE, say that we will only be needing the sign bit of OP0. */
10679 if (sign_bit_comparison_p
10680 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10681 op0 = force_to_mode (op0, mode,
10683 << (GET_MODE_BITSIZE (mode) - 1)),
10686 /* Now try cases based on the opcode of OP0. If none of the cases
10687 does a "continue", we exit this loop immediately after the
10690 switch (GET_CODE (op0))
10693 /* If we are extracting a single bit from a variable position in
10694 a constant that has only a single bit set and are comparing it
10695 with zero, we can convert this into an equality comparison
10696 between the position and the location of the single bit. */
10697 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10698 have already reduced the shift count modulo the word size. */
10699 if (!SHIFT_COUNT_TRUNCATED
10700 && CONST_INT_P (XEXP (op0, 0))
10701 && XEXP (op0, 1) == const1_rtx
10702 && equality_comparison_p && const_op == 0
10703 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10705 if (BITS_BIG_ENDIAN)
10707 enum machine_mode new_mode
10708 = mode_for_extraction (EP_extzv, 1);
10709 if (new_mode == MAX_MACHINE_MODE)
10710 i = BITS_PER_WORD - 1 - i;
10714 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10718 op0 = XEXP (op0, 2);
10722 /* Result is nonzero iff shift count is equal to I. */
10723 code = reverse_condition (code);
10727 /* ... fall through ... */
10730 tem = expand_compound_operation (op0);
10739 /* If testing for equality, we can take the NOT of the constant. */
10740 if (equality_comparison_p
10741 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10743 op0 = XEXP (op0, 0);
10748 /* If just looking at the sign bit, reverse the sense of the
10750 if (sign_bit_comparison_p)
10752 op0 = XEXP (op0, 0);
10753 code = (code == GE ? LT : GE);
10759 /* If testing for equality, we can take the NEG of the constant. */
10760 if (equality_comparison_p
10761 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10763 op0 = XEXP (op0, 0);
10768 /* The remaining cases only apply to comparisons with zero. */
10772 /* When X is ABS or is known positive,
10773 (neg X) is < 0 if and only if X != 0. */
10775 if (sign_bit_comparison_p
10776 && (GET_CODE (XEXP (op0, 0)) == ABS
10777 || (mode_width <= HOST_BITS_PER_WIDE_INT
10778 && (nonzero_bits (XEXP (op0, 0), mode)
10779 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10781 op0 = XEXP (op0, 0);
10782 code = (code == LT ? NE : EQ);
10786 /* If we have NEG of something whose two high-order bits are the
10787 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10788 if (num_sign_bit_copies (op0, mode) >= 2)
10790 op0 = XEXP (op0, 0);
10791 code = swap_condition (code);
10797 /* If we are testing equality and our count is a constant, we
10798 can perform the inverse operation on our RHS. */
10799 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10800 && (tem = simplify_binary_operation (ROTATERT, mode,
10801 op1, XEXP (op0, 1))) != 0)
10803 op0 = XEXP (op0, 0);
10808 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10809 a particular bit. Convert it to an AND of a constant of that
10810 bit. This will be converted into a ZERO_EXTRACT. */
10811 if (const_op == 0 && sign_bit_comparison_p
10812 && CONST_INT_P (XEXP (op0, 1))
10813 && mode_width <= HOST_BITS_PER_WIDE_INT)
10815 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10818 - INTVAL (XEXP (op0, 1)))));
10819 code = (code == LT ? NE : EQ);
10823 /* Fall through. */
10826 /* ABS is ignorable inside an equality comparison with zero. */
10827 if (const_op == 0 && equality_comparison_p)
10829 op0 = XEXP (op0, 0);
10835 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10836 (compare FOO CONST) if CONST fits in FOO's mode and we
10837 are either testing inequality or have an unsigned
10838 comparison with ZERO_EXTEND or a signed comparison with
10839 SIGN_EXTEND. But don't do it if we don't have a compare
10840 insn of the given mode, since we'd have to revert it
10841 later on, and then we wouldn't know whether to sign- or
10843 mode = GET_MODE (XEXP (op0, 0));
10844 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10845 && ! unsigned_comparison_p
10846 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10847 && ((unsigned HOST_WIDE_INT) const_op
10848 < (((unsigned HOST_WIDE_INT) 1
10849 << (GET_MODE_BITSIZE (mode) - 1))))
10850 && have_insn_for (COMPARE, mode))
10852 op0 = XEXP (op0, 0);
10858 /* Check for the case where we are comparing A - C1 with C2, that is
10860 (subreg:MODE (plus (A) (-C1))) op (C2)
10862 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10863 comparison in the wider mode. One of the following two conditions
10864 must be true in order for this to be valid:
10866 1. The mode extension results in the same bit pattern being added
10867 on both sides and the comparison is equality or unsigned. As
10868 C2 has been truncated to fit in MODE, the pattern can only be
10871 2. The mode extension results in the sign bit being copied on
10874 The difficulty here is that we have predicates for A but not for
10875 (A - C1) so we need to check that C1 is within proper bounds so
10876 as to perturbate A as little as possible. */
10878 if (mode_width <= HOST_BITS_PER_WIDE_INT
10879 && subreg_lowpart_p (op0)
10880 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10881 && GET_CODE (SUBREG_REG (op0)) == PLUS
10882 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10884 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10885 rtx a = XEXP (SUBREG_REG (op0), 0);
10886 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10889 && (unsigned HOST_WIDE_INT) c1
10890 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10891 && (equality_comparison_p || unsigned_comparison_p)
10892 /* (A - C1) zero-extends if it is positive and sign-extends
10893 if it is negative, C2 both zero- and sign-extends. */
10894 && ((0 == (nonzero_bits (a, inner_mode)
10895 & ~GET_MODE_MASK (mode))
10897 /* (A - C1) sign-extends if it is positive and 1-extends
10898 if it is negative, C2 both sign- and 1-extends. */
10899 || (num_sign_bit_copies (a, inner_mode)
10900 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10903 || ((unsigned HOST_WIDE_INT) c1
10904 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10905 /* (A - C1) always sign-extends, like C2. */
10906 && num_sign_bit_copies (a, inner_mode)
10907 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10908 - (mode_width - 1))))
10910 op0 = SUBREG_REG (op0);
10915 /* If the inner mode is narrower and we are extracting the low part,
10916 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10917 if (subreg_lowpart_p (op0)
10918 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10919 /* Fall through */ ;
10923 /* ... fall through ... */
10926 mode = GET_MODE (XEXP (op0, 0));
10927 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10928 && (unsigned_comparison_p || equality_comparison_p)
10929 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10930 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10931 && have_insn_for (COMPARE, mode))
10933 op0 = XEXP (op0, 0);
10939 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10940 this for equality comparisons due to pathological cases involving
10942 if (equality_comparison_p
10943 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10944 op1, XEXP (op0, 1))))
10946 op0 = XEXP (op0, 0);
10951 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10952 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10953 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10955 op0 = XEXP (XEXP (op0, 0), 0);
10956 code = (code == LT ? EQ : NE);
10962 /* We used to optimize signed comparisons against zero, but that
10963 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10964 arrive here as equality comparisons, or (GEU, LTU) are
10965 optimized away. No need to special-case them. */
10967 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10968 (eq B (minus A C)), whichever simplifies. We can only do
10969 this for equality comparisons due to pathological cases involving
10971 if (equality_comparison_p
10972 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10973 XEXP (op0, 1), op1)))
10975 op0 = XEXP (op0, 0);
10980 if (equality_comparison_p
10981 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10982 XEXP (op0, 0), op1)))
10984 op0 = XEXP (op0, 1);
10989 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10990 of bits in X minus 1, is one iff X > 0. */
10991 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10992 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10993 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10995 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10997 op0 = XEXP (op0, 1);
10998 code = (code == GE ? LE : GT);
11004 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11005 if C is zero or B is a constant. */
11006 if (equality_comparison_p
11007 && 0 != (tem = simplify_binary_operation (XOR, mode,
11008 XEXP (op0, 1), op1)))
11010 op0 = XEXP (op0, 0);
11017 case UNEQ: case LTGT:
11018 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11019 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11020 case UNORDERED: case ORDERED:
11021 /* We can't do anything if OP0 is a condition code value, rather
11022 than an actual data value. */
11024 || CC0_P (XEXP (op0, 0))
11025 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11028 /* Get the two operands being compared. */
11029 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11030 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11032 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11034 /* Check for the cases where we simply want the result of the
11035 earlier test or the opposite of that result. */
11036 if (code == NE || code == EQ
11037 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11038 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11039 && (STORE_FLAG_VALUE
11040 & (((HOST_WIDE_INT) 1
11041 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11042 && (code == LT || code == GE)))
11044 enum rtx_code new_code;
11045 if (code == LT || code == NE)
11046 new_code = GET_CODE (op0);
11048 new_code = reversed_comparison_code (op0, NULL);
11050 if (new_code != UNKNOWN)
11061 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11063 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11064 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11065 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11067 op0 = XEXP (op0, 1);
11068 code = (code == GE ? GT : LE);
11074 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11075 will be converted to a ZERO_EXTRACT later. */
11076 if (const_op == 0 && equality_comparison_p
11077 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11078 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11080 op0 = simplify_and_const_int
11081 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11083 XEXP (XEXP (op0, 0), 1)),
11084 (HOST_WIDE_INT) 1);
11088 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11089 zero and X is a comparison and C1 and C2 describe only bits set
11090 in STORE_FLAG_VALUE, we can compare with X. */
11091 if (const_op == 0 && equality_comparison_p
11092 && mode_width <= HOST_BITS_PER_WIDE_INT
11093 && CONST_INT_P (XEXP (op0, 1))
11094 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11095 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11096 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11097 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11099 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11100 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11101 if ((~STORE_FLAG_VALUE & mask) == 0
11102 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11103 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11104 && COMPARISON_P (tem))))
11106 op0 = XEXP (XEXP (op0, 0), 0);
11111 /* If we are doing an equality comparison of an AND of a bit equal
11112 to the sign bit, replace this with a LT or GE comparison of
11113 the underlying value. */
11114 if (equality_comparison_p
11116 && CONST_INT_P (XEXP (op0, 1))
11117 && mode_width <= HOST_BITS_PER_WIDE_INT
11118 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11119 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11121 op0 = XEXP (op0, 0);
11122 code = (code == EQ ? GE : LT);
11126 /* If this AND operation is really a ZERO_EXTEND from a narrower
11127 mode, the constant fits within that mode, and this is either an
11128 equality or unsigned comparison, try to do this comparison in
11133 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11134 -> (ne:DI (reg:SI 4) (const_int 0))
11136 unless TRULY_NOOP_TRUNCATION allows it or the register is
11137 known to hold a value of the required mode the
11138 transformation is invalid. */
11139 if ((equality_comparison_p || unsigned_comparison_p)
11140 && CONST_INT_P (XEXP (op0, 1))
11141 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11142 & GET_MODE_MASK (mode))
11144 && const_op >> i == 0
11145 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11146 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11147 GET_MODE_BITSIZE (GET_MODE (op0)))
11148 || (REG_P (XEXP (op0, 0))
11149 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11151 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11155 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11156 fits in both M1 and M2 and the SUBREG is either paradoxical
11157 or represents the low part, permute the SUBREG and the AND
11159 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11161 unsigned HOST_WIDE_INT c1;
11162 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11163 /* Require an integral mode, to avoid creating something like
11165 if (SCALAR_INT_MODE_P (tmode)
11166 /* It is unsafe to commute the AND into the SUBREG if the
11167 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11168 not defined. As originally written the upper bits
11169 have a defined value due to the AND operation.
11170 However, if we commute the AND inside the SUBREG then
11171 they no longer have defined values and the meaning of
11172 the code has been changed. */
11174 #ifdef WORD_REGISTER_OPERATIONS
11175 || (mode_width > GET_MODE_BITSIZE (tmode)
11176 && mode_width <= BITS_PER_WORD)
11178 || (mode_width <= GET_MODE_BITSIZE (tmode)
11179 && subreg_lowpart_p (XEXP (op0, 0))))
11180 && CONST_INT_P (XEXP (op0, 1))
11181 && mode_width <= HOST_BITS_PER_WIDE_INT
11182 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11183 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11184 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11186 && c1 != GET_MODE_MASK (tmode))
11188 op0 = simplify_gen_binary (AND, tmode,
11189 SUBREG_REG (XEXP (op0, 0)),
11190 gen_int_mode (c1, tmode));
11191 op0 = gen_lowpart (mode, op0);
11196 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11197 if (const_op == 0 && equality_comparison_p
11198 && XEXP (op0, 1) == const1_rtx
11199 && GET_CODE (XEXP (op0, 0)) == NOT)
11201 op0 = simplify_and_const_int
11202 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11203 code = (code == NE ? EQ : NE);
11207 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11208 (eq (and (lshiftrt X) 1) 0).
11209 Also handle the case where (not X) is expressed using xor. */
11210 if (const_op == 0 && equality_comparison_p
11211 && XEXP (op0, 1) == const1_rtx
11212 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11214 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11215 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11217 if (GET_CODE (shift_op) == NOT
11218 || (GET_CODE (shift_op) == XOR
11219 && CONST_INT_P (XEXP (shift_op, 1))
11220 && CONST_INT_P (shift_count)
11221 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11222 && (INTVAL (XEXP (shift_op, 1))
11223 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11225 op0 = simplify_and_const_int
11227 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11228 (HOST_WIDE_INT) 1);
11229 code = (code == NE ? EQ : NE);
11236 /* If we have (compare (ashift FOO N) (const_int C)) and
11237 the high order N bits of FOO (N+1 if an inequality comparison)
11238 are known to be zero, we can do this by comparing FOO with C
11239 shifted right N bits so long as the low-order N bits of C are
11241 if (CONST_INT_P (XEXP (op0, 1))
11242 && INTVAL (XEXP (op0, 1)) >= 0
11243 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11244 < HOST_BITS_PER_WIDE_INT)
11246 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11247 && mode_width <= HOST_BITS_PER_WIDE_INT
11248 && (nonzero_bits (XEXP (op0, 0), mode)
11249 & ~(mask >> (INTVAL (XEXP (op0, 1))
11250 + ! equality_comparison_p))) == 0)
11252 /* We must perform a logical shift, not an arithmetic one,
11253 as we want the top N bits of C to be zero. */
11254 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11256 temp >>= INTVAL (XEXP (op0, 1));
11257 op1 = gen_int_mode (temp, mode);
11258 op0 = XEXP (op0, 0);
11262 /* If we are doing a sign bit comparison, it means we are testing
11263 a particular bit. Convert it to the appropriate AND. */
11264 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11265 && mode_width <= HOST_BITS_PER_WIDE_INT)
11267 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11270 - INTVAL (XEXP (op0, 1)))));
11271 code = (code == LT ? NE : EQ);
11275 /* If this an equality comparison with zero and we are shifting
11276 the low bit to the sign bit, we can convert this to an AND of the
11278 if (const_op == 0 && equality_comparison_p
11279 && CONST_INT_P (XEXP (op0, 1))
11280 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11283 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11284 (HOST_WIDE_INT) 1);
11290 /* If this is an equality comparison with zero, we can do this
11291 as a logical shift, which might be much simpler. */
11292 if (equality_comparison_p && const_op == 0
11293 && CONST_INT_P (XEXP (op0, 1)))
11295 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11297 INTVAL (XEXP (op0, 1)));
11301 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11302 do the comparison in a narrower mode. */
11303 if (! unsigned_comparison_p
11304 && CONST_INT_P (XEXP (op0, 1))
11305 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11306 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11307 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11308 MODE_INT, 1)) != BLKmode
11309 && (((unsigned HOST_WIDE_INT) const_op
11310 + (GET_MODE_MASK (tmode) >> 1) + 1)
11311 <= GET_MODE_MASK (tmode)))
11313 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11317 /* Likewise if OP0 is a PLUS of a sign extension with a
11318 constant, which is usually represented with the PLUS
11319 between the shifts. */
11320 if (! unsigned_comparison_p
11321 && CONST_INT_P (XEXP (op0, 1))
11322 && GET_CODE (XEXP (op0, 0)) == PLUS
11323 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11324 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11325 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11326 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11327 MODE_INT, 1)) != BLKmode
11328 && (((unsigned HOST_WIDE_INT) const_op
11329 + (GET_MODE_MASK (tmode) >> 1) + 1)
11330 <= GET_MODE_MASK (tmode)))
11332 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11333 rtx add_const = XEXP (XEXP (op0, 0), 1);
11334 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11335 add_const, XEXP (op0, 1));
11337 op0 = simplify_gen_binary (PLUS, tmode,
11338 gen_lowpart (tmode, inner),
11343 /* ... fall through ... */
11345 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11346 the low order N bits of FOO are known to be zero, we can do this
11347 by comparing FOO with C shifted left N bits so long as no
11348 overflow occurs. */
11349 if (CONST_INT_P (XEXP (op0, 1))
11350 && INTVAL (XEXP (op0, 1)) >= 0
11351 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11352 && mode_width <= HOST_BITS_PER_WIDE_INT
11353 && (nonzero_bits (XEXP (op0, 0), mode)
11354 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11355 && (((unsigned HOST_WIDE_INT) const_op
11356 + (GET_CODE (op0) != LSHIFTRT
11357 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11360 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11362 /* If the shift was logical, then we must make the condition
11364 if (GET_CODE (op0) == LSHIFTRT)
11365 code = unsigned_condition (code);
11367 const_op <<= INTVAL (XEXP (op0, 1));
11368 op1 = GEN_INT (const_op);
11369 op0 = XEXP (op0, 0);
11373 /* If we are using this shift to extract just the sign bit, we
11374 can replace this with an LT or GE comparison. */
11376 && (equality_comparison_p || sign_bit_comparison_p)
11377 && CONST_INT_P (XEXP (op0, 1))
11378 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11381 op0 = XEXP (op0, 0);
11382 code = (code == NE || code == GT ? LT : GE);
11394 /* Now make any compound operations involved in this comparison. Then,
11395 check for an outmost SUBREG on OP0 that is not doing anything or is
11396 paradoxical. The latter transformation must only be performed when
11397 it is known that the "extra" bits will be the same in op0 and op1 or
11398 that they don't matter. There are three cases to consider:
11400 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11401 care bits and we can assume they have any convenient value. So
11402 making the transformation is safe.
11404 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11405 In this case the upper bits of op0 are undefined. We should not make
11406 the simplification in that case as we do not know the contents of
11409 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11410 UNKNOWN. In that case we know those bits are zeros or ones. We must
11411 also be sure that they are the same as the upper bits of op1.
11413 We can never remove a SUBREG for a non-equality comparison because
11414 the sign bit is in a different place in the underlying object. */
11416 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11417 op1 = make_compound_operation (op1, SET);
11419 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11420 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11421 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11422 && (code == NE || code == EQ))
11424 if (GET_MODE_SIZE (GET_MODE (op0))
11425 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11427 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11429 if (REG_P (SUBREG_REG (op0)))
11431 op0 = SUBREG_REG (op0);
11432 op1 = gen_lowpart (GET_MODE (op0), op1);
11435 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11436 <= HOST_BITS_PER_WIDE_INT)
11437 && (nonzero_bits (SUBREG_REG (op0),
11438 GET_MODE (SUBREG_REG (op0)))
11439 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11441 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11443 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11444 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11445 op0 = SUBREG_REG (op0), op1 = tem;
11449 /* We now do the opposite procedure: Some machines don't have compare
11450 insns in all modes. If OP0's mode is an integer mode smaller than a
11451 word and we can't do a compare in that mode, see if there is a larger
11452 mode for which we can do the compare. There are a number of cases in
11453 which we can use the wider mode. */
11455 mode = GET_MODE (op0);
11456 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11457 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11458 && ! have_insn_for (COMPARE, mode))
11459 for (tmode = GET_MODE_WIDER_MODE (mode);
11461 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11462 tmode = GET_MODE_WIDER_MODE (tmode))
11463 if (have_insn_for (COMPARE, tmode))
11467 /* If the only nonzero bits in OP0 and OP1 are those in the
11468 narrower mode and this is an equality or unsigned comparison,
11469 we can use the wider mode. Similarly for sign-extended
11470 values, in which case it is true for all comparisons. */
11471 zero_extended = ((code == EQ || code == NE
11472 || code == GEU || code == GTU
11473 || code == LEU || code == LTU)
11474 && (nonzero_bits (op0, tmode)
11475 & ~GET_MODE_MASK (mode)) == 0
11476 && ((CONST_INT_P (op1)
11477 || (nonzero_bits (op1, tmode)
11478 & ~GET_MODE_MASK (mode)) == 0)));
11481 || ((num_sign_bit_copies (op0, tmode)
11482 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11483 - GET_MODE_BITSIZE (mode)))
11484 && (num_sign_bit_copies (op1, tmode)
11485 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11486 - GET_MODE_BITSIZE (mode)))))
11488 /* If OP0 is an AND and we don't have an AND in MODE either,
11489 make a new AND in the proper mode. */
11490 if (GET_CODE (op0) == AND
11491 && !have_insn_for (AND, mode))
11492 op0 = simplify_gen_binary (AND, tmode,
11493 gen_lowpart (tmode,
11495 gen_lowpart (tmode,
11498 op0 = gen_lowpart (tmode, op0);
11499 if (zero_extended && CONST_INT_P (op1))
11500 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11501 op1 = gen_lowpart (tmode, op1);
11505 /* If this is a test for negative, we can make an explicit
11506 test of the sign bit. */
11508 if (op1 == const0_rtx && (code == LT || code == GE)
11509 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11511 op0 = simplify_gen_binary (AND, tmode,
11512 gen_lowpart (tmode, op0),
11513 GEN_INT ((HOST_WIDE_INT) 1
11514 << (GET_MODE_BITSIZE (mode)
11516 code = (code == LT) ? NE : EQ;
11521 #ifdef CANONICALIZE_COMPARISON
11522 /* If this machine only supports a subset of valid comparisons, see if we
11523 can convert an unsupported one into a supported one. */
11524 CANONICALIZE_COMPARISON (code, op0, op1);
11533 /* Utility function for record_value_for_reg. Count number of
11538 enum rtx_code code = GET_CODE (x);
11542 if (GET_RTX_CLASS (code) == '2'
11543 || GET_RTX_CLASS (code) == 'c')
11545 rtx x0 = XEXP (x, 0);
11546 rtx x1 = XEXP (x, 1);
11549 return 1 + 2 * count_rtxs (x0);
11551 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11552 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11553 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11554 return 2 + 2 * count_rtxs (x0)
11555 + count_rtxs (x == XEXP (x1, 0)
11556 ? XEXP (x1, 1) : XEXP (x1, 0));
11558 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11559 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11560 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11561 return 2 + 2 * count_rtxs (x1)
11562 + count_rtxs (x == XEXP (x0, 0)
11563 ? XEXP (x0, 1) : XEXP (x0, 0));
11566 fmt = GET_RTX_FORMAT (code);
11567 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11569 ret += count_rtxs (XEXP (x, i));
11570 else if (fmt[i] == 'E')
11571 for (j = 0; j < XVECLEN (x, i); j++)
11572 ret += count_rtxs (XVECEXP (x, i, j));
11577 /* Utility function for following routine. Called when X is part of a value
11578 being stored into last_set_value. Sets last_set_table_tick
11579 for each register mentioned. Similar to mention_regs in cse.c */
11582 update_table_tick (rtx x)
11584 enum rtx_code code = GET_CODE (x);
11585 const char *fmt = GET_RTX_FORMAT (code);
11590 unsigned int regno = REGNO (x);
11591 unsigned int endregno = END_REGNO (x);
11594 for (r = regno; r < endregno; r++)
11596 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11597 rsp->last_set_table_tick = label_tick;
11603 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11606 /* Check for identical subexpressions. If x contains
11607 identical subexpression we only have to traverse one of
11609 if (i == 0 && ARITHMETIC_P (x))
11611 /* Note that at this point x1 has already been
11613 rtx x0 = XEXP (x, 0);
11614 rtx x1 = XEXP (x, 1);
11616 /* If x0 and x1 are identical then there is no need to
11621 /* If x0 is identical to a subexpression of x1 then while
11622 processing x1, x0 has already been processed. Thus we
11623 are done with x. */
11624 if (ARITHMETIC_P (x1)
11625 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11628 /* If x1 is identical to a subexpression of x0 then we
11629 still have to process the rest of x0. */
11630 if (ARITHMETIC_P (x0)
11631 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11633 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11638 update_table_tick (XEXP (x, i));
11640 else if (fmt[i] == 'E')
11641 for (j = 0; j < XVECLEN (x, i); j++)
11642 update_table_tick (XVECEXP (x, i, j));
11645 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11646 are saying that the register is clobbered and we no longer know its
11647 value. If INSN is zero, don't update reg_stat[].last_set; this is
11648 only permitted with VALUE also zero and is used to invalidate the
11652 record_value_for_reg (rtx reg, rtx insn, rtx value)
11654 unsigned int regno = REGNO (reg);
11655 unsigned int endregno = END_REGNO (reg);
11657 reg_stat_type *rsp;
11659 /* If VALUE contains REG and we have a previous value for REG, substitute
11660 the previous value. */
11661 if (value && insn && reg_overlap_mentioned_p (reg, value))
11665 /* Set things up so get_last_value is allowed to see anything set up to
11667 subst_low_luid = DF_INSN_LUID (insn);
11668 tem = get_last_value (reg);
11670 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11671 it isn't going to be useful and will take a lot of time to process,
11672 so just use the CLOBBER. */
11676 if (ARITHMETIC_P (tem)
11677 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11678 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11679 tem = XEXP (tem, 0);
11680 else if (count_occurrences (value, reg, 1) >= 2)
11682 /* If there are two or more occurrences of REG in VALUE,
11683 prevent the value from growing too much. */
11684 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11685 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11688 value = replace_rtx (copy_rtx (value), reg, tem);
11692 /* For each register modified, show we don't know its value, that
11693 we don't know about its bitwise content, that its value has been
11694 updated, and that we don't know the location of the death of the
11696 for (i = regno; i < endregno; i++)
11698 rsp = VEC_index (reg_stat_type, reg_stat, i);
11701 rsp->last_set = insn;
11703 rsp->last_set_value = 0;
11704 rsp->last_set_mode = VOIDmode;
11705 rsp->last_set_nonzero_bits = 0;
11706 rsp->last_set_sign_bit_copies = 0;
11707 rsp->last_death = 0;
11708 rsp->truncated_to_mode = VOIDmode;
11711 /* Mark registers that are being referenced in this value. */
11713 update_table_tick (value);
11715 /* Now update the status of each register being set.
11716 If someone is using this register in this block, set this register
11717 to invalid since we will get confused between the two lives in this
11718 basic block. This makes using this register always invalid. In cse, we
11719 scan the table to invalidate all entries using this register, but this
11720 is too much work for us. */
11722 for (i = regno; i < endregno; i++)
11724 rsp = VEC_index (reg_stat_type, reg_stat, i);
11725 rsp->last_set_label = label_tick;
11727 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11728 rsp->last_set_invalid = 1;
11730 rsp->last_set_invalid = 0;
11733 /* The value being assigned might refer to X (like in "x++;"). In that
11734 case, we must replace it with (clobber (const_int 0)) to prevent
11736 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11737 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11739 value = copy_rtx (value);
11740 if (!get_last_value_validate (&value, insn, label_tick, 1))
11744 /* For the main register being modified, update the value, the mode, the
11745 nonzero bits, and the number of sign bit copies. */
11747 rsp->last_set_value = value;
11751 enum machine_mode mode = GET_MODE (reg);
11752 subst_low_luid = DF_INSN_LUID (insn);
11753 rsp->last_set_mode = mode;
11754 if (GET_MODE_CLASS (mode) == MODE_INT
11755 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11756 mode = nonzero_bits_mode;
11757 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11758 rsp->last_set_sign_bit_copies
11759 = num_sign_bit_copies (value, GET_MODE (reg));
11763 /* Called via note_stores from record_dead_and_set_regs to handle one
11764 SET or CLOBBER in an insn. DATA is the instruction in which the
11765 set is occurring. */
11768 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11770 rtx record_dead_insn = (rtx) data;
11772 if (GET_CODE (dest) == SUBREG)
11773 dest = SUBREG_REG (dest);
11775 if (!record_dead_insn)
11778 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11784 /* If we are setting the whole register, we know its value. Otherwise
11785 show that we don't know the value. We can handle SUBREG in
11787 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11788 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11789 else if (GET_CODE (setter) == SET
11790 && GET_CODE (SET_DEST (setter)) == SUBREG
11791 && SUBREG_REG (SET_DEST (setter)) == dest
11792 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11793 && subreg_lowpart_p (SET_DEST (setter)))
11794 record_value_for_reg (dest, record_dead_insn,
11795 gen_lowpart (GET_MODE (dest),
11796 SET_SRC (setter)));
11798 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11800 else if (MEM_P (dest)
11801 /* Ignore pushes, they clobber nothing. */
11802 && ! push_operand (dest, GET_MODE (dest)))
11803 mem_last_set = DF_INSN_LUID (record_dead_insn);
11806 /* Update the records of when each REG was most recently set or killed
11807 for the things done by INSN. This is the last thing done in processing
11808 INSN in the combiner loop.
11810 We update reg_stat[], in particular fields last_set, last_set_value,
11811 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11812 last_death, and also the similar information mem_last_set (which insn
11813 most recently modified memory) and last_call_luid (which insn was the
11814 most recent subroutine call). */
11817 record_dead_and_set_regs (rtx insn)
11822 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11824 if (REG_NOTE_KIND (link) == REG_DEAD
11825 && REG_P (XEXP (link, 0)))
11827 unsigned int regno = REGNO (XEXP (link, 0));
11828 unsigned int endregno = END_REGNO (XEXP (link, 0));
11830 for (i = regno; i < endregno; i++)
11832 reg_stat_type *rsp;
11834 rsp = VEC_index (reg_stat_type, reg_stat, i);
11835 rsp->last_death = insn;
11838 else if (REG_NOTE_KIND (link) == REG_INC)
11839 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11844 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11845 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11847 reg_stat_type *rsp;
11849 rsp = VEC_index (reg_stat_type, reg_stat, i);
11850 rsp->last_set_invalid = 1;
11851 rsp->last_set = insn;
11852 rsp->last_set_value = 0;
11853 rsp->last_set_mode = VOIDmode;
11854 rsp->last_set_nonzero_bits = 0;
11855 rsp->last_set_sign_bit_copies = 0;
11856 rsp->last_death = 0;
11857 rsp->truncated_to_mode = VOIDmode;
11860 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11862 /* We can't combine into a call pattern. Remember, though, that
11863 the return value register is set at this LUID. We could
11864 still replace a register with the return value from the
11865 wrong subroutine call! */
11866 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11869 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11872 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11873 register present in the SUBREG, so for each such SUBREG go back and
11874 adjust nonzero and sign bit information of the registers that are
11875 known to have some zero/sign bits set.
11877 This is needed because when combine blows the SUBREGs away, the
11878 information on zero/sign bits is lost and further combines can be
11879 missed because of that. */
11882 record_promoted_value (rtx insn, rtx subreg)
11885 unsigned int regno = REGNO (SUBREG_REG (subreg));
11886 enum machine_mode mode = GET_MODE (subreg);
11888 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11891 for (links = LOG_LINKS (insn); links;)
11893 reg_stat_type *rsp;
11895 insn = XEXP (links, 0);
11896 set = single_set (insn);
11898 if (! set || !REG_P (SET_DEST (set))
11899 || REGNO (SET_DEST (set)) != regno
11900 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11902 links = XEXP (links, 1);
11906 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11907 if (rsp->last_set == insn)
11909 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11910 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11913 if (REG_P (SET_SRC (set)))
11915 regno = REGNO (SET_SRC (set));
11916 links = LOG_LINKS (insn);
11923 /* Check if X, a register, is known to contain a value already
11924 truncated to MODE. In this case we can use a subreg to refer to
11925 the truncated value even though in the generic case we would need
11926 an explicit truncation. */
11929 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11931 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11932 enum machine_mode truncated = rsp->truncated_to_mode;
11935 || rsp->truncation_label < label_tick_ebb_start)
11937 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11939 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11940 GET_MODE_BITSIZE (truncated)))
11945 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11946 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11947 might be able to turn a truncate into a subreg using this information.
11948 Return -1 if traversing *P is complete or 0 otherwise. */
11951 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11954 enum machine_mode truncated_mode;
11955 reg_stat_type *rsp;
11957 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11959 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11960 truncated_mode = GET_MODE (x);
11962 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11965 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11966 GET_MODE_BITSIZE (original_mode)))
11969 x = SUBREG_REG (x);
11971 /* ??? For hard-regs we now record everything. We might be able to
11972 optimize this using last_set_mode. */
11973 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11974 truncated_mode = GET_MODE (x);
11978 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11979 if (rsp->truncated_to_mode == 0
11980 || rsp->truncation_label < label_tick_ebb_start
11981 || (GET_MODE_SIZE (truncated_mode)
11982 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11984 rsp->truncated_to_mode = truncated_mode;
11985 rsp->truncation_label = label_tick;
11991 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11992 the modes they are used in. This can help truning TRUNCATEs into
11996 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11998 for_each_rtx (x, record_truncated_value, NULL);
12001 /* Scan X for promoted SUBREGs. For each one found,
12002 note what it implies to the registers used in it. */
12005 check_promoted_subreg (rtx insn, rtx x)
12007 if (GET_CODE (x) == SUBREG
12008 && SUBREG_PROMOTED_VAR_P (x)
12009 && REG_P (SUBREG_REG (x)))
12010 record_promoted_value (insn, x);
12013 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12016 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12020 check_promoted_subreg (insn, XEXP (x, i));
12024 if (XVEC (x, i) != 0)
12025 for (j = 0; j < XVECLEN (x, i); j++)
12026 check_promoted_subreg (insn, XVECEXP (x, i, j));
12032 /* Verify that all the registers and memory references mentioned in *LOC are
12033 still valid. *LOC was part of a value set in INSN when label_tick was
12034 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12035 the invalid references with (clobber (const_int 0)) and return 1. This
12036 replacement is useful because we often can get useful information about
12037 the form of a value (e.g., if it was produced by a shift that always
12038 produces -1 or 0) even though we don't know exactly what registers it
12039 was produced from. */
12042 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12045 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12046 int len = GET_RTX_LENGTH (GET_CODE (x));
12051 unsigned int regno = REGNO (x);
12052 unsigned int endregno = END_REGNO (x);
12055 for (j = regno; j < endregno; j++)
12057 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12058 if (rsp->last_set_invalid
12059 /* If this is a pseudo-register that was only set once and not
12060 live at the beginning of the function, it is always valid. */
12061 || (! (regno >= FIRST_PSEUDO_REGISTER
12062 && REG_N_SETS (regno) == 1
12063 && (!REGNO_REG_SET_P
12064 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12065 && rsp->last_set_label > tick))
12068 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12075 /* If this is a memory reference, make sure that there were no stores after
12076 it that might have clobbered the value. We don't have alias info, so we
12077 assume any store invalidates it. Moreover, we only have local UIDs, so
12078 we also assume that there were stores in the intervening basic blocks. */
12079 else if (MEM_P (x) && !MEM_READONLY_P (x)
12080 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12083 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12087 for (i = 0; i < len; i++)
12091 /* Check for identical subexpressions. If x contains
12092 identical subexpression we only have to traverse one of
12094 if (i == 1 && ARITHMETIC_P (x))
12096 /* Note that at this point x0 has already been checked
12097 and found valid. */
12098 rtx x0 = XEXP (x, 0);
12099 rtx x1 = XEXP (x, 1);
12101 /* If x0 and x1 are identical then x is also valid. */
12105 /* If x1 is identical to a subexpression of x0 then
12106 while checking x0, x1 has already been checked. Thus
12107 it is valid and so as x. */
12108 if (ARITHMETIC_P (x0)
12109 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12112 /* If x0 is identical to a subexpression of x1 then x is
12113 valid iff the rest of x1 is valid. */
12114 if (ARITHMETIC_P (x1)
12115 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12117 get_last_value_validate (&XEXP (x1,
12118 x0 == XEXP (x1, 0) ? 1 : 0),
12119 insn, tick, replace);
12122 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12126 else if (fmt[i] == 'E')
12127 for (j = 0; j < XVECLEN (x, i); j++)
12128 if (get_last_value_validate (&XVECEXP (x, i, j),
12129 insn, tick, replace) == 0)
12133 /* If we haven't found a reason for it to be invalid, it is valid. */
12137 /* Get the last value assigned to X, if known. Some registers
12138 in the value may be replaced with (clobber (const_int 0)) if their value
12139 is known longer known reliably. */
12142 get_last_value (const_rtx x)
12144 unsigned int regno;
12146 reg_stat_type *rsp;
12148 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12149 then convert it to the desired mode. If this is a paradoxical SUBREG,
12150 we cannot predict what values the "extra" bits might have. */
12151 if (GET_CODE (x) == SUBREG
12152 && subreg_lowpart_p (x)
12153 && (GET_MODE_SIZE (GET_MODE (x))
12154 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12155 && (value = get_last_value (SUBREG_REG (x))) != 0)
12156 return gen_lowpart (GET_MODE (x), value);
12162 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12163 value = rsp->last_set_value;
12165 /* If we don't have a value, or if it isn't for this basic block and
12166 it's either a hard register, set more than once, or it's a live
12167 at the beginning of the function, return 0.
12169 Because if it's not live at the beginning of the function then the reg
12170 is always set before being used (is never used without being set).
12171 And, if it's set only once, and it's always set before use, then all
12172 uses must have the same last value, even if it's not from this basic
12176 || (rsp->last_set_label < label_tick_ebb_start
12177 && (regno < FIRST_PSEUDO_REGISTER
12178 || REG_N_SETS (regno) != 1
12180 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12183 /* If the value was set in a later insn than the ones we are processing,
12184 we can't use it even if the register was only set once. */
12185 if (rsp->last_set_label == label_tick
12186 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12189 /* If the value has all its registers valid, return it. */
12190 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12193 /* Otherwise, make a copy and replace any invalid register with
12194 (clobber (const_int 0)). If that fails for some reason, return 0. */
12196 value = copy_rtx (value);
12197 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12203 /* Return nonzero if expression X refers to a REG or to memory
12204 that is set in an instruction more recent than FROM_LUID. */
12207 use_crosses_set_p (const_rtx x, int from_luid)
12211 enum rtx_code code = GET_CODE (x);
12215 unsigned int regno = REGNO (x);
12216 unsigned endreg = END_REGNO (x);
12218 #ifdef PUSH_ROUNDING
12219 /* Don't allow uses of the stack pointer to be moved,
12220 because we don't know whether the move crosses a push insn. */
12221 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12224 for (; regno < endreg; regno++)
12226 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12228 && rsp->last_set_label == label_tick
12229 && DF_INSN_LUID (rsp->last_set) > from_luid)
12235 if (code == MEM && mem_last_set > from_luid)
12238 fmt = GET_RTX_FORMAT (code);
12240 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12245 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12246 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12249 else if (fmt[i] == 'e'
12250 && use_crosses_set_p (XEXP (x, i), from_luid))
12256 /* Define three variables used for communication between the following
12259 static unsigned int reg_dead_regno, reg_dead_endregno;
12260 static int reg_dead_flag;
12262 /* Function called via note_stores from reg_dead_at_p.
12264 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12265 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12268 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12270 unsigned int regno, endregno;
12275 regno = REGNO (dest);
12276 endregno = END_REGNO (dest);
12277 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12278 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12281 /* Return nonzero if REG is known to be dead at INSN.
12283 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12284 referencing REG, it is dead. If we hit a SET referencing REG, it is
12285 live. Otherwise, see if it is live or dead at the start of the basic
12286 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12287 must be assumed to be always live. */
12290 reg_dead_at_p (rtx reg, rtx insn)
12295 /* Set variables for reg_dead_at_p_1. */
12296 reg_dead_regno = REGNO (reg);
12297 reg_dead_endregno = END_REGNO (reg);
12301 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12302 we allow the machine description to decide whether use-and-clobber
12303 patterns are OK. */
12304 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12306 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12307 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12311 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12312 beginning of basic block. */
12313 block = BLOCK_FOR_INSN (insn);
12318 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12320 return reg_dead_flag == 1 ? 1 : 0;
12322 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12326 if (insn == BB_HEAD (block))
12329 insn = PREV_INSN (insn);
12332 /* Look at live-in sets for the basic block that we were in. */
12333 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12334 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12340 /* Note hard registers in X that are used. */
12343 mark_used_regs_combine (rtx x)
12345 RTX_CODE code = GET_CODE (x);
12346 unsigned int regno;
12359 case ADDR_DIFF_VEC:
12362 /* CC0 must die in the insn after it is set, so we don't need to take
12363 special note of it here. */
12369 /* If we are clobbering a MEM, mark any hard registers inside the
12370 address as used. */
12371 if (MEM_P (XEXP (x, 0)))
12372 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12377 /* A hard reg in a wide mode may really be multiple registers.
12378 If so, mark all of them just like the first. */
12379 if (regno < FIRST_PSEUDO_REGISTER)
12381 /* None of this applies to the stack, frame or arg pointers. */
12382 if (regno == STACK_POINTER_REGNUM
12383 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12384 || regno == HARD_FRAME_POINTER_REGNUM
12386 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12387 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12389 || regno == FRAME_POINTER_REGNUM)
12392 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12398 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12400 rtx testreg = SET_DEST (x);
12402 while (GET_CODE (testreg) == SUBREG
12403 || GET_CODE (testreg) == ZERO_EXTRACT
12404 || GET_CODE (testreg) == STRICT_LOW_PART)
12405 testreg = XEXP (testreg, 0);
12407 if (MEM_P (testreg))
12408 mark_used_regs_combine (XEXP (testreg, 0));
12410 mark_used_regs_combine (SET_SRC (x));
12418 /* Recursively scan the operands of this expression. */
12421 const char *fmt = GET_RTX_FORMAT (code);
12423 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12426 mark_used_regs_combine (XEXP (x, i));
12427 else if (fmt[i] == 'E')
12431 for (j = 0; j < XVECLEN (x, i); j++)
12432 mark_used_regs_combine (XVECEXP (x, i, j));
12438 /* Remove register number REGNO from the dead registers list of INSN.
12440 Return the note used to record the death, if there was one. */
12443 remove_death (unsigned int regno, rtx insn)
12445 rtx note = find_regno_note (insn, REG_DEAD, regno);
12448 remove_note (insn, note);
12453 /* For each register (hardware or pseudo) used within expression X, if its
12454 death is in an instruction with luid between FROM_LUID (inclusive) and
12455 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12456 list headed by PNOTES.
12458 That said, don't move registers killed by maybe_kill_insn.
12460 This is done when X is being merged by combination into TO_INSN. These
12461 notes will then be distributed as needed. */
12464 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12469 enum rtx_code code = GET_CODE (x);
12473 unsigned int regno = REGNO (x);
12474 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12476 /* Don't move the register if it gets killed in between from and to. */
12477 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12478 && ! reg_referenced_p (x, maybe_kill_insn))
12482 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12483 && DF_INSN_LUID (where_dead) >= from_luid
12484 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12486 rtx note = remove_death (regno, where_dead);
12488 /* It is possible for the call above to return 0. This can occur
12489 when last_death points to I2 or I1 that we combined with.
12490 In that case make a new note.
12492 We must also check for the case where X is a hard register
12493 and NOTE is a death note for a range of hard registers
12494 including X. In that case, we must put REG_DEAD notes for
12495 the remaining registers in place of NOTE. */
12497 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12498 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12499 > GET_MODE_SIZE (GET_MODE (x))))
12501 unsigned int deadregno = REGNO (XEXP (note, 0));
12502 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12503 unsigned int ourend = END_HARD_REGNO (x);
12506 for (i = deadregno; i < deadend; i++)
12507 if (i < regno || i >= ourend)
12508 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12511 /* If we didn't find any note, or if we found a REG_DEAD note that
12512 covers only part of the given reg, and we have a multi-reg hard
12513 register, then to be safe we must check for REG_DEAD notes
12514 for each register other than the first. They could have
12515 their own REG_DEAD notes lying around. */
12516 else if ((note == 0
12518 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12519 < GET_MODE_SIZE (GET_MODE (x)))))
12520 && regno < FIRST_PSEUDO_REGISTER
12521 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12523 unsigned int ourend = END_HARD_REGNO (x);
12524 unsigned int i, offset;
12528 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12532 for (i = regno + offset; i < ourend; i++)
12533 move_deaths (regno_reg_rtx[i],
12534 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12537 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12539 XEXP (note, 1) = *pnotes;
12543 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12549 else if (GET_CODE (x) == SET)
12551 rtx dest = SET_DEST (x);
12553 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12555 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12556 that accesses one word of a multi-word item, some
12557 piece of everything register in the expression is used by
12558 this insn, so remove any old death. */
12559 /* ??? So why do we test for equality of the sizes? */
12561 if (GET_CODE (dest) == ZERO_EXTRACT
12562 || GET_CODE (dest) == STRICT_LOW_PART
12563 || (GET_CODE (dest) == SUBREG
12564 && (((GET_MODE_SIZE (GET_MODE (dest))
12565 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12566 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12567 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12569 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12573 /* If this is some other SUBREG, we know it replaces the entire
12574 value, so use that as the destination. */
12575 if (GET_CODE (dest) == SUBREG)
12576 dest = SUBREG_REG (dest);
12578 /* If this is a MEM, adjust deaths of anything used in the address.
12579 For a REG (the only other possibility), the entire value is
12580 being replaced so the old value is not used in this insn. */
12583 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12588 else if (GET_CODE (x) == CLOBBER)
12591 len = GET_RTX_LENGTH (code);
12592 fmt = GET_RTX_FORMAT (code);
12594 for (i = 0; i < len; i++)
12599 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12600 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12603 else if (fmt[i] == 'e')
12604 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12608 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12609 pattern of an insn. X must be a REG. */
12612 reg_bitfield_target_p (rtx x, rtx body)
12616 if (GET_CODE (body) == SET)
12618 rtx dest = SET_DEST (body);
12620 unsigned int regno, tregno, endregno, endtregno;
12622 if (GET_CODE (dest) == ZERO_EXTRACT)
12623 target = XEXP (dest, 0);
12624 else if (GET_CODE (dest) == STRICT_LOW_PART)
12625 target = SUBREG_REG (XEXP (dest, 0));
12629 if (GET_CODE (target) == SUBREG)
12630 target = SUBREG_REG (target);
12632 if (!REG_P (target))
12635 tregno = REGNO (target), regno = REGNO (x);
12636 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12637 return target == x;
12639 endtregno = end_hard_regno (GET_MODE (target), tregno);
12640 endregno = end_hard_regno (GET_MODE (x), regno);
12642 return endregno > tregno && regno < endtregno;
12645 else if (GET_CODE (body) == PARALLEL)
12646 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12647 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12653 /* Return the next insn after INSN that is neither a NOTE nor a
12654 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12657 next_nonnote_nondebug_insn (rtx insn)
12661 insn = NEXT_INSN (insn);
12666 if (DEBUG_INSN_P (insn))
12676 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12677 as appropriate. I3 and I2 are the insns resulting from the combination
12678 insns including FROM (I2 may be zero).
12680 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12681 not need REG_DEAD notes because they are being substituted for. This
12682 saves searching in the most common cases.
12684 Each note in the list is either ignored or placed on some insns, depending
12685 on the type of note. */
12688 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12691 rtx note, next_note;
12694 for (note = notes; note; note = next_note)
12696 rtx place = 0, place2 = 0;
12698 next_note = XEXP (note, 1);
12699 switch (REG_NOTE_KIND (note))
12703 /* Doesn't matter much where we put this, as long as it's somewhere.
12704 It is preferable to keep these notes on branches, which is most
12705 likely to be i3. */
12709 case REG_VALUE_PROFILE:
12710 /* Just get rid of this note, as it is unused later anyway. */
12713 case REG_NON_LOCAL_GOTO:
12718 gcc_assert (i2 && JUMP_P (i2));
12723 case REG_EH_REGION:
12724 /* These notes must remain with the call or trapping instruction. */
12727 else if (i2 && CALL_P (i2))
12731 gcc_assert (flag_non_call_exceptions);
12732 if (may_trap_p (i3))
12734 else if (i2 && may_trap_p (i2))
12736 /* ??? Otherwise assume we've combined things such that we
12737 can now prove that the instructions can't trap. Drop the
12738 note in this case. */
12744 /* These notes must remain with the call. It should not be
12745 possible for both I2 and I3 to be a call. */
12750 gcc_assert (i2 && CALL_P (i2));
12756 /* Any clobbers for i3 may still exist, and so we must process
12757 REG_UNUSED notes from that insn.
12759 Any clobbers from i2 or i1 can only exist if they were added by
12760 recog_for_combine. In that case, recog_for_combine created the
12761 necessary REG_UNUSED notes. Trying to keep any original
12762 REG_UNUSED notes from these insns can cause incorrect output
12763 if it is for the same register as the original i3 dest.
12764 In that case, we will notice that the register is set in i3,
12765 and then add a REG_UNUSED note for the destination of i3, which
12766 is wrong. However, it is possible to have REG_UNUSED notes from
12767 i2 or i1 for register which were both used and clobbered, so
12768 we keep notes from i2 or i1 if they will turn into REG_DEAD
12771 /* If this register is set or clobbered in I3, put the note there
12772 unless there is one already. */
12773 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12775 if (from_insn != i3)
12778 if (! (REG_P (XEXP (note, 0))
12779 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12780 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12783 /* Otherwise, if this register is used by I3, then this register
12784 now dies here, so we must put a REG_DEAD note here unless there
12786 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12787 && ! (REG_P (XEXP (note, 0))
12788 ? find_regno_note (i3, REG_DEAD,
12789 REGNO (XEXP (note, 0)))
12790 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12792 PUT_REG_NOTE_KIND (note, REG_DEAD);
12800 /* These notes say something about results of an insn. We can
12801 only support them if they used to be on I3 in which case they
12802 remain on I3. Otherwise they are ignored.
12804 If the note refers to an expression that is not a constant, we
12805 must also ignore the note since we cannot tell whether the
12806 equivalence is still true. It might be possible to do
12807 slightly better than this (we only have a problem if I2DEST
12808 or I1DEST is present in the expression), but it doesn't
12809 seem worth the trouble. */
12811 if (from_insn == i3
12812 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12817 /* These notes say something about how a register is used. They must
12818 be present on any use of the register in I2 or I3. */
12819 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12822 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12831 case REG_LABEL_TARGET:
12832 case REG_LABEL_OPERAND:
12833 /* This can show up in several ways -- either directly in the
12834 pattern, or hidden off in the constant pool with (or without?)
12835 a REG_EQUAL note. */
12836 /* ??? Ignore the without-reg_equal-note problem for now. */
12837 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12838 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12839 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12840 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12844 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12845 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12846 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12847 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12855 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12856 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12858 if (place && JUMP_P (place)
12859 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12860 && (JUMP_LABEL (place) == NULL
12861 || JUMP_LABEL (place) == XEXP (note, 0)))
12863 rtx label = JUMP_LABEL (place);
12866 JUMP_LABEL (place) = XEXP (note, 0);
12867 else if (LABEL_P (label))
12868 LABEL_NUSES (label)--;
12871 if (place2 && JUMP_P (place2)
12872 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12873 && (JUMP_LABEL (place2) == NULL
12874 || JUMP_LABEL (place2) == XEXP (note, 0)))
12876 rtx label = JUMP_LABEL (place2);
12879 JUMP_LABEL (place2) = XEXP (note, 0);
12880 else if (LABEL_P (label))
12881 LABEL_NUSES (label)--;
12887 /* This note says something about the value of a register prior
12888 to the execution of an insn. It is too much trouble to see
12889 if the note is still correct in all situations. It is better
12890 to simply delete it. */
12894 /* If we replaced the right hand side of FROM_INSN with a
12895 REG_EQUAL note, the original use of the dying register
12896 will not have been combined into I3 and I2. In such cases,
12897 FROM_INSN is guaranteed to be the first of the combined
12898 instructions, so we simply need to search back before
12899 FROM_INSN for the previous use or set of this register,
12900 then alter the notes there appropriately.
12902 If the register is used as an input in I3, it dies there.
12903 Similarly for I2, if it is nonzero and adjacent to I3.
12905 If the register is not used as an input in either I3 or I2
12906 and it is not one of the registers we were supposed to eliminate,
12907 there are two possibilities. We might have a non-adjacent I2
12908 or we might have somehow eliminated an additional register
12909 from a computation. For example, we might have had A & B where
12910 we discover that B will always be zero. In this case we will
12911 eliminate the reference to A.
12913 In both cases, we must search to see if we can find a previous
12914 use of A and put the death note there. */
12917 && from_insn == i2mod
12918 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12923 && CALL_P (from_insn)
12924 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12926 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12928 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12929 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12931 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12933 && reg_overlap_mentioned_p (XEXP (note, 0),
12935 || rtx_equal_p (XEXP (note, 0), elim_i1))
12942 basic_block bb = this_basic_block;
12944 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12946 if (!NONDEBUG_INSN_P (tem))
12948 if (tem == BB_HEAD (bb))
12953 /* If the register is being set at TEM, see if that is all
12954 TEM is doing. If so, delete TEM. Otherwise, make this
12955 into a REG_UNUSED note instead. Don't delete sets to
12956 global register vars. */
12957 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12958 || !global_regs[REGNO (XEXP (note, 0))])
12959 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12961 rtx set = single_set (tem);
12962 rtx inner_dest = 0;
12964 rtx cc0_setter = NULL_RTX;
12968 for (inner_dest = SET_DEST (set);
12969 (GET_CODE (inner_dest) == STRICT_LOW_PART
12970 || GET_CODE (inner_dest) == SUBREG
12971 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12972 inner_dest = XEXP (inner_dest, 0))
12975 /* Verify that it was the set, and not a clobber that
12976 modified the register.
12978 CC0 targets must be careful to maintain setter/user
12979 pairs. If we cannot delete the setter due to side
12980 effects, mark the user with an UNUSED note instead
12983 if (set != 0 && ! side_effects_p (SET_SRC (set))
12984 && rtx_equal_p (XEXP (note, 0), inner_dest)
12986 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12987 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12988 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12992 /* Move the notes and links of TEM elsewhere.
12993 This might delete other dead insns recursively.
12994 First set the pattern to something that won't use
12996 rtx old_notes = REG_NOTES (tem);
12998 PATTERN (tem) = pc_rtx;
12999 REG_NOTES (tem) = NULL;
13001 distribute_notes (old_notes, tem, tem, NULL_RTX,
13002 NULL_RTX, NULL_RTX);
13003 distribute_links (LOG_LINKS (tem));
13005 SET_INSN_DELETED (tem);
13010 /* Delete the setter too. */
13013 PATTERN (cc0_setter) = pc_rtx;
13014 old_notes = REG_NOTES (cc0_setter);
13015 REG_NOTES (cc0_setter) = NULL;
13017 distribute_notes (old_notes, cc0_setter,
13018 cc0_setter, NULL_RTX,
13019 NULL_RTX, NULL_RTX);
13020 distribute_links (LOG_LINKS (cc0_setter));
13022 SET_INSN_DELETED (cc0_setter);
13023 if (cc0_setter == i2)
13030 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13032 /* If there isn't already a REG_UNUSED note, put one
13033 here. Do not place a REG_DEAD note, even if
13034 the register is also used here; that would not
13035 match the algorithm used in lifetime analysis
13036 and can cause the consistency check in the
13037 scheduler to fail. */
13038 if (! find_regno_note (tem, REG_UNUSED,
13039 REGNO (XEXP (note, 0))))
13044 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13046 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13050 /* If we are doing a 3->2 combination, and we have a
13051 register which formerly died in i3 and was not used
13052 by i2, which now no longer dies in i3 and is used in
13053 i2 but does not die in i2, and place is between i2
13054 and i3, then we may need to move a link from place to
13056 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13058 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13059 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13061 rtx links = LOG_LINKS (place);
13062 LOG_LINKS (place) = 0;
13063 distribute_links (links);
13068 if (tem == BB_HEAD (bb))
13074 /* If the register is set or already dead at PLACE, we needn't do
13075 anything with this note if it is still a REG_DEAD note.
13076 We check here if it is set at all, not if is it totally replaced,
13077 which is what `dead_or_set_p' checks, so also check for it being
13080 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13082 unsigned int regno = REGNO (XEXP (note, 0));
13083 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13085 if (dead_or_set_p (place, XEXP (note, 0))
13086 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13088 /* Unless the register previously died in PLACE, clear
13089 last_death. [I no longer understand why this is
13091 if (rsp->last_death != place)
13092 rsp->last_death = 0;
13096 rsp->last_death = place;
13098 /* If this is a death note for a hard reg that is occupying
13099 multiple registers, ensure that we are still using all
13100 parts of the object. If we find a piece of the object
13101 that is unused, we must arrange for an appropriate REG_DEAD
13102 note to be added for it. However, we can't just emit a USE
13103 and tag the note to it, since the register might actually
13104 be dead; so we recourse, and the recursive call then finds
13105 the previous insn that used this register. */
13107 if (place && regno < FIRST_PSEUDO_REGISTER
13108 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13110 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13114 for (i = regno; i < endregno; i++)
13115 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13116 && ! find_regno_fusage (place, USE, i))
13117 || dead_or_set_regno_p (place, i))
13122 /* Put only REG_DEAD notes for pieces that are
13123 not already dead or set. */
13125 for (i = regno; i < endregno;
13126 i += hard_regno_nregs[i][reg_raw_mode[i]])
13128 rtx piece = regno_reg_rtx[i];
13129 basic_block bb = this_basic_block;
13131 if (! dead_or_set_p (place, piece)
13132 && ! reg_bitfield_target_p (piece,
13135 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13138 distribute_notes (new_note, place, place,
13139 NULL_RTX, NULL_RTX, NULL_RTX);
13141 else if (! refers_to_regno_p (i, i + 1,
13142 PATTERN (place), 0)
13143 && ! find_regno_fusage (place, USE, i))
13144 for (tem = PREV_INSN (place); ;
13145 tem = PREV_INSN (tem))
13147 if (!NONDEBUG_INSN_P (tem))
13149 if (tem == BB_HEAD (bb))
13153 if (dead_or_set_p (tem, piece)
13154 || reg_bitfield_target_p (piece,
13157 add_reg_note (tem, REG_UNUSED, piece);
13171 /* Any other notes should not be present at this point in the
13173 gcc_unreachable ();
13178 XEXP (note, 1) = REG_NOTES (place);
13179 REG_NOTES (place) = note;
13183 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13187 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13188 I3, I2, and I1 to new locations. This is also called to add a link
13189 pointing at I3 when I3's destination is changed. */
13192 distribute_links (rtx links)
13194 rtx link, next_link;
13196 for (link = links; link; link = next_link)
13202 next_link = XEXP (link, 1);
13204 /* If the insn that this link points to is a NOTE or isn't a single
13205 set, ignore it. In the latter case, it isn't clear what we
13206 can do other than ignore the link, since we can't tell which
13207 register it was for. Such links wouldn't be used by combine
13210 It is not possible for the destination of the target of the link to
13211 have been changed by combine. The only potential of this is if we
13212 replace I3, I2, and I1 by I3 and I2. But in that case the
13213 destination of I2 also remains unchanged. */
13215 if (NOTE_P (XEXP (link, 0))
13216 || (set = single_set (XEXP (link, 0))) == 0)
13219 reg = SET_DEST (set);
13220 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13221 || GET_CODE (reg) == STRICT_LOW_PART)
13222 reg = XEXP (reg, 0);
13224 /* A LOG_LINK is defined as being placed on the first insn that uses
13225 a register and points to the insn that sets the register. Start
13226 searching at the next insn after the target of the link and stop
13227 when we reach a set of the register or the end of the basic block.
13229 Note that this correctly handles the link that used to point from
13230 I3 to I2. Also note that not much searching is typically done here
13231 since most links don't point very far away. */
13233 for (insn = NEXT_INSN (XEXP (link, 0));
13234 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13235 || BB_HEAD (this_basic_block->next_bb) != insn));
13236 insn = NEXT_INSN (insn))
13237 if (DEBUG_INSN_P (insn))
13239 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13241 if (reg_referenced_p (reg, PATTERN (insn)))
13245 else if (CALL_P (insn)
13246 && find_reg_fusage (insn, USE, reg))
13251 else if (INSN_P (insn) && reg_set_p (reg, insn))
13254 /* If we found a place to put the link, place it there unless there
13255 is already a link to the same insn as LINK at that point. */
13261 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13262 if (XEXP (link2, 0) == XEXP (link, 0))
13267 XEXP (link, 1) = LOG_LINKS (place);
13268 LOG_LINKS (place) = link;
13270 /* Set added_links_insn to the earliest insn we added a
13272 if (added_links_insn == 0
13273 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13274 added_links_insn = place;
13280 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13281 Check whether the expression pointer to by LOC is a register or
13282 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13283 Otherwise return zero. */
13286 unmentioned_reg_p_1 (rtx *loc, void *expr)
13291 && (REG_P (x) || MEM_P (x))
13292 && ! reg_mentioned_p (x, (rtx) expr))
13297 /* Check for any register or memory mentioned in EQUIV that is not
13298 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13299 of EXPR where some registers may have been replaced by constants. */
13302 unmentioned_reg_p (rtx equiv, rtx expr)
13304 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13308 dump_combine_stats (FILE *file)
13312 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13313 combine_attempts, combine_merges, combine_extras, combine_successes);
13317 dump_combine_total_stats (FILE *file)
13321 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13322 total_attempts, total_merges, total_extras, total_successes);
13326 gate_handle_combine (void)
13328 return (optimize > 0);
13331 /* Try combining insns through substitution. */
13332 static unsigned int
13333 rest_of_handle_combine (void)
13335 int rebuild_jump_labels_after_combine;
13337 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13338 df_note_add_problem ();
13341 regstat_init_n_sets_and_refs ();
13343 rebuild_jump_labels_after_combine
13344 = combine_instructions (get_insns (), max_reg_num ());
13346 /* Combining insns may have turned an indirect jump into a
13347 direct jump. Rebuild the JUMP_LABEL fields of jumping
13349 if (rebuild_jump_labels_after_combine)
13351 timevar_push (TV_JUMP);
13352 rebuild_jump_labels (get_insns ());
13354 timevar_pop (TV_JUMP);
13357 regstat_free_n_sets_and_refs ();
13361 struct rtl_opt_pass pass_combine =
13365 "combine", /* name */
13366 gate_handle_combine, /* gate */
13367 rest_of_handle_combine, /* execute */
13370 0, /* static_pass_number */
13371 TV_COMBINE, /* tv_id */
13372 PROP_cfglayout, /* properties_required */
13373 0, /* properties_provided */
13374 0, /* properties_destroyed */
13375 0, /* todo_flags_start */
13377 TODO_df_finish | TODO_verify_rtl_sharing |
13378 TODO_ggc_collect, /* todo_flags_finish */
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