1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
93 #include "stor-layout.h"
95 #include "cfgcleanup.h"
96 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
98 #include "insn-attr.h"
99 #include "rtlhooks-def.h"
101 #include "tree-pass.h"
102 #include "valtrack.h"
103 #include "rtl-iter.h"
104 #include "print-rtl.h"
106 #ifndef LOAD_EXTEND_OP
107 #define LOAD_EXTEND_OP(M) UNKNOWN
110 /* Number of attempts to combine instructions in this function. */
112 static int combine_attempts;
114 /* Number of attempts that got as far as substitution in this function. */
116 static int combine_merges;
118 /* Number of instructions combined with added SETs in this function. */
120 static int combine_extras;
122 /* Number of instructions combined in this function. */
124 static int combine_successes;
126 /* Totals over entire compilation. */
128 static int total_attempts, total_merges, total_extras, total_successes;
130 /* combine_instructions may try to replace the right hand side of the
131 second instruction with the value of an associated REG_EQUAL note
132 before throwing it at try_combine. That is problematic when there
133 is a REG_DEAD note for a register used in the old right hand side
134 and can cause distribute_notes to do wrong things. This is the
135 second instruction if it has been so modified, null otherwise. */
137 static rtx_insn *i2mod;
139 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 static rtx i2mod_old_rhs;
143 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
145 static rtx i2mod_new_rhs;
147 struct reg_stat_type {
148 /* Record last point of death of (hard or pseudo) register n. */
149 rtx_insn *last_death;
151 /* Record last point of modification of (hard or pseudo) register n. */
154 /* The next group of fields allows the recording of the last value assigned
155 to (hard or pseudo) register n. We use this information to see if an
156 operation being processed is redundant given a prior operation performed
157 on the register. For example, an `and' with a constant is redundant if
158 all the zero bits are already known to be turned off.
160 We use an approach similar to that used by cse, but change it in the
163 (1) We do not want to reinitialize at each label.
164 (2) It is useful, but not critical, to know the actual value assigned
165 to a register. Often just its form is helpful.
167 Therefore, we maintain the following fields:
169 last_set_value the last value assigned
170 last_set_label records the value of label_tick when the
171 register was assigned
172 last_set_table_tick records the value of label_tick when a
173 value using the register is assigned
174 last_set_invalid set to nonzero when it is not valid
175 to use the value of this register in some
178 To understand the usage of these tables, it is important to understand
179 the distinction between the value in last_set_value being valid and
180 the register being validly contained in some other expression in the
183 (The next two parameters are out of date).
185 reg_stat[i].last_set_value is valid if it is nonzero, and either
186 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
188 Register I may validly appear in any expression returned for the value
189 of another register if reg_n_sets[i] is 1. It may also appear in the
190 value for register J if reg_stat[j].last_set_invalid is zero, or
191 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
193 If an expression is found in the table containing a register which may
194 not validly appear in an expression, the register is replaced by
195 something that won't match, (clobber (const_int 0)). */
197 /* Record last value assigned to (hard or pseudo) register n. */
201 /* Record the value of label_tick when an expression involving register n
202 is placed in last_set_value. */
204 int last_set_table_tick;
206 /* Record the value of label_tick when the value for register n is placed in
211 /* These fields are maintained in parallel with last_set_value and are
212 used to store the mode in which the register was last set, the bits
213 that were known to be zero when it was last set, and the number of
214 sign bits copies it was known to have when it was last set. */
216 unsigned HOST_WIDE_INT last_set_nonzero_bits;
217 char last_set_sign_bit_copies;
218 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
220 /* Set nonzero if references to register n in expressions should not be
221 used. last_set_invalid is set nonzero when this register is being
222 assigned to and last_set_table_tick == label_tick. */
224 char last_set_invalid;
226 /* Some registers that are set more than once and used in more than one
227 basic block are nevertheless always set in similar ways. For example,
228 a QImode register may be loaded from memory in two places on a machine
229 where byte loads zero extend.
231 We record in the following fields if a register has some leading bits
232 that are always equal to the sign bit, and what we know about the
233 nonzero bits of a register, specifically which bits are known to be
236 If an entry is zero, it means that we don't know anything special. */
238 unsigned char sign_bit_copies;
240 unsigned HOST_WIDE_INT nonzero_bits;
242 /* Record the value of the label_tick when the last truncation
243 happened. The field truncated_to_mode is only valid if
244 truncation_label == label_tick. */
246 int truncation_label;
248 /* Record the last truncation seen for this register. If truncation
249 is not a nop to this mode we might be able to save an explicit
250 truncation if we know that value already contains a truncated
253 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
257 static vec<reg_stat_type> reg_stat;
259 /* One plus the highest pseudo for which we track REG_N_SETS.
260 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
261 but during combine_split_insns new pseudos can be created. As we don't have
262 updated DF information in that case, it is hard to initialize the array
263 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
264 so instead of growing the arrays, just assume all newly created pseudos
265 during combine might be set multiple times. */
267 static unsigned int reg_n_sets_max;
269 /* Record the luid of the last insn that invalidated memory
270 (anything that writes memory, and subroutine calls, but not pushes). */
272 static int mem_last_set;
274 /* Record the luid of the last CALL_INSN
275 so we can tell whether a potential combination crosses any calls. */
277 static int last_call_luid;
279 /* When `subst' is called, this is the insn that is being modified
280 (by combining in a previous insn). The PATTERN of this insn
281 is still the old pattern partially modified and it should not be
282 looked at, but this may be used to examine the successors of the insn
283 to judge whether a simplification is valid. */
285 static rtx_insn *subst_insn;
287 /* This is the lowest LUID that `subst' is currently dealing with.
288 get_last_value will not return a value if the register was set at or
289 after this LUID. If not for this mechanism, we could get confused if
290 I2 or I1 in try_combine were an insn that used the old value of a register
291 to obtain a new value. In that case, we might erroneously get the
292 new value of the register when we wanted the old one. */
294 static int subst_low_luid;
296 /* This contains any hard registers that are used in newpat; reg_dead_at_p
297 must consider all these registers to be always live. */
299 static HARD_REG_SET newpat_used_regs;
301 /* This is an insn to which a LOG_LINKS entry has been added. If this
302 insn is the earlier than I2 or I3, combine should rescan starting at
305 static rtx_insn *added_links_insn;
307 /* Basic block in which we are performing combines. */
308 static basic_block this_basic_block;
309 static bool optimize_this_for_speed_p;
312 /* Length of the currently allocated uid_insn_cost array. */
314 static int max_uid_known;
316 /* The following array records the insn_rtx_cost for every insn
317 in the instruction stream. */
319 static int *uid_insn_cost;
321 /* The following array records the LOG_LINKS for every insn in the
322 instruction stream as struct insn_link pointers. */
327 struct insn_link *next;
330 static struct insn_link **uid_log_links;
332 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
333 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
335 #define FOR_EACH_LOG_LINK(L, INSN) \
336 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
338 /* Links for LOG_LINKS are allocated from this obstack. */
340 static struct obstack insn_link_obstack;
342 /* Allocate a link. */
344 static inline struct insn_link *
345 alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
348 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
349 sizeof (struct insn_link));
356 /* Incremented for each basic block. */
358 static int label_tick;
360 /* Reset to label_tick for each extended basic block in scanning order. */
362 static int label_tick_ebb_start;
364 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
365 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
367 static machine_mode nonzero_bits_mode;
369 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
370 be safely used. It is zero while computing them and after combine has
371 completed. This former test prevents propagating values based on
372 previously set values, which can be incorrect if a variable is modified
375 static int nonzero_sign_valid;
378 /* Record one modification to rtl structure
379 to be undone by storing old_contents into *where. */
381 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
387 union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
388 union { rtx *r; int *i; struct insn_link **l; } where;
391 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
392 num_undo says how many are currently recorded.
394 other_insn is nonzero if we have modified some other insn in the process
395 of working on subst_insn. It must be verified too. */
401 rtx_insn *other_insn;
404 static struct undobuf undobuf;
406 /* Number of times the pseudo being substituted for
407 was found and replaced. */
409 static int n_occurrences;
411 static rtx reg_nonzero_bits_for_combine (const_rtx, machine_mode, const_rtx,
413 unsigned HOST_WIDE_INT,
414 unsigned HOST_WIDE_INT *);
415 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, machine_mode, const_rtx,
417 unsigned int, unsigned int *);
418 static void do_SUBST (rtx *, rtx);
419 static void do_SUBST_INT (int *, int);
420 static void init_reg_last (void);
421 static void setup_incoming_promotions (rtx_insn *);
422 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
423 static int cant_combine_insn_p (rtx_insn *);
424 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
425 rtx_insn *, rtx_insn *, rtx *, rtx *);
426 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *);
427 static int contains_muldiv (rtx);
428 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
430 static void undo_all (void);
431 static void undo_commit (void);
432 static rtx *find_split_point (rtx *, rtx_insn *, bool);
433 static rtx subst (rtx, rtx, rtx, int, int, int);
434 static rtx combine_simplify_rtx (rtx, machine_mode, int, int);
435 static rtx simplify_if_then_else (rtx);
436 static rtx simplify_set (rtx);
437 static rtx simplify_logical (rtx);
438 static rtx expand_compound_operation (rtx);
439 static const_rtx expand_field_assignment (const_rtx);
440 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT,
441 rtx, unsigned HOST_WIDE_INT, int, int, int);
442 static rtx extract_left_shift (rtx, int);
443 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
444 unsigned HOST_WIDE_INT *);
445 static rtx canon_reg_for_combine (rtx, rtx);
446 static rtx force_to_mode (rtx, machine_mode,
447 unsigned HOST_WIDE_INT, int);
448 static rtx if_then_else_cond (rtx, rtx *, rtx *);
449 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
450 static int rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
451 static rtx make_field_assignment (rtx);
452 static rtx apply_distributive_law (rtx);
453 static rtx distribute_and_simplify_rtx (rtx, int);
454 static rtx simplify_and_const_int_1 (machine_mode, rtx,
455 unsigned HOST_WIDE_INT);
456 static rtx simplify_and_const_int (rtx, machine_mode, rtx,
457 unsigned HOST_WIDE_INT);
458 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
459 HOST_WIDE_INT, machine_mode, int *);
460 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
461 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
463 static int recog_for_combine (rtx *, rtx_insn *, rtx *);
464 static rtx gen_lowpart_for_combine (machine_mode, rtx);
465 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
467 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
468 static void update_table_tick (rtx);
469 static void record_value_for_reg (rtx, rtx_insn *, rtx);
470 static void check_promoted_subreg (rtx_insn *, rtx);
471 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
472 static void record_dead_and_set_regs (rtx_insn *);
473 static int get_last_value_validate (rtx *, rtx_insn *, int, int);
474 static rtx get_last_value (const_rtx);
475 static int use_crosses_set_p (const_rtx, int);
476 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
477 static int reg_dead_at_p (rtx, rtx_insn *);
478 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
479 static int reg_bitfield_target_p (rtx, rtx);
480 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx);
481 static void distribute_links (struct insn_link *);
482 static void mark_used_regs_combine (rtx);
483 static void record_promoted_value (rtx_insn *, rtx);
484 static bool unmentioned_reg_p (rtx, rtx);
485 static void record_truncated_values (rtx *, void *);
486 static bool reg_truncated_to_mode (machine_mode, const_rtx);
487 static rtx gen_lowpart_or_truncate (machine_mode, rtx);
490 /* It is not safe to use ordinary gen_lowpart in combine.
491 See comments in gen_lowpart_for_combine. */
492 #undef RTL_HOOKS_GEN_LOWPART
493 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
495 /* Our implementation of gen_lowpart never emits a new pseudo. */
496 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
497 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
499 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
500 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
502 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
503 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
505 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
506 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
508 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
511 /* Convenience wrapper for the canonicalize_comparison target hook.
512 Target hooks cannot use enum rtx_code. */
514 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
515 bool op0_preserve_value)
517 int code_int = (int)*code;
518 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
519 *code = (enum rtx_code)code_int;
522 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
523 PATTERN can not be split. Otherwise, it returns an insn sequence.
524 This is a wrapper around split_insns which ensures that the
525 reg_stat vector is made larger if the splitter creates a new
529 combine_split_insns (rtx pattern, rtx_insn *insn)
534 ret = split_insns (pattern, insn);
535 nregs = max_reg_num ();
536 if (nregs > reg_stat.length ())
537 reg_stat.safe_grow_cleared (nregs);
541 /* This is used by find_single_use to locate an rtx in LOC that
542 contains exactly one use of DEST, which is typically either a REG
543 or CC0. It returns a pointer to the innermost rtx expression
544 containing DEST. Appearances of DEST that are being used to
545 totally replace it are not counted. */
548 find_single_use_1 (rtx dest, rtx *loc)
551 enum rtx_code code = GET_CODE (x);
567 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
568 of a REG that occupies all of the REG, the insn uses DEST if
569 it is mentioned in the destination or the source. Otherwise, we
570 need just check the source. */
571 if (GET_CODE (SET_DEST (x)) != CC0
572 && GET_CODE (SET_DEST (x)) != PC
573 && !REG_P (SET_DEST (x))
574 && ! (GET_CODE (SET_DEST (x)) == SUBREG
575 && REG_P (SUBREG_REG (SET_DEST (x)))
576 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
577 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
578 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
579 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
582 return find_single_use_1 (dest, &SET_SRC (x));
586 return find_single_use_1 (dest, &XEXP (x, 0));
592 /* If it wasn't one of the common cases above, check each expression and
593 vector of this code. Look for a unique usage of DEST. */
595 fmt = GET_RTX_FORMAT (code);
596 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
600 if (dest == XEXP (x, i)
601 || (REG_P (dest) && REG_P (XEXP (x, i))
602 && REGNO (dest) == REGNO (XEXP (x, i))))
605 this_result = find_single_use_1 (dest, &XEXP (x, i));
608 result = this_result;
609 else if (this_result)
610 /* Duplicate usage. */
613 else if (fmt[i] == 'E')
617 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
619 if (XVECEXP (x, i, j) == dest
621 && REG_P (XVECEXP (x, i, j))
622 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
625 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
628 result = this_result;
629 else if (this_result)
639 /* See if DEST, produced in INSN, is used only a single time in the
640 sequel. If so, return a pointer to the innermost rtx expression in which
643 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
645 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
646 care about REG_DEAD notes or LOG_LINKS.
648 Otherwise, we find the single use by finding an insn that has a
649 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
650 only referenced once in that insn, we know that it must be the first
651 and last insn referencing DEST. */
654 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
659 struct insn_link *link;
663 next = NEXT_INSN (insn);
665 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
668 result = find_single_use_1 (dest, &PATTERN (next));
677 bb = BLOCK_FOR_INSN (insn);
678 for (next = NEXT_INSN (insn);
679 next && BLOCK_FOR_INSN (next) == bb;
680 next = NEXT_INSN (next))
681 if (INSN_P (next) && dead_or_set_p (next, dest))
683 FOR_EACH_LOG_LINK (link, next)
684 if (link->insn == insn && link->regno == REGNO (dest))
689 result = find_single_use_1 (dest, &PATTERN (next));
699 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
700 insn. The substitution can be undone by undo_all. If INTO is already
701 set to NEWVAL, do not record this change. Because computing NEWVAL might
702 also call SUBST, we have to compute it before we put anything into
706 do_SUBST (rtx *into, rtx newval)
711 if (oldval == newval)
714 /* We'd like to catch as many invalid transformations here as
715 possible. Unfortunately, there are way too many mode changes
716 that are perfectly valid, so we'd waste too much effort for
717 little gain doing the checks here. Focus on catching invalid
718 transformations involving integer constants. */
719 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
720 && CONST_INT_P (newval))
722 /* Sanity check that we're replacing oldval with a CONST_INT
723 that is a valid sign-extension for the original mode. */
724 gcc_assert (INTVAL (newval)
725 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
727 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
728 CONST_INT is not valid, because after the replacement, the
729 original mode would be gone. Unfortunately, we can't tell
730 when do_SUBST is called to replace the operand thereof, so we
731 perform this test on oldval instead, checking whether an
732 invalid replacement took place before we got here. */
733 gcc_assert (!(GET_CODE (oldval) == SUBREG
734 && CONST_INT_P (SUBREG_REG (oldval))));
735 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
736 && CONST_INT_P (XEXP (oldval, 0))));
740 buf = undobuf.frees, undobuf.frees = buf->next;
742 buf = XNEW (struct undo);
744 buf->kind = UNDO_RTX;
746 buf->old_contents.r = oldval;
749 buf->next = undobuf.undos, undobuf.undos = buf;
752 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
754 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
755 for the value of a HOST_WIDE_INT value (including CONST_INT) is
759 do_SUBST_INT (int *into, int newval)
764 if (oldval == newval)
768 buf = undobuf.frees, undobuf.frees = buf->next;
770 buf = XNEW (struct undo);
772 buf->kind = UNDO_INT;
774 buf->old_contents.i = oldval;
777 buf->next = undobuf.undos, undobuf.undos = buf;
780 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but just substitute the mode. This is used when
783 changing the mode of a pseudo-register, so that any other
784 references to the entry in the regno_reg_rtx array will change as
788 do_SUBST_MODE (rtx *into, machine_mode newval)
791 machine_mode oldval = GET_MODE (*into);
793 if (oldval == newval)
797 buf = undobuf.frees, undobuf.frees = buf->next;
799 buf = XNEW (struct undo);
801 buf->kind = UNDO_MODE;
803 buf->old_contents.m = oldval;
804 adjust_reg_mode (*into, newval);
806 buf->next = undobuf.undos, undobuf.undos = buf;
809 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
811 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
814 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
817 struct insn_link * oldval = *into;
819 if (oldval == newval)
823 buf = undobuf.frees, undobuf.frees = buf->next;
825 buf = XNEW (struct undo);
827 buf->kind = UNDO_LINKS;
829 buf->old_contents.l = oldval;
832 buf->next = undobuf.undos, undobuf.undos = buf;
835 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
837 /* Subroutine of try_combine. Determine whether the replacement patterns
838 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
839 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
840 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
841 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
842 of all the instructions can be estimated and the replacements are more
843 expensive than the original sequence. */
846 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
847 rtx newpat, rtx newi2pat, rtx newotherpat)
849 int i0_cost, i1_cost, i2_cost, i3_cost;
850 int new_i2_cost, new_i3_cost;
851 int old_cost, new_cost;
853 /* Lookup the original insn_rtx_costs. */
854 i2_cost = INSN_COST (i2);
855 i3_cost = INSN_COST (i3);
859 i1_cost = INSN_COST (i1);
862 i0_cost = INSN_COST (i0);
863 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
864 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
868 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
869 ? i1_cost + i2_cost + i3_cost : 0);
875 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
876 i1_cost = i0_cost = 0;
879 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
881 if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
885 /* Calculate the replacement insn_rtx_costs. */
886 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
889 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
890 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
891 ? new_i2_cost + new_i3_cost : 0;
895 new_cost = new_i3_cost;
899 if (undobuf.other_insn)
901 int old_other_cost, new_other_cost;
903 old_other_cost = INSN_COST (undobuf.other_insn);
904 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
905 if (old_other_cost > 0 && new_other_cost > 0)
907 old_cost += old_other_cost;
908 new_cost += new_other_cost;
914 /* Disallow this combination if both new_cost and old_cost are greater than
915 zero, and new_cost is greater than old cost. */
916 int reject = old_cost > 0 && new_cost > old_cost;
920 fprintf (dump_file, "%s combination of insns ",
921 reject ? "rejecting" : "allowing");
923 fprintf (dump_file, "%d, ", INSN_UID (i0));
924 if (i1 && INSN_UID (i1) != INSN_UID (i2))
925 fprintf (dump_file, "%d, ", INSN_UID (i1));
926 fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
928 fprintf (dump_file, "original costs ");
930 fprintf (dump_file, "%d + ", i0_cost);
931 if (i1 && INSN_UID (i1) != INSN_UID (i2))
932 fprintf (dump_file, "%d + ", i1_cost);
933 fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
936 fprintf (dump_file, "replacement costs %d + %d = %d\n",
937 new_i2_cost, new_i3_cost, new_cost);
939 fprintf (dump_file, "replacement cost %d\n", new_cost);
945 /* Update the uid_insn_cost array with the replacement costs. */
946 INSN_COST (i2) = new_i2_cost;
947 INSN_COST (i3) = new_i3_cost;
959 /* Delete any insns that copy a register to itself. */
962 delete_noop_moves (void)
964 rtx_insn *insn, *next;
967 FOR_EACH_BB_FN (bb, cfun)
969 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
971 next = NEXT_INSN (insn);
972 if (INSN_P (insn) && noop_move_p (insn))
975 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
977 delete_insn_and_edges (insn);
984 /* Return false if we do not want to (or cannot) combine DEF. */
986 can_combine_def_p (df_ref def)
988 /* Do not consider if it is pre/post modification in MEM. */
989 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
992 unsigned int regno = DF_REF_REGNO (def);
994 /* Do not combine frame pointer adjustments. */
995 if ((regno == FRAME_POINTER_REGNUM
996 && (!reload_completed || frame_pointer_needed))
997 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
998 && regno == HARD_FRAME_POINTER_REGNUM
999 && (!reload_completed || frame_pointer_needed))
1000 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1001 && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
1007 /* Return false if we do not want to (or cannot) combine USE. */
1009 can_combine_use_p (df_ref use)
1011 /* Do not consider the usage of the stack pointer by function call. */
1012 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1018 /* Fill in log links field for all insns. */
1021 create_log_links (void)
1024 rtx_insn **next_use;
1028 next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1030 /* Pass through each block from the end, recording the uses of each
1031 register and establishing log links when def is encountered.
1032 Note that we do not clear next_use array in order to save time,
1033 so we have to test whether the use is in the same basic block as def.
1035 There are a few cases below when we do not consider the definition or
1036 usage -- these are taken from original flow.c did. Don't ask me why it is
1037 done this way; I don't know and if it works, I don't want to know. */
1039 FOR_EACH_BB_FN (bb, cfun)
1041 FOR_BB_INSNS_REVERSE (bb, insn)
1043 if (!NONDEBUG_INSN_P (insn))
1046 /* Log links are created only once. */
1047 gcc_assert (!LOG_LINKS (insn));
1049 FOR_EACH_INSN_DEF (def, insn)
1051 unsigned int regno = DF_REF_REGNO (def);
1054 if (!next_use[regno])
1057 if (!can_combine_def_p (def))
1060 use_insn = next_use[regno];
1061 next_use[regno] = NULL;
1063 if (BLOCK_FOR_INSN (use_insn) != bb)
1068 We don't build a LOG_LINK for hard registers contained
1069 in ASM_OPERANDs. If these registers get replaced,
1070 we might wind up changing the semantics of the insn,
1071 even if reload can make what appear to be valid
1072 assignments later. */
1073 if (regno < FIRST_PSEUDO_REGISTER
1074 && asm_noperands (PATTERN (use_insn)) >= 0)
1077 /* Don't add duplicate links between instructions. */
1078 struct insn_link *links;
1079 FOR_EACH_LOG_LINK (links, use_insn)
1080 if (insn == links->insn && regno == links->regno)
1084 LOG_LINKS (use_insn)
1085 = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1088 FOR_EACH_INSN_USE (use, insn)
1089 if (can_combine_use_p (use))
1090 next_use[DF_REF_REGNO (use)] = insn;
1097 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1098 true if we found a LOG_LINK that proves that A feeds B. This only works
1099 if there are no instructions between A and B which could have a link
1100 depending on A, since in that case we would not record a link for B.
1101 We also check the implicit dependency created by a cc0 setter/user
1105 insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1107 struct insn_link *links;
1108 FOR_EACH_LOG_LINK (links, b)
1109 if (links->insn == a)
1111 if (HAVE_cc0 && sets_cc0_p (a))
1116 /* Main entry point for combiner. F is the first insn of the function.
1117 NREGS is the first unused pseudo-reg number.
1119 Return nonzero if the combiner has turned an indirect jump
1120 instruction into a direct jump. */
1122 combine_instructions (rtx_insn *f, unsigned int nregs)
1124 rtx_insn *insn, *next;
1126 struct insn_link *links, *nextlinks;
1128 basic_block last_bb;
1130 int new_direct_jump_p = 0;
1132 for (first = f; first && !INSN_P (first); )
1133 first = NEXT_INSN (first);
1137 combine_attempts = 0;
1140 combine_successes = 0;
1142 rtl_hooks = combine_rtl_hooks;
1144 reg_stat.safe_grow_cleared (nregs);
1146 init_recog_no_volatile ();
1148 /* Allocate array for insn info. */
1149 max_uid_known = get_max_uid ();
1150 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1151 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1152 gcc_obstack_init (&insn_link_obstack);
1154 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1156 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1157 problems when, for example, we have j <<= 1 in a loop. */
1159 nonzero_sign_valid = 0;
1160 label_tick = label_tick_ebb_start = 1;
1162 /* Scan all SETs and see if we can deduce anything about what
1163 bits are known to be zero for some registers and how many copies
1164 of the sign bit are known to exist for those registers.
1166 Also set any known values so that we can use it while searching
1167 for what bits are known to be set. */
1169 setup_incoming_promotions (first);
1170 /* Allow the entry block and the first block to fall into the same EBB.
1171 Conceptually the incoming promotions are assigned to the entry block. */
1172 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1174 create_log_links ();
1175 FOR_EACH_BB_FN (this_basic_block, cfun)
1177 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1182 if (!single_pred_p (this_basic_block)
1183 || single_pred (this_basic_block) != last_bb)
1184 label_tick_ebb_start = label_tick;
1185 last_bb = this_basic_block;
1187 FOR_BB_INSNS (this_basic_block, insn)
1188 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1192 subst_low_luid = DF_INSN_LUID (insn);
1195 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1197 record_dead_and_set_regs (insn);
1200 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1201 if (REG_NOTE_KIND (links) == REG_INC)
1202 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1205 /* Record the current insn_rtx_cost of this instruction. */
1206 if (NONJUMP_INSN_P (insn))
1207 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1208 optimize_this_for_speed_p);
1210 fprintf (dump_file, "insn_cost %d: %d\n",
1211 INSN_UID (insn), INSN_COST (insn));
1215 nonzero_sign_valid = 1;
1217 /* Now scan all the insns in forward order. */
1218 label_tick = label_tick_ebb_start = 1;
1220 setup_incoming_promotions (first);
1221 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1222 int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS);
1224 FOR_EACH_BB_FN (this_basic_block, cfun)
1226 rtx_insn *last_combined_insn = NULL;
1227 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1232 if (!single_pred_p (this_basic_block)
1233 || single_pred (this_basic_block) != last_bb)
1234 label_tick_ebb_start = label_tick;
1235 last_bb = this_basic_block;
1237 rtl_profile_for_bb (this_basic_block);
1238 for (insn = BB_HEAD (this_basic_block);
1239 insn != NEXT_INSN (BB_END (this_basic_block));
1240 insn = next ? next : NEXT_INSN (insn))
1243 if (!NONDEBUG_INSN_P (insn))
1246 while (last_combined_insn
1247 && last_combined_insn->deleted ())
1248 last_combined_insn = PREV_INSN (last_combined_insn);
1249 if (last_combined_insn == NULL_RTX
1250 || BARRIER_P (last_combined_insn)
1251 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1252 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1253 last_combined_insn = insn;
1255 /* See if we know about function return values before this
1256 insn based upon SUBREG flags. */
1257 check_promoted_subreg (insn, PATTERN (insn));
1259 /* See if we can find hardregs and subreg of pseudos in
1260 narrower modes. This could help turning TRUNCATEs
1262 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1264 /* Try this insn with each insn it links back to. */
1266 FOR_EACH_LOG_LINK (links, insn)
1267 if ((next = try_combine (insn, links->insn, NULL,
1268 NULL, &new_direct_jump_p,
1269 last_combined_insn)) != 0)
1271 statistics_counter_event (cfun, "two-insn combine", 1);
1275 /* Try each sequence of three linked insns ending with this one. */
1277 if (max_combine >= 3)
1278 FOR_EACH_LOG_LINK (links, insn)
1280 rtx_insn *link = links->insn;
1282 /* If the linked insn has been replaced by a note, then there
1283 is no point in pursuing this chain any further. */
1287 FOR_EACH_LOG_LINK (nextlinks, link)
1288 if ((next = try_combine (insn, link, nextlinks->insn,
1289 NULL, &new_direct_jump_p,
1290 last_combined_insn)) != 0)
1292 statistics_counter_event (cfun, "three-insn combine", 1);
1297 /* Try to combine a jump insn that uses CC0
1298 with a preceding insn that sets CC0, and maybe with its
1299 logical predecessor as well.
1300 This is how we make decrement-and-branch insns.
1301 We need this special code because data flow connections
1302 via CC0 do not get entered in LOG_LINKS. */
1306 && (prev = prev_nonnote_insn (insn)) != 0
1307 && NONJUMP_INSN_P (prev)
1308 && sets_cc0_p (PATTERN (prev)))
1310 if ((next = try_combine (insn, prev, NULL, NULL,
1312 last_combined_insn)) != 0)
1315 FOR_EACH_LOG_LINK (nextlinks, prev)
1316 if ((next = try_combine (insn, prev, nextlinks->insn,
1317 NULL, &new_direct_jump_p,
1318 last_combined_insn)) != 0)
1322 /* Do the same for an insn that explicitly references CC0. */
1323 if (HAVE_cc0 && NONJUMP_INSN_P (insn)
1324 && (prev = prev_nonnote_insn (insn)) != 0
1325 && NONJUMP_INSN_P (prev)
1326 && sets_cc0_p (PATTERN (prev))
1327 && GET_CODE (PATTERN (insn)) == SET
1328 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1330 if ((next = try_combine (insn, prev, NULL, NULL,
1332 last_combined_insn)) != 0)
1335 FOR_EACH_LOG_LINK (nextlinks, prev)
1336 if ((next = try_combine (insn, prev, nextlinks->insn,
1337 NULL, &new_direct_jump_p,
1338 last_combined_insn)) != 0)
1342 /* Finally, see if any of the insns that this insn links to
1343 explicitly references CC0. If so, try this insn, that insn,
1344 and its predecessor if it sets CC0. */
1347 FOR_EACH_LOG_LINK (links, insn)
1348 if (NONJUMP_INSN_P (links->insn)
1349 && GET_CODE (PATTERN (links->insn)) == SET
1350 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1351 && (prev = prev_nonnote_insn (links->insn)) != 0
1352 && NONJUMP_INSN_P (prev)
1353 && sets_cc0_p (PATTERN (prev))
1354 && (next = try_combine (insn, links->insn,
1355 prev, NULL, &new_direct_jump_p,
1356 last_combined_insn)) != 0)
1360 /* Try combining an insn with two different insns whose results it
1362 if (max_combine >= 3)
1363 FOR_EACH_LOG_LINK (links, insn)
1364 for (nextlinks = links->next; nextlinks;
1365 nextlinks = nextlinks->next)
1366 if ((next = try_combine (insn, links->insn,
1367 nextlinks->insn, NULL,
1369 last_combined_insn)) != 0)
1372 statistics_counter_event (cfun, "three-insn combine", 1);
1376 /* Try four-instruction combinations. */
1377 if (max_combine >= 4)
1378 FOR_EACH_LOG_LINK (links, insn)
1380 struct insn_link *next1;
1381 rtx_insn *link = links->insn;
1383 /* If the linked insn has been replaced by a note, then there
1384 is no point in pursuing this chain any further. */
1388 FOR_EACH_LOG_LINK (next1, link)
1390 rtx_insn *link1 = next1->insn;
1393 /* I0 -> I1 -> I2 -> I3. */
1394 FOR_EACH_LOG_LINK (nextlinks, link1)
1395 if ((next = try_combine (insn, link, link1,
1398 last_combined_insn)) != 0)
1400 statistics_counter_event (cfun, "four-insn combine", 1);
1403 /* I0, I1 -> I2, I2 -> I3. */
1404 for (nextlinks = next1->next; nextlinks;
1405 nextlinks = nextlinks->next)
1406 if ((next = try_combine (insn, link, link1,
1409 last_combined_insn)) != 0)
1411 statistics_counter_event (cfun, "four-insn combine", 1);
1416 for (next1 = links->next; next1; next1 = next1->next)
1418 rtx_insn *link1 = next1->insn;
1421 /* I0 -> I2; I1, I2 -> I3. */
1422 FOR_EACH_LOG_LINK (nextlinks, link)
1423 if ((next = try_combine (insn, link, link1,
1426 last_combined_insn)) != 0)
1428 statistics_counter_event (cfun, "four-insn combine", 1);
1431 /* I0 -> I1; I1, I2 -> I3. */
1432 FOR_EACH_LOG_LINK (nextlinks, link1)
1433 if ((next = try_combine (insn, link, link1,
1436 last_combined_insn)) != 0)
1438 statistics_counter_event (cfun, "four-insn combine", 1);
1444 /* Try this insn with each REG_EQUAL note it links back to. */
1445 FOR_EACH_LOG_LINK (links, insn)
1448 rtx_insn *temp = links->insn;
1449 if ((set = single_set (temp)) != 0
1450 && (note = find_reg_equal_equiv_note (temp)) != 0
1451 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1452 /* Avoid using a register that may already been marked
1453 dead by an earlier instruction. */
1454 && ! unmentioned_reg_p (note, SET_SRC (set))
1455 && (GET_MODE (note) == VOIDmode
1456 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1457 : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1458 && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1459 || (GET_MODE (XEXP (SET_DEST (set), 0))
1460 == GET_MODE (note))))))
1462 /* Temporarily replace the set's source with the
1463 contents of the REG_EQUAL note. The insn will
1464 be deleted or recognized by try_combine. */
1465 rtx orig_src = SET_SRC (set);
1466 rtx orig_dest = SET_DEST (set);
1467 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1468 SET_DEST (set) = XEXP (SET_DEST (set), 0);
1469 SET_SRC (set) = note;
1471 i2mod_old_rhs = copy_rtx (orig_src);
1472 i2mod_new_rhs = copy_rtx (note);
1473 next = try_combine (insn, i2mod, NULL, NULL,
1475 last_combined_insn);
1479 statistics_counter_event (cfun, "insn-with-note combine", 1);
1482 SET_SRC (set) = orig_src;
1483 SET_DEST (set) = orig_dest;
1488 record_dead_and_set_regs (insn);
1495 default_rtl_profile ();
1497 new_direct_jump_p |= purge_all_dead_edges ();
1498 delete_noop_moves ();
1501 obstack_free (&insn_link_obstack, NULL);
1502 free (uid_log_links);
1503 free (uid_insn_cost);
1504 reg_stat.release ();
1507 struct undo *undo, *next;
1508 for (undo = undobuf.frees; undo; undo = next)
1516 total_attempts += combine_attempts;
1517 total_merges += combine_merges;
1518 total_extras += combine_extras;
1519 total_successes += combine_successes;
1521 nonzero_sign_valid = 0;
1522 rtl_hooks = general_rtl_hooks;
1524 /* Make recognizer allow volatile MEMs again. */
1527 return new_direct_jump_p;
1530 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1533 init_reg_last (void)
1538 FOR_EACH_VEC_ELT (reg_stat, i, p)
1539 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1542 /* Set up any promoted values for incoming argument registers. */
1545 setup_incoming_promotions (rtx_insn *first)
1548 bool strictly_local = false;
1550 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1551 arg = DECL_CHAIN (arg))
1553 rtx x, reg = DECL_INCOMING_RTL (arg);
1555 machine_mode mode1, mode2, mode3, mode4;
1557 /* Only continue if the incoming argument is in a register. */
1561 /* Determine, if possible, whether all call sites of the current
1562 function lie within the current compilation unit. (This does
1563 take into account the exporting of a function via taking its
1564 address, and so forth.) */
1565 strictly_local = cgraph_node::local_info (current_function_decl)->local;
1567 /* The mode and signedness of the argument before any promotions happen
1568 (equal to the mode of the pseudo holding it at that stage). */
1569 mode1 = TYPE_MODE (TREE_TYPE (arg));
1570 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1572 /* The mode and signedness of the argument after any source language and
1573 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1574 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1575 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1577 /* The mode and signedness of the argument as it is actually passed,
1578 see assign_parm_setup_reg in function.c. */
1579 mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1580 TREE_TYPE (cfun->decl), 0);
1582 /* The mode of the register in which the argument is being passed. */
1583 mode4 = GET_MODE (reg);
1585 /* Eliminate sign extensions in the callee when:
1586 (a) A mode promotion has occurred; */
1589 /* (b) The mode of the register is the same as the mode of
1590 the argument as it is passed; */
1593 /* (c) There's no language level extension; */
1596 /* (c.1) All callers are from the current compilation unit. If that's
1597 the case we don't have to rely on an ABI, we only have to know
1598 what we're generating right now, and we know that we will do the
1599 mode1 to mode2 promotion with the given sign. */
1600 else if (!strictly_local)
1602 /* (c.2) The combination of the two promotions is useful. This is
1603 true when the signs match, or if the first promotion is unsigned.
1604 In the later case, (sign_extend (zero_extend x)) is the same as
1605 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1611 /* Record that the value was promoted from mode1 to mode3,
1612 so that any sign extension at the head of the current
1613 function may be eliminated. */
1614 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1615 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1616 record_value_for_reg (reg, first, x);
1620 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1621 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1622 because some machines (maybe most) will actually do the sign-extension and
1623 this is the conservative approach.
1625 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1629 sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1631 if (GET_MODE_PRECISION (mode) < prec
1632 && CONST_INT_P (src)
1634 && val_signbit_known_set_p (mode, INTVAL (src)))
1635 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (mode));
1640 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1644 update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1647 rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1648 unsigned HOST_WIDE_INT bits = 0;
1649 rtx reg_equal = NULL, src = SET_SRC (set);
1650 unsigned int num = 0;
1653 reg_equal = XEXP (reg_equal_note, 0);
1655 if (SHORT_IMMEDIATES_SIGN_EXTEND)
1657 src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1659 reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1662 /* Don't call nonzero_bits if it cannot change anything. */
1663 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1665 bits = nonzero_bits (src, nonzero_bits_mode);
1666 if (reg_equal && bits)
1667 bits &= nonzero_bits (reg_equal, nonzero_bits_mode);
1668 rsp->nonzero_bits |= bits;
1671 /* Don't call num_sign_bit_copies if it cannot change anything. */
1672 if (rsp->sign_bit_copies != 1)
1674 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1675 if (reg_equal && num != GET_MODE_PRECISION (GET_MODE (x)))
1677 unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1678 if (num == 0 || numeq > num)
1681 if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1682 rsp->sign_bit_copies = num;
1686 /* Called via note_stores. If X is a pseudo that is narrower than
1687 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1689 If we are setting only a portion of X and we can't figure out what
1690 portion, assume all bits will be used since we don't know what will
1693 Similarly, set how many bits of X are known to be copies of the sign bit
1694 at all locations in the function. This is the smallest number implied
1698 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1700 rtx_insn *insn = (rtx_insn *) data;
1703 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1704 /* If this register is undefined at the start of the file, we can't
1705 say what its contents were. */
1706 && ! REGNO_REG_SET_P
1707 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1708 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1710 reg_stat_type *rsp = ®_stat[REGNO (x)];
1712 if (set == 0 || GET_CODE (set) == CLOBBER)
1714 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1715 rsp->sign_bit_copies = 1;
1719 /* If this register is being initialized using itself, and the
1720 register is uninitialized in this basic block, and there are
1721 no LOG_LINKS which set the register, then part of the
1722 register is uninitialized. In that case we can't assume
1723 anything about the number of nonzero bits.
1725 ??? We could do better if we checked this in
1726 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1727 could avoid making assumptions about the insn which initially
1728 sets the register, while still using the information in other
1729 insns. We would have to be careful to check every insn
1730 involved in the combination. */
1733 && reg_referenced_p (x, PATTERN (insn))
1734 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1737 struct insn_link *link;
1739 FOR_EACH_LOG_LINK (link, insn)
1740 if (dead_or_set_p (link->insn, x))
1744 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1745 rsp->sign_bit_copies = 1;
1750 /* If this is a complex assignment, see if we can convert it into a
1751 simple assignment. */
1752 set = expand_field_assignment (set);
1754 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1755 set what we know about X. */
1757 if (SET_DEST (set) == x
1758 || (paradoxical_subreg_p (SET_DEST (set))
1759 && SUBREG_REG (SET_DEST (set)) == x))
1760 update_rsp_from_reg_equal (rsp, insn, set, x);
1763 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1764 rsp->sign_bit_copies = 1;
1769 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1770 optionally insns that were previously combined into I3 or that will be
1771 combined into the merger of INSN and I3. The order is PRED, PRED2,
1772 INSN, SUCC, SUCC2, I3.
1774 Return 0 if the combination is not allowed for any reason.
1776 If the combination is allowed, *PDEST will be set to the single
1777 destination of INSN and *PSRC to the single source, and this function
1781 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1782 rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1783 rtx *pdest, rtx *psrc)
1790 bool all_adjacent = true;
1791 int (*is_volatile_p) (const_rtx);
1797 if (next_active_insn (succ2) != i3)
1798 all_adjacent = false;
1799 if (next_active_insn (succ) != succ2)
1800 all_adjacent = false;
1802 else if (next_active_insn (succ) != i3)
1803 all_adjacent = false;
1804 if (next_active_insn (insn) != succ)
1805 all_adjacent = false;
1807 else if (next_active_insn (insn) != i3)
1808 all_adjacent = false;
1810 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1811 or a PARALLEL consisting of such a SET and CLOBBERs.
1813 If INSN has CLOBBER parallel parts, ignore them for our processing.
1814 By definition, these happen during the execution of the insn. When it
1815 is merged with another insn, all bets are off. If they are, in fact,
1816 needed and aren't also supplied in I3, they may be added by
1817 recog_for_combine. Otherwise, it won't match.
1819 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1822 Get the source and destination of INSN. If more than one, can't
1825 if (GET_CODE (PATTERN (insn)) == SET)
1826 set = PATTERN (insn);
1827 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1828 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1830 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1832 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1834 switch (GET_CODE (elt))
1836 /* This is important to combine floating point insns
1837 for the SH4 port. */
1839 /* Combining an isolated USE doesn't make sense.
1840 We depend here on combinable_i3pat to reject them. */
1841 /* The code below this loop only verifies that the inputs of
1842 the SET in INSN do not change. We call reg_set_between_p
1843 to verify that the REG in the USE does not change between
1845 If the USE in INSN was for a pseudo register, the matching
1846 insn pattern will likely match any register; combining this
1847 with any other USE would only be safe if we knew that the
1848 used registers have identical values, or if there was
1849 something to tell them apart, e.g. different modes. For
1850 now, we forgo such complicated tests and simply disallow
1851 combining of USES of pseudo registers with any other USE. */
1852 if (REG_P (XEXP (elt, 0))
1853 && GET_CODE (PATTERN (i3)) == PARALLEL)
1855 rtx i3pat = PATTERN (i3);
1856 int i = XVECLEN (i3pat, 0) - 1;
1857 unsigned int regno = REGNO (XEXP (elt, 0));
1861 rtx i3elt = XVECEXP (i3pat, 0, i);
1863 if (GET_CODE (i3elt) == USE
1864 && REG_P (XEXP (i3elt, 0))
1865 && (REGNO (XEXP (i3elt, 0)) == regno
1866 ? reg_set_between_p (XEXP (elt, 0),
1867 PREV_INSN (insn), i3)
1868 : regno >= FIRST_PSEUDO_REGISTER))
1875 /* We can ignore CLOBBERs. */
1880 /* Ignore SETs whose result isn't used but not those that
1881 have side-effects. */
1882 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1883 && insn_nothrow_p (insn)
1884 && !side_effects_p (elt))
1887 /* If we have already found a SET, this is a second one and
1888 so we cannot combine with this insn. */
1896 /* Anything else means we can't combine. */
1902 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1903 so don't do anything with it. */
1904 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1913 /* The simplification in expand_field_assignment may call back to
1914 get_last_value, so set safe guard here. */
1915 subst_low_luid = DF_INSN_LUID (insn);
1917 set = expand_field_assignment (set);
1918 src = SET_SRC (set), dest = SET_DEST (set);
1920 /* Do not eliminate user-specified register if it is in an
1921 asm input because we may break the register asm usage defined
1922 in GCC manual if allow to do so.
1923 Be aware that this may cover more cases than we expect but this
1924 should be harmless. */
1925 if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1926 && extract_asm_operands (PATTERN (i3)))
1929 /* Don't eliminate a store in the stack pointer. */
1930 if (dest == stack_pointer_rtx
1931 /* Don't combine with an insn that sets a register to itself if it has
1932 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1933 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1934 /* Can't merge an ASM_OPERANDS. */
1935 || GET_CODE (src) == ASM_OPERANDS
1936 /* Can't merge a function call. */
1937 || GET_CODE (src) == CALL
1938 /* Don't eliminate a function call argument. */
1940 && (find_reg_fusage (i3, USE, dest)
1942 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1943 && global_regs[REGNO (dest)])))
1944 /* Don't substitute into an incremented register. */
1945 || FIND_REG_INC_NOTE (i3, dest)
1946 || (succ && FIND_REG_INC_NOTE (succ, dest))
1947 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1948 /* Don't substitute into a non-local goto, this confuses CFG. */
1949 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1950 /* Make sure that DEST is not used after SUCC but before I3. */
1953 && (reg_used_between_p (dest, succ2, i3)
1954 || reg_used_between_p (dest, succ, succ2)))
1955 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1956 /* Make sure that the value that is to be substituted for the register
1957 does not use any registers whose values alter in between. However,
1958 If the insns are adjacent, a use can't cross a set even though we
1959 think it might (this can happen for a sequence of insns each setting
1960 the same destination; last_set of that register might point to
1961 a NOTE). If INSN has a REG_EQUIV note, the register is always
1962 equivalent to the memory so the substitution is valid even if there
1963 are intervening stores. Also, don't move a volatile asm or
1964 UNSPEC_VOLATILE across any other insns. */
1967 || ! find_reg_note (insn, REG_EQUIV, src))
1968 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1969 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1970 || GET_CODE (src) == UNSPEC_VOLATILE))
1971 /* Don't combine across a CALL_INSN, because that would possibly
1972 change whether the life span of some REGs crosses calls or not,
1973 and it is a pain to update that information.
1974 Exception: if source is a constant, moving it later can't hurt.
1975 Accept that as a special case. */
1976 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1979 /* DEST must either be a REG or CC0. */
1982 /* If register alignment is being enforced for multi-word items in all
1983 cases except for parameters, it is possible to have a register copy
1984 insn referencing a hard register that is not allowed to contain the
1985 mode being copied and which would not be valid as an operand of most
1986 insns. Eliminate this problem by not combining with such an insn.
1988 Also, on some machines we don't want to extend the life of a hard
1992 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1993 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1994 /* Don't extend the life of a hard register unless it is
1995 user variable (if we have few registers) or it can't
1996 fit into the desired register (meaning something special
1998 Also avoid substituting a return register into I3, because
1999 reload can't handle a conflict with constraints of other
2001 || (REGNO (src) < FIRST_PSEUDO_REGISTER
2002 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
2005 else if (GET_CODE (dest) != CC0)
2009 if (GET_CODE (PATTERN (i3)) == PARALLEL)
2010 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
2011 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
2013 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
2015 /* If the clobber represents an earlyclobber operand, we must not
2016 substitute an expression containing the clobbered register.
2017 As we do not analyze the constraint strings here, we have to
2018 make the conservative assumption. However, if the register is
2019 a fixed hard reg, the clobber cannot represent any operand;
2020 we leave it up to the machine description to either accept or
2021 reject use-and-clobber patterns. */
2023 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
2024 || !fixed_regs[REGNO (reg)])
2025 if (reg_overlap_mentioned_p (reg, src))
2029 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2030 or not), reject, unless nothing volatile comes between it and I3 */
2032 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
2034 /* Make sure neither succ nor succ2 contains a volatile reference. */
2035 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
2037 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
2039 /* We'll check insns between INSN and I3 below. */
2042 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2043 to be an explicit register variable, and was chosen for a reason. */
2045 if (GET_CODE (src) == ASM_OPERANDS
2046 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2049 /* If INSN contains volatile references (specifically volatile MEMs),
2050 we cannot combine across any other volatile references.
2051 Even if INSN doesn't contain volatile references, any intervening
2052 volatile insn might affect machine state. */
2054 is_volatile_p = volatile_refs_p (PATTERN (insn))
2058 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2059 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2062 /* If INSN contains an autoincrement or autodecrement, make sure that
2063 register is not used between there and I3, and not already used in
2064 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2065 Also insist that I3 not be a jump; if it were one
2066 and the incremented register were spilled, we would lose. */
2069 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2070 if (REG_NOTE_KIND (link) == REG_INC
2072 || reg_used_between_p (XEXP (link, 0), insn, i3)
2073 || (pred != NULL_RTX
2074 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2075 || (pred2 != NULL_RTX
2076 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2077 || (succ != NULL_RTX
2078 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2079 || (succ2 != NULL_RTX
2080 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2081 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2084 /* Don't combine an insn that follows a CC0-setting insn.
2085 An insn that uses CC0 must not be separated from the one that sets it.
2086 We do, however, allow I2 to follow a CC0-setting insn if that insn
2087 is passed as I1; in that case it will be deleted also.
2088 We also allow combining in this case if all the insns are adjacent
2089 because that would leave the two CC0 insns adjacent as well.
2090 It would be more logical to test whether CC0 occurs inside I1 or I2,
2091 but that would be much slower, and this ought to be equivalent. */
2095 p = prev_nonnote_insn (insn);
2096 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2101 /* If we get here, we have passed all the tests and the combination is
2110 /* LOC is the location within I3 that contains its pattern or the component
2111 of a PARALLEL of the pattern. We validate that it is valid for combining.
2113 One problem is if I3 modifies its output, as opposed to replacing it
2114 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2115 doing so would produce an insn that is not equivalent to the original insns.
2119 (set (reg:DI 101) (reg:DI 100))
2120 (set (subreg:SI (reg:DI 101) 0) <foo>)
2122 This is NOT equivalent to:
2124 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2125 (set (reg:DI 101) (reg:DI 100))])
2127 Not only does this modify 100 (in which case it might still be valid
2128 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2130 We can also run into a problem if I2 sets a register that I1
2131 uses and I1 gets directly substituted into I3 (not via I2). In that
2132 case, we would be getting the wrong value of I2DEST into I3, so we
2133 must reject the combination. This case occurs when I2 and I1 both
2134 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2135 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2136 of a SET must prevent combination from occurring. The same situation
2137 can occur for I0, in which case I0_NOT_IN_SRC is set.
2139 Before doing the above check, we first try to expand a field assignment
2140 into a set of logical operations.
2142 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2143 we place a register that is both set and used within I3. If more than one
2144 such register is detected, we fail.
2146 Return 1 if the combination is valid, zero otherwise. */
2149 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2150 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2154 if (GET_CODE (x) == SET)
2157 rtx dest = SET_DEST (set);
2158 rtx src = SET_SRC (set);
2159 rtx inner_dest = dest;
2162 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2163 || GET_CODE (inner_dest) == SUBREG
2164 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2165 inner_dest = XEXP (inner_dest, 0);
2167 /* Check for the case where I3 modifies its output, as discussed
2168 above. We don't want to prevent pseudos from being combined
2169 into the address of a MEM, so only prevent the combination if
2170 i1 or i2 set the same MEM. */
2171 if ((inner_dest != dest &&
2172 (!MEM_P (inner_dest)
2173 || rtx_equal_p (i2dest, inner_dest)
2174 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2175 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2176 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2177 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2178 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2180 /* This is the same test done in can_combine_p except we can't test
2181 all_adjacent; we don't have to, since this instruction will stay
2182 in place, thus we are not considering increasing the lifetime of
2185 Also, if this insn sets a function argument, combining it with
2186 something that might need a spill could clobber a previous
2187 function argument; the all_adjacent test in can_combine_p also
2188 checks this; here, we do a more specific test for this case. */
2190 || (REG_P (inner_dest)
2191 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2192 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2193 GET_MODE (inner_dest))))
2194 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2195 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2198 /* If DEST is used in I3, it is being killed in this insn, so
2199 record that for later. We have to consider paradoxical
2200 subregs here, since they kill the whole register, but we
2201 ignore partial subregs, STRICT_LOW_PART, etc.
2202 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2203 STACK_POINTER_REGNUM, since these are always considered to be
2204 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2206 if (GET_CODE (subdest) == SUBREG
2207 && (GET_MODE_SIZE (GET_MODE (subdest))
2208 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2209 subdest = SUBREG_REG (subdest);
2212 && reg_referenced_p (subdest, PATTERN (i3))
2213 && REGNO (subdest) != FRAME_POINTER_REGNUM
2214 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2215 || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2216 && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2217 || (REGNO (subdest) != ARG_POINTER_REGNUM
2218 || ! fixed_regs [REGNO (subdest)]))
2219 && REGNO (subdest) != STACK_POINTER_REGNUM)
2221 if (*pi3dest_killed)
2224 *pi3dest_killed = subdest;
2228 else if (GET_CODE (x) == PARALLEL)
2232 for (i = 0; i < XVECLEN (x, 0); i++)
2233 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2234 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2241 /* Return 1 if X is an arithmetic expression that contains a multiplication
2242 and division. We don't count multiplications by powers of two here. */
2245 contains_muldiv (rtx x)
2247 switch (GET_CODE (x))
2249 case MOD: case DIV: case UMOD: case UDIV:
2253 return ! (CONST_INT_P (XEXP (x, 1))
2254 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2257 return contains_muldiv (XEXP (x, 0))
2258 || contains_muldiv (XEXP (x, 1));
2261 return contains_muldiv (XEXP (x, 0));
2267 /* Determine whether INSN can be used in a combination. Return nonzero if
2268 not. This is used in try_combine to detect early some cases where we
2269 can't perform combinations. */
2272 cant_combine_insn_p (rtx_insn *insn)
2277 /* If this isn't really an insn, we can't do anything.
2278 This can occur when flow deletes an insn that it has merged into an
2279 auto-increment address. */
2280 if (! INSN_P (insn))
2283 /* Never combine loads and stores involving hard regs that are likely
2284 to be spilled. The register allocator can usually handle such
2285 reg-reg moves by tying. If we allow the combiner to make
2286 substitutions of likely-spilled regs, reload might die.
2287 As an exception, we allow combinations involving fixed regs; these are
2288 not available to the register allocator so there's no risk involved. */
2290 set = single_set (insn);
2293 src = SET_SRC (set);
2294 dest = SET_DEST (set);
2295 if (GET_CODE (src) == SUBREG)
2296 src = SUBREG_REG (src);
2297 if (GET_CODE (dest) == SUBREG)
2298 dest = SUBREG_REG (dest);
2299 if (REG_P (src) && REG_P (dest)
2300 && ((HARD_REGISTER_P (src)
2301 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2302 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2303 || (HARD_REGISTER_P (dest)
2304 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2305 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2311 struct likely_spilled_retval_info
2313 unsigned regno, nregs;
2317 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2318 hard registers that are known to be written to / clobbered in full. */
2320 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2322 struct likely_spilled_retval_info *const info =
2323 (struct likely_spilled_retval_info *) data;
2324 unsigned regno, nregs;
2327 if (!REG_P (XEXP (set, 0)))
2330 if (regno >= info->regno + info->nregs)
2332 nregs = REG_NREGS (x);
2333 if (regno + nregs <= info->regno)
2335 new_mask = (2U << (nregs - 1)) - 1;
2336 if (regno < info->regno)
2337 new_mask >>= info->regno - regno;
2339 new_mask <<= regno - info->regno;
2340 info->mask &= ~new_mask;
2343 /* Return nonzero iff part of the return value is live during INSN, and
2344 it is likely spilled. This can happen when more than one insn is needed
2345 to copy the return value, e.g. when we consider to combine into the
2346 second copy insn for a complex value. */
2349 likely_spilled_retval_p (rtx_insn *insn)
2351 rtx_insn *use = BB_END (this_basic_block);
2354 unsigned regno, nregs;
2355 /* We assume here that no machine mode needs more than
2356 32 hard registers when the value overlaps with a register
2357 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2359 struct likely_spilled_retval_info info;
2361 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2363 reg = XEXP (PATTERN (use), 0);
2364 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2366 regno = REGNO (reg);
2367 nregs = REG_NREGS (reg);
2370 mask = (2U << (nregs - 1)) - 1;
2372 /* Disregard parts of the return value that are set later. */
2376 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2378 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2381 /* Check if any of the (probably) live return value registers is
2386 if ((mask & 1 << nregs)
2387 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2393 /* Adjust INSN after we made a change to its destination.
2395 Changing the destination can invalidate notes that say something about
2396 the results of the insn and a LOG_LINK pointing to the insn. */
2399 adjust_for_new_dest (rtx_insn *insn)
2401 /* For notes, be conservative and simply remove them. */
2402 remove_reg_equal_equiv_notes (insn);
2404 /* The new insn will have a destination that was previously the destination
2405 of an insn just above it. Call distribute_links to make a LOG_LINK from
2406 the next use of that destination. */
2408 rtx set = single_set (insn);
2411 rtx reg = SET_DEST (set);
2413 while (GET_CODE (reg) == ZERO_EXTRACT
2414 || GET_CODE (reg) == STRICT_LOW_PART
2415 || GET_CODE (reg) == SUBREG)
2416 reg = XEXP (reg, 0);
2417 gcc_assert (REG_P (reg));
2419 distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2421 df_insn_rescan (insn);
2424 /* Return TRUE if combine can reuse reg X in mode MODE.
2425 ADDED_SETS is nonzero if the original set is still required. */
2427 can_change_dest_mode (rtx x, int added_sets, machine_mode mode)
2435 /* Allow hard registers if the new mode is legal, and occupies no more
2436 registers than the old mode. */
2437 if (regno < FIRST_PSEUDO_REGISTER)
2438 return (HARD_REGNO_MODE_OK (regno, mode)
2439 && REG_NREGS (x) >= hard_regno_nregs[regno][mode]);
2441 /* Or a pseudo that is only used once. */
2442 return (regno < reg_n_sets_max
2443 && REG_N_SETS (regno) == 1
2445 && !REG_USERVAR_P (x));
2449 /* Check whether X, the destination of a set, refers to part of
2450 the register specified by REG. */
2453 reg_subword_p (rtx x, rtx reg)
2455 /* Check that reg is an integer mode register. */
2456 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2459 if (GET_CODE (x) == STRICT_LOW_PART
2460 || GET_CODE (x) == ZERO_EXTRACT)
2463 return GET_CODE (x) == SUBREG
2464 && SUBREG_REG (x) == reg
2465 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2468 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2469 Note that the INSN should be deleted *after* removing dead edges, so
2470 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2471 but not for a (set (pc) (label_ref FOO)). */
2474 update_cfg_for_uncondjump (rtx_insn *insn)
2476 basic_block bb = BLOCK_FOR_INSN (insn);
2477 gcc_assert (BB_END (bb) == insn);
2479 purge_dead_edges (bb);
2482 if (EDGE_COUNT (bb->succs) == 1)
2486 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2488 /* Remove barriers from the footer if there are any. */
2489 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2490 if (BARRIER_P (insn))
2492 if (PREV_INSN (insn))
2493 SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2495 BB_FOOTER (bb) = NEXT_INSN (insn);
2496 if (NEXT_INSN (insn))
2497 SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2499 else if (LABEL_P (insn))
2504 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2505 by an arbitrary number of CLOBBERs. */
2507 is_parallel_of_n_reg_sets (rtx pat, int n)
2509 if (GET_CODE (pat) != PARALLEL)
2512 int len = XVECLEN (pat, 0);
2517 for (i = 0; i < n; i++)
2518 if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2519 || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2521 for ( ; i < len; i++)
2522 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER
2523 || XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2529 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2530 CLOBBERs), can be split into individual SETs in that order, without
2531 changing semantics. */
2533 can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2535 if (!insn_nothrow_p (insn))
2538 rtx pat = PATTERN (insn);
2541 for (i = 0; i < n; i++)
2543 if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2546 rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2548 for (j = i + 1; j < n; j++)
2549 if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2556 /* Try to combine the insns I0, I1 and I2 into I3.
2557 Here I0, I1 and I2 appear earlier than I3.
2558 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2561 If we are combining more than two insns and the resulting insn is not
2562 recognized, try splitting it into two insns. If that happens, I2 and I3
2563 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2564 Otherwise, I0, I1 and I2 are pseudo-deleted.
2566 Return 0 if the combination does not work. Then nothing is changed.
2567 If we did the combination, return the insn at which combine should
2570 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2571 new direct jump instruction.
2573 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2574 been I3 passed to an earlier try_combine within the same basic
2578 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2579 int *new_direct_jump_p, rtx_insn *last_combined_insn)
2581 /* New patterns for I3 and I2, respectively. */
2582 rtx newpat, newi2pat = 0;
2583 rtvec newpat_vec_with_clobbers = 0;
2584 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2585 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2587 int added_sets_0, added_sets_1, added_sets_2;
2588 /* Total number of SETs to put into I3. */
2590 /* Nonzero if I2's or I1's body now appears in I3. */
2591 int i2_is_used = 0, i1_is_used = 0;
2592 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2593 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2594 /* Contains I3 if the destination of I3 is used in its source, which means
2595 that the old life of I3 is being killed. If that usage is placed into
2596 I2 and not in I3, a REG_DEAD note must be made. */
2597 rtx i3dest_killed = 0;
2598 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2599 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2600 /* Copy of SET_SRC of I1 and I0, if needed. */
2601 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2602 /* Set if I2DEST was reused as a scratch register. */
2603 bool i2scratch = false;
2604 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2605 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2606 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2607 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2608 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2609 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2610 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2611 /* Notes that must be added to REG_NOTES in I3 and I2. */
2612 rtx new_i3_notes, new_i2_notes;
2613 /* Notes that we substituted I3 into I2 instead of the normal case. */
2614 int i3_subst_into_i2 = 0;
2615 /* Notes that I1, I2 or I3 is a MULT operation. */
2618 int changed_i3_dest = 0;
2621 rtx_insn *temp_insn;
2623 struct insn_link *link;
2625 rtx new_other_notes;
2628 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2630 if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2633 /* Only try four-insn combinations when there's high likelihood of
2634 success. Look for simple insns, such as loads of constants or
2635 binary operations involving a constant. */
2643 if (!flag_expensive_optimizations)
2646 for (i = 0; i < 4; i++)
2648 rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2649 rtx set = single_set (insn);
2653 src = SET_SRC (set);
2654 if (CONSTANT_P (src))
2659 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2661 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2662 || GET_CODE (src) == LSHIFTRT)
2666 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2667 are likely manipulating its value. Ideally we'll be able to combine
2668 all four insns into a bitfield insertion of some kind.
2670 Note the source in I0 might be inside a sign/zero extension and the
2671 memory modes in I0 and I3 might be different. So extract the address
2672 from the destination of I3 and search for it in the source of I0.
2674 In the event that there's a match but the source/dest do not actually
2675 refer to the same memory, the worst that happens is we try some
2676 combinations that we wouldn't have otherwise. */
2677 if ((set0 = single_set (i0))
2678 /* Ensure the source of SET0 is a MEM, possibly buried inside
2680 && (GET_CODE (SET_SRC (set0)) == MEM
2681 || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2682 || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2683 && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2684 && (set3 = single_set (i3))
2685 /* Ensure the destination of SET3 is a MEM. */
2686 && GET_CODE (SET_DEST (set3)) == MEM
2687 /* Would it be better to extract the base address for the MEM
2688 in SET3 and look for that? I don't have cases where it matters
2689 but I could envision such cases. */
2690 && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2693 if (ngood < 2 && nshift < 2)
2697 /* Exit early if one of the insns involved can't be used for
2700 || (i1 && CALL_P (i1))
2701 || (i0 && CALL_P (i0))
2702 || cant_combine_insn_p (i3)
2703 || cant_combine_insn_p (i2)
2704 || (i1 && cant_combine_insn_p (i1))
2705 || (i0 && cant_combine_insn_p (i0))
2706 || likely_spilled_retval_p (i3))
2710 undobuf.other_insn = 0;
2712 /* Reset the hard register usage information. */
2713 CLEAR_HARD_REG_SET (newpat_used_regs);
2715 if (dump_file && (dump_flags & TDF_DETAILS))
2718 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2719 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2721 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2722 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2724 fprintf (dump_file, "\nTrying %d -> %d:\n",
2725 INSN_UID (i2), INSN_UID (i3));
2728 /* If multiple insns feed into one of I2 or I3, they can be in any
2729 order. To simplify the code below, reorder them in sequence. */
2730 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2732 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2734 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2737 added_links_insn = 0;
2739 /* First check for one important special case that the code below will
2740 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2741 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2742 we may be able to replace that destination with the destination of I3.
2743 This occurs in the common code where we compute both a quotient and
2744 remainder into a structure, in which case we want to do the computation
2745 directly into the structure to avoid register-register copies.
2747 Note that this case handles both multiple sets in I2 and also cases
2748 where I2 has a number of CLOBBERs inside the PARALLEL.
2750 We make very conservative checks below and only try to handle the
2751 most common cases of this. For example, we only handle the case
2752 where I2 and I3 are adjacent to avoid making difficult register
2755 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2756 && REG_P (SET_SRC (PATTERN (i3)))
2757 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2758 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2759 && GET_CODE (PATTERN (i2)) == PARALLEL
2760 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2761 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2762 below would need to check what is inside (and reg_overlap_mentioned_p
2763 doesn't support those codes anyway). Don't allow those destinations;
2764 the resulting insn isn't likely to be recognized anyway. */
2765 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2766 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2767 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2768 SET_DEST (PATTERN (i3)))
2769 && next_active_insn (i2) == i3)
2771 rtx p2 = PATTERN (i2);
2773 /* Make sure that the destination of I3,
2774 which we are going to substitute into one output of I2,
2775 is not used within another output of I2. We must avoid making this:
2776 (parallel [(set (mem (reg 69)) ...)
2777 (set (reg 69) ...)])
2778 which is not well-defined as to order of actions.
2779 (Besides, reload can't handle output reloads for this.)
2781 The problem can also happen if the dest of I3 is a memory ref,
2782 if another dest in I2 is an indirect memory ref. */
2783 for (i = 0; i < XVECLEN (p2, 0); i++)
2784 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2785 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2786 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2787 SET_DEST (XVECEXP (p2, 0, i))))
2790 /* Make sure this PARALLEL is not an asm. We do not allow combining
2791 that usually (see can_combine_p), so do not here either. */
2792 for (i = 0; i < XVECLEN (p2, 0); i++)
2793 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2794 && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2797 if (i == XVECLEN (p2, 0))
2798 for (i = 0; i < XVECLEN (p2, 0); i++)
2799 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2800 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2805 subst_low_luid = DF_INSN_LUID (i2);
2807 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2808 i2src = SET_SRC (XVECEXP (p2, 0, i));
2809 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2810 i2dest_killed = dead_or_set_p (i2, i2dest);
2812 /* Replace the dest in I2 with our dest and make the resulting
2813 insn the new pattern for I3. Then skip to where we validate
2814 the pattern. Everything was set up above. */
2815 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2817 i3_subst_into_i2 = 1;
2818 goto validate_replacement;
2822 /* If I2 is setting a pseudo to a constant and I3 is setting some
2823 sub-part of it to another constant, merge them by making a new
2826 && (temp_expr = single_set (i2)) != 0
2827 && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2828 && GET_CODE (PATTERN (i3)) == SET
2829 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2830 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2832 rtx dest = SET_DEST (PATTERN (i3));
2836 if (GET_CODE (dest) == ZERO_EXTRACT)
2838 if (CONST_INT_P (XEXP (dest, 1))
2839 && CONST_INT_P (XEXP (dest, 2)))
2841 width = INTVAL (XEXP (dest, 1));
2842 offset = INTVAL (XEXP (dest, 2));
2843 dest = XEXP (dest, 0);
2844 if (BITS_BIG_ENDIAN)
2845 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2850 if (GET_CODE (dest) == STRICT_LOW_PART)
2851 dest = XEXP (dest, 0);
2852 width = GET_MODE_PRECISION (GET_MODE (dest));
2858 /* If this is the low part, we're done. */
2859 if (subreg_lowpart_p (dest))
2861 /* Handle the case where inner is twice the size of outer. */
2862 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr)))
2863 == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2864 offset += GET_MODE_PRECISION (GET_MODE (dest));
2865 /* Otherwise give up for now. */
2872 rtx inner = SET_SRC (PATTERN (i3));
2873 rtx outer = SET_SRC (temp_expr);
2876 = wi::insert (std::make_pair (outer, GET_MODE (SET_DEST (temp_expr))),
2877 std::make_pair (inner, GET_MODE (dest)),
2882 subst_low_luid = DF_INSN_LUID (i2);
2883 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2884 i2dest = SET_DEST (temp_expr);
2885 i2dest_killed = dead_or_set_p (i2, i2dest);
2887 /* Replace the source in I2 with the new constant and make the
2888 resulting insn the new pattern for I3. Then skip to where we
2889 validate the pattern. Everything was set up above. */
2890 SUBST (SET_SRC (temp_expr),
2891 immed_wide_int_const (o, GET_MODE (SET_DEST (temp_expr))));
2893 newpat = PATTERN (i2);
2895 /* The dest of I3 has been replaced with the dest of I2. */
2896 changed_i3_dest = 1;
2897 goto validate_replacement;
2901 /* If we have no I1 and I2 looks like:
2902 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2904 make up a dummy I1 that is
2907 (set (reg:CC X) (compare:CC Y (const_int 0)))
2909 (We can ignore any trailing CLOBBERs.)
2911 This undoes a previous combination and allows us to match a branch-and-
2914 if (!HAVE_cc0 && i1 == 0
2915 && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2916 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2918 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2919 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2920 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2921 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2922 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2923 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2925 /* We make I1 with the same INSN_UID as I2. This gives it
2926 the same DF_INSN_LUID for value tracking. Our fake I1 will
2927 never appear in the insn stream so giving it the same INSN_UID
2928 as I2 will not cause a problem. */
2930 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2931 XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2933 INSN_UID (i1) = INSN_UID (i2);
2935 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2936 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2937 SET_DEST (PATTERN (i1)));
2938 unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2939 SUBST_LINK (LOG_LINKS (i2),
2940 alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2943 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2944 make those two SETs separate I1 and I2 insns, and make an I0 that is
2946 if (!HAVE_cc0 && i0 == 0
2947 && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2948 && can_split_parallel_of_n_reg_sets (i2, 2)
2949 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2950 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2952 /* If there is no I1, there is no I0 either. */
2955 /* We make I1 with the same INSN_UID as I2. This gives it
2956 the same DF_INSN_LUID for value tracking. Our fake I1 will
2957 never appear in the insn stream so giving it the same INSN_UID
2958 as I2 will not cause a problem. */
2960 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2961 XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
2963 INSN_UID (i1) = INSN_UID (i2);
2965 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2968 /* Verify that I2 and I1 are valid for combining. */
2969 if (! can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src)
2970 || (i1 && ! can_combine_p (i1, i3, i0, NULL, i2, NULL,
2972 || (i0 && ! can_combine_p (i0, i3, NULL, NULL, i1, i2,
2979 /* Record whether I2DEST is used in I2SRC and similarly for the other
2980 cases. Knowing this will help in register status updating below. */
2981 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2982 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2983 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2984 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2985 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2986 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2987 i2dest_killed = dead_or_set_p (i2, i2dest);
2988 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2989 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2991 /* For the earlier insns, determine which of the subsequent ones they
2993 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2994 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2995 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2996 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2997 && reg_overlap_mentioned_p (i0dest, i2src))));
2999 /* Ensure that I3's pattern can be the destination of combines. */
3000 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3001 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3002 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3003 || (i1dest_in_i0src && !i0_feeds_i1_n)),
3010 /* See if any of the insns is a MULT operation. Unless one is, we will
3011 reject a combination that is, since it must be slower. Be conservative
3013 if (GET_CODE (i2src) == MULT
3014 || (i1 != 0 && GET_CODE (i1src) == MULT)
3015 || (i0 != 0 && GET_CODE (i0src) == MULT)
3016 || (GET_CODE (PATTERN (i3)) == SET
3017 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3020 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3021 We used to do this EXCEPT in one case: I3 has a post-inc in an
3022 output operand. However, that exception can give rise to insns like
3024 which is a famous insn on the PDP-11 where the value of r3 used as the
3025 source was model-dependent. Avoid this sort of thing. */
3028 if (!(GET_CODE (PATTERN (i3)) == SET
3029 && REG_P (SET_SRC (PATTERN (i3)))
3030 && MEM_P (SET_DEST (PATTERN (i3)))
3031 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3032 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3033 /* It's not the exception. */
3038 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3039 if (REG_NOTE_KIND (link) == REG_INC
3040 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3042 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3049 /* See if the SETs in I1 or I2 need to be kept around in the merged
3050 instruction: whenever the value set there is still needed past I3.
3051 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3053 For the SET in I1, we have two cases: if I1 and I2 independently feed
3054 into I3, the set in I1 needs to be kept around unless I1DEST dies
3055 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3056 in I1 needs to be kept around unless I1DEST dies or is set in either
3057 I2 or I3. The same considerations apply to I0. */
3059 added_sets_2 = !dead_or_set_p (i3, i2dest);
3062 added_sets_1 = !(dead_or_set_p (i3, i1dest)
3063 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3068 added_sets_0 = !(dead_or_set_p (i3, i0dest)
3069 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3070 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3071 && dead_or_set_p (i2, i0dest)));
3075 /* We are about to copy insns for the case where they need to be kept
3076 around. Check that they can be copied in the merged instruction. */
3078 if (targetm.cannot_copy_insn_p
3079 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3080 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3081 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3087 /* If the set in I2 needs to be kept around, we must make a copy of
3088 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3089 PATTERN (I2), we are only substituting for the original I1DEST, not into
3090 an already-substituted copy. This also prevents making self-referential
3091 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3096 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3097 i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3099 i2pat = copy_rtx (PATTERN (i2));
3104 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3105 i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3107 i1pat = copy_rtx (PATTERN (i1));
3112 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3113 i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3115 i0pat = copy_rtx (PATTERN (i0));
3120 /* Substitute in the latest insn for the regs set by the earlier ones. */
3122 maxreg = max_reg_num ();
3126 /* Many machines that don't use CC0 have insns that can both perform an
3127 arithmetic operation and set the condition code. These operations will
3128 be represented as a PARALLEL with the first element of the vector
3129 being a COMPARE of an arithmetic operation with the constant zero.
3130 The second element of the vector will set some pseudo to the result
3131 of the same arithmetic operation. If we simplify the COMPARE, we won't
3132 match such a pattern and so will generate an extra insn. Here we test
3133 for this case, where both the comparison and the operation result are
3134 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3135 I2SRC. Later we will make the PARALLEL that contains I2. */
3137 if (!HAVE_cc0 && i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3138 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3139 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3140 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3143 rtx *cc_use_loc = NULL;
3144 rtx_insn *cc_use_insn = NULL;
3145 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3146 machine_mode compare_mode, orig_compare_mode;
3147 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3149 newpat = PATTERN (i3);
3150 newpat_dest = SET_DEST (newpat);
3151 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3153 if (undobuf.other_insn == 0
3154 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3157 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3158 compare_code = simplify_compare_const (compare_code,
3159 GET_MODE (i2dest), op0, &op1);
3160 target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3163 /* Do the rest only if op1 is const0_rtx, which may be the
3164 result of simplification. */
3165 if (op1 == const0_rtx)
3167 /* If a single use of the CC is found, prepare to modify it
3168 when SELECT_CC_MODE returns a new CC-class mode, or when
3169 the above simplify_compare_const() returned a new comparison
3170 operator. undobuf.other_insn is assigned the CC use insn
3171 when modifying it. */
3174 #ifdef SELECT_CC_MODE
3175 machine_mode new_mode
3176 = SELECT_CC_MODE (compare_code, op0, op1);
3177 if (new_mode != orig_compare_mode
3178 && can_change_dest_mode (SET_DEST (newpat),
3179 added_sets_2, new_mode))
3181 unsigned int regno = REGNO (newpat_dest);
3182 compare_mode = new_mode;
3183 if (regno < FIRST_PSEUDO_REGISTER)
3184 newpat_dest = gen_rtx_REG (compare_mode, regno);
3187 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3188 newpat_dest = regno_reg_rtx[regno];
3192 /* Cases for modifying the CC-using comparison. */
3193 if (compare_code != orig_compare_code
3194 /* ??? Do we need to verify the zero rtx? */
3195 && XEXP (*cc_use_loc, 1) == const0_rtx)
3197 /* Replace cc_use_loc with entire new RTX. */
3199 gen_rtx_fmt_ee (compare_code, compare_mode,
3200 newpat_dest, const0_rtx));
3201 undobuf.other_insn = cc_use_insn;
3203 else if (compare_mode != orig_compare_mode)
3205 /* Just replace the CC reg with a new mode. */
3206 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3207 undobuf.other_insn = cc_use_insn;
3211 /* Now we modify the current newpat:
3212 First, SET_DEST(newpat) is updated if the CC mode has been
3213 altered. For targets without SELECT_CC_MODE, this should be
3215 if (compare_mode != orig_compare_mode)
3216 SUBST (SET_DEST (newpat), newpat_dest);
3217 /* This is always done to propagate i2src into newpat. */
3218 SUBST (SET_SRC (newpat),
3219 gen_rtx_COMPARE (compare_mode, op0, op1));
3220 /* Create new version of i2pat if needed; the below PARALLEL
3221 creation needs this to work correctly. */
3222 if (! rtx_equal_p (i2src, op0))
3223 i2pat = gen_rtx_SET (i2dest, op0);
3228 if (i2_is_used == 0)
3230 /* It is possible that the source of I2 or I1 may be performing
3231 an unneeded operation, such as a ZERO_EXTEND of something
3232 that is known to have the high part zero. Handle that case
3233 by letting subst look at the inner insns.
3235 Another way to do this would be to have a function that tries
3236 to simplify a single insn instead of merging two or more
3237 insns. We don't do this because of the potential of infinite
3238 loops and because of the potential extra memory required.
3239 However, doing it the way we are is a bit of a kludge and
3240 doesn't catch all cases.
3242 But only do this if -fexpensive-optimizations since it slows
3243 things down and doesn't usually win.
3245 This is not done in the COMPARE case above because the
3246 unmodified I2PAT is used in the PARALLEL and so a pattern
3247 with a modified I2SRC would not match. */
3249 if (flag_expensive_optimizations)
3251 /* Pass pc_rtx so no substitutions are done, just
3255 subst_low_luid = DF_INSN_LUID (i1);
3256 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3259 subst_low_luid = DF_INSN_LUID (i2);
3260 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3263 n_occurrences = 0; /* `subst' counts here */
3264 subst_low_luid = DF_INSN_LUID (i2);
3266 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3267 copy of I2SRC each time we substitute it, in order to avoid creating
3268 self-referential RTL when we will be substituting I1SRC for I1DEST
3269 later. Likewise if I0 feeds into I2, either directly or indirectly
3270 through I1, and I0DEST is in I0SRC. */
3271 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3272 (i1_feeds_i2_n && i1dest_in_i1src)
3273 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3274 && i0dest_in_i0src));
3277 /* Record whether I2's body now appears within I3's body. */
3278 i2_is_used = n_occurrences;
3281 /* If we already got a failure, don't try to do more. Otherwise, try to
3282 substitute I1 if we have it. */
3284 if (i1 && GET_CODE (newpat) != CLOBBER)
3286 /* Check that an autoincrement side-effect on I1 has not been lost.
3287 This happens if I1DEST is mentioned in I2 and dies there, and
3288 has disappeared from the new pattern. */
3289 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3291 && dead_or_set_p (i2, i1dest)
3292 && !reg_overlap_mentioned_p (i1dest, newpat))
3293 /* Before we can do this substitution, we must redo the test done
3294 above (see detailed comments there) that ensures I1DEST isn't
3295 mentioned in any SETs in NEWPAT that are field assignments. */
3296 || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3304 subst_low_luid = DF_INSN_LUID (i1);
3306 /* If the following substitution will modify I1SRC, make a copy of it
3307 for the case where it is substituted for I1DEST in I2PAT later. */
3308 if (added_sets_2 && i1_feeds_i2_n)
3309 i1src_copy = copy_rtx (i1src);
3311 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3312 copy of I1SRC each time we substitute it, in order to avoid creating
3313 self-referential RTL when we will be substituting I0SRC for I0DEST
3315 newpat = subst (newpat, i1dest, i1src, 0, 0,
3316 i0_feeds_i1_n && i0dest_in_i0src);
3319 /* Record whether I1's body now appears within I3's body. */
3320 i1_is_used = n_occurrences;
3323 /* Likewise for I0 if we have it. */
3325 if (i0 && GET_CODE (newpat) != CLOBBER)
3327 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3328 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3329 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3330 && !reg_overlap_mentioned_p (i0dest, newpat))
3331 || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3338 /* If the following substitution will modify I0SRC, make a copy of it
3339 for the case where it is substituted for I0DEST in I1PAT later. */
3340 if (added_sets_1 && i0_feeds_i1_n)
3341 i0src_copy = copy_rtx (i0src);
3342 /* And a copy for I0DEST in I2PAT substitution. */
3343 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3344 || (i0_feeds_i2_n)))
3345 i0src_copy2 = copy_rtx (i0src);
3348 subst_low_luid = DF_INSN_LUID (i0);
3349 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3353 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3354 to count all the ways that I2SRC and I1SRC can be used. */
3355 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3356 && i2_is_used + added_sets_2 > 1)
3357 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3358 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3360 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3361 && (n_occurrences + added_sets_0
3362 + (added_sets_1 && i0_feeds_i1_n)
3363 + (added_sets_2 && i0_feeds_i2_n)
3365 /* Fail if we tried to make a new register. */
3366 || max_reg_num () != maxreg
3367 /* Fail if we couldn't do something and have a CLOBBER. */
3368 || GET_CODE (newpat) == CLOBBER
3369 /* Fail if this new pattern is a MULT and we didn't have one before
3370 at the outer level. */
3371 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3378 /* If the actions of the earlier insns must be kept
3379 in addition to substituting them into the latest one,
3380 we must make a new PARALLEL for the latest insn
3381 to hold additional the SETs. */
3383 if (added_sets_0 || added_sets_1 || added_sets_2)
3385 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3388 if (GET_CODE (newpat) == PARALLEL)
3390 rtvec old = XVEC (newpat, 0);
3391 total_sets = XVECLEN (newpat, 0) + extra_sets;
3392 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3393 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3394 sizeof (old->elem[0]) * old->num_elem);
3399 total_sets = 1 + extra_sets;
3400 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3401 XVECEXP (newpat, 0, 0) = old;
3405 XVECEXP (newpat, 0, --total_sets) = i0pat;
3411 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3413 XVECEXP (newpat, 0, --total_sets) = t;
3419 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3420 i0_feeds_i1_n && i0dest_in_i0src);
3421 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3422 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3424 XVECEXP (newpat, 0, --total_sets) = t;
3428 validate_replacement:
3430 /* Note which hard regs this insn has as inputs. */
3431 mark_used_regs_combine (newpat);
3433 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3434 consider splitting this pattern, we might need these clobbers. */
3435 if (i1 && GET_CODE (newpat) == PARALLEL
3436 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3438 int len = XVECLEN (newpat, 0);
3440 newpat_vec_with_clobbers = rtvec_alloc (len);
3441 for (i = 0; i < len; i++)
3442 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3445 /* We have recognized nothing yet. */
3446 insn_code_number = -1;
3448 /* See if this is a PARALLEL of two SETs where one SET's destination is
3449 a register that is unused and this isn't marked as an instruction that
3450 might trap in an EH region. In that case, we just need the other SET.
3451 We prefer this over the PARALLEL.
3453 This can occur when simplifying a divmod insn. We *must* test for this
3454 case here because the code below that splits two independent SETs doesn't
3455 handle this case correctly when it updates the register status.
3457 It's pointless doing this if we originally had two sets, one from
3458 i3, and one from i2. Combining then splitting the parallel results
3459 in the original i2 again plus an invalid insn (which we delete).
3460 The net effect is only to move instructions around, which makes
3461 debug info less accurate. */
3463 if (!(added_sets_2 && i1 == 0)
3464 && is_parallel_of_n_reg_sets (newpat, 2)
3465 && asm_noperands (newpat) < 0)
3467 rtx set0 = XVECEXP (newpat, 0, 0);
3468 rtx set1 = XVECEXP (newpat, 0, 1);
3469 rtx oldpat = newpat;
3471 if (((REG_P (SET_DEST (set1))
3472 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3473 || (GET_CODE (SET_DEST (set1)) == SUBREG
3474 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3475 && insn_nothrow_p (i3)
3476 && !side_effects_p (SET_SRC (set1)))
3479 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3482 else if (((REG_P (SET_DEST (set0))
3483 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3484 || (GET_CODE (SET_DEST (set0)) == SUBREG
3485 && find_reg_note (i3, REG_UNUSED,
3486 SUBREG_REG (SET_DEST (set0)))))
3487 && insn_nothrow_p (i3)
3488 && !side_effects_p (SET_SRC (set0)))
3491 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3493 if (insn_code_number >= 0)
3494 changed_i3_dest = 1;
3497 if (insn_code_number < 0)
3501 /* Is the result of combination a valid instruction? */
3502 if (insn_code_number < 0)
3503 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3505 /* If we were combining three insns and the result is a simple SET
3506 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3507 insns. There are two ways to do this. It can be split using a
3508 machine-specific method (like when you have an addition of a large
3509 constant) or by combine in the function find_split_point. */
3511 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3512 && asm_noperands (newpat) < 0)
3514 rtx parallel, *split;
3515 rtx_insn *m_split_insn;
3517 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3518 use I2DEST as a scratch register will help. In the latter case,
3519 convert I2DEST to the mode of the source of NEWPAT if we can. */
3521 m_split_insn = combine_split_insns (newpat, i3);
3523 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3524 inputs of NEWPAT. */
3526 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3527 possible to try that as a scratch reg. This would require adding
3528 more code to make it work though. */
3530 if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3532 machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3534 /* First try to split using the original register as a
3535 scratch register. */
3536 parallel = gen_rtx_PARALLEL (VOIDmode,
3537 gen_rtvec (2, newpat,
3538 gen_rtx_CLOBBER (VOIDmode,
3540 m_split_insn = combine_split_insns (parallel, i3);
3542 /* If that didn't work, try changing the mode of I2DEST if
3544 if (m_split_insn == 0
3545 && new_mode != GET_MODE (i2dest)
3546 && new_mode != VOIDmode
3547 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3549 machine_mode old_mode = GET_MODE (i2dest);
3552 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3553 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3556 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3557 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3560 parallel = (gen_rtx_PARALLEL
3562 gen_rtvec (2, newpat,
3563 gen_rtx_CLOBBER (VOIDmode,
3565 m_split_insn = combine_split_insns (parallel, i3);
3567 if (m_split_insn == 0
3568 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3572 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3573 buf = undobuf.undos;
3574 undobuf.undos = buf->next;
3575 buf->next = undobuf.frees;
3576 undobuf.frees = buf;
3580 i2scratch = m_split_insn != 0;
3583 /* If recog_for_combine has discarded clobbers, try to use them
3584 again for the split. */
3585 if (m_split_insn == 0 && newpat_vec_with_clobbers)
3587 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3588 m_split_insn = combine_split_insns (parallel, i3);
3591 if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3593 rtx m_split_pat = PATTERN (m_split_insn);
3594 insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3595 if (insn_code_number >= 0)
3596 newpat = m_split_pat;
3598 else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3599 && (next_nonnote_nondebug_insn (i2) == i3
3600 || ! use_crosses_set_p (PATTERN (m_split_insn), DF_INSN_LUID (i2))))
3603 rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3604 newi2pat = PATTERN (m_split_insn);
3606 i3set = single_set (NEXT_INSN (m_split_insn));
3607 i2set = single_set (m_split_insn);
3609 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3611 /* If I2 or I3 has multiple SETs, we won't know how to track
3612 register status, so don't use these insns. If I2's destination
3613 is used between I2 and I3, we also can't use these insns. */
3615 if (i2_code_number >= 0 && i2set && i3set
3616 && (next_nonnote_nondebug_insn (i2) == i3
3617 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3618 insn_code_number = recog_for_combine (&newi3pat, i3,
3620 if (insn_code_number >= 0)
3623 /* It is possible that both insns now set the destination of I3.
3624 If so, we must show an extra use of it. */
3626 if (insn_code_number >= 0)
3628 rtx new_i3_dest = SET_DEST (i3set);
3629 rtx new_i2_dest = SET_DEST (i2set);
3631 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3632 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3633 || GET_CODE (new_i3_dest) == SUBREG)
3634 new_i3_dest = XEXP (new_i3_dest, 0);
3636 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3637 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3638 || GET_CODE (new_i2_dest) == SUBREG)
3639 new_i2_dest = XEXP (new_i2_dest, 0);
3641 if (REG_P (new_i3_dest)
3642 && REG_P (new_i2_dest)
3643 && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3644 && REGNO (new_i2_dest) < reg_n_sets_max)
3645 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3649 /* If we can split it and use I2DEST, go ahead and see if that
3650 helps things be recognized. Verify that none of the registers
3651 are set between I2 and I3. */
3652 if (insn_code_number < 0
3653 && (split = find_split_point (&newpat, i3, false)) != 0
3654 && (!HAVE_cc0 || REG_P (i2dest))
3655 /* We need I2DEST in the proper mode. If it is a hard register
3656 or the only use of a pseudo, we can change its mode.
3657 Make sure we don't change a hard register to have a mode that
3658 isn't valid for it, or change the number of registers. */
3659 && (GET_MODE (*split) == GET_MODE (i2dest)
3660 || GET_MODE (*split) == VOIDmode
3661 || can_change_dest_mode (i2dest, added_sets_2,
3663 && (next_nonnote_nondebug_insn (i2) == i3
3664 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3665 /* We can't overwrite I2DEST if its value is still used by
3667 && ! reg_referenced_p (i2dest, newpat))
3669 rtx newdest = i2dest;
3670 enum rtx_code split_code = GET_CODE (*split);
3671 machine_mode split_mode = GET_MODE (*split);
3672 bool subst_done = false;
3673 newi2pat = NULL_RTX;
3677 /* *SPLIT may be part of I2SRC, so make sure we have the
3678 original expression around for later debug processing.
3679 We should not need I2SRC any more in other cases. */
3680 if (MAY_HAVE_DEBUG_INSNS)
3681 i2src = copy_rtx (i2src);
3685 /* Get NEWDEST as a register in the proper mode. We have already
3686 validated that we can do this. */
3687 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3689 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3690 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3693 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3694 newdest = regno_reg_rtx[REGNO (i2dest)];
3698 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3699 an ASHIFT. This can occur if it was inside a PLUS and hence
3700 appeared to be a memory address. This is a kludge. */
3701 if (split_code == MULT
3702 && CONST_INT_P (XEXP (*split, 1))
3703 && INTVAL (XEXP (*split, 1)) > 0
3704 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3706 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3707 XEXP (*split, 0), GEN_INT (i)));
3708 /* Update split_code because we may not have a multiply
3710 split_code = GET_CODE (*split);
3713 /* Similarly for (plus (mult FOO (const_int pow2))). */
3714 if (split_code == PLUS
3715 && GET_CODE (XEXP (*split, 0)) == MULT
3716 && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3717 && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3718 && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3720 rtx nsplit = XEXP (*split, 0);
3721 SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3722 XEXP (nsplit, 0), GEN_INT (i)));
3723 /* Update split_code because we may not have a multiply
3725 split_code = GET_CODE (*split);
3728 #ifdef INSN_SCHEDULING
3729 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3730 be written as a ZERO_EXTEND. */
3731 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3733 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3734 what it really is. */
3735 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3737 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3738 SUBREG_REG (*split)));
3740 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3741 SUBREG_REG (*split)));
3745 /* Attempt to split binary operators using arithmetic identities. */
3746 if (BINARY_P (SET_SRC (newpat))
3747 && split_mode == GET_MODE (SET_SRC (newpat))
3748 && ! side_effects_p (SET_SRC (newpat)))
3750 rtx setsrc = SET_SRC (newpat);
3751 machine_mode mode = GET_MODE (setsrc);
3752 enum rtx_code code = GET_CODE (setsrc);
3753 rtx src_op0 = XEXP (setsrc, 0);
3754 rtx src_op1 = XEXP (setsrc, 1);
3756 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3757 if (rtx_equal_p (src_op0, src_op1))
3759 newi2pat = gen_rtx_SET (newdest, src_op0);
3760 SUBST (XEXP (setsrc, 0), newdest);
3761 SUBST (XEXP (setsrc, 1), newdest);
3764 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3765 else if ((code == PLUS || code == MULT)
3766 && GET_CODE (src_op0) == code
3767 && GET_CODE (XEXP (src_op0, 0)) == code
3768 && (INTEGRAL_MODE_P (mode)
3769 || (FLOAT_MODE_P (mode)
3770 && flag_unsafe_math_optimizations)))
3772 rtx p = XEXP (XEXP (src_op0, 0), 0);
3773 rtx q = XEXP (XEXP (src_op0, 0), 1);
3774 rtx r = XEXP (src_op0, 1);
3777 /* Split both "((X op Y) op X) op Y" and
3778 "((X op Y) op Y) op X" as "T op T" where T is
3780 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3781 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3783 newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3784 SUBST (XEXP (setsrc, 0), newdest);
3785 SUBST (XEXP (setsrc, 1), newdest);
3788 /* Split "((X op X) op Y) op Y)" as "T op T" where
3790 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3792 rtx tmp = simplify_gen_binary (code, mode, p, r);
3793 newi2pat = gen_rtx_SET (newdest, tmp);
3794 SUBST (XEXP (setsrc, 0), newdest);
3795 SUBST (XEXP (setsrc, 1), newdest);
3803 newi2pat = gen_rtx_SET (newdest, *split);
3804 SUBST (*split, newdest);
3807 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3809 /* recog_for_combine might have added CLOBBERs to newi2pat.
3810 Make sure NEWPAT does not depend on the clobbered regs. */
3811 if (GET_CODE (newi2pat) == PARALLEL)
3812 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3813 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3815 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3816 if (reg_overlap_mentioned_p (reg, newpat))
3823 /* If the split point was a MULT and we didn't have one before,
3824 don't use one now. */
3825 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3826 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3830 /* Check for a case where we loaded from memory in a narrow mode and
3831 then sign extended it, but we need both registers. In that case,
3832 we have a PARALLEL with both loads from the same memory location.
3833 We can split this into a load from memory followed by a register-register
3834 copy. This saves at least one insn, more if register allocation can
3837 We cannot do this if the destination of the first assignment is a
3838 condition code register or cc0. We eliminate this case by making sure
3839 the SET_DEST and SET_SRC have the same mode.
3841 We cannot do this if the destination of the second assignment is
3842 a register that we have already assumed is zero-extended. Similarly
3843 for a SUBREG of such a register. */
3845 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3846 && GET_CODE (newpat) == PARALLEL
3847 && XVECLEN (newpat, 0) == 2
3848 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3849 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3850 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3851 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3852 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3853 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3854 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3855 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3857 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3858 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3859 && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3861 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3862 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
3863 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
3864 && (reg_stat[REGNO (temp_expr)].nonzero_bits
3865 != GET_MODE_MASK (word_mode))))
3866 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3867 && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3869 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3870 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
3871 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
3872 && (reg_stat[REGNO (temp_expr)].nonzero_bits
3873 != GET_MODE_MASK (word_mode)))))
3874 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3875 SET_SRC (XVECEXP (newpat, 0, 1)))
3876 && ! find_reg_note (i3, REG_UNUSED,
3877 SET_DEST (XVECEXP (newpat, 0, 0))))
3881 newi2pat = XVECEXP (newpat, 0, 0);
3882 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3883 newpat = XVECEXP (newpat, 0, 1);
3884 SUBST (SET_SRC (newpat),
3885 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3886 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3888 if (i2_code_number >= 0)
3889 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3891 if (insn_code_number >= 0)
3895 /* Similarly, check for a case where we have a PARALLEL of two independent
3896 SETs but we started with three insns. In this case, we can do the sets
3897 as two separate insns. This case occurs when some SET allows two
3898 other insns to combine, but the destination of that SET is still live.
3900 Also do this if we started with two insns and (at least) one of the
3901 resulting sets is a noop; this noop will be deleted later. */
3903 else if (insn_code_number < 0 && asm_noperands (newpat) < 0
3904 && GET_CODE (newpat) == PARALLEL
3905 && XVECLEN (newpat, 0) == 2
3906 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3907 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3908 && (i1 || set_noop_p (XVECEXP (newpat, 0, 0))
3909 || set_noop_p (XVECEXP (newpat, 0, 1)))
3910 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3911 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3912 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3913 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3914 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3915 XVECEXP (newpat, 0, 0))
3916 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3917 XVECEXP (newpat, 0, 1))
3918 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3919 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3921 rtx set0 = XVECEXP (newpat, 0, 0);
3922 rtx set1 = XVECEXP (newpat, 0, 1);
3924 /* Normally, it doesn't matter which of the two is done first,
3925 but the one that references cc0 can't be the second, and
3926 one which uses any regs/memory set in between i2 and i3 can't
3927 be first. The PARALLEL might also have been pre-existing in i3,
3928 so we need to make sure that we won't wrongly hoist a SET to i2
3929 that would conflict with a death note present in there. */
3930 if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3931 && !(REG_P (SET_DEST (set1))
3932 && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3933 && !(GET_CODE (SET_DEST (set1)) == SUBREG
3934 && find_reg_note (i2, REG_DEAD,
3935 SUBREG_REG (SET_DEST (set1))))
3936 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set0))
3937 /* If I3 is a jump, ensure that set0 is a jump so that
3938 we do not create invalid RTL. */
3939 && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
3945 else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3946 && !(REG_P (SET_DEST (set0))
3947 && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3948 && !(GET_CODE (SET_DEST (set0)) == SUBREG
3949 && find_reg_note (i2, REG_DEAD,
3950 SUBREG_REG (SET_DEST (set0))))
3951 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set1))
3952 /* If I3 is a jump, ensure that set1 is a jump so that
3953 we do not create invalid RTL. */
3954 && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
3966 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3968 if (i2_code_number >= 0)
3970 /* recog_for_combine might have added CLOBBERs to newi2pat.
3971 Make sure NEWPAT does not depend on the clobbered regs. */
3972 if (GET_CODE (newi2pat) == PARALLEL)
3974 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3975 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3977 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3978 if (reg_overlap_mentioned_p (reg, newpat))
3986 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3990 /* If it still isn't recognized, fail and change things back the way they
3992 if ((insn_code_number < 0
3993 /* Is the result a reasonable ASM_OPERANDS? */
3994 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4000 /* If we had to change another insn, make sure it is valid also. */
4001 if (undobuf.other_insn)
4003 CLEAR_HARD_REG_SET (newpat_used_regs);
4005 other_pat = PATTERN (undobuf.other_insn);
4006 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4009 if (other_code_number < 0 && ! check_asm_operands (other_pat))
4016 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4017 they are adjacent to each other or not. */
4020 rtx_insn *p = prev_nonnote_insn (i3);
4021 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
4022 && sets_cc0_p (newi2pat))
4029 /* Only allow this combination if insn_rtx_costs reports that the
4030 replacement instructions are cheaper than the originals. */
4031 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
4037 if (MAY_HAVE_DEBUG_INSNS)
4041 for (undo = undobuf.undos; undo; undo = undo->next)
4042 if (undo->kind == UNDO_MODE)
4044 rtx reg = *undo->where.r;
4045 machine_mode new_mode = GET_MODE (reg);
4046 machine_mode old_mode = undo->old_contents.m;
4048 /* Temporarily revert mode back. */
4049 adjust_reg_mode (reg, old_mode);
4051 if (reg == i2dest && i2scratch)
4053 /* If we used i2dest as a scratch register with a
4054 different mode, substitute it for the original
4055 i2src while its original mode is temporarily
4056 restored, and then clear i2scratch so that we don't
4057 do it again later. */
4058 propagate_for_debug (i2, last_combined_insn, reg, i2src,
4061 /* Put back the new mode. */
4062 adjust_reg_mode (reg, new_mode);
4066 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4067 rtx_insn *first, *last;
4072 last = last_combined_insn;
4077 last = undobuf.other_insn;
4079 if (DF_INSN_LUID (last)
4080 < DF_INSN_LUID (last_combined_insn))
4081 last = last_combined_insn;
4084 /* We're dealing with a reg that changed mode but not
4085 meaning, so we want to turn it into a subreg for
4086 the new mode. However, because of REG sharing and
4087 because its mode had already changed, we have to do
4088 it in two steps. First, replace any debug uses of
4089 reg, with its original mode temporarily restored,
4090 with this copy we have created; then, replace the
4091 copy with the SUBREG of the original shared reg,
4092 once again changed to the new mode. */
4093 propagate_for_debug (first, last, reg, tempreg,
4095 adjust_reg_mode (reg, new_mode);
4096 propagate_for_debug (first, last, tempreg,
4097 lowpart_subreg (old_mode, reg, new_mode),
4103 /* If we will be able to accept this, we have made a
4104 change to the destination of I3. This requires us to
4105 do a few adjustments. */
4107 if (changed_i3_dest)
4109 PATTERN (i3) = newpat;
4110 adjust_for_new_dest (i3);
4113 /* We now know that we can do this combination. Merge the insns and
4114 update the status of registers and LOG_LINKS. */
4116 if (undobuf.other_insn)
4120 PATTERN (undobuf.other_insn) = other_pat;
4122 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4123 ensure that they are still valid. Then add any non-duplicate
4124 notes added by recog_for_combine. */
4125 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4127 next = XEXP (note, 1);
4129 if ((REG_NOTE_KIND (note) == REG_DEAD
4130 && !reg_referenced_p (XEXP (note, 0),
4131 PATTERN (undobuf.other_insn)))
4132 ||(REG_NOTE_KIND (note) == REG_UNUSED
4133 && !reg_set_p (XEXP (note, 0),
4134 PATTERN (undobuf.other_insn))))
4135 remove_note (undobuf.other_insn, note);
4138 distribute_notes (new_other_notes, undobuf.other_insn,
4139 undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4146 struct insn_link *link;
4149 /* I3 now uses what used to be its destination and which is now
4150 I2's destination. This requires us to do a few adjustments. */
4151 PATTERN (i3) = newpat;
4152 adjust_for_new_dest (i3);
4154 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4157 However, some later insn might be using I2's dest and have
4158 a LOG_LINK pointing at I3. We must remove this link.
4159 The simplest way to remove the link is to point it at I1,
4160 which we know will be a NOTE. */
4162 /* newi2pat is usually a SET here; however, recog_for_combine might
4163 have added some clobbers. */
4164 if (GET_CODE (newi2pat) == PARALLEL)
4165 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4167 ni2dest = SET_DEST (newi2pat);
4169 for (insn = NEXT_INSN (i3);
4170 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4171 || insn != BB_HEAD (this_basic_block->next_bb));
4172 insn = NEXT_INSN (insn))
4174 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4176 FOR_EACH_LOG_LINK (link, insn)
4177 if (link->insn == i3)
4186 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4187 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4190 /* Compute which registers we expect to eliminate. newi2pat may be setting
4191 either i3dest or i2dest, so we must check it. */
4192 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4193 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4196 /* For i1, we need to compute both local elimination and global
4197 elimination information with respect to newi2pat because i1dest
4198 may be the same as i3dest, in which case newi2pat may be setting
4199 i1dest. Global information is used when distributing REG_DEAD
4200 note for i2 and i3, in which case it does matter if newi2pat sets
4203 Local information is used when distributing REG_DEAD note for i1,
4204 in which case it doesn't matter if newi2pat sets i1dest or not.
4205 See PR62151, if we have four insns combination:
4207 i1: r1 <- i1src (using r0)
4209 i2: r0 <- i2src (using r1)
4210 i3: r3 <- i3src (using r0)
4212 From i1's point of view, r0 is eliminated, no matter if it is set
4213 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4214 should be discarded.
4216 Note local information only affects cases in forms like "I1->I2->I3",
4217 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4218 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4220 rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4223 rtx elim_i1 = (local_elim_i1 == 0
4224 || (newi2pat && reg_set_p (i1dest, newi2pat))
4226 /* Same case as i1. */
4227 rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4229 rtx elim_i0 = (local_elim_i0 == 0
4230 || (newi2pat && reg_set_p (i0dest, newi2pat))
4233 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4235 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4236 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4238 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4240 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4242 /* Ensure that we do not have something that should not be shared but
4243 occurs multiple times in the new insns. Check this by first
4244 resetting all the `used' flags and then copying anything is shared. */
4246 reset_used_flags (i3notes);
4247 reset_used_flags (i2notes);
4248 reset_used_flags (i1notes);
4249 reset_used_flags (i0notes);
4250 reset_used_flags (newpat);
4251 reset_used_flags (newi2pat);
4252 if (undobuf.other_insn)
4253 reset_used_flags (PATTERN (undobuf.other_insn));
4255 i3notes = copy_rtx_if_shared (i3notes);
4256 i2notes = copy_rtx_if_shared (i2notes);
4257 i1notes = copy_rtx_if_shared (i1notes);
4258 i0notes = copy_rtx_if_shared (i0notes);
4259 newpat = copy_rtx_if_shared (newpat);
4260 newi2pat = copy_rtx_if_shared (newi2pat);
4261 if (undobuf.other_insn)
4262 reset_used_flags (PATTERN (undobuf.other_insn));
4264 INSN_CODE (i3) = insn_code_number;
4265 PATTERN (i3) = newpat;
4267 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4269 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4271 reset_used_flags (call_usage);
4272 call_usage = copy_rtx (call_usage);
4276 /* I2SRC must still be meaningful at this point. Some splitting
4277 operations can invalidate I2SRC, but those operations do not
4280 replace_rtx (call_usage, i2dest, i2src);
4284 replace_rtx (call_usage, i1dest, i1src);
4286 replace_rtx (call_usage, i0dest, i0src);
4288 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4291 if (undobuf.other_insn)
4292 INSN_CODE (undobuf.other_insn) = other_code_number;
4294 /* We had one special case above where I2 had more than one set and
4295 we replaced a destination of one of those sets with the destination
4296 of I3. In that case, we have to update LOG_LINKS of insns later
4297 in this basic block. Note that this (expensive) case is rare.
4299 Also, in this case, we must pretend that all REG_NOTEs for I2
4300 actually came from I3, so that REG_UNUSED notes from I2 will be
4301 properly handled. */
4303 if (i3_subst_into_i2)
4305 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4306 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4307 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4308 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4309 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4310 && ! find_reg_note (i2, REG_UNUSED,
4311 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4312 for (temp_insn = NEXT_INSN (i2);
4314 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4315 || BB_HEAD (this_basic_block) != temp_insn);
4316 temp_insn = NEXT_INSN (temp_insn))
4317 if (temp_insn != i3 && INSN_P (temp_insn))
4318 FOR_EACH_LOG_LINK (link, temp_insn)
4319 if (link->insn == i2)
4325 while (XEXP (link, 1))
4326 link = XEXP (link, 1);
4327 XEXP (link, 1) = i2notes;
4334 LOG_LINKS (i3) = NULL;
4336 LOG_LINKS (i2) = NULL;
4341 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4342 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4344 INSN_CODE (i2) = i2_code_number;
4345 PATTERN (i2) = newi2pat;
4349 if (MAY_HAVE_DEBUG_INSNS && i2src)
4350 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4352 SET_INSN_DELETED (i2);
4357 LOG_LINKS (i1) = NULL;
4359 if (MAY_HAVE_DEBUG_INSNS)
4360 propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4362 SET_INSN_DELETED (i1);
4367 LOG_LINKS (i0) = NULL;
4369 if (MAY_HAVE_DEBUG_INSNS)
4370 propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4372 SET_INSN_DELETED (i0);
4375 /* Get death notes for everything that is now used in either I3 or
4376 I2 and used to die in a previous insn. If we built two new
4377 patterns, move from I1 to I2 then I2 to I3 so that we get the
4378 proper movement on registers that I2 modifies. */
4381 from_luid = DF_INSN_LUID (i0);
4383 from_luid = DF_INSN_LUID (i1);
4385 from_luid = DF_INSN_LUID (i2);
4387 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4388 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4390 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4392 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4393 elim_i2, elim_i1, elim_i0);
4395 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4396 elim_i2, elim_i1, elim_i0);
4398 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4399 elim_i2, local_elim_i1, local_elim_i0);
4401 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4402 elim_i2, elim_i1, local_elim_i0);
4404 distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4405 elim_i2, elim_i1, elim_i0);
4407 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4408 know these are REG_UNUSED and want them to go to the desired insn,
4409 so we always pass it as i3. */
4411 if (newi2pat && new_i2_notes)
4412 distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4416 distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4419 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4420 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4421 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4422 in that case, it might delete I2. Similarly for I2 and I1.
4423 Show an additional death due to the REG_DEAD note we make here. If
4424 we discard it in distribute_notes, we will decrement it again. */
4428 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4429 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4430 distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4433 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4434 elim_i2, elim_i1, elim_i0);
4437 if (i2dest_in_i2src)
4439 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4440 if (newi2pat && reg_set_p (i2dest, newi2pat))
4441 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4442 NULL_RTX, NULL_RTX);
4444 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4445 NULL_RTX, NULL_RTX, NULL_RTX);
4448 if (i1dest_in_i1src)
4450 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4451 if (newi2pat && reg_set_p (i1dest, newi2pat))
4452 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4453 NULL_RTX, NULL_RTX);
4455 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4456 NULL_RTX, NULL_RTX, NULL_RTX);
4459 if (i0dest_in_i0src)
4461 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4462 if (newi2pat && reg_set_p (i0dest, newi2pat))
4463 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4464 NULL_RTX, NULL_RTX);
4466 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4467 NULL_RTX, NULL_RTX, NULL_RTX);
4470 distribute_links (i3links);
4471 distribute_links (i2links);
4472 distribute_links (i1links);
4473 distribute_links (i0links);
4477 struct insn_link *link;
4478 rtx_insn *i2_insn = 0;
4479 rtx i2_val = 0, set;
4481 /* The insn that used to set this register doesn't exist, and
4482 this life of the register may not exist either. See if one of
4483 I3's links points to an insn that sets I2DEST. If it does,
4484 that is now the last known value for I2DEST. If we don't update
4485 this and I2 set the register to a value that depended on its old
4486 contents, we will get confused. If this insn is used, thing
4487 will be set correctly in combine_instructions. */
4488 FOR_EACH_LOG_LINK (link, i3)
4489 if ((set = single_set (link->insn)) != 0
4490 && rtx_equal_p (i2dest, SET_DEST (set)))
4491 i2_insn = link->insn, i2_val = SET_SRC (set);
4493 record_value_for_reg (i2dest, i2_insn, i2_val);
4495 /* If the reg formerly set in I2 died only once and that was in I3,
4496 zero its use count so it won't make `reload' do any work. */
4498 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4499 && ! i2dest_in_i2src
4500 && REGNO (i2dest) < reg_n_sets_max)
4501 INC_REG_N_SETS (REGNO (i2dest), -1);
4504 if (i1 && REG_P (i1dest))
4506 struct insn_link *link;
4507 rtx_insn *i1_insn = 0;
4508 rtx i1_val = 0, set;
4510 FOR_EACH_LOG_LINK (link, i3)
4511 if ((set = single_set (link->insn)) != 0
4512 && rtx_equal_p (i1dest, SET_DEST (set)))
4513 i1_insn = link->insn, i1_val = SET_SRC (set);
4515 record_value_for_reg (i1dest, i1_insn, i1_val);
4518 && ! i1dest_in_i1src
4519 && REGNO (i1dest) < reg_n_sets_max)
4520 INC_REG_N_SETS (REGNO (i1dest), -1);
4523 if (i0 && REG_P (i0dest))
4525 struct insn_link *link;
4526 rtx_insn *i0_insn = 0;
4527 rtx i0_val = 0, set;
4529 FOR_EACH_LOG_LINK (link, i3)
4530 if ((set = single_set (link->insn)) != 0
4531 && rtx_equal_p (i0dest, SET_DEST (set)))
4532 i0_insn = link->insn, i0_val = SET_SRC (set);
4534 record_value_for_reg (i0dest, i0_insn, i0_val);
4537 && ! i0dest_in_i0src
4538 && REGNO (i0dest) < reg_n_sets_max)
4539 INC_REG_N_SETS (REGNO (i0dest), -1);
4542 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4543 been made to this insn. The order is important, because newi2pat
4544 can affect nonzero_bits of newpat. */
4546 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4547 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4550 if (undobuf.other_insn != NULL_RTX)
4554 fprintf (dump_file, "modifying other_insn ");
4555 dump_insn_slim (dump_file, undobuf.other_insn);
4557 df_insn_rescan (undobuf.other_insn);
4560 if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4564 fprintf (dump_file, "modifying insn i0 ");
4565 dump_insn_slim (dump_file, i0);
4567 df_insn_rescan (i0);
4570 if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4574 fprintf (dump_file, "modifying insn i1 ");
4575 dump_insn_slim (dump_file, i1);
4577 df_insn_rescan (i1);
4580 if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4584 fprintf (dump_file, "modifying insn i2 ");
4585 dump_insn_slim (dump_file, i2);
4587 df_insn_rescan (i2);
4590 if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4594 fprintf (dump_file, "modifying insn i3 ");
4595 dump_insn_slim (dump_file, i3);
4597 df_insn_rescan (i3);
4600 /* Set new_direct_jump_p if a new return or simple jump instruction
4601 has been created. Adjust the CFG accordingly. */
4602 if (returnjump_p (i3) || any_uncondjump_p (i3))
4604 *new_direct_jump_p = 1;
4605 mark_jump_label (PATTERN (i3), i3, 0);
4606 update_cfg_for_uncondjump (i3);
4609 if (undobuf.other_insn != NULL_RTX
4610 && (returnjump_p (undobuf.other_insn)
4611 || any_uncondjump_p (undobuf.other_insn)))
4613 *new_direct_jump_p = 1;
4614 update_cfg_for_uncondjump (undobuf.other_insn);
4617 /* A noop might also need cleaning up of CFG, if it comes from the
4618 simplification of a jump. */
4620 && GET_CODE (newpat) == SET
4621 && SET_SRC (newpat) == pc_rtx
4622 && SET_DEST (newpat) == pc_rtx)
4624 *new_direct_jump_p = 1;
4625 update_cfg_for_uncondjump (i3);
4628 if (undobuf.other_insn != NULL_RTX
4629 && JUMP_P (undobuf.other_insn)
4630 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4631 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4632 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4634 *new_direct_jump_p = 1;
4635 update_cfg_for_uncondjump (undobuf.other_insn);
4638 combine_successes++;
4641 if (added_links_insn
4642 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4643 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4644 return added_links_insn;
4646 return newi2pat ? i2 : i3;
4649 /* Get a marker for undoing to the current state. */
4652 get_undo_marker (void)
4654 return undobuf.undos;
4657 /* Undo the modifications up to the marker. */
4660 undo_to_marker (void *marker)
4662 struct undo *undo, *next;
4664 for (undo = undobuf.undos; undo != marker; undo = next)
4672 *undo->where.r = undo->old_contents.r;
4675 *undo->where.i = undo->old_contents.i;
4678 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4681 *undo->where.l = undo->old_contents.l;
4687 undo->next = undobuf.frees;
4688 undobuf.frees = undo;
4691 undobuf.undos = (struct undo *) marker;
4694 /* Undo all the modifications recorded in undobuf. */
4702 /* We've committed to accepting the changes we made. Move all
4703 of the undos to the free list. */
4708 struct undo *undo, *next;
4710 for (undo = undobuf.undos; undo; undo = next)
4713 undo->next = undobuf.frees;
4714 undobuf.frees = undo;
4719 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4720 where we have an arithmetic expression and return that point. LOC will
4723 try_combine will call this function to see if an insn can be split into
4727 find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4730 enum rtx_code code = GET_CODE (x);
4732 unsigned HOST_WIDE_INT len = 0;
4733 HOST_WIDE_INT pos = 0;
4735 rtx inner = NULL_RTX;
4737 /* First special-case some codes. */
4741 #ifdef INSN_SCHEDULING
4742 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4744 if (MEM_P (SUBREG_REG (x)))
4747 return find_split_point (&SUBREG_REG (x), insn, false);
4750 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4751 using LO_SUM and HIGH. */
4752 if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4753 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4755 machine_mode address_mode = get_address_mode (x);
4758 gen_rtx_LO_SUM (address_mode,
4759 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4761 return &XEXP (XEXP (x, 0), 0);
4764 /* If we have a PLUS whose second operand is a constant and the
4765 address is not valid, perhaps will can split it up using
4766 the machine-specific way to split large constants. We use
4767 the first pseudo-reg (one of the virtual regs) as a placeholder;
4768 it will not remain in the result. */
4769 if (GET_CODE (XEXP (x, 0)) == PLUS
4770 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4771 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4772 MEM_ADDR_SPACE (x)))
4774 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4775 rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4778 /* This should have produced two insns, each of which sets our
4779 placeholder. If the source of the second is a valid address,
4780 we can make put both sources together and make a split point
4784 && NEXT_INSN (seq) != NULL_RTX
4785 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4786 && NONJUMP_INSN_P (seq)
4787 && GET_CODE (PATTERN (seq)) == SET
4788 && SET_DEST (PATTERN (seq)) == reg
4789 && ! reg_mentioned_p (reg,
4790 SET_SRC (PATTERN (seq)))
4791 && NONJUMP_INSN_P (NEXT_INSN (seq))
4792 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4793 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4794 && memory_address_addr_space_p
4795 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4796 MEM_ADDR_SPACE (x)))
4798 rtx src1 = SET_SRC (PATTERN (seq));
4799 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4801 /* Replace the placeholder in SRC2 with SRC1. If we can
4802 find where in SRC2 it was placed, that can become our
4803 split point and we can replace this address with SRC2.
4804 Just try two obvious places. */
4806 src2 = replace_rtx (src2, reg, src1);
4808 if (XEXP (src2, 0) == src1)
4809 split = &XEXP (src2, 0);
4810 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4811 && XEXP (XEXP (src2, 0), 0) == src1)
4812 split = &XEXP (XEXP (src2, 0), 0);
4816 SUBST (XEXP (x, 0), src2);
4821 /* If that didn't work, perhaps the first operand is complex and
4822 needs to be computed separately, so make a split point there.
4823 This will occur on machines that just support REG + CONST
4824 and have a constant moved through some previous computation. */
4826 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4827 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4828 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4829 return &XEXP (XEXP (x, 0), 0);
4832 /* If we have a PLUS whose first operand is complex, try computing it
4833 separately by making a split there. */
4834 if (GET_CODE (XEXP (x, 0)) == PLUS
4835 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4837 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4838 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4839 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4840 return &XEXP (XEXP (x, 0), 0);
4844 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4845 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4846 we need to put the operand into a register. So split at that
4849 if (SET_DEST (x) == cc0_rtx
4850 && GET_CODE (SET_SRC (x)) != COMPARE
4851 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4852 && !OBJECT_P (SET_SRC (x))
4853 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4854 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4855 return &SET_SRC (x);
4857 /* See if we can split SET_SRC as it stands. */
4858 split = find_split_point (&SET_SRC (x), insn, true);
4859 if (split && split != &SET_SRC (x))
4862 /* See if we can split SET_DEST as it stands. */
4863 split = find_split_point (&SET_DEST (x), insn, false);
4864 if (split && split != &SET_DEST (x))
4867 /* See if this is a bitfield assignment with everything constant. If
4868 so, this is an IOR of an AND, so split it into that. */
4869 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4870 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4871 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4872 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4873 && CONST_INT_P (SET_SRC (x))
4874 && ((INTVAL (XEXP (SET_DEST (x), 1))
4875 + INTVAL (XEXP (SET_DEST (x), 2)))
4876 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4877 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4879 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4880 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4881 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4882 rtx dest = XEXP (SET_DEST (x), 0);
4883 machine_mode mode = GET_MODE (dest);
4884 unsigned HOST_WIDE_INT mask
4885 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4888 if (BITS_BIG_ENDIAN)
4889 pos = GET_MODE_PRECISION (mode) - len - pos;
4891 or_mask = gen_int_mode (src << pos, mode);
4894 simplify_gen_binary (IOR, mode, dest, or_mask));
4897 rtx negmask = gen_int_mode (~(mask << pos), mode);
4899 simplify_gen_binary (IOR, mode,
4900 simplify_gen_binary (AND, mode,
4905 SUBST (SET_DEST (x), dest);
4907 split = find_split_point (&SET_SRC (x), insn, true);
4908 if (split && split != &SET_SRC (x))
4912 /* Otherwise, see if this is an operation that we can split into two.
4913 If so, try to split that. */
4914 code = GET_CODE (SET_SRC (x));
4919 /* If we are AND'ing with a large constant that is only a single
4920 bit and the result is only being used in a context where we
4921 need to know if it is zero or nonzero, replace it with a bit
4922 extraction. This will avoid the large constant, which might
4923 have taken more than one insn to make. If the constant were
4924 not a valid argument to the AND but took only one insn to make,
4925 this is no worse, but if it took more than one insn, it will
4928 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4929 && REG_P (XEXP (SET_SRC (x), 0))
4930 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4931 && REG_P (SET_DEST (x))
4932 && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
4933 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4934 && XEXP (*split, 0) == SET_DEST (x)
4935 && XEXP (*split, 1) == const0_rtx)
4937 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4938 XEXP (SET_SRC (x), 0),
4939 pos, NULL_RTX, 1, 1, 0, 0);
4940 if (extraction != 0)
4942 SUBST (SET_SRC (x), extraction);
4943 return find_split_point (loc, insn, false);
4949 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4950 is known to be on, this can be converted into a NEG of a shift. */
4951 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4952 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4953 && 1 <= (pos = exact_log2
4954 (nonzero_bits (XEXP (SET_SRC (x), 0),
4955 GET_MODE (XEXP (SET_SRC (x), 0))))))
4957 machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4961 gen_rtx_LSHIFTRT (mode,
4962 XEXP (SET_SRC (x), 0),
4965 split = find_split_point (&SET_SRC (x), insn, true);
4966 if (split && split != &SET_SRC (x))
4972 inner = XEXP (SET_SRC (x), 0);
4974 /* We can't optimize if either mode is a partial integer
4975 mode as we don't know how many bits are significant
4977 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4978 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4982 len = GET_MODE_PRECISION (GET_MODE (inner));
4988 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4989 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4991 inner = XEXP (SET_SRC (x), 0);
4992 len = INTVAL (XEXP (SET_SRC (x), 1));
4993 pos = INTVAL (XEXP (SET_SRC (x), 2));
4995 if (BITS_BIG_ENDIAN)
4996 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4997 unsignedp = (code == ZERO_EXTRACT);
5006 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
5008 machine_mode mode = GET_MODE (SET_SRC (x));
5010 /* For unsigned, we have a choice of a shift followed by an
5011 AND or two shifts. Use two shifts for field sizes where the
5012 constant might be too large. We assume here that we can
5013 always at least get 8-bit constants in an AND insn, which is
5014 true for every current RISC. */
5016 if (unsignedp && len <= 8)
5018 unsigned HOST_WIDE_INT mask
5019 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
5023 (mode, gen_lowpart (mode, inner),
5025 gen_int_mode (mask, mode)));
5027 split = find_split_point (&SET_SRC (x), insn, true);
5028 if (split && split != &SET_SRC (x))
5035 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5036 gen_rtx_ASHIFT (mode,
5037 gen_lowpart (mode, inner),
5038 GEN_INT (GET_MODE_PRECISION (mode)
5040 GEN_INT (GET_MODE_PRECISION (mode) - len)));
5042 split = find_split_point (&SET_SRC (x), insn, true);
5043 if (split && split != &SET_SRC (x))
5048 /* See if this is a simple operation with a constant as the second
5049 operand. It might be that this constant is out of range and hence
5050 could be used as a split point. */
5051 if (BINARY_P (SET_SRC (x))
5052 && CONSTANT_P (XEXP (SET_SRC (x), 1))
5053 && (OBJECT_P (XEXP (SET_SRC (x), 0))
5054 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5055 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5056 return &XEXP (SET_SRC (x), 1);
5058 /* Finally, see if this is a simple operation with its first operand
5059 not in a register. The operation might require this operand in a
5060 register, so return it as a split point. We can always do this
5061 because if the first operand were another operation, we would have
5062 already found it as a split point. */
5063 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5064 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5065 return &XEXP (SET_SRC (x), 0);
5071 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5072 it is better to write this as (not (ior A B)) so we can split it.
5073 Similarly for IOR. */
5074 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5077 gen_rtx_NOT (GET_MODE (x),
5078 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5080 XEXP (XEXP (x, 0), 0),
5081 XEXP (XEXP (x, 1), 0))));
5082 return find_split_point (loc, insn, set_src);
5085 /* Many RISC machines have a large set of logical insns. If the
5086 second operand is a NOT, put it first so we will try to split the
5087 other operand first. */
5088 if (GET_CODE (XEXP (x, 1)) == NOT)
5090 rtx tem = XEXP (x, 0);
5091 SUBST (XEXP (x, 0), XEXP (x, 1));
5092 SUBST (XEXP (x, 1), tem);
5098 /* Canonicalization can produce (minus A (mult B C)), where C is a
5099 constant. It may be better to try splitting (plus (mult B -C) A)
5100 instead if this isn't a multiply by a power of two. */
5101 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5102 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5103 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
5105 machine_mode mode = GET_MODE (x);
5106 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5107 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5108 SUBST (*loc, gen_rtx_PLUS (mode,
5110 XEXP (XEXP (x, 1), 0),
5111 gen_int_mode (other_int,
5114 return find_split_point (loc, insn, set_src);
5117 /* Split at a multiply-accumulate instruction. However if this is
5118 the SET_SRC, we likely do not have such an instruction and it's
5119 worthless to try this split. */
5121 && (GET_CODE (XEXP (x, 0)) == MULT
5122 || (GET_CODE (XEXP (x, 0)) == ASHIFT
5123 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5130 /* Otherwise, select our actions depending on our rtx class. */
5131 switch (GET_RTX_CLASS (code))
5133 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5135 split = find_split_point (&XEXP (x, 2), insn, false);
5140 case RTX_COMM_ARITH:
5142 case RTX_COMM_COMPARE:
5143 split = find_split_point (&XEXP (x, 1), insn, false);
5148 /* Some machines have (and (shift ...) ...) insns. If X is not
5149 an AND, but XEXP (X, 0) is, use it as our split point. */
5150 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5151 return &XEXP (x, 0);
5153 split = find_split_point (&XEXP (x, 0), insn, false);
5159 /* Otherwise, we don't have a split point. */
5164 /* Throughout X, replace FROM with TO, and return the result.
5165 The result is TO if X is FROM;
5166 otherwise the result is X, but its contents may have been modified.
5167 If they were modified, a record was made in undobuf so that
5168 undo_all will (among other things) return X to its original state.
5170 If the number of changes necessary is too much to record to undo,
5171 the excess changes are not made, so the result is invalid.
5172 The changes already made can still be undone.
5173 undobuf.num_undo is incremented for such changes, so by testing that
5174 the caller can tell whether the result is valid.
5176 `n_occurrences' is incremented each time FROM is replaced.
5178 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5180 IN_COND is nonzero if we are at the top level of a condition.
5182 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5183 by copying if `n_occurrences' is nonzero. */
5186 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5188 enum rtx_code code = GET_CODE (x);
5189 machine_mode op0_mode = VOIDmode;
5194 /* Two expressions are equal if they are identical copies of a shared
5195 RTX or if they are both registers with the same register number
5198 #define COMBINE_RTX_EQUAL_P(X,Y) \
5200 || (REG_P (X) && REG_P (Y) \
5201 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5203 /* Do not substitute into clobbers of regs -- this will never result in
5205 if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5208 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5211 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5214 /* If X and FROM are the same register but different modes, they
5215 will not have been seen as equal above. However, the log links code
5216 will make a LOG_LINKS entry for that case. If we do nothing, we
5217 will try to rerecognize our original insn and, when it succeeds,
5218 we will delete the feeding insn, which is incorrect.
5220 So force this insn not to match in this (rare) case. */
5221 if (! in_dest && code == REG && REG_P (from)
5222 && reg_overlap_mentioned_p (x, from))
5223 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5225 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5226 of which may contain things that can be combined. */
5227 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5230 /* It is possible to have a subexpression appear twice in the insn.
5231 Suppose that FROM is a register that appears within TO.
5232 Then, after that subexpression has been scanned once by `subst',
5233 the second time it is scanned, TO may be found. If we were
5234 to scan TO here, we would find FROM within it and create a
5235 self-referent rtl structure which is completely wrong. */
5236 if (COMBINE_RTX_EQUAL_P (x, to))
5239 /* Parallel asm_operands need special attention because all of the
5240 inputs are shared across the arms. Furthermore, unsharing the
5241 rtl results in recognition failures. Failure to handle this case
5242 specially can result in circular rtl.
5244 Solve this by doing a normal pass across the first entry of the
5245 parallel, and only processing the SET_DESTs of the subsequent
5248 if (code == PARALLEL
5249 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5250 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5252 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5254 /* If this substitution failed, this whole thing fails. */
5255 if (GET_CODE (new_rtx) == CLOBBER
5256 && XEXP (new_rtx, 0) == const0_rtx)
5259 SUBST (XVECEXP (x, 0, 0), new_rtx);
5261 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5263 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5266 && GET_CODE (dest) != CC0
5267 && GET_CODE (dest) != PC)
5269 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5271 /* If this substitution failed, this whole thing fails. */
5272 if (GET_CODE (new_rtx) == CLOBBER
5273 && XEXP (new_rtx, 0) == const0_rtx)
5276 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5282 len = GET_RTX_LENGTH (code);
5283 fmt = GET_RTX_FORMAT (code);
5285 /* We don't need to process a SET_DEST that is a register, CC0,
5286 or PC, so set up to skip this common case. All other cases
5287 where we want to suppress replacing something inside a
5288 SET_SRC are handled via the IN_DEST operand. */
5290 && (REG_P (SET_DEST (x))
5291 || GET_CODE (SET_DEST (x)) == CC0
5292 || GET_CODE (SET_DEST (x)) == PC))
5295 /* Trying to simplify the operands of a widening MULT is not likely
5296 to create RTL matching a machine insn. */
5298 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5299 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5300 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5301 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5302 && REG_P (XEXP (XEXP (x, 0), 0))
5303 && REG_P (XEXP (XEXP (x, 1), 0))
5308 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5311 op0_mode = GET_MODE (XEXP (x, 0));
5313 for (i = 0; i < len; i++)
5318 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5320 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5322 new_rtx = (unique_copy && n_occurrences
5323 ? copy_rtx (to) : to);
5328 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5331 /* If this substitution failed, this whole thing
5333 if (GET_CODE (new_rtx) == CLOBBER
5334 && XEXP (new_rtx, 0) == const0_rtx)
5338 SUBST (XVECEXP (x, i, j), new_rtx);
5341 else if (fmt[i] == 'e')
5343 /* If this is a register being set, ignore it. */
5344 new_rtx = XEXP (x, i);
5347 && (((code == SUBREG || code == ZERO_EXTRACT)
5349 || code == STRICT_LOW_PART))
5352 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5354 /* In general, don't install a subreg involving two
5355 modes not tieable. It can worsen register
5356 allocation, and can even make invalid reload
5357 insns, since the reg inside may need to be copied
5358 from in the outside mode, and that may be invalid
5359 if it is an fp reg copied in integer mode.
5361 We allow two exceptions to this: It is valid if
5362 it is inside another SUBREG and the mode of that
5363 SUBREG and the mode of the inside of TO is
5364 tieable and it is valid if X is a SET that copies
5367 if (GET_CODE (to) == SUBREG
5368 && ! MODES_TIEABLE_P (GET_MODE (to),
5369 GET_MODE (SUBREG_REG (to)))
5370 && ! (code == SUBREG
5371 && MODES_TIEABLE_P (GET_MODE (x),
5372 GET_MODE (SUBREG_REG (to))))
5376 && XEXP (x, 0) == cc0_rtx))))
5377 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5381 && REGNO (to) < FIRST_PSEUDO_REGISTER
5382 && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5385 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5387 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5391 /* If we are in a SET_DEST, suppress most cases unless we
5392 have gone inside a MEM, in which case we want to
5393 simplify the address. We assume here that things that
5394 are actually part of the destination have their inner
5395 parts in the first expression. This is true for SUBREG,
5396 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5397 things aside from REG and MEM that should appear in a
5399 new_rtx = subst (XEXP (x, i), from, to,
5401 && (code == SUBREG || code == STRICT_LOW_PART
5402 || code == ZERO_EXTRACT))
5405 code == IF_THEN_ELSE && i == 0,
5408 /* If we found that we will have to reject this combination,
5409 indicate that by returning the CLOBBER ourselves, rather than
5410 an expression containing it. This will speed things up as
5411 well as prevent accidents where two CLOBBERs are considered
5412 to be equal, thus producing an incorrect simplification. */
5414 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5417 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5419 machine_mode mode = GET_MODE (x);
5421 x = simplify_subreg (GET_MODE (x), new_rtx,
5422 GET_MODE (SUBREG_REG (x)),
5425 x = gen_rtx_CLOBBER (mode, const0_rtx);
5427 else if (CONST_SCALAR_INT_P (new_rtx)
5428 && GET_CODE (x) == ZERO_EXTEND)
5430 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5431 new_rtx, GET_MODE (XEXP (x, 0)));
5435 SUBST (XEXP (x, i), new_rtx);
5440 /* Check if we are loading something from the constant pool via float
5441 extension; in this case we would undo compress_float_constant
5442 optimization and degenerate constant load to an immediate value. */
5443 if (GET_CODE (x) == FLOAT_EXTEND
5444 && MEM_P (XEXP (x, 0))
5445 && MEM_READONLY_P (XEXP (x, 0)))
5447 rtx tmp = avoid_constant_pool_reference (x);
5452 /* Try to simplify X. If the simplification changed the code, it is likely
5453 that further simplification will help, so loop, but limit the number
5454 of repetitions that will be performed. */
5456 for (i = 0; i < 4; i++)
5458 /* If X is sufficiently simple, don't bother trying to do anything
5460 if (code != CONST_INT && code != REG && code != CLOBBER)
5461 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5463 if (GET_CODE (x) == code)
5466 code = GET_CODE (x);
5468 /* We no longer know the original mode of operand 0 since we
5469 have changed the form of X) */
5470 op0_mode = VOIDmode;
5476 /* Simplify X, a piece of RTL. We just operate on the expression at the
5477 outer level; call `subst' to simplify recursively. Return the new
5480 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5481 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5485 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
5488 enum rtx_code code = GET_CODE (x);
5489 machine_mode mode = GET_MODE (x);
5493 /* If this is a commutative operation, put a constant last and a complex
5494 expression first. We don't need to do this for comparisons here. */
5495 if (COMMUTATIVE_ARITH_P (x)
5496 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5499 SUBST (XEXP (x, 0), XEXP (x, 1));
5500 SUBST (XEXP (x, 1), temp);
5503 /* Try to fold this expression in case we have constants that weren't
5506 switch (GET_RTX_CLASS (code))
5509 if (op0_mode == VOIDmode)
5510 op0_mode = GET_MODE (XEXP (x, 0));
5511 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5514 case RTX_COMM_COMPARE:
5516 machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5517 if (cmp_mode == VOIDmode)
5519 cmp_mode = GET_MODE (XEXP (x, 1));
5520 if (cmp_mode == VOIDmode)
5521 cmp_mode = op0_mode;
5523 temp = simplify_relational_operation (code, mode, cmp_mode,
5524 XEXP (x, 0), XEXP (x, 1));
5527 case RTX_COMM_ARITH:
5529 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5531 case RTX_BITFIELD_OPS:
5533 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5534 XEXP (x, 1), XEXP (x, 2));
5543 code = GET_CODE (temp);
5544 op0_mode = VOIDmode;
5545 mode = GET_MODE (temp);
5548 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5549 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5550 things. Check for cases where both arms are testing the same
5553 Don't do anything if all operands are very simple. */
5556 && ((!OBJECT_P (XEXP (x, 0))
5557 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5558 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5559 || (!OBJECT_P (XEXP (x, 1))
5560 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5561 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5563 && (!OBJECT_P (XEXP (x, 0))
5564 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5565 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5567 rtx cond, true_rtx, false_rtx;
5569 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5571 /* If everything is a comparison, what we have is highly unlikely
5572 to be simpler, so don't use it. */
5573 && ! (COMPARISON_P (x)
5574 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5576 rtx cop1 = const0_rtx;
5577 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5579 if (cond_code == NE && COMPARISON_P (cond))
5582 /* Simplify the alternative arms; this may collapse the true and
5583 false arms to store-flag values. Be careful to use copy_rtx
5584 here since true_rtx or false_rtx might share RTL with x as a
5585 result of the if_then_else_cond call above. */
5586 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5587 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5589 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5590 is unlikely to be simpler. */
5591 if (general_operand (true_rtx, VOIDmode)
5592 && general_operand (false_rtx, VOIDmode))
5594 enum rtx_code reversed;
5596 /* Restarting if we generate a store-flag expression will cause
5597 us to loop. Just drop through in this case. */
5599 /* If the result values are STORE_FLAG_VALUE and zero, we can
5600 just make the comparison operation. */
5601 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5602 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5604 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5605 && ((reversed = reversed_comparison_code_parts
5606 (cond_code, cond, cop1, NULL))
5608 x = simplify_gen_relational (reversed, mode, VOIDmode,
5611 /* Likewise, we can make the negate of a comparison operation
5612 if the result values are - STORE_FLAG_VALUE and zero. */
5613 else if (CONST_INT_P (true_rtx)
5614 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5615 && false_rtx == const0_rtx)
5616 x = simplify_gen_unary (NEG, mode,
5617 simplify_gen_relational (cond_code,
5621 else if (CONST_INT_P (false_rtx)
5622 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5623 && true_rtx == const0_rtx
5624 && ((reversed = reversed_comparison_code_parts
5625 (cond_code, cond, cop1, NULL))
5627 x = simplify_gen_unary (NEG, mode,
5628 simplify_gen_relational (reversed,
5633 return gen_rtx_IF_THEN_ELSE (mode,
5634 simplify_gen_relational (cond_code,
5639 true_rtx, false_rtx);
5641 code = GET_CODE (x);
5642 op0_mode = VOIDmode;
5647 /* First see if we can apply the inverse distributive law. */
5648 if (code == PLUS || code == MINUS
5649 || code == AND || code == IOR || code == XOR)
5651 x = apply_distributive_law (x);
5652 code = GET_CODE (x);
5653 op0_mode = VOIDmode;
5656 /* If CODE is an associative operation not otherwise handled, see if we
5657 can associate some operands. This can win if they are constants or
5658 if they are logically related (i.e. (a & b) & a). */
5659 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5660 || code == AND || code == IOR || code == XOR
5661 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5662 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5663 || (flag_associative_math && FLOAT_MODE_P (mode))))
5665 if (GET_CODE (XEXP (x, 0)) == code)
5667 rtx other = XEXP (XEXP (x, 0), 0);
5668 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5669 rtx inner_op1 = XEXP (x, 1);
5672 /* Make sure we pass the constant operand if any as the second
5673 one if this is a commutative operation. */
5674 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5675 std::swap (inner_op0, inner_op1);
5676 inner = simplify_binary_operation (code == MINUS ? PLUS
5677 : code == DIV ? MULT
5679 mode, inner_op0, inner_op1);
5681 /* For commutative operations, try the other pair if that one
5683 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5685 other = XEXP (XEXP (x, 0), 1);
5686 inner = simplify_binary_operation (code, mode,
5687 XEXP (XEXP (x, 0), 0),
5692 return simplify_gen_binary (code, mode, other, inner);
5696 /* A little bit of algebraic simplification here. */
5700 /* Ensure that our address has any ASHIFTs converted to MULT in case
5701 address-recognizing predicates are called later. */
5702 temp = make_compound_operation (XEXP (x, 0), MEM);
5703 SUBST (XEXP (x, 0), temp);
5707 if (op0_mode == VOIDmode)
5708 op0_mode = GET_MODE (SUBREG_REG (x));
5710 /* See if this can be moved to simplify_subreg. */
5711 if (CONSTANT_P (SUBREG_REG (x))
5712 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5713 /* Don't call gen_lowpart if the inner mode
5714 is VOIDmode and we cannot simplify it, as SUBREG without
5715 inner mode is invalid. */
5716 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5717 || gen_lowpart_common (mode, SUBREG_REG (x))))
5718 return gen_lowpart (mode, SUBREG_REG (x));
5720 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5724 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5729 /* If op is known to have all lower bits zero, the result is zero. */
5731 && SCALAR_INT_MODE_P (mode)
5732 && SCALAR_INT_MODE_P (op0_mode)
5733 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5734 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5735 && HWI_COMPUTABLE_MODE_P (op0_mode)
5736 && (nonzero_bits (SUBREG_REG (x), op0_mode)
5737 & GET_MODE_MASK (mode)) == 0)
5738 return CONST0_RTX (mode);
5741 /* Don't change the mode of the MEM if that would change the meaning
5743 if (MEM_P (SUBREG_REG (x))
5744 && (MEM_VOLATILE_P (SUBREG_REG (x))
5745 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5746 MEM_ADDR_SPACE (SUBREG_REG (x)))))
5747 return gen_rtx_CLOBBER (mode, const0_rtx);
5749 /* Note that we cannot do any narrowing for non-constants since
5750 we might have been counting on using the fact that some bits were
5751 zero. We now do this in the SET. */
5756 temp = expand_compound_operation (XEXP (x, 0));
5758 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5759 replaced by (lshiftrt X C). This will convert
5760 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5762 if (GET_CODE (temp) == ASHIFTRT
5763 && CONST_INT_P (XEXP (temp, 1))
5764 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5765 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5766 INTVAL (XEXP (temp, 1)));
5768 /* If X has only a single bit that might be nonzero, say, bit I, convert
5769 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5770 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5771 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5772 or a SUBREG of one since we'd be making the expression more
5773 complex if it was just a register. */
5776 && ! (GET_CODE (temp) == SUBREG
5777 && REG_P (SUBREG_REG (temp)))
5778 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5780 rtx temp1 = simplify_shift_const
5781 (NULL_RTX, ASHIFTRT, mode,
5782 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5783 GET_MODE_PRECISION (mode) - 1 - i),
5784 GET_MODE_PRECISION (mode) - 1 - i);
5786 /* If all we did was surround TEMP with the two shifts, we
5787 haven't improved anything, so don't use it. Otherwise,
5788 we are better off with TEMP1. */
5789 if (GET_CODE (temp1) != ASHIFTRT
5790 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5791 || XEXP (XEXP (temp1, 0), 0) != temp)
5797 /* We can't handle truncation to a partial integer mode here
5798 because we don't know the real bitsize of the partial
5800 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5803 if (HWI_COMPUTABLE_MODE_P (mode))
5805 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5806 GET_MODE_MASK (mode), 0));
5808 /* We can truncate a constant value and return it. */
5809 if (CONST_INT_P (XEXP (x, 0)))
5810 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5812 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5813 whose value is a comparison can be replaced with a subreg if
5814 STORE_FLAG_VALUE permits. */
5815 if (HWI_COMPUTABLE_MODE_P (mode)
5816 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5817 && (temp = get_last_value (XEXP (x, 0)))
5818 && COMPARISON_P (temp))
5819 return gen_lowpart (mode, XEXP (x, 0));
5823 /* (const (const X)) can become (const X). Do it this way rather than
5824 returning the inner CONST since CONST can be shared with a
5826 if (GET_CODE (XEXP (x, 0)) == CONST)
5827 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5831 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5832 can add in an offset. find_split_point will split this address up
5833 again if it doesn't match. */
5834 if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
5835 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5840 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5841 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5842 bit-field and can be replaced by either a sign_extend or a
5843 sign_extract. The `and' may be a zero_extend and the two
5844 <c>, -<c> constants may be reversed. */
5845 if (GET_CODE (XEXP (x, 0)) == XOR
5846 && CONST_INT_P (XEXP (x, 1))
5847 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5848 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5849 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5850 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5851 && HWI_COMPUTABLE_MODE_P (mode)
5852 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5853 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5854 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5855 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5856 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5857 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5858 == (unsigned int) i + 1))))
5859 return simplify_shift_const
5860 (NULL_RTX, ASHIFTRT, mode,
5861 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5862 XEXP (XEXP (XEXP (x, 0), 0), 0),
5863 GET_MODE_PRECISION (mode) - (i + 1)),
5864 GET_MODE_PRECISION (mode) - (i + 1));
5866 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5867 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5868 the bitsize of the mode - 1. This allows simplification of
5869 "a = (b & 8) == 0;" */
5870 if (XEXP (x, 1) == constm1_rtx
5871 && !REG_P (XEXP (x, 0))
5872 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5873 && REG_P (SUBREG_REG (XEXP (x, 0))))
5874 && nonzero_bits (XEXP (x, 0), mode) == 1)
5875 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5876 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5877 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5878 GET_MODE_PRECISION (mode) - 1),
5879 GET_MODE_PRECISION (mode) - 1);
5881 /* If we are adding two things that have no bits in common, convert
5882 the addition into an IOR. This will often be further simplified,
5883 for example in cases like ((a & 1) + (a & 2)), which can
5886 if (HWI_COMPUTABLE_MODE_P (mode)
5887 && (nonzero_bits (XEXP (x, 0), mode)
5888 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5890 /* Try to simplify the expression further. */
5891 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5892 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5894 /* If we could, great. If not, do not go ahead with the IOR
5895 replacement, since PLUS appears in many special purpose
5896 address arithmetic instructions. */
5897 if (GET_CODE (temp) != CLOBBER
5898 && (GET_CODE (temp) != IOR
5899 || ((XEXP (temp, 0) != XEXP (x, 0)
5900 || XEXP (temp, 1) != XEXP (x, 1))
5901 && (XEXP (temp, 0) != XEXP (x, 1)
5902 || XEXP (temp, 1) != XEXP (x, 0)))))
5906 /* Canonicalize x + x into x << 1. */
5907 if (GET_MODE_CLASS (mode) == MODE_INT
5908 && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
5909 && !side_effects_p (XEXP (x, 0)))
5910 return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
5915 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5916 (and <foo> (const_int pow2-1)) */
5917 if (GET_CODE (XEXP (x, 1)) == AND
5918 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5919 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5920 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5921 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5922 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5926 /* If we have (mult (plus A B) C), apply the distributive law and then
5927 the inverse distributive law to see if things simplify. This
5928 occurs mostly in addresses, often when unrolling loops. */
5930 if (GET_CODE (XEXP (x, 0)) == PLUS)
5932 rtx result = distribute_and_simplify_rtx (x, 0);
5937 /* Try simplify a*(b/c) as (a*b)/c. */
5938 if (FLOAT_MODE_P (mode) && flag_associative_math
5939 && GET_CODE (XEXP (x, 0)) == DIV)
5941 rtx tem = simplify_binary_operation (MULT, mode,
5942 XEXP (XEXP (x, 0), 0),
5945 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5950 /* If this is a divide by a power of two, treat it as a shift if
5951 its first operand is a shift. */
5952 if (CONST_INT_P (XEXP (x, 1))
5953 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5954 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5955 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5956 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5957 || GET_CODE (XEXP (x, 0)) == ROTATE
5958 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5959 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5963 case GT: case GTU: case GE: case GEU:
5964 case LT: case LTU: case LE: case LEU:
5965 case UNEQ: case LTGT:
5966 case UNGT: case UNGE:
5967 case UNLT: case UNLE:
5968 case UNORDERED: case ORDERED:
5969 /* If the first operand is a condition code, we can't do anything
5971 if (GET_CODE (XEXP (x, 0)) == COMPARE
5972 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5973 && ! CC0_P (XEXP (x, 0))))
5975 rtx op0 = XEXP (x, 0);
5976 rtx op1 = XEXP (x, 1);
5977 enum rtx_code new_code;
5979 if (GET_CODE (op0) == COMPARE)
5980 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5982 /* Simplify our comparison, if possible. */
5983 new_code = simplify_comparison (code, &op0, &op1);
5985 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5986 if only the low-order bit is possibly nonzero in X (such as when
5987 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5988 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5989 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5992 Remove any ZERO_EXTRACT we made when thinking this was a
5993 comparison. It may now be simpler to use, e.g., an AND. If a
5994 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5995 the call to make_compound_operation in the SET case.
5997 Don't apply these optimizations if the caller would
5998 prefer a comparison rather than a value.
5999 E.g., for the condition in an IF_THEN_ELSE most targets need
6000 an explicit comparison. */
6005 else if (STORE_FLAG_VALUE == 1
6006 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
6007 && op1 == const0_rtx
6008 && mode == GET_MODE (op0)
6009 && nonzero_bits (op0, mode) == 1)
6010 return gen_lowpart (mode,
6011 expand_compound_operation (op0));
6013 else if (STORE_FLAG_VALUE == 1
6014 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
6015 && op1 == const0_rtx
6016 && mode == GET_MODE (op0)
6017 && (num_sign_bit_copies (op0, mode)
6018 == GET_MODE_PRECISION (mode)))
6020 op0 = expand_compound_operation (op0);
6021 return simplify_gen_unary (NEG, mode,
6022 gen_lowpart (mode, op0),
6026 else if (STORE_FLAG_VALUE == 1
6027 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
6028 && op1 == const0_rtx
6029 && mode == GET_MODE (op0)
6030 && nonzero_bits (op0, mode) == 1)
6032 op0 = expand_compound_operation (op0);
6033 return simplify_gen_binary (XOR, mode,
6034 gen_lowpart (mode, op0),
6038 else if (STORE_FLAG_VALUE == 1
6039 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
6040 && op1 == const0_rtx
6041 && mode == GET_MODE (op0)
6042 && (num_sign_bit_copies (op0, mode)
6043 == GET_MODE_PRECISION (mode)))
6045 op0 = expand_compound_operation (op0);
6046 return plus_constant (mode, gen_lowpart (mode, op0), 1);
6049 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6054 else if (STORE_FLAG_VALUE == -1
6055 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
6056 && op1 == const0_rtx
6057 && mode == GET_MODE (op0)
6058 && (num_sign_bit_copies (op0, mode)
6059 == GET_MODE_PRECISION (mode)))
6060 return gen_lowpart (mode,
6061 expand_compound_operation (op0));
6063 else if (STORE_FLAG_VALUE == -1
6064 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
6065 && op1 == const0_rtx
6066 && mode == GET_MODE (op0)
6067 && nonzero_bits (op0, mode) == 1)
6069 op0 = expand_compound_operation (op0);
6070 return simplify_gen_unary (NEG, mode,
6071 gen_lowpart (mode, op0),
6075 else if (STORE_FLAG_VALUE == -1
6076 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
6077 && op1 == const0_rtx
6078 && mode == GET_MODE (op0)
6079 && (num_sign_bit_copies (op0, mode)
6080 == GET_MODE_PRECISION (mode)))
6082 op0 = expand_compound_operation (op0);
6083 return simplify_gen_unary (NOT, mode,
6084 gen_lowpart (mode, op0),
6088 /* If X is 0/1, (eq X 0) is X-1. */
6089 else if (STORE_FLAG_VALUE == -1
6090 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
6091 && op1 == const0_rtx
6092 && mode == GET_MODE (op0)
6093 && nonzero_bits (op0, mode) == 1)
6095 op0 = expand_compound_operation (op0);
6096 return plus_constant (mode, gen_lowpart (mode, op0), -1);
6099 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6100 one bit that might be nonzero, we can convert (ne x 0) to
6101 (ashift x c) where C puts the bit in the sign bit. Remove any
6102 AND with STORE_FLAG_VALUE when we are done, since we are only
6103 going to test the sign bit. */
6104 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
6105 && HWI_COMPUTABLE_MODE_P (mode)
6106 && val_signbit_p (mode, STORE_FLAG_VALUE)
6107 && op1 == const0_rtx
6108 && mode == GET_MODE (op0)
6109 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
6111 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6112 expand_compound_operation (op0),
6113 GET_MODE_PRECISION (mode) - 1 - i);
6114 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6120 /* If the code changed, return a whole new comparison.
6121 We also need to avoid using SUBST in cases where
6122 simplify_comparison has widened a comparison with a CONST_INT,
6123 since in that case the wider CONST_INT may fail the sanity
6124 checks in do_SUBST. */
6125 if (new_code != code
6126 || (CONST_INT_P (op1)
6127 && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6128 && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6129 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6131 /* Otherwise, keep this operation, but maybe change its operands.
6132 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6133 SUBST (XEXP (x, 0), op0);
6134 SUBST (XEXP (x, 1), op1);
6139 return simplify_if_then_else (x);
6145 /* If we are processing SET_DEST, we are done. */
6149 return expand_compound_operation (x);
6152 return simplify_set (x);
6156 return simplify_logical (x);
6163 /* If this is a shift by a constant amount, simplify it. */
6164 if (CONST_INT_P (XEXP (x, 1)))
6165 return simplify_shift_const (x, code, mode, XEXP (x, 0),
6166 INTVAL (XEXP (x, 1)));
6168 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6170 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6171 ((unsigned HOST_WIDE_INT) 1
6172 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
6184 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6187 simplify_if_then_else (rtx x)
6189 machine_mode mode = GET_MODE (x);
6190 rtx cond = XEXP (x, 0);
6191 rtx true_rtx = XEXP (x, 1);
6192 rtx false_rtx = XEXP (x, 2);
6193 enum rtx_code true_code = GET_CODE (cond);
6194 int comparison_p = COMPARISON_P (cond);
6197 enum rtx_code false_code;
6200 /* Simplify storing of the truth value. */
6201 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6202 return simplify_gen_relational (true_code, mode, VOIDmode,
6203 XEXP (cond, 0), XEXP (cond, 1));
6205 /* Also when the truth value has to be reversed. */
6207 && true_rtx == const0_rtx && false_rtx == const_true_rtx
6208 && (reversed = reversed_comparison (cond, mode)))
6211 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6212 in it is being compared against certain values. Get the true and false
6213 comparisons and see if that says anything about the value of each arm. */
6216 && ((false_code = reversed_comparison_code (cond, NULL))
6218 && REG_P (XEXP (cond, 0)))
6221 rtx from = XEXP (cond, 0);
6222 rtx true_val = XEXP (cond, 1);
6223 rtx false_val = true_val;
6226 /* If FALSE_CODE is EQ, swap the codes and arms. */
6228 if (false_code == EQ)
6230 swapped = 1, true_code = EQ, false_code = NE;
6231 std::swap (true_rtx, false_rtx);
6234 /* If we are comparing against zero and the expression being tested has
6235 only a single bit that might be nonzero, that is its value when it is
6236 not equal to zero. Similarly if it is known to be -1 or 0. */
6238 if (true_code == EQ && true_val == const0_rtx
6239 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6242 false_val = gen_int_mode (nzb, GET_MODE (from));
6244 else if (true_code == EQ && true_val == const0_rtx
6245 && (num_sign_bit_copies (from, GET_MODE (from))
6246 == GET_MODE_PRECISION (GET_MODE (from))))
6249 false_val = constm1_rtx;
6252 /* Now simplify an arm if we know the value of the register in the
6253 branch and it is used in the arm. Be careful due to the potential
6254 of locally-shared RTL. */
6256 if (reg_mentioned_p (from, true_rtx))
6257 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6259 pc_rtx, pc_rtx, 0, 0, 0);
6260 if (reg_mentioned_p (from, false_rtx))
6261 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6263 pc_rtx, pc_rtx, 0, 0, 0);
6265 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6266 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6268 true_rtx = XEXP (x, 1);
6269 false_rtx = XEXP (x, 2);
6270 true_code = GET_CODE (cond);
6273 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6274 reversed, do so to avoid needing two sets of patterns for
6275 subtract-and-branch insns. Similarly if we have a constant in the true
6276 arm, the false arm is the same as the first operand of the comparison, or
6277 the false arm is more complicated than the true arm. */
6280 && reversed_comparison_code (cond, NULL) != UNKNOWN
6281 && (true_rtx == pc_rtx
6282 || (CONSTANT_P (true_rtx)
6283 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6284 || true_rtx == const0_rtx
6285 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6286 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6287 && !OBJECT_P (false_rtx))
6288 || reg_mentioned_p (true_rtx, false_rtx)
6289 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6291 true_code = reversed_comparison_code (cond, NULL);
6292 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6293 SUBST (XEXP (x, 1), false_rtx);
6294 SUBST (XEXP (x, 2), true_rtx);
6296 std::swap (true_rtx, false_rtx);
6299 /* It is possible that the conditional has been simplified out. */
6300 true_code = GET_CODE (cond);
6301 comparison_p = COMPARISON_P (cond);
6304 /* If the two arms are identical, we don't need the comparison. */
6306 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6309 /* Convert a == b ? b : a to "a". */
6310 if (true_code == EQ && ! side_effects_p (cond)
6311 && !HONOR_NANS (mode)
6312 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6313 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6315 else if (true_code == NE && ! side_effects_p (cond)
6316 && !HONOR_NANS (mode)
6317 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6318 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6321 /* Look for cases where we have (abs x) or (neg (abs X)). */
6323 if (GET_MODE_CLASS (mode) == MODE_INT
6325 && XEXP (cond, 1) == const0_rtx
6326 && GET_CODE (false_rtx) == NEG
6327 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6328 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6329 && ! side_effects_p (true_rtx))
6334 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6338 simplify_gen_unary (NEG, mode,
6339 simplify_gen_unary (ABS, mode, true_rtx, mode),
6345 /* Look for MIN or MAX. */
6347 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6349 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6350 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6351 && ! side_effects_p (cond))
6356 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6359 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6362 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6365 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6370 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6371 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6372 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6373 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6374 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6375 neither 1 or -1, but it isn't worth checking for. */
6377 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6379 && GET_MODE_CLASS (mode) == MODE_INT
6380 && ! side_effects_p (x))
6382 rtx t = make_compound_operation (true_rtx, SET);
6383 rtx f = make_compound_operation (false_rtx, SET);
6384 rtx cond_op0 = XEXP (cond, 0);
6385 rtx cond_op1 = XEXP (cond, 1);
6386 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6387 machine_mode m = mode;
6388 rtx z = 0, c1 = NULL_RTX;
6390 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6391 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6392 || GET_CODE (t) == ASHIFT
6393 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6394 && rtx_equal_p (XEXP (t, 0), f))
6395 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6397 /* If an identity-zero op is commutative, check whether there
6398 would be a match if we swapped the operands. */
6399 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6400 || GET_CODE (t) == XOR)
6401 && rtx_equal_p (XEXP (t, 1), f))
6402 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6403 else if (GET_CODE (t) == SIGN_EXTEND
6404 && (GET_CODE (XEXP (t, 0)) == PLUS
6405 || GET_CODE (XEXP (t, 0)) == MINUS
6406 || GET_CODE (XEXP (t, 0)) == IOR
6407 || GET_CODE (XEXP (t, 0)) == XOR
6408 || GET_CODE (XEXP (t, 0)) == ASHIFT
6409 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6410 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6411 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6412 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6413 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6414 && (num_sign_bit_copies (f, GET_MODE (f))
6416 (GET_MODE_PRECISION (mode)
6417 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6419 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6420 extend_op = SIGN_EXTEND;
6421 m = GET_MODE (XEXP (t, 0));
6423 else if (GET_CODE (t) == SIGN_EXTEND
6424 && (GET_CODE (XEXP (t, 0)) == PLUS
6425 || GET_CODE (XEXP (t, 0)) == IOR
6426 || GET_CODE (XEXP (t, 0)) == XOR)
6427 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6428 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6429 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6430 && (num_sign_bit_copies (f, GET_MODE (f))
6432 (GET_MODE_PRECISION (mode)
6433 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6435 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6436 extend_op = SIGN_EXTEND;
6437 m = GET_MODE (XEXP (t, 0));
6439 else if (GET_CODE (t) == ZERO_EXTEND
6440 && (GET_CODE (XEXP (t, 0)) == PLUS
6441 || GET_CODE (XEXP (t, 0)) == MINUS
6442 || GET_CODE (XEXP (t, 0)) == IOR
6443 || GET_CODE (XEXP (t, 0)) == XOR
6444 || GET_CODE (XEXP (t, 0)) == ASHIFT
6445 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6446 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6447 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6448 && HWI_COMPUTABLE_MODE_P (mode)
6449 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6450 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6451 && ((nonzero_bits (f, GET_MODE (f))
6452 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6455 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6456 extend_op = ZERO_EXTEND;
6457 m = GET_MODE (XEXP (t, 0));
6459 else if (GET_CODE (t) == ZERO_EXTEND
6460 && (GET_CODE (XEXP (t, 0)) == PLUS
6461 || GET_CODE (XEXP (t, 0)) == IOR
6462 || GET_CODE (XEXP (t, 0)) == XOR)
6463 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6464 && HWI_COMPUTABLE_MODE_P (mode)
6465 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6466 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6467 && ((nonzero_bits (f, GET_MODE (f))
6468 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6471 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6472 extend_op = ZERO_EXTEND;
6473 m = GET_MODE (XEXP (t, 0));
6478 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6479 cond_op0, cond_op1),
6480 pc_rtx, pc_rtx, 0, 0, 0);
6481 temp = simplify_gen_binary (MULT, m, temp,
6482 simplify_gen_binary (MULT, m, c1,
6484 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6485 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6487 if (extend_op != UNKNOWN)
6488 temp = simplify_gen_unary (extend_op, mode, temp, m);
6494 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6495 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6496 negation of a single bit, we can convert this operation to a shift. We
6497 can actually do this more generally, but it doesn't seem worth it. */
6499 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6500 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6501 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6502 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6503 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6504 == GET_MODE_PRECISION (mode))
6505 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6507 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6508 gen_lowpart (mode, XEXP (cond, 0)), i);
6510 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6511 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6512 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6513 && GET_MODE (XEXP (cond, 0)) == mode
6514 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6515 == nonzero_bits (XEXP (cond, 0), mode)
6516 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6517 return XEXP (cond, 0);
6522 /* Simplify X, a SET expression. Return the new expression. */
6525 simplify_set (rtx x)
6527 rtx src = SET_SRC (x);
6528 rtx dest = SET_DEST (x);
6530 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6531 rtx_insn *other_insn;
6534 /* (set (pc) (return)) gets written as (return). */
6535 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6538 /* Now that we know for sure which bits of SRC we are using, see if we can
6539 simplify the expression for the object knowing that we only need the
6542 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6544 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6545 SUBST (SET_SRC (x), src);
6548 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6549 the comparison result and try to simplify it unless we already have used
6550 undobuf.other_insn. */
6551 if ((GET_MODE_CLASS (mode) == MODE_CC
6552 || GET_CODE (src) == COMPARE
6554 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6555 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6556 && COMPARISON_P (*cc_use)
6557 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6559 enum rtx_code old_code = GET_CODE (*cc_use);
6560 enum rtx_code new_code;
6562 int other_changed = 0;
6563 rtx inner_compare = NULL_RTX;
6564 machine_mode compare_mode = GET_MODE (dest);
6566 if (GET_CODE (src) == COMPARE)
6568 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6569 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6571 inner_compare = op0;
6572 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6576 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6578 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6581 new_code = old_code;
6582 else if (!CONSTANT_P (tmp))
6584 new_code = GET_CODE (tmp);
6585 op0 = XEXP (tmp, 0);
6586 op1 = XEXP (tmp, 1);
6590 rtx pat = PATTERN (other_insn);
6591 undobuf.other_insn = other_insn;
6592 SUBST (*cc_use, tmp);
6594 /* Attempt to simplify CC user. */
6595 if (GET_CODE (pat) == SET)
6597 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6598 if (new_rtx != NULL_RTX)
6599 SUBST (SET_SRC (pat), new_rtx);
6602 /* Convert X into a no-op move. */
6603 SUBST (SET_DEST (x), pc_rtx);
6604 SUBST (SET_SRC (x), pc_rtx);
6608 /* Simplify our comparison, if possible. */
6609 new_code = simplify_comparison (new_code, &op0, &op1);
6611 #ifdef SELECT_CC_MODE
6612 /* If this machine has CC modes other than CCmode, check to see if we
6613 need to use a different CC mode here. */
6614 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6615 compare_mode = GET_MODE (op0);
6616 else if (inner_compare
6617 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6618 && new_code == old_code
6619 && op0 == XEXP (inner_compare, 0)
6620 && op1 == XEXP (inner_compare, 1))
6621 compare_mode = GET_MODE (inner_compare);
6623 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6625 /* If the mode changed, we have to change SET_DEST, the mode in the
6626 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6627 a hard register, just build new versions with the proper mode. If it
6628 is a pseudo, we lose unless it is only time we set the pseudo, in
6629 which case we can safely change its mode. */
6630 if (!HAVE_cc0 && compare_mode != GET_MODE (dest))
6632 if (can_change_dest_mode (dest, 0, compare_mode))
6634 unsigned int regno = REGNO (dest);
6637 if (regno < FIRST_PSEUDO_REGISTER)
6638 new_dest = gen_rtx_REG (compare_mode, regno);
6641 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6642 new_dest = regno_reg_rtx[regno];
6645 SUBST (SET_DEST (x), new_dest);
6646 SUBST (XEXP (*cc_use, 0), new_dest);
6652 #endif /* SELECT_CC_MODE */
6654 /* If the code changed, we have to build a new comparison in
6655 undobuf.other_insn. */
6656 if (new_code != old_code)
6658 int other_changed_previously = other_changed;
6659 unsigned HOST_WIDE_INT mask;
6660 rtx old_cc_use = *cc_use;
6662 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6666 /* If the only change we made was to change an EQ into an NE or
6667 vice versa, OP0 has only one bit that might be nonzero, and OP1
6668 is zero, check if changing the user of the condition code will
6669 produce a valid insn. If it won't, we can keep the original code
6670 in that insn by surrounding our operation with an XOR. */
6672 if (((old_code == NE && new_code == EQ)
6673 || (old_code == EQ && new_code == NE))
6674 && ! other_changed_previously && op1 == const0_rtx
6675 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6676 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6678 rtx pat = PATTERN (other_insn), note = 0;
6680 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6681 && ! check_asm_operands (pat)))
6683 *cc_use = old_cc_use;
6686 op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6694 undobuf.other_insn = other_insn;
6696 /* Don't generate a compare of a CC with 0, just use that CC. */
6697 if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6699 SUBST (SET_SRC (x), op0);
6702 /* Otherwise, if we didn't previously have the same COMPARE we
6703 want, create it from scratch. */
6704 else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
6705 || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6707 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6713 /* Get SET_SRC in a form where we have placed back any
6714 compound expressions. Then do the checks below. */
6715 src = make_compound_operation (src, SET);
6716 SUBST (SET_SRC (x), src);
6719 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6720 and X being a REG or (subreg (reg)), we may be able to convert this to
6721 (set (subreg:m2 x) (op)).
6723 We can always do this if M1 is narrower than M2 because that means that
6724 we only care about the low bits of the result.
6726 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6727 perform a narrower operation than requested since the high-order bits will
6728 be undefined. On machine where it is defined, this transformation is safe
6729 as long as M1 and M2 have the same number of words. */
6731 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6732 && !OBJECT_P (SUBREG_REG (src))
6733 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6735 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6736 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6737 && (WORD_REGISTER_OPERATIONS
6738 || (GET_MODE_SIZE (GET_MODE (src))
6739 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
6740 #ifdef CANNOT_CHANGE_MODE_CLASS
6741 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6742 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6743 GET_MODE (SUBREG_REG (src)),
6747 || (GET_CODE (dest) == SUBREG
6748 && REG_P (SUBREG_REG (dest)))))
6750 SUBST (SET_DEST (x),
6751 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6753 SUBST (SET_SRC (x), SUBREG_REG (src));
6755 src = SET_SRC (x), dest = SET_DEST (x);
6758 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6761 && GET_CODE (src) == SUBREG
6762 && subreg_lowpart_p (src)
6763 && (GET_MODE_PRECISION (GET_MODE (src))
6764 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6766 rtx inner = SUBREG_REG (src);
6767 machine_mode inner_mode = GET_MODE (inner);
6769 /* Here we make sure that we don't have a sign bit on. */
6770 if (val_signbit_known_clear_p (GET_MODE (src),
6771 nonzero_bits (inner, inner_mode)))
6773 SUBST (SET_SRC (x), inner);
6778 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6779 would require a paradoxical subreg. Replace the subreg with a
6780 zero_extend to avoid the reload that would otherwise be required. */
6782 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6783 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6784 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6785 && SUBREG_BYTE (src) == 0
6786 && paradoxical_subreg_p (src)
6787 && MEM_P (SUBREG_REG (src)))
6790 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6791 GET_MODE (src), SUBREG_REG (src)));
6796 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6797 are comparing an item known to be 0 or -1 against 0, use a logical
6798 operation instead. Check for one of the arms being an IOR of the other
6799 arm with some value. We compute three terms to be IOR'ed together. In
6800 practice, at most two will be nonzero. Then we do the IOR's. */
6802 if (GET_CODE (dest) != PC
6803 && GET_CODE (src) == IF_THEN_ELSE
6804 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6805 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6806 && XEXP (XEXP (src, 0), 1) == const0_rtx
6807 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6808 && (!HAVE_conditional_move
6809 || ! can_conditionally_move_p (GET_MODE (src)))
6810 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6811 GET_MODE (XEXP (XEXP (src, 0), 0)))
6812 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6813 && ! side_effects_p (src))
6815 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6816 ? XEXP (src, 1) : XEXP (src, 2));
6817 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6818 ? XEXP (src, 2) : XEXP (src, 1));
6819 rtx term1 = const0_rtx, term2, term3;
6821 if (GET_CODE (true_rtx) == IOR
6822 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6823 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6824 else if (GET_CODE (true_rtx) == IOR
6825 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6826 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6827 else if (GET_CODE (false_rtx) == IOR
6828 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6829 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6830 else if (GET_CODE (false_rtx) == IOR
6831 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6832 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6834 term2 = simplify_gen_binary (AND, GET_MODE (src),
6835 XEXP (XEXP (src, 0), 0), true_rtx);
6836 term3 = simplify_gen_binary (AND, GET_MODE (src),
6837 simplify_gen_unary (NOT, GET_MODE (src),
6838 XEXP (XEXP (src, 0), 0),
6843 simplify_gen_binary (IOR, GET_MODE (src),
6844 simplify_gen_binary (IOR, GET_MODE (src),
6851 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6852 whole thing fail. */
6853 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6855 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6858 /* Convert this into a field assignment operation, if possible. */
6859 return make_field_assignment (x);
6862 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6866 simplify_logical (rtx x)
6868 machine_mode mode = GET_MODE (x);
6869 rtx op0 = XEXP (x, 0);
6870 rtx op1 = XEXP (x, 1);
6872 switch (GET_CODE (x))
6875 /* We can call simplify_and_const_int only if we don't lose
6876 any (sign) bits when converting INTVAL (op1) to
6877 "unsigned HOST_WIDE_INT". */
6878 if (CONST_INT_P (op1)
6879 && (HWI_COMPUTABLE_MODE_P (mode)
6880 || INTVAL (op1) > 0))
6882 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6883 if (GET_CODE (x) != AND)
6890 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6891 apply the distributive law and then the inverse distributive
6892 law to see if things simplify. */
6893 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6895 rtx result = distribute_and_simplify_rtx (x, 0);
6899 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6901 rtx result = distribute_and_simplify_rtx (x, 1);
6908 /* If we have (ior (and A B) C), apply the distributive law and then
6909 the inverse distributive law to see if things simplify. */
6911 if (GET_CODE (op0) == AND)
6913 rtx result = distribute_and_simplify_rtx (x, 0);
6918 if (GET_CODE (op1) == AND)
6920 rtx result = distribute_and_simplify_rtx (x, 1);
6933 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6934 operations" because they can be replaced with two more basic operations.
6935 ZERO_EXTEND is also considered "compound" because it can be replaced with
6936 an AND operation, which is simpler, though only one operation.
6938 The function expand_compound_operation is called with an rtx expression
6939 and will convert it to the appropriate shifts and AND operations,
6940 simplifying at each stage.
6942 The function make_compound_operation is called to convert an expression
6943 consisting of shifts and ANDs into the equivalent compound expression.
6944 It is the inverse of this function, loosely speaking. */
6947 expand_compound_operation (rtx x)
6949 unsigned HOST_WIDE_INT pos = 0, len;
6951 unsigned int modewidth;
6954 switch (GET_CODE (x))
6960 /* We can't necessarily use a const_int for a multiword mode;
6961 it depends on implicitly extending the value.
6962 Since we don't know the right way to extend it,
6963 we can't tell whether the implicit way is right.
6965 Even for a mode that is no wider than a const_int,
6966 we can't win, because we need to sign extend one of its bits through
6967 the rest of it, and we don't know which bit. */
6968 if (CONST_INT_P (XEXP (x, 0)))
6971 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6972 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6973 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6974 reloaded. If not for that, MEM's would very rarely be safe.
6976 Reject MODEs bigger than a word, because we might not be able
6977 to reference a two-register group starting with an arbitrary register
6978 (and currently gen_lowpart might crash for a SUBREG). */
6980 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6983 /* Reject MODEs that aren't scalar integers because turning vector
6984 or complex modes into shifts causes problems. */
6986 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6989 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6990 /* If the inner object has VOIDmode (the only way this can happen
6991 is if it is an ASM_OPERANDS), we can't do anything since we don't
6992 know how much masking to do. */
7004 /* If the operand is a CLOBBER, just return it. */
7005 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7008 if (!CONST_INT_P (XEXP (x, 1))
7009 || !CONST_INT_P (XEXP (x, 2))
7010 || GET_MODE (XEXP (x, 0)) == VOIDmode)
7013 /* Reject MODEs that aren't scalar integers because turning vector
7014 or complex modes into shifts causes problems. */
7016 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
7019 len = INTVAL (XEXP (x, 1));
7020 pos = INTVAL (XEXP (x, 2));
7022 /* This should stay within the object being extracted, fail otherwise. */
7023 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
7026 if (BITS_BIG_ENDIAN)
7027 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
7034 /* Convert sign extension to zero extension, if we know that the high
7035 bit is not set, as this is easier to optimize. It will be converted
7036 back to cheaper alternative in make_extraction. */
7037 if (GET_CODE (x) == SIGN_EXTEND
7038 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
7039 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7040 & ~(((unsigned HOST_WIDE_INT)
7041 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
7045 machine_mode mode = GET_MODE (x);
7046 rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7047 rtx temp2 = expand_compound_operation (temp);
7049 /* Make sure this is a profitable operation. */
7050 if (set_src_cost (x, mode, optimize_this_for_speed_p)
7051 > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7053 else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7054 > set_src_cost (temp, mode, optimize_this_for_speed_p))
7060 /* We can optimize some special cases of ZERO_EXTEND. */
7061 if (GET_CODE (x) == ZERO_EXTEND)
7063 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7064 know that the last value didn't have any inappropriate bits
7066 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7067 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
7068 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
7069 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
7070 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
7071 return XEXP (XEXP (x, 0), 0);
7073 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7074 if (GET_CODE (XEXP (x, 0)) == SUBREG
7075 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
7076 && subreg_lowpart_p (XEXP (x, 0))
7077 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
7078 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
7079 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
7080 return SUBREG_REG (XEXP (x, 0));
7082 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7083 is a comparison and STORE_FLAG_VALUE permits. This is like
7084 the first case, but it works even when GET_MODE (x) is larger
7085 than HOST_WIDE_INT. */
7086 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7087 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
7088 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7089 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
7090 <= HOST_BITS_PER_WIDE_INT)
7091 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
7092 return XEXP (XEXP (x, 0), 0);
7094 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7095 if (GET_CODE (XEXP (x, 0)) == SUBREG
7096 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
7097 && subreg_lowpart_p (XEXP (x, 0))
7098 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7099 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
7100 <= HOST_BITS_PER_WIDE_INT)
7101 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
7102 return SUBREG_REG (XEXP (x, 0));
7106 /* If we reach here, we want to return a pair of shifts. The inner
7107 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7108 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7109 logical depending on the value of UNSIGNEDP.
7111 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7112 converted into an AND of a shift.
7114 We must check for the case where the left shift would have a negative
7115 count. This can happen in a case like (x >> 31) & 255 on machines
7116 that can't shift by a constant. On those machines, we would first
7117 combine the shift with the AND to produce a variable-position
7118 extraction. Then the constant of 31 would be substituted in
7119 to produce such a position. */
7121 modewidth = GET_MODE_PRECISION (GET_MODE (x));
7122 if (modewidth >= pos + len)
7124 machine_mode mode = GET_MODE (x);
7125 tem = gen_lowpart (mode, XEXP (x, 0));
7126 if (!tem || GET_CODE (tem) == CLOBBER)
7128 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7129 tem, modewidth - pos - len);
7130 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7131 mode, tem, modewidth - len);
7133 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7134 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
7135 simplify_shift_const (NULL_RTX, LSHIFTRT,
7138 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
7140 /* Any other cases we can't handle. */
7143 /* If we couldn't do this for some reason, return the original
7145 if (GET_CODE (tem) == CLOBBER)
7151 /* X is a SET which contains an assignment of one object into
7152 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7153 or certain SUBREGS). If possible, convert it into a series of
7156 We half-heartedly support variable positions, but do not at all
7157 support variable lengths. */
7160 expand_field_assignment (const_rtx x)
7163 rtx pos; /* Always counts from low bit. */
7165 rtx mask, cleared, masked;
7166 machine_mode compute_mode;
7168 /* Loop until we find something we can't simplify. */
7171 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7172 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7174 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7175 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
7176 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
7178 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7179 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7181 inner = XEXP (SET_DEST (x), 0);
7182 len = INTVAL (XEXP (SET_DEST (x), 1));
7183 pos = XEXP (SET_DEST (x), 2);
7185 /* A constant position should stay within the width of INNER. */
7186 if (CONST_INT_P (pos)
7187 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
7190 if (BITS_BIG_ENDIAN)
7192 if (CONST_INT_P (pos))
7193 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
7195 else if (GET_CODE (pos) == MINUS
7196 && CONST_INT_P (XEXP (pos, 1))
7197 && (INTVAL (XEXP (pos, 1))
7198 == GET_MODE_PRECISION (GET_MODE (inner)) - len))
7199 /* If position is ADJUST - X, new position is X. */
7200 pos = XEXP (pos, 0);
7203 HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
7204 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7205 gen_int_mode (prec - len,
7212 /* A SUBREG between two modes that occupy the same numbers of words
7213 can be done by moving the SUBREG to the source. */
7214 else if (GET_CODE (SET_DEST (x)) == SUBREG
7215 /* We need SUBREGs to compute nonzero_bits properly. */
7216 && nonzero_sign_valid
7217 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
7218 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7219 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
7220 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
7222 x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7224 (GET_MODE (SUBREG_REG (SET_DEST (x))),
7231 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7232 inner = SUBREG_REG (inner);
7234 compute_mode = GET_MODE (inner);
7236 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7237 if (! SCALAR_INT_MODE_P (compute_mode))
7241 /* Don't do anything for vector or complex integral types. */
7242 if (! FLOAT_MODE_P (compute_mode))
7245 /* Try to find an integral mode to pun with. */
7246 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7247 if (imode == BLKmode)
7250 compute_mode = imode;
7251 inner = gen_lowpart (imode, inner);
7254 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7255 if (len >= HOST_BITS_PER_WIDE_INT)
7258 /* Don't try to compute in too wide unsupported modes. */
7259 if (!targetm.scalar_mode_supported_p (compute_mode))
7262 /* Now compute the equivalent expression. Make a copy of INNER
7263 for the SET_DEST in case it is a MEM into which we will substitute;
7264 we don't want shared RTL in that case. */
7265 mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
7267 cleared = simplify_gen_binary (AND, compute_mode,
7268 simplify_gen_unary (NOT, compute_mode,
7269 simplify_gen_binary (ASHIFT,
7274 masked = simplify_gen_binary (ASHIFT, compute_mode,
7275 simplify_gen_binary (
7277 gen_lowpart (compute_mode, SET_SRC (x)),
7281 x = gen_rtx_SET (copy_rtx (inner),
7282 simplify_gen_binary (IOR, compute_mode,
7289 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7290 it is an RTX that represents the (variable) starting position; otherwise,
7291 POS is the (constant) starting bit position. Both are counted from the LSB.
7293 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7295 IN_DEST is nonzero if this is a reference in the destination of a SET.
7296 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7297 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7300 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7301 ZERO_EXTRACT should be built even for bits starting at bit 0.
7303 MODE is the desired mode of the result (if IN_DEST == 0).
7305 The result is an RTX for the extraction or NULL_RTX if the target
7309 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7310 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7311 int in_dest, int in_compare)
7313 /* This mode describes the size of the storage area
7314 to fetch the overall value from. Within that, we
7315 ignore the POS lowest bits, etc. */
7316 machine_mode is_mode = GET_MODE (inner);
7317 machine_mode inner_mode;
7318 machine_mode wanted_inner_mode;
7319 machine_mode wanted_inner_reg_mode = word_mode;
7320 machine_mode pos_mode = word_mode;
7321 machine_mode extraction_mode = word_mode;
7322 machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7324 rtx orig_pos_rtx = pos_rtx;
7325 HOST_WIDE_INT orig_pos;
7327 if (pos_rtx && CONST_INT_P (pos_rtx))
7328 pos = INTVAL (pos_rtx), pos_rtx = 0;
7330 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7332 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7333 consider just the QI as the memory to extract from.
7334 The subreg adds or removes high bits; its mode is
7335 irrelevant to the meaning of this extraction,
7336 since POS and LEN count from the lsb. */
7337 if (MEM_P (SUBREG_REG (inner)))
7338 is_mode = GET_MODE (SUBREG_REG (inner));
7339 inner = SUBREG_REG (inner);
7341 else if (GET_CODE (inner) == ASHIFT
7342 && CONST_INT_P (XEXP (inner, 1))
7343 && pos_rtx == 0 && pos == 0
7344 && len > UINTVAL (XEXP (inner, 1)))
7346 /* We're extracting the least significant bits of an rtx
7347 (ashift X (const_int C)), where LEN > C. Extract the
7348 least significant (LEN - C) bits of X, giving an rtx
7349 whose mode is MODE, then shift it left C times. */
7350 new_rtx = make_extraction (mode, XEXP (inner, 0),
7351 0, 0, len - INTVAL (XEXP (inner, 1)),
7352 unsignedp, in_dest, in_compare);
7354 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7356 else if (GET_CODE (inner) == TRUNCATE)
7357 inner = XEXP (inner, 0);
7359 inner_mode = GET_MODE (inner);
7361 /* See if this can be done without an extraction. We never can if the
7362 width of the field is not the same as that of some integer mode. For
7363 registers, we can only avoid the extraction if the position is at the
7364 low-order bit and this is either not in the destination or we have the
7365 appropriate STRICT_LOW_PART operation available.
7367 For MEM, we can avoid an extract if the field starts on an appropriate
7368 boundary and we can change the mode of the memory reference. */
7370 if (tmode != BLKmode
7371 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7373 && (pos == 0 || REG_P (inner))
7374 && (inner_mode == tmode
7376 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7377 || reg_truncated_to_mode (tmode, inner))
7380 && have_insn_for (STRICT_LOW_PART, tmode))))
7381 || (MEM_P (inner) && pos_rtx == 0
7383 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7384 : BITS_PER_UNIT)) == 0
7385 /* We can't do this if we are widening INNER_MODE (it
7386 may not be aligned, for one thing). */
7387 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7388 && (inner_mode == tmode
7389 || (! mode_dependent_address_p (XEXP (inner, 0),
7390 MEM_ADDR_SPACE (inner))
7391 && ! MEM_VOLATILE_P (inner))))))
7393 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7394 field. If the original and current mode are the same, we need not
7395 adjust the offset. Otherwise, we do if bytes big endian.
7397 If INNER is not a MEM, get a piece consisting of just the field
7398 of interest (in this case POS % BITS_PER_WORD must be 0). */
7402 HOST_WIDE_INT offset;
7404 /* POS counts from lsb, but make OFFSET count in memory order. */
7405 if (BYTES_BIG_ENDIAN)
7406 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7408 offset = pos / BITS_PER_UNIT;
7410 new_rtx = adjust_address_nv (inner, tmode, offset);
7412 else if (REG_P (inner))
7414 if (tmode != inner_mode)
7416 /* We can't call gen_lowpart in a DEST since we
7417 always want a SUBREG (see below) and it would sometimes
7418 return a new hard register. */
7421 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7423 if (WORDS_BIG_ENDIAN
7424 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7425 final_word = ((GET_MODE_SIZE (inner_mode)
7426 - GET_MODE_SIZE (tmode))
7427 / UNITS_PER_WORD) - final_word;
7429 final_word *= UNITS_PER_WORD;
7430 if (BYTES_BIG_ENDIAN &&
7431 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7432 final_word += (GET_MODE_SIZE (inner_mode)
7433 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7435 /* Avoid creating invalid subregs, for example when
7436 simplifying (x>>32)&255. */
7437 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7440 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7443 new_rtx = gen_lowpart (tmode, inner);
7449 new_rtx = force_to_mode (inner, tmode,
7450 len >= HOST_BITS_PER_WIDE_INT
7451 ? ~(unsigned HOST_WIDE_INT) 0
7452 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 0);
7454 /* If this extraction is going into the destination of a SET,
7455 make a STRICT_LOW_PART unless we made a MEM. */
7458 return (MEM_P (new_rtx) ? new_rtx
7459 : (GET_CODE (new_rtx) != SUBREG
7460 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7461 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7466 if (CONST_SCALAR_INT_P (new_rtx))
7467 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7468 mode, new_rtx, tmode);
7470 /* If we know that no extraneous bits are set, and that the high
7471 bit is not set, convert the extraction to the cheaper of
7472 sign and zero extension, that are equivalent in these cases. */
7473 if (flag_expensive_optimizations
7474 && (HWI_COMPUTABLE_MODE_P (tmode)
7475 && ((nonzero_bits (new_rtx, tmode)
7476 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7479 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7480 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7482 /* Prefer ZERO_EXTENSION, since it gives more information to
7484 if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7485 <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7490 /* Otherwise, sign- or zero-extend unless we already are in the
7493 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7497 /* Unless this is a COMPARE or we have a funny memory reference,
7498 don't do anything with zero-extending field extracts starting at
7499 the low-order bit since they are simple AND operations. */
7500 if (pos_rtx == 0 && pos == 0 && ! in_dest
7501 && ! in_compare && unsignedp)
7504 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7505 if the position is not a constant and the length is not 1. In all
7506 other cases, we would only be going outside our object in cases when
7507 an original shift would have been undefined. */
7509 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7510 || (pos_rtx != 0 && len != 1)))
7513 enum extraction_pattern pattern = (in_dest ? EP_insv
7514 : unsignedp ? EP_extzv : EP_extv);
7516 /* If INNER is not from memory, we want it to have the mode of a register
7517 extraction pattern's structure operand, or word_mode if there is no
7518 such pattern. The same applies to extraction_mode and pos_mode
7519 and their respective operands.
7521 For memory, assume that the desired extraction_mode and pos_mode
7522 are the same as for a register operation, since at present we don't
7523 have named patterns for aligned memory structures. */
7524 struct extraction_insn insn;
7525 if (get_best_reg_extraction_insn (&insn, pattern,
7526 GET_MODE_BITSIZE (inner_mode), mode))
7528 wanted_inner_reg_mode = insn.struct_mode;
7529 pos_mode = insn.pos_mode;
7530 extraction_mode = insn.field_mode;
7533 /* Never narrow an object, since that might not be safe. */
7535 if (mode != VOIDmode
7536 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7537 extraction_mode = mode;
7540 wanted_inner_mode = wanted_inner_reg_mode;
7543 /* Be careful not to go beyond the extracted object and maintain the
7544 natural alignment of the memory. */
7545 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7546 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7547 > GET_MODE_BITSIZE (wanted_inner_mode))
7549 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7550 gcc_assert (wanted_inner_mode != VOIDmode);
7556 if (BITS_BIG_ENDIAN)
7558 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7559 BITS_BIG_ENDIAN style. If position is constant, compute new
7560 position. Otherwise, build subtraction.
7561 Note that POS is relative to the mode of the original argument.
7562 If it's a MEM we need to recompute POS relative to that.
7563 However, if we're extracting from (or inserting into) a register,
7564 we want to recompute POS relative to wanted_inner_mode. */
7565 int width = (MEM_P (inner)
7566 ? GET_MODE_BITSIZE (is_mode)
7567 : GET_MODE_BITSIZE (wanted_inner_mode));
7570 pos = width - len - pos;
7573 = gen_rtx_MINUS (GET_MODE (pos_rtx),
7574 gen_int_mode (width - len, GET_MODE (pos_rtx)),
7576 /* POS may be less than 0 now, but we check for that below.
7577 Note that it can only be less than 0 if !MEM_P (inner). */
7580 /* If INNER has a wider mode, and this is a constant extraction, try to
7581 make it smaller and adjust the byte to point to the byte containing
7583 if (wanted_inner_mode != VOIDmode
7584 && inner_mode != wanted_inner_mode
7586 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7588 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7589 && ! MEM_VOLATILE_P (inner))
7593 /* The computations below will be correct if the machine is big
7594 endian in both bits and bytes or little endian in bits and bytes.
7595 If it is mixed, we must adjust. */
7597 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7598 adjust OFFSET to compensate. */
7599 if (BYTES_BIG_ENDIAN
7600 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7601 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7603 /* We can now move to the desired byte. */
7604 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7605 * GET_MODE_SIZE (wanted_inner_mode);
7606 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7608 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7609 && is_mode != wanted_inner_mode)
7610 offset = (GET_MODE_SIZE (is_mode)
7611 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7613 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7616 /* If INNER is not memory, get it into the proper mode. If we are changing
7617 its mode, POS must be a constant and smaller than the size of the new
7619 else if (!MEM_P (inner))
7621 /* On the LHS, don't create paradoxical subregs implicitely truncating
7622 the register unless TRULY_NOOP_TRUNCATION. */
7624 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7628 if (GET_MODE (inner) != wanted_inner_mode
7630 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7636 inner = force_to_mode (inner, wanted_inner_mode,
7638 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7639 ? ~(unsigned HOST_WIDE_INT) 0
7640 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7645 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7646 have to zero extend. Otherwise, we can just use a SUBREG. */
7648 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7650 rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7651 GET_MODE (pos_rtx));
7653 /* If we know that no extraneous bits are set, and that the high
7654 bit is not set, convert extraction to cheaper one - either
7655 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7657 if (flag_expensive_optimizations
7658 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7659 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7660 & ~(((unsigned HOST_WIDE_INT)
7661 GET_MODE_MASK (GET_MODE (pos_rtx)))
7665 rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7666 GET_MODE (pos_rtx));
7668 /* Prefer ZERO_EXTENSION, since it gives more information to
7670 if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
7671 < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
7677 /* Make POS_RTX unless we already have it and it is correct. If we don't
7678 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7680 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7681 pos_rtx = orig_pos_rtx;
7683 else if (pos_rtx == 0)
7684 pos_rtx = GEN_INT (pos);
7686 /* Make the required operation. See if we can use existing rtx. */
7687 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7688 extraction_mode, inner, GEN_INT (len), pos_rtx);
7690 new_rtx = gen_lowpart (mode, new_rtx);
7695 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7696 with any other operations in X. Return X without that shift if so. */
7699 extract_left_shift (rtx x, int count)
7701 enum rtx_code code = GET_CODE (x);
7702 machine_mode mode = GET_MODE (x);
7708 /* This is the shift itself. If it is wide enough, we will return
7709 either the value being shifted if the shift count is equal to
7710 COUNT or a shift for the difference. */
7711 if (CONST_INT_P (XEXP (x, 1))
7712 && INTVAL (XEXP (x, 1)) >= count)
7713 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7714 INTVAL (XEXP (x, 1)) - count);
7718 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7719 return simplify_gen_unary (code, mode, tem, mode);
7723 case PLUS: case IOR: case XOR: case AND:
7724 /* If we can safely shift this constant and we find the inner shift,
7725 make a new operation. */
7726 if (CONST_INT_P (XEXP (x, 1))
7727 && (UINTVAL (XEXP (x, 1))
7728 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7729 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7731 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7732 return simplify_gen_binary (code, mode, tem,
7733 gen_int_mode (val, mode));
7744 /* Look at the expression rooted at X. Look for expressions
7745 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7746 Form these expressions.
7748 Return the new rtx, usually just X.
7750 Also, for machines like the VAX that don't have logical shift insns,
7751 try to convert logical to arithmetic shift operations in cases where
7752 they are equivalent. This undoes the canonicalizations to logical
7753 shifts done elsewhere.
7755 We try, as much as possible, to re-use rtl expressions to save memory.
7757 IN_CODE says what kind of expression we are processing. Normally, it is
7758 SET. In a memory address it is MEM. When processing the arguments of
7759 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
7760 precisely it is an equality comparison against zero. */
7763 make_compound_operation (rtx x, enum rtx_code in_code)
7765 enum rtx_code code = GET_CODE (x);
7766 machine_mode mode = GET_MODE (x);
7767 int mode_width = GET_MODE_PRECISION (mode);
7769 enum rtx_code next_code;
7774 bool equality_comparison = false;
7776 /* Select the code to be used in recursive calls. Once we are inside an
7777 address, we stay there. If we have a comparison, set to COMPARE,
7778 but once inside, go back to our default of SET. */
7782 equality_comparison = true;
7785 next_code = (code == MEM ? MEM
7786 : ((code == COMPARE || COMPARISON_P (x))
7787 && XEXP (x, 1) == const0_rtx) ? COMPARE
7788 : in_code == COMPARE ? SET : in_code);
7790 /* Process depending on the code of this operation. If NEW is set
7791 nonzero, it will be returned. */
7796 /* Convert shifts by constants into multiplications if inside
7798 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7799 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7800 && INTVAL (XEXP (x, 1)) >= 0
7801 && SCALAR_INT_MODE_P (mode))
7803 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7804 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7806 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7807 if (GET_CODE (new_rtx) == NEG)
7809 new_rtx = XEXP (new_rtx, 0);
7812 multval = trunc_int_for_mode (multval, mode);
7813 new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7820 lhs = make_compound_operation (lhs, next_code);
7821 rhs = make_compound_operation (rhs, next_code);
7822 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7823 && SCALAR_INT_MODE_P (mode))
7825 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7827 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7829 else if (GET_CODE (lhs) == MULT
7830 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7832 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7833 simplify_gen_unary (NEG, mode,
7836 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7840 SUBST (XEXP (x, 0), lhs);
7841 SUBST (XEXP (x, 1), rhs);
7844 x = gen_lowpart (mode, new_rtx);
7850 lhs = make_compound_operation (lhs, next_code);
7851 rhs = make_compound_operation (rhs, next_code);
7852 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7853 && SCALAR_INT_MODE_P (mode))
7855 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7857 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7859 else if (GET_CODE (rhs) == MULT
7860 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7862 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7863 simplify_gen_unary (NEG, mode,
7866 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7870 SUBST (XEXP (x, 0), lhs);
7871 SUBST (XEXP (x, 1), rhs);
7874 return gen_lowpart (mode, new_rtx);
7877 /* If the second operand is not a constant, we can't do anything
7879 if (!CONST_INT_P (XEXP (x, 1)))
7882 /* If the constant is a power of two minus one and the first operand
7883 is a logical right shift, make an extraction. */
7884 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7885 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7887 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7888 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7889 0, in_code == COMPARE);
7892 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7893 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7894 && subreg_lowpart_p (XEXP (x, 0))
7895 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7896 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7898 rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
7899 machine_mode inner_mode = GET_MODE (inner_x0);
7900 new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
7901 new_rtx = make_extraction (inner_mode, new_rtx, 0,
7903 i, 1, 0, in_code == COMPARE);
7907 /* If we narrowed the mode when dropping the subreg, then
7908 we must zero-extend to keep the semantics of the AND. */
7909 if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
7911 else if (SCALAR_INT_MODE_P (inner_mode))
7912 new_rtx = simplify_gen_unary (ZERO_EXTEND, mode,
7913 new_rtx, inner_mode);
7918 /* If that didn't give anything, see if the AND simplifies on
7920 if (!new_rtx && i >= 0)
7922 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7923 new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i, 1,
7924 0, in_code == COMPARE);
7927 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7928 else if ((GET_CODE (XEXP (x, 0)) == XOR
7929 || GET_CODE (XEXP (x, 0)) == IOR)
7930 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7931 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7932 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7934 /* Apply the distributive law, and then try to make extractions. */
7935 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7936 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7938 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7940 new_rtx = make_compound_operation (new_rtx, in_code);
7943 /* If we are have (and (rotate X C) M) and C is larger than the number
7944 of bits in M, this is an extraction. */
7946 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7947 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7948 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7949 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7951 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7952 new_rtx = make_extraction (mode, new_rtx,
7953 (GET_MODE_PRECISION (mode)
7954 - INTVAL (XEXP (XEXP (x, 0), 1))),
7955 NULL_RTX, i, 1, 0, in_code == COMPARE);
7958 /* On machines without logical shifts, if the operand of the AND is
7959 a logical shift and our mask turns off all the propagated sign
7960 bits, we can replace the logical shift with an arithmetic shift. */
7961 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7962 && !have_insn_for (LSHIFTRT, mode)
7963 && have_insn_for (ASHIFTRT, mode)
7964 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7965 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7966 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7967 && mode_width <= HOST_BITS_PER_WIDE_INT)
7969 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7971 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7972 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7974 gen_rtx_ASHIFTRT (mode,
7975 make_compound_operation
7976 (XEXP (XEXP (x, 0), 0), next_code),
7977 XEXP (XEXP (x, 0), 1)));
7980 /* If the constant is one less than a power of two, this might be
7981 representable by an extraction even if no shift is present.
7982 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7983 we are in a COMPARE. */
7984 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7985 new_rtx = make_extraction (mode,
7986 make_compound_operation (XEXP (x, 0),
7988 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7990 /* If we are in a comparison and this is an AND with a power of two,
7991 convert this into the appropriate bit extract. */
7992 else if (in_code == COMPARE
7993 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
7994 && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
7995 new_rtx = make_extraction (mode,
7996 make_compound_operation (XEXP (x, 0),
7998 i, NULL_RTX, 1, 1, 0, 1);
8003 /* If the sign bit is known to be zero, replace this with an
8004 arithmetic shift. */
8005 if (have_insn_for (ASHIFTRT, mode)
8006 && ! have_insn_for (LSHIFTRT, mode)
8007 && mode_width <= HOST_BITS_PER_WIDE_INT
8008 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8010 new_rtx = gen_rtx_ASHIFTRT (mode,
8011 make_compound_operation (XEXP (x, 0),
8023 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8024 this is a SIGN_EXTRACT. */
8025 if (CONST_INT_P (rhs)
8026 && GET_CODE (lhs) == ASHIFT
8027 && CONST_INT_P (XEXP (lhs, 1))
8028 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8029 && INTVAL (XEXP (lhs, 1)) >= 0
8030 && INTVAL (rhs) < mode_width)
8032 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8033 new_rtx = make_extraction (mode, new_rtx,
8034 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8035 NULL_RTX, mode_width - INTVAL (rhs),
8036 code == LSHIFTRT, 0, in_code == COMPARE);
8040 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8041 If so, try to merge the shifts into a SIGN_EXTEND. We could
8042 also do this for some cases of SIGN_EXTRACT, but it doesn't
8043 seem worth the effort; the case checked for occurs on Alpha. */
8046 && ! (GET_CODE (lhs) == SUBREG
8047 && (OBJECT_P (SUBREG_REG (lhs))))
8048 && CONST_INT_P (rhs)
8049 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8050 && INTVAL (rhs) < mode_width
8051 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
8052 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
8053 0, NULL_RTX, mode_width - INTVAL (rhs),
8054 code == LSHIFTRT, 0, in_code == COMPARE);
8059 /* Call ourselves recursively on the inner expression. If we are
8060 narrowing the object and it has a different RTL code from
8061 what it originally did, do this SUBREG as a force_to_mode. */
8063 rtx inner = SUBREG_REG (x), simplified;
8064 enum rtx_code subreg_code = in_code;
8066 /* If in_code is COMPARE, it isn't always safe to pass it through
8067 to the recursive make_compound_operation call. */
8068 if (subreg_code == COMPARE
8069 && (!subreg_lowpart_p (x)
8070 || GET_CODE (inner) == SUBREG
8071 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8072 is (const_int 0), rather than
8073 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8074 || (GET_CODE (inner) == AND
8075 && CONST_INT_P (XEXP (inner, 1))
8076 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
8077 && exact_log2 (UINTVAL (XEXP (inner, 1)))
8078 >= GET_MODE_BITSIZE (mode))))
8081 tem = make_compound_operation (inner, subreg_code);
8084 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8088 if (GET_CODE (tem) != GET_CODE (inner)
8089 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
8090 && subreg_lowpart_p (x))
8093 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
8095 /* If we have something other than a SUBREG, we might have
8096 done an expansion, so rerun ourselves. */
8097 if (GET_CODE (newer) != SUBREG)
8098 newer = make_compound_operation (newer, in_code);
8100 /* force_to_mode can expand compounds. If it just re-expanded the
8101 compound, use gen_lowpart to convert to the desired mode. */
8102 if (rtx_equal_p (newer, x)
8103 /* Likewise if it re-expanded the compound only partially.
8104 This happens for SUBREG of ZERO_EXTRACT if they extract
8105 the same number of bits. */
8106 || (GET_CODE (newer) == SUBREG
8107 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8108 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8109 && GET_CODE (inner) == AND
8110 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8111 return gen_lowpart (GET_MODE (x), tem);
8127 x = gen_lowpart (mode, new_rtx);
8128 code = GET_CODE (x);
8131 /* Now recursively process each operand of this operation. We need to
8132 handle ZERO_EXTEND specially so that we don't lose track of the
8134 if (GET_CODE (x) == ZERO_EXTEND)
8136 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8137 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
8138 new_rtx, GET_MODE (XEXP (x, 0)));
8141 SUBST (XEXP (x, 0), new_rtx);
8145 fmt = GET_RTX_FORMAT (code);
8146 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8149 new_rtx = make_compound_operation (XEXP (x, i), next_code);
8150 SUBST (XEXP (x, i), new_rtx);
8152 else if (fmt[i] == 'E')
8153 for (j = 0; j < XVECLEN (x, i); j++)
8155 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8156 SUBST (XVECEXP (x, i, j), new_rtx);
8160 /* If this is a commutative operation, the changes to the operands
8161 may have made it noncanonical. */
8162 if (COMMUTATIVE_ARITH_P (x)
8163 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
8166 SUBST (XEXP (x, 0), XEXP (x, 1));
8167 SUBST (XEXP (x, 1), tem);
8173 /* Given M see if it is a value that would select a field of bits
8174 within an item, but not the entire word. Return -1 if not.
8175 Otherwise, return the starting position of the field, where 0 is the
8178 *PLEN is set to the length of the field. */
8181 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8183 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8184 int pos = m ? ctz_hwi (m) : -1;
8188 /* Now shift off the low-order zero bits and see if we have a
8189 power of two minus 1. */
8190 len = exact_log2 ((m >> pos) + 1);
8199 /* If X refers to a register that equals REG in value, replace these
8200 references with REG. */
8202 canon_reg_for_combine (rtx x, rtx reg)
8209 enum rtx_code code = GET_CODE (x);
8210 switch (GET_RTX_CLASS (code))
8213 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8214 if (op0 != XEXP (x, 0))
8215 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8220 case RTX_COMM_ARITH:
8221 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8222 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8223 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8224 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8228 case RTX_COMM_COMPARE:
8229 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8230 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8231 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8232 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8233 GET_MODE (op0), op0, op1);
8237 case RTX_BITFIELD_OPS:
8238 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8239 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8240 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8241 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8242 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8243 GET_MODE (op0), op0, op1, op2);
8249 if (rtx_equal_p (get_last_value (reg), x)
8250 || rtx_equal_p (reg, get_last_value (x)))
8259 fmt = GET_RTX_FORMAT (code);
8261 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8264 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8265 if (op != XEXP (x, i))
8275 else if (fmt[i] == 'E')
8278 for (j = 0; j < XVECLEN (x, i); j++)
8280 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8281 if (op != XVECEXP (x, i, j))
8288 XVECEXP (x, i, j) = op;
8299 /* Return X converted to MODE. If the value is already truncated to
8300 MODE we can just return a subreg even though in the general case we
8301 would need an explicit truncation. */
8304 gen_lowpart_or_truncate (machine_mode mode, rtx x)
8306 if (!CONST_INT_P (x)
8307 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8308 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8309 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8311 /* Bit-cast X into an integer mode. */
8312 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8313 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8314 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8318 return gen_lowpart (mode, x);
8321 /* See if X can be simplified knowing that we will only refer to it in
8322 MODE and will only refer to those bits that are nonzero in MASK.
8323 If other bits are being computed or if masking operations are done
8324 that select a superset of the bits in MASK, they can sometimes be
8327 Return a possibly simplified expression, but always convert X to
8328 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8330 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8331 are all off in X. This is used when X will be complemented, by either
8332 NOT, NEG, or XOR. */
8335 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8338 enum rtx_code code = GET_CODE (x);
8339 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8340 machine_mode op_mode;
8341 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8344 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8345 code below will do the wrong thing since the mode of such an
8346 expression is VOIDmode.
8348 Also do nothing if X is a CLOBBER; this can happen if X was
8349 the return value from a call to gen_lowpart. */
8350 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8353 /* We want to perform the operation in its present mode unless we know
8354 that the operation is valid in MODE, in which case we do the operation
8356 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8357 && have_insn_for (code, mode))
8358 ? mode : GET_MODE (x));
8360 /* It is not valid to do a right-shift in a narrower mode
8361 than the one it came in with. */
8362 if ((code == LSHIFTRT || code == ASHIFTRT)
8363 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8364 op_mode = GET_MODE (x);
8366 /* Truncate MASK to fit OP_MODE. */
8368 mask &= GET_MODE_MASK (op_mode);
8370 /* When we have an arithmetic operation, or a shift whose count we
8371 do not know, we need to assume that all bits up to the highest-order
8372 bit in MASK will be needed. This is how we form such a mask. */
8373 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8374 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8376 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8379 /* Determine what bits of X are guaranteed to be (non)zero. */
8380 nonzero = nonzero_bits (x, mode);
8382 /* If none of the bits in X are needed, return a zero. */
8383 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8386 /* If X is a CONST_INT, return a new one. Do this here since the
8387 test below will fail. */
8388 if (CONST_INT_P (x))
8390 if (SCALAR_INT_MODE_P (mode))
8391 return gen_int_mode (INTVAL (x) & mask, mode);
8394 x = GEN_INT (INTVAL (x) & mask);
8395 return gen_lowpart_common (mode, x);
8399 /* If X is narrower than MODE and we want all the bits in X's mode, just
8400 get X in the proper mode. */
8401 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8402 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8403 return gen_lowpart (mode, x);
8405 /* We can ignore the effect of a SUBREG if it narrows the mode or
8406 if the constant masks to zero all the bits the mode doesn't have. */
8407 if (GET_CODE (x) == SUBREG
8408 && subreg_lowpart_p (x)
8409 && ((GET_MODE_SIZE (GET_MODE (x))
8410 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8412 & GET_MODE_MASK (GET_MODE (x))
8413 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8414 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8416 /* The arithmetic simplifications here only work for scalar integer modes. */
8417 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8418 return gen_lowpart_or_truncate (mode, x);
8423 /* If X is a (clobber (const_int)), return it since we know we are
8424 generating something that won't match. */
8431 x = expand_compound_operation (x);
8432 if (GET_CODE (x) != code)
8433 return force_to_mode (x, mode, mask, next_select);
8437 /* Similarly for a truncate. */
8438 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8441 /* If this is an AND with a constant, convert it into an AND
8442 whose constant is the AND of that constant with MASK. If it
8443 remains an AND of MASK, delete it since it is redundant. */
8445 if (CONST_INT_P (XEXP (x, 1)))
8447 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8448 mask & INTVAL (XEXP (x, 1)));
8450 /* If X is still an AND, see if it is an AND with a mask that
8451 is just some low-order bits. If so, and it is MASK, we don't
8454 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8455 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8459 /* If it remains an AND, try making another AND with the bits
8460 in the mode mask that aren't in MASK turned on. If the
8461 constant in the AND is wide enough, this might make a
8462 cheaper constant. */
8464 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8465 && GET_MODE_MASK (GET_MODE (x)) != mask
8466 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8468 unsigned HOST_WIDE_INT cval
8469 = UINTVAL (XEXP (x, 1))
8470 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8473 y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8474 gen_int_mode (cval, GET_MODE (x)));
8475 if (set_src_cost (y, GET_MODE (x), optimize_this_for_speed_p)
8476 < set_src_cost (x, GET_MODE (x), optimize_this_for_speed_p))
8486 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8487 low-order bits (as in an alignment operation) and FOO is already
8488 aligned to that boundary, mask C1 to that boundary as well.
8489 This may eliminate that PLUS and, later, the AND. */
8492 unsigned int width = GET_MODE_PRECISION (mode);
8493 unsigned HOST_WIDE_INT smask = mask;
8495 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8496 number, sign extend it. */
8498 if (width < HOST_BITS_PER_WIDE_INT
8499 && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8500 smask |= HOST_WIDE_INT_M1U << width;
8502 if (CONST_INT_P (XEXP (x, 1))
8503 && exact_log2 (- smask) >= 0
8504 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8505 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8506 return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8507 (INTVAL (XEXP (x, 1)) & smask)),
8508 mode, smask, next_select);
8514 /* Substituting into the operands of a widening MULT is not likely to
8515 create RTL matching a machine insn. */
8517 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8518 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8519 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8520 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8521 && REG_P (XEXP (XEXP (x, 0), 0))
8522 && REG_P (XEXP (XEXP (x, 1), 0)))
8523 return gen_lowpart_or_truncate (mode, x);
8525 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8526 most significant bit in MASK since carries from those bits will
8527 affect the bits we are interested in. */
8532 /* If X is (minus C Y) where C's least set bit is larger than any bit
8533 in the mask, then we may replace with (neg Y). */
8534 if (CONST_INT_P (XEXP (x, 0))
8535 && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask))
8537 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8539 return force_to_mode (x, mode, mask, next_select);
8542 /* Similarly, if C contains every bit in the fuller_mask, then we may
8543 replace with (not Y). */
8544 if (CONST_INT_P (XEXP (x, 0))
8545 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8547 x = simplify_gen_unary (NOT, GET_MODE (x),
8548 XEXP (x, 1), GET_MODE (x));
8549 return force_to_mode (x, mode, mask, next_select);
8557 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8558 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8559 operation which may be a bitfield extraction. Ensure that the
8560 constant we form is not wider than the mode of X. */
8562 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8563 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8564 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8565 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8566 && CONST_INT_P (XEXP (x, 1))
8567 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8568 + floor_log2 (INTVAL (XEXP (x, 1))))
8569 < GET_MODE_PRECISION (GET_MODE (x)))
8570 && (UINTVAL (XEXP (x, 1))
8571 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8573 temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8574 << INTVAL (XEXP (XEXP (x, 0), 1)),
8576 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8577 XEXP (XEXP (x, 0), 0), temp);
8578 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8579 XEXP (XEXP (x, 0), 1));
8580 return force_to_mode (x, mode, mask, next_select);
8584 /* For most binary operations, just propagate into the operation and
8585 change the mode if we have an operation of that mode. */
8587 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8588 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8590 /* If we ended up truncating both operands, truncate the result of the
8591 operation instead. */
8592 if (GET_CODE (op0) == TRUNCATE
8593 && GET_CODE (op1) == TRUNCATE)
8595 op0 = XEXP (op0, 0);
8596 op1 = XEXP (op1, 0);
8599 op0 = gen_lowpart_or_truncate (op_mode, op0);
8600 op1 = gen_lowpart_or_truncate (op_mode, op1);
8602 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8603 x = simplify_gen_binary (code, op_mode, op0, op1);
8607 /* For left shifts, do the same, but just for the first operand.
8608 However, we cannot do anything with shifts where we cannot
8609 guarantee that the counts are smaller than the size of the mode
8610 because such a count will have a different meaning in a
8613 if (! (CONST_INT_P (XEXP (x, 1))
8614 && INTVAL (XEXP (x, 1)) >= 0
8615 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8616 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8617 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8618 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8621 /* If the shift count is a constant and we can do arithmetic in
8622 the mode of the shift, refine which bits we need. Otherwise, use the
8623 conservative form of the mask. */
8624 if (CONST_INT_P (XEXP (x, 1))
8625 && INTVAL (XEXP (x, 1)) >= 0
8626 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8627 && HWI_COMPUTABLE_MODE_P (op_mode))
8628 mask >>= INTVAL (XEXP (x, 1));
8632 op0 = gen_lowpart_or_truncate (op_mode,
8633 force_to_mode (XEXP (x, 0), op_mode,
8634 mask, next_select));
8636 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8637 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8641 /* Here we can only do something if the shift count is a constant,
8642 this shift constant is valid for the host, and we can do arithmetic
8645 if (CONST_INT_P (XEXP (x, 1))
8646 && INTVAL (XEXP (x, 1)) >= 0
8647 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8648 && HWI_COMPUTABLE_MODE_P (op_mode))
8650 rtx inner = XEXP (x, 0);
8651 unsigned HOST_WIDE_INT inner_mask;
8653 /* Select the mask of the bits we need for the shift operand. */
8654 inner_mask = mask << INTVAL (XEXP (x, 1));
8656 /* We can only change the mode of the shift if we can do arithmetic
8657 in the mode of the shift and INNER_MASK is no wider than the
8658 width of X's mode. */
8659 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8660 op_mode = GET_MODE (x);
8662 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8664 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8665 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8668 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8669 shift and AND produces only copies of the sign bit (C2 is one less
8670 than a power of two), we can do this with just a shift. */
8672 if (GET_CODE (x) == LSHIFTRT
8673 && CONST_INT_P (XEXP (x, 1))
8674 /* The shift puts one of the sign bit copies in the least significant
8676 && ((INTVAL (XEXP (x, 1))
8677 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8678 >= GET_MODE_PRECISION (GET_MODE (x)))
8679 && exact_log2 (mask + 1) >= 0
8680 /* Number of bits left after the shift must be more than the mask
8682 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8683 <= GET_MODE_PRECISION (GET_MODE (x)))
8684 /* Must be more sign bit copies than the mask needs. */
8685 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8686 >= exact_log2 (mask + 1)))
8687 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8688 GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8689 - exact_log2 (mask + 1)));
8694 /* If we are just looking for the sign bit, we don't need this shift at
8695 all, even if it has a variable count. */
8696 if (val_signbit_p (GET_MODE (x), mask))
8697 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8699 /* If this is a shift by a constant, get a mask that contains those bits
8700 that are not copies of the sign bit. We then have two cases: If
8701 MASK only includes those bits, this can be a logical shift, which may
8702 allow simplifications. If MASK is a single-bit field not within
8703 those bits, we are requesting a copy of the sign bit and hence can
8704 shift the sign bit to the appropriate location. */
8706 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8707 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8711 /* If the considered data is wider than HOST_WIDE_INT, we can't
8712 represent a mask for all its bits in a single scalar.
8713 But we only care about the lower bits, so calculate these. */
8715 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8717 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8719 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8720 is the number of bits a full-width mask would have set.
8721 We need only shift if these are fewer than nonzero can
8722 hold. If not, we must keep all bits set in nonzero. */
8724 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8725 < HOST_BITS_PER_WIDE_INT)
8726 nonzero >>= INTVAL (XEXP (x, 1))
8727 + HOST_BITS_PER_WIDE_INT
8728 - GET_MODE_PRECISION (GET_MODE (x)) ;
8732 nonzero = GET_MODE_MASK (GET_MODE (x));
8733 nonzero >>= INTVAL (XEXP (x, 1));
8736 if ((mask & ~nonzero) == 0)
8738 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8739 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8740 if (GET_CODE (x) != ASHIFTRT)
8741 return force_to_mode (x, mode, mask, next_select);
8744 else if ((i = exact_log2 (mask)) >= 0)
8746 x = simplify_shift_const
8747 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8748 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8750 if (GET_CODE (x) != ASHIFTRT)
8751 return force_to_mode (x, mode, mask, next_select);
8755 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8756 even if the shift count isn't a constant. */
8758 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8759 XEXP (x, 0), XEXP (x, 1));
8763 /* If this is a zero- or sign-extension operation that just affects bits
8764 we don't care about, remove it. Be sure the call above returned
8765 something that is still a shift. */
8767 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8768 && CONST_INT_P (XEXP (x, 1))
8769 && INTVAL (XEXP (x, 1)) >= 0
8770 && (INTVAL (XEXP (x, 1))
8771 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8772 && GET_CODE (XEXP (x, 0)) == ASHIFT
8773 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8774 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8781 /* If the shift count is constant and we can do computations
8782 in the mode of X, compute where the bits we care about are.
8783 Otherwise, we can't do anything. Don't change the mode of
8784 the shift or propagate MODE into the shift, though. */
8785 if (CONST_INT_P (XEXP (x, 1))
8786 && INTVAL (XEXP (x, 1)) >= 0)
8788 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8790 gen_int_mode (mask, GET_MODE (x)),
8792 if (temp && CONST_INT_P (temp))
8793 x = simplify_gen_binary (code, GET_MODE (x),
8794 force_to_mode (XEXP (x, 0), GET_MODE (x),
8795 INTVAL (temp), next_select),
8801 /* If we just want the low-order bit, the NEG isn't needed since it
8802 won't change the low-order bit. */
8804 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8806 /* We need any bits less significant than the most significant bit in
8807 MASK since carries from those bits will affect the bits we are
8813 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8814 same as the XOR case above. Ensure that the constant we form is not
8815 wider than the mode of X. */
8817 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8818 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8819 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8820 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8821 < GET_MODE_PRECISION (GET_MODE (x)))
8822 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8824 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8826 temp = simplify_gen_binary (XOR, GET_MODE (x),
8827 XEXP (XEXP (x, 0), 0), temp);
8828 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8829 temp, XEXP (XEXP (x, 0), 1));
8831 return force_to_mode (x, mode, mask, next_select);
8834 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8835 use the full mask inside the NOT. */
8839 op0 = gen_lowpart_or_truncate (op_mode,
8840 force_to_mode (XEXP (x, 0), mode, mask,
8842 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8843 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8847 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8848 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8849 which is equal to STORE_FLAG_VALUE. */
8850 if ((mask & ~STORE_FLAG_VALUE) == 0
8851 && XEXP (x, 1) == const0_rtx
8852 && GET_MODE (XEXP (x, 0)) == mode
8853 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8854 && (nonzero_bits (XEXP (x, 0), mode)
8855 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8856 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8861 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8862 written in a narrower mode. We play it safe and do not do so. */
8864 op0 = gen_lowpart_or_truncate (GET_MODE (x),
8865 force_to_mode (XEXP (x, 1), mode,
8866 mask, next_select));
8867 op1 = gen_lowpart_or_truncate (GET_MODE (x),
8868 force_to_mode (XEXP (x, 2), mode,
8869 mask, next_select));
8870 if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
8871 x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),
8872 GET_MODE (XEXP (x, 0)), XEXP (x, 0),
8880 /* Ensure we return a value of the proper mode. */
8881 return gen_lowpart_or_truncate (mode, x);
8884 /* Return nonzero if X is an expression that has one of two values depending on
8885 whether some other value is zero or nonzero. In that case, we return the
8886 value that is being tested, *PTRUE is set to the value if the rtx being
8887 returned has a nonzero value, and *PFALSE is set to the other alternative.
8889 If we return zero, we set *PTRUE and *PFALSE to X. */
8892 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8894 machine_mode mode = GET_MODE (x);
8895 enum rtx_code code = GET_CODE (x);
8896 rtx cond0, cond1, true0, true1, false0, false1;
8897 unsigned HOST_WIDE_INT nz;
8899 /* If we are comparing a value against zero, we are done. */
8900 if ((code == NE || code == EQ)
8901 && XEXP (x, 1) == const0_rtx)
8903 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8904 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8908 /* If this is a unary operation whose operand has one of two values, apply
8909 our opcode to compute those values. */
8910 else if (UNARY_P (x)
8911 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8913 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8914 *pfalse = simplify_gen_unary (code, mode, false0,
8915 GET_MODE (XEXP (x, 0)));
8919 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8920 make can't possibly match and would suppress other optimizations. */
8921 else if (code == COMPARE)
8924 /* If this is a binary operation, see if either side has only one of two
8925 values. If either one does or if both do and they are conditional on
8926 the same value, compute the new true and false values. */
8927 else if (BINARY_P (x))
8929 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8930 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8932 if ((cond0 != 0 || cond1 != 0)
8933 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8935 /* If if_then_else_cond returned zero, then true/false are the
8936 same rtl. We must copy one of them to prevent invalid rtl
8939 true0 = copy_rtx (true0);
8940 else if (cond1 == 0)
8941 true1 = copy_rtx (true1);
8943 if (COMPARISON_P (x))
8945 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8947 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8952 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8953 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8956 return cond0 ? cond0 : cond1;
8959 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8960 operands is zero when the other is nonzero, and vice-versa,
8961 and STORE_FLAG_VALUE is 1 or -1. */
8963 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8964 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8966 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8968 rtx op0 = XEXP (XEXP (x, 0), 1);
8969 rtx op1 = XEXP (XEXP (x, 1), 1);
8971 cond0 = XEXP (XEXP (x, 0), 0);
8972 cond1 = XEXP (XEXP (x, 1), 0);
8974 if (COMPARISON_P (cond0)
8975 && COMPARISON_P (cond1)
8976 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8977 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8978 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8979 || ((swap_condition (GET_CODE (cond0))
8980 == reversed_comparison_code (cond1, NULL))
8981 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8982 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8983 && ! side_effects_p (x))
8985 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8986 *pfalse = simplify_gen_binary (MULT, mode,
8988 ? simplify_gen_unary (NEG, mode,
8996 /* Similarly for MULT, AND and UMIN, except that for these the result
8998 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8999 && (code == MULT || code == AND || code == UMIN)
9000 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9002 cond0 = XEXP (XEXP (x, 0), 0);
9003 cond1 = XEXP (XEXP (x, 1), 0);
9005 if (COMPARISON_P (cond0)
9006 && COMPARISON_P (cond1)
9007 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9008 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9009 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9010 || ((swap_condition (GET_CODE (cond0))
9011 == reversed_comparison_code (cond1, NULL))
9012 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9013 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9014 && ! side_effects_p (x))
9016 *ptrue = *pfalse = const0_rtx;
9022 else if (code == IF_THEN_ELSE)
9024 /* If we have IF_THEN_ELSE already, extract the condition and
9025 canonicalize it if it is NE or EQ. */
9026 cond0 = XEXP (x, 0);
9027 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9028 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9029 return XEXP (cond0, 0);
9030 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9032 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9033 return XEXP (cond0, 0);
9039 /* If X is a SUBREG, we can narrow both the true and false values
9040 if the inner expression, if there is a condition. */
9041 else if (code == SUBREG
9042 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
9045 true0 = simplify_gen_subreg (mode, true0,
9046 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9047 false0 = simplify_gen_subreg (mode, false0,
9048 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9049 if (true0 && false0)
9057 /* If X is a constant, this isn't special and will cause confusions
9058 if we treat it as such. Likewise if it is equivalent to a constant. */
9059 else if (CONSTANT_P (x)
9060 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9063 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9064 will be least confusing to the rest of the compiler. */
9065 else if (mode == BImode)
9067 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9071 /* If X is known to be either 0 or -1, those are the true and
9072 false values when testing X. */
9073 else if (x == constm1_rtx || x == const0_rtx
9074 || (mode != VOIDmode
9075 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
9077 *ptrue = constm1_rtx, *pfalse = const0_rtx;
9081 /* Likewise for 0 or a single bit. */
9082 else if (HWI_COMPUTABLE_MODE_P (mode)
9083 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
9085 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9089 /* Otherwise fail; show no condition with true and false values the same. */
9090 *ptrue = *pfalse = x;
9094 /* Return the value of expression X given the fact that condition COND
9095 is known to be true when applied to REG as its first operand and VAL
9096 as its second. X is known to not be shared and so can be modified in
9099 We only handle the simplest cases, and specifically those cases that
9100 arise with IF_THEN_ELSE expressions. */
9103 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9105 enum rtx_code code = GET_CODE (x);
9109 if (side_effects_p (x))
9112 /* If either operand of the condition is a floating point value,
9113 then we have to avoid collapsing an EQ comparison. */
9115 && rtx_equal_p (x, reg)
9116 && ! FLOAT_MODE_P (GET_MODE (x))
9117 && ! FLOAT_MODE_P (GET_MODE (val)))
9120 if (cond == UNEQ && rtx_equal_p (x, reg))
9123 /* If X is (abs REG) and we know something about REG's relationship
9124 with zero, we may be able to simplify this. */
9126 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9129 case GE: case GT: case EQ:
9132 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9134 GET_MODE (XEXP (x, 0)));
9139 /* The only other cases we handle are MIN, MAX, and comparisons if the
9140 operands are the same as REG and VAL. */
9142 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9144 if (rtx_equal_p (XEXP (x, 0), val))
9146 std::swap (val, reg);
9147 cond = swap_condition (cond);
9150 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9152 if (COMPARISON_P (x))
9154 if (comparison_dominates_p (cond, code))
9155 return const_true_rtx;
9157 code = reversed_comparison_code (x, NULL);
9159 && comparison_dominates_p (cond, code))
9164 else if (code == SMAX || code == SMIN
9165 || code == UMIN || code == UMAX)
9167 int unsignedp = (code == UMIN || code == UMAX);
9169 /* Do not reverse the condition when it is NE or EQ.
9170 This is because we cannot conclude anything about
9171 the value of 'SMAX (x, y)' when x is not equal to y,
9172 but we can when x equals y. */
9173 if ((code == SMAX || code == UMAX)
9174 && ! (cond == EQ || cond == NE))
9175 cond = reverse_condition (cond);
9180 return unsignedp ? x : XEXP (x, 1);
9182 return unsignedp ? x : XEXP (x, 0);
9184 return unsignedp ? XEXP (x, 1) : x;
9186 return unsignedp ? XEXP (x, 0) : x;
9193 else if (code == SUBREG)
9195 machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9196 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9198 if (SUBREG_REG (x) != r)
9200 /* We must simplify subreg here, before we lose track of the
9201 original inner_mode. */
9202 new_rtx = simplify_subreg (GET_MODE (x), r,
9203 inner_mode, SUBREG_BYTE (x));
9207 SUBST (SUBREG_REG (x), r);
9212 /* We don't have to handle SIGN_EXTEND here, because even in the
9213 case of replacing something with a modeless CONST_INT, a
9214 CONST_INT is already (supposed to be) a valid sign extension for
9215 its narrower mode, which implies it's already properly
9216 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9217 story is different. */
9218 else if (code == ZERO_EXTEND)
9220 machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9221 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9223 if (XEXP (x, 0) != r)
9225 /* We must simplify the zero_extend here, before we lose
9226 track of the original inner_mode. */
9227 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9232 SUBST (XEXP (x, 0), r);
9238 fmt = GET_RTX_FORMAT (code);
9239 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9242 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9243 else if (fmt[i] == 'E')
9244 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9245 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9252 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9253 assignment as a field assignment. */
9256 rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9258 if (widen_x && GET_MODE (x) != GET_MODE (y))
9260 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (y)))
9262 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9264 /* For big endian, adjust the memory offset. */
9265 if (BYTES_BIG_ENDIAN)
9266 x = adjust_address_nv (x, GET_MODE (y),
9267 -subreg_lowpart_offset (GET_MODE (x),
9270 x = adjust_address_nv (x, GET_MODE (y), 0);
9273 if (x == y || rtx_equal_p (x, y))
9276 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9279 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9280 Note that all SUBREGs of MEM are paradoxical; otherwise they
9281 would have been rewritten. */
9282 if (MEM_P (x) && GET_CODE (y) == SUBREG
9283 && MEM_P (SUBREG_REG (y))
9284 && rtx_equal_p (SUBREG_REG (y),
9285 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9288 if (MEM_P (y) && GET_CODE (x) == SUBREG
9289 && MEM_P (SUBREG_REG (x))
9290 && rtx_equal_p (SUBREG_REG (x),
9291 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9294 /* We used to see if get_last_value of X and Y were the same but that's
9295 not correct. In one direction, we'll cause the assignment to have
9296 the wrong destination and in the case, we'll import a register into this
9297 insn that might have already have been dead. So fail if none of the
9298 above cases are true. */
9302 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9303 Return that assignment if so.
9305 We only handle the most common cases. */
9308 make_field_assignment (rtx x)
9310 rtx dest = SET_DEST (x);
9311 rtx src = SET_SRC (x);
9316 unsigned HOST_WIDE_INT len;
9320 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9321 a clear of a one-bit field. We will have changed it to
9322 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9325 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9326 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9327 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9328 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9330 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9333 return gen_rtx_SET (assign, const0_rtx);
9337 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9338 && subreg_lowpart_p (XEXP (src, 0))
9339 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9340 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9341 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9342 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9343 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9344 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9346 assign = make_extraction (VOIDmode, dest, 0,
9347 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9350 return gen_rtx_SET (assign, const0_rtx);
9354 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9356 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9357 && XEXP (XEXP (src, 0), 0) == const1_rtx
9358 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9360 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9363 return gen_rtx_SET (assign, const1_rtx);
9367 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9368 SRC is an AND with all bits of that field set, then we can discard
9370 if (GET_CODE (dest) == ZERO_EXTRACT
9371 && CONST_INT_P (XEXP (dest, 1))
9372 && GET_CODE (src) == AND
9373 && CONST_INT_P (XEXP (src, 1)))
9375 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9376 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9377 unsigned HOST_WIDE_INT ze_mask;
9379 if (width >= HOST_BITS_PER_WIDE_INT)
9382 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9384 /* Complete overlap. We can remove the source AND. */
9385 if ((and_mask & ze_mask) == ze_mask)
9386 return gen_rtx_SET (dest, XEXP (src, 0));
9388 /* Partial overlap. We can reduce the source AND. */
9389 if ((and_mask & ze_mask) != and_mask)
9391 mode = GET_MODE (src);
9392 src = gen_rtx_AND (mode, XEXP (src, 0),
9393 gen_int_mode (and_mask & ze_mask, mode));
9394 return gen_rtx_SET (dest, src);
9398 /* The other case we handle is assignments into a constant-position
9399 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9400 a mask that has all one bits except for a group of zero bits and
9401 OTHER is known to have zeros where C1 has ones, this is such an
9402 assignment. Compute the position and length from C1. Shift OTHER
9403 to the appropriate position, force it to the required mode, and
9404 make the extraction. Check for the AND in both operands. */
9406 /* One or more SUBREGs might obscure the constant-position field
9407 assignment. The first one we are likely to encounter is an outer
9408 narrowing SUBREG, which we can just strip for the purposes of
9409 identifying the constant-field assignment. */
9410 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))
9411 src = SUBREG_REG (src);
9413 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9416 rhs = expand_compound_operation (XEXP (src, 0));
9417 lhs = expand_compound_operation (XEXP (src, 1));
9419 if (GET_CODE (rhs) == AND
9420 && CONST_INT_P (XEXP (rhs, 1))
9421 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9422 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9423 /* The second SUBREG that might get in the way is a paradoxical
9424 SUBREG around the first operand of the AND. We want to
9425 pretend the operand is as wide as the destination here. We
9426 do this by adjusting the MEM to wider mode for the sole
9427 purpose of the call to rtx_equal_for_field_assignment_p. Also
9428 note this trick only works for MEMs. */
9429 else if (GET_CODE (rhs) == AND
9430 && paradoxical_subreg_p (XEXP (rhs, 0))
9431 && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9432 && CONST_INT_P (XEXP (rhs, 1))
9433 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9435 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9436 else if (GET_CODE (lhs) == AND
9437 && CONST_INT_P (XEXP (lhs, 1))
9438 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9439 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9440 /* The second SUBREG that might get in the way is a paradoxical
9441 SUBREG around the first operand of the AND. We want to
9442 pretend the operand is as wide as the destination here. We
9443 do this by adjusting the MEM to wider mode for the sole
9444 purpose of the call to rtx_equal_for_field_assignment_p. Also
9445 note this trick only works for MEMs. */
9446 else if (GET_CODE (lhs) == AND
9447 && paradoxical_subreg_p (XEXP (lhs, 0))
9448 && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9449 && CONST_INT_P (XEXP (lhs, 1))
9450 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9452 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9456 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9457 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9458 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9459 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9462 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9466 /* The mode to use for the source is the mode of the assignment, or of
9467 what is inside a possible STRICT_LOW_PART. */
9468 mode = (GET_CODE (assign) == STRICT_LOW_PART
9469 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9471 /* Shift OTHER right POS places and make it the source, restricting it
9472 to the proper length and mode. */
9474 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9478 src = force_to_mode (src, mode,
9479 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9480 ? ~(unsigned HOST_WIDE_INT) 0
9481 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9484 /* If SRC is masked by an AND that does not make a difference in
9485 the value being stored, strip it. */
9486 if (GET_CODE (assign) == ZERO_EXTRACT
9487 && CONST_INT_P (XEXP (assign, 1))
9488 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9489 && GET_CODE (src) == AND
9490 && CONST_INT_P (XEXP (src, 1))
9491 && UINTVAL (XEXP (src, 1))
9492 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9493 src = XEXP (src, 0);
9495 return gen_rtx_SET (assign, src);
9498 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9502 apply_distributive_law (rtx x)
9504 enum rtx_code code = GET_CODE (x);
9505 enum rtx_code inner_code;
9506 rtx lhs, rhs, other;
9509 /* Distributivity is not true for floating point as it can change the
9510 value. So we don't do it unless -funsafe-math-optimizations. */
9511 if (FLOAT_MODE_P (GET_MODE (x))
9512 && ! flag_unsafe_math_optimizations)
9515 /* The outer operation can only be one of the following: */
9516 if (code != IOR && code != AND && code != XOR
9517 && code != PLUS && code != MINUS)
9523 /* If either operand is a primitive we can't do anything, so get out
9525 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9528 lhs = expand_compound_operation (lhs);
9529 rhs = expand_compound_operation (rhs);
9530 inner_code = GET_CODE (lhs);
9531 if (inner_code != GET_CODE (rhs))
9534 /* See if the inner and outer operations distribute. */
9541 /* These all distribute except over PLUS. */
9542 if (code == PLUS || code == MINUS)
9547 if (code != PLUS && code != MINUS)
9552 /* This is also a multiply, so it distributes over everything. */
9555 /* This used to handle SUBREG, but this turned out to be counter-
9556 productive, since (subreg (op ...)) usually is not handled by
9557 insn patterns, and this "optimization" therefore transformed
9558 recognizable patterns into unrecognizable ones. Therefore the
9559 SUBREG case was removed from here.
9561 It is possible that distributing SUBREG over arithmetic operations
9562 leads to an intermediate result than can then be optimized further,
9563 e.g. by moving the outer SUBREG to the other side of a SET as done
9564 in simplify_set. This seems to have been the original intent of
9565 handling SUBREGs here.
9567 However, with current GCC this does not appear to actually happen,
9568 at least on major platforms. If some case is found where removing
9569 the SUBREG case here prevents follow-on optimizations, distributing
9570 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9576 /* Set LHS and RHS to the inner operands (A and B in the example
9577 above) and set OTHER to the common operand (C in the example).
9578 There is only one way to do this unless the inner operation is
9580 if (COMMUTATIVE_ARITH_P (lhs)
9581 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9582 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9583 else if (COMMUTATIVE_ARITH_P (lhs)
9584 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9585 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9586 else if (COMMUTATIVE_ARITH_P (lhs)
9587 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9588 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9589 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9590 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9594 /* Form the new inner operation, seeing if it simplifies first. */
9595 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9597 /* There is one exception to the general way of distributing:
9598 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9599 if (code == XOR && inner_code == IOR)
9602 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9605 /* We may be able to continuing distributing the result, so call
9606 ourselves recursively on the inner operation before forming the
9607 outer operation, which we return. */
9608 return simplify_gen_binary (inner_code, GET_MODE (x),
9609 apply_distributive_law (tem), other);
9612 /* See if X is of the form (* (+ A B) C), and if so convert to
9613 (+ (* A C) (* B C)) and try to simplify.
9615 Most of the time, this results in no change. However, if some of
9616 the operands are the same or inverses of each other, simplifications
9619 For example, (and (ior A B) (not B)) can occur as the result of
9620 expanding a bit field assignment. When we apply the distributive
9621 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9622 which then simplifies to (and (A (not B))).
9624 Note that no checks happen on the validity of applying the inverse
9625 distributive law. This is pointless since we can do it in the
9626 few places where this routine is called.
9628 N is the index of the term that is decomposed (the arithmetic operation,
9629 i.e. (+ A B) in the first example above). !N is the index of the term that
9630 is distributed, i.e. of C in the first example above. */
9632 distribute_and_simplify_rtx (rtx x, int n)
9635 enum rtx_code outer_code, inner_code;
9636 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9638 /* Distributivity is not true for floating point as it can change the
9639 value. So we don't do it unless -funsafe-math-optimizations. */
9640 if (FLOAT_MODE_P (GET_MODE (x))
9641 && ! flag_unsafe_math_optimizations)
9644 decomposed = XEXP (x, n);
9645 if (!ARITHMETIC_P (decomposed))
9648 mode = GET_MODE (x);
9649 outer_code = GET_CODE (x);
9650 distributed = XEXP (x, !n);
9652 inner_code = GET_CODE (decomposed);
9653 inner_op0 = XEXP (decomposed, 0);
9654 inner_op1 = XEXP (decomposed, 1);
9656 /* Special case (and (xor B C) (not A)), which is equivalent to
9657 (xor (ior A B) (ior A C)) */
9658 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9660 distributed = XEXP (distributed, 0);
9666 /* Distribute the second term. */
9667 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9668 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9672 /* Distribute the first term. */
9673 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9674 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9677 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9679 if (GET_CODE (tmp) != outer_code
9680 && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
9681 < set_src_cost (x, mode, optimize_this_for_speed_p)))
9687 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9688 in MODE. Return an equivalent form, if different from (and VAROP
9689 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9692 simplify_and_const_int_1 (machine_mode mode, rtx varop,
9693 unsigned HOST_WIDE_INT constop)
9695 unsigned HOST_WIDE_INT nonzero;
9696 unsigned HOST_WIDE_INT orig_constop;
9701 orig_constop = constop;
9702 if (GET_CODE (varop) == CLOBBER)
9705 /* Simplify VAROP knowing that we will be only looking at some of the
9708 Note by passing in CONSTOP, we guarantee that the bits not set in
9709 CONSTOP are not significant and will never be examined. We must
9710 ensure that is the case by explicitly masking out those bits
9711 before returning. */
9712 varop = force_to_mode (varop, mode, constop, 0);
9714 /* If VAROP is a CLOBBER, we will fail so return it. */
9715 if (GET_CODE (varop) == CLOBBER)
9718 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9719 to VAROP and return the new constant. */
9720 if (CONST_INT_P (varop))
9721 return gen_int_mode (INTVAL (varop) & constop, mode);
9723 /* See what bits may be nonzero in VAROP. Unlike the general case of
9724 a call to nonzero_bits, here we don't care about bits outside
9727 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9729 /* Turn off all bits in the constant that are known to already be zero.
9730 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9731 which is tested below. */
9735 /* If we don't have any bits left, return zero. */
9739 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9740 a power of two, we can replace this with an ASHIFT. */
9741 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9742 && (i = exact_log2 (constop)) >= 0)
9743 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9745 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9746 or XOR, then try to apply the distributive law. This may eliminate
9747 operations if either branch can be simplified because of the AND.
9748 It may also make some cases more complex, but those cases probably
9749 won't match a pattern either with or without this. */
9751 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9755 apply_distributive_law
9756 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9757 simplify_and_const_int (NULL_RTX,
9761 simplify_and_const_int (NULL_RTX,
9766 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9767 the AND and see if one of the operands simplifies to zero. If so, we
9768 may eliminate it. */
9770 if (GET_CODE (varop) == PLUS
9771 && exact_log2 (constop + 1) >= 0)
9775 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9776 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9777 if (o0 == const0_rtx)
9779 if (o1 == const0_rtx)
9783 /* Make a SUBREG if necessary. If we can't make it, fail. */
9784 varop = gen_lowpart (mode, varop);
9785 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9788 /* If we are only masking insignificant bits, return VAROP. */
9789 if (constop == nonzero)
9792 if (varop == orig_varop && constop == orig_constop)
9795 /* Otherwise, return an AND. */
9796 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9800 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9803 Return an equivalent form, if different from X. Otherwise, return X. If
9804 X is zero, we are to always construct the equivalent form. */
9807 simplify_and_const_int (rtx x, machine_mode mode, rtx varop,
9808 unsigned HOST_WIDE_INT constop)
9810 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9815 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9816 gen_int_mode (constop, mode));
9817 if (GET_MODE (x) != mode)
9818 x = gen_lowpart (mode, x);
9822 /* Given a REG, X, compute which bits in X can be nonzero.
9823 We don't care about bits outside of those defined in MODE.
9825 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9826 a shift, AND, or zero_extract, we can do better. */
9829 reg_nonzero_bits_for_combine (const_rtx x, machine_mode mode,
9830 const_rtx known_x ATTRIBUTE_UNUSED,
9831 machine_mode known_mode ATTRIBUTE_UNUSED,
9832 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9833 unsigned HOST_WIDE_INT *nonzero)
9838 /* If X is a register whose nonzero bits value is current, use it.
9839 Otherwise, if X is a register whose value we can find, use that
9840 value. Otherwise, use the previously-computed global nonzero bits
9841 for this register. */
9843 rsp = ®_stat[REGNO (x)];
9844 if (rsp->last_set_value != 0
9845 && (rsp->last_set_mode == mode
9846 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9847 && GET_MODE_CLASS (mode) == MODE_INT))
9848 && ((rsp->last_set_label >= label_tick_ebb_start
9849 && rsp->last_set_label < label_tick)
9850 || (rsp->last_set_label == label_tick
9851 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9852 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9853 && REGNO (x) < reg_n_sets_max
9854 && REG_N_SETS (REGNO (x)) == 1
9856 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9859 unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits;
9861 if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode))
9862 /* We don't know anything about the upper bits. */
9863 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode);
9869 tem = get_last_value (x);
9873 if (SHORT_IMMEDIATES_SIGN_EXTEND)
9874 tem = sign_extend_short_imm (tem, GET_MODE (x),
9875 GET_MODE_PRECISION (mode));
9879 else if (nonzero_sign_valid && rsp->nonzero_bits)
9881 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9883 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9884 /* We don't know anything about the upper bits. */
9885 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9893 /* Return the number of bits at the high-order end of X that are known to
9894 be equal to the sign bit. X will be used in mode MODE; if MODE is
9895 VOIDmode, X will be used in its own mode. The returned value will always
9896 be between 1 and the number of bits in MODE. */
9899 reg_num_sign_bit_copies_for_combine (const_rtx x, machine_mode mode,
9900 const_rtx known_x ATTRIBUTE_UNUSED,
9901 machine_mode known_mode
9903 unsigned int known_ret ATTRIBUTE_UNUSED,
9904 unsigned int *result)
9909 rsp = ®_stat[REGNO (x)];
9910 if (rsp->last_set_value != 0
9911 && rsp->last_set_mode == mode
9912 && ((rsp->last_set_label >= label_tick_ebb_start
9913 && rsp->last_set_label < label_tick)
9914 || (rsp->last_set_label == label_tick
9915 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9916 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9917 && REGNO (x) < reg_n_sets_max
9918 && REG_N_SETS (REGNO (x)) == 1
9920 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9923 *result = rsp->last_set_sign_bit_copies;
9927 tem = get_last_value (x);
9931 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9932 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9933 *result = rsp->sign_bit_copies;
9938 /* Return the number of "extended" bits there are in X, when interpreted
9939 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9940 unsigned quantities, this is the number of high-order zero bits.
9941 For signed quantities, this is the number of copies of the sign bit
9942 minus 1. In both case, this function returns the number of "spare"
9943 bits. For example, if two quantities for which this function returns
9944 at least 1 are added, the addition is known not to overflow.
9946 This function will always return 0 unless called during combine, which
9947 implies that it must be called from a define_split. */
9950 extended_count (const_rtx x, machine_mode mode, int unsignedp)
9952 if (nonzero_sign_valid == 0)
9956 ? (HWI_COMPUTABLE_MODE_P (mode)
9957 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9958 - floor_log2 (nonzero_bits (x, mode)))
9960 : num_sign_bit_copies (x, mode) - 1);
9963 /* This function is called from `simplify_shift_const' to merge two
9964 outer operations. Specifically, we have already found that we need
9965 to perform operation *POP0 with constant *PCONST0 at the outermost
9966 position. We would now like to also perform OP1 with constant CONST1
9967 (with *POP0 being done last).
9969 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9970 the resulting operation. *PCOMP_P is set to 1 if we would need to
9971 complement the innermost operand, otherwise it is unchanged.
9973 MODE is the mode in which the operation will be done. No bits outside
9974 the width of this mode matter. It is assumed that the width of this mode
9975 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9977 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9978 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9979 result is simply *PCONST0.
9981 If the resulting operation cannot be expressed as one operation, we
9982 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9985 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9987 enum rtx_code op0 = *pop0;
9988 HOST_WIDE_INT const0 = *pconst0;
9990 const0 &= GET_MODE_MASK (mode);
9991 const1 &= GET_MODE_MASK (mode);
9993 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9997 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10000 if (op1 == UNKNOWN || op0 == SET)
10003 else if (op0 == UNKNOWN)
10004 op0 = op1, const0 = const1;
10006 else if (op0 == op1)
10030 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10031 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10034 /* If the two constants aren't the same, we can't do anything. The
10035 remaining six cases can all be done. */
10036 else if (const0 != const1)
10044 /* (a & b) | b == b */
10046 else /* op1 == XOR */
10047 /* (a ^ b) | b == a | b */
10053 /* (a & b) ^ b == (~a) & b */
10054 op0 = AND, *pcomp_p = 1;
10055 else /* op1 == IOR */
10056 /* (a | b) ^ b == a & ~b */
10057 op0 = AND, const0 = ~const0;
10062 /* (a | b) & b == b */
10064 else /* op1 == XOR */
10065 /* (a ^ b) & b) == (~a) & b */
10072 /* Check for NO-OP cases. */
10073 const0 &= GET_MODE_MASK (mode);
10075 && (op0 == IOR || op0 == XOR || op0 == PLUS))
10077 else if (const0 == 0 && op0 == AND)
10079 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10085 /* ??? Slightly redundant with the above mask, but not entirely.
10086 Moving this above means we'd have to sign-extend the mode mask
10087 for the final test. */
10088 if (op0 != UNKNOWN && op0 != NEG)
10089 *pconst0 = trunc_int_for_mode (const0, mode);
10094 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10095 the shift in. The original shift operation CODE is performed on OP in
10096 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10097 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10098 result of the shift is subject to operation OUTER_CODE with operand
10101 static machine_mode
10102 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10103 machine_mode orig_mode, machine_mode mode,
10104 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10106 if (orig_mode == mode)
10108 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10110 /* In general we can't perform in wider mode for right shift and rotate. */
10114 /* We can still widen if the bits brought in from the left are identical
10115 to the sign bit of ORIG_MODE. */
10116 if (num_sign_bit_copies (op, mode)
10117 > (unsigned) (GET_MODE_PRECISION (mode)
10118 - GET_MODE_PRECISION (orig_mode)))
10123 /* Similarly here but with zero bits. */
10124 if (HWI_COMPUTABLE_MODE_P (mode)
10125 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10128 /* We can also widen if the bits brought in will be masked off. This
10129 operation is performed in ORIG_MODE. */
10130 if (outer_code == AND)
10132 int care_bits = low_bitmask_len (orig_mode, outer_const);
10135 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10144 gcc_unreachable ();
10151 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10152 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10153 if we cannot simplify it. Otherwise, return a simplified value.
10155 The shift is normally computed in the widest mode we find in VAROP, as
10156 long as it isn't a different number of words than RESULT_MODE. Exceptions
10157 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10160 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10161 rtx varop, int orig_count)
10163 enum rtx_code orig_code = code;
10164 rtx orig_varop = varop;
10166 machine_mode mode = result_mode;
10167 machine_mode shift_mode, tmode;
10168 unsigned int mode_words
10169 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
10170 /* We form (outer_op (code varop count) (outer_const)). */
10171 enum rtx_code outer_op = UNKNOWN;
10172 HOST_WIDE_INT outer_const = 0;
10173 int complement_p = 0;
10176 /* Make sure and truncate the "natural" shift on the way in. We don't
10177 want to do this inside the loop as it makes it more difficult to
10179 if (SHIFT_COUNT_TRUNCATED)
10180 orig_count &= GET_MODE_BITSIZE (mode) - 1;
10182 /* If we were given an invalid count, don't do anything except exactly
10183 what was requested. */
10185 if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
10188 count = orig_count;
10190 /* Unless one of the branches of the `if' in this loop does a `continue',
10191 we will `break' the loop after the `if'. */
10195 /* If we have an operand of (clobber (const_int 0)), fail. */
10196 if (GET_CODE (varop) == CLOBBER)
10199 /* Convert ROTATERT to ROTATE. */
10200 if (code == ROTATERT)
10202 unsigned int bitsize = GET_MODE_PRECISION (result_mode);
10204 if (VECTOR_MODE_P (result_mode))
10205 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
10207 count = bitsize - count;
10210 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
10211 mode, outer_op, outer_const);
10213 /* Handle cases where the count is greater than the size of the mode
10214 minus 1. For ASHIFT, use the size minus one as the count (this can
10215 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10216 take the count modulo the size. For other shifts, the result is
10219 Since these shifts are being produced by the compiler by combining
10220 multiple operations, each of which are defined, we know what the
10221 result is supposed to be. */
10223 if (count > (GET_MODE_PRECISION (shift_mode) - 1))
10225 if (code == ASHIFTRT)
10226 count = GET_MODE_PRECISION (shift_mode) - 1;
10227 else if (code == ROTATE || code == ROTATERT)
10228 count %= GET_MODE_PRECISION (shift_mode);
10231 /* We can't simply return zero because there may be an
10233 varop = const0_rtx;
10239 /* If we discovered we had to complement VAROP, leave. Making a NOT
10240 here would cause an infinite loop. */
10244 /* An arithmetic right shift of a quantity known to be -1 or 0
10246 if (code == ASHIFTRT
10247 && (num_sign_bit_copies (varop, shift_mode)
10248 == GET_MODE_PRECISION (shift_mode)))
10254 /* If we are doing an arithmetic right shift and discarding all but
10255 the sign bit copies, this is equivalent to doing a shift by the
10256 bitsize minus one. Convert it into that shift because it will often
10257 allow other simplifications. */
10259 if (code == ASHIFTRT
10260 && (count + num_sign_bit_copies (varop, shift_mode)
10261 >= GET_MODE_PRECISION (shift_mode)))
10262 count = GET_MODE_PRECISION (shift_mode) - 1;
10264 /* We simplify the tests below and elsewhere by converting
10265 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10266 `make_compound_operation' will convert it to an ASHIFTRT for
10267 those machines (such as VAX) that don't have an LSHIFTRT. */
10268 if (code == ASHIFTRT
10269 && val_signbit_known_clear_p (shift_mode,
10270 nonzero_bits (varop, shift_mode)))
10273 if (((code == LSHIFTRT
10274 && HWI_COMPUTABLE_MODE_P (shift_mode)
10275 && !(nonzero_bits (varop, shift_mode) >> count))
10277 && HWI_COMPUTABLE_MODE_P (shift_mode)
10278 && !((nonzero_bits (varop, shift_mode) << count)
10279 & GET_MODE_MASK (shift_mode))))
10280 && !side_effects_p (varop))
10281 varop = const0_rtx;
10283 switch (GET_CODE (varop))
10289 new_rtx = expand_compound_operation (varop);
10290 if (new_rtx != varop)
10298 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10299 minus the width of a smaller mode, we can do this with a
10300 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10301 if ((code == ASHIFTRT || code == LSHIFTRT)
10302 && ! mode_dependent_address_p (XEXP (varop, 0),
10303 MEM_ADDR_SPACE (varop))
10304 && ! MEM_VOLATILE_P (varop)
10305 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
10306 MODE_INT, 1)) != BLKmode)
10308 new_rtx = adjust_address_nv (varop, tmode,
10309 BYTES_BIG_ENDIAN ? 0
10310 : count / BITS_PER_UNIT);
10312 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10313 : ZERO_EXTEND, mode, new_rtx);
10320 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10321 the same number of words as what we've seen so far. Then store
10322 the widest mode in MODE. */
10323 if (subreg_lowpart_p (varop)
10324 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10325 > GET_MODE_SIZE (GET_MODE (varop)))
10326 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10327 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10329 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10330 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10332 varop = SUBREG_REG (varop);
10333 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10334 mode = GET_MODE (varop);
10340 /* Some machines use MULT instead of ASHIFT because MULT
10341 is cheaper. But it is still better on those machines to
10342 merge two shifts into one. */
10343 if (CONST_INT_P (XEXP (varop, 1))
10344 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10347 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10349 GEN_INT (exact_log2 (
10350 UINTVAL (XEXP (varop, 1)))));
10356 /* Similar, for when divides are cheaper. */
10357 if (CONST_INT_P (XEXP (varop, 1))
10358 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10361 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10363 GEN_INT (exact_log2 (
10364 UINTVAL (XEXP (varop, 1)))));
10370 /* If we are extracting just the sign bit of an arithmetic
10371 right shift, that shift is not needed. However, the sign
10372 bit of a wider mode may be different from what would be
10373 interpreted as the sign bit in a narrower mode, so, if
10374 the result is narrower, don't discard the shift. */
10375 if (code == LSHIFTRT
10376 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10377 && (GET_MODE_BITSIZE (result_mode)
10378 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10380 varop = XEXP (varop, 0);
10389 /* Here we have two nested shifts. The result is usually the
10390 AND of a new shift with a mask. We compute the result below. */
10391 if (CONST_INT_P (XEXP (varop, 1))
10392 && INTVAL (XEXP (varop, 1)) >= 0
10393 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10394 && HWI_COMPUTABLE_MODE_P (result_mode)
10395 && HWI_COMPUTABLE_MODE_P (mode)
10396 && !VECTOR_MODE_P (result_mode))
10398 enum rtx_code first_code = GET_CODE (varop);
10399 unsigned int first_count = INTVAL (XEXP (varop, 1));
10400 unsigned HOST_WIDE_INT mask;
10403 /* We have one common special case. We can't do any merging if
10404 the inner code is an ASHIFTRT of a smaller mode. However, if
10405 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10406 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10407 we can convert it to
10408 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10409 This simplifies certain SIGN_EXTEND operations. */
10410 if (code == ASHIFT && first_code == ASHIFTRT
10411 && count == (GET_MODE_PRECISION (result_mode)
10412 - GET_MODE_PRECISION (GET_MODE (varop))))
10414 /* C3 has the low-order C1 bits zero. */
10416 mask = GET_MODE_MASK (mode)
10417 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10419 varop = simplify_and_const_int (NULL_RTX, result_mode,
10420 XEXP (varop, 0), mask);
10421 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10423 count = first_count;
10428 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10429 than C1 high-order bits equal to the sign bit, we can convert
10430 this to either an ASHIFT or an ASHIFTRT depending on the
10433 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10435 if (code == ASHIFTRT && first_code == ASHIFT
10436 && GET_MODE (varop) == shift_mode
10437 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10440 varop = XEXP (varop, 0);
10441 count -= first_count;
10451 /* There are some cases we can't do. If CODE is ASHIFTRT,
10452 we can only do this if FIRST_CODE is also ASHIFTRT.
10454 We can't do the case when CODE is ROTATE and FIRST_CODE is
10457 If the mode of this shift is not the mode of the outer shift,
10458 we can't do this if either shift is a right shift or ROTATE.
10460 Finally, we can't do any of these if the mode is too wide
10461 unless the codes are the same.
10463 Handle the case where the shift codes are the same
10466 if (code == first_code)
10468 if (GET_MODE (varop) != result_mode
10469 && (code == ASHIFTRT || code == LSHIFTRT
10470 || code == ROTATE))
10473 count += first_count;
10474 varop = XEXP (varop, 0);
10478 if (code == ASHIFTRT
10479 || (code == ROTATE && first_code == ASHIFTRT)
10480 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10481 || (GET_MODE (varop) != result_mode
10482 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10483 || first_code == ROTATE
10484 || code == ROTATE)))
10487 /* To compute the mask to apply after the shift, shift the
10488 nonzero bits of the inner shift the same way the
10489 outer shift will. */
10491 mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10495 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10498 /* Give up if we can't compute an outer operation to use. */
10500 || !CONST_INT_P (mask_rtx)
10501 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10503 result_mode, &complement_p))
10506 /* If the shifts are in the same direction, we add the
10507 counts. Otherwise, we subtract them. */
10508 if ((code == ASHIFTRT || code == LSHIFTRT)
10509 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10510 count += first_count;
10512 count -= first_count;
10514 /* If COUNT is positive, the new shift is usually CODE,
10515 except for the two exceptions below, in which case it is
10516 FIRST_CODE. If the count is negative, FIRST_CODE should
10519 && ((first_code == ROTATE && code == ASHIFT)
10520 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10522 else if (count < 0)
10523 code = first_code, count = -count;
10525 varop = XEXP (varop, 0);
10529 /* If we have (A << B << C) for any shift, we can convert this to
10530 (A << C << B). This wins if A is a constant. Only try this if
10531 B is not a constant. */
10533 else if (GET_CODE (varop) == code
10534 && CONST_INT_P (XEXP (varop, 0))
10535 && !CONST_INT_P (XEXP (varop, 1)))
10537 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10538 sure the result will be masked. See PR70222. */
10539 if (code == LSHIFTRT
10540 && mode != result_mode
10541 && !merge_outer_ops (&outer_op, &outer_const, AND,
10542 GET_MODE_MASK (result_mode)
10543 >> orig_count, result_mode,
10546 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10547 up outer sign extension (often left and right shift) is
10548 hardly more efficient than the original. See PR70429. */
10549 if (code == ASHIFTRT && mode != result_mode)
10552 rtx new_rtx = simplify_const_binary_operation (code, mode,
10555 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10562 if (VECTOR_MODE_P (mode))
10565 /* Make this fit the case below. */
10566 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10572 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10573 with C the size of VAROP - 1 and the shift is logical if
10574 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10575 we have an (le X 0) operation. If we have an arithmetic shift
10576 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10577 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10579 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10580 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10581 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10582 && (code == LSHIFTRT || code == ASHIFTRT)
10583 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10584 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10587 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10590 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10591 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10596 /* If we have (shift (logical)), move the logical to the outside
10597 to allow it to possibly combine with another logical and the
10598 shift to combine with another shift. This also canonicalizes to
10599 what a ZERO_EXTRACT looks like. Also, some machines have
10600 (and (shift)) insns. */
10602 if (CONST_INT_P (XEXP (varop, 1))
10603 /* We can't do this if we have (ashiftrt (xor)) and the
10604 constant has its sign bit set in shift_mode with shift_mode
10605 wider than result_mode. */
10606 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10607 && result_mode != shift_mode
10608 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10610 && (new_rtx = simplify_const_binary_operation
10611 (code, result_mode,
10612 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10613 GEN_INT (count))) != 0
10614 && CONST_INT_P (new_rtx)
10615 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10616 INTVAL (new_rtx), result_mode, &complement_p))
10618 varop = XEXP (varop, 0);
10622 /* If we can't do that, try to simplify the shift in each arm of the
10623 logical expression, make a new logical expression, and apply
10624 the inverse distributive law. This also can't be done for
10625 (ashiftrt (xor)) where we've widened the shift and the constant
10626 changes the sign bit. */
10627 if (CONST_INT_P (XEXP (varop, 1))
10628 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10629 && result_mode != shift_mode
10630 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10633 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10634 XEXP (varop, 0), count);
10635 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10636 XEXP (varop, 1), count);
10638 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10640 varop = apply_distributive_law (varop);
10648 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10649 says that the sign bit can be tested, FOO has mode MODE, C is
10650 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10651 that may be nonzero. */
10652 if (code == LSHIFTRT
10653 && XEXP (varop, 1) == const0_rtx
10654 && GET_MODE (XEXP (varop, 0)) == result_mode
10655 && count == (GET_MODE_PRECISION (result_mode) - 1)
10656 && HWI_COMPUTABLE_MODE_P (result_mode)
10657 && STORE_FLAG_VALUE == -1
10658 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10659 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10662 varop = XEXP (varop, 0);
10669 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10670 than the number of bits in the mode is equivalent to A. */
10671 if (code == LSHIFTRT
10672 && count == (GET_MODE_PRECISION (result_mode) - 1)
10673 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10675 varop = XEXP (varop, 0);
10680 /* NEG commutes with ASHIFT since it is multiplication. Move the
10681 NEG outside to allow shifts to combine. */
10683 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10686 varop = XEXP (varop, 0);
10692 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10693 is one less than the number of bits in the mode is
10694 equivalent to (xor A 1). */
10695 if (code == LSHIFTRT
10696 && count == (GET_MODE_PRECISION (result_mode) - 1)
10697 && XEXP (varop, 1) == constm1_rtx
10698 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10699 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10703 varop = XEXP (varop, 0);
10707 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10708 that might be nonzero in BAR are those being shifted out and those
10709 bits are known zero in FOO, we can replace the PLUS with FOO.
10710 Similarly in the other operand order. This code occurs when
10711 we are computing the size of a variable-size array. */
10713 if ((code == ASHIFTRT || code == LSHIFTRT)
10714 && count < HOST_BITS_PER_WIDE_INT
10715 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10716 && (nonzero_bits (XEXP (varop, 1), result_mode)
10717 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10719 varop = XEXP (varop, 0);
10722 else if ((code == ASHIFTRT || code == LSHIFTRT)
10723 && count < HOST_BITS_PER_WIDE_INT
10724 && HWI_COMPUTABLE_MODE_P (result_mode)
10725 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10727 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10728 & nonzero_bits (XEXP (varop, 1),
10731 varop = XEXP (varop, 1);
10735 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10737 && CONST_INT_P (XEXP (varop, 1))
10738 && (new_rtx = simplify_const_binary_operation
10739 (ASHIFT, result_mode,
10740 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10741 GEN_INT (count))) != 0
10742 && CONST_INT_P (new_rtx)
10743 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10744 INTVAL (new_rtx), result_mode, &complement_p))
10746 varop = XEXP (varop, 0);
10750 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10751 signbit', and attempt to change the PLUS to an XOR and move it to
10752 the outer operation as is done above in the AND/IOR/XOR case
10753 leg for shift(logical). See details in logical handling above
10754 for reasoning in doing so. */
10755 if (code == LSHIFTRT
10756 && CONST_INT_P (XEXP (varop, 1))
10757 && mode_signbit_p (result_mode, XEXP (varop, 1))
10758 && (new_rtx = simplify_const_binary_operation
10759 (code, result_mode,
10760 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10761 GEN_INT (count))) != 0
10762 && CONST_INT_P (new_rtx)
10763 && merge_outer_ops (&outer_op, &outer_const, XOR,
10764 INTVAL (new_rtx), result_mode, &complement_p))
10766 varop = XEXP (varop, 0);
10773 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10774 with C the size of VAROP - 1 and the shift is logical if
10775 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10776 we have a (gt X 0) operation. If the shift is arithmetic with
10777 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10778 we have a (neg (gt X 0)) operation. */
10780 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10781 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10782 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10783 && (code == LSHIFTRT || code == ASHIFTRT)
10784 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10785 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10786 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10789 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10792 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10793 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10800 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10801 if the truncate does not affect the value. */
10802 if (code == LSHIFTRT
10803 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10804 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10805 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10806 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10807 - GET_MODE_PRECISION (GET_MODE (varop)))))
10809 rtx varop_inner = XEXP (varop, 0);
10812 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10813 XEXP (varop_inner, 0),
10815 (count + INTVAL (XEXP (varop_inner, 1))));
10816 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10829 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10830 outer_op, outer_const);
10832 /* We have now finished analyzing the shift. The result should be
10833 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10834 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10835 to the result of the shift. OUTER_CONST is the relevant constant,
10836 but we must turn off all bits turned off in the shift. */
10838 if (outer_op == UNKNOWN
10839 && orig_code == code && orig_count == count
10840 && varop == orig_varop
10841 && shift_mode == GET_MODE (varop))
10844 /* Make a SUBREG if necessary. If we can't make it, fail. */
10845 varop = gen_lowpart (shift_mode, varop);
10846 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10849 /* If we have an outer operation and we just made a shift, it is
10850 possible that we could have simplified the shift were it not
10851 for the outer operation. So try to do the simplification
10854 if (outer_op != UNKNOWN)
10855 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10860 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10862 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10863 turn off all the bits that the shift would have turned off. */
10864 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10865 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10866 GET_MODE_MASK (result_mode) >> orig_count);
10868 /* Do the remainder of the processing in RESULT_MODE. */
10869 x = gen_lowpart_or_truncate (result_mode, x);
10871 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10874 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10876 if (outer_op != UNKNOWN)
10878 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10879 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10880 outer_const = trunc_int_for_mode (outer_const, result_mode);
10882 if (outer_op == AND)
10883 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10884 else if (outer_op == SET)
10886 /* This means that we have determined that the result is
10887 equivalent to a constant. This should be rare. */
10888 if (!side_effects_p (x))
10889 x = GEN_INT (outer_const);
10891 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10892 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10894 x = simplify_gen_binary (outer_op, result_mode, x,
10895 GEN_INT (outer_const));
10901 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10902 The result of the shift is RESULT_MODE. If we cannot simplify it,
10903 return X or, if it is NULL, synthesize the expression with
10904 simplify_gen_binary. Otherwise, return a simplified value.
10906 The shift is normally computed in the widest mode we find in VAROP, as
10907 long as it isn't a different number of words than RESULT_MODE. Exceptions
10908 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10911 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
10912 rtx varop, int count)
10914 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10919 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10920 if (GET_MODE (x) != result_mode)
10921 x = gen_lowpart (result_mode, x);
10926 /* A subroutine of recog_for_combine. See there for arguments and
10930 recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
10932 rtx pat = *pnewpat;
10933 rtx pat_without_clobbers;
10934 int insn_code_number;
10935 int num_clobbers_to_add = 0;
10937 rtx notes = NULL_RTX;
10938 rtx old_notes, old_pat;
10941 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10942 we use to indicate that something didn't match. If we find such a
10943 thing, force rejection. */
10944 if (GET_CODE (pat) == PARALLEL)
10945 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10946 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10947 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10950 old_pat = PATTERN (insn);
10951 old_notes = REG_NOTES (insn);
10952 PATTERN (insn) = pat;
10953 REG_NOTES (insn) = NULL_RTX;
10955 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10956 if (dump_file && (dump_flags & TDF_DETAILS))
10958 if (insn_code_number < 0)
10959 fputs ("Failed to match this instruction:\n", dump_file);
10961 fputs ("Successfully matched this instruction:\n", dump_file);
10962 print_rtl_single (dump_file, pat);
10965 /* If it isn't, there is the possibility that we previously had an insn
10966 that clobbered some register as a side effect, but the combined
10967 insn doesn't need to do that. So try once more without the clobbers
10968 unless this represents an ASM insn. */
10970 if (insn_code_number < 0 && ! check_asm_operands (pat)
10971 && GET_CODE (pat) == PARALLEL)
10975 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10976 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10979 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10983 SUBST_INT (XVECLEN (pat, 0), pos);
10986 pat = XVECEXP (pat, 0, 0);
10988 PATTERN (insn) = pat;
10989 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10990 if (dump_file && (dump_flags & TDF_DETAILS))
10992 if (insn_code_number < 0)
10993 fputs ("Failed to match this instruction:\n", dump_file);
10995 fputs ("Successfully matched this instruction:\n", dump_file);
10996 print_rtl_single (dump_file, pat);
11000 pat_without_clobbers = pat;
11002 PATTERN (insn) = old_pat;
11003 REG_NOTES (insn) = old_notes;
11005 /* Recognize all noop sets, these will be killed by followup pass. */
11006 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11007 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11009 /* If we had any clobbers to add, make a new pattern than contains
11010 them. Then check to make sure that all of them are dead. */
11011 if (num_clobbers_to_add)
11013 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11014 rtvec_alloc (GET_CODE (pat) == PARALLEL
11015 ? (XVECLEN (pat, 0)
11016 + num_clobbers_to_add)
11017 : num_clobbers_to_add + 1));
11019 if (GET_CODE (pat) == PARALLEL)
11020 for (i = 0; i < XVECLEN (pat, 0); i++)
11021 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11023 XVECEXP (newpat, 0, 0) = pat;
11025 add_clobbers (newpat, insn_code_number);
11027 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11028 i < XVECLEN (newpat, 0); i++)
11030 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11031 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11033 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11035 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11036 notes = alloc_reg_note (REG_UNUSED,
11037 XEXP (XVECEXP (newpat, 0, i), 0), notes);
11043 if (insn_code_number >= 0
11044 && insn_code_number != NOOP_MOVE_INSN_CODE)
11046 old_pat = PATTERN (insn);
11047 old_notes = REG_NOTES (insn);
11048 old_icode = INSN_CODE (insn);
11049 PATTERN (insn) = pat;
11050 REG_NOTES (insn) = notes;
11052 /* Allow targets to reject combined insn. */
11053 if (!targetm.legitimate_combined_insn (insn))
11055 if (dump_file && (dump_flags & TDF_DETAILS))
11056 fputs ("Instruction not appropriate for target.",
11059 /* Callers expect recog_for_combine to strip
11060 clobbers from the pattern on failure. */
11061 pat = pat_without_clobbers;
11064 insn_code_number = -1;
11067 PATTERN (insn) = old_pat;
11068 REG_NOTES (insn) = old_notes;
11069 INSN_CODE (insn) = old_icode;
11075 return insn_code_number;
11078 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11079 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11080 Return whether anything was so changed. */
11083 change_zero_ext (rtx *src)
11085 bool changed = false;
11087 subrtx_ptr_iterator::array_type array;
11088 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11091 machine_mode mode = GET_MODE (x);
11094 if (GET_CODE (x) == ZERO_EXTRACT
11095 && CONST_INT_P (XEXP (x, 1))
11096 && CONST_INT_P (XEXP (x, 2))
11097 && GET_MODE (XEXP (x, 0)) == mode)
11099 size = INTVAL (XEXP (x, 1));
11101 int start = INTVAL (XEXP (x, 2));
11102 if (BITS_BIG_ENDIAN)
11103 start = GET_MODE_PRECISION (mode) - size - start;
11105 x = simplify_gen_binary (LSHIFTRT, mode,
11106 XEXP (x, 0), GEN_INT (start));
11108 else if (GET_CODE (x) == ZERO_EXTEND
11109 && GET_CODE (XEXP (x, 0)) == SUBREG
11110 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
11111 && subreg_lowpart_p (XEXP (x, 0)))
11113 size = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
11114 x = SUBREG_REG (XEXP (x, 0));
11119 unsigned HOST_WIDE_INT mask = 1;
11123 x = gen_rtx_AND (mode, x, GEN_INT (mask));
11132 /* Like recog, but we receive the address of a pointer to a new pattern.
11133 We try to match the rtx that the pointer points to.
11134 If that fails, we may try to modify or replace the pattern,
11135 storing the replacement into the same pointer object.
11137 Modifications include deletion or addition of CLOBBERs. If the
11138 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11139 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11140 (and undo if that fails).
11142 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11143 the CLOBBERs are placed.
11145 The value is the final insn code from the pattern ultimately matched,
11149 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11151 rtx pat = PATTERN (insn);
11152 int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11153 if (insn_code_number >= 0 || check_asm_operands (pat))
11154 return insn_code_number;
11156 void *marker = get_undo_marker ();
11157 bool changed = false;
11159 if (GET_CODE (pat) == SET)
11160 changed = change_zero_ext (&SET_SRC (pat));
11161 else if (GET_CODE (pat) == PARALLEL)
11164 for (i = 0; i < XVECLEN (pat, 0); i++)
11166 rtx set = XVECEXP (pat, 0, i);
11167 if (GET_CODE (set) == SET)
11168 changed |= change_zero_ext (&SET_SRC (set));
11174 insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11176 if (insn_code_number < 0)
11177 undo_to_marker (marker);
11180 return insn_code_number;
11183 /* Like gen_lowpart_general but for use by combine. In combine it
11184 is not possible to create any new pseudoregs. However, it is
11185 safe to create invalid memory addresses, because combine will
11186 try to recognize them and all they will do is make the combine
11189 If for some reason this cannot do its job, an rtx
11190 (clobber (const_int 0)) is returned.
11191 An insn containing that will not be recognized. */
11194 gen_lowpart_for_combine (machine_mode omode, rtx x)
11196 machine_mode imode = GET_MODE (x);
11197 unsigned int osize = GET_MODE_SIZE (omode);
11198 unsigned int isize = GET_MODE_SIZE (imode);
11201 if (omode == imode)
11204 /* We can only support MODE being wider than a word if X is a
11205 constant integer or has a mode the same size. */
11206 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
11207 && ! (CONST_SCALAR_INT_P (x) || isize == osize))
11210 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11211 won't know what to do. So we will strip off the SUBREG here and
11212 process normally. */
11213 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11215 x = SUBREG_REG (x);
11217 /* For use in case we fall down into the address adjustments
11218 further below, we need to adjust the known mode and size of
11219 x; imode and isize, since we just adjusted x. */
11220 imode = GET_MODE (x);
11222 if (imode == omode)
11225 isize = GET_MODE_SIZE (imode);
11228 result = gen_lowpart_common (omode, x);
11237 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11239 if (MEM_VOLATILE_P (x)
11240 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11243 /* If we want to refer to something bigger than the original memref,
11244 generate a paradoxical subreg instead. That will force a reload
11245 of the original memref X. */
11247 return gen_rtx_SUBREG (omode, x, 0);
11249 if (WORDS_BIG_ENDIAN)
11250 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
11252 /* Adjust the address so that the address-after-the-data is
11254 if (BYTES_BIG_ENDIAN)
11255 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
11257 return adjust_address_nv (x, omode, offset);
11260 /* If X is a comparison operator, rewrite it in a new mode. This
11261 probably won't match, but may allow further simplifications. */
11262 else if (COMPARISON_P (x))
11263 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11265 /* If we couldn't simplify X any other way, just enclose it in a
11266 SUBREG. Normally, this SUBREG won't match, but some patterns may
11267 include an explicit SUBREG or we may simplify it further in combine. */
11272 if (imode == VOIDmode)
11274 imode = int_mode_for_mode (omode);
11275 x = gen_lowpart_common (imode, x);
11279 res = lowpart_subreg (omode, x, imode);
11285 return gen_rtx_CLOBBER (omode, const0_rtx);
11288 /* Try to simplify a comparison between OP0 and a constant OP1,
11289 where CODE is the comparison code that will be tested, into a
11290 (CODE OP0 const0_rtx) form.
11292 The result is a possibly different comparison code to use.
11293 *POP1 may be updated. */
11295 static enum rtx_code
11296 simplify_compare_const (enum rtx_code code, machine_mode mode,
11297 rtx op0, rtx *pop1)
11299 unsigned int mode_width = GET_MODE_PRECISION (mode);
11300 HOST_WIDE_INT const_op = INTVAL (*pop1);
11302 /* Get the constant we are comparing against and turn off all bits
11303 not on in our mode. */
11304 if (mode != VOIDmode)
11305 const_op = trunc_int_for_mode (const_op, mode);
11307 /* If we are comparing against a constant power of two and the value
11308 being compared can only have that single bit nonzero (e.g., it was
11309 `and'ed with that bit), we can replace this with a comparison
11312 && (code == EQ || code == NE || code == GE || code == GEU
11313 || code == LT || code == LTU)
11314 && mode_width - 1 < HOST_BITS_PER_WIDE_INT
11315 && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
11316 && (nonzero_bits (op0, mode)
11317 == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
11319 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11323 /* Similarly, if we are comparing a value known to be either -1 or
11324 0 with -1, change it to the opposite comparison against zero. */
11326 && (code == EQ || code == NE || code == GT || code == LE
11327 || code == GEU || code == LTU)
11328 && num_sign_bit_copies (op0, mode) == mode_width)
11330 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11334 /* Do some canonicalizations based on the comparison code. We prefer
11335 comparisons against zero and then prefer equality comparisons.
11336 If we can reduce the size of a constant, we will do that too. */
11340 /* < C is equivalent to <= (C - 1) */
11345 /* ... fall through to LE case below. */
11351 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11358 /* If we are doing a <= 0 comparison on a value known to have
11359 a zero sign bit, we can replace this with == 0. */
11360 else if (const_op == 0
11361 && mode_width - 1 < HOST_BITS_PER_WIDE_INT
11362 && (nonzero_bits (op0, mode)
11363 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11369 /* >= C is equivalent to > (C - 1). */
11374 /* ... fall through to GT below. */
11380 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11387 /* If we are doing a > 0 comparison on a value known to have
11388 a zero sign bit, we can replace this with != 0. */
11389 else if (const_op == 0
11390 && mode_width - 1 < HOST_BITS_PER_WIDE_INT
11391 && (nonzero_bits (op0, mode)
11392 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11398 /* < C is equivalent to <= (C - 1). */
11403 /* ... fall through ... */
11405 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11406 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11407 && (unsigned HOST_WIDE_INT) const_op
11408 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11418 /* unsigned <= 0 is equivalent to == 0 */
11421 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11422 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11423 && (unsigned HOST_WIDE_INT) const_op
11424 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11432 /* >= C is equivalent to > (C - 1). */
11437 /* ... fall through ... */
11440 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11441 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11442 && (unsigned HOST_WIDE_INT) const_op
11443 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11453 /* unsigned > 0 is equivalent to != 0 */
11456 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11457 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11458 && (unsigned HOST_WIDE_INT) const_op
11459 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11470 *pop1 = GEN_INT (const_op);
11474 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11475 comparison code that will be tested.
11477 The result is a possibly different comparison code to use. *POP0 and
11478 *POP1 may be updated.
11480 It is possible that we might detect that a comparison is either always
11481 true or always false. However, we do not perform general constant
11482 folding in combine, so this knowledge isn't useful. Such tautologies
11483 should have been detected earlier. Hence we ignore all such cases. */
11485 static enum rtx_code
11486 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11492 machine_mode mode, tmode;
11494 /* Try a few ways of applying the same transformation to both operands. */
11497 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11498 so check specially. */
11499 if (!WORD_REGISTER_OPERATIONS
11500 && code != GTU && code != GEU && code != LTU && code != LEU
11501 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11502 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11503 && GET_CODE (XEXP (op1, 0)) == ASHIFT
11504 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11505 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11506 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11507 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11508 && CONST_INT_P (XEXP (op0, 1))
11509 && XEXP (op0, 1) == XEXP (op1, 1)
11510 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11511 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11512 && (INTVAL (XEXP (op0, 1))
11513 == (GET_MODE_PRECISION (GET_MODE (op0))
11514 - (GET_MODE_PRECISION
11515 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11517 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11518 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11521 /* If both operands are the same constant shift, see if we can ignore the
11522 shift. We can if the shift is a rotate or if the bits shifted out of
11523 this shift are known to be zero for both inputs and if the type of
11524 comparison is compatible with the shift. */
11525 if (GET_CODE (op0) == GET_CODE (op1)
11526 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11527 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11528 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11529 && (code != GT && code != LT && code != GE && code != LE))
11530 || (GET_CODE (op0) == ASHIFTRT
11531 && (code != GTU && code != LTU
11532 && code != GEU && code != LEU)))
11533 && CONST_INT_P (XEXP (op0, 1))
11534 && INTVAL (XEXP (op0, 1)) >= 0
11535 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11536 && XEXP (op0, 1) == XEXP (op1, 1))
11538 machine_mode mode = GET_MODE (op0);
11539 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11540 int shift_count = INTVAL (XEXP (op0, 1));
11542 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11543 mask &= (mask >> shift_count) << shift_count;
11544 else if (GET_CODE (op0) == ASHIFT)
11545 mask = (mask & (mask << shift_count)) >> shift_count;
11547 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11548 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11549 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11554 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11555 SUBREGs are of the same mode, and, in both cases, the AND would
11556 be redundant if the comparison was done in the narrower mode,
11557 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11558 and the operand's possibly nonzero bits are 0xffffff01; in that case
11559 if we only care about QImode, we don't need the AND). This case
11560 occurs if the output mode of an scc insn is not SImode and
11561 STORE_FLAG_VALUE == 1 (e.g., the 386).
11563 Similarly, check for a case where the AND's are ZERO_EXTEND
11564 operations from some narrower mode even though a SUBREG is not
11567 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11568 && CONST_INT_P (XEXP (op0, 1))
11569 && CONST_INT_P (XEXP (op1, 1)))
11571 rtx inner_op0 = XEXP (op0, 0);
11572 rtx inner_op1 = XEXP (op1, 0);
11573 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11574 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11577 if (paradoxical_subreg_p (inner_op0)
11578 && GET_CODE (inner_op1) == SUBREG
11579 && (GET_MODE (SUBREG_REG (inner_op0))
11580 == GET_MODE (SUBREG_REG (inner_op1)))
11581 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11582 <= HOST_BITS_PER_WIDE_INT)
11583 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11584 GET_MODE (SUBREG_REG (inner_op0)))))
11585 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11586 GET_MODE (SUBREG_REG (inner_op1))))))
11588 op0 = SUBREG_REG (inner_op0);
11589 op1 = SUBREG_REG (inner_op1);
11591 /* The resulting comparison is always unsigned since we masked
11592 off the original sign bit. */
11593 code = unsigned_condition (code);
11599 for (tmode = GET_CLASS_NARROWEST_MODE
11600 (GET_MODE_CLASS (GET_MODE (op0)));
11601 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11602 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11604 op0 = gen_lowpart_or_truncate (tmode, inner_op0);
11605 op1 = gen_lowpart_or_truncate (tmode, inner_op1);
11606 code = unsigned_condition (code);
11615 /* If both operands are NOT, we can strip off the outer operation
11616 and adjust the comparison code for swapped operands; similarly for
11617 NEG, except that this must be an equality comparison. */
11618 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11619 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11620 && (code == EQ || code == NE)))
11621 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11627 /* If the first operand is a constant, swap the operands and adjust the
11628 comparison code appropriately, but don't do this if the second operand
11629 is already a constant integer. */
11630 if (swap_commutative_operands_p (op0, op1))
11632 std::swap (op0, op1);
11633 code = swap_condition (code);
11636 /* We now enter a loop during which we will try to simplify the comparison.
11637 For the most part, we only are concerned with comparisons with zero,
11638 but some things may really be comparisons with zero but not start
11639 out looking that way. */
11641 while (CONST_INT_P (op1))
11643 machine_mode mode = GET_MODE (op0);
11644 unsigned int mode_width = GET_MODE_PRECISION (mode);
11645 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11646 int equality_comparison_p;
11647 int sign_bit_comparison_p;
11648 int unsigned_comparison_p;
11649 HOST_WIDE_INT const_op;
11651 /* We only want to handle integral modes. This catches VOIDmode,
11652 CCmode, and the floating-point modes. An exception is that we
11653 can handle VOIDmode if OP0 is a COMPARE or a comparison
11656 if (GET_MODE_CLASS (mode) != MODE_INT
11657 && ! (mode == VOIDmode
11658 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11661 /* Try to simplify the compare to constant, possibly changing the
11662 comparison op, and/or changing op1 to zero. */
11663 code = simplify_compare_const (code, mode, op0, &op1);
11664 const_op = INTVAL (op1);
11666 /* Compute some predicates to simplify code below. */
11668 equality_comparison_p = (code == EQ || code == NE);
11669 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11670 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11673 /* If this is a sign bit comparison and we can do arithmetic in
11674 MODE, say that we will only be needing the sign bit of OP0. */
11675 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11676 op0 = force_to_mode (op0, mode,
11677 (unsigned HOST_WIDE_INT) 1
11678 << (GET_MODE_PRECISION (mode) - 1),
11681 /* Now try cases based on the opcode of OP0. If none of the cases
11682 does a "continue", we exit this loop immediately after the
11685 switch (GET_CODE (op0))
11688 /* If we are extracting a single bit from a variable position in
11689 a constant that has only a single bit set and are comparing it
11690 with zero, we can convert this into an equality comparison
11691 between the position and the location of the single bit. */
11692 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11693 have already reduced the shift count modulo the word size. */
11694 if (!SHIFT_COUNT_TRUNCATED
11695 && CONST_INT_P (XEXP (op0, 0))
11696 && XEXP (op0, 1) == const1_rtx
11697 && equality_comparison_p && const_op == 0
11698 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11700 if (BITS_BIG_ENDIAN)
11701 i = BITS_PER_WORD - 1 - i;
11703 op0 = XEXP (op0, 2);
11707 /* Result is nonzero iff shift count is equal to I. */
11708 code = reverse_condition (code);
11715 tem = expand_compound_operation (op0);
11724 /* If testing for equality, we can take the NOT of the constant. */
11725 if (equality_comparison_p
11726 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11728 op0 = XEXP (op0, 0);
11733 /* If just looking at the sign bit, reverse the sense of the
11735 if (sign_bit_comparison_p)
11737 op0 = XEXP (op0, 0);
11738 code = (code == GE ? LT : GE);
11744 /* If testing for equality, we can take the NEG of the constant. */
11745 if (equality_comparison_p
11746 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11748 op0 = XEXP (op0, 0);
11753 /* The remaining cases only apply to comparisons with zero. */
11757 /* When X is ABS or is known positive,
11758 (neg X) is < 0 if and only if X != 0. */
11760 if (sign_bit_comparison_p
11761 && (GET_CODE (XEXP (op0, 0)) == ABS
11762 || (mode_width <= HOST_BITS_PER_WIDE_INT
11763 && (nonzero_bits (XEXP (op0, 0), mode)
11764 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11767 op0 = XEXP (op0, 0);
11768 code = (code == LT ? NE : EQ);
11772 /* If we have NEG of something whose two high-order bits are the
11773 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11774 if (num_sign_bit_copies (op0, mode) >= 2)
11776 op0 = XEXP (op0, 0);
11777 code = swap_condition (code);
11783 /* If we are testing equality and our count is a constant, we
11784 can perform the inverse operation on our RHS. */
11785 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11786 && (tem = simplify_binary_operation (ROTATERT, mode,
11787 op1, XEXP (op0, 1))) != 0)
11789 op0 = XEXP (op0, 0);
11794 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11795 a particular bit. Convert it to an AND of a constant of that
11796 bit. This will be converted into a ZERO_EXTRACT. */
11797 if (const_op == 0 && sign_bit_comparison_p
11798 && CONST_INT_P (XEXP (op0, 1))
11799 && mode_width <= HOST_BITS_PER_WIDE_INT)
11801 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11802 ((unsigned HOST_WIDE_INT) 1
11804 - INTVAL (XEXP (op0, 1)))));
11805 code = (code == LT ? NE : EQ);
11809 /* Fall through. */
11812 /* ABS is ignorable inside an equality comparison with zero. */
11813 if (const_op == 0 && equality_comparison_p)
11815 op0 = XEXP (op0, 0);
11821 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11822 (compare FOO CONST) if CONST fits in FOO's mode and we
11823 are either testing inequality or have an unsigned
11824 comparison with ZERO_EXTEND or a signed comparison with
11825 SIGN_EXTEND. But don't do it if we don't have a compare
11826 insn of the given mode, since we'd have to revert it
11827 later on, and then we wouldn't know whether to sign- or
11829 mode = GET_MODE (XEXP (op0, 0));
11830 if (GET_MODE_CLASS (mode) == MODE_INT
11831 && ! unsigned_comparison_p
11832 && HWI_COMPUTABLE_MODE_P (mode)
11833 && trunc_int_for_mode (const_op, mode) == const_op
11834 && have_insn_for (COMPARE, mode))
11836 op0 = XEXP (op0, 0);
11842 /* Check for the case where we are comparing A - C1 with C2, that is
11844 (subreg:MODE (plus (A) (-C1))) op (C2)
11846 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11847 comparison in the wider mode. One of the following two conditions
11848 must be true in order for this to be valid:
11850 1. The mode extension results in the same bit pattern being added
11851 on both sides and the comparison is equality or unsigned. As
11852 C2 has been truncated to fit in MODE, the pattern can only be
11855 2. The mode extension results in the sign bit being copied on
11858 The difficulty here is that we have predicates for A but not for
11859 (A - C1) so we need to check that C1 is within proper bounds so
11860 as to perturbate A as little as possible. */
11862 if (mode_width <= HOST_BITS_PER_WIDE_INT
11863 && subreg_lowpart_p (op0)
11864 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11865 && GET_CODE (SUBREG_REG (op0)) == PLUS
11866 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11868 machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11869 rtx a = XEXP (SUBREG_REG (op0), 0);
11870 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11873 && (unsigned HOST_WIDE_INT) c1
11874 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11875 && (equality_comparison_p || unsigned_comparison_p)
11876 /* (A - C1) zero-extends if it is positive and sign-extends
11877 if it is negative, C2 both zero- and sign-extends. */
11878 && ((0 == (nonzero_bits (a, inner_mode)
11879 & ~GET_MODE_MASK (mode))
11881 /* (A - C1) sign-extends if it is positive and 1-extends
11882 if it is negative, C2 both sign- and 1-extends. */
11883 || (num_sign_bit_copies (a, inner_mode)
11884 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11887 || ((unsigned HOST_WIDE_INT) c1
11888 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11889 /* (A - C1) always sign-extends, like C2. */
11890 && num_sign_bit_copies (a, inner_mode)
11891 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11892 - (mode_width - 1))))
11894 op0 = SUBREG_REG (op0);
11899 /* If the inner mode is narrower and we are extracting the low part,
11900 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11901 if (subreg_lowpart_p (op0)
11902 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11903 /* Fall through */ ;
11907 /* ... fall through ... */
11910 mode = GET_MODE (XEXP (op0, 0));
11911 if (GET_MODE_CLASS (mode) == MODE_INT
11912 && (unsigned_comparison_p || equality_comparison_p)
11913 && HWI_COMPUTABLE_MODE_P (mode)
11914 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11916 && have_insn_for (COMPARE, mode))
11918 op0 = XEXP (op0, 0);
11924 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11925 this for equality comparisons due to pathological cases involving
11927 if (equality_comparison_p
11928 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11929 op1, XEXP (op0, 1))))
11931 op0 = XEXP (op0, 0);
11936 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11937 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11938 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11940 op0 = XEXP (XEXP (op0, 0), 0);
11941 code = (code == LT ? EQ : NE);
11947 /* We used to optimize signed comparisons against zero, but that
11948 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11949 arrive here as equality comparisons, or (GEU, LTU) are
11950 optimized away. No need to special-case them. */
11952 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11953 (eq B (minus A C)), whichever simplifies. We can only do
11954 this for equality comparisons due to pathological cases involving
11956 if (equality_comparison_p
11957 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11958 XEXP (op0, 1), op1)))
11960 op0 = XEXP (op0, 0);
11965 if (equality_comparison_p
11966 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11967 XEXP (op0, 0), op1)))
11969 op0 = XEXP (op0, 1);
11974 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11975 of bits in X minus 1, is one iff X > 0. */
11976 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11977 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11978 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11979 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11981 op0 = XEXP (op0, 1);
11982 code = (code == GE ? LE : GT);
11988 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11989 if C is zero or B is a constant. */
11990 if (equality_comparison_p
11991 && 0 != (tem = simplify_binary_operation (XOR, mode,
11992 XEXP (op0, 1), op1)))
11994 op0 = XEXP (op0, 0);
12001 case UNEQ: case LTGT:
12002 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
12003 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
12004 case UNORDERED: case ORDERED:
12005 /* We can't do anything if OP0 is a condition code value, rather
12006 than an actual data value. */
12008 || CC0_P (XEXP (op0, 0))
12009 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12012 /* Get the two operands being compared. */
12013 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12014 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12016 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12018 /* Check for the cases where we simply want the result of the
12019 earlier test or the opposite of that result. */
12020 if (code == NE || code == EQ
12021 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
12022 && (code == LT || code == GE)))
12024 enum rtx_code new_code;
12025 if (code == LT || code == NE)
12026 new_code = GET_CODE (op0);
12028 new_code = reversed_comparison_code (op0, NULL);
12030 if (new_code != UNKNOWN)
12041 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12043 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12044 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12045 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12047 op0 = XEXP (op0, 1);
12048 code = (code == GE ? GT : LE);
12054 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12055 will be converted to a ZERO_EXTRACT later. */
12056 if (const_op == 0 && equality_comparison_p
12057 && GET_CODE (XEXP (op0, 0)) == ASHIFT
12058 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12060 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12061 XEXP (XEXP (op0, 0), 1));
12062 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12066 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12067 zero and X is a comparison and C1 and C2 describe only bits set
12068 in STORE_FLAG_VALUE, we can compare with X. */
12069 if (const_op == 0 && equality_comparison_p
12070 && mode_width <= HOST_BITS_PER_WIDE_INT
12071 && CONST_INT_P (XEXP (op0, 1))
12072 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12073 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12074 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12075 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12077 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12078 << INTVAL (XEXP (XEXP (op0, 0), 1)));
12079 if ((~STORE_FLAG_VALUE & mask) == 0
12080 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12081 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12082 && COMPARISON_P (tem))))
12084 op0 = XEXP (XEXP (op0, 0), 0);
12089 /* If we are doing an equality comparison of an AND of a bit equal
12090 to the sign bit, replace this with a LT or GE comparison of
12091 the underlying value. */
12092 if (equality_comparison_p
12094 && CONST_INT_P (XEXP (op0, 1))
12095 && mode_width <= HOST_BITS_PER_WIDE_INT
12096 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12097 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
12099 op0 = XEXP (op0, 0);
12100 code = (code == EQ ? GE : LT);
12104 /* If this AND operation is really a ZERO_EXTEND from a narrower
12105 mode, the constant fits within that mode, and this is either an
12106 equality or unsigned comparison, try to do this comparison in
12111 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12112 -> (ne:DI (reg:SI 4) (const_int 0))
12114 unless TRULY_NOOP_TRUNCATION allows it or the register is
12115 known to hold a value of the required mode the
12116 transformation is invalid. */
12117 if ((equality_comparison_p || unsigned_comparison_p)
12118 && CONST_INT_P (XEXP (op0, 1))
12119 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12120 & GET_MODE_MASK (mode))
12122 && const_op >> i == 0
12123 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
12125 op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12129 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12130 fits in both M1 and M2 and the SUBREG is either paradoxical
12131 or represents the low part, permute the SUBREG and the AND
12133 if (GET_CODE (XEXP (op0, 0)) == SUBREG
12134 && CONST_INT_P (XEXP (op0, 1)))
12136 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
12137 unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
12138 /* Require an integral mode, to avoid creating something like
12140 if (SCALAR_INT_MODE_P (tmode)
12141 /* It is unsafe to commute the AND into the SUBREG if the
12142 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12143 not defined. As originally written the upper bits
12144 have a defined value due to the AND operation.
12145 However, if we commute the AND inside the SUBREG then
12146 they no longer have defined values and the meaning of
12147 the code has been changed.
12148 Also C1 should not change value in the smaller mode,
12149 see PR67028 (a positive C1 can become negative in the
12150 smaller mode, so that the AND does no longer mask the
12152 && ((WORD_REGISTER_OPERATIONS
12153 && mode_width > GET_MODE_PRECISION (tmode)
12154 && mode_width <= BITS_PER_WORD
12155 && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1)
12156 || (mode_width <= GET_MODE_PRECISION (tmode)
12157 && subreg_lowpart_p (XEXP (op0, 0))))
12158 && mode_width <= HOST_BITS_PER_WIDE_INT
12159 && HWI_COMPUTABLE_MODE_P (tmode)
12160 && (c1 & ~mask) == 0
12161 && (c1 & ~GET_MODE_MASK (tmode)) == 0
12163 && c1 != GET_MODE_MASK (tmode))
12165 op0 = simplify_gen_binary (AND, tmode,
12166 SUBREG_REG (XEXP (op0, 0)),
12167 gen_int_mode (c1, tmode));
12168 op0 = gen_lowpart (mode, op0);
12173 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12174 if (const_op == 0 && equality_comparison_p
12175 && XEXP (op0, 1) == const1_rtx
12176 && GET_CODE (XEXP (op0, 0)) == NOT)
12178 op0 = simplify_and_const_int (NULL_RTX, mode,
12179 XEXP (XEXP (op0, 0), 0), 1);
12180 code = (code == NE ? EQ : NE);
12184 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12185 (eq (and (lshiftrt X) 1) 0).
12186 Also handle the case where (not X) is expressed using xor. */
12187 if (const_op == 0 && equality_comparison_p
12188 && XEXP (op0, 1) == const1_rtx
12189 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12191 rtx shift_op = XEXP (XEXP (op0, 0), 0);
12192 rtx shift_count = XEXP (XEXP (op0, 0), 1);
12194 if (GET_CODE (shift_op) == NOT
12195 || (GET_CODE (shift_op) == XOR
12196 && CONST_INT_P (XEXP (shift_op, 1))
12197 && CONST_INT_P (shift_count)
12198 && HWI_COMPUTABLE_MODE_P (mode)
12199 && (UINTVAL (XEXP (shift_op, 1))
12200 == (unsigned HOST_WIDE_INT) 1
12201 << INTVAL (shift_count))))
12204 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12205 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12206 code = (code == NE ? EQ : NE);
12213 /* If we have (compare (ashift FOO N) (const_int C)) and
12214 the high order N bits of FOO (N+1 if an inequality comparison)
12215 are known to be zero, we can do this by comparing FOO with C
12216 shifted right N bits so long as the low-order N bits of C are
12218 if (CONST_INT_P (XEXP (op0, 1))
12219 && INTVAL (XEXP (op0, 1)) >= 0
12220 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12221 < HOST_BITS_PER_WIDE_INT)
12222 && (((unsigned HOST_WIDE_INT) const_op
12223 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
12225 && mode_width <= HOST_BITS_PER_WIDE_INT
12226 && (nonzero_bits (XEXP (op0, 0), mode)
12227 & ~(mask >> (INTVAL (XEXP (op0, 1))
12228 + ! equality_comparison_p))) == 0)
12230 /* We must perform a logical shift, not an arithmetic one,
12231 as we want the top N bits of C to be zero. */
12232 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12234 temp >>= INTVAL (XEXP (op0, 1));
12235 op1 = gen_int_mode (temp, mode);
12236 op0 = XEXP (op0, 0);
12240 /* If we are doing a sign bit comparison, it means we are testing
12241 a particular bit. Convert it to the appropriate AND. */
12242 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12243 && mode_width <= HOST_BITS_PER_WIDE_INT)
12245 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12246 ((unsigned HOST_WIDE_INT) 1
12248 - INTVAL (XEXP (op0, 1)))));
12249 code = (code == LT ? NE : EQ);
12253 /* If this an equality comparison with zero and we are shifting
12254 the low bit to the sign bit, we can convert this to an AND of the
12256 if (const_op == 0 && equality_comparison_p
12257 && CONST_INT_P (XEXP (op0, 1))
12258 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12260 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
12266 /* If this is an equality comparison with zero, we can do this
12267 as a logical shift, which might be much simpler. */
12268 if (equality_comparison_p && const_op == 0
12269 && CONST_INT_P (XEXP (op0, 1)))
12271 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
12273 INTVAL (XEXP (op0, 1)));
12277 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12278 do the comparison in a narrower mode. */
12279 if (! unsigned_comparison_p
12280 && CONST_INT_P (XEXP (op0, 1))
12281 && GET_CODE (XEXP (op0, 0)) == ASHIFT
12282 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12283 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
12284 MODE_INT, 1)) != BLKmode
12285 && (((unsigned HOST_WIDE_INT) const_op
12286 + (GET_MODE_MASK (tmode) >> 1) + 1)
12287 <= GET_MODE_MASK (tmode)))
12289 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
12293 /* Likewise if OP0 is a PLUS of a sign extension with a
12294 constant, which is usually represented with the PLUS
12295 between the shifts. */
12296 if (! unsigned_comparison_p
12297 && CONST_INT_P (XEXP (op0, 1))
12298 && GET_CODE (XEXP (op0, 0)) == PLUS
12299 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12300 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
12301 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
12302 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
12303 MODE_INT, 1)) != BLKmode
12304 && (((unsigned HOST_WIDE_INT) const_op
12305 + (GET_MODE_MASK (tmode) >> 1) + 1)
12306 <= GET_MODE_MASK (tmode)))
12308 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
12309 rtx add_const = XEXP (XEXP (op0, 0), 1);
12310 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
12311 add_const, XEXP (op0, 1));
12313 op0 = simplify_gen_binary (PLUS, tmode,
12314 gen_lowpart (tmode, inner),
12319 /* ... fall through ... */
12321 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12322 the low order N bits of FOO are known to be zero, we can do this
12323 by comparing FOO with C shifted left N bits so long as no
12324 overflow occurs. Even if the low order N bits of FOO aren't known
12325 to be zero, if the comparison is >= or < we can use the same
12326 optimization and for > or <= by setting all the low
12327 order N bits in the comparison constant. */
12328 if (CONST_INT_P (XEXP (op0, 1))
12329 && INTVAL (XEXP (op0, 1)) > 0
12330 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12331 && mode_width <= HOST_BITS_PER_WIDE_INT
12332 && (((unsigned HOST_WIDE_INT) const_op
12333 + (GET_CODE (op0) != LSHIFTRT
12334 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
12337 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
12339 unsigned HOST_WIDE_INT low_bits
12340 = (nonzero_bits (XEXP (op0, 0), mode)
12341 & (((unsigned HOST_WIDE_INT) 1
12342 << INTVAL (XEXP (op0, 1))) - 1));
12343 if (low_bits == 0 || !equality_comparison_p)
12345 /* If the shift was logical, then we must make the condition
12347 if (GET_CODE (op0) == LSHIFTRT)
12348 code = unsigned_condition (code);
12350 const_op <<= INTVAL (XEXP (op0, 1));
12352 && (code == GT || code == GTU
12353 || code == LE || code == LEU))
12355 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
12356 op1 = GEN_INT (const_op);
12357 op0 = XEXP (op0, 0);
12362 /* If we are using this shift to extract just the sign bit, we
12363 can replace this with an LT or GE comparison. */
12365 && (equality_comparison_p || sign_bit_comparison_p)
12366 && CONST_INT_P (XEXP (op0, 1))
12367 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12369 op0 = XEXP (op0, 0);
12370 code = (code == NE || code == GT ? LT : GE);
12382 /* Now make any compound operations involved in this comparison. Then,
12383 check for an outmost SUBREG on OP0 that is not doing anything or is
12384 paradoxical. The latter transformation must only be performed when
12385 it is known that the "extra" bits will be the same in op0 and op1 or
12386 that they don't matter. There are three cases to consider:
12388 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12389 care bits and we can assume they have any convenient value. So
12390 making the transformation is safe.
12392 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12393 In this case the upper bits of op0 are undefined. We should not make
12394 the simplification in that case as we do not know the contents of
12397 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12398 UNKNOWN. In that case we know those bits are zeros or ones. We must
12399 also be sure that they are the same as the upper bits of op1.
12401 We can never remove a SUBREG for a non-equality comparison because
12402 the sign bit is in a different place in the underlying object. */
12404 rtx_code op0_mco_code = SET;
12405 if (op1 == const0_rtx)
12406 op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
12408 op0 = make_compound_operation (op0, op0_mco_code);
12409 op1 = make_compound_operation (op1, SET);
12411 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
12412 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
12413 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
12414 && (code == NE || code == EQ))
12416 if (paradoxical_subreg_p (op0))
12418 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12420 if (REG_P (SUBREG_REG (op0)))
12422 op0 = SUBREG_REG (op0);
12423 op1 = gen_lowpart (GET_MODE (op0), op1);
12426 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
12427 <= HOST_BITS_PER_WIDE_INT)
12428 && (nonzero_bits (SUBREG_REG (op0),
12429 GET_MODE (SUBREG_REG (op0)))
12430 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12432 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12434 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12435 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12436 op0 = SUBREG_REG (op0), op1 = tem;
12440 /* We now do the opposite procedure: Some machines don't have compare
12441 insns in all modes. If OP0's mode is an integer mode smaller than a
12442 word and we can't do a compare in that mode, see if there is a larger
12443 mode for which we can do the compare. There are a number of cases in
12444 which we can use the wider mode. */
12446 mode = GET_MODE (op0);
12447 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12448 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12449 && ! have_insn_for (COMPARE, mode))
12450 for (tmode = GET_MODE_WIDER_MODE (mode);
12451 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12452 tmode = GET_MODE_WIDER_MODE (tmode))
12453 if (have_insn_for (COMPARE, tmode))
12457 /* If this is a test for negative, we can make an explicit
12458 test of the sign bit. Test this first so we can use
12459 a paradoxical subreg to extend OP0. */
12461 if (op1 == const0_rtx && (code == LT || code == GE)
12462 && HWI_COMPUTABLE_MODE_P (mode))
12464 unsigned HOST_WIDE_INT sign
12465 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
12466 op0 = simplify_gen_binary (AND, tmode,
12467 gen_lowpart (tmode, op0),
12468 gen_int_mode (sign, tmode));
12469 code = (code == LT) ? NE : EQ;
12473 /* If the only nonzero bits in OP0 and OP1 are those in the
12474 narrower mode and this is an equality or unsigned comparison,
12475 we can use the wider mode. Similarly for sign-extended
12476 values, in which case it is true for all comparisons. */
12477 zero_extended = ((code == EQ || code == NE
12478 || code == GEU || code == GTU
12479 || code == LEU || code == LTU)
12480 && (nonzero_bits (op0, tmode)
12481 & ~GET_MODE_MASK (mode)) == 0
12482 && ((CONST_INT_P (op1)
12483 || (nonzero_bits (op1, tmode)
12484 & ~GET_MODE_MASK (mode)) == 0)));
12487 || ((num_sign_bit_copies (op0, tmode)
12488 > (unsigned int) (GET_MODE_PRECISION (tmode)
12489 - GET_MODE_PRECISION (mode)))
12490 && (num_sign_bit_copies (op1, tmode)
12491 > (unsigned int) (GET_MODE_PRECISION (tmode)
12492 - GET_MODE_PRECISION (mode)))))
12494 /* If OP0 is an AND and we don't have an AND in MODE either,
12495 make a new AND in the proper mode. */
12496 if (GET_CODE (op0) == AND
12497 && !have_insn_for (AND, mode))
12498 op0 = simplify_gen_binary (AND, tmode,
12499 gen_lowpart (tmode,
12501 gen_lowpart (tmode,
12507 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12508 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12512 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12513 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12520 /* We may have changed the comparison operands. Re-canonicalize. */
12521 if (swap_commutative_operands_p (op0, op1))
12523 std::swap (op0, op1);
12524 code = swap_condition (code);
12527 /* If this machine only supports a subset of valid comparisons, see if we
12528 can convert an unsupported one into a supported one. */
12529 target_canonicalize_comparison (&code, &op0, &op1, 0);
12537 /* Utility function for record_value_for_reg. Count number of
12542 enum rtx_code code = GET_CODE (x);
12546 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12547 || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12549 rtx x0 = XEXP (x, 0);
12550 rtx x1 = XEXP (x, 1);
12553 return 1 + 2 * count_rtxs (x0);
12555 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12556 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12557 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12558 return 2 + 2 * count_rtxs (x0)
12559 + count_rtxs (x == XEXP (x1, 0)
12560 ? XEXP (x1, 1) : XEXP (x1, 0));
12562 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12563 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12564 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12565 return 2 + 2 * count_rtxs (x1)
12566 + count_rtxs (x == XEXP (x0, 0)
12567 ? XEXP (x0, 1) : XEXP (x0, 0));
12570 fmt = GET_RTX_FORMAT (code);
12571 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12573 ret += count_rtxs (XEXP (x, i));
12574 else if (fmt[i] == 'E')
12575 for (j = 0; j < XVECLEN (x, i); j++)
12576 ret += count_rtxs (XVECEXP (x, i, j));
12581 /* Utility function for following routine. Called when X is part of a value
12582 being stored into last_set_value. Sets last_set_table_tick
12583 for each register mentioned. Similar to mention_regs in cse.c */
12586 update_table_tick (rtx x)
12588 enum rtx_code code = GET_CODE (x);
12589 const char *fmt = GET_RTX_FORMAT (code);
12594 unsigned int regno = REGNO (x);
12595 unsigned int endregno = END_REGNO (x);
12598 for (r = regno; r < endregno; r++)
12600 reg_stat_type *rsp = ®_stat[r];
12601 rsp->last_set_table_tick = label_tick;
12607 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12610 /* Check for identical subexpressions. If x contains
12611 identical subexpression we only have to traverse one of
12613 if (i == 0 && ARITHMETIC_P (x))
12615 /* Note that at this point x1 has already been
12617 rtx x0 = XEXP (x, 0);
12618 rtx x1 = XEXP (x, 1);
12620 /* If x0 and x1 are identical then there is no need to
12625 /* If x0 is identical to a subexpression of x1 then while
12626 processing x1, x0 has already been processed. Thus we
12627 are done with x. */
12628 if (ARITHMETIC_P (x1)
12629 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12632 /* If x1 is identical to a subexpression of x0 then we
12633 still have to process the rest of x0. */
12634 if (ARITHMETIC_P (x0)
12635 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12637 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12642 update_table_tick (XEXP (x, i));
12644 else if (fmt[i] == 'E')
12645 for (j = 0; j < XVECLEN (x, i); j++)
12646 update_table_tick (XVECEXP (x, i, j));
12649 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12650 are saying that the register is clobbered and we no longer know its
12651 value. If INSN is zero, don't update reg_stat[].last_set; this is
12652 only permitted with VALUE also zero and is used to invalidate the
12656 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
12658 unsigned int regno = REGNO (reg);
12659 unsigned int endregno = END_REGNO (reg);
12661 reg_stat_type *rsp;
12663 /* If VALUE contains REG and we have a previous value for REG, substitute
12664 the previous value. */
12665 if (value && insn && reg_overlap_mentioned_p (reg, value))
12669 /* Set things up so get_last_value is allowed to see anything set up to
12671 subst_low_luid = DF_INSN_LUID (insn);
12672 tem = get_last_value (reg);
12674 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12675 it isn't going to be useful and will take a lot of time to process,
12676 so just use the CLOBBER. */
12680 if (ARITHMETIC_P (tem)
12681 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12682 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12683 tem = XEXP (tem, 0);
12684 else if (count_occurrences (value, reg, 1) >= 2)
12686 /* If there are two or more occurrences of REG in VALUE,
12687 prevent the value from growing too much. */
12688 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12689 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12692 value = replace_rtx (copy_rtx (value), reg, tem);
12696 /* For each register modified, show we don't know its value, that
12697 we don't know about its bitwise content, that its value has been
12698 updated, and that we don't know the location of the death of the
12700 for (i = regno; i < endregno; i++)
12702 rsp = ®_stat[i];
12705 rsp->last_set = insn;
12707 rsp->last_set_value = 0;
12708 rsp->last_set_mode = VOIDmode;
12709 rsp->last_set_nonzero_bits = 0;
12710 rsp->last_set_sign_bit_copies = 0;
12711 rsp->last_death = 0;
12712 rsp->truncated_to_mode = VOIDmode;
12715 /* Mark registers that are being referenced in this value. */
12717 update_table_tick (value);
12719 /* Now update the status of each register being set.
12720 If someone is using this register in this block, set this register
12721 to invalid since we will get confused between the two lives in this
12722 basic block. This makes using this register always invalid. In cse, we
12723 scan the table to invalidate all entries using this register, but this
12724 is too much work for us. */
12726 for (i = regno; i < endregno; i++)
12728 rsp = ®_stat[i];
12729 rsp->last_set_label = label_tick;
12731 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12732 rsp->last_set_invalid = 1;
12734 rsp->last_set_invalid = 0;
12737 /* The value being assigned might refer to X (like in "x++;"). In that
12738 case, we must replace it with (clobber (const_int 0)) to prevent
12740 rsp = ®_stat[regno];
12741 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12743 value = copy_rtx (value);
12744 if (!get_last_value_validate (&value, insn, label_tick, 1))
12748 /* For the main register being modified, update the value, the mode, the
12749 nonzero bits, and the number of sign bit copies. */
12751 rsp->last_set_value = value;
12755 machine_mode mode = GET_MODE (reg);
12756 subst_low_luid = DF_INSN_LUID (insn);
12757 rsp->last_set_mode = mode;
12758 if (GET_MODE_CLASS (mode) == MODE_INT
12759 && HWI_COMPUTABLE_MODE_P (mode))
12760 mode = nonzero_bits_mode;
12761 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12762 rsp->last_set_sign_bit_copies
12763 = num_sign_bit_copies (value, GET_MODE (reg));
12767 /* Called via note_stores from record_dead_and_set_regs to handle one
12768 SET or CLOBBER in an insn. DATA is the instruction in which the
12769 set is occurring. */
12772 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12774 rtx_insn *record_dead_insn = (rtx_insn *) data;
12776 if (GET_CODE (dest) == SUBREG)
12777 dest = SUBREG_REG (dest);
12779 if (!record_dead_insn)
12782 record_value_for_reg (dest, NULL, NULL_RTX);
12788 /* If we are setting the whole register, we know its value. Otherwise
12789 show that we don't know the value. We can handle SUBREG in
12791 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12792 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12793 else if (GET_CODE (setter) == SET
12794 && GET_CODE (SET_DEST (setter)) == SUBREG
12795 && SUBREG_REG (SET_DEST (setter)) == dest
12796 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12797 && subreg_lowpart_p (SET_DEST (setter)))
12798 record_value_for_reg (dest, record_dead_insn,
12799 gen_lowpart (GET_MODE (dest),
12800 SET_SRC (setter)));
12802 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12804 else if (MEM_P (dest)
12805 /* Ignore pushes, they clobber nothing. */
12806 && ! push_operand (dest, GET_MODE (dest)))
12807 mem_last_set = DF_INSN_LUID (record_dead_insn);
12810 /* Update the records of when each REG was most recently set or killed
12811 for the things done by INSN. This is the last thing done in processing
12812 INSN in the combiner loop.
12814 We update reg_stat[], in particular fields last_set, last_set_value,
12815 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12816 last_death, and also the similar information mem_last_set (which insn
12817 most recently modified memory) and last_call_luid (which insn was the
12818 most recent subroutine call). */
12821 record_dead_and_set_regs (rtx_insn *insn)
12826 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12828 if (REG_NOTE_KIND (link) == REG_DEAD
12829 && REG_P (XEXP (link, 0)))
12831 unsigned int regno = REGNO (XEXP (link, 0));
12832 unsigned int endregno = END_REGNO (XEXP (link, 0));
12834 for (i = regno; i < endregno; i++)
12836 reg_stat_type *rsp;
12838 rsp = ®_stat[i];
12839 rsp->last_death = insn;
12842 else if (REG_NOTE_KIND (link) == REG_INC)
12843 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12848 hard_reg_set_iterator hrsi;
12849 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12851 reg_stat_type *rsp;
12853 rsp = ®_stat[i];
12854 rsp->last_set_invalid = 1;
12855 rsp->last_set = insn;
12856 rsp->last_set_value = 0;
12857 rsp->last_set_mode = VOIDmode;
12858 rsp->last_set_nonzero_bits = 0;
12859 rsp->last_set_sign_bit_copies = 0;
12860 rsp->last_death = 0;
12861 rsp->truncated_to_mode = VOIDmode;
12864 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12866 /* We can't combine into a call pattern. Remember, though, that
12867 the return value register is set at this LUID. We could
12868 still replace a register with the return value from the
12869 wrong subroutine call! */
12870 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12873 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12876 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12877 register present in the SUBREG, so for each such SUBREG go back and
12878 adjust nonzero and sign bit information of the registers that are
12879 known to have some zero/sign bits set.
12881 This is needed because when combine blows the SUBREGs away, the
12882 information on zero/sign bits is lost and further combines can be
12883 missed because of that. */
12886 record_promoted_value (rtx_insn *insn, rtx subreg)
12888 struct insn_link *links;
12890 unsigned int regno = REGNO (SUBREG_REG (subreg));
12891 machine_mode mode = GET_MODE (subreg);
12893 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12896 for (links = LOG_LINKS (insn); links;)
12898 reg_stat_type *rsp;
12900 insn = links->insn;
12901 set = single_set (insn);
12903 if (! set || !REG_P (SET_DEST (set))
12904 || REGNO (SET_DEST (set)) != regno
12905 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12907 links = links->next;
12911 rsp = ®_stat[regno];
12912 if (rsp->last_set == insn)
12914 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
12915 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12918 if (REG_P (SET_SRC (set)))
12920 regno = REGNO (SET_SRC (set));
12921 links = LOG_LINKS (insn);
12928 /* Check if X, a register, is known to contain a value already
12929 truncated to MODE. In this case we can use a subreg to refer to
12930 the truncated value even though in the generic case we would need
12931 an explicit truncation. */
12934 reg_truncated_to_mode (machine_mode mode, const_rtx x)
12936 reg_stat_type *rsp = ®_stat[REGNO (x)];
12937 machine_mode truncated = rsp->truncated_to_mode;
12940 || rsp->truncation_label < label_tick_ebb_start)
12942 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12944 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12949 /* If X is a hard reg or a subreg record the mode that the register is
12950 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12951 to turn a truncate into a subreg using this information. Return true
12952 if traversing X is complete. */
12955 record_truncated_value (rtx x)
12957 machine_mode truncated_mode;
12958 reg_stat_type *rsp;
12960 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12962 machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12963 truncated_mode = GET_MODE (x);
12965 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12968 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12971 x = SUBREG_REG (x);
12973 /* ??? For hard-regs we now record everything. We might be able to
12974 optimize this using last_set_mode. */
12975 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12976 truncated_mode = GET_MODE (x);
12980 rsp = ®_stat[REGNO (x)];
12981 if (rsp->truncated_to_mode == 0
12982 || rsp->truncation_label < label_tick_ebb_start
12983 || (GET_MODE_SIZE (truncated_mode)
12984 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12986 rsp->truncated_to_mode = truncated_mode;
12987 rsp->truncation_label = label_tick;
12993 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12994 the modes they are used in. This can help truning TRUNCATEs into
12998 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13000 subrtx_var_iterator::array_type array;
13001 FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13002 if (record_truncated_value (*iter))
13003 iter.skip_subrtxes ();
13006 /* Scan X for promoted SUBREGs. For each one found,
13007 note what it implies to the registers used in it. */
13010 check_promoted_subreg (rtx_insn *insn, rtx x)
13012 if (GET_CODE (x) == SUBREG
13013 && SUBREG_PROMOTED_VAR_P (x)
13014 && REG_P (SUBREG_REG (x)))
13015 record_promoted_value (insn, x);
13018 const char *format = GET_RTX_FORMAT (GET_CODE (x));
13021 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13025 check_promoted_subreg (insn, XEXP (x, i));
13029 if (XVEC (x, i) != 0)
13030 for (j = 0; j < XVECLEN (x, i); j++)
13031 check_promoted_subreg (insn, XVECEXP (x, i, j));
13037 /* Verify that all the registers and memory references mentioned in *LOC are
13038 still valid. *LOC was part of a value set in INSN when label_tick was
13039 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13040 the invalid references with (clobber (const_int 0)) and return 1. This
13041 replacement is useful because we often can get useful information about
13042 the form of a value (e.g., if it was produced by a shift that always
13043 produces -1 or 0) even though we don't know exactly what registers it
13044 was produced from. */
13047 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace)
13050 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13051 int len = GET_RTX_LENGTH (GET_CODE (x));
13056 unsigned int regno = REGNO (x);
13057 unsigned int endregno = END_REGNO (x);
13060 for (j = regno; j < endregno; j++)
13062 reg_stat_type *rsp = ®_stat[j];
13063 if (rsp->last_set_invalid
13064 /* If this is a pseudo-register that was only set once and not
13065 live at the beginning of the function, it is always valid. */
13066 || (! (regno >= FIRST_PSEUDO_REGISTER
13067 && regno < reg_n_sets_max
13068 && REG_N_SETS (regno) == 1
13069 && (!REGNO_REG_SET_P
13070 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13072 && rsp->last_set_label > tick))
13075 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13082 /* If this is a memory reference, make sure that there were no stores after
13083 it that might have clobbered the value. We don't have alias info, so we
13084 assume any store invalidates it. Moreover, we only have local UIDs, so
13085 we also assume that there were stores in the intervening basic blocks. */
13086 else if (MEM_P (x) && !MEM_READONLY_P (x)
13087 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13090 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13094 for (i = 0; i < len; i++)
13098 /* Check for identical subexpressions. If x contains
13099 identical subexpression we only have to traverse one of
13101 if (i == 1 && ARITHMETIC_P (x))
13103 /* Note that at this point x0 has already been checked
13104 and found valid. */
13105 rtx x0 = XEXP (x, 0);
13106 rtx x1 = XEXP (x, 1);
13108 /* If x0 and x1 are identical then x is also valid. */
13112 /* If x1 is identical to a subexpression of x0 then
13113 while checking x0, x1 has already been checked. Thus
13114 it is valid and so as x. */
13115 if (ARITHMETIC_P (x0)
13116 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13119 /* If x0 is identical to a subexpression of x1 then x is
13120 valid iff the rest of x1 is valid. */
13121 if (ARITHMETIC_P (x1)
13122 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13124 get_last_value_validate (&XEXP (x1,
13125 x0 == XEXP (x1, 0) ? 1 : 0),
13126 insn, tick, replace);
13129 if (get_last_value_validate (&XEXP (x, i), insn, tick,
13133 else if (fmt[i] == 'E')
13134 for (j = 0; j < XVECLEN (x, i); j++)
13135 if (get_last_value_validate (&XVECEXP (x, i, j),
13136 insn, tick, replace) == 0)
13140 /* If we haven't found a reason for it to be invalid, it is valid. */
13144 /* Get the last value assigned to X, if known. Some registers
13145 in the value may be replaced with (clobber (const_int 0)) if their value
13146 is known longer known reliably. */
13149 get_last_value (const_rtx x)
13151 unsigned int regno;
13153 reg_stat_type *rsp;
13155 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13156 then convert it to the desired mode. If this is a paradoxical SUBREG,
13157 we cannot predict what values the "extra" bits might have. */
13158 if (GET_CODE (x) == SUBREG
13159 && subreg_lowpart_p (x)
13160 && !paradoxical_subreg_p (x)
13161 && (value = get_last_value (SUBREG_REG (x))) != 0)
13162 return gen_lowpart (GET_MODE (x), value);
13168 rsp = ®_stat[regno];
13169 value = rsp->last_set_value;
13171 /* If we don't have a value, or if it isn't for this basic block and
13172 it's either a hard register, set more than once, or it's a live
13173 at the beginning of the function, return 0.
13175 Because if it's not live at the beginning of the function then the reg
13176 is always set before being used (is never used without being set).
13177 And, if it's set only once, and it's always set before use, then all
13178 uses must have the same last value, even if it's not from this basic
13182 || (rsp->last_set_label < label_tick_ebb_start
13183 && (regno < FIRST_PSEUDO_REGISTER
13184 || regno >= reg_n_sets_max
13185 || REG_N_SETS (regno) != 1
13187 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13190 /* If the value was set in a later insn than the ones we are processing,
13191 we can't use it even if the register was only set once. */
13192 if (rsp->last_set_label == label_tick
13193 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13196 /* If fewer bits were set than what we are asked for now, we cannot use
13198 if (GET_MODE_PRECISION (rsp->last_set_mode)
13199 < GET_MODE_PRECISION (GET_MODE (x)))
13202 /* If the value has all its registers valid, return it. */
13203 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
13206 /* Otherwise, make a copy and replace any invalid register with
13207 (clobber (const_int 0)). If that fails for some reason, return 0. */
13209 value = copy_rtx (value);
13210 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
13216 /* Return nonzero if expression X refers to a REG or to memory
13217 that is set in an instruction more recent than FROM_LUID. */
13220 use_crosses_set_p (const_rtx x, int from_luid)
13224 enum rtx_code code = GET_CODE (x);
13228 unsigned int regno = REGNO (x);
13229 unsigned endreg = END_REGNO (x);
13231 #ifdef PUSH_ROUNDING
13232 /* Don't allow uses of the stack pointer to be moved,
13233 because we don't know whether the move crosses a push insn. */
13234 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
13237 for (; regno < endreg; regno++)
13239 reg_stat_type *rsp = ®_stat[regno];
13241 && rsp->last_set_label == label_tick
13242 && DF_INSN_LUID (rsp->last_set) > from_luid)
13248 if (code == MEM && mem_last_set > from_luid)
13251 fmt = GET_RTX_FORMAT (code);
13253 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13258 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13259 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
13262 else if (fmt[i] == 'e'
13263 && use_crosses_set_p (XEXP (x, i), from_luid))
13269 /* Define three variables used for communication between the following
13272 static unsigned int reg_dead_regno, reg_dead_endregno;
13273 static int reg_dead_flag;
13275 /* Function called via note_stores from reg_dead_at_p.
13277 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13278 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13281 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13283 unsigned int regno, endregno;
13288 regno = REGNO (dest);
13289 endregno = END_REGNO (dest);
13290 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13291 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13294 /* Return nonzero if REG is known to be dead at INSN.
13296 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13297 referencing REG, it is dead. If we hit a SET referencing REG, it is
13298 live. Otherwise, see if it is live or dead at the start of the basic
13299 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13300 must be assumed to be always live. */
13303 reg_dead_at_p (rtx reg, rtx_insn *insn)
13308 /* Set variables for reg_dead_at_p_1. */
13309 reg_dead_regno = REGNO (reg);
13310 reg_dead_endregno = END_REGNO (reg);
13314 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13315 we allow the machine description to decide whether use-and-clobber
13316 patterns are OK. */
13317 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
13319 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13320 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
13324 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13325 beginning of basic block. */
13326 block = BLOCK_FOR_INSN (insn);
13331 if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
13334 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
13336 return reg_dead_flag == 1 ? 1 : 0;
13338 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
13342 if (insn == BB_HEAD (block))
13345 insn = PREV_INSN (insn);
13348 /* Look at live-in sets for the basic block that we were in. */
13349 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13350 if (REGNO_REG_SET_P (df_get_live_in (block), i))
13356 /* Note hard registers in X that are used. */
13359 mark_used_regs_combine (rtx x)
13361 RTX_CODE code = GET_CODE (x);
13362 unsigned int regno;
13373 case ADDR_DIFF_VEC:
13375 /* CC0 must die in the insn after it is set, so we don't need to take
13376 special note of it here. */
13381 /* If we are clobbering a MEM, mark any hard registers inside the
13382 address as used. */
13383 if (MEM_P (XEXP (x, 0)))
13384 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
13389 /* A hard reg in a wide mode may really be multiple registers.
13390 If so, mark all of them just like the first. */
13391 if (regno < FIRST_PSEUDO_REGISTER)
13393 /* None of this applies to the stack, frame or arg pointers. */
13394 if (regno == STACK_POINTER_REGNUM
13395 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13396 && regno == HARD_FRAME_POINTER_REGNUM)
13397 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13398 && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
13399 || regno == FRAME_POINTER_REGNUM)
13402 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
13408 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13410 rtx testreg = SET_DEST (x);
13412 while (GET_CODE (testreg) == SUBREG
13413 || GET_CODE (testreg) == ZERO_EXTRACT
13414 || GET_CODE (testreg) == STRICT_LOW_PART)
13415 testreg = XEXP (testreg, 0);
13417 if (MEM_P (testreg))
13418 mark_used_regs_combine (XEXP (testreg, 0));
13420 mark_used_regs_combine (SET_SRC (x));
13428 /* Recursively scan the operands of this expression. */
13431 const char *fmt = GET_RTX_FORMAT (code);
13433 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13436 mark_used_regs_combine (XEXP (x, i));
13437 else if (fmt[i] == 'E')
13441 for (j = 0; j < XVECLEN (x, i); j++)
13442 mark_used_regs_combine (XVECEXP (x, i, j));
13448 /* Remove register number REGNO from the dead registers list of INSN.
13450 Return the note used to record the death, if there was one. */
13453 remove_death (unsigned int regno, rtx_insn *insn)
13455 rtx note = find_regno_note (insn, REG_DEAD, regno);
13458 remove_note (insn, note);
13463 /* For each register (hardware or pseudo) used within expression X, if its
13464 death is in an instruction with luid between FROM_LUID (inclusive) and
13465 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13466 list headed by PNOTES.
13468 That said, don't move registers killed by maybe_kill_insn.
13470 This is done when X is being merged by combination into TO_INSN. These
13471 notes will then be distributed as needed. */
13474 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
13479 enum rtx_code code = GET_CODE (x);
13483 unsigned int regno = REGNO (x);
13484 rtx_insn *where_dead = reg_stat[regno].last_death;
13486 /* Don't move the register if it gets killed in between from and to. */
13487 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13488 && ! reg_referenced_p (x, maybe_kill_insn))
13492 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13493 && DF_INSN_LUID (where_dead) >= from_luid
13494 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13496 rtx note = remove_death (regno, where_dead);
13498 /* It is possible for the call above to return 0. This can occur
13499 when last_death points to I2 or I1 that we combined with.
13500 In that case make a new note.
13502 We must also check for the case where X is a hard register
13503 and NOTE is a death note for a range of hard registers
13504 including X. In that case, we must put REG_DEAD notes for
13505 the remaining registers in place of NOTE. */
13507 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13508 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13509 > GET_MODE_SIZE (GET_MODE (x))))
13511 unsigned int deadregno = REGNO (XEXP (note, 0));
13512 unsigned int deadend = END_REGNO (XEXP (note, 0));
13513 unsigned int ourend = END_REGNO (x);
13516 for (i = deadregno; i < deadend; i++)
13517 if (i < regno || i >= ourend)
13518 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13521 /* If we didn't find any note, or if we found a REG_DEAD note that
13522 covers only part of the given reg, and we have a multi-reg hard
13523 register, then to be safe we must check for REG_DEAD notes
13524 for each register other than the first. They could have
13525 their own REG_DEAD notes lying around. */
13526 else if ((note == 0
13528 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13529 < GET_MODE_SIZE (GET_MODE (x)))))
13530 && regno < FIRST_PSEUDO_REGISTER
13531 && REG_NREGS (x) > 1)
13533 unsigned int ourend = END_REGNO (x);
13534 unsigned int i, offset;
13538 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13542 for (i = regno + offset; i < ourend; i++)
13543 move_deaths (regno_reg_rtx[i],
13544 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13547 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13549 XEXP (note, 1) = *pnotes;
13553 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13559 else if (GET_CODE (x) == SET)
13561 rtx dest = SET_DEST (x);
13563 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13565 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13566 that accesses one word of a multi-word item, some
13567 piece of everything register in the expression is used by
13568 this insn, so remove any old death. */
13569 /* ??? So why do we test for equality of the sizes? */
13571 if (GET_CODE (dest) == ZERO_EXTRACT
13572 || GET_CODE (dest) == STRICT_LOW_PART
13573 || (GET_CODE (dest) == SUBREG
13574 && (((GET_MODE_SIZE (GET_MODE (dest))
13575 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13576 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13577 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13579 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13583 /* If this is some other SUBREG, we know it replaces the entire
13584 value, so use that as the destination. */
13585 if (GET_CODE (dest) == SUBREG)
13586 dest = SUBREG_REG (dest);
13588 /* If this is a MEM, adjust deaths of anything used in the address.
13589 For a REG (the only other possibility), the entire value is
13590 being replaced so the old value is not used in this insn. */
13593 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13598 else if (GET_CODE (x) == CLOBBER)
13601 len = GET_RTX_LENGTH (code);
13602 fmt = GET_RTX_FORMAT (code);
13604 for (i = 0; i < len; i++)
13609 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13610 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13613 else if (fmt[i] == 'e')
13614 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13618 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13619 pattern of an insn. X must be a REG. */
13622 reg_bitfield_target_p (rtx x, rtx body)
13626 if (GET_CODE (body) == SET)
13628 rtx dest = SET_DEST (body);
13630 unsigned int regno, tregno, endregno, endtregno;
13632 if (GET_CODE (dest) == ZERO_EXTRACT)
13633 target = XEXP (dest, 0);
13634 else if (GET_CODE (dest) == STRICT_LOW_PART)
13635 target = SUBREG_REG (XEXP (dest, 0));
13639 if (GET_CODE (target) == SUBREG)
13640 target = SUBREG_REG (target);
13642 if (!REG_P (target))
13645 tregno = REGNO (target), regno = REGNO (x);
13646 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13647 return target == x;
13649 endtregno = end_hard_regno (GET_MODE (target), tregno);
13650 endregno = end_hard_regno (GET_MODE (x), regno);
13652 return endregno > tregno && regno < endtregno;
13655 else if (GET_CODE (body) == PARALLEL)
13656 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13657 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13663 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13664 as appropriate. I3 and I2 are the insns resulting from the combination
13665 insns including FROM (I2 may be zero).
13667 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13668 not need REG_DEAD notes because they are being substituted for. This
13669 saves searching in the most common cases.
13671 Each note in the list is either ignored or placed on some insns, depending
13672 on the type of note. */
13675 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
13676 rtx elim_i2, rtx elim_i1, rtx elim_i0)
13678 rtx note, next_note;
13680 rtx_insn *tem_insn;
13682 for (note = notes; note; note = next_note)
13684 rtx_insn *place = 0, *place2 = 0;
13686 next_note = XEXP (note, 1);
13687 switch (REG_NOTE_KIND (note))
13691 /* Doesn't matter much where we put this, as long as it's somewhere.
13692 It is preferable to keep these notes on branches, which is most
13693 likely to be i3. */
13697 case REG_NON_LOCAL_GOTO:
13702 gcc_assert (i2 && JUMP_P (i2));
13707 case REG_EH_REGION:
13708 /* These notes must remain with the call or trapping instruction. */
13711 else if (i2 && CALL_P (i2))
13715 gcc_assert (cfun->can_throw_non_call_exceptions);
13716 if (may_trap_p (i3))
13718 else if (i2 && may_trap_p (i2))
13720 /* ??? Otherwise assume we've combined things such that we
13721 can now prove that the instructions can't trap. Drop the
13722 note in this case. */
13726 case REG_ARGS_SIZE:
13727 /* ??? How to distribute between i3-i1. Assume i3 contains the
13728 entire adjustment. Assert i3 contains at least some adjust. */
13729 if (!noop_move_p (i3))
13731 int old_size, args_size = INTVAL (XEXP (note, 0));
13732 /* fixup_args_size_notes looks at REG_NORETURN note,
13733 so ensure the note is placed there first. */
13737 for (np = &next_note; *np; np = &XEXP (*np, 1))
13738 if (REG_NOTE_KIND (*np) == REG_NORETURN)
13742 XEXP (n, 1) = REG_NOTES (i3);
13743 REG_NOTES (i3) = n;
13747 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13748 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13749 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13750 gcc_assert (old_size != args_size
13752 && !ACCUMULATE_OUTGOING_ARGS
13753 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13760 case REG_CALL_DECL:
13761 /* These notes must remain with the call. It should not be
13762 possible for both I2 and I3 to be a call. */
13767 gcc_assert (i2 && CALL_P (i2));
13773 /* Any clobbers for i3 may still exist, and so we must process
13774 REG_UNUSED notes from that insn.
13776 Any clobbers from i2 or i1 can only exist if they were added by
13777 recog_for_combine. In that case, recog_for_combine created the
13778 necessary REG_UNUSED notes. Trying to keep any original
13779 REG_UNUSED notes from these insns can cause incorrect output
13780 if it is for the same register as the original i3 dest.
13781 In that case, we will notice that the register is set in i3,
13782 and then add a REG_UNUSED note for the destination of i3, which
13783 is wrong. However, it is possible to have REG_UNUSED notes from
13784 i2 or i1 for register which were both used and clobbered, so
13785 we keep notes from i2 or i1 if they will turn into REG_DEAD
13788 /* If this register is set or clobbered in I3, put the note there
13789 unless there is one already. */
13790 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13792 if (from_insn != i3)
13795 if (! (REG_P (XEXP (note, 0))
13796 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13797 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13800 /* Otherwise, if this register is used by I3, then this register
13801 now dies here, so we must put a REG_DEAD note here unless there
13803 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13804 && ! (REG_P (XEXP (note, 0))
13805 ? find_regno_note (i3, REG_DEAD,
13806 REGNO (XEXP (note, 0)))
13807 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13809 PUT_REG_NOTE_KIND (note, REG_DEAD);
13817 /* These notes say something about results of an insn. We can
13818 only support them if they used to be on I3 in which case they
13819 remain on I3. Otherwise they are ignored.
13821 If the note refers to an expression that is not a constant, we
13822 must also ignore the note since we cannot tell whether the
13823 equivalence is still true. It might be possible to do
13824 slightly better than this (we only have a problem if I2DEST
13825 or I1DEST is present in the expression), but it doesn't
13826 seem worth the trouble. */
13828 if (from_insn == i3
13829 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13834 /* These notes say something about how a register is used. They must
13835 be present on any use of the register in I2 or I3. */
13836 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13839 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13848 case REG_LABEL_TARGET:
13849 case REG_LABEL_OPERAND:
13850 /* This can show up in several ways -- either directly in the
13851 pattern, or hidden off in the constant pool with (or without?)
13852 a REG_EQUAL note. */
13853 /* ??? Ignore the without-reg_equal-note problem for now. */
13854 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13855 || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13856 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
13857 && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0)))
13861 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13862 || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13863 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
13864 && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0))))
13872 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13873 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13875 if (place && JUMP_P (place)
13876 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13877 && (JUMP_LABEL (place) == NULL
13878 || JUMP_LABEL (place) == XEXP (note, 0)))
13880 rtx label = JUMP_LABEL (place);
13883 JUMP_LABEL (place) = XEXP (note, 0);
13884 else if (LABEL_P (label))
13885 LABEL_NUSES (label)--;
13888 if (place2 && JUMP_P (place2)
13889 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13890 && (JUMP_LABEL (place2) == NULL
13891 || JUMP_LABEL (place2) == XEXP (note, 0)))
13893 rtx label = JUMP_LABEL (place2);
13896 JUMP_LABEL (place2) = XEXP (note, 0);
13897 else if (LABEL_P (label))
13898 LABEL_NUSES (label)--;
13904 /* This note says something about the value of a register prior
13905 to the execution of an insn. It is too much trouble to see
13906 if the note is still correct in all situations. It is better
13907 to simply delete it. */
13911 /* If we replaced the right hand side of FROM_INSN with a
13912 REG_EQUAL note, the original use of the dying register
13913 will not have been combined into I3 and I2. In such cases,
13914 FROM_INSN is guaranteed to be the first of the combined
13915 instructions, so we simply need to search back before
13916 FROM_INSN for the previous use or set of this register,
13917 then alter the notes there appropriately.
13919 If the register is used as an input in I3, it dies there.
13920 Similarly for I2, if it is nonzero and adjacent to I3.
13922 If the register is not used as an input in either I3 or I2
13923 and it is not one of the registers we were supposed to eliminate,
13924 there are two possibilities. We might have a non-adjacent I2
13925 or we might have somehow eliminated an additional register
13926 from a computation. For example, we might have had A & B where
13927 we discover that B will always be zero. In this case we will
13928 eliminate the reference to A.
13930 In both cases, we must search to see if we can find a previous
13931 use of A and put the death note there. */
13934 && from_insn == i2mod
13935 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13936 tem_insn = from_insn;
13940 && CALL_P (from_insn)
13941 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13943 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13945 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13946 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13948 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13950 && reg_overlap_mentioned_p (XEXP (note, 0),
13952 || rtx_equal_p (XEXP (note, 0), elim_i1)
13953 || rtx_equal_p (XEXP (note, 0), elim_i0))
13956 /* If the new I2 sets the same register that is marked dead
13957 in the note, we do not know where to put the note.
13959 if (i2 != 0 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
13965 basic_block bb = this_basic_block;
13967 for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
13969 if (!NONDEBUG_INSN_P (tem_insn))
13971 if (tem_insn == BB_HEAD (bb))
13976 /* If the register is being set at TEM_INSN, see if that is all
13977 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13978 into a REG_UNUSED note instead. Don't delete sets to
13979 global register vars. */
13980 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13981 || !global_regs[REGNO (XEXP (note, 0))])
13982 && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
13984 rtx set = single_set (tem_insn);
13985 rtx inner_dest = 0;
13986 rtx_insn *cc0_setter = NULL;
13989 for (inner_dest = SET_DEST (set);
13990 (GET_CODE (inner_dest) == STRICT_LOW_PART
13991 || GET_CODE (inner_dest) == SUBREG
13992 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13993 inner_dest = XEXP (inner_dest, 0))
13996 /* Verify that it was the set, and not a clobber that
13997 modified the register.
13999 CC0 targets must be careful to maintain setter/user
14000 pairs. If we cannot delete the setter due to side
14001 effects, mark the user with an UNUSED note instead
14004 if (set != 0 && ! side_effects_p (SET_SRC (set))
14005 && rtx_equal_p (XEXP (note, 0), inner_dest)
14007 || (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
14008 || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
14009 && sets_cc0_p (PATTERN (cc0_setter)) > 0))))
14011 /* Move the notes and links of TEM_INSN elsewhere.
14012 This might delete other dead insns recursively.
14013 First set the pattern to something that won't use
14015 rtx old_notes = REG_NOTES (tem_insn);
14017 PATTERN (tem_insn) = pc_rtx;
14018 REG_NOTES (tem_insn) = NULL;
14020 distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14021 NULL_RTX, NULL_RTX, NULL_RTX);
14022 distribute_links (LOG_LINKS (tem_insn));
14024 SET_INSN_DELETED (tem_insn);
14025 if (tem_insn == i2)
14028 /* Delete the setter too. */
14031 PATTERN (cc0_setter) = pc_rtx;
14032 old_notes = REG_NOTES (cc0_setter);
14033 REG_NOTES (cc0_setter) = NULL;
14035 distribute_notes (old_notes, cc0_setter,
14037 NULL_RTX, NULL_RTX, NULL_RTX);
14038 distribute_links (LOG_LINKS (cc0_setter));
14040 SET_INSN_DELETED (cc0_setter);
14041 if (cc0_setter == i2)
14047 PUT_REG_NOTE_KIND (note, REG_UNUSED);
14049 /* If there isn't already a REG_UNUSED note, put one
14050 here. Do not place a REG_DEAD note, even if
14051 the register is also used here; that would not
14052 match the algorithm used in lifetime analysis
14053 and can cause the consistency check in the
14054 scheduler to fail. */
14055 if (! find_regno_note (tem_insn, REG_UNUSED,
14056 REGNO (XEXP (note, 0))))
14061 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14062 || (CALL_P (tem_insn)
14063 && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14067 /* If we are doing a 3->2 combination, and we have a
14068 register which formerly died in i3 and was not used
14069 by i2, which now no longer dies in i3 and is used in
14070 i2 but does not die in i2, and place is between i2
14071 and i3, then we may need to move a link from place to
14073 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14075 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14076 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14078 struct insn_link *links = LOG_LINKS (place);
14079 LOG_LINKS (place) = NULL;
14080 distribute_links (links);
14085 if (tem_insn == BB_HEAD (bb))
14091 /* If the register is set or already dead at PLACE, we needn't do
14092 anything with this note if it is still a REG_DEAD note.
14093 We check here if it is set at all, not if is it totally replaced,
14094 which is what `dead_or_set_p' checks, so also check for it being
14097 if (place && REG_NOTE_KIND (note) == REG_DEAD)
14099 unsigned int regno = REGNO (XEXP (note, 0));
14100 reg_stat_type *rsp = ®_stat[regno];
14102 if (dead_or_set_p (place, XEXP (note, 0))
14103 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14105 /* Unless the register previously died in PLACE, clear
14106 last_death. [I no longer understand why this is
14108 if (rsp->last_death != place)
14109 rsp->last_death = 0;
14113 rsp->last_death = place;
14115 /* If this is a death note for a hard reg that is occupying
14116 multiple registers, ensure that we are still using all
14117 parts of the object. If we find a piece of the object
14118 that is unused, we must arrange for an appropriate REG_DEAD
14119 note to be added for it. However, we can't just emit a USE
14120 and tag the note to it, since the register might actually
14121 be dead; so we recourse, and the recursive call then finds
14122 the previous insn that used this register. */
14124 if (place && REG_NREGS (XEXP (note, 0)) > 1)
14126 unsigned int endregno = END_REGNO (XEXP (note, 0));
14127 bool all_used = true;
14130 for (i = regno; i < endregno; i++)
14131 if ((! refers_to_regno_p (i, PATTERN (place))
14132 && ! find_regno_fusage (place, USE, i))
14133 || dead_or_set_regno_p (place, i))
14141 /* Put only REG_DEAD notes for pieces that are
14142 not already dead or set. */
14144 for (i = regno; i < endregno;
14145 i += hard_regno_nregs[i][reg_raw_mode[i]])
14147 rtx piece = regno_reg_rtx[i];
14148 basic_block bb = this_basic_block;
14150 if (! dead_or_set_p (place, piece)
14151 && ! reg_bitfield_target_p (piece,
14154 rtx new_note = alloc_reg_note (REG_DEAD, piece,
14157 distribute_notes (new_note, place, place,
14158 NULL, NULL_RTX, NULL_RTX,
14161 else if (! refers_to_regno_p (i, PATTERN (place))
14162 && ! find_regno_fusage (place, USE, i))
14163 for (tem_insn = PREV_INSN (place); ;
14164 tem_insn = PREV_INSN (tem_insn))
14166 if (!NONDEBUG_INSN_P (tem_insn))
14168 if (tem_insn == BB_HEAD (bb))
14172 if (dead_or_set_p (tem_insn, piece)
14173 || reg_bitfield_target_p (piece,
14174 PATTERN (tem_insn)))
14176 add_reg_note (tem_insn, REG_UNUSED, piece);
14189 /* Any other notes should not be present at this point in the
14191 gcc_unreachable ();
14196 XEXP (note, 1) = REG_NOTES (place);
14197 REG_NOTES (place) = note;
14201 add_shallow_copy_of_reg_note (place2, note);
14205 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14206 I3, I2, and I1 to new locations. This is also called to add a link
14207 pointing at I3 when I3's destination is changed. */
14210 distribute_links (struct insn_link *links)
14212 struct insn_link *link, *next_link;
14214 for (link = links; link; link = next_link)
14216 rtx_insn *place = 0;
14220 next_link = link->next;
14222 /* If the insn that this link points to is a NOTE, ignore it. */
14223 if (NOTE_P (link->insn))
14227 rtx pat = PATTERN (link->insn);
14228 if (GET_CODE (pat) == SET)
14230 else if (GET_CODE (pat) == PARALLEL)
14233 for (i = 0; i < XVECLEN (pat, 0); i++)
14235 set = XVECEXP (pat, 0, i);
14236 if (GET_CODE (set) != SET)
14239 reg = SET_DEST (set);
14240 while (GET_CODE (reg) == ZERO_EXTRACT
14241 || GET_CODE (reg) == STRICT_LOW_PART
14242 || GET_CODE (reg) == SUBREG)
14243 reg = XEXP (reg, 0);
14248 if (REGNO (reg) == link->regno)
14251 if (i == XVECLEN (pat, 0))
14257 reg = SET_DEST (set);
14259 while (GET_CODE (reg) == ZERO_EXTRACT
14260 || GET_CODE (reg) == STRICT_LOW_PART
14261 || GET_CODE (reg) == SUBREG)
14262 reg = XEXP (reg, 0);
14264 /* A LOG_LINK is defined as being placed on the first insn that uses
14265 a register and points to the insn that sets the register. Start
14266 searching at the next insn after the target of the link and stop
14267 when we reach a set of the register or the end of the basic block.
14269 Note that this correctly handles the link that used to point from
14270 I3 to I2. Also note that not much searching is typically done here
14271 since most links don't point very far away. */
14273 for (insn = NEXT_INSN (link->insn);
14274 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
14275 || BB_HEAD (this_basic_block->next_bb) != insn));
14276 insn = NEXT_INSN (insn))
14277 if (DEBUG_INSN_P (insn))
14279 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
14281 if (reg_referenced_p (reg, PATTERN (insn)))
14285 else if (CALL_P (insn)
14286 && find_reg_fusage (insn, USE, reg))
14291 else if (INSN_P (insn) && reg_set_p (reg, insn))
14294 /* If we found a place to put the link, place it there unless there
14295 is already a link to the same insn as LINK at that point. */
14299 struct insn_link *link2;
14301 FOR_EACH_LOG_LINK (link2, place)
14302 if (link2->insn == link->insn && link2->regno == link->regno)
14307 link->next = LOG_LINKS (place);
14308 LOG_LINKS (place) = link;
14310 /* Set added_links_insn to the earliest insn we added a
14312 if (added_links_insn == 0
14313 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
14314 added_links_insn = place;
14320 /* Check for any register or memory mentioned in EQUIV that is not
14321 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14322 of EXPR where some registers may have been replaced by constants. */
14325 unmentioned_reg_p (rtx equiv, rtx expr)
14327 subrtx_iterator::array_type array;
14328 FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
14330 const_rtx x = *iter;
14331 if ((REG_P (x) || MEM_P (x))
14332 && !reg_mentioned_p (x, expr))
14338 DEBUG_FUNCTION void
14339 dump_combine_stats (FILE *file)
14343 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14344 combine_attempts, combine_merges, combine_extras, combine_successes);
14348 dump_combine_total_stats (FILE *file)
14352 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14353 total_attempts, total_merges, total_extras, total_successes);
14356 /* Try combining insns through substitution. */
14357 static unsigned int
14358 rest_of_handle_combine (void)
14360 int rebuild_jump_labels_after_combine;
14362 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
14363 df_note_add_problem ();
14366 regstat_init_n_sets_and_refs ();
14367 reg_n_sets_max = max_reg_num ();
14369 rebuild_jump_labels_after_combine
14370 = combine_instructions (get_insns (), max_reg_num ());
14372 /* Combining insns may have turned an indirect jump into a
14373 direct jump. Rebuild the JUMP_LABEL fields of jumping
14375 if (rebuild_jump_labels_after_combine)
14377 timevar_push (TV_JUMP);
14378 rebuild_jump_labels (get_insns ());
14380 timevar_pop (TV_JUMP);
14383 regstat_free_n_sets_and_refs ();
14389 const pass_data pass_data_combine =
14391 RTL_PASS, /* type */
14392 "combine", /* name */
14393 OPTGROUP_NONE, /* optinfo_flags */
14394 TV_COMBINE, /* tv_id */
14395 PROP_cfglayout, /* properties_required */
14396 0, /* properties_provided */
14397 0, /* properties_destroyed */
14398 0, /* todo_flags_start */
14399 TODO_df_finish, /* todo_flags_finish */
14402 class pass_combine : public rtl_opt_pass
14405 pass_combine (gcc::context *ctxt)
14406 : rtl_opt_pass (pass_data_combine, ctxt)
14409 /* opt_pass methods: */
14410 virtual bool gate (function *) { return (optimize > 0); }
14411 virtual unsigned int execute (function *)
14413 return rest_of_handle_combine ();
14416 }; // class pass_combine
14418 } // anon namespace
14421 make_pass_combine (gcc::context *ctxt)
14423 return new pass_combine (ctxt);