5 .global _opcodes, _opcodes_end
\r
11 add *ar0+, a ; Smem, src
\r
12 add *ar1+, ts, a ; Smem, TS, src
\r
13 add *ar2+, 16, a ; Smem, 16, src [,dst]
\r
14 add *ar3+, a, b ; Smem [,SHIFT], src [,dst] (-16<=SHIFT<=15)
\r
16 add *ar4+, 1, a ; Xmem, SHFT, src (0<=SHFT<=15)
\r
17 add *ar3+, *ar4+, a ; Xmem, Ymem, dst
\r
18 add #-32768, a ; #lk [,SHFT], src [,dst] (-32768<=lk<=32767)
\r
20 add #0,16,a,b ; #lk, 16, src, [,dst]
\r
22 add a,-16,b ; src [,SHIFT][,dst]
\r
23 add a,asm,b ; src, ASM [,dst]
\r
28 and *ar3+,a ; Smem,src
\r
29 and #1,1,a,b ; #lk[,SHFT],src[,dst]
\r
31 and #1,#16,a,b ; #lk,16,src[,dst]
\r
33 and a ; src[,SHIFT][,dst]
\r
47 banz _opcodes_end,*ar1+
\r
49 banzd _opcodes_end,*ar2+
\r
53 bc _opcodes_end, AEQ,AOV
\r
55 bcd _opcodes_end, BIO,C,TC
\r
74 cc _opcodes_end, tc
\r
76 ccd _opcodes_end, aeq
\r
95 firs *ar3+,*ar4+,_opcodes_end
\r
100 ld *ar0+,a ; Smem,dst
\r
101 ld *ar1+,ts,a ; Smem,TS,dst
\r
102 ld *ar2+,16,a ; Smem,16,dst
\r
103 ld *ar3+,1,a ; Smem[,SHIFT],dst
\r
105 ld *ar4+,1,a ; Xmem,SHFT,dst
\r
107 ld #32767,1,a ; #lk,[,SHFT],dst
\r
109 ld #32767,16,a ; #lk,16,dst
\r
111 ld a,asm,b ; src,ASM[,dst]
\r
112 ld a,1,b ; src[,SHIFT],dst
\r
115 ld #_opcodes_end,dp ; FIXME try to print label on disasm
\r
116 ; note: TI assembler doesn't shift
\r
117 ; the address encoding.
\r
122 ld *ar2+,a || mac *ar3+,b ; single-line parallell
\r
123 ld *ar4+,b || macr *ar5+,a ; with optional DST_ specified
\r
124 ld *ar2+,a ; double-line parallel
\r
126 ld *ar4+,b ; parallel spans
\r
135 mac *ar2+,*ar3+,a,b
\r
136 macr *ar4+,*ar5+,a,b
\r
141 maca *ar1+ ; *ar6+,b (valid)
\r
143 macd *ar2+,_opcodes_end,a
\r
145 macp *ar3+,_opcodes_end,a
\r
147 macsu *ar4+,*ar5+,a
\r
151 mas *ar3+,*ar4+,a,b
\r
152 masr *ar2+,*ar5+,a,b
\r
153 masa *ar6+ ; *ar6+,b (valid)
\r
172 mvdp *ar6+,_opcodes_end
\r
179 mvpd _opcodes_end,*ar3+
\r
225 rptb _opcodes_end-1
\r
227 rptbd _opcodes_end-1
\r