5 /* Integer instructions. */
27 dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */
31 /* Debug instructions. */
38 /* Coprocessor 0 instructions, minus standard ISA 3 ones.
39 That leaves just the performance monitoring registers. */
46 /* Multimedia instructions. */
49 /* Test each form of each vector opcode. */
53 .if 0 /* Which is right?? */
54 /* Test negative numbers in immediate-value slot. */
57 /* Test that it's recognized as an unsigned field. */
63 /* Test each form of each vector opcode. */
67 .if 0 /* Which is right?? */
68 /* Test negative numbers in immediate-value slot. */
71 /* Test that it's recognized as an unsigned field. */
95 /* ALNI, SHFL: Vector only. */
97 shfl.mixh.ob $f1,$f2,$f3
98 shfl.mixl.ob $f1,$f2,$f3
99 shfl.pach.ob $f1,$f2,$f3
100 shfl.pacl.ob $f1,$f2,$f3
102 /* SLL,SRL: Scalar or immediate. */
103 sll.ob $f2,$f4,$f5[3]
105 srl.ob $f2,$f4,$f5[3]
108 /* RZU: Immediate, must be 0, 8, or 16. */