tizen 2.4 release
[external/binutils.git] / gas / testsuite / gas / i386 / x86-64-avx512dq-rcigrne-intel.d
1 #as: -mevexrcig=rne
2 #objdump: -dw -Mintel
3 #name: x86_64 AVX512DQ rcig insns (Intel disassembly)
4 #source: x86-64-avx512dq-rcig.s
5
6 .*: +file format .*
7
8
9 Disassembly of section \.text:
10
11 0+ <_start>:
12 [       ]*[a-f0-9]+:[   ]*62 03 95 10 50 f4 ab[         ]*vrangepd zmm30,zmm29,zmm28,\{sae\},0xab
13 [       ]*[a-f0-9]+:[   ]*62 03 95 10 50 f4 7b[         ]*vrangepd zmm30,zmm29,zmm28,\{sae\},0x7b
14 [       ]*[a-f0-9]+:[   ]*62 03 15 10 50 f4 ab[         ]*vrangeps zmm30,zmm29,zmm28,\{sae\},0xab
15 [       ]*[a-f0-9]+:[   ]*62 03 15 10 50 f4 7b[         ]*vrangeps zmm30,zmm29,zmm28,\{sae\},0x7b
16 [       ]*[a-f0-9]+:[   ]*62 03 95 10 51 f4 ab[         ]*vrangesd xmm30,xmm29,xmm28,\{sae\},0xab
17 [       ]*[a-f0-9]+:[   ]*62 03 95 10 51 f4 7b[         ]*vrangesd xmm30,xmm29,xmm28,\{sae\},0x7b
18 [       ]*[a-f0-9]+:[   ]*62 03 15 10 51 f4 ab[         ]*vrangess xmm30,xmm29,xmm28,\{sae\},0xab
19 [       ]*[a-f0-9]+:[   ]*62 03 15 10 51 f4 7b[         ]*vrangess xmm30,xmm29,xmm28,\{sae\},0x7b
20 [       ]*[a-f0-9]+:[   ]*62 03 fd 18 56 f5 ab[         ]*vreducepd zmm30,zmm29,\{sae\},0xab
21 [       ]*[a-f0-9]+:[   ]*62 03 fd 18 56 f5 7b[         ]*vreducepd zmm30,zmm29,\{sae\},0x7b
22 [       ]*[a-f0-9]+:[   ]*62 03 7d 18 56 f5 ab[         ]*vreduceps zmm30,zmm29,\{sae\},0xab
23 [       ]*[a-f0-9]+:[   ]*62 03 7d 18 56 f5 7b[         ]*vreduceps zmm30,zmm29,\{sae\},0x7b
24 [       ]*[a-f0-9]+:[   ]*62 03 95 10 57 f4 ab[         ]*vreducesd xmm30,xmm29,xmm28,\{sae\},0xab
25 [       ]*[a-f0-9]+:[   ]*62 03 95 10 57 f4 7b[         ]*vreducesd xmm30,xmm29,xmm28,\{sae\},0x7b
26 [       ]*[a-f0-9]+:[   ]*62 03 15 10 57 f4 ab[         ]*vreducess xmm30,xmm29,xmm28,\{sae\},0xab
27 [       ]*[a-f0-9]+:[   ]*62 03 15 10 57 f4 7b[         ]*vreducess xmm30,xmm29,xmm28,\{sae\},0x7b
28 [       ]*[a-f0-9]+:[   ]*62 01 fd 18 7a f5[    ]*vcvttpd2qq zmm30,zmm29,\{sae\}
29 [       ]*[a-f0-9]+:[   ]*62 01 fd 18 78 f5[    ]*vcvttpd2uqq zmm30,zmm29,\{sae\}
30 [       ]*[a-f0-9]+:[   ]*62 01 7d 18 7a f5[    ]*vcvttps2qq zmm30,ymm29,\{sae\}
31 [       ]*[a-f0-9]+:[   ]*62 01 7d 18 78 f5[    ]*vcvttps2uqq zmm30,ymm29,\{sae\}
32 [       ]*[a-f0-9]+:[   ]*62 03 95 10 50 f4 ab[         ]*vrangepd zmm30,zmm29,zmm28,\{sae\},0xab
33 [       ]*[a-f0-9]+:[   ]*62 03 95 10 50 f4 7b[         ]*vrangepd zmm30,zmm29,zmm28,\{sae\},0x7b
34 [       ]*[a-f0-9]+:[   ]*62 03 15 10 50 f4 ab[         ]*vrangeps zmm30,zmm29,zmm28,\{sae\},0xab
35 [       ]*[a-f0-9]+:[   ]*62 03 15 10 50 f4 7b[         ]*vrangeps zmm30,zmm29,zmm28,\{sae\},0x7b
36 [       ]*[a-f0-9]+:[   ]*62 03 95 10 51 f4 ab[         ]*vrangesd xmm30,xmm29,xmm28,\{sae\},0xab
37 [       ]*[a-f0-9]+:[   ]*62 03 95 10 51 f4 7b[         ]*vrangesd xmm30,xmm29,xmm28,\{sae\},0x7b
38 [       ]*[a-f0-9]+:[   ]*62 03 15 10 51 f4 ab[         ]*vrangess xmm30,xmm29,xmm28,\{sae\},0xab
39 [       ]*[a-f0-9]+:[   ]*62 03 15 10 51 f4 7b[         ]*vrangess xmm30,xmm29,xmm28,\{sae\},0x7b
40 [       ]*[a-f0-9]+:[   ]*62 03 fd 18 56 f5 ab[         ]*vreducepd zmm30,zmm29,\{sae\},0xab
41 [       ]*[a-f0-9]+:[   ]*62 03 fd 18 56 f5 7b[         ]*vreducepd zmm30,zmm29,\{sae\},0x7b
42 [       ]*[a-f0-9]+:[   ]*62 03 7d 18 56 f5 ab[         ]*vreduceps zmm30,zmm29,\{sae\},0xab
43 [       ]*[a-f0-9]+:[   ]*62 03 7d 18 56 f5 7b[         ]*vreduceps zmm30,zmm29,\{sae\},0x7b
44 [       ]*[a-f0-9]+:[   ]*62 03 95 10 57 f4 ab[         ]*vreducesd xmm30,xmm29,xmm28,\{sae\},0xab
45 [       ]*[a-f0-9]+:[   ]*62 03 95 10 57 f4 7b[         ]*vreducesd xmm30,xmm29,xmm28,\{sae\},0x7b
46 [       ]*[a-f0-9]+:[   ]*62 03 15 10 57 f4 ab[         ]*vreducess xmm30,xmm29,xmm28,\{sae\},0xab
47 [       ]*[a-f0-9]+:[   ]*62 03 15 10 57 f4 7b[         ]*vreducess xmm30,xmm29,xmm28,\{sae\},0x7b
48 [       ]*[a-f0-9]+:[   ]*62 01 fd 18 7a f5[    ]*vcvttpd2qq zmm30,zmm29,\{sae\}
49 [       ]*[a-f0-9]+:[   ]*62 01 fd 18 78 f5[    ]*vcvttpd2uqq zmm30,zmm29,\{sae\}
50 [       ]*[a-f0-9]+:[   ]*62 01 7d 18 7a f5[    ]*vcvttps2qq zmm30,ymm29,\{sae\}
51 [       ]*[a-f0-9]+:[   ]*62 01 7d 18 78 f5[    ]*vcvttps2uqq zmm30,ymm29,\{sae\}
52 #pass