9 //genreg = genreg ; /* (a) */
\r
73 //genreg = dagreg ; /* (a) */
\r
131 //dagreg = genreg ; /* (a) */
\r
169 //dagreg = dagreg ; /* (a) */
\r
191 //genreg = USP ; /* (a)*/
\r
199 //USP = genreg ; /* (a)*/
\r
207 //Dreg = sysreg ; /* sysreg to 32-bit D-register (a) */
\r
225 //sysreg = Dreg ; /* 32-bit D-register to sysreg (a) */
\r
243 //sysreg = Preg ; /* 32-bit P-register to sysreg (a) */
\r
263 //sysreg = USP ; /* (a) */
\r
282 A0 = A1 ; /* move 40-bit Accumulator value (b) */
\r
284 A1 = A0 ; /* move 40-bit Accumulator value (b) */
\r
286 //A0 = Dreg ; /* 32-bit D-register to 40-bit A0, sign extended (b)*/
\r
291 //A1 = Dreg ; /* 32-bit D-register to 40-bit A1, sign extended (b)*/
\r
296 //Dreg_even = A0 (opt_mode) ; /* move 32-bit A0.W to even Dreg (b) */
\r
301 //Dreg_odd = A1 (opt_mode) ; /* move 32-bit A1.W to odd Dreg (b) */
\r
306 //Dreg_even = A0, Dreg_odd = A1 (opt_mode) ; /* move both Accumulators to a register pair (b) */
\r
308 R0 = A0, R1 = A1(FU);
\r
309 R6 = A0, R7 = A1(ISS2);
\r
312 //Dreg_odd = A1, Dreg_even = A0 (opt_mode) ; /* move both Accumulators to a register pair (b) */
\r
314 R3 = A1, R2 = A0(FU);
\r
315 R5 = A1, R4 = A0(ISS2);
\r
317 //IF CC DPreg = DPreg ; /* move if CC = 1 (a) */
\r
338 //IF ! CC DPreg = DPreg ; /* move if CC = 0 (a) */
\r
358 //Dreg = Dreg_lo (Z) ; /* (a) */
\r
365 //Dreg = Dreg_lo (X) ; /* (a)*/
\r
376 //A0.X = Dreg_lo ; /* least significant 8 bits of Dreg into A0.X (b) */
\r
380 //A1.X = Dreg_lo ; /* least significant 8 bits of Dreg into A1.X (b) */
\r
384 //Dreg_lo = A0.X ; /* 8-bit A0.X, sign-extended, into least significant 16 bits of Dreg (b) */
\r
389 //Dreg_lo = A1.X ; /* 8-bit A1.X, sign-extended, into least significant 16 bits of Dreg (b) */
\r
394 //A0.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A0.W (b) */
\r
399 //A1.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A1.W (b) */
\r
404 //A0.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A0.W (b) */
\r
408 //A1.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A1.W (b) */
\r
413 //Dreg_lo = A0 (opt_mode) ; /* move A0 to lower half of Dreg (b) */
\r
438 //Dreg_hi = A1 (opt_mode) ; /* move A1 to upper half of Dreg (b) */
\r
464 //Dreg_lo = A0, Dreg_hi = A1 (opt_mode) ; /* move both values at once; must go to the lower and upper halves of the same Dreg (b)*/
\r
466 R0.L = A0, R0.H = A1;
\r
467 R1.L = A0, R1.H = A1;
\r
469 R0.L = A0, R0.H = A1(FU);
\r
470 R1.L = A0, R1.H = A1(FU);
\r
472 R0.L = A0, R0.H = A1(IS);
\r
473 R1.L = A0, R1.H = A1(IS);
\r
475 R0.L = A0, R0.H = A1(IU);
\r
476 R1.L = A0, R1.H = A1(IU);
\r
478 R0.L = A0, R0.H = A1(T);
\r
479 R1.L = A0, R1.H = A1(T);
\r
481 R0.L = A0, R0.H = A1(S2RND);
\r
482 R1.L = A0, R1.H = A1(S2RND);
\r
484 R0.L = A0, R0.H = A1(ISS2);
\r
485 R1.L = A0, R1.H = A1(ISS2);
\r
487 R0.L = A0, R0.H = A1(IH);
\r
488 R1.L = A0, R1.H = A1(IH);
\r
490 //Dreg_hi = A1, Dreg_lo = AO (opt_mode) ; /* move both values at once; must go to the upper and lower halves of the same Dreg (b) */
\r
492 R0.H = A1,R0.L = A0;
\r
493 R1.H = A1,R1.L = A0;
\r
495 R0.H = A1,R0.L = A0 (FU);
\r
496 R1.H = A1,R1.L = A0 (FU);
\r
498 R0.H = A1,R0.L = A0 (IS);
\r
499 R1.H = A1,R1.L = A0 (IS);
\r
501 R0.H = A1,R0.L = A0 (IU);
\r
502 R1.H = A1,R1.L = A0 (IU);
\r
504 R0.H = A1,R0.L = A0 (T);
\r
505 R1.H = A1,R1.L = A0 (T);
\r
507 R0.H = A1,R0.L = A0 (S2RND);
\r
508 R1.H = A1,R1.L = A0 (S2RND);
\r
510 R0.H = A1,R0.L = A0 (ISS2);
\r
511 R1.H = A1,R1.L = A0 (ISS2);
\r
513 R0.H = A1,R0.L = A0 (IH);
\r
514 R1.H = A1,R1.L = A0 (IH);
\r
516 //Dreg = Dreg_byte (Z) ; /* (a)*/
\r
524 //Dreg = Dreg_byte (X) ; /* (a) */
\r