1 # Generates tests to see if the following conditions make the instruction
5 # 2) size == 3 && Q == 0
7 # These patterns can't be created by the assembler so instead manually encode
8 # them from a starting pattern.
9 .macro gen_insns_same opc
11 .inst (\opc & 0xff3fffff) // size == 0
12 .inst ((\opc | 0xc00000) & 0xbfffffff) // size == 3 && Q == 0
15 # Generates tests to see if the following conditions make the instruction
18 # 1) size == 0 || size == 3
19 # 2) size == 1 && H == 1 && Q == 0
20 # 3) size == 2 && (L == 1 || Q == 0)
22 # These patterns can't be created by the assembler so instead manually encode
23 # them from a starting pattern.
24 .macro gen_insns_elem opc
26 .inst (\opc & 0xff3fffff) // size == 0
27 .inst (\opc | 0xc00000) // size == 3
28 .inst ((\opc | 0x400800) & 0xbf7fffff) // size == 1 && H == 1 && Q == 0
29 .inst ((\opc | 0xa00000) & 0xffbfffff) // size == 2 && L == 1
30 .inst ((\opc | 0x800000) & 0xbfbfffff) // size == 2 && Q == 0
33 # fcmla v1.2d, v2.2d, v3.2d, #0
34 gen_insns_same 0x6ec3c441
36 # fcmla v1.2s, v2.2s, v3.2s, #0
37 gen_insns_same 0x2e83c441
39 # fcmla v1.4s, v2.4s, v3.4s, #0
40 gen_insns_same 0x6e83c441
42 # fcmla v1.4h, v2.4h, v3.4h, #0
43 gen_insns_same 0x2e43c441
45 # fcmla v1.8h, v2.8h, v3.8h, #0
46 gen_insns_same 0x6e43c441
48 # fcmla v1.4s, v2.4s, v3.s[0], #0
49 gen_insns_elem 0x6f831041
51 # fcmla v1.4h, v2.4h, v3.h[0], #0
52 gen_insns_elem 0x2f431041
54 # fcmla v1.8h, v2.8h, v3.h[0], #0
55 gen_insns_elem 0x6f431041
57 # fcadd v1.2d, v2.2d, v3.2d, #90
58 gen_insns_same 0x6ec3e441
60 # fcadd v1.2s, v2.2s, v3.2s, #90
61 gen_insns_same 0x2e83e441
63 # fcadd v1.4s, v2.4s, v3.4s, #90
64 gen_insns_same 0x6e83e441
66 # fcadd v1.4h, v2.4h, v3.4h, #90
67 gen_insns_same 0x2e43e441
69 # fcadd v1.8h, v2.8h, v3.8h, #90
70 gen_insns_same 0x6e43e441