1 /* ld-reg-uns-imm.s Test file for AArch64 load-store reg. (uns.imm)
4 Copyright (C) 2011-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the license, or
12 (at your option) any later version.
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
23 /* Prefetch memory instruction is not tested here.
25 Also note that as a programmer-friendly assembler, GAS generates
26 LDUR/STUR instructions in response to the standard LDR/STR mnemonics
27 when the immediate offset is unambiguous, i.e. when it is negative
28 or unaligned. Similarly a disassembler could display these
29 instructions using the standard LDR/STR mnemonics when the encoded
30 immediate is negative or unaligned. However this behaviour is not
31 required by the architectural assembly language. */
33 .macro op2_no_imm op, reg
37 .macro op2 op, reg, simm
38 \op \reg\()7, [sp, #\simm]
41 // load to or store from core register
42 // size is the access size in byte
43 .macro ld_or_st op, suffix, reg, size
45 op2 \op\suffix, \reg, \simm
47 op2_no_imm \op\suffix, \reg
48 .irp simm, 0, 2, 4, 8, 16, 85, 255
49 op2 \op\suffix, \reg, \simm
51 op2 \op\suffix, \reg, "(4095*\size)"
54 // load to or store from FP/SIMD register
56 .irp reg, b, h, s, d, q
61 .irp simm, 0, 2, 4, 8, 16, 85, 255
83 // load to or store from FP/SIMD register
87 // load to or store from core register
88 // op, suffix, reg, size(in byte)
97 ld_or_st ldr, sb, x, 1
98 ld_or_st ldr, sh, x, 2
99 ld_or_st ldr, sw, x, 4
100 ld_or_st ldr, sb, w, 1
101 ld_or_st ldr, sh, w, 2