1 /* illegal.s Test file for AArch64 instructions that should be rejected
4 Copyright (C) 2011-2019 Free Software Foundation, Inc. Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
23 // For urecpe and ursqrte, only 2s and 4s are accepted qualifiers.
29 // For AdvSIMD (across) instructions, there are restraints on the register type and qualifiers.
55 sha256su0 v7.2d, v7.2d
58 sha1m v8.4s, v7.4s, q8
59 sha1su0 v0.2d, v1.2d, v2.2d
62 pmull v7.8b, v15.8b, v31.8b
63 pmull v7.1q, v15.1q, v31.1d
64 pmull2 v7.8h, v15.8b, v31.8b
65 pmull2 v7.1q, v15.2d, v31.1q
67 ld2 {v1.4h, v0.4h}, [x1]
68 strb x0, [sp, x1, lsl #0]
69 strb w7, [x30, x0, lsl]
70 strb w7, [x30, x0, lsl #1]
77 st2 {v4.2d, v5.2d}, [x3, #3]
78 st2 {v4.2d, v5.2d, v6.2d}, [x3]
79 st1 {v4.2d, v6.2d, v8.2d}, [x3]
80 st3 {v4.2d, v6.2d}, [x3]
81 st4 {v4.2d, v6.2d}, [x3]
82 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3]
83 st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3], 48
85 ext v0.8b, v1.8b, v2.8b, 8
86 ext v0.16b, v1.16b, v2.16b, 20
100 smaddl x0, w1, w2, w3
102 ld1 {v1.s, v2.s}[1], [x3]
103 st1 {v2.s, v3.s}[1], [x4]
104 ld2 {v1.s, v2.s, v3.s}[1], [x3]
105 st2 {v2.s, v2.s, v3.s}[1], [x4]
106 ld3 {v1.s, v2.s, v3.s, v4.s}[1], [x3]
107 st3 {v2.s, v3.s, v4.s, v5.s}[1], [x4]
111 ld2 {v1.b, v3.b}[1], [x3]
112 st2 {v2.b, v4.b}[1], [x4]
113 ld3 {v1.b, v3.b, v5.b}[1], [x3]
114 st3 {v2.b, v4.b, v6.b}[1], [x4]
115 ld4 {v1.b, v3.b, v5.b, v7.b}[1], [x3]
116 st4 {v2.b, v4.b, v6.b, v8.b}[1], [x4]
120 ld1r {v1.4s, v3.4s}, [x3]
121 ld1r {v1.4s, v2.4s, v3.4s}, [x3]
122 ld2r {v1.4s, v2.4s, v3.4s}, [x3]
123 ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3]
126 ld1r {v1.4s, v3.4s}, [x3], x4
127 ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
128 ld2r {v1.4s, v2.4s, v3.4s}, [x3], x4
129 ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], x4
130 ld4r {v1.4s}, [x3], x4
132 ld1r {v1.4s}, [x3], #1
133 ld1r {v1.4s, v2.4s}, [x3], #8
134 ld2r {v1.4s, v2.4s}, [x3], #4
135 ld3r {v1.4s, v2.4s, v3.4s}, [x3], #16
136 ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], #32
146 shll v0.8h, v1.8b, 16
147 shll2 v0.2d, v1.4s, 16
159 sshr v0.4s, v1.4s, #0
160 sshr v0.4s, v1.4s, #33
161 sshr v0.4h, v1.4h, #20
163 shl v0.4s, v1.4s, #32
164 fcvtzs v0.2h, v1.2h, #2
165 uqshrn v0.2s, v1.2d, 33
166 uqrshrn v0.2s, v1.2s, 32
167 sshll v8.8h, v2.8b, #8
169 sysl x7, #10, C15, C7, #11
170 sysl w7, #1, C15, C7, #1
177 prfm pldl3strm, [sp, #8]!
178 prfm pldl3strm, [sp], #8
179 prfm pldl3strm, [sp, w0, sxtw #3]!
180 prfm pldl3strm, =0x100
199 sys #0, c0, c0, 0, w0
203 movz x1,#:abs_g2:u48, lsl #16
204 movz x1, 0xddee, lsl #8
207 movk x1,#:abs_g1_s:s12
210 movi v0.2d, #0xabcdef
212 bic v0.4s, #255, msl #8
214 bic v0.4s, #1, lsl #31
215 // bic v0.4h, #1, lsl #16
217 orr v0.4s, #255, msl #8
220 movi v0.4s, #127, lsl #4
221 movi v0.4s, #127, msl #24
222 // movi v0.4h, #127, lsl #16
224 mvni v0.4s, #127, lsl #4
225 mvni v0.4s, #127, msl #24
226 // mvni v0.4h, #127, lsl #16
228 fmov v0.2s, #3.1415926
229 fmov v0.4s, #3.1415926
230 fmov v0.2d, #3.1415926
237 tbl v0.16b, {v1.16b, v3.16b, v5.16b}, v2.16b
238 tbx v0.8b, {v1.16b, v3.16b, v5.16b, v7.16b}, v2.8b
240 // Alternating register list forms are no longer available A64 ISA
242 .macro ldst2_reg_list_post_imm_reg_64 inst type postreg
243 \inst\()2 {v0.\type, v2.\type}, [x0], #16
244 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
246 \inst\()2 {v0.\type, v2.\type}, [x0], \postreg
247 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
251 .macro ldst2_reg_list_post_imm_reg_128 inst type postreg
252 \inst\()2 {v0.\type, v2.\type}, [x0], #32
253 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
255 \inst\()2 {v0.\type, v2.\type}, [x0], \postreg
256 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
261 .irp bits_64 8b, 4h, 2s
262 ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7
267 .irp bits_128 16b, 8h, 4s, 2d
268 ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7
272 .macro ldst34_reg_list_post_imm_reg_64 inst type postreg
273 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #24
274 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #32
275 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
276 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
279 .macro ldst34_reg_list_post_imm_reg_128 inst type postreg
280 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #48
281 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #64
282 \inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
283 \inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
287 .irp bits_64 8b, 4h, 2s
288 ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7
293 .irp bits_128 16b, 8h, 4s, 2d
294 ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7
298 // LD1R expects one register only.
300 ld1r {v0.8b, v1.8b}, [x0], #1
301 ld1r {v0.16b, v1.16b}, [x0], #1
302 ld1r {v0.4h, v1.4h}, [x0], #2
303 ld1r {v0.8h, v1.8h}, [x0], #2
304 ld1r {v0.2s, v1.2s}, [x0], #4
305 ld1r {v0.4s, v1.4s}, [x0], #4
306 ld1r {v0.1d, v1.1d}, [x0], #8
307 ld1r {v0.2d, v1.2d}, [x0], #8
309 .macro ldstn_index_rep_H_altreg_imm inst index type rep
310 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #4
311 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #6
312 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #8
316 ldstn_index_rep_H_altreg_imm \instr index="[1]" type=h rep=""
319 ldstn_index_rep_H_altreg_imm \instr index="" type=\types rep="r"
324 .macro ldstn_index_rep_S_altreg_imm inst index type rep
325 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #8
326 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #12
327 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #16
331 ldstn_index_rep_S_altreg_imm \instr index="[1]" type=s rep=""
334 ldstn_index_rep_S_altreg_imm \instr index="" type=\types rep="r"
339 .macro ldstn_index_rep_D_altreg_imm inst index type rep
340 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], #16
341 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #24
342 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #32
346 ldstn_index_rep_D_altreg_imm \instr index="[1]" type=d rep=""
349 ldstn_index_rep_D_altreg_imm \instr index="" type=\types rep="r"
354 .irp type 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
355 ld1r {v0.\type, v1.\type}, [x0], x7
358 .macro ldstn_index_rep_reg_altreg inst index type rep postreg
359 \inst\()2\rep {v0.\type, v2.\type}\index, [x0], \postreg
360 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], \postreg
361 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], \postreg
366 ldstn_index_rep_reg_altreg \instr index="[1]" type=\itypes rep="" postreg=x7
369 .irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
370 ldstn_index_rep_reg_altreg \instr index="" type=\types rep="r" postreg=x7
375 .macro ldnstn_reg_list type inst index rep
378 \inst\()1\rep {v0.\type, v1.\type}\index, [x0]
383 \inst\()2\rep {v0.\type, v2.\type}\index, [x0]
387 \inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0]
391 \inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0]
396 ldnstn_reg_list type="8B", inst="ld" index="" rep=""
397 ldnstn_reg_list type="8B", inst="st" index="" rep=""
399 ldnstn_reg_list type="16B", inst="ld" index="" rep=""
400 ldnstn_reg_list type="16B", inst="st" index="" rep=""
402 ldnstn_reg_list type="4H", inst="ld" index="" rep=""
403 ldnstn_reg_list type="4H", inst="st" index="" rep=""
405 ldnstn_reg_list type="8H", inst="ld" index="" rep=""
406 ldnstn_reg_list type="8H", inst="st" index="" rep=""
408 ldnstn_reg_list type="2S", inst="ld" index="" rep=""
409 ldnstn_reg_list type="2S", inst="st" index="" rep=""
411 ldnstn_reg_list type="4S", inst="ld" index="" rep=""
412 ldnstn_reg_list type="4S", inst="st" index="" rep=""
414 ldnstn_reg_list type="2D", inst="ld" index="" rep=""
415 ldnstn_reg_list type="2D", inst="st" index="" rep=""
417 ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
418 ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
420 ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
421 ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
423 ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
424 ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
426 ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
427 ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
429 ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
430 ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
432 ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
433 ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
435 ldnstn_reg_list type="D", inst="ld" index="[1]" rep=""
436 ldnstn_reg_list type="D", inst="st" index="[1]" rep=""
438 ldnstn_reg_list type="8B", inst="ld" index="" rep="r"
440 ldnstn_reg_list type="16B", inst="ld" index="" rep="r"
442 ldnstn_reg_list type="4H", inst="ld" index="" rep="r"
444 ldnstn_reg_list type="8H", inst="ld" index="" rep="r"
446 ldnstn_reg_list type="2S", inst="ld" index="" rep="r"
448 ldnstn_reg_list type="4S", inst="ld" index="" rep="r"
450 ldnstn_reg_list type="1D", inst="ld" index="" rep="r"
452 ldnstn_reg_list type="2D", inst="ld" index="" rep="r"
454 pmull v0.1q, v1.1d, v2.1d
455 pmull2 v0.1q, v1.2d, v2.2d
457 // #<fbits> out of range
458 .irp instr, scvtf, ucvtf
464 .irp instr, fcvtzs, fcvtzu
471 // Invalid instruction.
475 ldrh w0, [x1, x2, lsr #1]
477 add w0, w1, w2, ror #1
478 sub w0, w1, w2, asr #32
479 eor w0, w1, w2, ror #32
481 add x0, x1, #20, LSL #16
482 add x0, x1, #20, UXTX #12
486 ldnp h7, h15, [x0, #2]
487 ldnp b15, b31, [x0], #4
488 ldnp h0, h1, [x0, #6]!
493 bfxil w7, w15, #15, #30
496 str x1,page_table_count
498 prfm PLDL3KEEP, [x9, x15, sxtx #2]
500 mrs x5, S1_0_C17_C8_0
501 msr S3_1_C13_C15_1, x7
502 msr S3_1_C11_C15_-1, x7
505 // MOVI (alias of ORR immediate) is no longer supported.
507 .set u48, 0xaabbccddeeff
523 uabdl2 v20.4S, v12.8H, v29.8
525 movi d1, 0xffff, lsl #16
527 ST3 {v18.D-v20.D}[0],[x28],x
529 ST1 {v22.1D-v25.1D},[x10],x
534 orr x0, x0, #0xff, lsl #1
535 orr x0. x0, #0xff, lsl #1
536 orr x0, x0, #0xff lsl #1
544 fmov s0, #0xC0280000C1400000
545 fmov d0, #0xC02f800000000000
547 // No 16-byte relocation
550 ands w0, w24, #0xffeefffffffffffd
565 mrs x5, S4_0_C12_C8_0
566 mrs x6, S0_8_C11_C7_5
567 mrs x7, S1_1_C16_C6_6
568 mrs x8, S2_2_C15_C16_7
569 mrs x9, S3_3_C14_C15_8
572 fmov s0, #0x40000000 // OK
574 fmov s0, #0xc0000000 // OK
576 fmov d0, #0x4000000000000000 // OK
577 fmov d0, #0x8000000000000000
578 fmov d0, #0xc000000000000000 // OK
580 fcmgt v0.4s, v0.4s, #0.0 // OK
581 fcmgt v0.4s, v0.4s, #0 // OK
582 fcmgt v0.4s, v0.4s, #-0.0
583 fcmgt v0.2d, v0.2d, #0.0 // OK
584 fcmgt v0.2d, v0.2d, #0 // OK
585 fcmgt v0.2d, v0.2d, #-0.0
587 # PR 20319: FMOV instructions changing the size from 32 bits
588 # to 64 bits and vice versa are illegal.
593 st2 {v0.16b-v1.16b}[1],[x0]
594 st3 {v0.16b-v2.16b}[2],[x0]
595 st4 {v0.8b-v3.8b}[4],[x0]
597 // End (for errors during literal pool generation)