1 // diagnostic.s Test file for diagnostic quality.
9 aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
11 ext v0.8b, v1.8b, v2.8b, 8
12 ext v0.16b, v1.16b, v2.16b, 20
24 smlal v0.4s, v31.4h, v16.h[1]
25 smlal v0.4s, v31.4h, v15.h[8]
26 add sp, x0, x7, lsr #2
27 add x0, x0, x7, uxtx #5
28 add x0, xzr, x7, ror #5
29 add w0, wzr, w7, asr #32
30 st2 {v0.4s, v1.4s}, [sp], #24
31 ldr q0, [x0, w0, uxtw #5]
32 st2 {v0.4s, v1.4s, v2.4s, v3.4s}, [sp], #64
33 adds x1, sp, 2134, lsl #4
35 movz w0, 2134, lsl #32
36 movz x0, 2134, lsl #47
39 shll v1.4s, v2.4h, #15
40 shll v1.4s, v2.4h, #32
42 sqshrn2 v2.16b, v3.8h, #17
45 movi v1.4h, 255, msl #8
47 movi v1.4h, 255, lsl #7
48 movi v1.4h, 255, lsl #16
49 movi v2.2s, 255, msl #0
50 movi v2.2s, 255, msl #15
59 st2 {v0.4s, v1.4s}, [sp], sp
60 st2 {v0.4s, v1.4s}, [sp], zr
61 ldr q0, [x0, w0, lsr #4]
62 adds x1, sp, 2134, uxtw #12
63 movz x0, 2134, lsl #64
64 adds sp, sp, 2134, lsl #12
67 prfm PLDL3KEEP, [x9, x15, sxtx #2]
68 sysl x7, #1, C16, C30, #1
69 sysl x7, #1, C15, C77, #1
70 add x0, xzr, x7, uxtx #5
74 orr x0. x0, #0xff, lsl #1
75 movk x1, #:abs_g1_s:s12
76 movz x1, #:abs_g1_s:s12, lsl #16
77 prfm pldl3strm, [sp, w0, sxtw #3]!
81 st2 {v4.2d, v5.2d, v6.2d}, [x3]
82 ld2 {v1.4h, v0.4h}, [x1]
84 st2 {v4.2d, v5.2d, v6.2d}, \[x3\]
85 ldnp w7, w15, [x3, #3]
86 stnp x7, x15, [x3, #32]!
87 ldnp w7, w15, [x3, #256]
88 movi v1.2d, 4294967295, lsl #0
89 movi v1.8b, 97, lsl #8
103 # test diagnostic info on optional operand
109 sys #0, c0, c0, #0, kk
112 casp w0,w1,w2,w3,[x4]
114 # test warning of unpredictable load pairs
117 ldp x0, x0, [sp], #16
120 # test warning of unpredictable writeback
124 stp x0, x1, [x0, #16]!
125 ldp x0, x1, [x1], #16
127 ldr x0, [x0, :got:s1]
129 # Test error of 32-bit base reg
131 ldp x6, x29, [w7, #8]!
133 stp x8, x27, [wsp, #8]!
135 # Test various valid load/store reg combination.
136 # especially we shouldn't warn on xzr, although
137 # xzr is with the same encoding 31 as sp.
138 .macro ldst_pair_wb_2 op, reg1, reg2
139 .irp base x3, x6, x25, sp
140 \op \reg1, \reg2, [\base], #16
141 \op \reg1, \reg2, [\base, #32]!
142 \op \reg2, \reg1, [\base], #32
143 \op \reg2, \reg1, [\base, #16]!
147 .macro ldst_pair_wb_1 op, reg1, width
148 .irp reg2 0, 14, 21, 23, 29
149 ldst_pair_wb_2 \op, \reg1, \width\reg2
153 .macro ldst_pair_wb_64 op
154 .irp reg1 x2, x15, x16, x27, x30, xzr
155 ldst_pair_wb_1 \op, \reg1, x
159 .macro ldst_pair_wb_32 op
160 .irp reg1 w1, w12, w16, w19, w30, wzr
161 ldst_pair_wb_1 \op, \reg1, w
165 .macro ldst_single_wb_1 op, reg
166 .irp base x1, x4, x13, x26, sp
167 \op \reg, [\base], #16
171 .macro ldst_single_wb_32 op
172 .irp reg w0, w3, w12, w21, w28, w30, wzr
173 ldst_single_wb_1 \op, \reg
177 .macro ldst_single_wb_64 op
178 .irp reg x2, x5, x17, x23, x24, x30, xzr
179 ldst_single_wb_1 \op, \reg
189 ldst_pair_wb_64 ldpsw
191 ldst_single_wb_32 str
192 ldst_single_wb_64 str
194 ldst_single_wb_32 strb
196 ldst_single_wb_32 strh
198 ldst_single_wb_32 ldr
199 ldst_single_wb_64 ldr
201 ldst_single_wb_32 ldrb
203 ldst_single_wb_32 ldrh
205 ldst_single_wb_32 ldrsb
206 ldst_single_wb_64 ldrsb
208 ldst_single_wb_32 ldrsh
209 ldst_single_wb_64 ldrsh
211 ldst_single_wb_64 ldrsw