1 // diagnostic.s Test file for diagnostic quality.
9 aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
11 ext v0.8b, v1.8b, v2.8b, 8
12 ext v0.16b, v1.16b, v2.16b, 20
24 smlal v0.4s, v31.4h, v16.h[1]
25 smlal v0.4s, v31.4h, v15.h[8]
26 add sp, x0, x7, lsr #2
27 add x0, x0, x7, uxtx #5
28 add x0, xzr, x7, ror #5
29 add w0, wzr, w7, asr #32
30 st2 {v0.4s, v1.4s}, [sp], #24
31 ldr q0, [x0, w0, uxtw #5]
32 st2 {v0.4s, v1.4s, v2.4s, v3.4s}, [sp], #64
33 adds x1, sp, 2134, lsl #4
35 movz w0, 2134, lsl #32
36 movz x0, 2134, lsl #47
39 shll v1.4s, v2.4h, #15
40 shll v1.4s, v2.4h, #32
42 sqshrn2 v2.16b, v3.8h, #17
45 movi v1.4h, 255, msl #8
47 movi v1.4h, 255, lsl #7
48 movi v1.4h, 255, lsl #16
49 movi v2.2s, 255, msl #0
50 movi v2.2s, 255, msl #15
59 st2 {v0.4s, v1.4s}, [sp], sp
60 st2 {v0.4s, v1.4s}, [sp], zr
61 ldr q0, [x0, w0, lsr #4]
62 adds x1, sp, 2134, uxtw #12
63 movz x0, 2134, lsl #64
64 adds sp, sp, 2134, lsl #12
67 prfm PLDL3KEEP, [x9, x15, sxtx #2]
68 sysl x7, #1, C16, C30, #1
69 sysl x7, #1, C15, C77, #1
70 sysl x7, #1, x15, C1, #1
71 add x0, xzr, x7, uxtx #5
75 orr x0. x0, #0xff, lsl #1
76 movk x1, #:abs_g1_s:s12
77 movz x1, #:abs_g1_s:s12, lsl #16
78 prfm pldl3strm, [sp, w0, sxtw #3]!
82 st2 {v4.2d, v5.2d, v6.2d}, [x3]
83 ld2 {v1.4h, v0.4h}, [x1]
85 st2 {v4.2d, v5.2d, v6.2d}, \[x3\]
86 ldnp w7, w15, [x3, #3]
87 stnp x7, x15, [x3, #32]!
88 ldnp w7, w15, [x3, #256]
89 movi v1.2d, 4294967295, lsl #0
90 movi v1.8b, 97, lsl #8
104 # test diagnostic info on optional operand
110 sys #0, c0, c0, #0, kk
113 casp w0,w1,w2,w3,[x4]
115 # test warning of unpredictable load pairs
118 ldp x0, x0, [sp], #16
121 # test warning of unpredictable writeback
125 stp x0, x1, [x0, #16]!
126 ldp x0, x1, [x1], #16
128 ldr x0, [x0, :got:s1]
130 # Test error of 32-bit base reg
132 ldp x6, x29, [w7, #8]!
134 stp x8, x27, [wsp, #8]!
136 # Test various valid load/store reg combination.
137 # especially we shouldn't warn on xzr, although
138 # xzr is with the same encoding 31 as sp.
139 .macro ldst_pair_wb_2 op, reg1, reg2
140 .irp base x3, x6, x25, sp
141 \op \reg1, \reg2, [\base], #16
142 \op \reg1, \reg2, [\base, #32]!
143 \op \reg2, \reg1, [\base], #32
144 \op \reg2, \reg1, [\base, #16]!
148 .macro ldst_pair_wb_1 op, reg1, width
149 .irp reg2 0, 14, 21, 23, 29
150 ldst_pair_wb_2 \op, \reg1, \width\reg2
154 .macro ldst_pair_wb_64 op
155 .irp reg1 x2, x15, x16, x27, x30, xzr
156 ldst_pair_wb_1 \op, \reg1, x
160 .macro ldst_pair_wb_32 op
161 .irp reg1 w1, w12, w16, w19, w30, wzr
162 ldst_pair_wb_1 \op, \reg1, w
166 .macro ldst_single_wb_1 op, reg
167 .irp base x1, x4, x13, x26, sp
168 \op \reg, [\base], #16
172 .macro ldst_single_wb_32 op
173 .irp reg w0, w3, w12, w21, w28, w30, wzr
174 ldst_single_wb_1 \op, \reg
178 .macro ldst_single_wb_64 op
179 .irp reg x2, x5, x17, x23, x24, x30, xzr
180 ldst_single_wb_1 \op, \reg
190 ldst_pair_wb_64 ldpsw
192 ldst_single_wb_32 str
193 ldst_single_wb_64 str
195 ldst_single_wb_32 strb
197 ldst_single_wb_32 strh
199 ldst_single_wb_32 ldr
200 ldst_single_wb_64 ldr
202 ldst_single_wb_32 ldrb
204 ldst_single_wb_32 ldrh
206 ldst_single_wb_32 ldrsb
207 ldst_single_wb_64 ldrsb
209 ldst_single_wb_32 ldrsh
210 ldst_single_wb_64 ldrsh
212 ldst_single_wb_64 ldrsw
232 dup v0.16b, v1.16b[-1]
233 dup v0.16b, v1.16b[0]
234 dup v0.16b, v1.16b[15]
235 dup v0.16b, v1.16b[16]
236 dup v0.16b, v1.16b[67]
238 ld2 {v0.d, v1.d}[-1], [x0]
239 ld2 {v0.d, v1.d}[0], [x0]
240 ld2 {v0.d, v1.d}[1], [x0]
241 ld2 {v0.d, v1.d}[2], [x0]
242 ld2 {v0.d, v1.d}[64], [x0]
244 ld2 {v0.s, v1.s}[-1], [x0]
245 ld2 {v0.s, v1.s}[0], [x0]
246 ld2 {v0.s, v1.s}[3], [x0]
247 ld2 {v0.s, v1.s}[4], [x0]
248 ld2 {v0.s, v1.s}[65], [x0]
250 ld2 {v0.h, v1.h}[-1], [x0]
251 ld2 {v0.h, v1.h}[0], [x0]
252 ld2 {v0.h, v1.h}[7], [x0]
253 ld2 {v0.h, v1.h}[8], [x0]
254 ld2 {v0.h, v1.h}[66], [x0]
256 ld2 {v0.b, v1.b}[-1], [x0]
257 ld2 {v0.b, v1.b}[0], [x0]
258 ld2 {v0.b, v1.b}[15], [x0]
259 ld2 {v0.b, v1.b}[16], [x0]
260 ld2 {v0.b, v1.b}[67], [x0]
267 st2 {v0.4s, v1.4s}, [sp], xzr
270 ldr x0, [x1, #:lo12:foo] // OK
271 ldnp x1, x2, [x3, #:lo12:foo]
272 ld1 {v0.4s}, [x3, #:lo12:foo]
273 stuminl x0, [x3, #:lo12:foo]
274 prfum pldl1keep, [x3, #:lo12:foo]
277 ldnp x1, x2, [x3], x4
278 ld1 {v0.4s}, [x3], x4 // OK
280 prfum pldl1keep, [x3], x4
282 ldr x0, [x1, #1, mul vl]
283 ldr x0, [x1, x2, mul vl]
284 ldr x0, [x1, x2, mul #1]
285 ldr x0, [x1, x2, mul #4]
287 strb w7, [x30, x0, mul]
288 strb w7, [x30, x0, mul #1]
289 strb w7, [x30, w0, mul]
290 strb w7, [x30, w0, mul #2]
292 adds x1, sp, 1, mul #1
293 adds x1, sp, 2, mul #255
294 adds x1, sp, 3, mul #256
295 orr x0, x0, #0xff, mul #1
296 orr x0, x0, #0xfe, mul #255
297 orr x0, x0, #0xfc, mul #256
304 stlxrb w26, w26, [x0]
305 stlxrh w26, w26, [x1]
307 stlxrb w26, w27, [x26]
308 stlxrh w26, w27, [x26]
309 stlxr w26, w27, [x26]
310 stlxr w26, x27, [x26]
314 st4 {v0.16b-v3.16b}[4], [x0]