4 Copyright (C) 1997 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /*======================================================================*/
25 * Herein lies the support for dynamic specification of processor
26 * instructions and registers. Mnemonics, values, and formats for each
27 * instruction and register are specified in an ascii file consisting of
28 * table entries. The grammar for the table is defined in the document
29 * "Processor instruction table specification".
31 * Instructions use the gnu assembler syntax, with the addition of
32 * allowing mnemonics for register.
33 * Eg. "func $2,reg3,0x100,symbol ; comment"
36 * reg3 - mnemonic for processor's register defined in table
37 * 0xddd..d - immediate value
38 * symbol - address of label or external symbol
40 * First, itbl_parse reads in the table of register and instruction
41 * names and formats, and builds a list of entries for each
42 * processor/type combination. lex and yacc are used to parse
43 * the entries in the table and call functions defined here to
44 * add each entry to our list.
46 * Then, when assembling or disassembling, these functions are called to
47 * 1) get information on a processor's registers and
48 * 2) assemble/disassemble an instruction.
49 * To assemble(disassemble) an instruction, the function
50 * itbl_assemble(itbl_disassemble) is called to search the list of
51 * instruction entries, and if a match is found, uses the format
52 * described in the instruction entry structure to complete the action.
54 * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2"
55 * and we want to define function "pig" which takes two operands.
57 * Given the table entries:
58 * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0"
60 * and that the instruction encoding for coprocessor pz has encoding:
61 * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25)
62 * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum)
64 * a structure to describe the instruction might look something like:
65 * struct itbl_entry = {
66 * e_processor processor = e_p3
67 * e_type type = e_insn
71 * struct itbl_range range = 24-21
72 * struct itbl_field *field = {
73 * e_type type = e_dreg
74 * struct itbl_range range = 20-16
75 * struct itbl_field *next = {
76 * e_type type = e_immed
77 * struct itbl_range range = 15-0
78 * struct itbl_field *next = 0
81 * struct itbl_entry *next = 0
84 * And the assembler instructions:
88 * would both assemble to the hex value:
97 #include "itbl-parse.h"
103 #define ASSERT(x) assert(x)
104 #define DBG(x) printf x
111 #define min(a,b) (a<b?a:b)
114 int itbl_have_entries = 0;
116 /*======================================================================*/
117 /* structures for keeping itbl format entries */
121 int sbit; /* mask starting bit position */
122 int ebit; /* mask ending bit position */
127 e_type type; /* dreg/creg/greg/immed/symb */
128 struct itbl_range range; /* field's bitfield range within instruction */
129 unsigned long flags; /* field flags */
130 struct itbl_field *next; /* next field in list */
134 /* These structures define the instructions and registers for a processor.
135 * If the type is an instruction, the structure defines the format of an
136 * instruction where the fields are the list of operands.
137 * The flags field below uses the same values as those defined in the
138 * gnu assembler and are machine specific. */
141 e_processor processor; /* processor number */
142 e_type type; /* dreg/creg/greg/insn */
143 char *name; /* mnemionic name for insn/register */
144 unsigned long value; /* opcode/instruction mask/register number */
145 unsigned long flags; /* effects of the instruction */
146 struct itbl_range range; /* bit range within instruction for value */
147 struct itbl_field *fields; /* list of operand definitions (if any) */
148 struct itbl_entry *next; /* next entry */
152 /* local data and structures */
154 static int itbl_num_opcodes = 0;
155 /* Array of entries for each processor and entry type */
156 static struct itbl_entry *entries[e_nprocs][e_ntypes] =
164 /* local prototypes */
165 static unsigned long build_opcode PARAMS ((struct itbl_entry *e));
166 static e_type get_type PARAMS ((int yytype));
167 static e_processor get_processor PARAMS ((int yyproc));
168 static struct itbl_entry **get_entries PARAMS ((e_processor processor,
170 static struct itbl_entry *find_entry_byname PARAMS ((e_processor processor,
171 e_type type, char *name));
172 static struct itbl_entry *find_entry_byval PARAMS ((e_processor processor,
173 e_type type, unsigned long val, struct itbl_range *r));
174 static struct itbl_entry *alloc_entry PARAMS ((e_processor processor,
175 e_type type, char *name, unsigned long value));
176 static unsigned long apply_range PARAMS ((unsigned long value,
177 struct itbl_range r));
178 static unsigned long extract_range PARAMS ((unsigned long value,
179 struct itbl_range r));
180 static struct itbl_field *alloc_field PARAMS ((e_type type, int sbit,
181 int ebit, unsigned long flags));
184 /*======================================================================*/
185 /* Interfaces to the parser */
188 /* Open the table and use lex and yacc to parse the entries.
189 * Return 1 for failure; 0 for success. */
192 itbl_parse (char *insntbl)
195 extern int yyparse (void);
196 yyin = fopen (insntbl, "r");
199 printf ("Can't open processor instruction specification file \"%s\"\n",
208 itbl_have_entries = 1;
212 /* Add a register entry */
215 itbl_add_reg (int yyprocessor, int yytype, char *regname,
221 /* Since register names don't have a prefix, we put them in the symbol table so
222 they can't be used as symbols. This also simplifies argument parsing as
223 we can let gas parse registers for us. The recorded register number is
225 /* Use symbol_create here instead of symbol_new so we don't try to
226 output registers into the object file's symbol table. */
227 symbol_table_insert (symbol_create (regname, reg_section,
228 regnum, &zero_address_frag));
230 return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname,
231 (unsigned long) regnum);
234 /* Add an instruction entry */
237 itbl_add_insn (int yyprocessor, char *name, unsigned long value,
238 int sbit, int ebit, unsigned long flags)
240 struct itbl_entry *e;
241 e = alloc_entry (get_processor (yyprocessor), e_insn, name, value);
244 e->range.sbit = sbit;
245 e->range.ebit = ebit;
252 /* Add an operand to an instruction entry */
255 itbl_add_operand (struct itbl_entry *e, int yytype, int sbit,
256 int ebit, unsigned long flags)
258 struct itbl_field *f, **last_f;
261 /* Add to end of fields' list. */
262 f = alloc_field (get_type (yytype), sbit, ebit, flags);
267 last_f = &(*last_f)->next;
275 /*======================================================================*/
276 /* Interfaces for assembler and disassembler */
281 static void append_insns_as_macros (void);
283 /* initialize for gas */
287 struct itbl_entry *e, **es;
291 /* Since register names don't have a prefix, put them in the symbol table so
292 they can't be used as symbols. This simplifies argument parsing as
293 we can let gas parse registers for us. */
294 /* Use symbol_create instead of symbol_new so we don't try to
295 output registers into the object file's symbol table. */
297 for (type = e_regtype0; type < e_nregtypes; type++)
298 for (procn = e_p0; procn < e_nprocs; procn++)
300 es = get_entries (procn, type);
301 for (e = *es; e; e = e->next)
303 symbol_table_insert (symbol_create (e->name, reg_section,
304 e->value, &zero_address_frag));
307 append_insns_as_macros ();
311 /* Append insns to opcodes table and increase number of opcodes
312 * Structure of opcodes table:
316 * const char *args; - string describing the arguments.
317 * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO
318 * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO
319 * unsigned long pinfo; - insn flags, or INSN_MACRO
322 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
323 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
326 static char *form_args (struct itbl_entry *e);
328 append_insns_as_macros (void)
330 struct ITBL_OPCODE_STRUCT *new_opcodes, *o;
331 struct itbl_entry *e, **es;
332 int n, id, size, new_size, new_num_opcodes;
334 ASSERT (itbl_num_opcodes > 0);
335 if (!itbl_num_opcodes) /* no new instructions to add! */
339 DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES));
341 new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes;
342 ASSERT (new_num_opcodes >= itbl_num_opcodes);
344 size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES;
346 DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0])));
348 new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes;
349 ASSERT (new_size > size);
351 /* FIXME since ITBL_OPCODES culd be a static table,
352 we can't realloc or delete the old memory. */
353 new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size);
356 printf ("Unable to allocate memory for new instructions\n");
359 if (size) /* copy prexisting opcodes table */
360 memcpy (new_opcodes, ITBL_OPCODES, size);
362 /* FIXME! some NUMOPCODES are calculated expressions.
363 These need to be changed before itbls can be supported. */
365 id = ITBL_NUM_MACROS; /* begin the next macro id after the last */
366 o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */
367 for (n = e_p0; n < e_nprocs; n++)
369 es = get_entries (n, e_insn);
370 for (e = *es; e; e = e->next)
372 /* name, args, mask, match, pinfo
373 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
374 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
375 * Construct args from itbl_fields.
378 o->args = strdup (form_args (e));
379 o->mask = apply_range (e->value, e->range);
380 /* FIXME how to catch durring assembly? */
381 /* mask to identify this insn */
382 o->match = apply_range (e->value, e->range);
386 o->mask = id++; /* FIXME how to catch durring assembly? */
387 o->match = 0; /* for macros, the insn_isa number */
388 o->pinfo = INSN_MACRO;
391 /* Don't add instructions which caused an error */
398 ITBL_OPCODES = new_opcodes;
399 ITBL_NUM_OPCODES = new_num_opcodes;
402 At this point, we can free the entries, as they should have
403 been added to the assembler's tables.
404 Don't free name though, since name is being used by the new
407 Eventually, we should also free the new opcodes table itself
413 form_args (struct itbl_entry *e)
417 struct itbl_field *f;
420 for (f = e->fields; f; f = f->next)
440 c = 0; /* ignore; unknown field type */
452 #endif /* !STAND_ALONE */
455 /* Get processor's register name from val */
458 itbl_get_reg_val (char *name)
463 for (p = e_p0; p < e_nprocs; p++)
464 for (t = e_regtype0; t < e_nregtypes; t++)
466 if (r = itbl_get_val (p, t, name), r)
473 itbl_get_name (e_processor processor, e_type type, unsigned long val)
475 struct itbl_entry *r;
476 /* type depends on instruction passed */
477 r = find_entry_byval (processor, type, val, 0);
481 return 0; /* error; invalid operand */
484 /* Get processor's register value from name */
487 itbl_get_val (e_processor processor, e_type type, char *name)
489 struct itbl_entry *r;
490 /* type depends on instruction passed */
491 r = find_entry_byname (processor, type, name);
495 return 0; /* error; invalid operand */
499 /* Assemble instruction "name" with operands "s".
500 * name - name of instruction
502 * returns - long word for assembled instruction */
505 itbl_assemble (char *name, char *s)
507 unsigned long opcode;
508 struct itbl_entry *e;
509 struct itbl_field *f;
514 return 0; /* error! must have a opcode name/expr */
516 /* find entry in list of instructions for all processors */
517 for (processor = 0; processor < e_nprocs; processor++)
519 e = find_entry_byname (processor, e_insn, name);
524 return 0; /* opcode not in table; invalid instrustion */
525 opcode = build_opcode (e);
527 /* parse opcode's args (if any) */
528 for (f = e->fields; f; f = f->next) /* for each arg, ... */
530 struct itbl_entry *r;
533 return 0; /* error - not enough operands */
534 n = itbl_get_field (&s);
535 /* n should be in form $n or 0xhhh (are symbol names valid?? */
541 /* Accept either a string name
542 * or '$' followed by the register number */
546 value = strtol (n, 0, 10);
547 /* FIXME! could have "0l"... then what?? */
548 if (value == 0 && *n != '0')
549 return 0; /* error; invalid operand */
553 r = find_entry_byname (e->processor, f->type, n);
557 return 0; /* error; invalid operand */
561 /* use assembler's symbol table to find symbol */
562 /* FIXME!! Do we need this?
563 if so, what about relocs??
564 my_getExpression (&imm_expr, s);
565 return 0; /-* error; invalid operand *-/
568 /* If not a symbol, fall thru to IMMED */
570 if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */
573 value = strtol (n, 0, 16);
574 /* FIXME! could have "0xl"... then what?? */
578 value = strtol (n, 0, 10);
579 /* FIXME! could have "0l"... then what?? */
580 if (value == 0 && *n != '0')
581 return 0; /* error; invalid operand */
585 return 0; /* error; invalid field spec */
587 opcode |= apply_range (value, f->range);
590 return 0; /* error - too many operands */
591 return opcode; /* done! */
594 /* Disassemble instruction "insn".
596 * s - buffer to hold disassembled instruction
597 * returns - 1 if succeeded; 0 if failed
601 itbl_disassemble (char *s, unsigned long insn)
603 e_processor processor;
604 struct itbl_entry *e;
605 struct itbl_field *f;
607 if (!ITBL_IS_INSN (insn))
609 processor = get_processor (ITBL_DECODE_PNUM (insn));
611 /* find entry in list */
612 e = find_entry_byval (processor, e_insn, insn, 0);
614 return 0; /* opcode not in table; invalid instrustion */
617 /* parse insn's args (if any) */
618 for (f = e->fields; f; f = f->next) /* for each arg, ... */
620 struct itbl_entry *r;
623 if (f == e->fields) /* first operand is preceeded by tab */
625 else /* ','s separate following operands */
627 value = extract_range (insn, f->range);
628 /* n should be in form $n or 0xhhh (are symbol names valid?? */
634 /* Accept either a string name
635 * or '$' followed by the register number */
636 r = find_entry_byval (e->processor, f->type, value, &f->range);
640 sprintf (s, "%s$%d", s, value);
643 /* use assembler's symbol table to find symbol */
644 /* FIXME!! Do we need this?
645 * if so, what about relocs??
647 /* If not a symbol, fall thru to IMMED */
649 sprintf (s, "%s0x%x", s, value);
652 return 0; /* error; invalid field spec */
655 return 1; /* done! */
658 /*======================================================================*/
660 * Local functions for manipulating private structures containing
661 * the names and format for the new instructions and registers
662 * for each processor.
665 /* Calculate instruction's opcode and function values from entry */
668 build_opcode (struct itbl_entry *e)
670 unsigned long opcode;
672 opcode = apply_range (e->value, e->range);
673 opcode |= ITBL_ENCODE_PNUM (e->processor);
677 /* Calculate absolute value given the relative value and bit position range
678 * within the instruction.
679 * The range is inclusive where 0 is least significant bit.
680 * A range of { 24, 20 } will have a mask of
682 * pos: 1098 7654 3210 9876 5432 1098 7654 3210
683 * bin: 0000 0001 1111 0000 0000 0000 0000 0000
684 * hex: 0 1 f 0 0 0 0 0
689 apply_range (unsigned long rval, struct itbl_range r)
693 int len = MAX_BITPOS - r.sbit;
695 ASSERT (r.sbit >= r.ebit);
696 ASSERT (MAX_BITPOS >= r.sbit);
697 ASSERT (r.ebit >= 0);
699 /* create mask by truncating 1s by shifting */
700 mask = 0xffffffff << len;
702 mask = mask >> r.ebit;
703 mask = mask << r.ebit;
705 aval = (rval << r.ebit) & mask;
709 /* Calculate relative value given the absolute value and bit position range
710 * within the instruction. */
713 extract_range (unsigned long aval, struct itbl_range r)
717 int len = MAX_BITPOS - r.sbit;
719 /* create mask by truncating 1s by shifting */
720 mask = 0xffffffff << len;
722 mask = mask >> r.ebit;
723 mask = mask << r.ebit;
725 rval = (aval & mask) >> r.ebit;
729 /* Extract processor's assembly instruction field name from s;
730 * forms are "n args" "n,args" or "n" */
731 /* Return next argument from string pointer "s" and advance s.
732 * delimiters are " ,\0" */
735 itbl_get_field (char **S)
745 if (ps = strchr (s, ','), ps)
747 if (ps = strchr (s, ' '), ps)
749 if (ps = strchr (s, '\0'), ps)
752 return 0; /* error! */
754 ASSERT (128 > len + 1);
758 s = 0; /* no more args */
760 s += len + 1; /* advance to next arg */
766 /* Search entries for a given processor and type
767 * to find one matching the name "n".
768 * Return a pointer to the entry */
770 static struct itbl_entry *
771 find_entry_byname (e_processor processor,
772 e_type type, char *n)
774 struct itbl_entry *e, **es;
776 es = get_entries (processor, type);
777 for (e = *es; e; e = e->next) /* for each entry, ... */
779 if (!strcmp (e->name, n))
785 /* Search entries for a given processor and type
786 * to find one matching the value "val" for the range "r".
787 * Return a pointer to the entry.
788 * This function is used for disassembling fields of an instruction.
791 static struct itbl_entry *
792 find_entry_byval (e_processor processor, e_type type,
793 unsigned long val, struct itbl_range *r)
795 struct itbl_entry *e, **es;
798 es = get_entries (processor, type);
799 for (e = *es; e; e = e->next) /* for each entry, ... */
801 if (processor != e->processor)
803 /* For insns, we might not know the range of the opcode,
804 * so a range of 0 will allow this routine to match against
805 * the range of the entry to be compared with.
806 * This could cause ambiguities.
807 * For operands, we get an extracted value and a range.
809 /* if range is 0, mask val against the range of the compared entry. */
810 if (r == 0) /* if no range passed, must be whole 32-bits
811 * so create 32-bit value from entry's range */
813 eval = apply_range (e->value, e->range);
814 val &= apply_range (0xffffffff, e->range);
816 else if (r->sbit == e->range.sbit && r->ebit == e->range.ebit
817 || e->range.sbit == 0 && e->range.ebit == 0)
819 eval = apply_range (e->value, *r);
820 val = apply_range (val, *r);
830 /* Return a pointer to the list of entries for a given processor and type. */
832 static struct itbl_entry **
833 get_entries (e_processor processor, e_type type)
835 return &entries[processor][type];
838 /* Return an integral value for the processor passed from yyparse. */
841 get_processor (int yyproc)
843 /* translate from yacc's processor to enum */
844 if (yyproc >= e_p0 && yyproc < e_nprocs)
845 return (e_processor) yyproc;
846 return e_invproc; /* error; invalid processor */
849 /* Return an integral value for the entry type passed from yyparse. */
852 get_type (int yytype)
856 /* translate from yacc's type to enum */
870 return e_invtype; /* error; invalid type */
875 /* Allocate and initialize an entry */
877 static struct itbl_entry *
878 alloc_entry (e_processor processor, e_type type,
879 char *name, unsigned long value)
881 struct itbl_entry *e, **es;
884 e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry));
887 memset (e, 0, sizeof (struct itbl_entry));
888 e->name = (char *) malloc (sizeof (strlen (name)) + 1);
890 strcpy (e->name, name);
891 e->processor = processor;
894 es = get_entries (e->processor, e->type);
901 /* Allocate and initialize an entry's field */
903 static struct itbl_field *
904 alloc_field (e_type type, int sbit, int ebit,
907 struct itbl_field *f;
908 f = (struct itbl_field *) malloc (sizeof (struct itbl_field));
911 memset (f, 0, sizeof (struct itbl_field));
913 f->range.sbit = sbit;
914 f->range.ebit = ebit;