2 Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 /*======================================================================*/
23 * Herein lies the support for dynamic specification of processor
24 * instructions and registers. Mnemonics, values, and formats for each
25 * instruction and register are specified in an ascii file consisting of
26 * table entries. The grammar for the table is defined in the document
27 * "Processor instruction table specification".
29 * Instructions use the gnu assembler syntax, with the addition of
30 * allowing mnemonics for register.
31 * Eg. "func $2,reg3,0x100,symbol ; comment"
34 * reg3 - mnemonic for processor's register defined in table
35 * 0xddd..d - immediate value
36 * symbol - address of label or external symbol
38 * First, itbl_parse reads in the table of register and instruction
39 * names and formats, and builds a list of entries for each
40 * processor/type combination. lex and yacc are used to parse
41 * the entries in the table and call functions defined here to
42 * add each entry to our list.
44 * Then, when assembling or disassembling, these functions are called to
45 * 1) get information on a processor's registers and
46 * 2) assemble/disassemble an instruction.
47 * To assemble(disassemble) an instruction, the function
48 * itbl_assemble(itbl_disassemble) is called to search the list of
49 * instruction entries, and if a match is found, uses the format
50 * described in the instruction entry structure to complete the action.
52 * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2"
53 * and we want to define function "pig" which takes two operands.
55 * Given the table entries:
56 * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0"
58 * and that the instruction encoding for coprocessor pz has encoding:
59 * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25)
60 * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum)
62 * a structure to describe the instruction might look something like:
63 * struct itbl_entry = {
64 * e_processor processor = e_p3
65 * e_type type = e_insn
69 * struct itbl_range range = 24-21
70 * struct itbl_field *field = {
71 * e_type type = e_dreg
72 * struct itbl_range range = 20-16
73 * struct itbl_field *next = {
74 * e_type type = e_immed
75 * struct itbl_range range = 15-0
76 * struct itbl_field *next = 0
79 * struct itbl_entry *next = 0
82 * And the assembler instructions:
86 * would both assemble to the hex value:
95 #include "itbl-parse.h"
101 #define ASSERT(x) assert(x)
102 #define DBG(x) printf x
109 #define min(a,b) (a<b?a:b)
112 int itbl_have_entries = 0;
114 /*======================================================================*/
115 /* structures for keeping itbl format entries */
119 int sbit; /* mask starting bit position */
120 int ebit; /* mask ending bit position */
125 e_type type; /* dreg/creg/greg/immed/symb */
126 struct itbl_range range; /* field's bitfield range within instruction */
127 unsigned long flags; /* field flags */
128 struct itbl_field *next; /* next field in list */
132 /* These structures define the instructions and registers for a processor.
133 * If the type is an instruction, the structure defines the format of an
134 * instruction where the fields are the list of operands.
135 * The flags field below uses the same values as those defined in the
136 * gnu assembler and are machine specific. */
139 e_processor processor; /* processor number */
140 e_type type; /* dreg/creg/greg/insn */
141 char *name; /* mnemionic name for insn/register */
142 unsigned long value; /* opcode/instruction mask/register number */
143 unsigned long flags; /* effects of the instruction */
144 struct itbl_range range; /* bit range within instruction for value */
145 struct itbl_field *fields; /* list of operand definitions (if any) */
146 struct itbl_entry *next; /* next entry */
150 /* local data and structures */
152 static int itbl_num_opcodes = 0;
153 /* Array of entries for each processor and entry type */
154 static struct itbl_entry *entries[e_nprocs][e_ntypes] =
162 /* local prototypes */
163 static unsigned long build_opcode PARAMS ((struct itbl_entry *e));
164 static e_type get_type PARAMS ((int yytype));
165 static e_processor get_processor PARAMS ((int yyproc));
166 static struct itbl_entry **get_entries PARAMS ((e_processor processor,
168 static struct itbl_entry *find_entry_byname PARAMS ((e_processor processor,
169 e_type type, char *name));
170 static struct itbl_entry *find_entry_byval PARAMS ((e_processor processor,
171 e_type type, unsigned long val, struct itbl_range *r));
172 static struct itbl_entry *alloc_entry PARAMS ((e_processor processor,
173 e_type type, char *name, unsigned long value));
174 static unsigned long apply_range PARAMS ((unsigned long value,
175 struct itbl_range r));
176 static unsigned long extract_range PARAMS ((unsigned long value,
177 struct itbl_range r));
178 static struct itbl_field *alloc_field PARAMS ((e_type type, int sbit,
179 int ebit, unsigned long flags));
182 /*======================================================================*/
183 /* Interfaces to the parser */
186 /* Open the table and use lex and yacc to parse the entries.
187 * Return 1 for failure; 0 for success. */
190 itbl_parse (char *insntbl)
193 extern int yyparse (void);
194 yyin = fopen (insntbl, "r");
197 printf ("Can't open processor instruction specification file \"%s\"\n",
206 itbl_have_entries = 1;
210 /* Add a register entry */
213 itbl_add_reg (int yyprocessor, int yytype, char *regname,
219 /* Since register names don't have a prefix, we put them in the symbol table so
220 they can't be used as symbols. This also simplifies argument parsing as
221 we can let gas parse registers for us. The recorded register number is
223 /* Use symbol_create here instead of symbol_new so we don't try to
224 output registers into the object file's symbol table. */
225 symbol_table_insert (symbol_create (regname, reg_section,
226 regnum, &zero_address_frag));
228 return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname,
229 (unsigned long) regnum);
232 /* Add an instruction entry */
235 itbl_add_insn (int yyprocessor, char *name, unsigned long value,
236 int sbit, int ebit, unsigned long flags)
238 struct itbl_entry *e;
239 e = alloc_entry (get_processor (yyprocessor), e_insn, name, value);
242 e->range.sbit = sbit;
243 e->range.ebit = ebit;
250 /* Add an operand to an instruction entry */
253 itbl_add_operand (struct itbl_entry *e, int yytype, int sbit,
254 int ebit, unsigned long flags)
256 struct itbl_field *f, **last_f;
259 /* Add to end of fields' list. */
260 f = alloc_field (get_type (yytype), sbit, ebit, flags);
265 last_f = &(*last_f)->next;
273 /*======================================================================*/
274 /* Interfaces for assembler and disassembler */
279 static void append_insns_as_macros (void);
281 /* initialize for gas */
285 struct itbl_entry *e, **es;
289 if (!itbl_have_entries)
292 /* Since register names don't have a prefix, put them in the symbol table so
293 they can't be used as symbols. This simplifies argument parsing as
294 we can let gas parse registers for us. */
295 /* Use symbol_create instead of symbol_new so we don't try to
296 output registers into the object file's symbol table. */
298 for (type = e_regtype0; type < e_nregtypes; type++)
299 for (procn = e_p0; procn < e_nprocs; procn++)
301 es = get_entries (procn, type);
302 for (e = *es; e; e = e->next)
304 symbol_table_insert (symbol_create (e->name, reg_section,
305 e->value, &zero_address_frag));
308 append_insns_as_macros ();
312 /* Append insns to opcodes table and increase number of opcodes
313 * Structure of opcodes table:
317 * const char *args; - string describing the arguments.
318 * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO
319 * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO
320 * unsigned long pinfo; - insn flags, or INSN_MACRO
323 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
324 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
327 static char *form_args (struct itbl_entry *e);
329 append_insns_as_macros (void)
331 struct ITBL_OPCODE_STRUCT *new_opcodes, *o;
332 struct itbl_entry *e, **es;
333 int n, id, size, new_size, new_num_opcodes;
335 if (!itbl_have_entries)
338 if (!itbl_num_opcodes) /* no new instructions to add! */
342 DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES));
344 new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes;
345 ASSERT (new_num_opcodes >= itbl_num_opcodes);
347 size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES;
349 DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0])));
351 new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes;
352 ASSERT (new_size > size);
354 /* FIXME since ITBL_OPCODES culd be a static table,
355 we can't realloc or delete the old memory. */
356 new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size);
359 printf (_("Unable to allocate memory for new instructions\n"));
362 if (size) /* copy prexisting opcodes table */
363 memcpy (new_opcodes, ITBL_OPCODES, size);
365 /* FIXME! some NUMOPCODES are calculated expressions.
366 These need to be changed before itbls can be supported. */
368 id = ITBL_NUM_MACROS; /* begin the next macro id after the last */
369 o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */
370 for (n = e_p0; n < e_nprocs; n++)
372 es = get_entries (n, e_insn);
373 for (e = *es; e; e = e->next)
375 /* name, args, mask, match, pinfo
376 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
377 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
378 * Construct args from itbl_fields.
381 o->args = strdup (form_args (e));
382 o->mask = apply_range (e->value, e->range);
383 /* FIXME how to catch durring assembly? */
384 /* mask to identify this insn */
385 o->match = apply_range (e->value, e->range);
389 o->mask = id++; /* FIXME how to catch durring assembly? */
390 o->match = 0; /* for macros, the insn_isa number */
391 o->pinfo = INSN_MACRO;
394 /* Don't add instructions which caused an error */
401 ITBL_OPCODES = new_opcodes;
402 ITBL_NUM_OPCODES = new_num_opcodes;
405 At this point, we can free the entries, as they should have
406 been added to the assembler's tables.
407 Don't free name though, since name is being used by the new
410 Eventually, we should also free the new opcodes table itself
416 form_args (struct itbl_entry *e)
420 struct itbl_field *f;
423 for (f = e->fields; f; f = f->next)
443 c = 0; /* ignore; unknown field type */
455 #endif /* !STAND_ALONE */
458 /* Get processor's register name from val */
461 itbl_get_reg_val (char *name, unsigned long *pval)
466 for (p = e_p0; p < e_nprocs; p++)
468 for (t = e_regtype0; t < e_nregtypes; t++)
470 if (itbl_get_val (p, t, name, pval))
478 itbl_get_name (e_processor processor, e_type type, unsigned long val)
480 struct itbl_entry *r;
481 /* type depends on instruction passed */
482 r = find_entry_byval (processor, type, val, 0);
486 return 0; /* error; invalid operand */
489 /* Get processor's register value from name */
492 itbl_get_val (e_processor processor, e_type type, char *name,
495 struct itbl_entry *r;
496 /* type depends on instruction passed */
497 r = find_entry_byname (processor, type, name);
505 /* Assemble instruction "name" with operands "s".
506 * name - name of instruction
508 * returns - long word for assembled instruction */
511 itbl_assemble (char *name, char *s)
513 unsigned long opcode;
514 struct itbl_entry *e;
515 struct itbl_field *f;
520 return 0; /* error! must have a opcode name/expr */
522 /* find entry in list of instructions for all processors */
523 for (processor = 0; processor < e_nprocs; processor++)
525 e = find_entry_byname (processor, e_insn, name);
530 return 0; /* opcode not in table; invalid instrustion */
531 opcode = build_opcode (e);
533 /* parse opcode's args (if any) */
534 for (f = e->fields; f; f = f->next) /* for each arg, ... */
536 struct itbl_entry *r;
539 return 0; /* error - not enough operands */
540 n = itbl_get_field (&s);
541 /* n should be in form $n or 0xhhh (are symbol names valid?? */
547 /* Accept either a string name
548 * or '$' followed by the register number */
552 value = strtol (n, 0, 10);
553 /* FIXME! could have "0l"... then what?? */
554 if (value == 0 && *n != '0')
555 return 0; /* error; invalid operand */
559 r = find_entry_byname (e->processor, f->type, n);
563 return 0; /* error; invalid operand */
567 /* use assembler's symbol table to find symbol */
568 /* FIXME!! Do we need this?
569 if so, what about relocs??
570 my_getExpression (&imm_expr, s);
571 return 0; /-* error; invalid operand *-/
574 /* If not a symbol, fall thru to IMMED */
576 if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */
579 value = strtol (n, 0, 16);
580 /* FIXME! could have "0xl"... then what?? */
584 value = strtol (n, 0, 10);
585 /* FIXME! could have "0l"... then what?? */
586 if (value == 0 && *n != '0')
587 return 0; /* error; invalid operand */
591 return 0; /* error; invalid field spec */
593 opcode |= apply_range (value, f->range);
596 return 0; /* error - too many operands */
597 return opcode; /* done! */
600 /* Disassemble instruction "insn".
602 * s - buffer to hold disassembled instruction
603 * returns - 1 if succeeded; 0 if failed
607 itbl_disassemble (char *s, unsigned long insn)
609 e_processor processor;
610 struct itbl_entry *e;
611 struct itbl_field *f;
613 if (!ITBL_IS_INSN (insn))
615 processor = get_processor (ITBL_DECODE_PNUM (insn));
617 /* find entry in list */
618 e = find_entry_byval (processor, e_insn, insn, 0);
620 return 0; /* opcode not in table; invalid instrustion */
623 /* parse insn's args (if any) */
624 for (f = e->fields; f; f = f->next) /* for each arg, ... */
626 struct itbl_entry *r;
629 if (f == e->fields) /* first operand is preceeded by tab */
631 else /* ','s separate following operands */
633 value = extract_range (insn, f->range);
634 /* n should be in form $n or 0xhhh (are symbol names valid?? */
640 /* Accept either a string name
641 * or '$' followed by the register number */
642 r = find_entry_byval (e->processor, f->type, value, &f->range);
646 sprintf (s, "%s$%d", s, value);
649 /* use assembler's symbol table to find symbol */
650 /* FIXME!! Do we need this?
651 * if so, what about relocs??
653 /* If not a symbol, fall thru to IMMED */
655 sprintf (s, "%s0x%x", s, value);
658 return 0; /* error; invalid field spec */
661 return 1; /* done! */
664 /*======================================================================*/
666 * Local functions for manipulating private structures containing
667 * the names and format for the new instructions and registers
668 * for each processor.
671 /* Calculate instruction's opcode and function values from entry */
674 build_opcode (struct itbl_entry *e)
676 unsigned long opcode;
678 opcode = apply_range (e->value, e->range);
679 opcode |= ITBL_ENCODE_PNUM (e->processor);
683 /* Calculate absolute value given the relative value and bit position range
684 * within the instruction.
685 * The range is inclusive where 0 is least significant bit.
686 * A range of { 24, 20 } will have a mask of
688 * pos: 1098 7654 3210 9876 5432 1098 7654 3210
689 * bin: 0000 0001 1111 0000 0000 0000 0000 0000
690 * hex: 0 1 f 0 0 0 0 0
695 apply_range (unsigned long rval, struct itbl_range r)
699 int len = MAX_BITPOS - r.sbit;
701 ASSERT (r.sbit >= r.ebit);
702 ASSERT (MAX_BITPOS >= r.sbit);
703 ASSERT (r.ebit >= 0);
705 /* create mask by truncating 1s by shifting */
706 mask = 0xffffffff << len;
708 mask = mask >> r.ebit;
709 mask = mask << r.ebit;
711 aval = (rval << r.ebit) & mask;
715 /* Calculate relative value given the absolute value and bit position range
716 * within the instruction. */
719 extract_range (unsigned long aval, struct itbl_range r)
723 int len = MAX_BITPOS - r.sbit;
725 /* create mask by truncating 1s by shifting */
726 mask = 0xffffffff << len;
728 mask = mask >> r.ebit;
729 mask = mask << r.ebit;
731 rval = (aval & mask) >> r.ebit;
735 /* Extract processor's assembly instruction field name from s;
736 * forms are "n args" "n,args" or "n" */
737 /* Return next argument from string pointer "s" and advance s.
738 * delimiters are " ,()" */
741 itbl_get_field (char **S)
750 /* FIXME: This is a weird set of delimiters. */
751 len = strcspn (s, " \t,()");
752 ASSERT (128 > len + 1);
756 s = 0; /* no more args */
758 s += len + 1; /* advance to next arg */
764 /* Search entries for a given processor and type
765 * to find one matching the name "n".
766 * Return a pointer to the entry */
768 static struct itbl_entry *
769 find_entry_byname (e_processor processor,
770 e_type type, char *n)
772 struct itbl_entry *e, **es;
774 es = get_entries (processor, type);
775 for (e = *es; e; e = e->next) /* for each entry, ... */
777 if (!strcmp (e->name, n))
783 /* Search entries for a given processor and type
784 * to find one matching the value "val" for the range "r".
785 * Return a pointer to the entry.
786 * This function is used for disassembling fields of an instruction.
789 static struct itbl_entry *
790 find_entry_byval (e_processor processor, e_type type,
791 unsigned long val, struct itbl_range *r)
793 struct itbl_entry *e, **es;
796 es = get_entries (processor, type);
797 for (e = *es; e; e = e->next) /* for each entry, ... */
799 if (processor != e->processor)
801 /* For insns, we might not know the range of the opcode,
802 * so a range of 0 will allow this routine to match against
803 * the range of the entry to be compared with.
804 * This could cause ambiguities.
805 * For operands, we get an extracted value and a range.
807 /* if range is 0, mask val against the range of the compared entry. */
808 if (r == 0) /* if no range passed, must be whole 32-bits
809 * so create 32-bit value from entry's range */
811 eval = apply_range (e->value, e->range);
812 val &= apply_range (0xffffffff, e->range);
814 else if (r->sbit == e->range.sbit && r->ebit == e->range.ebit
815 || e->range.sbit == 0 && e->range.ebit == 0)
817 eval = apply_range (e->value, *r);
818 val = apply_range (val, *r);
828 /* Return a pointer to the list of entries for a given processor and type. */
830 static struct itbl_entry **
831 get_entries (e_processor processor, e_type type)
833 return &entries[processor][type];
836 /* Return an integral value for the processor passed from yyparse. */
839 get_processor (int yyproc)
841 /* translate from yacc's processor to enum */
842 if (yyproc >= e_p0 && yyproc < e_nprocs)
843 return (e_processor) yyproc;
844 return e_invproc; /* error; invalid processor */
847 /* Return an integral value for the entry type passed from yyparse. */
850 get_type (int yytype)
854 /* translate from yacc's type to enum */
868 return e_invtype; /* error; invalid type */
873 /* Allocate and initialize an entry */
875 static struct itbl_entry *
876 alloc_entry (e_processor processor, e_type type,
877 char *name, unsigned long value)
879 struct itbl_entry *e, **es;
882 e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry));
885 memset (e, 0, sizeof (struct itbl_entry));
886 e->name = (char *) malloc (sizeof (strlen (name)) + 1);
888 strcpy (e->name, name);
889 e->processor = processor;
892 es = get_entries (e->processor, e->type);
899 /* Allocate and initialize an entry's field */
901 static struct itbl_field *
902 alloc_field (e_type type, int sbit, int ebit,
905 struct itbl_field *f;
906 f = (struct itbl_field *) malloc (sizeof (struct itbl_field));
909 memset (f, 0, sizeof (struct itbl_field));
911 f->range.sbit = sbit;
912 f->range.ebit = ebit;