2 Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 /*======================================================================*/
23 * Herein lies the support for dynamic specification of processor
24 * instructions and registers. Mnemonics, values, and formats for each
25 * instruction and register are specified in an ascii file consisting of
26 * table entries. The grammar for the table is defined in the document
27 * "Processor instruction table specification".
29 * Instructions use the gnu assembler syntax, with the addition of
30 * allowing mnemonics for register.
31 * Eg. "func $2,reg3,0x100,symbol ; comment"
34 * reg3 - mnemonic for processor's register defined in table
35 * 0xddd..d - immediate value
36 * symbol - address of label or external symbol
38 * First, itbl_parse reads in the table of register and instruction
39 * names and formats, and builds a list of entries for each
40 * processor/type combination. lex and yacc are used to parse
41 * the entries in the table and call functions defined here to
42 * add each entry to our list.
44 * Then, when assembling or disassembling, these functions are called to
45 * 1) get information on a processor's registers and
46 * 2) assemble/disassemble an instruction.
47 * To assemble(disassemble) an instruction, the function
48 * itbl_assemble(itbl_disassemble) is called to search the list of
49 * instruction entries, and if a match is found, uses the format
50 * described in the instruction entry structure to complete the action.
52 * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2"
53 * and we want to define function "pig" which takes two operands.
55 * Given the table entries:
56 * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0"
58 * and that the instruction encoding for coprocessor pz has encoding:
59 * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25)
60 * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum)
62 * a structure to describe the instruction might look something like:
63 * struct itbl_entry = {
64 * e_processor processor = e_p3
65 * e_type type = e_insn
69 * struct itbl_range range = 24-21
70 * struct itbl_field *field = {
71 * e_type type = e_dreg
72 * struct itbl_range range = 20-16
73 * struct itbl_field *next = {
74 * e_type type = e_immed
75 * struct itbl_range range = 15-0
76 * struct itbl_field *next = 0
79 * struct itbl_entry *next = 0
82 * And the assembler instructions:
86 * would both assemble to the hex value:
95 #include "itbl-parse.h"
101 #define ASSERT(x) assert(x)
102 #define DBG(x) printf x
109 #define min(a,b) (a<b?a:b)
112 int itbl_have_entries = 0;
114 /*======================================================================*/
115 /* structures for keeping itbl format entries */
119 int sbit; /* mask starting bit position */
120 int ebit; /* mask ending bit position */
125 e_type type; /* dreg/creg/greg/immed/symb */
126 struct itbl_range range; /* field's bitfield range within instruction */
127 unsigned long flags; /* field flags */
128 struct itbl_field *next; /* next field in list */
131 /* These structures define the instructions and registers for a processor.
132 * If the type is an instruction, the structure defines the format of an
133 * instruction where the fields are the list of operands.
134 * The flags field below uses the same values as those defined in the
135 * gnu assembler and are machine specific. */
138 e_processor processor; /* processor number */
139 e_type type; /* dreg/creg/greg/insn */
140 char *name; /* mnemionic name for insn/register */
141 unsigned long value; /* opcode/instruction mask/register number */
142 unsigned long flags; /* effects of the instruction */
143 struct itbl_range range; /* bit range within instruction for value */
144 struct itbl_field *fields; /* list of operand definitions (if any) */
145 struct itbl_entry *next; /* next entry */
148 /* local data and structures */
150 static int itbl_num_opcodes = 0;
151 /* Array of entries for each processor and entry type */
152 static struct itbl_entry *entries[e_nprocs][e_ntypes] =
160 /* local prototypes */
161 static unsigned long build_opcode PARAMS ((struct itbl_entry *e));
162 static e_type get_type PARAMS ((int yytype));
163 static e_processor get_processor PARAMS ((int yyproc));
164 static struct itbl_entry **get_entries PARAMS ((e_processor processor,
166 static struct itbl_entry *find_entry_byname PARAMS ((e_processor processor,
167 e_type type, char *name));
168 static struct itbl_entry *find_entry_byval PARAMS ((e_processor processor,
169 e_type type, unsigned long val, struct itbl_range *r));
170 static struct itbl_entry *alloc_entry PARAMS ((e_processor processor,
171 e_type type, char *name, unsigned long value));
172 static unsigned long apply_range PARAMS ((unsigned long value,
173 struct itbl_range r));
174 static unsigned long extract_range PARAMS ((unsigned long value,
175 struct itbl_range r));
176 static struct itbl_field *alloc_field PARAMS ((e_type type, int sbit,
177 int ebit, unsigned long flags));
179 /*======================================================================*/
180 /* Interfaces to the parser */
182 /* Open the table and use lex and yacc to parse the entries.
183 * Return 1 for failure; 0 for success. */
186 itbl_parse (char *insntbl)
189 extern int yyparse (void);
190 yyin = fopen (insntbl, "r");
193 printf ("Can't open processor instruction specification file \"%s\"\n",
202 itbl_have_entries = 1;
206 /* Add a register entry */
209 itbl_add_reg (int yyprocessor, int yytype, char *regname,
215 /* Since register names don't have a prefix, we put them in the symbol table so
216 they can't be used as symbols. This also simplifies argument parsing as
217 we can let gas parse registers for us. The recorded register number is
219 /* Use symbol_create here instead of symbol_new so we don't try to
220 output registers into the object file's symbol table. */
221 symbol_table_insert (symbol_create (regname, reg_section,
222 regnum, &zero_address_frag));
224 return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname,
225 (unsigned long) regnum);
228 /* Add an instruction entry */
231 itbl_add_insn (int yyprocessor, char *name, unsigned long value,
232 int sbit, int ebit, unsigned long flags)
234 struct itbl_entry *e;
235 e = alloc_entry (get_processor (yyprocessor), e_insn, name, value);
238 e->range.sbit = sbit;
239 e->range.ebit = ebit;
246 /* Add an operand to an instruction entry */
249 itbl_add_operand (struct itbl_entry *e, int yytype, int sbit,
250 int ebit, unsigned long flags)
252 struct itbl_field *f, **last_f;
255 /* Add to end of fields' list. */
256 f = alloc_field (get_type (yytype), sbit, ebit, flags);
261 last_f = &(*last_f)->next;
268 /*======================================================================*/
269 /* Interfaces for assembler and disassembler */
274 static void append_insns_as_macros (void);
276 /* initialize for gas */
280 struct itbl_entry *e, **es;
284 if (!itbl_have_entries)
287 /* Since register names don't have a prefix, put them in the symbol table so
288 they can't be used as symbols. This simplifies argument parsing as
289 we can let gas parse registers for us. */
290 /* Use symbol_create instead of symbol_new so we don't try to
291 output registers into the object file's symbol table. */
293 for (type = e_regtype0; type < e_nregtypes; type++)
294 for (procn = e_p0; procn < e_nprocs; procn++)
296 es = get_entries (procn, type);
297 for (e = *es; e; e = e->next)
299 symbol_table_insert (symbol_create (e->name, reg_section,
300 e->value, &zero_address_frag));
303 append_insns_as_macros ();
306 /* Append insns to opcodes table and increase number of opcodes
307 * Structure of opcodes table:
311 * const char *args; - string describing the arguments.
312 * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO
313 * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO
314 * unsigned long pinfo; - insn flags, or INSN_MACRO
317 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
318 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
321 static char *form_args (struct itbl_entry *e);
323 append_insns_as_macros (void)
325 struct ITBL_OPCODE_STRUCT *new_opcodes, *o;
326 struct itbl_entry *e, **es;
327 int n, id, size, new_size, new_num_opcodes;
329 if (!itbl_have_entries)
332 if (!itbl_num_opcodes) /* no new instructions to add! */
336 DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES));
338 new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes;
339 ASSERT (new_num_opcodes >= itbl_num_opcodes);
341 size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES;
343 DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0])));
345 new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes;
346 ASSERT (new_size > size);
348 /* FIXME since ITBL_OPCODES culd be a static table,
349 we can't realloc or delete the old memory. */
350 new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size);
353 printf (_("Unable to allocate memory for new instructions\n"));
356 if (size) /* copy prexisting opcodes table */
357 memcpy (new_opcodes, ITBL_OPCODES, size);
359 /* FIXME! some NUMOPCODES are calculated expressions.
360 These need to be changed before itbls can be supported. */
362 id = ITBL_NUM_MACROS; /* begin the next macro id after the last */
363 o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */
364 for (n = e_p0; n < e_nprocs; n++)
366 es = get_entries (n, e_insn);
367 for (e = *es; e; e = e->next)
369 /* name, args, mask, match, pinfo
370 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
371 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
372 * Construct args from itbl_fields.
375 o->args = strdup (form_args (e));
376 o->mask = apply_range (e->value, e->range);
377 /* FIXME how to catch durring assembly? */
378 /* mask to identify this insn */
379 o->match = apply_range (e->value, e->range);
383 o->mask = id++; /* FIXME how to catch durring assembly? */
384 o->match = 0; /* for macros, the insn_isa number */
385 o->pinfo = INSN_MACRO;
388 /* Don't add instructions which caused an error */
395 ITBL_OPCODES = new_opcodes;
396 ITBL_NUM_OPCODES = new_num_opcodes;
399 At this point, we can free the entries, as they should have
400 been added to the assembler's tables.
401 Don't free name though, since name is being used by the new
404 Eventually, we should also free the new opcodes table itself
410 form_args (struct itbl_entry *e)
414 struct itbl_field *f;
417 for (f = e->fields; f; f = f->next)
437 c = 0; /* ignore; unknown field type */
449 #endif /* !STAND_ALONE */
451 /* Get processor's register name from val */
454 itbl_get_reg_val (char *name, unsigned long *pval)
459 for (p = e_p0; p < e_nprocs; p++)
461 for (t = e_regtype0; t < e_nregtypes; t++)
463 if (itbl_get_val (p, t, name, pval))
471 itbl_get_name (e_processor processor, e_type type, unsigned long val)
473 struct itbl_entry *r;
474 /* type depends on instruction passed */
475 r = find_entry_byval (processor, type, val, 0);
479 return 0; /* error; invalid operand */
482 /* Get processor's register value from name */
485 itbl_get_val (e_processor processor, e_type type, char *name,
488 struct itbl_entry *r;
489 /* type depends on instruction passed */
490 r = find_entry_byname (processor, type, name);
497 /* Assemble instruction "name" with operands "s".
498 * name - name of instruction
500 * returns - long word for assembled instruction */
503 itbl_assemble (char *name, char *s)
505 unsigned long opcode;
506 struct itbl_entry *e;
507 struct itbl_field *f;
512 return 0; /* error! must have a opcode name/expr */
514 /* find entry in list of instructions for all processors */
515 for (processor = 0; processor < e_nprocs; processor++)
517 e = find_entry_byname (processor, e_insn, name);
522 return 0; /* opcode not in table; invalid instrustion */
523 opcode = build_opcode (e);
525 /* parse opcode's args (if any) */
526 for (f = e->fields; f; f = f->next) /* for each arg, ... */
528 struct itbl_entry *r;
531 return 0; /* error - not enough operands */
532 n = itbl_get_field (&s);
533 /* n should be in form $n or 0xhhh (are symbol names valid?? */
539 /* Accept either a string name
540 * or '$' followed by the register number */
544 value = strtol (n, 0, 10);
545 /* FIXME! could have "0l"... then what?? */
546 if (value == 0 && *n != '0')
547 return 0; /* error; invalid operand */
551 r = find_entry_byname (e->processor, f->type, n);
555 return 0; /* error; invalid operand */
559 /* use assembler's symbol table to find symbol */
560 /* FIXME!! Do we need this?
561 if so, what about relocs??
562 my_getExpression (&imm_expr, s);
563 return 0; /-* error; invalid operand *-/
566 /* If not a symbol, fall thru to IMMED */
568 if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */
571 value = strtol (n, 0, 16);
572 /* FIXME! could have "0xl"... then what?? */
576 value = strtol (n, 0, 10);
577 /* FIXME! could have "0l"... then what?? */
578 if (value == 0 && *n != '0')
579 return 0; /* error; invalid operand */
583 return 0; /* error; invalid field spec */
585 opcode |= apply_range (value, f->range);
588 return 0; /* error - too many operands */
589 return opcode; /* done! */
592 /* Disassemble instruction "insn".
594 * s - buffer to hold disassembled instruction
595 * returns - 1 if succeeded; 0 if failed
599 itbl_disassemble (char *s, unsigned long insn)
601 e_processor processor;
602 struct itbl_entry *e;
603 struct itbl_field *f;
605 if (!ITBL_IS_INSN (insn))
607 processor = get_processor (ITBL_DECODE_PNUM (insn));
609 /* find entry in list */
610 e = find_entry_byval (processor, e_insn, insn, 0);
612 return 0; /* opcode not in table; invalid instrustion */
615 /* parse insn's args (if any) */
616 for (f = e->fields; f; f = f->next) /* for each arg, ... */
618 struct itbl_entry *r;
621 if (f == e->fields) /* first operand is preceeded by tab */
623 else /* ','s separate following operands */
625 value = extract_range (insn, f->range);
626 /* n should be in form $n or 0xhhh (are symbol names valid?? */
632 /* Accept either a string name
633 * or '$' followed by the register number */
634 r = find_entry_byval (e->processor, f->type, value, &f->range);
638 sprintf (s, "%s$%lu", s, value);
641 /* use assembler's symbol table to find symbol */
642 /* FIXME!! Do we need this?
643 * if so, what about relocs??
645 /* If not a symbol, fall thru to IMMED */
647 sprintf (s, "%s0x%lx", s, value);
650 return 0; /* error; invalid field spec */
653 return 1; /* done! */
656 /*======================================================================*/
658 * Local functions for manipulating private structures containing
659 * the names and format for the new instructions and registers
660 * for each processor.
663 /* Calculate instruction's opcode and function values from entry */
666 build_opcode (struct itbl_entry *e)
668 unsigned long opcode;
670 opcode = apply_range (e->value, e->range);
671 opcode |= ITBL_ENCODE_PNUM (e->processor);
675 /* Calculate absolute value given the relative value and bit position range
676 * within the instruction.
677 * The range is inclusive where 0 is least significant bit.
678 * A range of { 24, 20 } will have a mask of
680 * pos: 1098 7654 3210 9876 5432 1098 7654 3210
681 * bin: 0000 0001 1111 0000 0000 0000 0000 0000
682 * hex: 0 1 f 0 0 0 0 0
687 apply_range (unsigned long rval, struct itbl_range r)
691 int len = MAX_BITPOS - r.sbit;
693 ASSERT (r.sbit >= r.ebit);
694 ASSERT (MAX_BITPOS >= r.sbit);
695 ASSERT (r.ebit >= 0);
697 /* create mask by truncating 1s by shifting */
698 mask = 0xffffffff << len;
700 mask = mask >> r.ebit;
701 mask = mask << r.ebit;
703 aval = (rval << r.ebit) & mask;
707 /* Calculate relative value given the absolute value and bit position range
708 * within the instruction. */
711 extract_range (unsigned long aval, struct itbl_range r)
715 int len = MAX_BITPOS - r.sbit;
717 /* create mask by truncating 1s by shifting */
718 mask = 0xffffffff << len;
720 mask = mask >> r.ebit;
721 mask = mask << r.ebit;
723 rval = (aval & mask) >> r.ebit;
727 /* Extract processor's assembly instruction field name from s;
728 * forms are "n args" "n,args" or "n" */
729 /* Return next argument from string pointer "s" and advance s.
730 * delimiters are " ,()" */
733 itbl_get_field (char **S)
742 /* FIXME: This is a weird set of delimiters. */
743 len = strcspn (s, " \t,()");
744 ASSERT (128 > len + 1);
748 s = 0; /* no more args */
750 s += len + 1; /* advance to next arg */
756 /* Search entries for a given processor and type
757 * to find one matching the name "n".
758 * Return a pointer to the entry */
760 static struct itbl_entry *
761 find_entry_byname (e_processor processor,
762 e_type type, char *n)
764 struct itbl_entry *e, **es;
766 es = get_entries (processor, type);
767 for (e = *es; e; e = e->next) /* for each entry, ... */
769 if (!strcmp (e->name, n))
775 /* Search entries for a given processor and type
776 * to find one matching the value "val" for the range "r".
777 * Return a pointer to the entry.
778 * This function is used for disassembling fields of an instruction.
781 static struct itbl_entry *
782 find_entry_byval (e_processor processor, e_type type,
783 unsigned long val, struct itbl_range *r)
785 struct itbl_entry *e, **es;
788 es = get_entries (processor, type);
789 for (e = *es; e; e = e->next) /* for each entry, ... */
791 if (processor != e->processor)
793 /* For insns, we might not know the range of the opcode,
794 * so a range of 0 will allow this routine to match against
795 * the range of the entry to be compared with.
796 * This could cause ambiguities.
797 * For operands, we get an extracted value and a range.
799 /* if range is 0, mask val against the range of the compared entry. */
800 if (r == 0) /* if no range passed, must be whole 32-bits
801 * so create 32-bit value from entry's range */
803 eval = apply_range (e->value, e->range);
804 val &= apply_range (0xffffffff, e->range);
806 else if ((r->sbit == e->range.sbit && r->ebit == e->range.ebit)
807 || (e->range.sbit == 0 && e->range.ebit == 0))
809 eval = apply_range (e->value, *r);
810 val = apply_range (val, *r);
820 /* Return a pointer to the list of entries for a given processor and type. */
822 static struct itbl_entry **
823 get_entries (e_processor processor, e_type type)
825 return &entries[processor][type];
828 /* Return an integral value for the processor passed from yyparse. */
831 get_processor (int yyproc)
833 /* translate from yacc's processor to enum */
834 if (yyproc >= e_p0 && yyproc < e_nprocs)
835 return (e_processor) yyproc;
836 return e_invproc; /* error; invalid processor */
839 /* Return an integral value for the entry type passed from yyparse. */
842 get_type (int yytype)
846 /* translate from yacc's type to enum */
860 return e_invtype; /* error; invalid type */
864 /* Allocate and initialize an entry */
866 static struct itbl_entry *
867 alloc_entry (e_processor processor, e_type type,
868 char *name, unsigned long value)
870 struct itbl_entry *e, **es;
873 e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry));
876 memset (e, 0, sizeof (struct itbl_entry));
877 e->name = (char *) malloc (sizeof (strlen (name)) + 1);
879 strcpy (e->name, name);
880 e->processor = processor;
883 es = get_entries (e->processor, e->type);
890 /* Allocate and initialize an entry's field */
892 static struct itbl_field *
893 alloc_field (e_type type, int sbit, int ebit,
896 struct itbl_field *f;
897 f = (struct itbl_field *) malloc (sizeof (struct itbl_field));
900 memset (f, 0, sizeof (struct itbl_field));
902 f->range.sbit = sbit;
903 f->range.ebit = ebit;