2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node TILE-Gx-Dependent
10 @chapter TILE-Gx Dependent Features
13 @node Machine Dependencies
14 @chapter TILE-Gx Dependent Features
17 @cindex TILE-Gx support
19 * TILE-Gx Options:: TILE-Gx Options
20 * TILE-Gx Syntax:: TILE-Gx Syntax
21 * TILE-Gx Directives:: TILE-Gx Directives
27 The following table lists all available TILE-Gx specific options:
31 @cindex @samp{-m32} option, TILE-Gx
32 @cindex @samp{-m64} option, TILE-Gx
34 Select the word size, either 32 bits or 64 bits.
36 @cindex @samp{-EB} option, TILE-Gx
37 @cindex @samp{-EL} option, TILE-Gx
39 Select the endianness, either big-endian (-EB) or little-endian (-EL).
46 @cindex TILE-Gx syntax
47 @cindex syntax, TILE-Gx
49 Block comments are delimited by @samp{/*} and @samp{*/}. End of line
50 comments may be introduced by @samp{#}.
52 Instructions consist of a leading opcode or macro name followed by
53 whitespace and an optional comma-separated list of operands:
56 @var{opcode} [@var{operand}, @dots{}]
59 Instructions must be separated by a newline or semicolon.
61 There are two ways to write code: either write naked instructions,
62 which the assembler is free to combine into VLIW bundles, or specify
63 the VLIW bundles explicitly.
65 Bundles are specified using curly braces:
68 @{ @var{add} r3,r4,r5 ; @var{add} r7,r8,r9 ; @var{lw} r10,r11 @}
71 A bundle can span multiple lines. If you want to put multiple
72 instructions on a line, whether in a bundle or not, you need to
73 separate them with semicolons as in this example.
75 A bundle may contain one or more instructions, up to the limit
76 specified by the ISA (currently three). If fewer instructions are
77 specified than the hardware supports in a bundle, the assembler
78 inserts @code{fnop} instructions automatically.
80 The assembler will prefer to preserve the ordering of instructions
81 within the bundle, putting the first instruction in a lower-numbered
82 pipeline than the next one, etc. This fact, combined with the
83 optional use of explicit @code{fnop} or @code{nop} instructions,
84 allows precise control over which pipeline executes each instruction.
86 If the instructions cannot be bundled in the listed order, the
87 assembler will automatically try to find a valid pipeline
88 assignment. If there is no way to bundle the instructions together,
89 the assembler reports an error.
91 The assembler does not yet auto-bundle (automatically combine multiple
92 instructions into one bundle), but it reserves the right to do so in
93 the future. If you want to force an instruction to run by itself, put
94 it in a bundle explicitly with curly braces and use @code{nop}
95 instructions (not @code{fnop}) to fill the remaining pipeline slots in
99 * TILE-Gx Opcodes:: Opcode Naming Conventions.
100 * TILE-Gx Registers:: Register Naming.
101 * TILE-Gx Modifiers:: Symbolic Operand Modifiers.
104 @node TILE-Gx Opcodes
105 @subsection Opcode Names
106 @cindex TILE-Gx opcode names
107 @cindex opcode names, TILE-Gx
109 For a complete list of opcodes and descriptions of their semantics,
110 see @cite{TILE-Gx Instruction Set Architecture}, available upon
111 request at www.tilera.com.
113 @node TILE-Gx Registers
114 @subsection Register Names
115 @cindex TILE-Gx register names
116 @cindex register names, TILE-Gx
118 General-purpose registers are represented by predefined symbols of the
119 form @samp{r@var{N}}, where @var{N} represents a number between
120 @code{0} and @code{63}. However, the following registers have
121 canonical names that must be used instead:
156 The assembler will emit a warning if a numeric name is used instead of
157 the non-numeric name. The @code{.no_require_canonical_reg_names}
158 assembler pseudo-op turns off this
159 warning. @code{.require_canonical_reg_names} turns it back on.
161 @node TILE-Gx Modifiers
162 @subsection Symbolic Operand Modifiers
163 @cindex TILE-Gx modifiers
164 @cindex symbol modifiers, TILE-Gx
166 The assembler supports several modifiers when using symbol addresses
167 in TILE-Gx instruction operands. The general syntax is the following:
173 The following modifiers are supported:
179 This modifier is used to load bits 0-15 of the symbol's address.
183 This modifier is used to load bits 16-31 of the symbol's address.
187 This modifier is used to load bits 32-47 of the symbol's address.
191 This modifier is used to load bits 48-63 of the symbol's address.
195 This modifier yields the same value as @code{hw0}, but it also checks
196 that the value does not overflow.
200 This modifier yields the same value as @code{hw1}, but it also checks
201 that the value does not overflow.
205 This modifier yields the same value as @code{hw2}, but it also checks
206 that the value does not overflow.
208 A 48-bit symbolic value is constructed by using the following idiom:
211 moveli r0, hw2_last(sym)
212 shl16insli r0, r0, hw1(sym)
213 shl16insli r0, r0, hw0(sym)
218 This modifier is used to load bits 0-15 of the symbol's offset in the
219 GOT entry corresponding to the symbol.
223 This modifier yields the same value as @code{hw0_got}, but it also
224 checks that the value does not overflow.
228 This modifier is used to load bits 16-31 of the symbol's offset in the
229 GOT entry corresponding to the symbol, and it also checks that the
230 value does not overflow.
234 This modifier is used for function symbols. It causes a
235 @emph{procedure linkage table}, an array of code stubs, to be created
236 at the time the shared object is created or linked against, together
237 with a global offset table entry. The value is a pc-relative offset
238 to the corresponding stub code in the procedure linkage table. This
239 arrangement causes the run-time symbol resolver to be called to look
240 up and set the value of the symbol the first time the function is
241 called (at latest; depending environment variables). It is only safe
242 to leave the symbol unresolved this way if all references are function
247 This modifier is used to load bits 0-15 of the pc-relative address of
252 This modifier is used to load bits 16-31 of the pc-relative address of
257 This modifier yields the same value as @code{hw1_plt}, but it also
258 checks that the value does not overflow.
262 This modifier is used to load bits 32-47 of the pc-relative address of
263 a plt entry, and it also checks that the value does not overflow.
267 This modifier is used to load bits 0-15 of the offset of the GOT entry
268 of the symbol's TLS descriptor, to be used for general-dynamic TLS
271 @item hw0_last_tls_gd
273 This modifier yields the same value as @code{hw0_tls_gd}, but it also
274 checks that the value does not overflow.
276 @item hw1_last_tls_gd
278 This modifier is used to load bits 16-31 of the offset of the GOT
279 entry of the symbol's TLS descriptor, to be used for general-dynamic
280 TLS accesses. It also checks that the value does not overflow.
284 This modifier is used to load bits 0-15 of the offset of the GOT entry
285 containing the offset of the symbol's address from the TCB, to be used
286 for initial-exec TLS accesses.
288 @item hw0_last_tls_ie
290 This modifier yields the same value as @code{hw0_tls_ie}, but it also
291 checks that the value does not overflow.
293 @item hw1_last_tls_ie
295 This modifier is used to load bits 16-31 of the offset of the GOT
296 entry containing the offset of the symbol's address from the TCB, to
297 be used for initial-exec TLS accesses. It also checks that the value
302 This modifier is used to load bits 0-15 of the offset of the symbol's
303 address from the TCB, to be used for local-exec TLS accesses.
305 @item hw0_last_tls_le
307 This modifier yields the same value as @code{hw0_tls_le}, but it also
308 checks that the value does not overflow.
310 @item hw1_last_tls_le
312 This modifier is used to load bits 16-31 of the offset of the symbol's
313 address from the TCB, to be used for local-exec TLS accesses. It
314 also checks that the value does not overflow.
318 This modifier is used to tag an instrution as the ``call'' part of a
319 calling sequence for a TLS GD reference of its operand.
323 This modifier is used to tag an instruction as the ``add'' part of a
324 calling sequence for a TLS GD reference of its operand.
328 This modifier is used to tag an instruction as the ``load'' part of a
329 calling sequence for a TLS IE reference of its operand.
333 @node TILE-Gx Directives
334 @section TILE-Gx Directives
335 @cindex machine directives, TILE-Gx
336 @cindex TILE-Gx machine directives
340 @cindex @code{.align} directive, TILE-Gx
341 @item .align @var{expression} [, @var{expression}]
342 This is the generic @var{.align} directive. The first argument is the
343 requested alignment in bytes.
345 @cindex @code{.allow_suspicious_bundles} directive, TILE-Gx
346 @item .allow_suspicious_bundles
347 Turns on error checking for combinations of instructions in a bundle
348 that probably indicate a programming error. This is on by default.
350 @item .no_allow_suspicious_bundles
351 Turns off error checking for combinations of instructions in a bundle
352 that probably indicate a programming error.
354 @cindex @code{.require_canonical_reg_names} directive, TILE-Gx
355 @item .require_canonical_reg_names
356 Require that canonical register names be used, and emit a warning if
357 the numeric names are used. This is on by default.
359 @item .no_require_canonical_reg_names
360 Permit the use of numeric names for registers that have canonical