1 @c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
16 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
18 information about the @sc{mips} instruction set, see @cite{MIPS RISC
19 Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
20 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
21 Programming'' in the same work.
24 * MIPS Opts:: Assembler options
25 * MIPS Object:: ECOFF object code
26 * MIPS Stabs:: Directives for debugging information
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
29 * MIPS insn:: Directive to mark data as an instruction
30 * MIPS option stack:: Directives to save and restore options
34 @section Assembler options
36 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
40 @cindex @code{-G} option (MIPS)
42 This option sets the largest size of an object that can be referenced
43 implicitly with the @code{gp} register. It is only accepted for targets
44 that use @sc{ecoff} format. The default value is 8.
46 @cindex @code{-EB} option (MIPS)
47 @cindex @code{-EL} option (MIPS)
48 @cindex MIPS big-endian output
49 @cindex MIPS little-endian output
50 @cindex big-endian output, MIPS
51 @cindex little-endian output, MIPS
54 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
55 little-endian output at run time (unlike the other @sc{gnu} development
56 tools, which must be configured for one or the other). Use @samp{-EB}
57 to select big-endian output, and @samp{-EL} for little-endian.
59 @cindex MIPS architecture options
67 Generate code for a particular MIPS Instruction Set Architecture level.
68 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
69 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
70 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
71 @sc{r10000} processors.
72 @samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
73 to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
74 processors, respectively.
75 You can also switch instruction sets during the
76 assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
79 Assume that 32-bit general purpose registers are available. This
80 affects synthetic instructions such as @code{move}, which will assemble
81 to a 32-bit or a 64-bit instruction depending on this flag. On some
82 MIPS variants there is a 32-bit mode flag; when this flag is set,
83 64-bit instructions generate a trap. Also, some 32-bit OSes only save
84 the 32-bit registers on a context switch, so it is essential never to
85 use the 64-bit registers.
88 Assume that 64-bit general purpose registers are available. This is
89 provided in the interests of symmetry with -gp32.
93 Generate code for the MIPS 16 processor. This is equivalent to putting
94 @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
95 turns off this option.
99 Cause nops to be inserted if the read of the destination register
100 of an mfhi or mflo instruction occurs in the following two instructions.
104 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
105 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
106 etc.), and to not schedule @samp{nop} instructions around accesses to
107 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
112 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
113 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
114 instructions around accesses to the @samp{HI} and @samp{LO} registers.
115 @samp{-no-m4650} turns off this option.
121 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
122 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
123 specific to that chip, and to schedule for that chip's hazards.
125 @item -mcpu=@var{cpu}
126 Generate code for a particular MIPS cpu. It is exactly equivalent to
127 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
128 understood. Valid @var{cpu} value are:
157 @cindex @code{-nocpp} ignored (MIPS)
159 This option is ignored. It is accepted for command-line compatibility with
160 other assemblers, which use it to turn off C style preprocessing. With
161 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
162 @sc{gnu} assembler itself never runs the C preprocessor.
164 @item --construct-floats
165 @itemx --no-construct-floats
166 @cindex --construct-floats
167 @cindex --no-construct-floats
168 The @code{--no-construct-floats} option disables the construction of
169 double width floating point constants by loading the two halves of the
170 value into the two single width floating point registers that make up
171 the double width register. This feature is useful if the processor
172 support the FR bit in its status register, and this bit is known (by
173 the programmer) to be set. This bit prevents the aliasing of the double
174 width register by the single width registers.
176 By default @code{--construct-floats} is selected, allowing construction
177 of these floating point constants.
181 @c FIXME! (1) reflect these options (next item too) in option summaries;
182 @c (2) stop teasing, say _which_ instructions expanded _how_.
183 @code{@value{AS}} automatically macro expands certain division and
184 multiplication instructions to check for overflow and division by zero. This
185 option causes @code{@value{AS}} to generate code to take a trap exception
186 rather than a break exception when an error is detected. The trap instructions
187 are only supported at Instruction Set Architecture level 2 and higher.
191 Generate code to take a break exception rather than a trap exception when an
192 error is detected. This is the default.
196 @section MIPS ECOFF object code
198 @cindex ECOFF sections
199 @cindex MIPS ECOFF sections
200 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
201 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
202 additional sections are @code{.rdata}, used for read-only data,
203 @code{.sdata}, used for small data, and @code{.sbss}, used for small
206 @cindex small objects, MIPS ECOFF
207 @cindex @code{gp} register, MIPS
208 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
209 register to form the address of a ``small object''. Any object in the
210 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
211 For external objects, or for objects in the @code{.bss} section, you can use
212 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
213 @code{$gp}; the default value is 8, meaning that a reference to any object
214 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
215 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
216 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
217 or @code{sbss} in any case). The size of an object in the @code{.bss} section
218 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
219 size of an external object may be set with the @code{.extern} directive. For
220 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
221 in length, whie leaving @code{sym} otherwise undefined.
223 Using small @sc{ecoff} objects requires linker support, and assumes that the
224 @code{$gp} register is correctly initialized (normally done automatically by
225 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
229 @section Directives for debugging information
231 @cindex MIPS debugging directives
232 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
233 generating debugging information which are not support by traditional @sc{mips}
234 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
235 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
236 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
237 generated by the three @code{.stab} directives can only be read by @sc{gdb},
238 not by traditional @sc{mips} debuggers (this enhancement is required to fully
239 support C++ debugging). These directives are primarily used by compilers, not
240 assembly language programmers!
243 @section Directives to override the ISA level
245 @cindex MIPS ISA override
246 @kindex @code{.set mips@var{n}}
247 @sc{gnu} @code{@value{AS}} supports an additional directive to change
248 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
249 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
250 The values 1 to 5, 32, and 64 make the assembler accept instructions
251 for the corresponding
252 @sc{isa} level, from that point on in the assembly. @code{.set
253 mips@var{n}} affects not only which instructions are permitted, but also
254 how certain macros are expanded. @code{.set mips0} restores the
255 @sc{isa} level to its original level: either the level you selected with
256 command line options, or the default for your configuration. You can
257 use this feature to permit specific @sc{r4000} instructions while
258 assembling in 32 bit mode. Use this directive with care!
260 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
261 in which it will assemble instructions for the MIPS 16 processor. Use
262 @samp{.set nomips16} to return to normal 32 bit mode.
264 Traditional @sc{mips} assemblers do not support this directive.
266 @node MIPS autoextend
267 @section Directives for extending MIPS 16 bit instructions
269 @kindex @code{.set autoextend}
270 @kindex @code{.set noautoextend}
271 By default, MIPS 16 instructions are automatically extended to 32 bits
272 when necessary. The directive @samp{.set noautoextend} will turn this
273 off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
274 must be explicitly extended with the @samp{.e} modifier (e.g.,
275 @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
276 to once again automatically extend instructions when necessary.
278 This directive is only meaningful when in MIPS 16 mode. Traditional
279 @sc{mips} assemblers do not support this directive.
282 @section Directive to mark data as an instruction
285 The @code{.insn} directive tells @code{@value{AS}} that the following
286 data is actually instructions. This makes a difference in MIPS 16 mode:
287 when loading the address of a label which precedes instructions,
288 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
289 the loaded address will do the right thing.
291 @node MIPS option stack
292 @section Directives to save and restore options
294 @cindex MIPS option stack
295 @kindex @code{.set push}
296 @kindex @code{.set pop}
297 The directives @code{.set push} and @code{.set pop} may be used to save
298 and restore the current settings for all the options which are
299 controlled by @code{.set}. The @code{.set push} directive saves the
300 current settings on a stack. The @code{.set pop} directive pops the
301 stack and restores the settings.
303 These directives can be useful inside an macro which must change an
304 option such as the ISA level or instruction reordering but does not want
305 to change the state of the code which invoked the macro.
307 Traditional @sc{mips} assemblers do not support these directives.