1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
32 * MIPS Option Stack:: Directives to save and restore options
33 * MIPS ASE Instruction Generation Overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS Floating-Point:: Directives to override floating-point options
36 * MIPS Syntax:: MIPS specific syntactical considerations
40 @section Assembler options
42 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
46 @cindex @code{-G} option (MIPS)
48 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
49 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
51 @cindex @code{-EB} option (MIPS)
52 @cindex @code{-EL} option (MIPS)
53 @cindex MIPS big-endian output
54 @cindex MIPS little-endian output
55 @cindex big-endian output, MIPS
56 @cindex little-endian output, MIPS
59 Any MIPS configuration of @code{@value{AS}} can select big-endian or
60 little-endian output at run time (unlike the other @sc{gnu} development
61 tools, which must be configured for one or the other). Use @samp{-EB}
62 to select big-endian output, and @samp{-EL} for little-endian.
65 @cindex PIC selection, MIPS
66 @cindex @option{-KPIC} option, MIPS
67 Generate SVR4-style PIC. This option tells the assembler to generate
68 SVR4-style position-independent macro expansions. It also tells the
69 assembler to mark the output file as PIC.
72 @cindex @option{-mvxworks-pic} option, MIPS
73 Generate VxWorks PIC. This option tells the assembler to generate
74 VxWorks-style position-independent macro expansions.
76 @cindex MIPS architecture options
90 Generate code for a particular MIPS Instruction Set Architecture level.
91 @samp{-mips1} corresponds to the R2000 and R3000 processors,
92 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
93 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
94 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
95 @samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and
96 @samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
97 MIPS32 Release 3, MIPS32 Release 5, MIPS64, and MIPS64 Release 2,
98 MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively. You
99 can also switch instruction sets during the assembly; see @ref{MIPS ISA,
100 Directives to override the ISA level}.
104 Some macros have different expansions for 32-bit and 64-bit registers.
105 The register sizes are normally inferred from the ISA and ABI, but these
106 flags force a certain group of registers to be treated as 32 bits wide at
107 all times. @samp{-mgp32} controls the size of general-purpose registers
108 and @samp{-mfp32} controls the size of floating-point registers.
110 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
111 of registers to be changed for parts of an object. The default value is
112 restored by @code{.set gp=default} and @code{.set fp=default}.
114 On some MIPS variants there is a 32-bit mode flag; when this flag is
115 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
116 save the 32-bit registers on a context switch, so it is essential never
117 to use the 64-bit registers.
121 Assume that 64-bit registers are available. This is provided in the
122 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
124 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
125 of registers to be changed for parts of an object. The default value is
126 restored by @code{.set gp=default} and @code{.set fp=default}.
130 Generate code for the MIPS 16 processor. This is equivalent to putting
131 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
132 turns off this option.
135 @itemx -mno-micromips
136 Generate code for the microMIPS processor. This is equivalent to putting
137 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
138 turns off this option. This is equivalent to putting @code{.set nomicromips}
139 at the start of the assembly file.
142 @itemx -mno-smartmips
143 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
144 provides a number of new instructions which target smartcard and
145 cryptographic applications. This is equivalent to putting
146 @code{.set smartmips} at the start of the assembly file.
147 @samp{-mno-smartmips} turns off this option.
151 Generate code for the MIPS-3D Application Specific Extension.
152 This tells the assembler to accept MIPS-3D instructions.
153 @samp{-no-mips3d} turns off this option.
157 Generate code for the MDMX Application Specific Extension.
158 This tells the assembler to accept MDMX instructions.
159 @samp{-no-mdmx} turns off this option.
163 Generate code for the DSP Release 1 Application Specific Extension.
164 This tells the assembler to accept DSP Release 1 instructions.
165 @samp{-mno-dsp} turns off this option.
169 Generate code for the DSP Release 2 Application Specific Extension.
170 This option implies -mdsp.
171 This tells the assembler to accept DSP Release 2 instructions.
172 @samp{-mno-dspr2} turns off this option.
176 Generate code for the MT Application Specific Extension.
177 This tells the assembler to accept MT instructions.
178 @samp{-mno-mt} turns off this option.
182 Generate code for the MCU Application Specific Extension.
183 This tells the assembler to accept MCU instructions.
184 @samp{-mno-mcu} turns off this option.
188 Generate code for the MIPS SIMD Architecture Extension.
189 This tells the assembler to accept MSA instructions.
190 @samp{-mno-msa} turns off this option.
194 Generate code for the MIPS eXtended Physical Address (XPA) Extension.
195 This tells the assembler to accept XPA instructions.
196 @samp{-mno-xpa} turns off this option.
200 Generate code for the Virtualization Application Specific Extension.
201 This tells the assembler to accept Virtualization instructions.
202 @samp{-mno-virt} turns off this option.
206 Only use 32-bit instruction encodings when generating code for the
207 microMIPS processor. This option inhibits the use of any 16-bit
208 instructions. This is equivalent to putting @code{.set insn32} at
209 the start of the assembly file. @samp{-mno-insn32} turns off this
210 option. This is equivalent to putting @code{.set noinsn32} at the
211 start of the assembly file. By default @samp{-mno-insn32} is
212 selected, allowing all instructions to be used.
216 Cause nops to be inserted if the read of the destination register
217 of an mfhi or mflo instruction occurs in the following two instructions.
220 @itemx -mno-fix-rm7000
221 Cause nops to be inserted if a dmult or dmultu instruction is
222 followed by a load instruction.
224 @item -mfix-loongson2f-jump
225 @itemx -mno-fix-loongson2f-jump
226 Eliminate instruction fetch from outside 256M region to work around the
227 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
228 the kernel may crash. The issue has been solved in latest processor
229 batches, but this fix has no side effect to them.
231 @item -mfix-loongson2f-nop
232 @itemx -mno-fix-loongson2f-nop
233 Replace nops by @code{or at,at,zero} to work around the Loongson2F
234 @samp{nop} errata. Without it, under extreme cases, the CPU might
235 deadlock. The issue has been solved in later Loongson2F batches, but
236 this fix has no side effect to them.
239 @itemx -mno-fix-vr4120
240 Insert nops to work around certain VR4120 errata. This option is
241 intended to be used on GCC-generated code: it is not designed to catch
242 all problems in hand-written assembler code.
245 @itemx -mno-fix-vr4130
246 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
250 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
253 @itemx -mno-fix-cn63xxp1
254 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
255 certain CN63XXP1 errata.
259 Generate code for the LSI R4010 chip. This tells the assembler to
260 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
261 etc.), and to not schedule @samp{nop} instructions around accesses to
262 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
267 Generate code for the MIPS R4650 chip. This tells the assembler to accept
268 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
269 instructions around accesses to the @samp{HI} and @samp{LO} registers.
270 @samp{-no-m4650} turns off this option.
276 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
277 R@var{nnnn} chip. This tells the assembler to accept instructions
278 specific to that chip, and to schedule for that chip's hazards.
280 @item -march=@var{cpu}
281 Generate code for a particular MIPS CPU. It is exactly equivalent to
282 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
283 understood. Valid @var{cpu} value are:
369 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
370 accepted as synonyms for @samp{@var{n}f1_1}. These values are
373 @item -mtune=@var{cpu}
374 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
375 identical to @samp{-march=@var{cpu}}.
377 @item -mabi=@var{abi}
378 Record which ABI the source code uses. The recognized arguments
379 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
385 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
386 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
388 @cindex @code{-nocpp} ignored (MIPS)
390 This option is ignored. It is accepted for command-line compatibility with
391 other assemblers, which use it to turn off C style preprocessing. With
392 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
393 @sc{gnu} assembler itself never runs the C preprocessor.
397 Disable or enable floating-point instructions. Note that by default
398 floating-point instructions are always allowed even with CPU targets
399 that don't have support for these instructions.
402 @itemx -mdouble-float
403 Disable or enable double-precision floating-point operations. Note
404 that by default double-precision floating-point operations are always
405 allowed even with CPU targets that don't have support for these
408 @item --construct-floats
409 @itemx --no-construct-floats
410 The @code{--no-construct-floats} option disables the construction of
411 double width floating point constants by loading the two halves of the
412 value into the two single width floating point registers that make up
413 the double width register. This feature is useful if the processor
414 support the FR bit in its status register, and this bit is known (by
415 the programmer) to be set. This bit prevents the aliasing of the double
416 width register by the single width registers.
418 By default @code{--construct-floats} is selected, allowing construction
419 of these floating point constants.
422 @itemx --no-relax-branch
423 The @samp{--relax-branch} option enables the relaxation of out-of-range
424 branches. Any branches whose target cannot be reached directly are
425 converted to a small instruction sequence including an inverse-condition
426 branch to the physically next instruction, and a jump to the original
427 target is inserted between the two instructions. In PIC code the jump
428 will involve further instructions for address calculation.
430 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
431 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
432 relaxation, because they have no complementing counterparts. They could
433 be relaxed with the use of a longer sequence involving another branch,
434 however this has not been implemented and if their target turns out of
435 reach, they produce an error even if branch relaxation is enabled.
437 Also no MIPS16 branches are ever relaxed.
439 By default @samp{--no-relax-branch} is selected, causing any out-of-range
440 branches to produce an error.
442 @cindex @option{-mnan=} command line option, MIPS
443 @item -mnan=@var{encoding}
444 This option indicates whether the source code uses the IEEE 2008
445 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
446 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
447 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
449 @option{-mnan=legacy} is the default if no @option{-mnan} option or
450 @code{.nan} directive is used.
454 @c FIXME! (1) reflect these options (next item too) in option summaries;
455 @c (2) stop teasing, say _which_ instructions expanded _how_.
456 @code{@value{AS}} automatically macro expands certain division and
457 multiplication instructions to check for overflow and division by zero. This
458 option causes @code{@value{AS}} to generate code to take a trap exception
459 rather than a break exception when an error is detected. The trap instructions
460 are only supported at Instruction Set Architecture level 2 and higher.
464 Generate code to take a break exception rather than a trap exception when an
465 error is detected. This is the default.
469 Control generation of @code{.pdr} sections. Off by default on IRIX, on
474 When generating code using the Unix calling conventions (selected by
475 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
476 which can go into a shared library. The @samp{-mno-shared} option
477 tells gas to generate code which uses the calling convention, but can
478 not go into a shared library. The resulting code is slightly more
479 efficient. This option only affects the handling of the
480 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
484 @section High-level assembly macros
486 MIPS assemblers have traditionally provided a wider range of
487 instructions than the MIPS architecture itself. These extra
488 instructions are usually referred to as ``macro'' instructions
489 @footnote{The term ``macro'' is somewhat overloaded here, since
490 these macros have no relation to those defined by @code{.macro},
491 @pxref{Macro,, @code{.macro}}.}.
493 Some MIPS macro instructions extend an underlying architectural instruction
494 while others are entirely new. An example of the former type is @code{and},
495 which allows the third operand to be either a register or an arbitrary
496 immediate value. Examples of the latter type include @code{bgt}, which
497 branches to the third operand when the first operand is greater than
498 the second operand, and @code{ulh}, which implements an unaligned
501 One of the most common extensions provided by macros is to expand
502 memory offsets to the full address range (32 or 64 bits) and to allow
503 symbolic offsets such as @samp{my_data + 4} to be used in place of
504 integer constants. For example, the architectural instruction
505 @code{lbu} allows only a signed 16-bit offset, whereas the macro
506 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
507 The implementation of these symbolic offsets depends on several factors,
508 such as whether the assembler is generating SVR4-style PIC (selected by
509 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
510 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
511 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
512 of small data accesses}).
514 @kindex @code{.set macro}
515 @kindex @code{.set nomacro}
516 Sometimes it is undesirable to have one assembly instruction expand
517 to several machine instructions. The directive @code{.set nomacro}
518 tells the assembler to warn when this happens. @code{.set macro}
519 restores the default behavior.
521 @cindex @code{at} register, MIPS
522 @kindex @code{.set at=@var{reg}}
523 Some macro instructions need a temporary register to store intermediate
524 results. This register is usually @code{$1}, also known as @code{$at},
525 but it can be changed to any core register @var{reg} using
526 @code{.set at=@var{reg}}. Note that @code{$at} always refers
527 to @code{$1} regardless of which register is being used as the
530 @kindex @code{.set at}
531 @kindex @code{.set noat}
532 Implicit uses of the temporary register in macros could interfere with
533 explicit uses in the assembly code. The assembler therefore warns
534 whenever it sees an explicit use of the temporary register. The directive
535 @code{.set noat} silences this warning while @code{.set at} restores
536 the default behavior. It is safe to use @code{.set noat} while
537 @code{.set nomacro} is in effect since single-instruction macros
538 never need a temporary register.
540 Note that while the @sc{gnu} assembler provides these macros for compatibility,
541 it does not make any attempt to optimize them with the surrounding code.
543 @node MIPS Symbol Sizes
544 @section Directives to override the size of symbols
546 @kindex @code{.set sym32}
547 @kindex @code{.set nosym32}
548 The n64 ABI allows symbols to have any 64-bit value. Although this
549 provides a great deal of flexibility, it means that some macros have
550 much longer expansions than their 32-bit counterparts. For example,
551 the non-PIC expansion of @samp{dla $4,sym} is usually:
556 daddiu $4,$4,%higher(sym)
557 daddiu $1,$1,%lo(sym)
562 whereas the 32-bit expansion is simply:
566 daddiu $4,$4,%lo(sym)
569 n64 code is sometimes constructed in such a way that all symbolic
570 constants are known to have 32-bit values, and in such cases, it's
571 preferable to use the 32-bit expansion instead of the 64-bit
574 You can use the @code{.set sym32} directive to tell the assembler
575 that, from this point on, all expressions of the form
576 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
577 have 32-bit values. For example:
586 will cause the assembler to treat @samp{sym}, @code{sym+16} and
587 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
588 addresses is not affected.
590 The directive @code{.set nosym32} ends a @code{.set sym32} block and
591 reverts to the normal behavior. It is also possible to change the
592 symbol size using the command-line options @option{-msym32} and
595 These options and directives are always accepted, but at present,
596 they have no effect for anything other than n64.
598 @node MIPS Small Data
599 @section Controlling the use of small data accesses
601 @c This section deliberately glosses over the possibility of using -G
602 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
603 @cindex small data, MIPS
604 @cindex @code{gp} register, MIPS
605 It often takes several instructions to load the address of a symbol.
606 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
607 of @samp{dla $4,addr} is usually:
611 daddiu $4,$4,%lo(addr)
614 The sequence is much longer when @samp{addr} is a 64-bit symbol.
615 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
617 In order to cut down on this overhead, most embedded MIPS systems
618 set aside a 64-kilobyte ``small data'' area and guarantee that all
619 data of size @var{n} and smaller will be placed in that area.
620 The limit @var{n} is passed to both the assembler and the linker
621 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
622 Assembler options}. Note that the same value of @var{n} must be used
623 when linking and when assembling all input files to the link; any
624 inconsistency could cause a relocation overflow error.
626 The size of an object in the @code{.bss} section is set by the
627 @code{.comm} or @code{.lcomm} directive that defines it. The size of
628 an external object may be set with the @code{.extern} directive. For
629 example, @samp{.extern sym,4} declares that the object at @code{sym}
630 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
632 When no @option{-G} option is given, the default limit is 8 bytes.
633 The option @option{-G 0} prevents any data from being automatically
636 It is also possible to mark specific objects as small by putting them
637 in the special sections @code{.sdata} and @code{.sbss}, which are
638 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
639 The toolchain will treat such data as small regardless of the
642 On startup, systems that support a small data area are expected to
643 initialize register @code{$28}, also known as @code{$gp}, in such a
644 way that small data can be accessed using a 16-bit offset from that
645 register. For example, when @samp{addr} is small data,
646 the @samp{dla $4,addr} instruction above is equivalent to:
649 daddiu $4,$28,%gp_rel(addr)
652 Small data is not supported for SVR4-style PIC.
655 @section Directives to override the ISA level
657 @cindex MIPS ISA override
658 @kindex @code{.set mips@var{n}}
659 @sc{gnu} @code{@value{AS}} supports an additional directive to change
660 the MIPS Instruction Set Architecture level on the fly: @code{.set
661 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
662 32r5, 64, 64r2, 64r3 or 64r5.
663 The values other than 0 make the assembler accept instructions
664 for the corresponding ISA level, from that point on in the
665 assembly. @code{.set mips@var{n}} affects not only which instructions
666 are permitted, but also how certain macros are expanded. @code{.set
667 mips0} restores the ISA level to its original level: either the
668 level you selected with command line options, or the default for your
669 configuration. You can use this feature to permit specific MIPS III
670 instructions while assembling in 32 bit mode. Use this directive with
673 @cindex MIPS CPU override
674 @kindex @code{.set arch=@var{cpu}}
675 The @code{.set arch=@var{cpu}} directive provides even finer control.
676 It changes the effective CPU target and allows the assembler to use
677 instructions specific to a particular CPU. All CPUs supported by the
678 @samp{-march} command line option are also selectable by this directive.
679 The original value is restored by @code{.set arch=default}.
681 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
682 in which it will assemble instructions for the MIPS 16 processor. Use
683 @code{.set nomips16} to return to normal 32 bit mode.
685 Traditional MIPS assemblers do not support this directive.
687 The directive @code{.set micromips} puts the assembler into microMIPS mode,
688 in which it will assemble instructions for the microMIPS processor. Use
689 @code{.set nomicromips} to return to normal 32 bit mode.
691 Traditional MIPS assemblers do not support this directive.
693 @node MIPS assembly options
694 @section Directives to control code generation
696 @cindex MIPS 32-bit microMIPS instruction generation override
697 @kindex @code{.set insn32}
698 @kindex @code{.set noinsn32}
699 The directive @code{.set insn32} makes the assembler only use 32-bit
700 instruction encodings when generating code for the microMIPS processor.
701 This directive inhibits the use of any 16-bit instructions from that
702 point on in the assembly. The @code{.set noinsn32} directive allows
703 16-bit instructions to be accepted.
705 Traditional MIPS assemblers do not support this directive.
707 @node MIPS autoextend
708 @section Directives for extending MIPS 16 bit instructions
710 @kindex @code{.set autoextend}
711 @kindex @code{.set noautoextend}
712 By default, MIPS 16 instructions are automatically extended to 32 bits
713 when necessary. The directive @code{.set noautoextend} will turn this
714 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
715 must be explicitly extended with the @code{.e} modifier (e.g.,
716 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
717 to once again automatically extend instructions when necessary.
719 This directive is only meaningful when in MIPS 16 mode. Traditional
720 MIPS assemblers do not support this directive.
723 @section Directive to mark data as an instruction
726 The @code{.insn} directive tells @code{@value{AS}} that the following
727 data is actually instructions. This makes a difference in MIPS 16 and
728 microMIPS modes: when loading the address of a label which precedes
729 instructions, @code{@value{AS}} automatically adds 1 to the value, so
730 that jumping to the loaded address will do the right thing.
732 @kindex @code{.global}
733 The @code{.global} and @code{.globl} directives supported by
734 @code{@value{AS}} will by default mark the symbol as pointing to a
735 region of data not code. This means that, for example, any
736 instructions following such a symbol will not be disassembled by
737 @code{objdump} as it will regard them as data. To change this
738 behaviour an optional section name can be placed after the symbol name
739 in the @code{.global} directive. If this section exists and is known
740 to be a code section, then the symbol will be marked as poiting at
741 code not data. Ie the syntax for the directive is:
743 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
745 Here is a short example:
748 .global foo .text, bar, baz .data
758 @node MIPS NaN Encodings
759 @section Directives to record which NaN encoding is being used
761 @cindex MIPS IEEE 754 NaN data encoding selection
762 @cindex @code{.nan} directive, MIPS
763 The IEEE 754 floating-point standard defines two types of not-a-number
764 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
765 of the standard did not specify how these two types should be
766 distinguished. Most implementations followed the i387 model, in which
767 the first bit of the significand is set for quiet NaNs and clear for
768 signalling NaNs. However, the original MIPS implementation assigned the
769 opposite meaning to the bit, so that it was set for signalling NaNs and
770 clear for quiet NaNs.
772 The 2008 revision of the standard formally suggested the i387 choice
773 and as from Sep 2012 the current release of the MIPS architecture
774 therefore optionally supports that form. Code that uses one NaN encoding
775 would usually be incompatible with code that uses the other NaN encoding,
776 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
777 encoding is being used.
779 Assembly files can use the @code{.nan} directive to select between the
780 two encodings. @samp{.nan 2008} says that the assembly file uses the
781 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
782 the original MIPS encoding. If several @code{.nan} directives are given,
783 the final setting is the one that is used.
785 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
786 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
787 respectively. However, any @code{.nan} directive overrides the
788 command-line setting.
790 @samp{.nan legacy} is the default if no @code{.nan} directive or
791 @option{-mnan} option is given.
793 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
794 therefore these directives do not affect code generation. They simply
795 control the setting of the @code{EF_MIPS_NAN2008} flag.
797 Traditional MIPS assemblers do not support these directives.
799 @node MIPS Option Stack
800 @section Directives to save and restore options
802 @cindex MIPS option stack
803 @kindex @code{.set push}
804 @kindex @code{.set pop}
805 The directives @code{.set push} and @code{.set pop} may be used to save
806 and restore the current settings for all the options which are
807 controlled by @code{.set}. The @code{.set push} directive saves the
808 current settings on a stack. The @code{.set pop} directive pops the
809 stack and restores the settings.
811 These directives can be useful inside an macro which must change an
812 option such as the ISA level or instruction reordering but does not want
813 to change the state of the code which invoked the macro.
815 Traditional MIPS assemblers do not support these directives.
817 @node MIPS ASE Instruction Generation Overrides
818 @section Directives to control generation of MIPS ASE instructions
820 @cindex MIPS MIPS-3D instruction generation override
821 @kindex @code{.set mips3d}
822 @kindex @code{.set nomips3d}
823 The directive @code{.set mips3d} makes the assembler accept instructions
824 from the MIPS-3D Application Specific Extension from that point on
825 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
826 instructions from being accepted.
828 @cindex SmartMIPS instruction generation override
829 @kindex @code{.set smartmips}
830 @kindex @code{.set nosmartmips}
831 The directive @code{.set smartmips} makes the assembler accept
832 instructions from the SmartMIPS Application Specific Extension to the
833 MIPS32 ISA from that point on in the assembly. The
834 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
837 @cindex MIPS MDMX instruction generation override
838 @kindex @code{.set mdmx}
839 @kindex @code{.set nomdmx}
840 The directive @code{.set mdmx} makes the assembler accept instructions
841 from the MDMX Application Specific Extension from that point on
842 in the assembly. The @code{.set nomdmx} directive prevents MDMX
843 instructions from being accepted.
845 @cindex MIPS DSP Release 1 instruction generation override
846 @kindex @code{.set dsp}
847 @kindex @code{.set nodsp}
848 The directive @code{.set dsp} makes the assembler accept instructions
849 from the DSP Release 1 Application Specific Extension from that point
850 on in the assembly. The @code{.set nodsp} directive prevents DSP
851 Release 1 instructions from being accepted.
853 @cindex MIPS DSP Release 2 instruction generation override
854 @kindex @code{.set dspr2}
855 @kindex @code{.set nodspr2}
856 The directive @code{.set dspr2} makes the assembler accept instructions
857 from the DSP Release 2 Application Specific Extension from that point
858 on in the assembly. This dirctive implies @code{.set dsp}. The
859 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
862 @cindex MIPS MT instruction generation override
863 @kindex @code{.set mt}
864 @kindex @code{.set nomt}
865 The directive @code{.set mt} makes the assembler accept instructions
866 from the MT Application Specific Extension from that point on
867 in the assembly. The @code{.set nomt} directive prevents MT
868 instructions from being accepted.
870 @cindex MIPS MCU instruction generation override
871 @kindex @code{.set mcu}
872 @kindex @code{.set nomcu}
873 The directive @code{.set mcu} makes the assembler accept instructions
874 from the MCU Application Specific Extension from that point on
875 in the assembly. The @code{.set nomcu} directive prevents MCU
876 instructions from being accepted.
878 @cindex MIPS SIMD Architecture instruction generation override
879 @kindex @code{.set msa}
880 @kindex @code{.set nomsa}
881 The directive @code{.set msa} makes the assembler accept instructions
882 from the MIPS SIMD Architecture Extension from that point on
883 in the assembly. The @code{.set nomsa} directive prevents MSA
884 instructions from being accepted.
886 @cindex Virtualization instruction generation override
887 @kindex @code{.set virt}
888 @kindex @code{.set novirt}
889 The directive @code{.set virt} makes the assembler accept instructions
890 from the Virtualization Application Specific Extension from that point
891 on in the assembly. The @code{.set novirt} directive prevents Virtualization
892 instructions from being accepted.
894 @cindex MIPS eXtended Physical Address (XPA) instruction generation override
895 @kindex @code{.set xpa}
896 @kindex @code{.set noxpa}
897 The directive @code{.set xpa} makes the assembler accept instructions
898 from the XPA Extension from that point on in the assembly. The
899 @code{.set noxpa} directive prevents XPA instructions from being accepted.
901 Traditional MIPS assemblers do not support these directives.
903 @node MIPS Floating-Point
904 @section Directives to override floating-point options
906 @cindex Disable floating-point instructions
907 @kindex @code{.set softfloat}
908 @kindex @code{.set hardfloat}
909 The directives @code{.set softfloat} and @code{.set hardfloat} provide
910 finer control of disabling and enabling float-point instructions.
911 These directives always override the default (that hard-float
912 instructions are accepted) or the command-line options
913 (@samp{-msoft-float} and @samp{-mhard-float}).
915 @cindex Disable single-precision floating-point operations
916 @kindex @code{.set singlefloat}
917 @kindex @code{.set doublefloat}
918 The directives @code{.set singlefloat} and @code{.set doublefloat}
919 provide finer control of disabling and enabling double-precision
920 float-point operations. These directives always override the default
921 (that double-precision operations are accepted) or the command-line
922 options (@samp{-msingle-float} and @samp{-mdouble-float}).
924 Traditional MIPS assemblers do not support these directives.
927 @section Syntactical considerations for the MIPS assembler
929 * MIPS-Chars:: Special Characters
933 @subsection Special Characters
935 @cindex line comment character, MIPS
936 @cindex MIPS line comment character
937 The presence of a @samp{#} on a line indicates the start of a comment
938 that extends to the end of the current line.
940 If a @samp{#} appears as the first character of a line, the whole line
941 is treated as a comment, but in this case the line can also be a
942 logical line number directive (@pxref{Comments}) or a
943 preprocessor control command (@pxref{Preprocessing}).
945 @cindex line separator, MIPS
946 @cindex statement separator, MIPS
947 @cindex MIPS line separator
948 The @samp{;} character can be used to separate statements on the same