1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
8 @chapter MIPS Dependent Features
11 @node Machine Dependencies
12 @chapter MIPS Dependent Features
15 @cindex MIPS processor
16 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
17 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
18 and MIPS64. For information about the @sc{mips} instruction set, see
19 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
20 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
21 Assembly Language Programming'' in the same work.
24 * MIPS Opts:: Assembler options
25 * MIPS Object:: ECOFF object code
26 * MIPS Stabs:: Directives for debugging information
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
29 * MIPS insn:: Directive to mark data as an instruction
30 * MIPS option stack:: Directives to save and restore options
31 * MIPS ASE instruction generation overrides:: Directives to control generation of MIPS ASE instructions
35 @section Assembler options
37 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
41 @cindex @code{-G} option (MIPS)
43 This option sets the largest size of an object that can be referenced
44 implicitly with the @code{gp} register. It is only accepted for targets
45 that use @sc{ecoff} format. The default value is 8.
47 @cindex @code{-EB} option (MIPS)
48 @cindex @code{-EL} option (MIPS)
49 @cindex MIPS big-endian output
50 @cindex MIPS little-endian output
51 @cindex big-endian output, MIPS
52 @cindex little-endian output, MIPS
55 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
56 little-endian output at run time (unlike the other @sc{gnu} development
57 tools, which must be configured for one or the other). Use @samp{-EB}
58 to select big-endian output, and @samp{-EL} for little-endian.
60 @cindex MIPS architecture options
68 Generate code for a particular MIPS Instruction Set Architecture level.
69 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
70 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
71 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
72 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, and
73 @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and
74 @sc{MIPS64} ISA processors, respectively. You can also switch
75 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
76 override the ISA level}.
80 Some macros have different expansions for 32-bit and 64-bit registers.
81 The register sizes are normally inferred from the ISA and ABI, but these
82 flags force a certain group of registers to be treated as 32 bits wide at
83 all times. @samp{-mgp32} controls the size of general-purpose registers
84 and @samp{-mfp32} controls the size of floating-point registers.
86 On some MIPS variants there is a 32-bit mode flag; when this flag is
87 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
88 save the 32-bit registers on a context switch, so it is essential never
89 to use the 64-bit registers.
92 Assume that 64-bit general purpose registers are available. This is
93 provided in the interests of symmetry with -gp32.
97 Generate code for the MIPS 16 processor. This is equivalent to putting
98 @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
99 turns off this option.
103 Generate code for the MIPS-3D Application Specific Extension.
104 This tells the assembler to accept MIPS-3D instructions.
105 @samp{-no-mips3d} turns off this option.
109 Cause nops to be inserted if the read of the destination register
110 of an mfhi or mflo instruction occurs in the following two instructions.
114 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
115 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
116 etc.), and to not schedule @samp{nop} instructions around accesses to
117 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
122 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
123 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
124 instructions around accesses to the @samp{HI} and @samp{LO} registers.
125 @samp{-no-m4650} turns off this option.
131 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
132 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
133 specific to that chip, and to schedule for that chip's hazards.
135 @item -march=@var{cpu}
136 Generate code for a particular MIPS cpu. It is exactly equivalent to
137 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
138 understood. Valid @var{cpu} value are:
167 @item -mtune=@var{cpu}
168 Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
169 identical to @samp{-march=@var{cpu}}.
171 @item -mcpu=@var{cpu}
172 Generate code and schedule for a particular MIPS cpu. This is exactly
173 equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}. Valid
174 @var{cpu} values are identical to @samp{-march=@var{cpu}}.
175 Use of this option is discouraged.
178 @cindex @code{-nocpp} ignored (MIPS)
180 This option is ignored. It is accepted for command-line compatibility with
181 other assemblers, which use it to turn off C style preprocessing. With
182 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
183 @sc{gnu} assembler itself never runs the C preprocessor.
185 @item --construct-floats
186 @itemx --no-construct-floats
187 @cindex --construct-floats
188 @cindex --no-construct-floats
189 The @code{--no-construct-floats} option disables the construction of
190 double width floating point constants by loading the two halves of the
191 value into the two single width floating point registers that make up
192 the double width register. This feature is useful if the processor
193 support the FR bit in its status register, and this bit is known (by
194 the programmer) to be set. This bit prevents the aliasing of the double
195 width register by the single width registers.
197 By default @code{--construct-floats} is selected, allowing construction
198 of these floating point constants.
202 @c FIXME! (1) reflect these options (next item too) in option summaries;
203 @c (2) stop teasing, say _which_ instructions expanded _how_.
204 @code{@value{AS}} automatically macro expands certain division and
205 multiplication instructions to check for overflow and division by zero. This
206 option causes @code{@value{AS}} to generate code to take a trap exception
207 rather than a break exception when an error is detected. The trap instructions
208 are only supported at Instruction Set Architecture level 2 and higher.
212 Generate code to take a break exception rather than a trap exception when an
213 error is detected. This is the default.
216 When this option is used, @code{@value{AS}} will issue a warning every
217 time it generates a nop instruction from a macro.
221 @section MIPS ECOFF object code
223 @cindex ECOFF sections
224 @cindex MIPS ECOFF sections
225 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
226 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
227 additional sections are @code{.rdata}, used for read-only data,
228 @code{.sdata}, used for small data, and @code{.sbss}, used for small
231 @cindex small objects, MIPS ECOFF
232 @cindex @code{gp} register, MIPS
233 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
234 register to form the address of a ``small object''. Any object in the
235 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
236 For external objects, or for objects in the @code{.bss} section, you can use
237 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
238 @code{$gp}; the default value is 8, meaning that a reference to any object
239 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
240 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
241 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
242 or @code{sbss} in any case). The size of an object in the @code{.bss} section
243 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
244 size of an external object may be set with the @code{.extern} directive. For
245 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
246 in length, whie leaving @code{sym} otherwise undefined.
248 Using small @sc{ecoff} objects requires linker support, and assumes that the
249 @code{$gp} register is correctly initialized (normally done automatically by
250 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
254 @section Directives for debugging information
256 @cindex MIPS debugging directives
257 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
258 generating debugging information which are not support by traditional @sc{mips}
259 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
260 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
261 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
262 generated by the three @code{.stab} directives can only be read by @sc{gdb},
263 not by traditional @sc{mips} debuggers (this enhancement is required to fully
264 support C++ debugging). These directives are primarily used by compilers, not
265 assembly language programmers!
268 @section Directives to override the ISA level
270 @cindex MIPS ISA override
271 @kindex @code{.set mips@var{n}}
272 @sc{gnu} @code{@value{AS}} supports an additional directive to change
273 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
274 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
275 The values 1 to 5, 32, and 64 make the assembler accept instructions
276 for the corresponding @sc{isa} level, from that point on in the
277 assembly. @code{.set mips@var{n}} affects not only which instructions
278 are permitted, but also how certain macros are expanded. @code{.set
279 mips0} restores the @sc{isa} level to its original level: either the
280 level you selected with command line options, or the default for your
281 configuration. You can use this feature to permit specific @sc{r4000}
282 instructions while assembling in 32 bit mode. Use this directive with
285 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
286 in which it will assemble instructions for the MIPS 16 processor. Use
287 @samp{.set nomips16} to return to normal 32 bit mode.
289 Traditional @sc{mips} assemblers do not support this directive.
291 @node MIPS autoextend
292 @section Directives for extending MIPS 16 bit instructions
294 @kindex @code{.set autoextend}
295 @kindex @code{.set noautoextend}
296 By default, MIPS 16 instructions are automatically extended to 32 bits
297 when necessary. The directive @samp{.set noautoextend} will turn this
298 off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
299 must be explicitly extended with the @samp{.e} modifier (e.g.,
300 @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
301 to once again automatically extend instructions when necessary.
303 This directive is only meaningful when in MIPS 16 mode. Traditional
304 @sc{mips} assemblers do not support this directive.
307 @section Directive to mark data as an instruction
310 The @code{.insn} directive tells @code{@value{AS}} that the following
311 data is actually instructions. This makes a difference in MIPS 16 mode:
312 when loading the address of a label which precedes instructions,
313 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
314 the loaded address will do the right thing.
316 @node MIPS option stack
317 @section Directives to save and restore options
319 @cindex MIPS option stack
320 @kindex @code{.set push}
321 @kindex @code{.set pop}
322 The directives @code{.set push} and @code{.set pop} may be used to save
323 and restore the current settings for all the options which are
324 controlled by @code{.set}. The @code{.set push} directive saves the
325 current settings on a stack. The @code{.set pop} directive pops the
326 stack and restores the settings.
328 These directives can be useful inside an macro which must change an
329 option such as the ISA level or instruction reordering but does not want
330 to change the state of the code which invoked the macro.
332 Traditional @sc{mips} assemblers do not support these directives.
334 @node MIPS ASE instruction generation overrides
335 @section Directives to control generation of MIPS ASE instructions
337 @cindex MIPS MIPS-3D instruction generation override
338 @kindex @code{.set mips3d}
339 @kindex @code{.set nomips3d}
340 The directive @code{.set mips3d} makes the assembler accept instructions
341 from the MIPS-3D Application Specific Extension from that point on
342 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
343 instructions from being accepted.
345 Traditional @sc{mips} assemblers do not support these directives.