1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
18 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the @sc{mips} instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Opts:: Assembler options
26 * MIPS Object:: ECOFF object code
27 * MIPS Stabs:: Directives for debugging information
28 * MIPS ISA:: Directives to override the ISA level
29 * MIPS symbol sizes:: Directives to override the size of symbols
30 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
31 * MIPS insn:: Directive to mark data as an instruction
32 * MIPS option stack:: Directives to save and restore options
33 * MIPS ASE instruction generation overrides:: Directives to control
34 generation of MIPS ASE instructions
38 @section Assembler options
40 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
44 @cindex @code{-G} option (MIPS)
46 This option sets the largest size of an object that can be referenced
47 implicitly with the @code{gp} register. It is only accepted for targets
48 that use @sc{ecoff} format. The default value is 8.
50 @cindex @code{-EB} option (MIPS)
51 @cindex @code{-EL} option (MIPS)
52 @cindex MIPS big-endian output
53 @cindex MIPS little-endian output
54 @cindex big-endian output, MIPS
55 @cindex little-endian output, MIPS
58 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
59 little-endian output at run time (unlike the other @sc{gnu} development
60 tools, which must be configured for one or the other). Use @samp{-EB}
61 to select big-endian output, and @samp{-EL} for little-endian.
63 @cindex MIPS architecture options
73 Generate code for a particular MIPS Instruction Set Architecture level.
74 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
75 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
76 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
77 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
78 @samp{-mips64}, and @samp{-mips64r2}
80 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
81 and @sc{MIPS64 Release 2}
82 ISA processors, respectively. You can also switch
83 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
84 override the ISA level}.
88 Some macros have different expansions for 32-bit and 64-bit registers.
89 The register sizes are normally inferred from the ISA and ABI, but these
90 flags force a certain group of registers to be treated as 32 bits wide at
91 all times. @samp{-mgp32} controls the size of general-purpose registers
92 and @samp{-mfp32} controls the size of floating-point registers.
94 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
95 of registers to be changed for parts of an object. The default value is
96 restored by @code{.set gp=default} and @code{.set fp=default}.
98 On some MIPS variants there is a 32-bit mode flag; when this flag is
99 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
100 save the 32-bit registers on a context switch, so it is essential never
101 to use the 64-bit registers.
105 Assume that 64-bit registers are available. This is provided in the
106 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
108 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
109 of registers to be changed for parts of an object. The default value is
110 restored by @code{.set gp=default} and @code{.set fp=default}.
114 Generate code for the MIPS 16 processor. This is equivalent to putting
115 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
116 turns off this option.
119 @itemx -mno-smartmips
120 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
121 provides a number of new instructions which target smartcard and
122 cryptographic applications. This is equivalent to putting
123 @code{.set smartmips} at the start of the assembly file.
124 @samp{-mno-smartmips} turns off this option.
128 Generate code for the MIPS-3D Application Specific Extension.
129 This tells the assembler to accept MIPS-3D instructions.
130 @samp{-no-mips3d} turns off this option.
134 Generate code for the MDMX Application Specific Extension.
135 This tells the assembler to accept MDMX instructions.
136 @samp{-no-mdmx} turns off this option.
140 Generate code for the DSP Release 1 Application Specific Extension.
141 This tells the assembler to accept DSP Release 1 instructions.
142 @samp{-mno-dsp} turns off this option.
146 Generate code for the DSP Release 2 Application Specific Extension.
147 This option implies -mdsp.
148 This tells the assembler to accept DSP Release 2 instructions.
149 @samp{-mno-dspr2} turns off this option.
153 Generate code for the MT Application Specific Extension.
154 This tells the assembler to accept MT instructions.
155 @samp{-mno-mt} turns off this option.
159 Cause nops to be inserted if the read of the destination register
160 of an mfhi or mflo instruction occurs in the following two instructions.
163 @itemx -no-mfix-vr4120
164 Insert nops to work around certain VR4120 errata. This option is
165 intended to be used on GCC-generated code: it is not designed to catch
166 all problems in hand-written assembler code.
169 @itemx -no-mfix-vr4130
170 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
174 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
175 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
176 etc.), and to not schedule @samp{nop} instructions around accesses to
177 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
182 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
183 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
184 instructions around accesses to the @samp{HI} and @samp{LO} registers.
185 @samp{-no-m4650} turns off this option.
191 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
192 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
193 specific to that chip, and to schedule for that chip's hazards.
195 @item -march=@var{cpu}
196 Generate code for a particular MIPS cpu. It is exactly equivalent to
197 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
198 understood. Valid @var{cpu} value are:
256 @item -mtune=@var{cpu}
257 Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
258 identical to @samp{-march=@var{cpu}}.
260 @item -mabi=@var{abi}
261 Record which ABI the source code uses. The recognized arguments
262 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
268 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
269 the beginning of the assembler input. @xref{MIPS symbol sizes}.
271 @cindex @code{-nocpp} ignored (MIPS)
273 This option is ignored. It is accepted for command-line compatibility with
274 other assemblers, which use it to turn off C style preprocessing. With
275 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
276 @sc{gnu} assembler itself never runs the C preprocessor.
278 @item --construct-floats
279 @itemx --no-construct-floats
280 @cindex --construct-floats
281 @cindex --no-construct-floats
282 The @code{--no-construct-floats} option disables the construction of
283 double width floating point constants by loading the two halves of the
284 value into the two single width floating point registers that make up
285 the double width register. This feature is useful if the processor
286 support the FR bit in its status register, and this bit is known (by
287 the programmer) to be set. This bit prevents the aliasing of the double
288 width register by the single width registers.
290 By default @code{--construct-floats} is selected, allowing construction
291 of these floating point constants.
295 @c FIXME! (1) reflect these options (next item too) in option summaries;
296 @c (2) stop teasing, say _which_ instructions expanded _how_.
297 @code{@value{AS}} automatically macro expands certain division and
298 multiplication instructions to check for overflow and division by zero. This
299 option causes @code{@value{AS}} to generate code to take a trap exception
300 rather than a break exception when an error is detected. The trap instructions
301 are only supported at Instruction Set Architecture level 2 and higher.
305 Generate code to take a break exception rather than a trap exception when an
306 error is detected. This is the default.
310 Control generation of @code{.pdr} sections. Off by default on IRIX, on
315 When generating code using the Unix calling conventions (selected by
316 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
317 which can go into a shared library. The @samp{-mno-shared} option
318 tells gas to generate code which uses the calling convention, but can
319 not go into a shared library. The resulting code is slightly more
320 efficient. This option only affects the handling of the
321 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
325 @section MIPS ECOFF object code
327 @cindex ECOFF sections
328 @cindex MIPS ECOFF sections
329 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
330 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
331 additional sections are @code{.rdata}, used for read-only data,
332 @code{.sdata}, used for small data, and @code{.sbss}, used for small
335 @cindex small objects, MIPS ECOFF
336 @cindex @code{gp} register, MIPS
337 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
338 register to form the address of a ``small object''. Any object in the
339 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
340 For external objects, or for objects in the @code{.bss} section, you can use
341 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
342 @code{$gp}; the default value is 8, meaning that a reference to any object
343 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
344 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
345 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
346 or @code{sbss} in any case). The size of an object in the @code{.bss} section
347 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
348 size of an external object may be set with the @code{.extern} directive. For
349 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
350 in length, whie leaving @code{sym} otherwise undefined.
352 Using small @sc{ecoff} objects requires linker support, and assumes that the
353 @code{$gp} register is correctly initialized (normally done automatically by
354 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
358 @section Directives for debugging information
360 @cindex MIPS debugging directives
361 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
362 generating debugging information which are not support by traditional @sc{mips}
363 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
364 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
365 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
366 generated by the three @code{.stab} directives can only be read by @sc{gdb},
367 not by traditional @sc{mips} debuggers (this enhancement is required to fully
368 support C++ debugging). These directives are primarily used by compilers, not
369 assembly language programmers!
371 @node MIPS symbol sizes
372 @section Directives to override the size of symbols
374 @cindex @code{.set sym32}
375 @cindex @code{.set nosym32}
376 The n64 ABI allows symbols to have any 64-bit value. Although this
377 provides a great deal of flexibility, it means that some macros have
378 much longer expansions than their 32-bit counterparts. For example,
379 the non-PIC expansion of @samp{dla $4,sym} is usually:
384 daddiu $4,$4,%higher(sym)
385 daddiu $1,$1,%lo(sym)
390 whereas the 32-bit expansion is simply:
394 daddiu $4,$4,%lo(sym)
397 n64 code is sometimes constructed in such a way that all symbolic
398 constants are known to have 32-bit values, and in such cases, it's
399 preferable to use the 32-bit expansion instead of the 64-bit
402 You can use the @code{.set sym32} directive to tell the assembler
403 that, from this point on, all expressions of the form
404 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
405 have 32-bit values. For example:
414 will cause the assembler to treat @samp{sym}, @code{sym+16} and
415 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
416 addresses is not affected.
418 The directive @code{.set nosym32} ends a @code{.set sym32} block and
419 reverts to the normal behavior. It is also possible to change the
420 symbol size using the command-line options @option{-msym32} and
423 These options and directives are always accepted, but at present,
424 they have no effect for anything other than n64.
427 @section Directives to override the ISA level
429 @cindex MIPS ISA override
430 @kindex @code{.set mips@var{n}}
431 @sc{gnu} @code{@value{AS}} supports an additional directive to change
432 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
433 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
435 The values other than 0 make the assembler accept instructions
436 for the corresponding @sc{isa} level, from that point on in the
437 assembly. @code{.set mips@var{n}} affects not only which instructions
438 are permitted, but also how certain macros are expanded. @code{.set
439 mips0} restores the @sc{isa} level to its original level: either the
440 level you selected with command line options, or the default for your
441 configuration. You can use this feature to permit specific @sc{mips3}
442 instructions while assembling in 32 bit mode. Use this directive with
445 @cindex MIPS CPU override
446 @kindex @code{.set arch=@var{cpu}}
447 The @code{.set arch=@var{cpu}} directive provides even finer control.
448 It changes the effective CPU target and allows the assembler to use
449 instructions specific to a particular CPU. All CPUs supported by the
450 @samp{-march} command line option are also selectable by this directive.
451 The original value is restored by @code{.set arch=default}.
453 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
454 in which it will assemble instructions for the MIPS 16 processor. Use
455 @code{.set nomips16} to return to normal 32 bit mode.
457 Traditional @sc{mips} assemblers do not support this directive.
459 @node MIPS autoextend
460 @section Directives for extending MIPS 16 bit instructions
462 @kindex @code{.set autoextend}
463 @kindex @code{.set noautoextend}
464 By default, MIPS 16 instructions are automatically extended to 32 bits
465 when necessary. The directive @code{.set noautoextend} will turn this
466 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
467 must be explicitly extended with the @code{.e} modifier (e.g.,
468 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
469 to once again automatically extend instructions when necessary.
471 This directive is only meaningful when in MIPS 16 mode. Traditional
472 @sc{mips} assemblers do not support this directive.
475 @section Directive to mark data as an instruction
478 The @code{.insn} directive tells @code{@value{AS}} that the following
479 data is actually instructions. This makes a difference in MIPS 16 mode:
480 when loading the address of a label which precedes instructions,
481 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
482 the loaded address will do the right thing.
484 @node MIPS option stack
485 @section Directives to save and restore options
487 @cindex MIPS option stack
488 @kindex @code{.set push}
489 @kindex @code{.set pop}
490 The directives @code{.set push} and @code{.set pop} may be used to save
491 and restore the current settings for all the options which are
492 controlled by @code{.set}. The @code{.set push} directive saves the
493 current settings on a stack. The @code{.set pop} directive pops the
494 stack and restores the settings.
496 These directives can be useful inside an macro which must change an
497 option such as the ISA level or instruction reordering but does not want
498 to change the state of the code which invoked the macro.
500 Traditional @sc{mips} assemblers do not support these directives.
502 @node MIPS ASE instruction generation overrides
503 @section Directives to control generation of MIPS ASE instructions
505 @cindex MIPS MIPS-3D instruction generation override
506 @kindex @code{.set mips3d}
507 @kindex @code{.set nomips3d}
508 The directive @code{.set mips3d} makes the assembler accept instructions
509 from the MIPS-3D Application Specific Extension from that point on
510 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
511 instructions from being accepted.
513 @cindex SmartMIPS instruction generation override
514 @kindex @code{.set smartmips}
515 @kindex @code{.set nosmartmips}
516 The directive @code{.set smartmips} makes the assembler accept
517 instructions from the SmartMIPS Application Specific Extension to the
518 MIPS32 @sc{isa} from that point on in the assembly. The
519 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
522 @cindex MIPS MDMX instruction generation override
523 @kindex @code{.set mdmx}
524 @kindex @code{.set nomdmx}
525 The directive @code{.set mdmx} makes the assembler accept instructions
526 from the MDMX Application Specific Extension from that point on
527 in the assembly. The @code{.set nomdmx} directive prevents MDMX
528 instructions from being accepted.
530 @cindex MIPS DSP Release 1 instruction generation override
531 @kindex @code{.set dsp}
532 @kindex @code{.set nodsp}
533 The directive @code{.set dsp} makes the assembler accept instructions
534 from the DSP Release 1 Application Specific Extension from that point
535 on in the assembly. The @code{.set nodsp} directive prevents DSP
536 Release 1 instructions from being accepted.
538 @cindex MIPS DSP Release 2 instruction generation override
539 @kindex @code{.set dspr2}
540 @kindex @code{.set nodspr2}
541 The directive @code{.set dspr2} makes the assembler accept instructions
542 from the DSP Release 2 Application Specific Extension from that point
543 on in the assembly. This dirctive implies @code{.set dsp}. The
544 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
547 @cindex MIPS MT instruction generation override
548 @kindex @code{.set mt}
549 @kindex @code{.set nomt}
550 The directive @code{.set mt} makes the assembler accept instructions
551 from the MT Application Specific Extension from that point on
552 in the assembly. The @code{.set nomt} directive prevents MT
553 instructions from being accepted.
555 Traditional @sc{mips} assemblers do not support these directives.