1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
18 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the MIPS instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of MIPS assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Options:: Assembler options
26 * MIPS Macros:: High-level assembly macros
27 * MIPS Symbol Sizes:: Directives to override the size of symbols
28 * MIPS Small Data:: Controlling the use of small data accesses
29 * MIPS ISA:: Directives to override the ISA level
30 * MIPS assembly options:: Directives to control code generation
31 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
32 * MIPS insn:: Directive to mark data as an instruction
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
41 @section Assembler options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
49 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
87 Generate code for a particular MIPS Instruction Set Architecture level.
88 @samp{-mips1} corresponds to the R2000 and R3000 processors,
89 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
90 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
91 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
92 @samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
93 MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also
94 switch instruction sets during the assembly; see @ref{MIPS ISA,
95 Directives to override the ISA level}.
99 Some macros have different expansions for 32-bit and 64-bit registers.
100 The register sizes are normally inferred from the ISA and ABI, but these
101 flags force a certain group of registers to be treated as 32 bits wide at
102 all times. @samp{-mgp32} controls the size of general-purpose registers
103 and @samp{-mfp32} controls the size of floating-point registers.
105 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
106 of registers to be changed for parts of an object. The default value is
107 restored by @code{.set gp=default} and @code{.set fp=default}.
109 On some MIPS variants there is a 32-bit mode flag; when this flag is
110 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
111 save the 32-bit registers on a context switch, so it is essential never
112 to use the 64-bit registers.
116 Assume that 64-bit registers are available. This is provided in the
117 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
119 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
120 of registers to be changed for parts of an object. The default value is
121 restored by @code{.set gp=default} and @code{.set fp=default}.
125 Generate code for the MIPS 16 processor. This is equivalent to putting
126 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
127 turns off this option.
130 @itemx -mno-micromips
131 Generate code for the microMIPS processor. This is equivalent to putting
132 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
133 turns off this option. This is equivalent to putting @code{.set nomicromips}
134 at the start of the assembly file.
137 @itemx -mno-smartmips
138 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
139 provides a number of new instructions which target smartcard and
140 cryptographic applications. This is equivalent to putting
141 @code{.set smartmips} at the start of the assembly file.
142 @samp{-mno-smartmips} turns off this option.
146 Generate code for the MIPS-3D Application Specific Extension.
147 This tells the assembler to accept MIPS-3D instructions.
148 @samp{-no-mips3d} turns off this option.
152 Generate code for the MDMX Application Specific Extension.
153 This tells the assembler to accept MDMX instructions.
154 @samp{-no-mdmx} turns off this option.
158 Generate code for the DSP Release 1 Application Specific Extension.
159 This tells the assembler to accept DSP Release 1 instructions.
160 @samp{-mno-dsp} turns off this option.
164 Generate code for the DSP Release 2 Application Specific Extension.
165 This option implies -mdsp.
166 This tells the assembler to accept DSP Release 2 instructions.
167 @samp{-mno-dspr2} turns off this option.
171 Generate code for the MT Application Specific Extension.
172 This tells the assembler to accept MT instructions.
173 @samp{-mno-mt} turns off this option.
177 Generate code for the MCU Application Specific Extension.
178 This tells the assembler to accept MCU instructions.
179 @samp{-mno-mcu} turns off this option.
183 Generate code for the Virtualization Application Specific Extension.
184 This tells the assembler to accept Virtualization instructions.
185 @samp{-mno-virt} turns off this option.
189 Only use 32-bit instruction encodings when generating code for the
190 microMIPS processor. This option inhibits the use of any 16-bit
191 instructions. This is equivalent to putting @code{.set insn32} at
192 the start of the assembly file. @samp{-mno-insn32} turns off this
193 option. This is equivalent to putting @code{.set noinsn32} at the
194 start of the assembly file. By default @samp{-mno-insn32} is
195 selected, allowing all instructions to be used.
199 Cause nops to be inserted if the read of the destination register
200 of an mfhi or mflo instruction occurs in the following two instructions.
202 @item -mfix-loongson2f-jump
203 @itemx -mno-fix-loongson2f-jump
204 Eliminate instruction fetch from outside 256M region to work around the
205 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
206 the kernel may crash. The issue has been solved in latest processor
207 batches, but this fix has no side effect to them.
209 @item -mfix-loongson2f-nop
210 @itemx -mno-fix-loongson2f-nop
211 Replace nops by @code{or at,at,zero} to work around the Loongson2F
212 @samp{nop} errata. Without it, under extreme cases, the CPU might
213 deadlock. The issue has been solved in later Loongson2F batches, but
214 this fix has no side effect to them.
217 @itemx -mno-fix-vr4120
218 Insert nops to work around certain VR4120 errata. This option is
219 intended to be used on GCC-generated code: it is not designed to catch
220 all problems in hand-written assembler code.
223 @itemx -mno-fix-vr4130
224 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
228 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
231 @itemx -mno-fix-cn63xxp1
232 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
233 certain CN63XXP1 errata.
237 Generate code for the LSI R4010 chip. This tells the assembler to
238 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
239 etc.), and to not schedule @samp{nop} instructions around accesses to
240 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
245 Generate code for the MIPS R4650 chip. This tells the assembler to accept
246 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
247 instructions around accesses to the @samp{HI} and @samp{LO} registers.
248 @samp{-no-m4650} turns off this option.
254 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
255 R@var{nnnn} chip. This tells the assembler to accept instructions
256 specific to that chip, and to schedule for that chip's hazards.
258 @item -march=@var{cpu}
259 Generate code for a particular MIPS CPU. It is exactly equivalent to
260 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
261 understood. Valid @var{cpu} value are:
346 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
347 accepted as synonyms for @samp{@var{n}f1_1}. These values are
350 @item -mtune=@var{cpu}
351 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
352 identical to @samp{-march=@var{cpu}}.
354 @item -mabi=@var{abi}
355 Record which ABI the source code uses. The recognized arguments
356 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
362 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
363 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
365 @cindex @code{-nocpp} ignored (MIPS)
367 This option is ignored. It is accepted for command-line compatibility with
368 other assemblers, which use it to turn off C style preprocessing. With
369 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
370 @sc{gnu} assembler itself never runs the C preprocessor.
374 Disable or enable floating-point instructions. Note that by default
375 floating-point instructions are always allowed even with CPU targets
376 that don't have support for these instructions.
379 @itemx -mdouble-float
380 Disable or enable double-precision floating-point operations. Note
381 that by default double-precision floating-point operations are always
382 allowed even with CPU targets that don't have support for these
385 @item --construct-floats
386 @itemx --no-construct-floats
387 The @code{--no-construct-floats} option disables the construction of
388 double width floating point constants by loading the two halves of the
389 value into the two single width floating point registers that make up
390 the double width register. This feature is useful if the processor
391 support the FR bit in its status register, and this bit is known (by
392 the programmer) to be set. This bit prevents the aliasing of the double
393 width register by the single width registers.
395 By default @code{--construct-floats} is selected, allowing construction
396 of these floating point constants.
399 @itemx --no-relax-branch
400 The @samp{--relax-branch} option enables the relaxation of out-of-range
401 branches. Any branches whose target cannot be reached directly are
402 converted to a small instruction sequence including an inverse-condition
403 branch to the physically next instruction, and a jump to the original
404 target is inserted between the two instructions. In PIC code the jump
405 will involve further instructions for address calculation.
407 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
408 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
409 relaxation, because they have no complementing counterparts. They could
410 be relaxed with the use of a longer sequence involving another branch,
411 however this has not been implemented and if their target turns out of
412 reach, they produce an error even if branch relaxation is enabled.
414 Also no MIPS16 branches are ever relaxed.
416 By default @samp{--no-relax-branch} is selected, causing any out-of-range
417 branches to produce an error.
421 @c FIXME! (1) reflect these options (next item too) in option summaries;
422 @c (2) stop teasing, say _which_ instructions expanded _how_.
423 @code{@value{AS}} automatically macro expands certain division and
424 multiplication instructions to check for overflow and division by zero. This
425 option causes @code{@value{AS}} to generate code to take a trap exception
426 rather than a break exception when an error is detected. The trap instructions
427 are only supported at Instruction Set Architecture level 2 and higher.
431 Generate code to take a break exception rather than a trap exception when an
432 error is detected. This is the default.
436 Control generation of @code{.pdr} sections. Off by default on IRIX, on
441 When generating code using the Unix calling conventions (selected by
442 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
443 which can go into a shared library. The @samp{-mno-shared} option
444 tells gas to generate code which uses the calling convention, but can
445 not go into a shared library. The resulting code is slightly more
446 efficient. This option only affects the handling of the
447 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
451 @section High-level assembly macros
453 MIPS assemblers have traditionally provided a wider range of
454 instructions than the MIPS architecture itself. These extra
455 instructions are usually referred to as ``macro'' instructions
456 @footnote{The term ``macro'' is somewhat overloaded here, since
457 these macros have no relation to those defined by @code{.macro},
458 @pxref{Macro,, @code{.macro}}.}.
460 Some MIPS macro instructions extend an underlying architectural instruction
461 while others are entirely new. An example of the former type is @code{and},
462 which allows the third operand to be either a register or an arbitrary
463 immediate value. Examples of the latter type include @code{bgt}, which
464 branches to the third operand when the first operand is greater than
465 the second operand, and @code{ulh}, which implements an unaligned
468 One of the most common extensions provided by macros is to expand
469 memory offsets to the full address range (32 or 64 bits) and to allow
470 symbolic offsets such as @samp{my_data + 4} to be used in place of
471 integer constants. For example, the architectural instruction
472 @code{lbu} allows only a signed 16-bit offset, whereas the macro
473 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
474 The implementation of these symbolic offsets depends on several factors,
475 such as whether the assembler is generating SVR4-style PIC (selected by
476 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
477 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
478 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
479 of small data accesses}).
481 @kindex @code{.set macro}
482 @kindex @code{.set nomacro}
483 Sometimes it is undesirable to have one assembly instruction expand
484 to several machine instructions. The directive @code{.set nomacro}
485 tells the assembler to warn when this happens. @code{.set macro}
486 restores the default behavior.
488 @cindex @code{at} register, MIPS
489 @kindex @code{.set at=@var{reg}}
490 Some macro instructions need a temporary register to store intermediate
491 results. This register is usually @code{$1}, also known as @code{$at},
492 but it can be changed to any core register @var{reg} using
493 @code{.set at=@var{reg}}. Note that @code{$at} always refers
494 to @code{$1} regardless of which register is being used as the
497 @kindex @code{.set at}
498 @kindex @code{.set noat}
499 Implicit uses of the temporary register in macros could interfere with
500 explicit uses in the assembly code. The assembler therefore warns
501 whenever it sees an explicit use of the temporary register. The directive
502 @code{.set noat} silences this warning while @code{.set at} restores
503 the default behavior. It is safe to use @code{.set noat} while
504 @code{.set nomacro} is in effect since single-instruction macros
505 never need a temporary register.
507 Note that while the @sc{gnu} assembler provides these macros for compatibility,
508 it does not make any attempt to optimize them with the surrounding code.
510 @node MIPS Symbol Sizes
511 @section Directives to override the size of symbols
513 @kindex @code{.set sym32}
514 @kindex @code{.set nosym32}
515 The n64 ABI allows symbols to have any 64-bit value. Although this
516 provides a great deal of flexibility, it means that some macros have
517 much longer expansions than their 32-bit counterparts. For example,
518 the non-PIC expansion of @samp{dla $4,sym} is usually:
523 daddiu $4,$4,%higher(sym)
524 daddiu $1,$1,%lo(sym)
529 whereas the 32-bit expansion is simply:
533 daddiu $4,$4,%lo(sym)
536 n64 code is sometimes constructed in such a way that all symbolic
537 constants are known to have 32-bit values, and in such cases, it's
538 preferable to use the 32-bit expansion instead of the 64-bit
541 You can use the @code{.set sym32} directive to tell the assembler
542 that, from this point on, all expressions of the form
543 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
544 have 32-bit values. For example:
553 will cause the assembler to treat @samp{sym}, @code{sym+16} and
554 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
555 addresses is not affected.
557 The directive @code{.set nosym32} ends a @code{.set sym32} block and
558 reverts to the normal behavior. It is also possible to change the
559 symbol size using the command-line options @option{-msym32} and
562 These options and directives are always accepted, but at present,
563 they have no effect for anything other than n64.
565 @node MIPS Small Data
566 @section Controlling the use of small data accesses
568 @c This section deliberately glosses over the possibility of using -G
569 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
570 @cindex small data, MIPS
571 @cindex @code{gp} register, MIPS
572 It often takes several instructions to load the address of a symbol.
573 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
574 of @samp{dla $4,addr} is usually:
578 daddiu $4,$4,%lo(addr)
581 The sequence is much longer when @samp{addr} is a 64-bit symbol.
582 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
584 In order to cut down on this overhead, most embedded MIPS systems
585 set aside a 64-kilobyte ``small data'' area and guarantee that all
586 data of size @var{n} and smaller will be placed in that area.
587 The limit @var{n} is passed to both the assembler and the linker
588 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
589 Assembler options}. Note that the same value of @var{n} must be used
590 when linking and when assembling all input files to the link; any
591 inconsistency could cause a relocation overflow error.
593 The size of an object in the @code{.bss} section is set by the
594 @code{.comm} or @code{.lcomm} directive that defines it. The size of
595 an external object may be set with the @code{.extern} directive. For
596 example, @samp{.extern sym,4} declares that the object at @code{sym}
597 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
599 When no @option{-G} option is given, the default limit is 8 bytes.
600 The option @option{-G 0} prevents any data from being automatically
603 It is also possible to mark specific objects as small by putting them
604 in the special sections @code{.sdata} and @code{.sbss}, which are
605 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
606 The toolchain will treat such data as small regardless of the
609 On startup, systems that support a small data area are expected to
610 initialize register @code{$28}, also known as @code{$gp}, in such a
611 way that small data can be accessed using a 16-bit offset from that
612 register. For example, when @samp{addr} is small data,
613 the @samp{dla $4,addr} instruction above is equivalent to:
616 daddiu $4,$28,%gp_rel(addr)
619 Small data is not supported for SVR4-style PIC.
622 @section Directives to override the ISA level
624 @cindex MIPS ISA override
625 @kindex @code{.set mips@var{n}}
626 @sc{gnu} @code{@value{AS}} supports an additional directive to change
627 the MIPS Instruction Set Architecture level on the fly: @code{.set
628 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
630 The values other than 0 make the assembler accept instructions
631 for the corresponding ISA level, from that point on in the
632 assembly. @code{.set mips@var{n}} affects not only which instructions
633 are permitted, but also how certain macros are expanded. @code{.set
634 mips0} restores the ISA level to its original level: either the
635 level you selected with command line options, or the default for your
636 configuration. You can use this feature to permit specific MIPS III
637 instructions while assembling in 32 bit mode. Use this directive with
640 @cindex MIPS CPU override
641 @kindex @code{.set arch=@var{cpu}}
642 The @code{.set arch=@var{cpu}} directive provides even finer control.
643 It changes the effective CPU target and allows the assembler to use
644 instructions specific to a particular CPU. All CPUs supported by the
645 @samp{-march} command line option are also selectable by this directive.
646 The original value is restored by @code{.set arch=default}.
648 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
649 in which it will assemble instructions for the MIPS 16 processor. Use
650 @code{.set nomips16} to return to normal 32 bit mode.
652 Traditional MIPS assemblers do not support this directive.
654 The directive @code{.set micromips} puts the assembler into microMIPS mode,
655 in which it will assemble instructions for the microMIPS processor. Use
656 @code{.set nomicromips} to return to normal 32 bit mode.
658 Traditional MIPS assemblers do not support this directive.
660 @node MIPS assembly options
661 @section Directives to control code generation
663 @cindex MIPS 32-bit microMIPS instruction generation override
664 @kindex @code{.set insn32}
665 @kindex @code{.set noinsn32}
666 The directive @code{.set insn32} makes the assembler only use 32-bit
667 instruction encodings when generating code for the microMIPS processor.
668 This directive inhibits the use of any 16-bit instructions from that
669 point on in the assembly. The @code{.set noinsn32} directive allows
670 16-bit instructions to be accepted.
672 Traditional MIPS assemblers do not support this directive.
674 @node MIPS autoextend
675 @section Directives for extending MIPS 16 bit instructions
677 @kindex @code{.set autoextend}
678 @kindex @code{.set noautoextend}
679 By default, MIPS 16 instructions are automatically extended to 32 bits
680 when necessary. The directive @code{.set noautoextend} will turn this
681 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
682 must be explicitly extended with the @code{.e} modifier (e.g.,
683 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
684 to once again automatically extend instructions when necessary.
686 This directive is only meaningful when in MIPS 16 mode. Traditional
687 MIPS assemblers do not support this directive.
690 @section Directive to mark data as an instruction
693 The @code{.insn} directive tells @code{@value{AS}} that the following
694 data is actually instructions. This makes a difference in MIPS 16 and
695 microMIPS modes: when loading the address of a label which precedes
696 instructions, @code{@value{AS}} automatically adds 1 to the value, so
697 that jumping to the loaded address will do the right thing.
699 @kindex @code{.global}
700 The @code{.global} and @code{.globl} directives supported by
701 @code{@value{AS}} will by default mark the symbol as pointing to a
702 region of data not code. This means that, for example, any
703 instructions following such a symbol will not be disassembled by
704 @code{objdump} as it will regard them as data. To change this
705 behaviour an optional section name can be placed after the symbol name
706 in the @code{.global} directive. If this section exists and is known
707 to be a code section, then the symbol will be marked as poiting at
708 code not data. Ie the syntax for the directive is:
710 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
712 Here is a short example:
715 .global foo .text, bar, baz .data
725 @node MIPS Option Stack
726 @section Directives to save and restore options
728 @cindex MIPS option stack
729 @kindex @code{.set push}
730 @kindex @code{.set pop}
731 The directives @code{.set push} and @code{.set pop} may be used to save
732 and restore the current settings for all the options which are
733 controlled by @code{.set}. The @code{.set push} directive saves the
734 current settings on a stack. The @code{.set pop} directive pops the
735 stack and restores the settings.
737 These directives can be useful inside an macro which must change an
738 option such as the ISA level or instruction reordering but does not want
739 to change the state of the code which invoked the macro.
741 Traditional MIPS assemblers do not support these directives.
743 @node MIPS ASE Instruction Generation Overrides
744 @section Directives to control generation of MIPS ASE instructions
746 @cindex MIPS MIPS-3D instruction generation override
747 @kindex @code{.set mips3d}
748 @kindex @code{.set nomips3d}
749 The directive @code{.set mips3d} makes the assembler accept instructions
750 from the MIPS-3D Application Specific Extension from that point on
751 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
752 instructions from being accepted.
754 @cindex SmartMIPS instruction generation override
755 @kindex @code{.set smartmips}
756 @kindex @code{.set nosmartmips}
757 The directive @code{.set smartmips} makes the assembler accept
758 instructions from the SmartMIPS Application Specific Extension to the
759 MIPS32 ISA from that point on in the assembly. The
760 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
763 @cindex MIPS MDMX instruction generation override
764 @kindex @code{.set mdmx}
765 @kindex @code{.set nomdmx}
766 The directive @code{.set mdmx} makes the assembler accept instructions
767 from the MDMX Application Specific Extension from that point on
768 in the assembly. The @code{.set nomdmx} directive prevents MDMX
769 instructions from being accepted.
771 @cindex MIPS DSP Release 1 instruction generation override
772 @kindex @code{.set dsp}
773 @kindex @code{.set nodsp}
774 The directive @code{.set dsp} makes the assembler accept instructions
775 from the DSP Release 1 Application Specific Extension from that point
776 on in the assembly. The @code{.set nodsp} directive prevents DSP
777 Release 1 instructions from being accepted.
779 @cindex MIPS DSP Release 2 instruction generation override
780 @kindex @code{.set dspr2}
781 @kindex @code{.set nodspr2}
782 The directive @code{.set dspr2} makes the assembler accept instructions
783 from the DSP Release 2 Application Specific Extension from that point
784 on in the assembly. This dirctive implies @code{.set dsp}. The
785 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
788 @cindex MIPS MT instruction generation override
789 @kindex @code{.set mt}
790 @kindex @code{.set nomt}
791 The directive @code{.set mt} makes the assembler accept instructions
792 from the MT Application Specific Extension from that point on
793 in the assembly. The @code{.set nomt} directive prevents MT
794 instructions from being accepted.
796 @cindex MIPS MCU instruction generation override
797 @kindex @code{.set mcu}
798 @kindex @code{.set nomcu}
799 The directive @code{.set mcu} makes the assembler accept instructions
800 from the MCU Application Specific Extension from that point on
801 in the assembly. The @code{.set nomcu} directive prevents MCU
802 instructions from being accepted.
804 @cindex Virtualization instruction generation override
805 @kindex @code{.set virt}
806 @kindex @code{.set novirt}
807 The directive @code{.set virt} makes the assembler accept instructions
808 from the Virtualization Application Specific Extension from that point
809 on in the assembly. The @code{.set novirt} directive prevents Virtualization
810 instructions from being accepted.
812 Traditional MIPS assemblers do not support these directives.
814 @node MIPS Floating-Point
815 @section Directives to override floating-point options
817 @cindex Disable floating-point instructions
818 @kindex @code{.set softfloat}
819 @kindex @code{.set hardfloat}
820 The directives @code{.set softfloat} and @code{.set hardfloat} provide
821 finer control of disabling and enabling float-point instructions.
822 These directives always override the default (that hard-float
823 instructions are accepted) or the command-line options
824 (@samp{-msoft-float} and @samp{-mhard-float}).
826 @cindex Disable single-precision floating-point operations
827 @kindex @code{.set singlefloat}
828 @kindex @code{.set doublefloat}
829 The directives @code{.set singlefloat} and @code{.set doublefloat}
830 provide finer control of disabling and enabling double-precision
831 float-point operations. These directives always override the default
832 (that double-precision operations are accepted) or the command-line
833 options (@samp{-msingle-float} and @samp{-mdouble-float}).
835 Traditional MIPS assemblers do not support these directives.
838 @section Syntactical considerations for the MIPS assembler
840 * MIPS-Chars:: Special Characters
844 @subsection Special Characters
846 @cindex line comment character, MIPS
847 @cindex MIPS line comment character
848 The presence of a @samp{#} on a line indicates the start of a comment
849 that extends to the end of the current line.
851 If a @samp{#} appears as the first character of a line, the whole line
852 is treated as a comment, but in this case the line can also be a
853 logical line number directive (@pxref{Comments}) or a
854 preprocessor control command (@pxref{Preprocessing}).
856 @cindex line separator, MIPS
857 @cindex statement separator, MIPS
858 @cindex MIPS line separator
859 The @samp{;} character can be used to separate statements on the same