1 @c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
16 different @sc{mips} processors, and MIPS ISA levels I through IV. For
17 information about the @sc{mips} instruction set, see @cite{MIPS RISC
18 Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
19 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
20 Programming'' in the same work.
23 * MIPS Opts:: Assembler options
24 * MIPS Object:: ECOFF object code
25 * MIPS Stabs:: Directives for debugging information
26 * MIPS ISA:: Directives to override the ISA level
27 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
28 * MIPS insn:: Directive to mark data as an instruction
29 * MIPS option stack:: Directives to save and restore options
33 @section Assembler options
35 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
39 @cindex @code{-G} option (MIPS)
41 This option sets the largest size of an object that can be referenced
42 implicitly with the @code{gp} register. It is only accepted for targets
43 that use @sc{ecoff} format. The default value is 8.
45 @cindex @code{-EB} option (MIPS)
46 @cindex @code{-EL} option (MIPS)
47 @cindex MIPS big-endian output
48 @cindex MIPS little-endian output
49 @cindex big-endian output, MIPS
50 @cindex little-endian output, MIPS
53 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
54 little-endian output at run time (unlike the other @sc{gnu} development
55 tools, which must be configured for one or the other). Use @samp{-EB}
56 to select big-endian output, and @samp{-EL} for little-endian.
58 @cindex MIPS architecture options
63 Generate code for a particular MIPS Instruction Set Architecture level.
64 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
65 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
66 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
67 @sc{r10000} processors. You can also switch instruction sets during the
68 assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
72 Generate code for the MIPS 16 processor. This is equivalent to putting
73 @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
74 turns off this option.
78 Cause nops to be inserted if the read of the destination register
79 of an mfhi or mflo instruction occurs in the following two instructions.
83 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
84 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
85 etc.), and to not schedule @samp{nop} instructions around accesses to
86 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
91 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
92 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
93 instructions around accesses to the @samp{HI} and @samp{LO} registers.
94 @samp{-no-m4650} turns off this option.
100 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
101 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
102 specific to that chip, and to schedule for that chip's hazards.
104 @item -mcpu=@var{cpu}
105 Generate code for a particular MIPS cpu. It is exactly equivalent to
106 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
107 understood. Valid @var{cpu} value are:
128 @cindex @code{-nocpp} ignored (MIPS)
130 This option is ignored. It is accepted for command-line compatibility with
131 other assemblers, which use it to turn off C style preprocessing. With
132 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
133 @sc{gnu} assembler itself never runs the C preprocessor.
137 @c FIXME! (1) reflect these options (next item too) in option summaries;
138 @c (2) stop teasing, say _which_ instructions expanded _how_.
139 @code{@value{AS}} automatically macro expands certain division and
140 multiplication instructions to check for overflow and division by zero. This
141 option causes @code{@value{AS}} to generate code to take a trap exception
142 rather than a break exception when an error is detected. The trap instructions
143 are only supported at Instruction Set Architecture level 2 and higher.
147 Generate code to take a break exception rather than a trap exception when an
148 error is detected. This is the default.
152 @section MIPS ECOFF object code
154 @cindex ECOFF sections
155 @cindex MIPS ECOFF sections
156 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
157 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
158 additional sections are @code{.rdata}, used for read-only data,
159 @code{.sdata}, used for small data, and @code{.sbss}, used for small
162 @cindex small objects, MIPS ECOFF
163 @cindex @code{gp} register, MIPS
164 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
165 register to form the address of a ``small object''. Any object in the
166 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
167 For external objects, or for objects in the @code{.bss} section, you can use
168 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
169 @code{$gp}; the default value is 8, meaning that a reference to any object
170 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
171 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
172 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
173 or @code{sbss} in any case). The size of an object in the @code{.bss} section
174 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
175 size of an external object may be set with the @code{.extern} directive. For
176 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
177 in length, whie leaving @code{sym} otherwise undefined.
179 Using small @sc{ecoff} objects requires linker support, and assumes that the
180 @code{$gp} register is correctly initialized (normally done automatically by
181 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
185 @section Directives for debugging information
187 @cindex MIPS debugging directives
188 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
189 generating debugging information which are not support by traditional @sc{mips}
190 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
191 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
192 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
193 generated by the three @code{.stab} directives can only be read by @sc{gdb},
194 not by traditional @sc{mips} debuggers (this enhancement is required to fully
195 support C++ debugging). These directives are primarily used by compilers, not
196 assembly language programmers!
199 @section Directives to override the ISA level
201 @cindex MIPS ISA override
202 @kindex @code{.set mips@var{n}}
203 @sc{gnu} @code{@value{AS}} supports an additional directive to change
204 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
205 mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1
206 to 4 makes the assembler accept instructions for the corresponding
207 @sc{isa} level, from that point on in the assembly. @code{.set
208 mips@var{n}} affects not only which instructions are permitted, but also
209 how certain macros are expanded. @code{.set mips0} restores the
210 @sc{isa} level to its original level: either the level you selected with
211 command line options, or the default for your configuration. You can
212 use this feature to permit specific @sc{r4000} instructions while
213 assembling in 32 bit mode. Use this directive with care!
215 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
216 in which it will assemble instructions for the MIPS 16 processor. Use
217 @samp{.set nomips16} to return to normal 32 bit mode.
219 Traditional @sc{mips} assemblers do not support this directive.
221 @node MIPS autoextend
222 @section Directives for extending MIPS 16 bit instructions
224 @kindex @code{.set autoextend}
225 @kindex @code{.set noautoextend}
226 By default, MIPS 16 instructions are automatically extended to 32 bits
227 when necessary. The directive @samp{.set noautoextend} will turn this
228 off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
229 must be explicitly extended with the @samp{.e} modifier (e.g.,
230 @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
231 to once again automatically extend instructions when necessary.
233 This directive is only meaningful when in MIPS 16 mode. Traditional
234 @sc{mips} assemblers do not support this directive.
237 @section Directive to mark data as an instruction
240 The @code{.insn} directive tells @code{@value{AS}} that the following
241 data is actually instructions. This makes a difference in MIPS 16 mode:
242 when loading the address of a label which precedes instructions,
243 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
244 the loaded address will do the right thing.
246 @node MIPS option stack
247 @section Directives to save and restore options
249 @cindex MIPS option stack
250 @kindex @code{.set push}
251 @kindex @code{.set pop}
252 The directives @code{.set push} and @code{.set pop} may be used to save
253 and restore the current settings for all the options which are
254 controlled by @code{.set}. The @code{.set push} directive saves the
255 current settings on a stack. The @code{.set pop} directive pops the
256 stack and restores the settings.
258 These directives can be useful inside an macro which must change an
259 option such as the ISA level or instruction reordering but does not want
260 to change the state of the code which invoked the macro.
262 Traditional @sc{mips} assemblers do not support these directives.