1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
18 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the MIPS instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of MIPS assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Options:: Assembler options
26 * MIPS Macros:: High-level assembly macros
27 * MIPS Symbol Sizes:: Directives to override the size of symbols
28 * MIPS Small Data:: Controlling the use of small data accesses
29 * MIPS ISA:: Directives to override the ISA level
30 * MIPS assembly options:: Directives to control code generation
31 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
32 * MIPS insn:: Directive to mark data as an instruction
33 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
34 * MIPS Option Stack:: Directives to save and restore options
35 * MIPS ASE Instruction Generation Overrides:: Directives to control
36 generation of MIPS ASE instructions
37 * MIPS Floating-Point:: Directives to override floating-point options
38 * MIPS Syntax:: MIPS specific syntactical considerations
42 @section Assembler options
44 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
48 @cindex @code{-G} option (MIPS)
50 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
51 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
53 @cindex @code{-EB} option (MIPS)
54 @cindex @code{-EL} option (MIPS)
55 @cindex MIPS big-endian output
56 @cindex MIPS little-endian output
57 @cindex big-endian output, MIPS
58 @cindex little-endian output, MIPS
61 Any MIPS configuration of @code{@value{AS}} can select big-endian or
62 little-endian output at run time (unlike the other @sc{gnu} development
63 tools, which must be configured for one or the other). Use @samp{-EB}
64 to select big-endian output, and @samp{-EL} for little-endian.
67 @cindex PIC selection, MIPS
68 @cindex @option{-KPIC} option, MIPS
69 Generate SVR4-style PIC. This option tells the assembler to generate
70 SVR4-style position-independent macro expansions. It also tells the
71 assembler to mark the output file as PIC.
74 @cindex @option{-mvxworks-pic} option, MIPS
75 Generate VxWorks PIC. This option tells the assembler to generate
76 VxWorks-style position-independent macro expansions.
78 @cindex MIPS architecture options
88 Generate code for a particular MIPS Instruction Set Architecture level.
89 @samp{-mips1} corresponds to the R2000 and R3000 processors,
90 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
91 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
92 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
93 @samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
94 MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also
95 switch instruction sets during the assembly; see @ref{MIPS ISA,
96 Directives to override the ISA level}.
100 Some macros have different expansions for 32-bit and 64-bit registers.
101 The register sizes are normally inferred from the ISA and ABI, but these
102 flags force a certain group of registers to be treated as 32 bits wide at
103 all times. @samp{-mgp32} controls the size of general-purpose registers
104 and @samp{-mfp32} controls the size of floating-point registers.
106 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
107 of registers to be changed for parts of an object. The default value is
108 restored by @code{.set gp=default} and @code{.set fp=default}.
110 On some MIPS variants there is a 32-bit mode flag; when this flag is
111 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
112 save the 32-bit registers on a context switch, so it is essential never
113 to use the 64-bit registers.
117 Assume that 64-bit registers are available. This is provided in the
118 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
120 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
121 of registers to be changed for parts of an object. The default value is
122 restored by @code{.set gp=default} and @code{.set fp=default}.
126 Generate code for the MIPS 16 processor. This is equivalent to putting
127 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
128 turns off this option.
131 @itemx -mno-micromips
132 Generate code for the microMIPS processor. This is equivalent to putting
133 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
134 turns off this option. This is equivalent to putting @code{.set nomicromips}
135 at the start of the assembly file.
138 @itemx -mno-smartmips
139 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
140 provides a number of new instructions which target smartcard and
141 cryptographic applications. This is equivalent to putting
142 @code{.set smartmips} at the start of the assembly file.
143 @samp{-mno-smartmips} turns off this option.
147 Generate code for the MIPS-3D Application Specific Extension.
148 This tells the assembler to accept MIPS-3D instructions.
149 @samp{-no-mips3d} turns off this option.
153 Generate code for the MDMX Application Specific Extension.
154 This tells the assembler to accept MDMX instructions.
155 @samp{-no-mdmx} turns off this option.
159 Generate code for the DSP Release 1 Application Specific Extension.
160 This tells the assembler to accept DSP Release 1 instructions.
161 @samp{-mno-dsp} turns off this option.
165 Generate code for the DSP Release 2 Application Specific Extension.
166 This option implies -mdsp.
167 This tells the assembler to accept DSP Release 2 instructions.
168 @samp{-mno-dspr2} turns off this option.
172 Generate code for the MT Application Specific Extension.
173 This tells the assembler to accept MT instructions.
174 @samp{-mno-mt} turns off this option.
178 Generate code for the MCU Application Specific Extension.
179 This tells the assembler to accept MCU instructions.
180 @samp{-mno-mcu} turns off this option.
184 Generate code for the MIPS SIMD Architecture Extension.
185 This tells the assembler to accept MSA instructions.
186 @samp{-mno-msa} turns off this option.
190 Generate code for the Virtualization Application Specific Extension.
191 This tells the assembler to accept Virtualization instructions.
192 @samp{-mno-virt} turns off this option.
196 Only use 32-bit instruction encodings when generating code for the
197 microMIPS processor. This option inhibits the use of any 16-bit
198 instructions. This is equivalent to putting @code{.set insn32} at
199 the start of the assembly file. @samp{-mno-insn32} turns off this
200 option. This is equivalent to putting @code{.set noinsn32} at the
201 start of the assembly file. By default @samp{-mno-insn32} is
202 selected, allowing all instructions to be used.
206 Cause nops to be inserted if the read of the destination register
207 of an mfhi or mflo instruction occurs in the following two instructions.
209 @item -mfix-loongson2f-jump
210 @itemx -mno-fix-loongson2f-jump
211 Eliminate instruction fetch from outside 256M region to work around the
212 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
213 the kernel may crash. The issue has been solved in latest processor
214 batches, but this fix has no side effect to them.
216 @item -mfix-loongson2f-nop
217 @itemx -mno-fix-loongson2f-nop
218 Replace nops by @code{or at,at,zero} to work around the Loongson2F
219 @samp{nop} errata. Without it, under extreme cases, the CPU might
220 deadlock. The issue has been solved in later Loongson2F batches, but
221 this fix has no side effect to them.
224 @itemx -mno-fix-vr4120
225 Insert nops to work around certain VR4120 errata. This option is
226 intended to be used on GCC-generated code: it is not designed to catch
227 all problems in hand-written assembler code.
230 @itemx -mno-fix-vr4130
231 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
235 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
238 @itemx -mno-fix-cn63xxp1
239 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
240 certain CN63XXP1 errata.
244 Generate code for the LSI R4010 chip. This tells the assembler to
245 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
246 etc.), and to not schedule @samp{nop} instructions around accesses to
247 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
252 Generate code for the MIPS R4650 chip. This tells the assembler to accept
253 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
254 instructions around accesses to the @samp{HI} and @samp{LO} registers.
255 @samp{-no-m4650} turns off this option.
261 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
262 R@var{nnnn} chip. This tells the assembler to accept instructions
263 specific to that chip, and to schedule for that chip's hazards.
265 @item -march=@var{cpu}
266 Generate code for a particular MIPS CPU. It is exactly equivalent to
267 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
268 understood. Valid @var{cpu} value are:
353 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
354 accepted as synonyms for @samp{@var{n}f1_1}. These values are
357 @item -mtune=@var{cpu}
358 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
359 identical to @samp{-march=@var{cpu}}.
361 @item -mabi=@var{abi}
362 Record which ABI the source code uses. The recognized arguments
363 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
369 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
370 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
372 @cindex @code{-nocpp} ignored (MIPS)
374 This option is ignored. It is accepted for command-line compatibility with
375 other assemblers, which use it to turn off C style preprocessing. With
376 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
377 @sc{gnu} assembler itself never runs the C preprocessor.
381 Disable or enable floating-point instructions. Note that by default
382 floating-point instructions are always allowed even with CPU targets
383 that don't have support for these instructions.
386 @itemx -mdouble-float
387 Disable or enable double-precision floating-point operations. Note
388 that by default double-precision floating-point operations are always
389 allowed even with CPU targets that don't have support for these
392 @item --construct-floats
393 @itemx --no-construct-floats
394 The @code{--no-construct-floats} option disables the construction of
395 double width floating point constants by loading the two halves of the
396 value into the two single width floating point registers that make up
397 the double width register. This feature is useful if the processor
398 support the FR bit in its status register, and this bit is known (by
399 the programmer) to be set. This bit prevents the aliasing of the double
400 width register by the single width registers.
402 By default @code{--construct-floats} is selected, allowing construction
403 of these floating point constants.
406 @itemx --no-relax-branch
407 The @samp{--relax-branch} option enables the relaxation of out-of-range
408 branches. Any branches whose target cannot be reached directly are
409 converted to a small instruction sequence including an inverse-condition
410 branch to the physically next instruction, and a jump to the original
411 target is inserted between the two instructions. In PIC code the jump
412 will involve further instructions for address calculation.
414 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
415 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
416 relaxation, because they have no complementing counterparts. They could
417 be relaxed with the use of a longer sequence involving another branch,
418 however this has not been implemented and if their target turns out of
419 reach, they produce an error even if branch relaxation is enabled.
421 Also no MIPS16 branches are ever relaxed.
423 By default @samp{--no-relax-branch} is selected, causing any out-of-range
424 branches to produce an error.
426 @cindex @option{-mnan=} command line option, MIPS
427 @item -mnan=@var{encoding}
428 This option indicates whether the source code uses the IEEE 2008
429 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
430 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
431 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
433 @option{-mnan=legacy} is the default if no @option{-mnan} option or
434 @code{.nan} directive is used.
438 @c FIXME! (1) reflect these options (next item too) in option summaries;
439 @c (2) stop teasing, say _which_ instructions expanded _how_.
440 @code{@value{AS}} automatically macro expands certain division and
441 multiplication instructions to check for overflow and division by zero. This
442 option causes @code{@value{AS}} to generate code to take a trap exception
443 rather than a break exception when an error is detected. The trap instructions
444 are only supported at Instruction Set Architecture level 2 and higher.
448 Generate code to take a break exception rather than a trap exception when an
449 error is detected. This is the default.
453 Control generation of @code{.pdr} sections. Off by default on IRIX, on
458 When generating code using the Unix calling conventions (selected by
459 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
460 which can go into a shared library. The @samp{-mno-shared} option
461 tells gas to generate code which uses the calling convention, but can
462 not go into a shared library. The resulting code is slightly more
463 efficient. This option only affects the handling of the
464 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
468 @section High-level assembly macros
470 MIPS assemblers have traditionally provided a wider range of
471 instructions than the MIPS architecture itself. These extra
472 instructions are usually referred to as ``macro'' instructions
473 @footnote{The term ``macro'' is somewhat overloaded here, since
474 these macros have no relation to those defined by @code{.macro},
475 @pxref{Macro,, @code{.macro}}.}.
477 Some MIPS macro instructions extend an underlying architectural instruction
478 while others are entirely new. An example of the former type is @code{and},
479 which allows the third operand to be either a register or an arbitrary
480 immediate value. Examples of the latter type include @code{bgt}, which
481 branches to the third operand when the first operand is greater than
482 the second operand, and @code{ulh}, which implements an unaligned
485 One of the most common extensions provided by macros is to expand
486 memory offsets to the full address range (32 or 64 bits) and to allow
487 symbolic offsets such as @samp{my_data + 4} to be used in place of
488 integer constants. For example, the architectural instruction
489 @code{lbu} allows only a signed 16-bit offset, whereas the macro
490 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
491 The implementation of these symbolic offsets depends on several factors,
492 such as whether the assembler is generating SVR4-style PIC (selected by
493 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
494 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
495 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
496 of small data accesses}).
498 @kindex @code{.set macro}
499 @kindex @code{.set nomacro}
500 Sometimes it is undesirable to have one assembly instruction expand
501 to several machine instructions. The directive @code{.set nomacro}
502 tells the assembler to warn when this happens. @code{.set macro}
503 restores the default behavior.
505 @cindex @code{at} register, MIPS
506 @kindex @code{.set at=@var{reg}}
507 Some macro instructions need a temporary register to store intermediate
508 results. This register is usually @code{$1}, also known as @code{$at},
509 but it can be changed to any core register @var{reg} using
510 @code{.set at=@var{reg}}. Note that @code{$at} always refers
511 to @code{$1} regardless of which register is being used as the
514 @kindex @code{.set at}
515 @kindex @code{.set noat}
516 Implicit uses of the temporary register in macros could interfere with
517 explicit uses in the assembly code. The assembler therefore warns
518 whenever it sees an explicit use of the temporary register. The directive
519 @code{.set noat} silences this warning while @code{.set at} restores
520 the default behavior. It is safe to use @code{.set noat} while
521 @code{.set nomacro} is in effect since single-instruction macros
522 never need a temporary register.
524 Note that while the @sc{gnu} assembler provides these macros for compatibility,
525 it does not make any attempt to optimize them with the surrounding code.
527 @node MIPS Symbol Sizes
528 @section Directives to override the size of symbols
530 @kindex @code{.set sym32}
531 @kindex @code{.set nosym32}
532 The n64 ABI allows symbols to have any 64-bit value. Although this
533 provides a great deal of flexibility, it means that some macros have
534 much longer expansions than their 32-bit counterparts. For example,
535 the non-PIC expansion of @samp{dla $4,sym} is usually:
540 daddiu $4,$4,%higher(sym)
541 daddiu $1,$1,%lo(sym)
546 whereas the 32-bit expansion is simply:
550 daddiu $4,$4,%lo(sym)
553 n64 code is sometimes constructed in such a way that all symbolic
554 constants are known to have 32-bit values, and in such cases, it's
555 preferable to use the 32-bit expansion instead of the 64-bit
558 You can use the @code{.set sym32} directive to tell the assembler
559 that, from this point on, all expressions of the form
560 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
561 have 32-bit values. For example:
570 will cause the assembler to treat @samp{sym}, @code{sym+16} and
571 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
572 addresses is not affected.
574 The directive @code{.set nosym32} ends a @code{.set sym32} block and
575 reverts to the normal behavior. It is also possible to change the
576 symbol size using the command-line options @option{-msym32} and
579 These options and directives are always accepted, but at present,
580 they have no effect for anything other than n64.
582 @node MIPS Small Data
583 @section Controlling the use of small data accesses
585 @c This section deliberately glosses over the possibility of using -G
586 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
587 @cindex small data, MIPS
588 @cindex @code{gp} register, MIPS
589 It often takes several instructions to load the address of a symbol.
590 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
591 of @samp{dla $4,addr} is usually:
595 daddiu $4,$4,%lo(addr)
598 The sequence is much longer when @samp{addr} is a 64-bit symbol.
599 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
601 In order to cut down on this overhead, most embedded MIPS systems
602 set aside a 64-kilobyte ``small data'' area and guarantee that all
603 data of size @var{n} and smaller will be placed in that area.
604 The limit @var{n} is passed to both the assembler and the linker
605 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
606 Assembler options}. Note that the same value of @var{n} must be used
607 when linking and when assembling all input files to the link; any
608 inconsistency could cause a relocation overflow error.
610 The size of an object in the @code{.bss} section is set by the
611 @code{.comm} or @code{.lcomm} directive that defines it. The size of
612 an external object may be set with the @code{.extern} directive. For
613 example, @samp{.extern sym,4} declares that the object at @code{sym}
614 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
616 When no @option{-G} option is given, the default limit is 8 bytes.
617 The option @option{-G 0} prevents any data from being automatically
620 It is also possible to mark specific objects as small by putting them
621 in the special sections @code{.sdata} and @code{.sbss}, which are
622 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
623 The toolchain will treat such data as small regardless of the
626 On startup, systems that support a small data area are expected to
627 initialize register @code{$28}, also known as @code{$gp}, in such a
628 way that small data can be accessed using a 16-bit offset from that
629 register. For example, when @samp{addr} is small data,
630 the @samp{dla $4,addr} instruction above is equivalent to:
633 daddiu $4,$28,%gp_rel(addr)
636 Small data is not supported for SVR4-style PIC.
639 @section Directives to override the ISA level
641 @cindex MIPS ISA override
642 @kindex @code{.set mips@var{n}}
643 @sc{gnu} @code{@value{AS}} supports an additional directive to change
644 the MIPS Instruction Set Architecture level on the fly: @code{.set
645 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
647 The values other than 0 make the assembler accept instructions
648 for the corresponding ISA level, from that point on in the
649 assembly. @code{.set mips@var{n}} affects not only which instructions
650 are permitted, but also how certain macros are expanded. @code{.set
651 mips0} restores the ISA level to its original level: either the
652 level you selected with command line options, or the default for your
653 configuration. You can use this feature to permit specific MIPS III
654 instructions while assembling in 32 bit mode. Use this directive with
657 @cindex MIPS CPU override
658 @kindex @code{.set arch=@var{cpu}}
659 The @code{.set arch=@var{cpu}} directive provides even finer control.
660 It changes the effective CPU target and allows the assembler to use
661 instructions specific to a particular CPU. All CPUs supported by the
662 @samp{-march} command line option are also selectable by this directive.
663 The original value is restored by @code{.set arch=default}.
665 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
666 in which it will assemble instructions for the MIPS 16 processor. Use
667 @code{.set nomips16} to return to normal 32 bit mode.
669 Traditional MIPS assemblers do not support this directive.
671 The directive @code{.set micromips} puts the assembler into microMIPS mode,
672 in which it will assemble instructions for the microMIPS processor. Use
673 @code{.set nomicromips} to return to normal 32 bit mode.
675 Traditional MIPS assemblers do not support this directive.
677 @node MIPS assembly options
678 @section Directives to control code generation
680 @cindex MIPS 32-bit microMIPS instruction generation override
681 @kindex @code{.set insn32}
682 @kindex @code{.set noinsn32}
683 The directive @code{.set insn32} makes the assembler only use 32-bit
684 instruction encodings when generating code for the microMIPS processor.
685 This directive inhibits the use of any 16-bit instructions from that
686 point on in the assembly. The @code{.set noinsn32} directive allows
687 16-bit instructions to be accepted.
689 Traditional MIPS assemblers do not support this directive.
691 @node MIPS autoextend
692 @section Directives for extending MIPS 16 bit instructions
694 @kindex @code{.set autoextend}
695 @kindex @code{.set noautoextend}
696 By default, MIPS 16 instructions are automatically extended to 32 bits
697 when necessary. The directive @code{.set noautoextend} will turn this
698 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
699 must be explicitly extended with the @code{.e} modifier (e.g.,
700 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
701 to once again automatically extend instructions when necessary.
703 This directive is only meaningful when in MIPS 16 mode. Traditional
704 MIPS assemblers do not support this directive.
707 @section Directive to mark data as an instruction
710 The @code{.insn} directive tells @code{@value{AS}} that the following
711 data is actually instructions. This makes a difference in MIPS 16 and
712 microMIPS modes: when loading the address of a label which precedes
713 instructions, @code{@value{AS}} automatically adds 1 to the value, so
714 that jumping to the loaded address will do the right thing.
716 @kindex @code{.global}
717 The @code{.global} and @code{.globl} directives supported by
718 @code{@value{AS}} will by default mark the symbol as pointing to a
719 region of data not code. This means that, for example, any
720 instructions following such a symbol will not be disassembled by
721 @code{objdump} as it will regard them as data. To change this
722 behaviour an optional section name can be placed after the symbol name
723 in the @code{.global} directive. If this section exists and is known
724 to be a code section, then the symbol will be marked as poiting at
725 code not data. Ie the syntax for the directive is:
727 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
729 Here is a short example:
732 .global foo .text, bar, baz .data
742 @node MIPS NaN Encodings
743 @section Directives to record which NaN encoding is being used
745 @cindex MIPS IEEE 754 NaN data encoding selection
746 @cindex @code{.nan} directive, MIPS
747 The IEEE 754 floating-point standard defines two types of not-a-number
748 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
749 of the standard did not specify how these two types should be
750 distinguished. Most implementations followed the i387 model, in which
751 the first bit of the significand is set for quiet NaNs and clear for
752 signalling NaNs. However, the original MIPS implementation assigned the
753 opposite meaning to the bit, so that it was set for signalling NaNs and
754 clear for quiet NaNs.
756 The 2008 revision of the standard formally suggested the i387 choice
757 and as from Sep 2012 the current release of the MIPS architecture
758 therefore optionally supports that form. Code that uses one NaN encoding
759 would usually be incompatible with code that uses the other NaN encoding,
760 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
761 encoding is being used.
763 Assembly files can use the @code{.nan} directive to select between the
764 two encodings. @samp{.nan 2008} says that the assembly file uses the
765 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
766 the original MIPS encoding. If several @code{.nan} directives are given,
767 the final setting is the one that is used.
769 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
770 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
771 respectively. However, any @code{.nan} directive overrides the
772 command-line setting.
774 @samp{.nan legacy} is the default if no @code{.nan} directive or
775 @option{-mnan} option is given.
777 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
778 therefore these directives do not affect code generation. They simply
779 control the setting of the @code{EF_MIPS_NAN2008} flag.
781 Traditional MIPS assemblers do not support these directives.
783 @node MIPS Option Stack
784 @section Directives to save and restore options
786 @cindex MIPS option stack
787 @kindex @code{.set push}
788 @kindex @code{.set pop}
789 The directives @code{.set push} and @code{.set pop} may be used to save
790 and restore the current settings for all the options which are
791 controlled by @code{.set}. The @code{.set push} directive saves the
792 current settings on a stack. The @code{.set pop} directive pops the
793 stack and restores the settings.
795 These directives can be useful inside an macro which must change an
796 option such as the ISA level or instruction reordering but does not want
797 to change the state of the code which invoked the macro.
799 Traditional MIPS assemblers do not support these directives.
801 @node MIPS ASE Instruction Generation Overrides
802 @section Directives to control generation of MIPS ASE instructions
804 @cindex MIPS MIPS-3D instruction generation override
805 @kindex @code{.set mips3d}
806 @kindex @code{.set nomips3d}
807 The directive @code{.set mips3d} makes the assembler accept instructions
808 from the MIPS-3D Application Specific Extension from that point on
809 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
810 instructions from being accepted.
812 @cindex SmartMIPS instruction generation override
813 @kindex @code{.set smartmips}
814 @kindex @code{.set nosmartmips}
815 The directive @code{.set smartmips} makes the assembler accept
816 instructions from the SmartMIPS Application Specific Extension to the
817 MIPS32 ISA from that point on in the assembly. The
818 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
821 @cindex MIPS MDMX instruction generation override
822 @kindex @code{.set mdmx}
823 @kindex @code{.set nomdmx}
824 The directive @code{.set mdmx} makes the assembler accept instructions
825 from the MDMX Application Specific Extension from that point on
826 in the assembly. The @code{.set nomdmx} directive prevents MDMX
827 instructions from being accepted.
829 @cindex MIPS DSP Release 1 instruction generation override
830 @kindex @code{.set dsp}
831 @kindex @code{.set nodsp}
832 The directive @code{.set dsp} makes the assembler accept instructions
833 from the DSP Release 1 Application Specific Extension from that point
834 on in the assembly. The @code{.set nodsp} directive prevents DSP
835 Release 1 instructions from being accepted.
837 @cindex MIPS DSP Release 2 instruction generation override
838 @kindex @code{.set dspr2}
839 @kindex @code{.set nodspr2}
840 The directive @code{.set dspr2} makes the assembler accept instructions
841 from the DSP Release 2 Application Specific Extension from that point
842 on in the assembly. This dirctive implies @code{.set dsp}. The
843 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
846 @cindex MIPS MT instruction generation override
847 @kindex @code{.set mt}
848 @kindex @code{.set nomt}
849 The directive @code{.set mt} makes the assembler accept instructions
850 from the MT Application Specific Extension from that point on
851 in the assembly. The @code{.set nomt} directive prevents MT
852 instructions from being accepted.
854 @cindex MIPS MCU instruction generation override
855 @kindex @code{.set mcu}
856 @kindex @code{.set nomcu}
857 The directive @code{.set mcu} makes the assembler accept instructions
858 from the MCU Application Specific Extension from that point on
859 in the assembly. The @code{.set nomcu} directive prevents MCU
860 instructions from being accepted.
862 @cindex MIPS SIMD Architecture instruction generation override
863 @kindex @code{.set msa}
864 @kindex @code{.set nomsa}
865 The directive @code{.set msa} makes the assembler accept instructions
866 from the MIPS SIMD Architecture Extension from that point on
867 in the assembly. The @code{.set nomsa} directive prevents MSA
868 instructions from being accepted.
870 @cindex Virtualization instruction generation override
871 @kindex @code{.set virt}
872 @kindex @code{.set novirt}
873 The directive @code{.set virt} makes the assembler accept instructions
874 from the Virtualization Application Specific Extension from that point
875 on in the assembly. The @code{.set novirt} directive prevents Virtualization
876 instructions from being accepted.
878 Traditional MIPS assemblers do not support these directives.
880 @node MIPS Floating-Point
881 @section Directives to override floating-point options
883 @cindex Disable floating-point instructions
884 @kindex @code{.set softfloat}
885 @kindex @code{.set hardfloat}
886 The directives @code{.set softfloat} and @code{.set hardfloat} provide
887 finer control of disabling and enabling float-point instructions.
888 These directives always override the default (that hard-float
889 instructions are accepted) or the command-line options
890 (@samp{-msoft-float} and @samp{-mhard-float}).
892 @cindex Disable single-precision floating-point operations
893 @kindex @code{.set singlefloat}
894 @kindex @code{.set doublefloat}
895 The directives @code{.set singlefloat} and @code{.set doublefloat}
896 provide finer control of disabling and enabling double-precision
897 float-point operations. These directives always override the default
898 (that double-precision operations are accepted) or the command-line
899 options (@samp{-msingle-float} and @samp{-mdouble-float}).
901 Traditional MIPS assemblers do not support these directives.
904 @section Syntactical considerations for the MIPS assembler
906 * MIPS-Chars:: Special Characters
910 @subsection Special Characters
912 @cindex line comment character, MIPS
913 @cindex MIPS line comment character
914 The presence of a @samp{#} on a line indicates the start of a comment
915 that extends to the end of the current line.
917 If a @samp{#} appears as the first character of a line, the whole line
918 is treated as a comment, but in this case the line can also be a
919 logical line number directive (@pxref{Comments}) or a
920 preprocessor control command (@pxref{Preprocessing}).
922 @cindex line separator, MIPS
923 @cindex statement separator, MIPS
924 @cindex MIPS line separator
925 The @samp{;} character can be used to separate statements on the same