1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
32 * MIPS Option Stack:: Directives to save and restore options
33 * MIPS ASE Instruction Generation Overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS Floating-Point:: Directives to override floating-point options
36 * MIPS Syntax:: MIPS specific syntactical considerations
40 @section Assembler options
42 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
46 @cindex @code{-G} option (MIPS)
48 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
49 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
51 @cindex @code{-EB} option (MIPS)
52 @cindex @code{-EL} option (MIPS)
53 @cindex MIPS big-endian output
54 @cindex MIPS little-endian output
55 @cindex big-endian output, MIPS
56 @cindex little-endian output, MIPS
59 Any MIPS configuration of @code{@value{AS}} can select big-endian or
60 little-endian output at run time (unlike the other @sc{gnu} development
61 tools, which must be configured for one or the other). Use @samp{-EB}
62 to select big-endian output, and @samp{-EL} for little-endian.
65 @cindex PIC selection, MIPS
66 @cindex @option{-KPIC} option, MIPS
67 Generate SVR4-style PIC. This option tells the assembler to generate
68 SVR4-style position-independent macro expansions. It also tells the
69 assembler to mark the output file as PIC.
72 @cindex @option{-mvxworks-pic} option, MIPS
73 Generate VxWorks PIC. This option tells the assembler to generate
74 VxWorks-style position-independent macro expansions.
76 @cindex MIPS architecture options
86 Generate code for a particular MIPS Instruction Set Architecture level.
87 @samp{-mips1} corresponds to the R2000 and R3000 processors,
88 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
89 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
90 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
91 @samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
92 MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also
93 switch instruction sets during the assembly; see @ref{MIPS ISA,
94 Directives to override the ISA level}.
98 Some macros have different expansions for 32-bit and 64-bit registers.
99 The register sizes are normally inferred from the ISA and ABI, but these
100 flags force a certain group of registers to be treated as 32 bits wide at
101 all times. @samp{-mgp32} controls the size of general-purpose registers
102 and @samp{-mfp32} controls the size of floating-point registers.
104 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
105 of registers to be changed for parts of an object. The default value is
106 restored by @code{.set gp=default} and @code{.set fp=default}.
108 On some MIPS variants there is a 32-bit mode flag; when this flag is
109 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
110 save the 32-bit registers on a context switch, so it is essential never
111 to use the 64-bit registers.
115 Assume that 64-bit registers are available. This is provided in the
116 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
118 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
119 of registers to be changed for parts of an object. The default value is
120 restored by @code{.set gp=default} and @code{.set fp=default}.
124 Generate code for the MIPS 16 processor. This is equivalent to putting
125 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
126 turns off this option.
129 @itemx -mno-micromips
130 Generate code for the microMIPS processor. This is equivalent to putting
131 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
132 turns off this option. This is equivalent to putting @code{.set nomicromips}
133 at the start of the assembly file.
136 @itemx -mno-smartmips
137 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
138 provides a number of new instructions which target smartcard and
139 cryptographic applications. This is equivalent to putting
140 @code{.set smartmips} at the start of the assembly file.
141 @samp{-mno-smartmips} turns off this option.
145 Generate code for the MIPS-3D Application Specific Extension.
146 This tells the assembler to accept MIPS-3D instructions.
147 @samp{-no-mips3d} turns off this option.
151 Generate code for the MDMX Application Specific Extension.
152 This tells the assembler to accept MDMX instructions.
153 @samp{-no-mdmx} turns off this option.
157 Generate code for the DSP Release 1 Application Specific Extension.
158 This tells the assembler to accept DSP Release 1 instructions.
159 @samp{-mno-dsp} turns off this option.
163 Generate code for the DSP Release 2 Application Specific Extension.
164 This option implies -mdsp.
165 This tells the assembler to accept DSP Release 2 instructions.
166 @samp{-mno-dspr2} turns off this option.
170 Generate code for the MT Application Specific Extension.
171 This tells the assembler to accept MT instructions.
172 @samp{-mno-mt} turns off this option.
176 Generate code for the MCU Application Specific Extension.
177 This tells the assembler to accept MCU instructions.
178 @samp{-mno-mcu} turns off this option.
182 Generate code for the MIPS SIMD Architecture Extension.
183 This tells the assembler to accept MSA instructions.
184 @samp{-mno-msa} turns off this option.
188 Generate code for the Virtualization Application Specific Extension.
189 This tells the assembler to accept Virtualization instructions.
190 @samp{-mno-virt} turns off this option.
194 Only use 32-bit instruction encodings when generating code for the
195 microMIPS processor. This option inhibits the use of any 16-bit
196 instructions. This is equivalent to putting @code{.set insn32} at
197 the start of the assembly file. @samp{-mno-insn32} turns off this
198 option. This is equivalent to putting @code{.set noinsn32} at the
199 start of the assembly file. By default @samp{-mno-insn32} is
200 selected, allowing all instructions to be used.
204 Cause nops to be inserted if the read of the destination register
205 of an mfhi or mflo instruction occurs in the following two instructions.
208 @itemx -mno-fix-rm7000
209 Cause nops to be inserted if a dmult or dmultu instruction is
210 followed by a load instruction.
212 @item -mfix-loongson2f-jump
213 @itemx -mno-fix-loongson2f-jump
214 Eliminate instruction fetch from outside 256M region to work around the
215 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
216 the kernel may crash. The issue has been solved in latest processor
217 batches, but this fix has no side effect to them.
219 @item -mfix-loongson2f-nop
220 @itemx -mno-fix-loongson2f-nop
221 Replace nops by @code{or at,at,zero} to work around the Loongson2F
222 @samp{nop} errata. Without it, under extreme cases, the CPU might
223 deadlock. The issue has been solved in later Loongson2F batches, but
224 this fix has no side effect to them.
227 @itemx -mno-fix-vr4120
228 Insert nops to work around certain VR4120 errata. This option is
229 intended to be used on GCC-generated code: it is not designed to catch
230 all problems in hand-written assembler code.
233 @itemx -mno-fix-vr4130
234 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
238 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
241 @itemx -mno-fix-cn63xxp1
242 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
243 certain CN63XXP1 errata.
247 Generate code for the LSI R4010 chip. This tells the assembler to
248 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
249 etc.), and to not schedule @samp{nop} instructions around accesses to
250 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
255 Generate code for the MIPS R4650 chip. This tells the assembler to accept
256 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
257 instructions around accesses to the @samp{HI} and @samp{LO} registers.
258 @samp{-no-m4650} turns off this option.
264 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
265 R@var{nnnn} chip. This tells the assembler to accept instructions
266 specific to that chip, and to schedule for that chip's hazards.
268 @item -march=@var{cpu}
269 Generate code for a particular MIPS CPU. It is exactly equivalent to
270 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
271 understood. Valid @var{cpu} value are:
356 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
357 accepted as synonyms for @samp{@var{n}f1_1}. These values are
360 @item -mtune=@var{cpu}
361 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
362 identical to @samp{-march=@var{cpu}}.
364 @item -mabi=@var{abi}
365 Record which ABI the source code uses. The recognized arguments
366 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
372 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
373 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
375 @cindex @code{-nocpp} ignored (MIPS)
377 This option is ignored. It is accepted for command-line compatibility with
378 other assemblers, which use it to turn off C style preprocessing. With
379 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
380 @sc{gnu} assembler itself never runs the C preprocessor.
384 Disable or enable floating-point instructions. Note that by default
385 floating-point instructions are always allowed even with CPU targets
386 that don't have support for these instructions.
389 @itemx -mdouble-float
390 Disable or enable double-precision floating-point operations. Note
391 that by default double-precision floating-point operations are always
392 allowed even with CPU targets that don't have support for these
395 @item --construct-floats
396 @itemx --no-construct-floats
397 The @code{--no-construct-floats} option disables the construction of
398 double width floating point constants by loading the two halves of the
399 value into the two single width floating point registers that make up
400 the double width register. This feature is useful if the processor
401 support the FR bit in its status register, and this bit is known (by
402 the programmer) to be set. This bit prevents the aliasing of the double
403 width register by the single width registers.
405 By default @code{--construct-floats} is selected, allowing construction
406 of these floating point constants.
409 @itemx --no-relax-branch
410 The @samp{--relax-branch} option enables the relaxation of out-of-range
411 branches. Any branches whose target cannot be reached directly are
412 converted to a small instruction sequence including an inverse-condition
413 branch to the physically next instruction, and a jump to the original
414 target is inserted between the two instructions. In PIC code the jump
415 will involve further instructions for address calculation.
417 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
418 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
419 relaxation, because they have no complementing counterparts. They could
420 be relaxed with the use of a longer sequence involving another branch,
421 however this has not been implemented and if their target turns out of
422 reach, they produce an error even if branch relaxation is enabled.
424 Also no MIPS16 branches are ever relaxed.
426 By default @samp{--no-relax-branch} is selected, causing any out-of-range
427 branches to produce an error.
429 @cindex @option{-mnan=} command line option, MIPS
430 @item -mnan=@var{encoding}
431 This option indicates whether the source code uses the IEEE 2008
432 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
433 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
434 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
436 @option{-mnan=legacy} is the default if no @option{-mnan} option or
437 @code{.nan} directive is used.
441 @c FIXME! (1) reflect these options (next item too) in option summaries;
442 @c (2) stop teasing, say _which_ instructions expanded _how_.
443 @code{@value{AS}} automatically macro expands certain division and
444 multiplication instructions to check for overflow and division by zero. This
445 option causes @code{@value{AS}} to generate code to take a trap exception
446 rather than a break exception when an error is detected. The trap instructions
447 are only supported at Instruction Set Architecture level 2 and higher.
451 Generate code to take a break exception rather than a trap exception when an
452 error is detected. This is the default.
456 Control generation of @code{.pdr} sections. Off by default on IRIX, on
461 When generating code using the Unix calling conventions (selected by
462 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
463 which can go into a shared library. The @samp{-mno-shared} option
464 tells gas to generate code which uses the calling convention, but can
465 not go into a shared library. The resulting code is slightly more
466 efficient. This option only affects the handling of the
467 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
471 @section High-level assembly macros
473 MIPS assemblers have traditionally provided a wider range of
474 instructions than the MIPS architecture itself. These extra
475 instructions are usually referred to as ``macro'' instructions
476 @footnote{The term ``macro'' is somewhat overloaded here, since
477 these macros have no relation to those defined by @code{.macro},
478 @pxref{Macro,, @code{.macro}}.}.
480 Some MIPS macro instructions extend an underlying architectural instruction
481 while others are entirely new. An example of the former type is @code{and},
482 which allows the third operand to be either a register or an arbitrary
483 immediate value. Examples of the latter type include @code{bgt}, which
484 branches to the third operand when the first operand is greater than
485 the second operand, and @code{ulh}, which implements an unaligned
488 One of the most common extensions provided by macros is to expand
489 memory offsets to the full address range (32 or 64 bits) and to allow
490 symbolic offsets such as @samp{my_data + 4} to be used in place of
491 integer constants. For example, the architectural instruction
492 @code{lbu} allows only a signed 16-bit offset, whereas the macro
493 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
494 The implementation of these symbolic offsets depends on several factors,
495 such as whether the assembler is generating SVR4-style PIC (selected by
496 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
497 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
498 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
499 of small data accesses}).
501 @kindex @code{.set macro}
502 @kindex @code{.set nomacro}
503 Sometimes it is undesirable to have one assembly instruction expand
504 to several machine instructions. The directive @code{.set nomacro}
505 tells the assembler to warn when this happens. @code{.set macro}
506 restores the default behavior.
508 @cindex @code{at} register, MIPS
509 @kindex @code{.set at=@var{reg}}
510 Some macro instructions need a temporary register to store intermediate
511 results. This register is usually @code{$1}, also known as @code{$at},
512 but it can be changed to any core register @var{reg} using
513 @code{.set at=@var{reg}}. Note that @code{$at} always refers
514 to @code{$1} regardless of which register is being used as the
517 @kindex @code{.set at}
518 @kindex @code{.set noat}
519 Implicit uses of the temporary register in macros could interfere with
520 explicit uses in the assembly code. The assembler therefore warns
521 whenever it sees an explicit use of the temporary register. The directive
522 @code{.set noat} silences this warning while @code{.set at} restores
523 the default behavior. It is safe to use @code{.set noat} while
524 @code{.set nomacro} is in effect since single-instruction macros
525 never need a temporary register.
527 Note that while the @sc{gnu} assembler provides these macros for compatibility,
528 it does not make any attempt to optimize them with the surrounding code.
530 @node MIPS Symbol Sizes
531 @section Directives to override the size of symbols
533 @kindex @code{.set sym32}
534 @kindex @code{.set nosym32}
535 The n64 ABI allows symbols to have any 64-bit value. Although this
536 provides a great deal of flexibility, it means that some macros have
537 much longer expansions than their 32-bit counterparts. For example,
538 the non-PIC expansion of @samp{dla $4,sym} is usually:
543 daddiu $4,$4,%higher(sym)
544 daddiu $1,$1,%lo(sym)
549 whereas the 32-bit expansion is simply:
553 daddiu $4,$4,%lo(sym)
556 n64 code is sometimes constructed in such a way that all symbolic
557 constants are known to have 32-bit values, and in such cases, it's
558 preferable to use the 32-bit expansion instead of the 64-bit
561 You can use the @code{.set sym32} directive to tell the assembler
562 that, from this point on, all expressions of the form
563 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
564 have 32-bit values. For example:
573 will cause the assembler to treat @samp{sym}, @code{sym+16} and
574 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
575 addresses is not affected.
577 The directive @code{.set nosym32} ends a @code{.set sym32} block and
578 reverts to the normal behavior. It is also possible to change the
579 symbol size using the command-line options @option{-msym32} and
582 These options and directives are always accepted, but at present,
583 they have no effect for anything other than n64.
585 @node MIPS Small Data
586 @section Controlling the use of small data accesses
588 @c This section deliberately glosses over the possibility of using -G
589 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
590 @cindex small data, MIPS
591 @cindex @code{gp} register, MIPS
592 It often takes several instructions to load the address of a symbol.
593 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
594 of @samp{dla $4,addr} is usually:
598 daddiu $4,$4,%lo(addr)
601 The sequence is much longer when @samp{addr} is a 64-bit symbol.
602 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
604 In order to cut down on this overhead, most embedded MIPS systems
605 set aside a 64-kilobyte ``small data'' area and guarantee that all
606 data of size @var{n} and smaller will be placed in that area.
607 The limit @var{n} is passed to both the assembler and the linker
608 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
609 Assembler options}. Note that the same value of @var{n} must be used
610 when linking and when assembling all input files to the link; any
611 inconsistency could cause a relocation overflow error.
613 The size of an object in the @code{.bss} section is set by the
614 @code{.comm} or @code{.lcomm} directive that defines it. The size of
615 an external object may be set with the @code{.extern} directive. For
616 example, @samp{.extern sym,4} declares that the object at @code{sym}
617 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
619 When no @option{-G} option is given, the default limit is 8 bytes.
620 The option @option{-G 0} prevents any data from being automatically
623 It is also possible to mark specific objects as small by putting them
624 in the special sections @code{.sdata} and @code{.sbss}, which are
625 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
626 The toolchain will treat such data as small regardless of the
629 On startup, systems that support a small data area are expected to
630 initialize register @code{$28}, also known as @code{$gp}, in such a
631 way that small data can be accessed using a 16-bit offset from that
632 register. For example, when @samp{addr} is small data,
633 the @samp{dla $4,addr} instruction above is equivalent to:
636 daddiu $4,$28,%gp_rel(addr)
639 Small data is not supported for SVR4-style PIC.
642 @section Directives to override the ISA level
644 @cindex MIPS ISA override
645 @kindex @code{.set mips@var{n}}
646 @sc{gnu} @code{@value{AS}} supports an additional directive to change
647 the MIPS Instruction Set Architecture level on the fly: @code{.set
648 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
650 The values other than 0 make the assembler accept instructions
651 for the corresponding ISA level, from that point on in the
652 assembly. @code{.set mips@var{n}} affects not only which instructions
653 are permitted, but also how certain macros are expanded. @code{.set
654 mips0} restores the ISA level to its original level: either the
655 level you selected with command line options, or the default for your
656 configuration. You can use this feature to permit specific MIPS III
657 instructions while assembling in 32 bit mode. Use this directive with
660 @cindex MIPS CPU override
661 @kindex @code{.set arch=@var{cpu}}
662 The @code{.set arch=@var{cpu}} directive provides even finer control.
663 It changes the effective CPU target and allows the assembler to use
664 instructions specific to a particular CPU. All CPUs supported by the
665 @samp{-march} command line option are also selectable by this directive.
666 The original value is restored by @code{.set arch=default}.
668 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
669 in which it will assemble instructions for the MIPS 16 processor. Use
670 @code{.set nomips16} to return to normal 32 bit mode.
672 Traditional MIPS assemblers do not support this directive.
674 The directive @code{.set micromips} puts the assembler into microMIPS mode,
675 in which it will assemble instructions for the microMIPS processor. Use
676 @code{.set nomicromips} to return to normal 32 bit mode.
678 Traditional MIPS assemblers do not support this directive.
680 @node MIPS assembly options
681 @section Directives to control code generation
683 @cindex MIPS 32-bit microMIPS instruction generation override
684 @kindex @code{.set insn32}
685 @kindex @code{.set noinsn32}
686 The directive @code{.set insn32} makes the assembler only use 32-bit
687 instruction encodings when generating code for the microMIPS processor.
688 This directive inhibits the use of any 16-bit instructions from that
689 point on in the assembly. The @code{.set noinsn32} directive allows
690 16-bit instructions to be accepted.
692 Traditional MIPS assemblers do not support this directive.
694 @node MIPS autoextend
695 @section Directives for extending MIPS 16 bit instructions
697 @kindex @code{.set autoextend}
698 @kindex @code{.set noautoextend}
699 By default, MIPS 16 instructions are automatically extended to 32 bits
700 when necessary. The directive @code{.set noautoextend} will turn this
701 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
702 must be explicitly extended with the @code{.e} modifier (e.g.,
703 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
704 to once again automatically extend instructions when necessary.
706 This directive is only meaningful when in MIPS 16 mode. Traditional
707 MIPS assemblers do not support this directive.
710 @section Directive to mark data as an instruction
713 The @code{.insn} directive tells @code{@value{AS}} that the following
714 data is actually instructions. This makes a difference in MIPS 16 and
715 microMIPS modes: when loading the address of a label which precedes
716 instructions, @code{@value{AS}} automatically adds 1 to the value, so
717 that jumping to the loaded address will do the right thing.
719 @kindex @code{.global}
720 The @code{.global} and @code{.globl} directives supported by
721 @code{@value{AS}} will by default mark the symbol as pointing to a
722 region of data not code. This means that, for example, any
723 instructions following such a symbol will not be disassembled by
724 @code{objdump} as it will regard them as data. To change this
725 behaviour an optional section name can be placed after the symbol name
726 in the @code{.global} directive. If this section exists and is known
727 to be a code section, then the symbol will be marked as poiting at
728 code not data. Ie the syntax for the directive is:
730 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
732 Here is a short example:
735 .global foo .text, bar, baz .data
745 @node MIPS NaN Encodings
746 @section Directives to record which NaN encoding is being used
748 @cindex MIPS IEEE 754 NaN data encoding selection
749 @cindex @code{.nan} directive, MIPS
750 The IEEE 754 floating-point standard defines two types of not-a-number
751 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
752 of the standard did not specify how these two types should be
753 distinguished. Most implementations followed the i387 model, in which
754 the first bit of the significand is set for quiet NaNs and clear for
755 signalling NaNs. However, the original MIPS implementation assigned the
756 opposite meaning to the bit, so that it was set for signalling NaNs and
757 clear for quiet NaNs.
759 The 2008 revision of the standard formally suggested the i387 choice
760 and as from Sep 2012 the current release of the MIPS architecture
761 therefore optionally supports that form. Code that uses one NaN encoding
762 would usually be incompatible with code that uses the other NaN encoding,
763 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
764 encoding is being used.
766 Assembly files can use the @code{.nan} directive to select between the
767 two encodings. @samp{.nan 2008} says that the assembly file uses the
768 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
769 the original MIPS encoding. If several @code{.nan} directives are given,
770 the final setting is the one that is used.
772 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
773 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
774 respectively. However, any @code{.nan} directive overrides the
775 command-line setting.
777 @samp{.nan legacy} is the default if no @code{.nan} directive or
778 @option{-mnan} option is given.
780 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
781 therefore these directives do not affect code generation. They simply
782 control the setting of the @code{EF_MIPS_NAN2008} flag.
784 Traditional MIPS assemblers do not support these directives.
786 @node MIPS Option Stack
787 @section Directives to save and restore options
789 @cindex MIPS option stack
790 @kindex @code{.set push}
791 @kindex @code{.set pop}
792 The directives @code{.set push} and @code{.set pop} may be used to save
793 and restore the current settings for all the options which are
794 controlled by @code{.set}. The @code{.set push} directive saves the
795 current settings on a stack. The @code{.set pop} directive pops the
796 stack and restores the settings.
798 These directives can be useful inside an macro which must change an
799 option such as the ISA level or instruction reordering but does not want
800 to change the state of the code which invoked the macro.
802 Traditional MIPS assemblers do not support these directives.
804 @node MIPS ASE Instruction Generation Overrides
805 @section Directives to control generation of MIPS ASE instructions
807 @cindex MIPS MIPS-3D instruction generation override
808 @kindex @code{.set mips3d}
809 @kindex @code{.set nomips3d}
810 The directive @code{.set mips3d} makes the assembler accept instructions
811 from the MIPS-3D Application Specific Extension from that point on
812 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
813 instructions from being accepted.
815 @cindex SmartMIPS instruction generation override
816 @kindex @code{.set smartmips}
817 @kindex @code{.set nosmartmips}
818 The directive @code{.set smartmips} makes the assembler accept
819 instructions from the SmartMIPS Application Specific Extension to the
820 MIPS32 ISA from that point on in the assembly. The
821 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
824 @cindex MIPS MDMX instruction generation override
825 @kindex @code{.set mdmx}
826 @kindex @code{.set nomdmx}
827 The directive @code{.set mdmx} makes the assembler accept instructions
828 from the MDMX Application Specific Extension from that point on
829 in the assembly. The @code{.set nomdmx} directive prevents MDMX
830 instructions from being accepted.
832 @cindex MIPS DSP Release 1 instruction generation override
833 @kindex @code{.set dsp}
834 @kindex @code{.set nodsp}
835 The directive @code{.set dsp} makes the assembler accept instructions
836 from the DSP Release 1 Application Specific Extension from that point
837 on in the assembly. The @code{.set nodsp} directive prevents DSP
838 Release 1 instructions from being accepted.
840 @cindex MIPS DSP Release 2 instruction generation override
841 @kindex @code{.set dspr2}
842 @kindex @code{.set nodspr2}
843 The directive @code{.set dspr2} makes the assembler accept instructions
844 from the DSP Release 2 Application Specific Extension from that point
845 on in the assembly. This dirctive implies @code{.set dsp}. The
846 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
849 @cindex MIPS MT instruction generation override
850 @kindex @code{.set mt}
851 @kindex @code{.set nomt}
852 The directive @code{.set mt} makes the assembler accept instructions
853 from the MT Application Specific Extension from that point on
854 in the assembly. The @code{.set nomt} directive prevents MT
855 instructions from being accepted.
857 @cindex MIPS MCU instruction generation override
858 @kindex @code{.set mcu}
859 @kindex @code{.set nomcu}
860 The directive @code{.set mcu} makes the assembler accept instructions
861 from the MCU Application Specific Extension from that point on
862 in the assembly. The @code{.set nomcu} directive prevents MCU
863 instructions from being accepted.
865 @cindex MIPS SIMD Architecture instruction generation override
866 @kindex @code{.set msa}
867 @kindex @code{.set nomsa}
868 The directive @code{.set msa} makes the assembler accept instructions
869 from the MIPS SIMD Architecture Extension from that point on
870 in the assembly. The @code{.set nomsa} directive prevents MSA
871 instructions from being accepted.
873 @cindex Virtualization instruction generation override
874 @kindex @code{.set virt}
875 @kindex @code{.set novirt}
876 The directive @code{.set virt} makes the assembler accept instructions
877 from the Virtualization Application Specific Extension from that point
878 on in the assembly. The @code{.set novirt} directive prevents Virtualization
879 instructions from being accepted.
881 Traditional MIPS assemblers do not support these directives.
883 @node MIPS Floating-Point
884 @section Directives to override floating-point options
886 @cindex Disable floating-point instructions
887 @kindex @code{.set softfloat}
888 @kindex @code{.set hardfloat}
889 The directives @code{.set softfloat} and @code{.set hardfloat} provide
890 finer control of disabling and enabling float-point instructions.
891 These directives always override the default (that hard-float
892 instructions are accepted) or the command-line options
893 (@samp{-msoft-float} and @samp{-mhard-float}).
895 @cindex Disable single-precision floating-point operations
896 @kindex @code{.set singlefloat}
897 @kindex @code{.set doublefloat}
898 The directives @code{.set singlefloat} and @code{.set doublefloat}
899 provide finer control of disabling and enabling double-precision
900 float-point operations. These directives always override the default
901 (that double-precision operations are accepted) or the command-line
902 options (@samp{-msingle-float} and @samp{-mdouble-float}).
904 Traditional MIPS assemblers do not support these directives.
907 @section Syntactical considerations for the MIPS assembler
909 * MIPS-Chars:: Special Characters
913 @subsection Special Characters
915 @cindex line comment character, MIPS
916 @cindex MIPS line comment character
917 The presence of a @samp{#} on a line indicates the start of a comment
918 that extends to the end of the current line.
920 If a @samp{#} appears as the first character of a line, the whole line
921 is treated as a comment, but in this case the line can also be a
922 logical line number directive (@pxref{Comments}) or a
923 preprocessor control command (@pxref{Preprocessing}).
925 @cindex line separator, MIPS
926 @cindex statement separator, MIPS
927 @cindex MIPS line separator
928 The @samp{;} character can be used to separate statements on the same
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